CCSModuleSW30Web.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001e8 08008000 08008000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000e7a8 080081e8 080081e8 000011e8 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000c64 08016990 08016990 0000f990 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 080175f4 080175f4 00011258 2**0 CONTENTS 4 .ARM 00000008 080175f4 080175f4 000105f4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 080175fc 080175fc 00011258 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 080175fc 080175fc 000105fc 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08017600 08017600 00010600 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000258 20000000 08017604 00011000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00001168 20000258 0801785c 00011258 2**3 ALLOC 10 ._user_heap_stack 00000600 200013c0 0801785c 000113c0 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 00011258 2**0 CONTENTS, READONLY 12 .debug_info 0001d4db 00000000 00000000 00011281 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 000057a8 00000000 00000000 0002e75c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_loclists 00000f2c 00000000 00000000 00033f04 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_aranges 00001708 00000000 00000000 00034e30 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_rnglists 00001215 00000000 00000000 00036538 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_macro 0002652a 00000000 00000000 0003774d 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_line 00021501 00000000 00000000 0005dc77 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_str 000c99d1 00000000 00000000 0007f178 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .comment 00000043 00000000 00000000 00148b49 2**0 CONTENTS, READONLY 21 .debug_frame 00006d8c 00000000 00000000 00148b8c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 22 .debug_line_str 00000073 00000000 00000000 0014f918 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080081e8 <__do_global_dtors_aux>: 80081e8: b510 push {r4, lr} 80081ea: 4c05 ldr r4, [pc, #20] @ (8008200 <__do_global_dtors_aux+0x18>) 80081ec: 7823 ldrb r3, [r4, #0] 80081ee: b933 cbnz r3, 80081fe <__do_global_dtors_aux+0x16> 80081f0: 4b04 ldr r3, [pc, #16] @ (8008204 <__do_global_dtors_aux+0x1c>) 80081f2: b113 cbz r3, 80081fa <__do_global_dtors_aux+0x12> 80081f4: 4804 ldr r0, [pc, #16] @ (8008208 <__do_global_dtors_aux+0x20>) 80081f6: f3af 8000 nop.w 80081fa: 2301 movs r3, #1 80081fc: 7023 strb r3, [r4, #0] 80081fe: bd10 pop {r4, pc} 8008200: 20000258 .word 0x20000258 8008204: 00000000 .word 0x00000000 8008208: 08016978 .word 0x08016978 0800820c : 800820c: b508 push {r3, lr} 800820e: 4b03 ldr r3, [pc, #12] @ (800821c ) 8008210: b11b cbz r3, 800821a 8008212: 4903 ldr r1, [pc, #12] @ (8008220 ) 8008214: 4803 ldr r0, [pc, #12] @ (8008224 ) 8008216: f3af 8000 nop.w 800821a: bd08 pop {r3, pc} 800821c: 00000000 .word 0x00000000 8008220: 2000025c .word 0x2000025c 8008224: 08016978 .word 0x08016978 08008228 : 8008228: 4603 mov r3, r0 800822a: f813 2b01 ldrb.w r2, [r3], #1 800822e: 2a00 cmp r2, #0 8008230: d1fb bne.n 800822a 8008232: 1a18 subs r0, r3, r0 8008234: 3801 subs r0, #1 8008236: 4770 bx lr 08008238 <__aeabi_drsub>: 8008238: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 800823c: e002 b.n 8008244 <__adddf3> 800823e: bf00 nop 08008240 <__aeabi_dsub>: 8008240: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 08008244 <__adddf3>: 8008244: b530 push {r4, r5, lr} 8008246: ea4f 0441 mov.w r4, r1, lsl #1 800824a: ea4f 0543 mov.w r5, r3, lsl #1 800824e: ea94 0f05 teq r4, r5 8008252: bf08 it eq 8008254: ea90 0f02 teqeq r0, r2 8008258: bf1f itttt ne 800825a: ea54 0c00 orrsne.w ip, r4, r0 800825e: ea55 0c02 orrsne.w ip, r5, r2 8008262: ea7f 5c64 mvnsne.w ip, r4, asr #21 8008266: ea7f 5c65 mvnsne.w ip, r5, asr #21 800826a: f000 80e2 beq.w 8008432 <__adddf3+0x1ee> 800826e: ea4f 5454 mov.w r4, r4, lsr #21 8008272: ebd4 5555 rsbs r5, r4, r5, lsr #21 8008276: bfb8 it lt 8008278: 426d neglt r5, r5 800827a: dd0c ble.n 8008296 <__adddf3+0x52> 800827c: 442c add r4, r5 800827e: ea80 0202 eor.w r2, r0, r2 8008282: ea81 0303 eor.w r3, r1, r3 8008286: ea82 0000 eor.w r0, r2, r0 800828a: ea83 0101 eor.w r1, r3, r1 800828e: ea80 0202 eor.w r2, r0, r2 8008292: ea81 0303 eor.w r3, r1, r3 8008296: 2d36 cmp r5, #54 @ 0x36 8008298: bf88 it hi 800829a: bd30 pophi {r4, r5, pc} 800829c: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 80082a0: ea4f 3101 mov.w r1, r1, lsl #12 80082a4: f44f 1c80 mov.w ip, #1048576 @ 0x100000 80082a8: ea4c 3111 orr.w r1, ip, r1, lsr #12 80082ac: d002 beq.n 80082b4 <__adddf3+0x70> 80082ae: 4240 negs r0, r0 80082b0: eb61 0141 sbc.w r1, r1, r1, lsl #1 80082b4: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 80082b8: ea4f 3303 mov.w r3, r3, lsl #12 80082bc: ea4c 3313 orr.w r3, ip, r3, lsr #12 80082c0: d002 beq.n 80082c8 <__adddf3+0x84> 80082c2: 4252 negs r2, r2 80082c4: eb63 0343 sbc.w r3, r3, r3, lsl #1 80082c8: ea94 0f05 teq r4, r5 80082cc: f000 80a7 beq.w 800841e <__adddf3+0x1da> 80082d0: f1a4 0401 sub.w r4, r4, #1 80082d4: f1d5 0e20 rsbs lr, r5, #32 80082d8: db0d blt.n 80082f6 <__adddf3+0xb2> 80082da: fa02 fc0e lsl.w ip, r2, lr 80082de: fa22 f205 lsr.w r2, r2, r5 80082e2: 1880 adds r0, r0, r2 80082e4: f141 0100 adc.w r1, r1, #0 80082e8: fa03 f20e lsl.w r2, r3, lr 80082ec: 1880 adds r0, r0, r2 80082ee: fa43 f305 asr.w r3, r3, r5 80082f2: 4159 adcs r1, r3 80082f4: e00e b.n 8008314 <__adddf3+0xd0> 80082f6: f1a5 0520 sub.w r5, r5, #32 80082fa: f10e 0e20 add.w lr, lr, #32 80082fe: 2a01 cmp r2, #1 8008300: fa03 fc0e lsl.w ip, r3, lr 8008304: bf28 it cs 8008306: f04c 0c02 orrcs.w ip, ip, #2 800830a: fa43 f305 asr.w r3, r3, r5 800830e: 18c0 adds r0, r0, r3 8008310: eb51 71e3 adcs.w r1, r1, r3, asr #31 8008314: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008318: d507 bpl.n 800832a <__adddf3+0xe6> 800831a: f04f 0e00 mov.w lr, #0 800831e: f1dc 0c00 rsbs ip, ip, #0 8008322: eb7e 0000 sbcs.w r0, lr, r0 8008326: eb6e 0101 sbc.w r1, lr, r1 800832a: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 800832e: d31b bcc.n 8008368 <__adddf3+0x124> 8008330: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 8008334: d30c bcc.n 8008350 <__adddf3+0x10c> 8008336: 0849 lsrs r1, r1, #1 8008338: ea5f 0030 movs.w r0, r0, rrx 800833c: ea4f 0c3c mov.w ip, ip, rrx 8008340: f104 0401 add.w r4, r4, #1 8008344: ea4f 5244 mov.w r2, r4, lsl #21 8008348: f512 0f80 cmn.w r2, #4194304 @ 0x400000 800834c: f080 809a bcs.w 8008484 <__adddf3+0x240> 8008350: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008354: bf08 it eq 8008356: ea5f 0c50 movseq.w ip, r0, lsr #1 800835a: f150 0000 adcs.w r0, r0, #0 800835e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008362: ea41 0105 orr.w r1, r1, r5 8008366: bd30 pop {r4, r5, pc} 8008368: ea5f 0c4c movs.w ip, ip, lsl #1 800836c: 4140 adcs r0, r0 800836e: eb41 0101 adc.w r1, r1, r1 8008372: 3c01 subs r4, #1 8008374: bf28 it cs 8008376: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 800837a: d2e9 bcs.n 8008350 <__adddf3+0x10c> 800837c: f091 0f00 teq r1, #0 8008380: bf04 itt eq 8008382: 4601 moveq r1, r0 8008384: 2000 moveq r0, #0 8008386: fab1 f381 clz r3, r1 800838a: bf08 it eq 800838c: 3320 addeq r3, #32 800838e: f1a3 030b sub.w r3, r3, #11 8008392: f1b3 0220 subs.w r2, r3, #32 8008396: da0c bge.n 80083b2 <__adddf3+0x16e> 8008398: 320c adds r2, #12 800839a: dd08 ble.n 80083ae <__adddf3+0x16a> 800839c: f102 0c14 add.w ip, r2, #20 80083a0: f1c2 020c rsb r2, r2, #12 80083a4: fa01 f00c lsl.w r0, r1, ip 80083a8: fa21 f102 lsr.w r1, r1, r2 80083ac: e00c b.n 80083c8 <__adddf3+0x184> 80083ae: f102 0214 add.w r2, r2, #20 80083b2: bfd8 it le 80083b4: f1c2 0c20 rsble ip, r2, #32 80083b8: fa01 f102 lsl.w r1, r1, r2 80083bc: fa20 fc0c lsr.w ip, r0, ip 80083c0: bfdc itt le 80083c2: ea41 010c orrle.w r1, r1, ip 80083c6: 4090 lslle r0, r2 80083c8: 1ae4 subs r4, r4, r3 80083ca: bfa2 ittt ge 80083cc: eb01 5104 addge.w r1, r1, r4, lsl #20 80083d0: 4329 orrge r1, r5 80083d2: bd30 popge {r4, r5, pc} 80083d4: ea6f 0404 mvn.w r4, r4 80083d8: 3c1f subs r4, #31 80083da: da1c bge.n 8008416 <__adddf3+0x1d2> 80083dc: 340c adds r4, #12 80083de: dc0e bgt.n 80083fe <__adddf3+0x1ba> 80083e0: f104 0414 add.w r4, r4, #20 80083e4: f1c4 0220 rsb r2, r4, #32 80083e8: fa20 f004 lsr.w r0, r0, r4 80083ec: fa01 f302 lsl.w r3, r1, r2 80083f0: ea40 0003 orr.w r0, r0, r3 80083f4: fa21 f304 lsr.w r3, r1, r4 80083f8: ea45 0103 orr.w r1, r5, r3 80083fc: bd30 pop {r4, r5, pc} 80083fe: f1c4 040c rsb r4, r4, #12 8008402: f1c4 0220 rsb r2, r4, #32 8008406: fa20 f002 lsr.w r0, r0, r2 800840a: fa01 f304 lsl.w r3, r1, r4 800840e: ea40 0003 orr.w r0, r0, r3 8008412: 4629 mov r1, r5 8008414: bd30 pop {r4, r5, pc} 8008416: fa21 f004 lsr.w r0, r1, r4 800841a: 4629 mov r1, r5 800841c: bd30 pop {r4, r5, pc} 800841e: f094 0f00 teq r4, #0 8008422: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 8008426: bf06 itte eq 8008428: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 800842c: 3401 addeq r4, #1 800842e: 3d01 subne r5, #1 8008430: e74e b.n 80082d0 <__adddf3+0x8c> 8008432: ea7f 5c64 mvns.w ip, r4, asr #21 8008436: bf18 it ne 8008438: ea7f 5c65 mvnsne.w ip, r5, asr #21 800843c: d029 beq.n 8008492 <__adddf3+0x24e> 800843e: ea94 0f05 teq r4, r5 8008442: bf08 it eq 8008444: ea90 0f02 teqeq r0, r2 8008448: d005 beq.n 8008456 <__adddf3+0x212> 800844a: ea54 0c00 orrs.w ip, r4, r0 800844e: bf04 itt eq 8008450: 4619 moveq r1, r3 8008452: 4610 moveq r0, r2 8008454: bd30 pop {r4, r5, pc} 8008456: ea91 0f03 teq r1, r3 800845a: bf1e ittt ne 800845c: 2100 movne r1, #0 800845e: 2000 movne r0, #0 8008460: bd30 popne {r4, r5, pc} 8008462: ea5f 5c54 movs.w ip, r4, lsr #21 8008466: d105 bne.n 8008474 <__adddf3+0x230> 8008468: 0040 lsls r0, r0, #1 800846a: 4149 adcs r1, r1 800846c: bf28 it cs 800846e: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 8008472: bd30 pop {r4, r5, pc} 8008474: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 8008478: bf3c itt cc 800847a: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 800847e: bd30 popcc {r4, r5, pc} 8008480: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008484: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 8008488: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 800848c: f04f 0000 mov.w r0, #0 8008490: bd30 pop {r4, r5, pc} 8008492: ea7f 5c64 mvns.w ip, r4, asr #21 8008496: bf1a itte ne 8008498: 4619 movne r1, r3 800849a: 4610 movne r0, r2 800849c: ea7f 5c65 mvnseq.w ip, r5, asr #21 80084a0: bf1c itt ne 80084a2: 460b movne r3, r1 80084a4: 4602 movne r2, r0 80084a6: ea50 3401 orrs.w r4, r0, r1, lsl #12 80084aa: bf06 itte eq 80084ac: ea52 3503 orrseq.w r5, r2, r3, lsl #12 80084b0: ea91 0f03 teqeq r1, r3 80084b4: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 80084b8: bd30 pop {r4, r5, pc} 80084ba: bf00 nop 080084bc <__aeabi_ui2d>: 80084bc: f090 0f00 teq r0, #0 80084c0: bf04 itt eq 80084c2: 2100 moveq r1, #0 80084c4: 4770 bxeq lr 80084c6: b530 push {r4, r5, lr} 80084c8: f44f 6480 mov.w r4, #1024 @ 0x400 80084cc: f104 0432 add.w r4, r4, #50 @ 0x32 80084d0: f04f 0500 mov.w r5, #0 80084d4: f04f 0100 mov.w r1, #0 80084d8: e750 b.n 800837c <__adddf3+0x138> 80084da: bf00 nop 080084dc <__aeabi_i2d>: 80084dc: f090 0f00 teq r0, #0 80084e0: bf04 itt eq 80084e2: 2100 moveq r1, #0 80084e4: 4770 bxeq lr 80084e6: b530 push {r4, r5, lr} 80084e8: f44f 6480 mov.w r4, #1024 @ 0x400 80084ec: f104 0432 add.w r4, r4, #50 @ 0x32 80084f0: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 80084f4: bf48 it mi 80084f6: 4240 negmi r0, r0 80084f8: f04f 0100 mov.w r1, #0 80084fc: e73e b.n 800837c <__adddf3+0x138> 80084fe: bf00 nop 08008500 <__aeabi_f2d>: 8008500: 0042 lsls r2, r0, #1 8008502: ea4f 01e2 mov.w r1, r2, asr #3 8008506: ea4f 0131 mov.w r1, r1, rrx 800850a: ea4f 7002 mov.w r0, r2, lsl #28 800850e: bf1f itttt ne 8008510: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 8008514: f093 4f7f teqne r3, #4278190080 @ 0xff000000 8008518: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 800851c: 4770 bxne lr 800851e: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 8008522: bf08 it eq 8008524: 4770 bxeq lr 8008526: f093 4f7f teq r3, #4278190080 @ 0xff000000 800852a: bf04 itt eq 800852c: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 8008530: 4770 bxeq lr 8008532: b530 push {r4, r5, lr} 8008534: f44f 7460 mov.w r4, #896 @ 0x380 8008538: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 800853c: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 8008540: e71c b.n 800837c <__adddf3+0x138> 8008542: bf00 nop 08008544 <__aeabi_ul2d>: 8008544: ea50 0201 orrs.w r2, r0, r1 8008548: bf08 it eq 800854a: 4770 bxeq lr 800854c: b530 push {r4, r5, lr} 800854e: f04f 0500 mov.w r5, #0 8008552: e00a b.n 800856a <__aeabi_l2d+0x16> 08008554 <__aeabi_l2d>: 8008554: ea50 0201 orrs.w r2, r0, r1 8008558: bf08 it eq 800855a: 4770 bxeq lr 800855c: b530 push {r4, r5, lr} 800855e: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 8008562: d502 bpl.n 800856a <__aeabi_l2d+0x16> 8008564: 4240 negs r0, r0 8008566: eb61 0141 sbc.w r1, r1, r1, lsl #1 800856a: f44f 6480 mov.w r4, #1024 @ 0x400 800856e: f104 0432 add.w r4, r4, #50 @ 0x32 8008572: ea5f 5c91 movs.w ip, r1, lsr #22 8008576: f43f aed8 beq.w 800832a <__adddf3+0xe6> 800857a: f04f 0203 mov.w r2, #3 800857e: ea5f 0cdc movs.w ip, ip, lsr #3 8008582: bf18 it ne 8008584: 3203 addne r2, #3 8008586: ea5f 0cdc movs.w ip, ip, lsr #3 800858a: bf18 it ne 800858c: 3203 addne r2, #3 800858e: eb02 02dc add.w r2, r2, ip, lsr #3 8008592: f1c2 0320 rsb r3, r2, #32 8008596: fa00 fc03 lsl.w ip, r0, r3 800859a: fa20 f002 lsr.w r0, r0, r2 800859e: fa01 fe03 lsl.w lr, r1, r3 80085a2: ea40 000e orr.w r0, r0, lr 80085a6: fa21 f102 lsr.w r1, r1, r2 80085aa: 4414 add r4, r2 80085ac: e6bd b.n 800832a <__adddf3+0xe6> 80085ae: bf00 nop 080085b0 <__aeabi_dmul>: 80085b0: b570 push {r4, r5, r6, lr} 80085b2: f04f 0cff mov.w ip, #255 @ 0xff 80085b6: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 80085ba: ea1c 5411 ands.w r4, ip, r1, lsr #20 80085be: bf1d ittte ne 80085c0: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80085c4: ea94 0f0c teqne r4, ip 80085c8: ea95 0f0c teqne r5, ip 80085cc: f000 f8de bleq 800878c <__aeabi_dmul+0x1dc> 80085d0: 442c add r4, r5 80085d2: ea81 0603 eor.w r6, r1, r3 80085d6: ea21 514c bic.w r1, r1, ip, lsl #21 80085da: ea23 534c bic.w r3, r3, ip, lsl #21 80085de: ea50 3501 orrs.w r5, r0, r1, lsl #12 80085e2: bf18 it ne 80085e4: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80085e8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 80085ec: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80085f0: d038 beq.n 8008664 <__aeabi_dmul+0xb4> 80085f2: fba0 ce02 umull ip, lr, r0, r2 80085f6: f04f 0500 mov.w r5, #0 80085fa: fbe1 e502 umlal lr, r5, r1, r2 80085fe: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000 8008602: fbe0 e503 umlal lr, r5, r0, r3 8008606: f04f 0600 mov.w r6, #0 800860a: fbe1 5603 umlal r5, r6, r1, r3 800860e: f09c 0f00 teq ip, #0 8008612: bf18 it ne 8008614: f04e 0e01 orrne.w lr, lr, #1 8008618: f1a4 04ff sub.w r4, r4, #255 @ 0xff 800861c: f5b6 7f00 cmp.w r6, #512 @ 0x200 8008620: f564 7440 sbc.w r4, r4, #768 @ 0x300 8008624: d204 bcs.n 8008630 <__aeabi_dmul+0x80> 8008626: ea5f 0e4e movs.w lr, lr, lsl #1 800862a: 416d adcs r5, r5 800862c: eb46 0606 adc.w r6, r6, r6 8008630: ea42 21c6 orr.w r1, r2, r6, lsl #11 8008634: ea41 5155 orr.w r1, r1, r5, lsr #21 8008638: ea4f 20c5 mov.w r0, r5, lsl #11 800863c: ea40 505e orr.w r0, r0, lr, lsr #21 8008640: ea4f 2ece mov.w lr, lr, lsl #11 8008644: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008648: bf88 it hi 800864a: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800864e: d81e bhi.n 800868e <__aeabi_dmul+0xde> 8008650: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000 8008654: bf08 it eq 8008656: ea5f 0e50 movseq.w lr, r0, lsr #1 800865a: f150 0000 adcs.w r0, r0, #0 800865e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008662: bd70 pop {r4, r5, r6, pc} 8008664: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000 8008668: ea46 0101 orr.w r1, r6, r1 800866c: ea40 0002 orr.w r0, r0, r2 8008670: ea81 0103 eor.w r1, r1, r3 8008674: ebb4 045c subs.w r4, r4, ip, lsr #1 8008678: bfc2 ittt gt 800867a: ebd4 050c rsbsgt r5, r4, ip 800867e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8008682: bd70 popgt {r4, r5, r6, pc} 8008684: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008688: f04f 0e00 mov.w lr, #0 800868c: 3c01 subs r4, #1 800868e: f300 80ab bgt.w 80087e8 <__aeabi_dmul+0x238> 8008692: f114 0f36 cmn.w r4, #54 @ 0x36 8008696: bfde ittt le 8008698: 2000 movle r0, #0 800869a: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000 800869e: bd70 pople {r4, r5, r6, pc} 80086a0: f1c4 0400 rsb r4, r4, #0 80086a4: 3c20 subs r4, #32 80086a6: da35 bge.n 8008714 <__aeabi_dmul+0x164> 80086a8: 340c adds r4, #12 80086aa: dc1b bgt.n 80086e4 <__aeabi_dmul+0x134> 80086ac: f104 0414 add.w r4, r4, #20 80086b0: f1c4 0520 rsb r5, r4, #32 80086b4: fa00 f305 lsl.w r3, r0, r5 80086b8: fa20 f004 lsr.w r0, r0, r4 80086bc: fa01 f205 lsl.w r2, r1, r5 80086c0: ea40 0002 orr.w r0, r0, r2 80086c4: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000 80086c8: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 80086cc: eb10 70d3 adds.w r0, r0, r3, lsr #31 80086d0: fa21 f604 lsr.w r6, r1, r4 80086d4: eb42 0106 adc.w r1, r2, r6 80086d8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80086dc: bf08 it eq 80086de: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80086e2: bd70 pop {r4, r5, r6, pc} 80086e4: f1c4 040c rsb r4, r4, #12 80086e8: f1c4 0520 rsb r5, r4, #32 80086ec: fa00 f304 lsl.w r3, r0, r4 80086f0: fa20 f005 lsr.w r0, r0, r5 80086f4: fa01 f204 lsl.w r2, r1, r4 80086f8: ea40 0002 orr.w r0, r0, r2 80086fc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8008700: eb10 70d3 adds.w r0, r0, r3, lsr #31 8008704: f141 0100 adc.w r1, r1, #0 8008708: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 800870c: bf08 it eq 800870e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8008712: bd70 pop {r4, r5, r6, pc} 8008714: f1c4 0520 rsb r5, r4, #32 8008718: fa00 f205 lsl.w r2, r0, r5 800871c: ea4e 0e02 orr.w lr, lr, r2 8008720: fa20 f304 lsr.w r3, r0, r4 8008724: fa01 f205 lsl.w r2, r1, r5 8008728: ea43 0302 orr.w r3, r3, r2 800872c: fa21 f004 lsr.w r0, r1, r4 8008730: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8008734: fa21 f204 lsr.w r2, r1, r4 8008738: ea20 0002 bic.w r0, r0, r2 800873c: eb00 70d3 add.w r0, r0, r3, lsr #31 8008740: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8008744: bf08 it eq 8008746: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800874a: bd70 pop {r4, r5, r6, pc} 800874c: f094 0f00 teq r4, #0 8008750: d10f bne.n 8008772 <__aeabi_dmul+0x1c2> 8008752: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000 8008756: 0040 lsls r0, r0, #1 8008758: eb41 0101 adc.w r1, r1, r1 800875c: f411 1f80 tst.w r1, #1048576 @ 0x100000 8008760: bf08 it eq 8008762: 3c01 subeq r4, #1 8008764: d0f7 beq.n 8008756 <__aeabi_dmul+0x1a6> 8008766: ea41 0106 orr.w r1, r1, r6 800876a: f095 0f00 teq r5, #0 800876e: bf18 it ne 8008770: 4770 bxne lr 8008772: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000 8008776: 0052 lsls r2, r2, #1 8008778: eb43 0303 adc.w r3, r3, r3 800877c: f413 1f80 tst.w r3, #1048576 @ 0x100000 8008780: bf08 it eq 8008782: 3d01 subeq r5, #1 8008784: d0f7 beq.n 8008776 <__aeabi_dmul+0x1c6> 8008786: ea43 0306 orr.w r3, r3, r6 800878a: 4770 bx lr 800878c: ea94 0f0c teq r4, ip 8008790: ea0c 5513 and.w r5, ip, r3, lsr #20 8008794: bf18 it ne 8008796: ea95 0f0c teqne r5, ip 800879a: d00c beq.n 80087b6 <__aeabi_dmul+0x206> 800879c: ea50 0641 orrs.w r6, r0, r1, lsl #1 80087a0: bf18 it ne 80087a2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80087a6: d1d1 bne.n 800874c <__aeabi_dmul+0x19c> 80087a8: ea81 0103 eor.w r1, r1, r3 80087ac: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087b0: f04f 0000 mov.w r0, #0 80087b4: bd70 pop {r4, r5, r6, pc} 80087b6: ea50 0641 orrs.w r6, r0, r1, lsl #1 80087ba: bf06 itte eq 80087bc: 4610 moveq r0, r2 80087be: 4619 moveq r1, r3 80087c0: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80087c4: d019 beq.n 80087fa <__aeabi_dmul+0x24a> 80087c6: ea94 0f0c teq r4, ip 80087ca: d102 bne.n 80087d2 <__aeabi_dmul+0x222> 80087cc: ea50 3601 orrs.w r6, r0, r1, lsl #12 80087d0: d113 bne.n 80087fa <__aeabi_dmul+0x24a> 80087d2: ea95 0f0c teq r5, ip 80087d6: d105 bne.n 80087e4 <__aeabi_dmul+0x234> 80087d8: ea52 3603 orrs.w r6, r2, r3, lsl #12 80087dc: bf1c itt ne 80087de: 4610 movne r0, r2 80087e0: 4619 movne r1, r3 80087e2: d10a bne.n 80087fa <__aeabi_dmul+0x24a> 80087e4: ea81 0103 eor.w r1, r1, r3 80087e8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087ec: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087f0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 80087f4: f04f 0000 mov.w r0, #0 80087f8: bd70 pop {r4, r5, r6, pc} 80087fa: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087fe: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000 8008802: bd70 pop {r4, r5, r6, pc} 08008804 <__aeabi_ddiv>: 8008804: b570 push {r4, r5, r6, lr} 8008806: f04f 0cff mov.w ip, #255 @ 0xff 800880a: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 800880e: ea1c 5411 ands.w r4, ip, r1, lsr #20 8008812: bf1d ittte ne 8008814: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8008818: ea94 0f0c teqne r4, ip 800881c: ea95 0f0c teqne r5, ip 8008820: f000 f8a7 bleq 8008972 <__aeabi_ddiv+0x16e> 8008824: eba4 0405 sub.w r4, r4, r5 8008828: ea81 0e03 eor.w lr, r1, r3 800882c: ea52 3503 orrs.w r5, r2, r3, lsl #12 8008830: ea4f 3101 mov.w r1, r1, lsl #12 8008834: f000 8088 beq.w 8008948 <__aeabi_ddiv+0x144> 8008838: ea4f 3303 mov.w r3, r3, lsl #12 800883c: f04f 5580 mov.w r5, #268435456 @ 0x10000000 8008840: ea45 1313 orr.w r3, r5, r3, lsr #4 8008844: ea43 6312 orr.w r3, r3, r2, lsr #24 8008848: ea4f 2202 mov.w r2, r2, lsl #8 800884c: ea45 1511 orr.w r5, r5, r1, lsr #4 8008850: ea45 6510 orr.w r5, r5, r0, lsr #24 8008854: ea4f 2600 mov.w r6, r0, lsl #8 8008858: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000 800885c: 429d cmp r5, r3 800885e: bf08 it eq 8008860: 4296 cmpeq r6, r2 8008862: f144 04fd adc.w r4, r4, #253 @ 0xfd 8008866: f504 7440 add.w r4, r4, #768 @ 0x300 800886a: d202 bcs.n 8008872 <__aeabi_ddiv+0x6e> 800886c: 085b lsrs r3, r3, #1 800886e: ea4f 0232 mov.w r2, r2, rrx 8008872: 1ab6 subs r6, r6, r2 8008874: eb65 0503 sbc.w r5, r5, r3 8008878: 085b lsrs r3, r3, #1 800887a: ea4f 0232 mov.w r2, r2, rrx 800887e: f44f 1080 mov.w r0, #1048576 @ 0x100000 8008882: f44f 2c00 mov.w ip, #524288 @ 0x80000 8008886: ebb6 0e02 subs.w lr, r6, r2 800888a: eb75 0e03 sbcs.w lr, r5, r3 800888e: bf22 ittt cs 8008890: 1ab6 subcs r6, r6, r2 8008892: 4675 movcs r5, lr 8008894: ea40 000c orrcs.w r0, r0, ip 8008898: 085b lsrs r3, r3, #1 800889a: ea4f 0232 mov.w r2, r2, rrx 800889e: ebb6 0e02 subs.w lr, r6, r2 80088a2: eb75 0e03 sbcs.w lr, r5, r3 80088a6: bf22 ittt cs 80088a8: 1ab6 subcs r6, r6, r2 80088aa: 4675 movcs r5, lr 80088ac: ea40 005c orrcs.w r0, r0, ip, lsr #1 80088b0: 085b lsrs r3, r3, #1 80088b2: ea4f 0232 mov.w r2, r2, rrx 80088b6: ebb6 0e02 subs.w lr, r6, r2 80088ba: eb75 0e03 sbcs.w lr, r5, r3 80088be: bf22 ittt cs 80088c0: 1ab6 subcs r6, r6, r2 80088c2: 4675 movcs r5, lr 80088c4: ea40 009c orrcs.w r0, r0, ip, lsr #2 80088c8: 085b lsrs r3, r3, #1 80088ca: ea4f 0232 mov.w r2, r2, rrx 80088ce: ebb6 0e02 subs.w lr, r6, r2 80088d2: eb75 0e03 sbcs.w lr, r5, r3 80088d6: bf22 ittt cs 80088d8: 1ab6 subcs r6, r6, r2 80088da: 4675 movcs r5, lr 80088dc: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80088e0: ea55 0e06 orrs.w lr, r5, r6 80088e4: d018 beq.n 8008918 <__aeabi_ddiv+0x114> 80088e6: ea4f 1505 mov.w r5, r5, lsl #4 80088ea: ea45 7516 orr.w r5, r5, r6, lsr #28 80088ee: ea4f 1606 mov.w r6, r6, lsl #4 80088f2: ea4f 03c3 mov.w r3, r3, lsl #3 80088f6: ea43 7352 orr.w r3, r3, r2, lsr #29 80088fa: ea4f 02c2 mov.w r2, r2, lsl #3 80088fe: ea5f 1c1c movs.w ip, ip, lsr #4 8008902: d1c0 bne.n 8008886 <__aeabi_ddiv+0x82> 8008904: f411 1f80 tst.w r1, #1048576 @ 0x100000 8008908: d10b bne.n 8008922 <__aeabi_ddiv+0x11e> 800890a: ea41 0100 orr.w r1, r1, r0 800890e: f04f 0000 mov.w r0, #0 8008912: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000 8008916: e7b6 b.n 8008886 <__aeabi_ddiv+0x82> 8008918: f411 1f80 tst.w r1, #1048576 @ 0x100000 800891c: bf04 itt eq 800891e: 4301 orreq r1, r0 8008920: 2000 moveq r0, #0 8008922: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008926: bf88 it hi 8008928: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800892c: f63f aeaf bhi.w 800868e <__aeabi_dmul+0xde> 8008930: ebb5 0c03 subs.w ip, r5, r3 8008934: bf04 itt eq 8008936: ebb6 0c02 subseq.w ip, r6, r2 800893a: ea5f 0c50 movseq.w ip, r0, lsr #1 800893e: f150 0000 adcs.w r0, r0, #0 8008942: eb41 5104 adc.w r1, r1, r4, lsl #20 8008946: bd70 pop {r4, r5, r6, pc} 8008948: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000 800894c: ea4e 3111 orr.w r1, lr, r1, lsr #12 8008950: eb14 045c adds.w r4, r4, ip, lsr #1 8008954: bfc2 ittt gt 8008956: ebd4 050c rsbsgt r5, r4, ip 800895a: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800895e: bd70 popgt {r4, r5, r6, pc} 8008960: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008964: f04f 0e00 mov.w lr, #0 8008968: 3c01 subs r4, #1 800896a: e690 b.n 800868e <__aeabi_dmul+0xde> 800896c: ea45 0e06 orr.w lr, r5, r6 8008970: e68d b.n 800868e <__aeabi_dmul+0xde> 8008972: ea0c 5513 and.w r5, ip, r3, lsr #20 8008976: ea94 0f0c teq r4, ip 800897a: bf08 it eq 800897c: ea95 0f0c teqeq r5, ip 8008980: f43f af3b beq.w 80087fa <__aeabi_dmul+0x24a> 8008984: ea94 0f0c teq r4, ip 8008988: d10a bne.n 80089a0 <__aeabi_ddiv+0x19c> 800898a: ea50 3401 orrs.w r4, r0, r1, lsl #12 800898e: f47f af34 bne.w 80087fa <__aeabi_dmul+0x24a> 8008992: ea95 0f0c teq r5, ip 8008996: f47f af25 bne.w 80087e4 <__aeabi_dmul+0x234> 800899a: 4610 mov r0, r2 800899c: 4619 mov r1, r3 800899e: e72c b.n 80087fa <__aeabi_dmul+0x24a> 80089a0: ea95 0f0c teq r5, ip 80089a4: d106 bne.n 80089b4 <__aeabi_ddiv+0x1b0> 80089a6: ea52 3503 orrs.w r5, r2, r3, lsl #12 80089aa: f43f aefd beq.w 80087a8 <__aeabi_dmul+0x1f8> 80089ae: 4610 mov r0, r2 80089b0: 4619 mov r1, r3 80089b2: e722 b.n 80087fa <__aeabi_dmul+0x24a> 80089b4: ea50 0641 orrs.w r6, r0, r1, lsl #1 80089b8: bf18 it ne 80089ba: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80089be: f47f aec5 bne.w 800874c <__aeabi_dmul+0x19c> 80089c2: ea50 0441 orrs.w r4, r0, r1, lsl #1 80089c6: f47f af0d bne.w 80087e4 <__aeabi_dmul+0x234> 80089ca: ea52 0543 orrs.w r5, r2, r3, lsl #1 80089ce: f47f aeeb bne.w 80087a8 <__aeabi_dmul+0x1f8> 80089d2: e712 b.n 80087fa <__aeabi_dmul+0x24a> 080089d4 <__gedf2>: 80089d4: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80089d8: e006 b.n 80089e8 <__cmpdf2+0x4> 80089da: bf00 nop 080089dc <__ledf2>: 80089dc: f04f 0c01 mov.w ip, #1 80089e0: e002 b.n 80089e8 <__cmpdf2+0x4> 80089e2: bf00 nop 080089e4 <__cmpdf2>: 80089e4: f04f 0c01 mov.w ip, #1 80089e8: f84d cd04 str.w ip, [sp, #-4]! 80089ec: ea4f 0c41 mov.w ip, r1, lsl #1 80089f0: ea7f 5c6c mvns.w ip, ip, asr #21 80089f4: ea4f 0c43 mov.w ip, r3, lsl #1 80089f8: bf18 it ne 80089fa: ea7f 5c6c mvnsne.w ip, ip, asr #21 80089fe: d01b beq.n 8008a38 <__cmpdf2+0x54> 8008a00: b001 add sp, #4 8008a02: ea50 0c41 orrs.w ip, r0, r1, lsl #1 8008a06: bf0c ite eq 8008a08: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 8008a0c: ea91 0f03 teqne r1, r3 8008a10: bf02 ittt eq 8008a12: ea90 0f02 teqeq r0, r2 8008a16: 2000 moveq r0, #0 8008a18: 4770 bxeq lr 8008a1a: f110 0f00 cmn.w r0, #0 8008a1e: ea91 0f03 teq r1, r3 8008a22: bf58 it pl 8008a24: 4299 cmppl r1, r3 8008a26: bf08 it eq 8008a28: 4290 cmpeq r0, r2 8008a2a: bf2c ite cs 8008a2c: 17d8 asrcs r0, r3, #31 8008a2e: ea6f 70e3 mvncc.w r0, r3, asr #31 8008a32: f040 0001 orr.w r0, r0, #1 8008a36: 4770 bx lr 8008a38: ea4f 0c41 mov.w ip, r1, lsl #1 8008a3c: ea7f 5c6c mvns.w ip, ip, asr #21 8008a40: d102 bne.n 8008a48 <__cmpdf2+0x64> 8008a42: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8008a46: d107 bne.n 8008a58 <__cmpdf2+0x74> 8008a48: ea4f 0c43 mov.w ip, r3, lsl #1 8008a4c: ea7f 5c6c mvns.w ip, ip, asr #21 8008a50: d1d6 bne.n 8008a00 <__cmpdf2+0x1c> 8008a52: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8008a56: d0d3 beq.n 8008a00 <__cmpdf2+0x1c> 8008a58: f85d 0b04 ldr.w r0, [sp], #4 8008a5c: 4770 bx lr 8008a5e: bf00 nop 08008a60 <__aeabi_cdrcmple>: 8008a60: 4684 mov ip, r0 8008a62: 4610 mov r0, r2 8008a64: 4662 mov r2, ip 8008a66: 468c mov ip, r1 8008a68: 4619 mov r1, r3 8008a6a: 4663 mov r3, ip 8008a6c: e000 b.n 8008a70 <__aeabi_cdcmpeq> 8008a6e: bf00 nop 08008a70 <__aeabi_cdcmpeq>: 8008a70: b501 push {r0, lr} 8008a72: f7ff ffb7 bl 80089e4 <__cmpdf2> 8008a76: 2800 cmp r0, #0 8008a78: bf48 it mi 8008a7a: f110 0f00 cmnmi.w r0, #0 8008a7e: bd01 pop {r0, pc} 08008a80 <__aeabi_dcmpeq>: 8008a80: f84d ed08 str.w lr, [sp, #-8]! 8008a84: f7ff fff4 bl 8008a70 <__aeabi_cdcmpeq> 8008a88: bf0c ite eq 8008a8a: 2001 moveq r0, #1 8008a8c: 2000 movne r0, #0 8008a8e: f85d fb08 ldr.w pc, [sp], #8 8008a92: bf00 nop 08008a94 <__aeabi_dcmplt>: 8008a94: f84d ed08 str.w lr, [sp, #-8]! 8008a98: f7ff ffea bl 8008a70 <__aeabi_cdcmpeq> 8008a9c: bf34 ite cc 8008a9e: 2001 movcc r0, #1 8008aa0: 2000 movcs r0, #0 8008aa2: f85d fb08 ldr.w pc, [sp], #8 8008aa6: bf00 nop 08008aa8 <__aeabi_dcmple>: 8008aa8: f84d ed08 str.w lr, [sp, #-8]! 8008aac: f7ff ffe0 bl 8008a70 <__aeabi_cdcmpeq> 8008ab0: bf94 ite ls 8008ab2: 2001 movls r0, #1 8008ab4: 2000 movhi r0, #0 8008ab6: f85d fb08 ldr.w pc, [sp], #8 8008aba: bf00 nop 08008abc <__aeabi_dcmpge>: 8008abc: f84d ed08 str.w lr, [sp, #-8]! 8008ac0: f7ff ffce bl 8008a60 <__aeabi_cdrcmple> 8008ac4: bf94 ite ls 8008ac6: 2001 movls r0, #1 8008ac8: 2000 movhi r0, #0 8008aca: f85d fb08 ldr.w pc, [sp], #8 8008ace: bf00 nop 08008ad0 <__aeabi_dcmpgt>: 8008ad0: f84d ed08 str.w lr, [sp, #-8]! 8008ad4: f7ff ffc4 bl 8008a60 <__aeabi_cdrcmple> 8008ad8: bf34 ite cc 8008ada: 2001 movcc r0, #1 8008adc: 2000 movcs r0, #0 8008ade: f85d fb08 ldr.w pc, [sp], #8 8008ae2: bf00 nop 08008ae4 <__aeabi_dcmpun>: 8008ae4: ea4f 0c41 mov.w ip, r1, lsl #1 8008ae8: ea7f 5c6c mvns.w ip, ip, asr #21 8008aec: d102 bne.n 8008af4 <__aeabi_dcmpun+0x10> 8008aee: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8008af2: d10a bne.n 8008b0a <__aeabi_dcmpun+0x26> 8008af4: ea4f 0c43 mov.w ip, r3, lsl #1 8008af8: ea7f 5c6c mvns.w ip, ip, asr #21 8008afc: d102 bne.n 8008b04 <__aeabi_dcmpun+0x20> 8008afe: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8008b02: d102 bne.n 8008b0a <__aeabi_dcmpun+0x26> 8008b04: f04f 0000 mov.w r0, #0 8008b08: 4770 bx lr 8008b0a: f04f 0001 mov.w r0, #1 8008b0e: 4770 bx lr 08008b10 <__aeabi_d2iz>: 8008b10: ea4f 0241 mov.w r2, r1, lsl #1 8008b14: f512 1200 adds.w r2, r2, #2097152 @ 0x200000 8008b18: d215 bcs.n 8008b46 <__aeabi_d2iz+0x36> 8008b1a: d511 bpl.n 8008b40 <__aeabi_d2iz+0x30> 8008b1c: f46f 7378 mvn.w r3, #992 @ 0x3e0 8008b20: ebb3 5262 subs.w r2, r3, r2, asr #21 8008b24: d912 bls.n 8008b4c <__aeabi_d2iz+0x3c> 8008b26: ea4f 23c1 mov.w r3, r1, lsl #11 8008b2a: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8008b2e: ea43 5350 orr.w r3, r3, r0, lsr #21 8008b32: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008b36: fa23 f002 lsr.w r0, r3, r2 8008b3a: bf18 it ne 8008b3c: 4240 negne r0, r0 8008b3e: 4770 bx lr 8008b40: f04f 0000 mov.w r0, #0 8008b44: 4770 bx lr 8008b46: ea50 3001 orrs.w r0, r0, r1, lsl #12 8008b4a: d105 bne.n 8008b58 <__aeabi_d2iz+0x48> 8008b4c: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000 8008b50: bf08 it eq 8008b52: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 8008b56: 4770 bx lr 8008b58: f04f 0000 mov.w r0, #0 8008b5c: 4770 bx lr 8008b5e: bf00 nop 08008b60 <__aeabi_d2f>: 8008b60: ea4f 0241 mov.w r2, r1, lsl #1 8008b64: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000 8008b68: bf24 itt cs 8008b6a: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000 8008b6e: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000 8008b72: d90d bls.n 8008b90 <__aeabi_d2f+0x30> 8008b74: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008b78: ea4f 02c0 mov.w r2, r0, lsl #3 8008b7c: ea4c 7050 orr.w r0, ip, r0, lsr #29 8008b80: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000 8008b84: eb40 0083 adc.w r0, r0, r3, lsl #2 8008b88: bf08 it eq 8008b8a: f020 0001 biceq.w r0, r0, #1 8008b8e: 4770 bx lr 8008b90: f011 4f80 tst.w r1, #1073741824 @ 0x40000000 8008b94: d121 bne.n 8008bda <__aeabi_d2f+0x7a> 8008b96: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000 8008b9a: bfbc itt lt 8008b9c: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000 8008ba0: 4770 bxlt lr 8008ba2: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008ba6: ea4f 5252 mov.w r2, r2, lsr #21 8008baa: f1c2 0218 rsb r2, r2, #24 8008bae: f1c2 0c20 rsb ip, r2, #32 8008bb2: fa10 f30c lsls.w r3, r0, ip 8008bb6: fa20 f002 lsr.w r0, r0, r2 8008bba: bf18 it ne 8008bbc: f040 0001 orrne.w r0, r0, #1 8008bc0: ea4f 23c1 mov.w r3, r1, lsl #11 8008bc4: ea4f 23d3 mov.w r3, r3, lsr #11 8008bc8: fa03 fc0c lsl.w ip, r3, ip 8008bcc: ea40 000c orr.w r0, r0, ip 8008bd0: fa23 f302 lsr.w r3, r3, r2 8008bd4: ea4f 0343 mov.w r3, r3, lsl #1 8008bd8: e7cc b.n 8008b74 <__aeabi_d2f+0x14> 8008bda: ea7f 5362 mvns.w r3, r2, asr #21 8008bde: d107 bne.n 8008bf0 <__aeabi_d2f+0x90> 8008be0: ea50 3301 orrs.w r3, r0, r1, lsl #12 8008be4: bf1e ittt ne 8008be6: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000 8008bea: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000 8008bee: 4770 bxne lr 8008bf0: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000 8008bf4: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008bf8: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008bfc: 4770 bx lr 8008bfe: bf00 nop 08008c00 <__aeabi_frsub>: 8008c00: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000 8008c04: e002 b.n 8008c0c <__addsf3> 8008c06: bf00 nop 08008c08 <__aeabi_fsub>: 8008c08: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 08008c0c <__addsf3>: 8008c0c: 0042 lsls r2, r0, #1 8008c0e: bf1f itttt ne 8008c10: ea5f 0341 movsne.w r3, r1, lsl #1 8008c14: ea92 0f03 teqne r2, r3 8008c18: ea7f 6c22 mvnsne.w ip, r2, asr #24 8008c1c: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008c20: d06a beq.n 8008cf8 <__addsf3+0xec> 8008c22: ea4f 6212 mov.w r2, r2, lsr #24 8008c26: ebd2 6313 rsbs r3, r2, r3, lsr #24 8008c2a: bfc1 itttt gt 8008c2c: 18d2 addgt r2, r2, r3 8008c2e: 4041 eorgt r1, r0 8008c30: 4048 eorgt r0, r1 8008c32: 4041 eorgt r1, r0 8008c34: bfb8 it lt 8008c36: 425b neglt r3, r3 8008c38: 2b19 cmp r3, #25 8008c3a: bf88 it hi 8008c3c: 4770 bxhi lr 8008c3e: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 8008c42: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008c46: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000 8008c4a: bf18 it ne 8008c4c: 4240 negne r0, r0 8008c4e: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008c52: f441 0100 orr.w r1, r1, #8388608 @ 0x800000 8008c56: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000 8008c5a: bf18 it ne 8008c5c: 4249 negne r1, r1 8008c5e: ea92 0f03 teq r2, r3 8008c62: d03f beq.n 8008ce4 <__addsf3+0xd8> 8008c64: f1a2 0201 sub.w r2, r2, #1 8008c68: fa41 fc03 asr.w ip, r1, r3 8008c6c: eb10 000c adds.w r0, r0, ip 8008c70: f1c3 0320 rsb r3, r3, #32 8008c74: fa01 f103 lsl.w r1, r1, r3 8008c78: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008c7c: d502 bpl.n 8008c84 <__addsf3+0x78> 8008c7e: 4249 negs r1, r1 8008c80: eb60 0040 sbc.w r0, r0, r0, lsl #1 8008c84: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000 8008c88: d313 bcc.n 8008cb2 <__addsf3+0xa6> 8008c8a: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000 8008c8e: d306 bcc.n 8008c9e <__addsf3+0x92> 8008c90: 0840 lsrs r0, r0, #1 8008c92: ea4f 0131 mov.w r1, r1, rrx 8008c96: f102 0201 add.w r2, r2, #1 8008c9a: 2afe cmp r2, #254 @ 0xfe 8008c9c: d251 bcs.n 8008d42 <__addsf3+0x136> 8008c9e: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000 8008ca2: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008ca6: bf08 it eq 8008ca8: f020 0001 biceq.w r0, r0, #1 8008cac: ea40 0003 orr.w r0, r0, r3 8008cb0: 4770 bx lr 8008cb2: 0049 lsls r1, r1, #1 8008cb4: eb40 0000 adc.w r0, r0, r0 8008cb8: 3a01 subs r2, #1 8008cba: bf28 it cs 8008cbc: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000 8008cc0: d2ed bcs.n 8008c9e <__addsf3+0x92> 8008cc2: fab0 fc80 clz ip, r0 8008cc6: f1ac 0c08 sub.w ip, ip, #8 8008cca: ebb2 020c subs.w r2, r2, ip 8008cce: fa00 f00c lsl.w r0, r0, ip 8008cd2: bfaa itet ge 8008cd4: eb00 50c2 addge.w r0, r0, r2, lsl #23 8008cd8: 4252 neglt r2, r2 8008cda: 4318 orrge r0, r3 8008cdc: bfbc itt lt 8008cde: 40d0 lsrlt r0, r2 8008ce0: 4318 orrlt r0, r3 8008ce2: 4770 bx lr 8008ce4: f092 0f00 teq r2, #0 8008ce8: f481 0100 eor.w r1, r1, #8388608 @ 0x800000 8008cec: bf06 itte eq 8008cee: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000 8008cf2: 3201 addeq r2, #1 8008cf4: 3b01 subne r3, #1 8008cf6: e7b5 b.n 8008c64 <__addsf3+0x58> 8008cf8: ea4f 0341 mov.w r3, r1, lsl #1 8008cfc: ea7f 6c22 mvns.w ip, r2, asr #24 8008d00: bf18 it ne 8008d02: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008d06: d021 beq.n 8008d4c <__addsf3+0x140> 8008d08: ea92 0f03 teq r2, r3 8008d0c: d004 beq.n 8008d18 <__addsf3+0x10c> 8008d0e: f092 0f00 teq r2, #0 8008d12: bf08 it eq 8008d14: 4608 moveq r0, r1 8008d16: 4770 bx lr 8008d18: ea90 0f01 teq r0, r1 8008d1c: bf1c itt ne 8008d1e: 2000 movne r0, #0 8008d20: 4770 bxne lr 8008d22: f012 4f7f tst.w r2, #4278190080 @ 0xff000000 8008d26: d104 bne.n 8008d32 <__addsf3+0x126> 8008d28: 0040 lsls r0, r0, #1 8008d2a: bf28 it cs 8008d2c: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000 8008d30: 4770 bx lr 8008d32: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000 8008d36: bf3c itt cc 8008d38: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000 8008d3c: 4770 bxcc lr 8008d3e: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008d42: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000 8008d46: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008d4a: 4770 bx lr 8008d4c: ea7f 6222 mvns.w r2, r2, asr #24 8008d50: bf16 itet ne 8008d52: 4608 movne r0, r1 8008d54: ea7f 6323 mvnseq.w r3, r3, asr #24 8008d58: 4601 movne r1, r0 8008d5a: 0242 lsls r2, r0, #9 8008d5c: bf06 itte eq 8008d5e: ea5f 2341 movseq.w r3, r1, lsl #9 8008d62: ea90 0f01 teqeq r0, r1 8008d66: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000 8008d6a: 4770 bx lr 08008d6c <__aeabi_ui2f>: 8008d6c: f04f 0300 mov.w r3, #0 8008d70: e004 b.n 8008d7c <__aeabi_i2f+0x8> 8008d72: bf00 nop 08008d74 <__aeabi_i2f>: 8008d74: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000 8008d78: bf48 it mi 8008d7a: 4240 negmi r0, r0 8008d7c: ea5f 0c00 movs.w ip, r0 8008d80: bf08 it eq 8008d82: 4770 bxeq lr 8008d84: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000 8008d88: 4601 mov r1, r0 8008d8a: f04f 0000 mov.w r0, #0 8008d8e: e01c b.n 8008dca <__aeabi_l2f+0x2a> 08008d90 <__aeabi_ul2f>: 8008d90: ea50 0201 orrs.w r2, r0, r1 8008d94: bf08 it eq 8008d96: 4770 bxeq lr 8008d98: f04f 0300 mov.w r3, #0 8008d9c: e00a b.n 8008db4 <__aeabi_l2f+0x14> 8008d9e: bf00 nop 08008da0 <__aeabi_l2f>: 8008da0: ea50 0201 orrs.w r2, r0, r1 8008da4: bf08 it eq 8008da6: 4770 bxeq lr 8008da8: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000 8008dac: d502 bpl.n 8008db4 <__aeabi_l2f+0x14> 8008dae: 4240 negs r0, r0 8008db0: eb61 0141 sbc.w r1, r1, r1, lsl #1 8008db4: ea5f 0c01 movs.w ip, r1 8008db8: bf02 ittt eq 8008dba: 4684 moveq ip, r0 8008dbc: 4601 moveq r1, r0 8008dbe: 2000 moveq r0, #0 8008dc0: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000 8008dc4: bf08 it eq 8008dc6: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000 8008dca: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 8008dce: fabc f28c clz r2, ip 8008dd2: 3a08 subs r2, #8 8008dd4: eba3 53c2 sub.w r3, r3, r2, lsl #23 8008dd8: db10 blt.n 8008dfc <__aeabi_l2f+0x5c> 8008dda: fa01 fc02 lsl.w ip, r1, r2 8008dde: 4463 add r3, ip 8008de0: fa00 fc02 lsl.w ip, r0, r2 8008de4: f1c2 0220 rsb r2, r2, #32 8008de8: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008dec: fa20 f202 lsr.w r2, r0, r2 8008df0: eb43 0002 adc.w r0, r3, r2 8008df4: bf08 it eq 8008df6: f020 0001 biceq.w r0, r0, #1 8008dfa: 4770 bx lr 8008dfc: f102 0220 add.w r2, r2, #32 8008e00: fa01 fc02 lsl.w ip, r1, r2 8008e04: f1c2 0220 rsb r2, r2, #32 8008e08: ea50 004c orrs.w r0, r0, ip, lsl #1 8008e0c: fa21 f202 lsr.w r2, r1, r2 8008e10: eb43 0002 adc.w r0, r3, r2 8008e14: bf08 it eq 8008e16: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008e1a: 4770 bx lr 08008e1c <__aeabi_fmul>: 8008e1c: f04f 0cff mov.w ip, #255 @ 0xff 8008e20: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008e24: bf1e ittt ne 8008e26: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008e2a: ea92 0f0c teqne r2, ip 8008e2e: ea93 0f0c teqne r3, ip 8008e32: d06f beq.n 8008f14 <__aeabi_fmul+0xf8> 8008e34: 441a add r2, r3 8008e36: ea80 0c01 eor.w ip, r0, r1 8008e3a: 0240 lsls r0, r0, #9 8008e3c: bf18 it ne 8008e3e: ea5f 2141 movsne.w r1, r1, lsl #9 8008e42: d01e beq.n 8008e82 <__aeabi_fmul+0x66> 8008e44: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8008e48: ea43 1050 orr.w r0, r3, r0, lsr #5 8008e4c: ea43 1151 orr.w r1, r3, r1, lsr #5 8008e50: fba0 3101 umull r3, r1, r0, r1 8008e54: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008e58: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000 8008e5c: bf3e ittt cc 8008e5e: 0049 lslcc r1, r1, #1 8008e60: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 8008e64: 005b lslcc r3, r3, #1 8008e66: ea40 0001 orr.w r0, r0, r1 8008e6a: f162 027f sbc.w r2, r2, #127 @ 0x7f 8008e6e: 2afd cmp r2, #253 @ 0xfd 8008e70: d81d bhi.n 8008eae <__aeabi_fmul+0x92> 8008e72: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008e76: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008e7a: bf08 it eq 8008e7c: f020 0001 biceq.w r0, r0, #1 8008e80: 4770 bx lr 8008e82: f090 0f00 teq r0, #0 8008e86: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8008e8a: bf08 it eq 8008e8c: 0249 lsleq r1, r1, #9 8008e8e: ea4c 2050 orr.w r0, ip, r0, lsr #9 8008e92: ea40 2051 orr.w r0, r0, r1, lsr #9 8008e96: 3a7f subs r2, #127 @ 0x7f 8008e98: bfc2 ittt gt 8008e9a: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 8008e9e: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8008ea2: 4770 bxgt lr 8008ea4: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008ea8: f04f 0300 mov.w r3, #0 8008eac: 3a01 subs r2, #1 8008eae: dc5d bgt.n 8008f6c <__aeabi_fmul+0x150> 8008eb0: f112 0f19 cmn.w r2, #25 8008eb4: bfdc itt le 8008eb6: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000 8008eba: 4770 bxle lr 8008ebc: f1c2 0200 rsb r2, r2, #0 8008ec0: 0041 lsls r1, r0, #1 8008ec2: fa21 f102 lsr.w r1, r1, r2 8008ec6: f1c2 0220 rsb r2, r2, #32 8008eca: fa00 fc02 lsl.w ip, r0, r2 8008ece: ea5f 0031 movs.w r0, r1, rrx 8008ed2: f140 0000 adc.w r0, r0, #0 8008ed6: ea53 034c orrs.w r3, r3, ip, lsl #1 8008eda: bf08 it eq 8008edc: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008ee0: 4770 bx lr 8008ee2: f092 0f00 teq r2, #0 8008ee6: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8008eea: bf02 ittt eq 8008eec: 0040 lsleq r0, r0, #1 8008eee: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 8008ef2: 3a01 subeq r2, #1 8008ef4: d0f9 beq.n 8008eea <__aeabi_fmul+0xce> 8008ef6: ea40 000c orr.w r0, r0, ip 8008efa: f093 0f00 teq r3, #0 8008efe: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008f02: bf02 ittt eq 8008f04: 0049 lsleq r1, r1, #1 8008f06: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8008f0a: 3b01 subeq r3, #1 8008f0c: d0f9 beq.n 8008f02 <__aeabi_fmul+0xe6> 8008f0e: ea41 010c orr.w r1, r1, ip 8008f12: e78f b.n 8008e34 <__aeabi_fmul+0x18> 8008f14: ea0c 53d1 and.w r3, ip, r1, lsr #23 8008f18: ea92 0f0c teq r2, ip 8008f1c: bf18 it ne 8008f1e: ea93 0f0c teqne r3, ip 8008f22: d00a beq.n 8008f3a <__aeabi_fmul+0x11e> 8008f24: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 8008f28: bf18 it ne 8008f2a: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 8008f2e: d1d8 bne.n 8008ee2 <__aeabi_fmul+0xc6> 8008f30: ea80 0001 eor.w r0, r0, r1 8008f34: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008f38: 4770 bx lr 8008f3a: f090 0f00 teq r0, #0 8008f3e: bf17 itett ne 8008f40: f090 4f00 teqne r0, #2147483648 @ 0x80000000 8008f44: 4608 moveq r0, r1 8008f46: f091 0f00 teqne r1, #0 8008f4a: f091 4f00 teqne r1, #2147483648 @ 0x80000000 8008f4e: d014 beq.n 8008f7a <__aeabi_fmul+0x15e> 8008f50: ea92 0f0c teq r2, ip 8008f54: d101 bne.n 8008f5a <__aeabi_fmul+0x13e> 8008f56: 0242 lsls r2, r0, #9 8008f58: d10f bne.n 8008f7a <__aeabi_fmul+0x15e> 8008f5a: ea93 0f0c teq r3, ip 8008f5e: d103 bne.n 8008f68 <__aeabi_fmul+0x14c> 8008f60: 024b lsls r3, r1, #9 8008f62: bf18 it ne 8008f64: 4608 movne r0, r1 8008f66: d108 bne.n 8008f7a <__aeabi_fmul+0x15e> 8008f68: ea80 0001 eor.w r0, r0, r1 8008f6c: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008f70: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008f74: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008f78: 4770 bx lr 8008f7a: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008f7e: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000 8008f82: 4770 bx lr 08008f84 <__aeabi_fdiv>: 8008f84: f04f 0cff mov.w ip, #255 @ 0xff 8008f88: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008f8c: bf1e ittt ne 8008f8e: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008f92: ea92 0f0c teqne r2, ip 8008f96: ea93 0f0c teqne r3, ip 8008f9a: d069 beq.n 8009070 <__aeabi_fdiv+0xec> 8008f9c: eba2 0203 sub.w r2, r2, r3 8008fa0: ea80 0c01 eor.w ip, r0, r1 8008fa4: 0249 lsls r1, r1, #9 8008fa6: ea4f 2040 mov.w r0, r0, lsl #9 8008faa: d037 beq.n 800901c <__aeabi_fdiv+0x98> 8008fac: f04f 5380 mov.w r3, #268435456 @ 0x10000000 8008fb0: ea43 1111 orr.w r1, r3, r1, lsr #4 8008fb4: ea43 1310 orr.w r3, r3, r0, lsr #4 8008fb8: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008fbc: 428b cmp r3, r1 8008fbe: bf38 it cc 8008fc0: 005b lslcc r3, r3, #1 8008fc2: f142 027d adc.w r2, r2, #125 @ 0x7d 8008fc6: f44f 0c00 mov.w ip, #8388608 @ 0x800000 8008fca: 428b cmp r3, r1 8008fcc: bf24 itt cs 8008fce: 1a5b subcs r3, r3, r1 8008fd0: ea40 000c orrcs.w r0, r0, ip 8008fd4: ebb3 0f51 cmp.w r3, r1, lsr #1 8008fd8: bf24 itt cs 8008fda: eba3 0351 subcs.w r3, r3, r1, lsr #1 8008fde: ea40 005c orrcs.w r0, r0, ip, lsr #1 8008fe2: ebb3 0f91 cmp.w r3, r1, lsr #2 8008fe6: bf24 itt cs 8008fe8: eba3 0391 subcs.w r3, r3, r1, lsr #2 8008fec: ea40 009c orrcs.w r0, r0, ip, lsr #2 8008ff0: ebb3 0fd1 cmp.w r3, r1, lsr #3 8008ff4: bf24 itt cs 8008ff6: eba3 03d1 subcs.w r3, r3, r1, lsr #3 8008ffa: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8008ffe: 011b lsls r3, r3, #4 8009000: bf18 it ne 8009002: ea5f 1c1c movsne.w ip, ip, lsr #4 8009006: d1e0 bne.n 8008fca <__aeabi_fdiv+0x46> 8009008: 2afd cmp r2, #253 @ 0xfd 800900a: f63f af50 bhi.w 8008eae <__aeabi_fmul+0x92> 800900e: 428b cmp r3, r1 8009010: eb40 50c2 adc.w r0, r0, r2, lsl #23 8009014: bf08 it eq 8009016: f020 0001 biceq.w r0, r0, #1 800901a: 4770 bx lr 800901c: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8009020: ea4c 2050 orr.w r0, ip, r0, lsr #9 8009024: 327f adds r2, #127 @ 0x7f 8009026: bfc2 ittt gt 8009028: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 800902c: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8009030: 4770 bxgt lr 8009032: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8009036: f04f 0300 mov.w r3, #0 800903a: 3a01 subs r2, #1 800903c: e737 b.n 8008eae <__aeabi_fmul+0x92> 800903e: f092 0f00 teq r2, #0 8009042: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8009046: bf02 ittt eq 8009048: 0040 lsleq r0, r0, #1 800904a: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 800904e: 3a01 subeq r2, #1 8009050: d0f9 beq.n 8009046 <__aeabi_fdiv+0xc2> 8009052: ea40 000c orr.w r0, r0, ip 8009056: f093 0f00 teq r3, #0 800905a: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 800905e: bf02 ittt eq 8009060: 0049 lsleq r1, r1, #1 8009062: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8009066: 3b01 subeq r3, #1 8009068: d0f9 beq.n 800905e <__aeabi_fdiv+0xda> 800906a: ea41 010c orr.w r1, r1, ip 800906e: e795 b.n 8008f9c <__aeabi_fdiv+0x18> 8009070: ea0c 53d1 and.w r3, ip, r1, lsr #23 8009074: ea92 0f0c teq r2, ip 8009078: d108 bne.n 800908c <__aeabi_fdiv+0x108> 800907a: 0242 lsls r2, r0, #9 800907c: f47f af7d bne.w 8008f7a <__aeabi_fmul+0x15e> 8009080: ea93 0f0c teq r3, ip 8009084: f47f af70 bne.w 8008f68 <__aeabi_fmul+0x14c> 8009088: 4608 mov r0, r1 800908a: e776 b.n 8008f7a <__aeabi_fmul+0x15e> 800908c: ea93 0f0c teq r3, ip 8009090: d104 bne.n 800909c <__aeabi_fdiv+0x118> 8009092: 024b lsls r3, r1, #9 8009094: f43f af4c beq.w 8008f30 <__aeabi_fmul+0x114> 8009098: 4608 mov r0, r1 800909a: e76e b.n 8008f7a <__aeabi_fmul+0x15e> 800909c: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 80090a0: bf18 it ne 80090a2: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 80090a6: d1ca bne.n 800903e <__aeabi_fdiv+0xba> 80090a8: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000 80090ac: f47f af5c bne.w 8008f68 <__aeabi_fmul+0x14c> 80090b0: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000 80090b4: f47f af3c bne.w 8008f30 <__aeabi_fmul+0x114> 80090b8: e75f b.n 8008f7a <__aeabi_fmul+0x15e> 80090ba: bf00 nop 080090bc <__gesf2>: 80090bc: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80090c0: e006 b.n 80090d0 <__cmpsf2+0x4> 80090c2: bf00 nop 080090c4 <__lesf2>: 80090c4: f04f 0c01 mov.w ip, #1 80090c8: e002 b.n 80090d0 <__cmpsf2+0x4> 80090ca: bf00 nop 080090cc <__cmpsf2>: 80090cc: f04f 0c01 mov.w ip, #1 80090d0: f84d cd04 str.w ip, [sp, #-4]! 80090d4: ea4f 0240 mov.w r2, r0, lsl #1 80090d8: ea4f 0341 mov.w r3, r1, lsl #1 80090dc: ea7f 6c22 mvns.w ip, r2, asr #24 80090e0: bf18 it ne 80090e2: ea7f 6c23 mvnsne.w ip, r3, asr #24 80090e6: d011 beq.n 800910c <__cmpsf2+0x40> 80090e8: b001 add sp, #4 80090ea: ea52 0c53 orrs.w ip, r2, r3, lsr #1 80090ee: bf18 it ne 80090f0: ea90 0f01 teqne r0, r1 80090f4: bf58 it pl 80090f6: ebb2 0003 subspl.w r0, r2, r3 80090fa: bf88 it hi 80090fc: 17c8 asrhi r0, r1, #31 80090fe: bf38 it cc 8009100: ea6f 70e1 mvncc.w r0, r1, asr #31 8009104: bf18 it ne 8009106: f040 0001 orrne.w r0, r0, #1 800910a: 4770 bx lr 800910c: ea7f 6c22 mvns.w ip, r2, asr #24 8009110: d102 bne.n 8009118 <__cmpsf2+0x4c> 8009112: ea5f 2c40 movs.w ip, r0, lsl #9 8009116: d105 bne.n 8009124 <__cmpsf2+0x58> 8009118: ea7f 6c23 mvns.w ip, r3, asr #24 800911c: d1e4 bne.n 80090e8 <__cmpsf2+0x1c> 800911e: ea5f 2c41 movs.w ip, r1, lsl #9 8009122: d0e1 beq.n 80090e8 <__cmpsf2+0x1c> 8009124: f85d 0b04 ldr.w r0, [sp], #4 8009128: 4770 bx lr 800912a: bf00 nop 0800912c <__aeabi_cfrcmple>: 800912c: 4684 mov ip, r0 800912e: 4608 mov r0, r1 8009130: 4661 mov r1, ip 8009132: e7ff b.n 8009134 <__aeabi_cfcmpeq> 08009134 <__aeabi_cfcmpeq>: 8009134: b50f push {r0, r1, r2, r3, lr} 8009136: f7ff ffc9 bl 80090cc <__cmpsf2> 800913a: 2800 cmp r0, #0 800913c: bf48 it mi 800913e: f110 0f00 cmnmi.w r0, #0 8009142: bd0f pop {r0, r1, r2, r3, pc} 08009144 <__aeabi_fcmpeq>: 8009144: f84d ed08 str.w lr, [sp, #-8]! 8009148: f7ff fff4 bl 8009134 <__aeabi_cfcmpeq> 800914c: bf0c ite eq 800914e: 2001 moveq r0, #1 8009150: 2000 movne r0, #0 8009152: f85d fb08 ldr.w pc, [sp], #8 8009156: bf00 nop 08009158 <__aeabi_fcmplt>: 8009158: f84d ed08 str.w lr, [sp, #-8]! 800915c: f7ff ffea bl 8009134 <__aeabi_cfcmpeq> 8009160: bf34 ite cc 8009162: 2001 movcc r0, #1 8009164: 2000 movcs r0, #0 8009166: f85d fb08 ldr.w pc, [sp], #8 800916a: bf00 nop 0800916c <__aeabi_fcmple>: 800916c: f84d ed08 str.w lr, [sp, #-8]! 8009170: f7ff ffe0 bl 8009134 <__aeabi_cfcmpeq> 8009174: bf94 ite ls 8009176: 2001 movls r0, #1 8009178: 2000 movhi r0, #0 800917a: f85d fb08 ldr.w pc, [sp], #8 800917e: bf00 nop 08009180 <__aeabi_fcmpge>: 8009180: f84d ed08 str.w lr, [sp, #-8]! 8009184: f7ff ffd2 bl 800912c <__aeabi_cfrcmple> 8009188: bf94 ite ls 800918a: 2001 movls r0, #1 800918c: 2000 movhi r0, #0 800918e: f85d fb08 ldr.w pc, [sp], #8 8009192: bf00 nop 08009194 <__aeabi_fcmpgt>: 8009194: f84d ed08 str.w lr, [sp, #-8]! 8009198: f7ff ffc8 bl 800912c <__aeabi_cfrcmple> 800919c: bf34 ite cc 800919e: 2001 movcc r0, #1 80091a0: 2000 movcs r0, #0 80091a2: f85d fb08 ldr.w pc, [sp], #8 80091a6: bf00 nop 080091a8 <__aeabi_f2iz>: 80091a8: ea4f 0240 mov.w r2, r0, lsl #1 80091ac: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000 80091b0: d30f bcc.n 80091d2 <__aeabi_f2iz+0x2a> 80091b2: f04f 039e mov.w r3, #158 @ 0x9e 80091b6: ebb3 6212 subs.w r2, r3, r2, lsr #24 80091ba: d90d bls.n 80091d8 <__aeabi_f2iz+0x30> 80091bc: ea4f 2300 mov.w r3, r0, lsl #8 80091c0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80091c4: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 80091c8: fa23 f002 lsr.w r0, r3, r2 80091cc: bf18 it ne 80091ce: 4240 negne r0, r0 80091d0: 4770 bx lr 80091d2: f04f 0000 mov.w r0, #0 80091d6: 4770 bx lr 80091d8: f112 0f61 cmn.w r2, #97 @ 0x61 80091dc: d101 bne.n 80091e2 <__aeabi_f2iz+0x3a> 80091de: 0242 lsls r2, r0, #9 80091e0: d105 bne.n 80091ee <__aeabi_f2iz+0x46> 80091e2: f010 4000 ands.w r0, r0, #2147483648 @ 0x80000000 80091e6: bf08 it eq 80091e8: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 80091ec: 4770 bx lr 80091ee: f04f 0000 mov.w r0, #0 80091f2: 4770 bx lr 080091f4 <__aeabi_uldivmod>: 80091f4: b953 cbnz r3, 800920c <__aeabi_uldivmod+0x18> 80091f6: b94a cbnz r2, 800920c <__aeabi_uldivmod+0x18> 80091f8: 2900 cmp r1, #0 80091fa: bf08 it eq 80091fc: 2800 cmpeq r0, #0 80091fe: bf1c itt ne 8009200: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8009204: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8009208: f000 b98c b.w 8009524 <__aeabi_idiv0> 800920c: f1ad 0c08 sub.w ip, sp, #8 8009210: e96d ce04 strd ip, lr, [sp, #-16]! 8009214: f000 f806 bl 8009224 <__udivmoddi4> 8009218: f8dd e004 ldr.w lr, [sp, #4] 800921c: e9dd 2302 ldrd r2, r3, [sp, #8] 8009220: b004 add sp, #16 8009222: 4770 bx lr 08009224 <__udivmoddi4>: 8009224: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8009228: 9d08 ldr r5, [sp, #32] 800922a: 468e mov lr, r1 800922c: 4604 mov r4, r0 800922e: 4688 mov r8, r1 8009230: 2b00 cmp r3, #0 8009232: d14a bne.n 80092ca <__udivmoddi4+0xa6> 8009234: 428a cmp r2, r1 8009236: 4617 mov r7, r2 8009238: d962 bls.n 8009300 <__udivmoddi4+0xdc> 800923a: fab2 f682 clz r6, r2 800923e: b14e cbz r6, 8009254 <__udivmoddi4+0x30> 8009240: f1c6 0320 rsb r3, r6, #32 8009244: fa01 f806 lsl.w r8, r1, r6 8009248: fa20 f303 lsr.w r3, r0, r3 800924c: 40b7 lsls r7, r6 800924e: ea43 0808 orr.w r8, r3, r8 8009252: 40b4 lsls r4, r6 8009254: ea4f 4e17 mov.w lr, r7, lsr #16 8009258: fbb8 f1fe udiv r1, r8, lr 800925c: fa1f fc87 uxth.w ip, r7 8009260: fb0e 8811 mls r8, lr, r1, r8 8009264: fb01 f20c mul.w r2, r1, ip 8009268: 0c23 lsrs r3, r4, #16 800926a: ea43 4308 orr.w r3, r3, r8, lsl #16 800926e: 429a cmp r2, r3 8009270: d909 bls.n 8009286 <__udivmoddi4+0x62> 8009272: 18fb adds r3, r7, r3 8009274: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8009278: f080 80eb bcs.w 8009452 <__udivmoddi4+0x22e> 800927c: 429a cmp r2, r3 800927e: f240 80e8 bls.w 8009452 <__udivmoddi4+0x22e> 8009282: 3902 subs r1, #2 8009284: 443b add r3, r7 8009286: 1a9a subs r2, r3, r2 8009288: fbb2 f0fe udiv r0, r2, lr 800928c: fb0e 2210 mls r2, lr, r0, r2 8009290: fb00 fc0c mul.w ip, r0, ip 8009294: b2a3 uxth r3, r4 8009296: ea43 4302 orr.w r3, r3, r2, lsl #16 800929a: 459c cmp ip, r3 800929c: d909 bls.n 80092b2 <__udivmoddi4+0x8e> 800929e: 18fb adds r3, r7, r3 80092a0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80092a4: f080 80d7 bcs.w 8009456 <__udivmoddi4+0x232> 80092a8: 459c cmp ip, r3 80092aa: f240 80d4 bls.w 8009456 <__udivmoddi4+0x232> 80092ae: 443b add r3, r7 80092b0: 3802 subs r0, #2 80092b2: ea40 4001 orr.w r0, r0, r1, lsl #16 80092b6: 2100 movs r1, #0 80092b8: eba3 030c sub.w r3, r3, ip 80092bc: b11d cbz r5, 80092c6 <__udivmoddi4+0xa2> 80092be: 2200 movs r2, #0 80092c0: 40f3 lsrs r3, r6 80092c2: e9c5 3200 strd r3, r2, [r5] 80092c6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80092ca: 428b cmp r3, r1 80092cc: d905 bls.n 80092da <__udivmoddi4+0xb6> 80092ce: b10d cbz r5, 80092d4 <__udivmoddi4+0xb0> 80092d0: e9c5 0100 strd r0, r1, [r5] 80092d4: 2100 movs r1, #0 80092d6: 4608 mov r0, r1 80092d8: e7f5 b.n 80092c6 <__udivmoddi4+0xa2> 80092da: fab3 f183 clz r1, r3 80092de: 2900 cmp r1, #0 80092e0: d146 bne.n 8009370 <__udivmoddi4+0x14c> 80092e2: 4573 cmp r3, lr 80092e4: d302 bcc.n 80092ec <__udivmoddi4+0xc8> 80092e6: 4282 cmp r2, r0 80092e8: f200 8108 bhi.w 80094fc <__udivmoddi4+0x2d8> 80092ec: 1a84 subs r4, r0, r2 80092ee: eb6e 0203 sbc.w r2, lr, r3 80092f2: 2001 movs r0, #1 80092f4: 4690 mov r8, r2 80092f6: 2d00 cmp r5, #0 80092f8: d0e5 beq.n 80092c6 <__udivmoddi4+0xa2> 80092fa: e9c5 4800 strd r4, r8, [r5] 80092fe: e7e2 b.n 80092c6 <__udivmoddi4+0xa2> 8009300: 2a00 cmp r2, #0 8009302: f000 8091 beq.w 8009428 <__udivmoddi4+0x204> 8009306: fab2 f682 clz r6, r2 800930a: 2e00 cmp r6, #0 800930c: f040 80a5 bne.w 800945a <__udivmoddi4+0x236> 8009310: 1a8a subs r2, r1, r2 8009312: 2101 movs r1, #1 8009314: 0c03 lsrs r3, r0, #16 8009316: ea4f 4e17 mov.w lr, r7, lsr #16 800931a: b280 uxth r0, r0 800931c: b2bc uxth r4, r7 800931e: fbb2 fcfe udiv ip, r2, lr 8009322: fb0e 221c mls r2, lr, ip, r2 8009326: ea43 4302 orr.w r3, r3, r2, lsl #16 800932a: fb04 f20c mul.w r2, r4, ip 800932e: 429a cmp r2, r3 8009330: d907 bls.n 8009342 <__udivmoddi4+0x11e> 8009332: 18fb adds r3, r7, r3 8009334: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8009338: d202 bcs.n 8009340 <__udivmoddi4+0x11c> 800933a: 429a cmp r2, r3 800933c: f200 80e3 bhi.w 8009506 <__udivmoddi4+0x2e2> 8009340: 46c4 mov ip, r8 8009342: 1a9b subs r3, r3, r2 8009344: fbb3 f2fe udiv r2, r3, lr 8009348: fb0e 3312 mls r3, lr, r2, r3 800934c: fb02 f404 mul.w r4, r2, r4 8009350: ea40 4303 orr.w r3, r0, r3, lsl #16 8009354: 429c cmp r4, r3 8009356: d907 bls.n 8009368 <__udivmoddi4+0x144> 8009358: 18fb adds r3, r7, r3 800935a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800935e: d202 bcs.n 8009366 <__udivmoddi4+0x142> 8009360: 429c cmp r4, r3 8009362: f200 80cd bhi.w 8009500 <__udivmoddi4+0x2dc> 8009366: 4602 mov r2, r0 8009368: 1b1b subs r3, r3, r4 800936a: ea42 400c orr.w r0, r2, ip, lsl #16 800936e: e7a5 b.n 80092bc <__udivmoddi4+0x98> 8009370: f1c1 0620 rsb r6, r1, #32 8009374: 408b lsls r3, r1 8009376: fa22 f706 lsr.w r7, r2, r6 800937a: 431f orrs r7, r3 800937c: fa2e fa06 lsr.w sl, lr, r6 8009380: ea4f 4917 mov.w r9, r7, lsr #16 8009384: fbba f8f9 udiv r8, sl, r9 8009388: fa0e fe01 lsl.w lr, lr, r1 800938c: fa20 f306 lsr.w r3, r0, r6 8009390: fb09 aa18 mls sl, r9, r8, sl 8009394: fa1f fc87 uxth.w ip, r7 8009398: ea43 030e orr.w r3, r3, lr 800939c: fa00 fe01 lsl.w lr, r0, r1 80093a0: fb08 f00c mul.w r0, r8, ip 80093a4: 0c1c lsrs r4, r3, #16 80093a6: ea44 440a orr.w r4, r4, sl, lsl #16 80093aa: 42a0 cmp r0, r4 80093ac: fa02 f201 lsl.w r2, r2, r1 80093b0: d90a bls.n 80093c8 <__udivmoddi4+0x1a4> 80093b2: 193c adds r4, r7, r4 80093b4: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff 80093b8: f080 809e bcs.w 80094f8 <__udivmoddi4+0x2d4> 80093bc: 42a0 cmp r0, r4 80093be: f240 809b bls.w 80094f8 <__udivmoddi4+0x2d4> 80093c2: f1a8 0802 sub.w r8, r8, #2 80093c6: 443c add r4, r7 80093c8: 1a24 subs r4, r4, r0 80093ca: b298 uxth r0, r3 80093cc: fbb4 f3f9 udiv r3, r4, r9 80093d0: fb09 4413 mls r4, r9, r3, r4 80093d4: fb03 fc0c mul.w ip, r3, ip 80093d8: ea40 4404 orr.w r4, r0, r4, lsl #16 80093dc: 45a4 cmp ip, r4 80093de: d909 bls.n 80093f4 <__udivmoddi4+0x1d0> 80093e0: 193c adds r4, r7, r4 80093e2: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 80093e6: f080 8085 bcs.w 80094f4 <__udivmoddi4+0x2d0> 80093ea: 45a4 cmp ip, r4 80093ec: f240 8082 bls.w 80094f4 <__udivmoddi4+0x2d0> 80093f0: 3b02 subs r3, #2 80093f2: 443c add r4, r7 80093f4: ea43 4008 orr.w r0, r3, r8, lsl #16 80093f8: eba4 040c sub.w r4, r4, ip 80093fc: fba0 8c02 umull r8, ip, r0, r2 8009400: 4564 cmp r4, ip 8009402: 4643 mov r3, r8 8009404: 46e1 mov r9, ip 8009406: d364 bcc.n 80094d2 <__udivmoddi4+0x2ae> 8009408: d061 beq.n 80094ce <__udivmoddi4+0x2aa> 800940a: b15d cbz r5, 8009424 <__udivmoddi4+0x200> 800940c: ebbe 0203 subs.w r2, lr, r3 8009410: eb64 0409 sbc.w r4, r4, r9 8009414: fa04 f606 lsl.w r6, r4, r6 8009418: fa22 f301 lsr.w r3, r2, r1 800941c: 431e orrs r6, r3 800941e: 40cc lsrs r4, r1 8009420: e9c5 6400 strd r6, r4, [r5] 8009424: 2100 movs r1, #0 8009426: e74e b.n 80092c6 <__udivmoddi4+0xa2> 8009428: fbb1 fcf2 udiv ip, r1, r2 800942c: 0c01 lsrs r1, r0, #16 800942e: ea41 410e orr.w r1, r1, lr, lsl #16 8009432: b280 uxth r0, r0 8009434: ea40 4201 orr.w r2, r0, r1, lsl #16 8009438: 463b mov r3, r7 800943a: fbb1 f1f7 udiv r1, r1, r7 800943e: 4638 mov r0, r7 8009440: 463c mov r4, r7 8009442: 46b8 mov r8, r7 8009444: 46be mov lr, r7 8009446: 2620 movs r6, #32 8009448: eba2 0208 sub.w r2, r2, r8 800944c: ea41 410c orr.w r1, r1, ip, lsl #16 8009450: e765 b.n 800931e <__udivmoddi4+0xfa> 8009452: 4601 mov r1, r0 8009454: e717 b.n 8009286 <__udivmoddi4+0x62> 8009456: 4610 mov r0, r2 8009458: e72b b.n 80092b2 <__udivmoddi4+0x8e> 800945a: f1c6 0120 rsb r1, r6, #32 800945e: fa2e fc01 lsr.w ip, lr, r1 8009462: 40b7 lsls r7, r6 8009464: fa0e fe06 lsl.w lr, lr, r6 8009468: fa20 f101 lsr.w r1, r0, r1 800946c: ea41 010e orr.w r1, r1, lr 8009470: ea4f 4e17 mov.w lr, r7, lsr #16 8009474: fbbc f8fe udiv r8, ip, lr 8009478: b2bc uxth r4, r7 800947a: fb0e cc18 mls ip, lr, r8, ip 800947e: fb08 f904 mul.w r9, r8, r4 8009482: 0c0a lsrs r2, r1, #16 8009484: ea42 420c orr.w r2, r2, ip, lsl #16 8009488: 40b0 lsls r0, r6 800948a: 4591 cmp r9, r2 800948c: ea4f 4310 mov.w r3, r0, lsr #16 8009490: b280 uxth r0, r0 8009492: d93e bls.n 8009512 <__udivmoddi4+0x2ee> 8009494: 18ba adds r2, r7, r2 8009496: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 800949a: d201 bcs.n 80094a0 <__udivmoddi4+0x27c> 800949c: 4591 cmp r9, r2 800949e: d81f bhi.n 80094e0 <__udivmoddi4+0x2bc> 80094a0: eba2 0209 sub.w r2, r2, r9 80094a4: fbb2 f9fe udiv r9, r2, lr 80094a8: fb09 f804 mul.w r8, r9, r4 80094ac: fb0e 2a19 mls sl, lr, r9, r2 80094b0: b28a uxth r2, r1 80094b2: ea42 420a orr.w r2, r2, sl, lsl #16 80094b6: 4542 cmp r2, r8 80094b8: d229 bcs.n 800950e <__udivmoddi4+0x2ea> 80094ba: 18ba adds r2, r7, r2 80094bc: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80094c0: d2c2 bcs.n 8009448 <__udivmoddi4+0x224> 80094c2: 4542 cmp r2, r8 80094c4: d2c0 bcs.n 8009448 <__udivmoddi4+0x224> 80094c6: f1a9 0102 sub.w r1, r9, #2 80094ca: 443a add r2, r7 80094cc: e7bc b.n 8009448 <__udivmoddi4+0x224> 80094ce: 45c6 cmp lr, r8 80094d0: d29b bcs.n 800940a <__udivmoddi4+0x1e6> 80094d2: ebb8 0302 subs.w r3, r8, r2 80094d6: eb6c 0c07 sbc.w ip, ip, r7 80094da: 3801 subs r0, #1 80094dc: 46e1 mov r9, ip 80094de: e794 b.n 800940a <__udivmoddi4+0x1e6> 80094e0: eba7 0909 sub.w r9, r7, r9 80094e4: 444a add r2, r9 80094e6: fbb2 f9fe udiv r9, r2, lr 80094ea: f1a8 0c02 sub.w ip, r8, #2 80094ee: fb09 f804 mul.w r8, r9, r4 80094f2: e7db b.n 80094ac <__udivmoddi4+0x288> 80094f4: 4603 mov r3, r0 80094f6: e77d b.n 80093f4 <__udivmoddi4+0x1d0> 80094f8: 46d0 mov r8, sl 80094fa: e765 b.n 80093c8 <__udivmoddi4+0x1a4> 80094fc: 4608 mov r0, r1 80094fe: e6fa b.n 80092f6 <__udivmoddi4+0xd2> 8009500: 443b add r3, r7 8009502: 3a02 subs r2, #2 8009504: e730 b.n 8009368 <__udivmoddi4+0x144> 8009506: f1ac 0c02 sub.w ip, ip, #2 800950a: 443b add r3, r7 800950c: e719 b.n 8009342 <__udivmoddi4+0x11e> 800950e: 4649 mov r1, r9 8009510: e79a b.n 8009448 <__udivmoddi4+0x224> 8009512: eba2 0209 sub.w r2, r2, r9 8009516: fbb2 f9fe udiv r9, r2, lr 800951a: 46c4 mov ip, r8 800951c: fb09 f804 mul.w r8, r9, r4 8009520: e7c4 b.n 80094ac <__udivmoddi4+0x288> 8009522: bf00 nop 08009524 <__aeabi_idiv0>: 8009524: 4770 bx lr 8009526: bf00 nop 08009528 : static volatile uint16_t adc_dma_raw[6]; volatile ADC_ScanData_t adc_data = {0}; static volatile uint8_t adc_scan_data_ready = 0u; void ADC_ScanStart(void) { 8009528: b580 push {r7, lr} 800952a: af00 add r7, sp, #0 if (HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc_dma_raw, 6u) != HAL_OK) 800952c: 2206 movs r2, #6 800952e: 4905 ldr r1, [pc, #20] @ (8009544 ) 8009530: 4805 ldr r0, [pc, #20] @ (8009548 ) 8009532: f004 fe75 bl 800e220 8009536: 4603 mov r3, r0 8009538: 2b00 cmp r3, #0 800953a: d001 beq.n 8009540 { Error_Handler(); 800953c: f001 fb48 bl 800abd0 } } 8009540: bf00 nop 8009542: bd80 pop {r7, pc} 8009544: 20000274 .word 0x20000274 8009548: 20000290 .word 0x20000290 0800954c : ISR_FAST void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { if (hadc->Instance != ADC1) 800954c: 4b0e ldr r3, [pc, #56] @ (8009588 ) 800954e: 6802 ldr r2, [r0, #0] 8009550: 429a cmp r2, r3 8009552: d118 bne.n 8009586 adc_data.cp_raw = adc_dma_raw[1]; adc_data.ntc1_raw = adc_dma_raw[2]; adc_data.ntc2_raw = adc_dma_raw[3]; adc_data.temp_sensor_raw = adc_dma_raw[4]; adc_data.vrefint_raw = adc_dma_raw[5]; adc_scan_data_ready = 1u; 8009554: f04f 0c01 mov.w ip, #1 adc_data.in3_raw = adc_dma_raw[0]; 8009558: 4a0c ldr r2, [pc, #48] @ (800958c ) 800955a: 4b0d ldr r3, [pc, #52] @ (8009590 ) 800955c: 8811 ldrh r1, [r2, #0] adc_scan_data_ready = 1u; 800955e: 480d ldr r0, [pc, #52] @ (8009594 ) adc_data.in3_raw = adc_dma_raw[0]; 8009560: b289 uxth r1, r1 8009562: 8019 strh r1, [r3, #0] adc_data.cp_raw = adc_dma_raw[1]; 8009564: 8851 ldrh r1, [r2, #2] 8009566: b289 uxth r1, r1 8009568: 8059 strh r1, [r3, #2] adc_data.ntc1_raw = adc_dma_raw[2]; 800956a: 8891 ldrh r1, [r2, #4] 800956c: b289 uxth r1, r1 800956e: 8099 strh r1, [r3, #4] adc_data.ntc2_raw = adc_dma_raw[3]; 8009570: 88d1 ldrh r1, [r2, #6] 8009572: b289 uxth r1, r1 8009574: 80d9 strh r1, [r3, #6] adc_data.temp_sensor_raw = adc_dma_raw[4]; 8009576: 8911 ldrh r1, [r2, #8] 8009578: b289 uxth r1, r1 800957a: 8119 strh r1, [r3, #8] adc_data.vrefint_raw = adc_dma_raw[5]; 800957c: 8952 ldrh r2, [r2, #10] 800957e: b292 uxth r2, r2 8009580: 815a strh r2, [r3, #10] adc_scan_data_ready = 1u; 8009582: f880 c000 strb.w ip, [r0] } 8009586: 4770 bx lr 8009588: 40012400 .word 0x40012400 800958c: 20000274 .word 0x20000274 8009590: 20000280 .word 0x20000280 8009594: 2000028c .word 0x2000028c 08009598 : ADC_HandleTypeDef hadc1; DMA_HandleTypeDef hdma_adc1; /* ADC1 init function */ void MX_ADC1_Init(void) { 8009598: b580 push {r7, lr} 800959a: b084 sub sp, #16 800959c: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 800959e: 1d3b adds r3, r7, #4 80095a0: 2200 movs r2, #0 80095a2: 601a str r2, [r3, #0] 80095a4: 605a str r2, [r3, #4] 80095a6: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 80095a8: 4b3c ldr r3, [pc, #240] @ (800969c ) 80095aa: 4a3d ldr r2, [pc, #244] @ (80096a0 ) 80095ac: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 80095ae: 4b3b ldr r3, [pc, #236] @ (800969c ) 80095b0: f44f 7280 mov.w r2, #256 @ 0x100 80095b4: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = DISABLE; 80095b6: 4b39 ldr r3, [pc, #228] @ (800969c ) 80095b8: 2200 movs r2, #0 80095ba: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 80095bc: 4b37 ldr r3, [pc, #220] @ (800969c ) 80095be: 2200 movs r2, #0 80095c0: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T3_TRGO; 80095c2: 4b36 ldr r3, [pc, #216] @ (800969c ) 80095c4: f44f 2200 mov.w r2, #524288 @ 0x80000 80095c8: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80095ca: 4b34 ldr r3, [pc, #208] @ (800969c ) 80095cc: 2200 movs r2, #0 80095ce: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 6; 80095d0: 4b32 ldr r3, [pc, #200] @ (800969c ) 80095d2: 2206 movs r2, #6 80095d4: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 80095d6: 4831 ldr r0, [pc, #196] @ (800969c ) 80095d8: f004 fd4a bl 800e070 80095dc: 4603 mov r3, r0 80095de: 2b00 cmp r3, #0 80095e0: d001 beq.n 80095e6 { Error_Handler(); 80095e2: f001 faf5 bl 800abd0 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 80095e6: 2303 movs r3, #3 80095e8: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 80095ea: 2301 movs r3, #1 80095ec: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_41CYCLES_5; 80095ee: 2304 movs r3, #4 80095f0: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80095f2: 1d3b adds r3, r7, #4 80095f4: 4619 mov r1, r3 80095f6: 4829 ldr r0, [pc, #164] @ (800969c ) 80095f8: f004 ffca bl 800e590 80095fc: 4603 mov r3, r0 80095fe: 2b00 cmp r3, #0 8009600: d001 beq.n 8009606 { Error_Handler(); 8009602: f001 fae5 bl 800abd0 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8009606: 2304 movs r3, #4 8009608: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 800960a: 2302 movs r3, #2 800960c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800960e: 1d3b adds r3, r7, #4 8009610: 4619 mov r1, r3 8009612: 4822 ldr r0, [pc, #136] @ (800969c ) 8009614: f004 ffbc bl 800e590 8009618: 4603 mov r3, r0 800961a: 2b00 cmp r3, #0 800961c: d001 beq.n 8009622 { Error_Handler(); 800961e: f001 fad7 bl 800abd0 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 8009622: 2308 movs r3, #8 8009624: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8009626: 2303 movs r3, #3 8009628: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800962a: 1d3b adds r3, r7, #4 800962c: 4619 mov r1, r3 800962e: 481b ldr r0, [pc, #108] @ (800969c ) 8009630: f004 ffae bl 800e590 8009634: 4603 mov r3, r0 8009636: 2b00 cmp r3, #0 8009638: d001 beq.n 800963e { Error_Handler(); 800963a: f001 fac9 bl 800abd0 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_9; 800963e: 2309 movs r3, #9 8009640: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_4; 8009642: 2304 movs r3, #4 8009644: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8009646: 1d3b adds r3, r7, #4 8009648: 4619 mov r1, r3 800964a: 4814 ldr r0, [pc, #80] @ (800969c ) 800964c: f004 ffa0 bl 800e590 8009650: 4603 mov r3, r0 8009652: 2b00 cmp r3, #0 8009654: d001 beq.n 800965a { Error_Handler(); 8009656: f001 fabb bl 800abd0 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; 800965a: 2310 movs r3, #16 800965c: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_5; 800965e: 2305 movs r3, #5 8009660: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8009662: 1d3b adds r3, r7, #4 8009664: 4619 mov r1, r3 8009666: 480d ldr r0, [pc, #52] @ (800969c ) 8009668: f004 ff92 bl 800e590 800966c: 4603 mov r3, r0 800966e: 2b00 cmp r3, #0 8009670: d001 beq.n 8009676 { Error_Handler(); 8009672: f001 faad bl 800abd0 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; 8009676: 2311 movs r3, #17 8009678: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_6; 800967a: 2306 movs r3, #6 800967c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800967e: 1d3b adds r3, r7, #4 8009680: 4619 mov r1, r3 8009682: 4806 ldr r0, [pc, #24] @ (800969c ) 8009684: f004 ff84 bl 800e590 8009688: 4603 mov r3, r0 800968a: 2b00 cmp r3, #0 800968c: d001 beq.n 8009692 { Error_Handler(); 800968e: f001 fa9f bl 800abd0 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 8009692: bf00 nop 8009694: 3710 adds r7, #16 8009696: 46bd mov sp, r7 8009698: bd80 pop {r7, pc} 800969a: bf00 nop 800969c: 20000290 .word 0x20000290 80096a0: 40012400 .word 0x40012400 080096a4 : void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 80096a4: b580 push {r7, lr} 80096a6: b08a sub sp, #40 @ 0x28 80096a8: af00 add r7, sp, #0 80096aa: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80096ac: f107 0318 add.w r3, r7, #24 80096b0: 2200 movs r2, #0 80096b2: 601a str r2, [r3, #0] 80096b4: 605a str r2, [r3, #4] 80096b6: 609a str r2, [r3, #8] 80096b8: 60da str r2, [r3, #12] if(adcHandle->Instance==ADC1) 80096ba: 687b ldr r3, [r7, #4] 80096bc: 681b ldr r3, [r3, #0] 80096be: 4a38 ldr r2, [pc, #224] @ (80097a0 ) 80096c0: 4293 cmp r3, r2 80096c2: d168 bne.n 8009796 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* ADC1 clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 80096c4: 4b37 ldr r3, [pc, #220] @ (80097a4 ) 80096c6: 699b ldr r3, [r3, #24] 80096c8: 4a36 ldr r2, [pc, #216] @ (80097a4 ) 80096ca: f443 7300 orr.w r3, r3, #512 @ 0x200 80096ce: 6193 str r3, [r2, #24] 80096d0: 4b34 ldr r3, [pc, #208] @ (80097a4 ) 80096d2: 699b ldr r3, [r3, #24] 80096d4: f403 7300 and.w r3, r3, #512 @ 0x200 80096d8: 617b str r3, [r7, #20] 80096da: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 80096dc: 4b31 ldr r3, [pc, #196] @ (80097a4 ) 80096de: 699b ldr r3, [r3, #24] 80096e0: 4a30 ldr r2, [pc, #192] @ (80097a4 ) 80096e2: f043 0304 orr.w r3, r3, #4 80096e6: 6193 str r3, [r2, #24] 80096e8: 4b2e ldr r3, [pc, #184] @ (80097a4 ) 80096ea: 699b ldr r3, [r3, #24] 80096ec: f003 0304 and.w r3, r3, #4 80096f0: 613b str r3, [r7, #16] 80096f2: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 80096f4: 4b2b ldr r3, [pc, #172] @ (80097a4 ) 80096f6: 699b ldr r3, [r3, #24] 80096f8: 4a2a ldr r2, [pc, #168] @ (80097a4 ) 80096fa: f043 0308 orr.w r3, r3, #8 80096fe: 6193 str r3, [r2, #24] 8009700: 4b28 ldr r3, [pc, #160] @ (80097a4 ) 8009702: 699b ldr r3, [r3, #24] 8009704: f003 0308 and.w r3, r3, #8 8009708: 60fb str r3, [r7, #12] 800970a: 68fb ldr r3, [r7, #12] PA3 ------> ADC1_IN3 PA4 ------> ADC1_IN4 PB0 ------> ADC1_IN8 PB1 ------> ADC1_IN9 */ GPIO_InitStruct.Pin = GPIO_PIN_3|CP_ADC_Pin; 800970c: 2318 movs r3, #24 800970e: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009710: 2303 movs r3, #3 8009712: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8009714: f107 0318 add.w r3, r7, #24 8009718: 4619 mov r1, r3 800971a: 4823 ldr r0, [pc, #140] @ (80097a8 ) 800971c: f006 fe9e bl 801045c GPIO_InitStruct.Pin = ADC_NTC1_Pin|ADC_NTC2_Pin; 8009720: 2303 movs r3, #3 8009722: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009724: 2303 movs r3, #3 8009726: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009728: f107 0318 add.w r3, r7, #24 800972c: 4619 mov r1, r3 800972e: 481f ldr r0, [pc, #124] @ (80097ac ) 8009730: f006 fe94 bl 801045c /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel1; 8009734: 4b1e ldr r3, [pc, #120] @ (80097b0 ) 8009736: 4a1f ldr r2, [pc, #124] @ (80097b4 ) 8009738: 601a str r2, [r3, #0] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 800973a: 4b1d ldr r3, [pc, #116] @ (80097b0 ) 800973c: 2200 movs r2, #0 800973e: 605a str r2, [r3, #4] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8009740: 4b1b ldr r3, [pc, #108] @ (80097b0 ) 8009742: 2200 movs r2, #0 8009744: 609a str r2, [r3, #8] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8009746: 4b1a ldr r3, [pc, #104] @ (80097b0 ) 8009748: 2280 movs r2, #128 @ 0x80 800974a: 60da str r2, [r3, #12] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 800974c: 4b18 ldr r3, [pc, #96] @ (80097b0 ) 800974e: f44f 7280 mov.w r2, #256 @ 0x100 8009752: 611a str r2, [r3, #16] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8009754: 4b16 ldr r3, [pc, #88] @ (80097b0 ) 8009756: f44f 6280 mov.w r2, #1024 @ 0x400 800975a: 615a str r2, [r3, #20] hdma_adc1.Init.Mode = DMA_CIRCULAR; 800975c: 4b14 ldr r3, [pc, #80] @ (80097b0 ) 800975e: 2220 movs r2, #32 8009760: 619a str r2, [r3, #24] hdma_adc1.Init.Priority = DMA_PRIORITY_HIGH; 8009762: 4b13 ldr r3, [pc, #76] @ (80097b0 ) 8009764: f44f 5200 mov.w r2, #8192 @ 0x2000 8009768: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 800976a: 4811 ldr r0, [pc, #68] @ (80097b0 ) 800976c: f006 f9f2 bl 800fb54 8009770: 4603 mov r3, r0 8009772: 2b00 cmp r3, #0 8009774: d001 beq.n 800977a { Error_Handler(); 8009776: f001 fa2b bl 800abd0 } __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1); 800977a: 687b ldr r3, [r7, #4] 800977c: 4a0c ldr r2, [pc, #48] @ (80097b0 ) 800977e: 621a str r2, [r3, #32] 8009780: 4a0b ldr r2, [pc, #44] @ (80097b0 ) 8009782: 687b ldr r3, [r7, #4] 8009784: 6253 str r3, [r2, #36] @ 0x24 /* ADC1 interrupt Init */ HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0); 8009786: 2200 movs r2, #0 8009788: 2100 movs r1, #0 800978a: 2012 movs r0, #18 800978c: f006 f981 bl 800fa92 HAL_NVIC_EnableIRQ(ADC1_2_IRQn); 8009790: 2012 movs r0, #18 8009792: f006 f99a bl 800faca /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 8009796: bf00 nop 8009798: 3728 adds r7, #40 @ 0x28 800979a: 46bd mov sp, r7 800979c: bd80 pop {r7, pc} 800979e: bf00 nop 80097a0: 40012400 .word 0x40012400 80097a4: 40021000 .word 0x40021000 80097a8: 40010800 .word 0x40010800 80097ac: 40010c00 .word 0x40010c00 80097b0: 200002c0 .word 0x200002c0 80097b4: 40020008 .word 0x40020008 080097b8 : uint8_t RELAY_State[RELAY_COUNT]; static volatile uint8_t adc_lock = 0; static SMAFilter_t conn_temp_adc_filter[2]; void RELAY_Write(relay_t num, uint8_t state){ 80097b8: b580 push {r7, lr} 80097ba: b082 sub sp, #8 80097bc: af00 add r7, sp, #0 80097be: 4603 mov r3, r0 80097c0: 460a mov r2, r1 80097c2: 71fb strb r3, [r7, #7] 80097c4: 4613 mov r3, r2 80097c6: 71bb strb r3, [r7, #6] switch (num) { 80097c8: 79fb ldrb r3, [r7, #7] 80097ca: 2b07 cmp r3, #7 80097cc: d850 bhi.n 8009870 80097ce: a201 add r2, pc, #4 @ (adr r2, 80097d4 ) 80097d0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80097d4: 080097f5 .word 0x080097f5 80097d8: 08009805 .word 0x08009805 80097dc: 08009815 .word 0x08009815 80097e0: 08009825 .word 0x08009825 80097e4: 08009835 .word 0x08009835 80097e8: 08009845 .word 0x08009845 80097ec: 08009853 .word 0x08009853 80097f0: 08009863 .word 0x08009863 case RELAY_AUX0: HAL_GPIO_WritePin(RELAY1_GPIO_Port, RELAY1_Pin, state); 80097f4: 79bb ldrb r3, [r7, #6] 80097f6: 461a mov r2, r3 80097f8: f44f 7180 mov.w r1, #256 @ 0x100 80097fc: 4821 ldr r0, [pc, #132] @ (8009884 ) 80097fe: f007 f884 bl 801090a break; 8009802: e036 b.n 8009872 case RELAY_AUX1: HAL_GPIO_WritePin(RELAY2_GPIO_Port, RELAY2_Pin, state); 8009804: 79bb ldrb r3, [r7, #6] 8009806: 461a mov r2, r3 8009808: f44f 7100 mov.w r1, #512 @ 0x200 800980c: 481d ldr r0, [pc, #116] @ (8009884 ) 800980e: f007 f87c bl 801090a break; 8009812: e02e b.n 8009872 case RELAY3: HAL_GPIO_WritePin(RELAY3_GPIO_Port, RELAY3_Pin, state); 8009814: 79bb ldrb r3, [r7, #6] 8009816: 461a mov r2, r3 8009818: f44f 6180 mov.w r1, #1024 @ 0x400 800981c: 4819 ldr r0, [pc, #100] @ (8009884 ) 800981e: f007 f874 bl 801090a break; 8009822: e026 b.n 8009872 case RELAY_DC: HAL_GPIO_WritePin(RELAY4_GPIO_Port, RELAY4_Pin, state); 8009824: 79bb ldrb r3, [r7, #6] 8009826: 461a mov r2, r3 8009828: f44f 6100 mov.w r1, #2048 @ 0x800 800982c: 4815 ldr r0, [pc, #84] @ (8009884 ) 800982e: f007 f86c bl 801090a break; 8009832: e01e b.n 8009872 case RELAY_AC: HAL_GPIO_WritePin(RELAY5_GPIO_Port, RELAY5_Pin, state); 8009834: 79bb ldrb r3, [r7, #6] 8009836: 461a mov r2, r3 8009838: f44f 5180 mov.w r1, #4096 @ 0x1000 800983c: 4811 ldr r0, [pc, #68] @ (8009884 ) 800983e: f007 f864 bl 801090a break; 8009842: e016 b.n 8009872 case RELAY_CP: HAL_GPIO_WritePin(RELAY_CP_GPIO_Port, RELAY_CP_Pin, state); 8009844: 79bb ldrb r3, [r7, #6] 8009846: 461a mov r2, r3 8009848: 2108 movs r1, #8 800984a: 480f ldr r0, [pc, #60] @ (8009888 ) 800984c: f007 f85d bl 801090a break; 8009850: e00f b.n 8009872 case RELAY_CC: HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, state); 8009852: 79bb ldrb r3, [r7, #6] 8009854: 461a mov r2, r3 8009856: f44f 4100 mov.w r1, #32768 @ 0x8000 800985a: 480c ldr r0, [pc, #48] @ (800988c ) 800985c: f007 f855 bl 801090a break; 8009860: e007 b.n 8009872 case RELAY_DC1: HAL_GPIO_WritePin(RELAY_DC_GPIO_Port, RELAY_DC_Pin, state); 8009862: 79bb ldrb r3, [r7, #6] 8009864: 461a mov r2, r3 8009866: 2108 movs r1, #8 8009868: 4809 ldr r0, [pc, #36] @ (8009890 ) 800986a: f007 f84e bl 801090a break; 800986e: e000 b.n 8009872 default: break; 8009870: bf00 nop } RELAY_State[num] = state; 8009872: 79fb ldrb r3, [r7, #7] 8009874: 4907 ldr r1, [pc, #28] @ (8009894 ) 8009876: 79ba ldrb r2, [r7, #6] 8009878: 54ca strb r2, [r1, r3] } 800987a: bf00 nop 800987c: 3708 adds r7, #8 800987e: 46bd mov sp, r7 8009880: bd80 pop {r7, pc} 8009882: bf00 nop 8009884: 40011800 .word 0x40011800 8009888: 40011000 .word 0x40011000 800988c: 40010800 .word 0x40010800 8009890: 40011400 .word 0x40011400 8009894: 20000304 .word 0x20000304 08009898 : uint8_t RELAY_Read(relay_t num){ 8009898: b480 push {r7} 800989a: b083 sub sp, #12 800989c: af00 add r7, sp, #0 800989e: 4603 mov r3, r0 80098a0: 71fb strb r3, [r7, #7] return RELAY_State[num]; 80098a2: 79fb ldrb r3, [r7, #7] 80098a4: 4a03 ldr r2, [pc, #12] @ (80098b4 ) 80098a6: 5cd3 ldrb r3, [r2, r3] } 80098a8: 4618 mov r0, r3 80098aa: 370c adds r7, #12 80098ac: 46bd mov sp, r7 80098ae: bc80 pop {r7} 80098b0: 4770 bx lr 80098b2: bf00 nop 80098b4: 20000304 .word 0x20000304 080098b8 : uint8_t IN_ReadInput(inputNum_t input_n){ 80098b8: b580 push {r7, lr} 80098ba: b082 sub sp, #8 80098bc: af00 add r7, sp, #0 80098be: 4603 mov r3, r0 80098c0: 71fb strb r3, [r7, #7] switch(input_n){ 80098c2: 79fb ldrb r3, [r7, #7] 80098c4: 2b06 cmp r3, #6 80098c6: d83b bhi.n 8009940 80098c8: a201 add r2, pc, #4 @ (adr r2, 80098d0 ) 80098ca: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80098ce: bf00 nop 80098d0: 080098ed .word 0x080098ed 80098d4: 080098f9 .word 0x080098f9 80098d8: 08009905 .word 0x08009905 80098dc: 08009911 .word 0x08009911 80098e0: 0800991d .word 0x0800991d 80098e4: 08009929 .word 0x08009929 80098e8: 08009935 .word 0x08009935 case IN_SW0: return HAL_GPIO_ReadPin(IN_SW0_GPIO_Port, IN_SW0_Pin); 80098ec: 2102 movs r1, #2 80098ee: 4817 ldr r0, [pc, #92] @ (800994c ) 80098f0: f006 fff4 bl 80108dc 80098f4: 4603 mov r3, r0 80098f6: e024 b.n 8009942 case IN_SW1: return HAL_GPIO_ReadPin(IN_SW1_GPIO_Port, IN_SW1_Pin); 80098f8: 2104 movs r1, #4 80098fa: 4814 ldr r0, [pc, #80] @ (800994c ) 80098fc: f006 ffee bl 80108dc 8009900: 4603 mov r3, r0 8009902: e01e b.n 8009942 case IN0: return HAL_GPIO_ReadPin(IN0_GPIO_Port, IN0_Pin); 8009904: 2180 movs r1, #128 @ 0x80 8009906: 4812 ldr r0, [pc, #72] @ (8009950 ) 8009908: f006 ffe8 bl 80108dc 800990c: 4603 mov r3, r0 800990e: e018 b.n 8009942 case IN_ESTOP: return HAL_GPIO_ReadPin(IN_ESTOP_GPIO_Port, IN_ESTOP_Pin); 8009910: 2180 movs r1, #128 @ 0x80 8009912: 4810 ldr r0, [pc, #64] @ (8009954 ) 8009914: f006 ffe2 bl 80108dc 8009918: 4603 mov r3, r0 800991a: e012 b.n 8009942 case IN_FB1: return HAL_GPIO_ReadPin(IN_FB1_GPIO_Port, IN_FB1_Pin); 800991c: 2110 movs r1, #16 800991e: 480e ldr r0, [pc, #56] @ (8009958 ) 8009920: f006 ffdc bl 80108dc 8009924: 4603 mov r3, r0 8009926: e00c b.n 8009942 case IN_CONT_FB_DC: return HAL_GPIO_ReadPin(IN_FB2_GPIO_Port, IN_FB2_Pin); 8009928: 2108 movs r1, #8 800992a: 480b ldr r0, [pc, #44] @ (8009958 ) 800992c: f006 ffd6 bl 80108dc 8009930: 4603 mov r3, r0 8009932: e006 b.n 8009942 case ISO_IN: return HAL_GPIO_ReadPin(ISO_IN_GPIO_Port, ISO_IN_Pin); 8009934: 2102 movs r1, #2 8009936: 4806 ldr r0, [pc, #24] @ (8009950 ) 8009938: f006 ffd0 bl 80108dc 800993c: 4603 mov r3, r0 800993e: e000 b.n 8009942 default: return 0; 8009940: 2300 movs r3, #0 } } 8009942: 4618 mov r0, r3 8009944: 3708 adds r7, #8 8009946: 46bd mov sp, r7 8009948: bd80 pop {r7, pc} 800994a: bf00 nop 800994c: 40010800 .word 0x40010800 8009950: 40011800 .word 0x40011800 8009954: 40011400 .word 0x40011400 8009958: 40010c00 .word 0x40010c00 0800995c : // // HAL_ADC_Stop(&hadc1); // stop adc return 0; } void Init_Peripheral(){ 800995c: b580 push {r7, lr} 800995e: af00 add r7, sp, #0 HAL_ADCEx_Calibration_Start(&hadc1); 8009960: 4816 ldr r0, [pc, #88] @ (80099bc ) 8009962: f005 f80f bl 800e984 ADC_ScanStart(); 8009966: f7ff fddf bl 8009528 RELAY_Write(RELAY_AUX0, 0); 800996a: 2100 movs r1, #0 800996c: 2000 movs r0, #0 800996e: f7ff ff23 bl 80097b8 RELAY_Write(RELAY_AUX1, 0); 8009972: 2100 movs r1, #0 8009974: 2001 movs r0, #1 8009976: f7ff ff1f bl 80097b8 RELAY_Write(RELAY3, 0); 800997a: 2100 movs r1, #0 800997c: 2002 movs r0, #2 800997e: f7ff ff1b bl 80097b8 RELAY_Write(RELAY_DC, 0); 8009982: 2100 movs r1, #0 8009984: 2003 movs r0, #3 8009986: f7ff ff17 bl 80097b8 RELAY_Write(RELAY_AC, 0); 800998a: 2100 movs r1, #0 800998c: 2004 movs r0, #4 800998e: f7ff ff13 bl 80097b8 RELAY_Write(RELAY_CP, 0); 8009992: 2100 movs r1, #0 8009994: 2005 movs r0, #5 8009996: f7ff ff0f bl 80097b8 RELAY_Write(RELAY_CC, 0); 800999a: 2100 movs r1, #0 800999c: 2006 movs r0, #6 800999e: f7ff ff0b bl 80097b8 RELAY_Write(RELAY_DC1, 0); 80099a2: 2100 movs r1, #0 80099a4: 2007 movs r0, #7 80099a6: f7ff ff07 bl 80097b8 SMAFilter_Init(&conn_temp_adc_filter[0]); 80099aa: 4805 ldr r0, [pc, #20] @ (80099c0 ) 80099ac: f003 fc4a bl 800d244 SMAFilter_Init(&conn_temp_adc_filter[1]); 80099b0: 4804 ldr r0, [pc, #16] @ (80099c4 ) 80099b2: f003 fc47 bl 800d244 } 80099b6: bf00 nop 80099b8: bd80 pop {r7, pc} 80099ba: bf00 nop 80099bc: 20000290 .word 0x20000290 80099c0: 2000030c .word 0x2000030c 80099c4: 20000334 .word 0x20000334 080099c8 : float pt1000_to_temperature(float resistance) { 80099c8: b590 push {r4, r7, lr} 80099ca: b087 sub sp, #28 80099cc: af00 add r7, sp, #0 80099ce: 6078 str r0, [r7, #4] // Константы для PT1000 const float R0 = 1000.0; // Сопротивление при 0 °C 80099d0: 4b0c ldr r3, [pc, #48] @ (8009a04 ) 80099d2: 617b str r3, [r7, #20] const float C_A = 3.9083E-3f; 80099d4: 4b0c ldr r3, [pc, #48] @ (8009a08 ) 80099d6: 613b str r3, [r7, #16] float temperature = (resistance-R0) / ( R0 * C_A); 80099d8: 6979 ldr r1, [r7, #20] 80099da: 6878 ldr r0, [r7, #4] 80099dc: f7ff f914 bl 8008c08 <__aeabi_fsub> 80099e0: 4603 mov r3, r0 80099e2: 461c mov r4, r3 80099e4: 6939 ldr r1, [r7, #16] 80099e6: 6978 ldr r0, [r7, #20] 80099e8: f7ff fa18 bl 8008e1c <__aeabi_fmul> 80099ec: 4603 mov r3, r0 80099ee: 4619 mov r1, r3 80099f0: 4620 mov r0, r4 80099f2: f7ff fac7 bl 8008f84 <__aeabi_fdiv> 80099f6: 4603 mov r3, r0 80099f8: 60fb str r3, [r7, #12] return temperature; 80099fa: 68fb ldr r3, [r7, #12] } 80099fc: 4618 mov r0, r3 80099fe: 371c adds r7, #28 8009a00: 46bd mov sp, r7 8009a02: bd90 pop {r4, r7, pc} 8009a04: 447a0000 .word 0x447a0000 8009a08: 3b801132 .word 0x3b801132 8009a0c: 00000000 .word 0x00000000 08009a10 : float calculate_NTC_resistance(int adc_value, float Vref, float Vin, float R) { 8009a10: b5b0 push {r4, r5, r7, lr} 8009a12: b086 sub sp, #24 8009a14: af00 add r7, sp, #0 8009a16: 60f8 str r0, [r7, #12] 8009a18: 60b9 str r1, [r7, #8] 8009a1a: 607a str r2, [r7, #4] 8009a1c: 603b str r3, [r7, #0] // Преобразуем значение АЦП в выходное напряжение float Vout = (adc_value / 4095.0) * Vref; 8009a1e: 68f8 ldr r0, [r7, #12] 8009a20: f7fe fd5c bl 80084dc <__aeabi_i2d> 8009a24: a31c add r3, pc, #112 @ (adr r3, 8009a98 ) 8009a26: e9d3 2300 ldrd r2, r3, [r3] 8009a2a: f7fe feeb bl 8008804 <__aeabi_ddiv> 8009a2e: 4602 mov r2, r0 8009a30: 460b mov r3, r1 8009a32: 4614 mov r4, r2 8009a34: 461d mov r5, r3 8009a36: 68b8 ldr r0, [r7, #8] 8009a38: f7fe fd62 bl 8008500 <__aeabi_f2d> 8009a3c: 4602 mov r2, r0 8009a3e: 460b mov r3, r1 8009a40: 4620 mov r0, r4 8009a42: 4629 mov r1, r5 8009a44: f7fe fdb4 bl 80085b0 <__aeabi_dmul> 8009a48: 4602 mov r2, r0 8009a4a: 460b mov r3, r1 8009a4c: 4610 mov r0, r2 8009a4e: 4619 mov r1, r3 8009a50: f7ff f886 bl 8008b60 <__aeabi_d2f> 8009a54: 4603 mov r3, r0 8009a56: 617b str r3, [r7, #20] // Проверяем, чтобы Vout не было равно Vin if (Vout >= Vin) { 8009a58: 6879 ldr r1, [r7, #4] 8009a5a: 6978 ldr r0, [r7, #20] 8009a5c: f7ff fb90 bl 8009180 <__aeabi_fcmpge> 8009a60: 4603 mov r3, r0 8009a62: 2b00 cmp r3, #0 8009a64: d001 beq.n 8009a6a return -1; // Ошибка: Vout не может быть больше или равно Vin 8009a66: 4b0e ldr r3, [pc, #56] @ (8009aa0 ) 8009a68: e010 b.n 8009a8c } // Вычисляем сопротивление термистора float R_NTC = R * (Vout / (Vin - Vout)); 8009a6a: 6979 ldr r1, [r7, #20] 8009a6c: 6878 ldr r0, [r7, #4] 8009a6e: f7ff f8cb bl 8008c08 <__aeabi_fsub> 8009a72: 4603 mov r3, r0 8009a74: 4619 mov r1, r3 8009a76: 6978 ldr r0, [r7, #20] 8009a78: f7ff fa84 bl 8008f84 <__aeabi_fdiv> 8009a7c: 4603 mov r3, r0 8009a7e: 4619 mov r1, r3 8009a80: 6838 ldr r0, [r7, #0] 8009a82: f7ff f9cb bl 8008e1c <__aeabi_fmul> 8009a86: 4603 mov r3, r0 8009a88: 613b str r3, [r7, #16] return R_NTC; 8009a8a: 693b ldr r3, [r7, #16] } 8009a8c: 4618 mov r0, r3 8009a8e: 3718 adds r7, #24 8009a90: 46bd mov sp, r7 8009a92: bdb0 pop {r4, r5, r7, pc} 8009a94: f3af 8000 nop.w 8009a98: 00000000 .word 0x00000000 8009a9c: 40affe00 .word 0x40affe00 8009aa0: bf800000 .word 0xbf800000 08009aa4 : int16_t CONN_ReadTemp(uint8_t ch){ 8009aa4: b580 push {r7, lr} 8009aa6: b088 sub sp, #32 8009aa8: af00 add r7, sp, #0 8009aaa: 4603 mov r3, r0 8009aac: 71fb strb r3, [r7, #7] uint32_t adcValue = 0u; 8009aae: 2300 movs r3, #0 8009ab0: 61fb str r3, [r7, #28] adcValue = ch ? adc_data.ntc2_raw : adc_data.ntc1_raw; 8009ab2: 79fb ldrb r3, [r7, #7] 8009ab4: 2b00 cmp r3, #0 8009ab6: d003 beq.n 8009ac0 8009ab8: 4b1c ldr r3, [pc, #112] @ (8009b2c ) 8009aba: 88db ldrh r3, [r3, #6] 8009abc: b29b uxth r3, r3 8009abe: e002 b.n 8009ac6 8009ac0: 4b1a ldr r3, [pc, #104] @ (8009b2c ) 8009ac2: 889b ldrh r3, [r3, #4] 8009ac4: b29b uxth r3, r3 8009ac6: 61fb str r3, [r7, #28] int32_t adc_filtered = SMAFilter_Update(&conn_temp_adc_filter[ch ? 1u : 0u], (int32_t)adcValue); 8009ac8: 79fb ldrb r3, [r7, #7] 8009aca: 2b00 cmp r3, #0 8009acc: d001 beq.n 8009ad2 8009ace: 2201 movs r2, #1 8009ad0: e000 b.n 8009ad4 8009ad2: 2200 movs r2, #0 8009ad4: 4613 mov r3, r2 8009ad6: 009b lsls r3, r3, #2 8009ad8: 4413 add r3, r2 8009ada: 00db lsls r3, r3, #3 8009adc: 4a14 ldr r2, [pc, #80] @ (8009b30 ) 8009ade: 4413 add r3, r2 8009ae0: 69fa ldr r2, [r7, #28] 8009ae2: 4611 mov r1, r2 8009ae4: 4618 mov r0, r3 8009ae6: f003 fbd2 bl 800d28e 8009aea: 61b8 str r0, [r7, #24] if((uint32_t)adc_filtered > 4000u) { 8009aec: 69bb ldr r3, [r7, #24] 8009aee: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 8009af2: d901 bls.n 8009af8 return 20; //Термодатчик не подключен 8009af4: 2314 movs r3, #20 8009af6: e015 b.n 8009b24 } // int adc_value = 2048; // Пример значения АЦП float Vref = 3.3; // Напряжение опорное 8009af8: 4b0e ldr r3, [pc, #56] @ (8009b34 ) 8009afa: 617b str r3, [r7, #20] float Vin = 5.0; // Входное напряжение 8009afc: 4b0e ldr r3, [pc, #56] @ (8009b38 ) 8009afe: 613b str r3, [r7, #16] float R = 1000; // Сопротивление резистора в Омах 8009b00: 4b0e ldr r3, [pc, #56] @ (8009b3c ) 8009b02: 60fb str r3, [r7, #12] float temp = pt1000_to_temperature(calculate_NTC_resistance((int)adc_filtered, Vref, Vin, R)); 8009b04: 68fb ldr r3, [r7, #12] 8009b06: 693a ldr r2, [r7, #16] 8009b08: 6979 ldr r1, [r7, #20] 8009b0a: 69b8 ldr r0, [r7, #24] 8009b0c: f7ff ff80 bl 8009a10 8009b10: 4603 mov r3, r0 8009b12: 4618 mov r0, r3 8009b14: f7ff ff58 bl 80099c8 8009b18: 60b8 str r0, [r7, #8] return (int16_t)temp; 8009b1a: 68b8 ldr r0, [r7, #8] 8009b1c: f7ff fb44 bl 80091a8 <__aeabi_f2iz> 8009b20: 4603 mov r3, r0 8009b22: b21b sxth r3, r3 } 8009b24: 4618 mov r0, r3 8009b26: 3720 adds r7, #32 8009b28: 46bd mov sp, r7 8009b2a: bd80 pop {r7, pc} 8009b2c: 20000280 .word 0x20000280 8009b30: 2000030c .word 0x2000030c 8009b34: 40533333 .word 0x40533333 8009b38: 40a00000 .word 0x40a00000 8009b3c: 447a0000 .word 0x447a0000 08009b40 : CAN_HandleTypeDef hcan1; CAN_HandleTypeDef hcan2; /* CAN1 init function */ void MX_CAN1_Init(void) { 8009b40: b580 push {r7, lr} 8009b42: af00 add r7, sp, #0 /* USER CODE END CAN1_Init 0 */ /* USER CODE BEGIN CAN1_Init 1 */ /* USER CODE END CAN1_Init 1 */ hcan1.Instance = CAN1; 8009b44: 4b17 ldr r3, [pc, #92] @ (8009ba4 ) 8009b46: 4a18 ldr r2, [pc, #96] @ (8009ba8 ) 8009b48: 601a str r2, [r3, #0] hcan1.Init.Prescaler = 8; 8009b4a: 4b16 ldr r3, [pc, #88] @ (8009ba4 ) 8009b4c: 2208 movs r2, #8 8009b4e: 605a str r2, [r3, #4] hcan1.Init.Mode = CAN_MODE_NORMAL; 8009b50: 4b14 ldr r3, [pc, #80] @ (8009ba4 ) 8009b52: 2200 movs r2, #0 8009b54: 609a str r2, [r3, #8] hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; 8009b56: 4b13 ldr r3, [pc, #76] @ (8009ba4 ) 8009b58: 2200 movs r2, #0 8009b5a: 60da str r2, [r3, #12] hcan1.Init.TimeSeg1 = CAN_BS1_15TQ; 8009b5c: 4b11 ldr r3, [pc, #68] @ (8009ba4 ) 8009b5e: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009b62: 611a str r2, [r3, #16] hcan1.Init.TimeSeg2 = CAN_BS2_2TQ; 8009b64: 4b0f ldr r3, [pc, #60] @ (8009ba4 ) 8009b66: f44f 1280 mov.w r2, #1048576 @ 0x100000 8009b6a: 615a str r2, [r3, #20] hcan1.Init.TimeTriggeredMode = DISABLE; 8009b6c: 4b0d ldr r3, [pc, #52] @ (8009ba4 ) 8009b6e: 2200 movs r2, #0 8009b70: 761a strb r2, [r3, #24] hcan1.Init.AutoBusOff = ENABLE; 8009b72: 4b0c ldr r3, [pc, #48] @ (8009ba4 ) 8009b74: 2201 movs r2, #1 8009b76: 765a strb r2, [r3, #25] hcan1.Init.AutoWakeUp = ENABLE; 8009b78: 4b0a ldr r3, [pc, #40] @ (8009ba4 ) 8009b7a: 2201 movs r2, #1 8009b7c: 769a strb r2, [r3, #26] hcan1.Init.AutoRetransmission = ENABLE; 8009b7e: 4b09 ldr r3, [pc, #36] @ (8009ba4 ) 8009b80: 2201 movs r2, #1 8009b82: 76da strb r2, [r3, #27] hcan1.Init.ReceiveFifoLocked = DISABLE; 8009b84: 4b07 ldr r3, [pc, #28] @ (8009ba4 ) 8009b86: 2200 movs r2, #0 8009b88: 771a strb r2, [r3, #28] hcan1.Init.TransmitFifoPriority = ENABLE; 8009b8a: 4b06 ldr r3, [pc, #24] @ (8009ba4 ) 8009b8c: 2201 movs r2, #1 8009b8e: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan1) != HAL_OK) 8009b90: 4804 ldr r0, [pc, #16] @ (8009ba4 ) 8009b92: f004 ffae bl 800eaf2 8009b96: 4603 mov r3, r0 8009b98: 2b00 cmp r3, #0 8009b9a: d001 beq.n 8009ba0 { Error_Handler(); 8009b9c: f001 f818 bl 800abd0 } /* USER CODE BEGIN CAN1_Init 2 */ /* USER CODE END CAN1_Init 2 */ } 8009ba0: bf00 nop 8009ba2: bd80 pop {r7, pc} 8009ba4: 2000035c .word 0x2000035c 8009ba8: 40006400 .word 0x40006400 08009bac : /* CAN2 init function */ void MX_CAN2_Init(void) { 8009bac: b580 push {r7, lr} 8009bae: af00 add r7, sp, #0 /* USER CODE END CAN2_Init 0 */ /* USER CODE BEGIN CAN2_Init 1 */ /* USER CODE END CAN2_Init 1 */ hcan2.Instance = CAN2; 8009bb0: 4b17 ldr r3, [pc, #92] @ (8009c10 ) 8009bb2: 4a18 ldr r2, [pc, #96] @ (8009c14 ) 8009bb4: 601a str r2, [r3, #0] hcan2.Init.Prescaler = 16; 8009bb6: 4b16 ldr r3, [pc, #88] @ (8009c10 ) 8009bb8: 2210 movs r2, #16 8009bba: 605a str r2, [r3, #4] hcan2.Init.Mode = CAN_MODE_NORMAL; 8009bbc: 4b14 ldr r3, [pc, #80] @ (8009c10 ) 8009bbe: 2200 movs r2, #0 8009bc0: 609a str r2, [r3, #8] hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; 8009bc2: 4b13 ldr r3, [pc, #76] @ (8009c10 ) 8009bc4: 2200 movs r2, #0 8009bc6: 60da str r2, [r3, #12] hcan2.Init.TimeSeg1 = CAN_BS1_15TQ; 8009bc8: 4b11 ldr r3, [pc, #68] @ (8009c10 ) 8009bca: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009bce: 611a str r2, [r3, #16] hcan2.Init.TimeSeg2 = CAN_BS2_2TQ; 8009bd0: 4b0f ldr r3, [pc, #60] @ (8009c10 ) 8009bd2: f44f 1280 mov.w r2, #1048576 @ 0x100000 8009bd6: 615a str r2, [r3, #20] hcan2.Init.TimeTriggeredMode = DISABLE; 8009bd8: 4b0d ldr r3, [pc, #52] @ (8009c10 ) 8009bda: 2200 movs r2, #0 8009bdc: 761a strb r2, [r3, #24] hcan2.Init.AutoBusOff = ENABLE; 8009bde: 4b0c ldr r3, [pc, #48] @ (8009c10 ) 8009be0: 2201 movs r2, #1 8009be2: 765a strb r2, [r3, #25] hcan2.Init.AutoWakeUp = ENABLE; 8009be4: 4b0a ldr r3, [pc, #40] @ (8009c10 ) 8009be6: 2201 movs r2, #1 8009be8: 769a strb r2, [r3, #26] hcan2.Init.AutoRetransmission = ENABLE; 8009bea: 4b09 ldr r3, [pc, #36] @ (8009c10 ) 8009bec: 2201 movs r2, #1 8009bee: 76da strb r2, [r3, #27] hcan2.Init.ReceiveFifoLocked = DISABLE; 8009bf0: 4b07 ldr r3, [pc, #28] @ (8009c10 ) 8009bf2: 2200 movs r2, #0 8009bf4: 771a strb r2, [r3, #28] hcan2.Init.TransmitFifoPriority = ENABLE; 8009bf6: 4b06 ldr r3, [pc, #24] @ (8009c10 ) 8009bf8: 2201 movs r2, #1 8009bfa: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan2) != HAL_OK) 8009bfc: 4804 ldr r0, [pc, #16] @ (8009c10 ) 8009bfe: f004 ff78 bl 800eaf2 8009c02: 4603 mov r3, r0 8009c04: 2b00 cmp r3, #0 8009c06: d001 beq.n 8009c0c { Error_Handler(); 8009c08: f000 ffe2 bl 800abd0 } /* USER CODE BEGIN CAN2_Init 2 */ /* USER CODE END CAN2_Init 2 */ } 8009c0c: bf00 nop 8009c0e: bd80 pop {r7, pc} 8009c10: 20000384 .word 0x20000384 8009c14: 40006800 .word 0x40006800 08009c18 : static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0; void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) { 8009c18: b580 push {r7, lr} 8009c1a: b08e sub sp, #56 @ 0x38 8009c1c: af00 add r7, sp, #0 8009c1e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8009c20: f107 0320 add.w r3, r7, #32 8009c24: 2200 movs r2, #0 8009c26: 601a str r2, [r3, #0] 8009c28: 605a str r2, [r3, #4] 8009c2a: 609a str r2, [r3, #8] 8009c2c: 60da str r2, [r3, #12] if(canHandle->Instance==CAN1) 8009c2e: 687b ldr r3, [r7, #4] 8009c30: 681b ldr r3, [r3, #0] 8009c32: 4a61 ldr r2, [pc, #388] @ (8009db8 ) 8009c34: 4293 cmp r3, r2 8009c36: d153 bne.n 8009ce0 { /* USER CODE BEGIN CAN1_MspInit 0 */ /* USER CODE END CAN1_MspInit 0 */ /* CAN1 clock enable */ HAL_RCC_CAN1_CLK_ENABLED++; 8009c38: 4b60 ldr r3, [pc, #384] @ (8009dbc ) 8009c3a: 681b ldr r3, [r3, #0] 8009c3c: 3301 adds r3, #1 8009c3e: 4a5f ldr r2, [pc, #380] @ (8009dbc ) 8009c40: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009c42: 4b5e ldr r3, [pc, #376] @ (8009dbc ) 8009c44: 681b ldr r3, [r3, #0] 8009c46: 2b01 cmp r3, #1 8009c48: d10b bne.n 8009c62 __HAL_RCC_CAN1_CLK_ENABLE(); 8009c4a: 4b5d ldr r3, [pc, #372] @ (8009dc0 ) 8009c4c: 69db ldr r3, [r3, #28] 8009c4e: 4a5c ldr r2, [pc, #368] @ (8009dc0 ) 8009c50: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009c54: 61d3 str r3, [r2, #28] 8009c56: 4b5a ldr r3, [pc, #360] @ (8009dc0 ) 8009c58: 69db ldr r3, [r3, #28] 8009c5a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009c5e: 61fb str r3, [r7, #28] 8009c60: 69fb ldr r3, [r7, #28] } __HAL_RCC_GPIOD_CLK_ENABLE(); 8009c62: 4b57 ldr r3, [pc, #348] @ (8009dc0 ) 8009c64: 699b ldr r3, [r3, #24] 8009c66: 4a56 ldr r2, [pc, #344] @ (8009dc0 ) 8009c68: f043 0320 orr.w r3, r3, #32 8009c6c: 6193 str r3, [r2, #24] 8009c6e: 4b54 ldr r3, [pc, #336] @ (8009dc0 ) 8009c70: 699b ldr r3, [r3, #24] 8009c72: f003 0320 and.w r3, r3, #32 8009c76: 61bb str r3, [r7, #24] 8009c78: 69bb ldr r3, [r7, #24] /**CAN1 GPIO Configuration PD0 ------> CAN1_RX PD1 ------> CAN1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0; 8009c7a: 2301 movs r3, #1 8009c7c: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009c7e: 2300 movs r3, #0 8009c80: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009c82: 2300 movs r3, #0 8009c84: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009c86: f107 0320 add.w r3, r7, #32 8009c8a: 4619 mov r1, r3 8009c8c: 484d ldr r0, [pc, #308] @ (8009dc4 ) 8009c8e: f006 fbe5 bl 801045c GPIO_InitStruct.Pin = GPIO_PIN_1; 8009c92: 2302 movs r3, #2 8009c94: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009c96: 2302 movs r3, #2 8009c98: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009c9a: 2303 movs r3, #3 8009c9c: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009c9e: f107 0320 add.w r3, r7, #32 8009ca2: 4619 mov r1, r3 8009ca4: 4847 ldr r0, [pc, #284] @ (8009dc4 ) 8009ca6: f006 fbd9 bl 801045c __HAL_AFIO_REMAP_CAN1_3(); 8009caa: 4b47 ldr r3, [pc, #284] @ (8009dc8 ) 8009cac: 685b ldr r3, [r3, #4] 8009cae: 633b str r3, [r7, #48] @ 0x30 8009cb0: 6b3b ldr r3, [r7, #48] @ 0x30 8009cb2: f423 43c0 bic.w r3, r3, #24576 @ 0x6000 8009cb6: 633b str r3, [r7, #48] @ 0x30 8009cb8: 6b3b ldr r3, [r7, #48] @ 0x30 8009cba: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009cbe: 633b str r3, [r7, #48] @ 0x30 8009cc0: 6b3b ldr r3, [r7, #48] @ 0x30 8009cc2: f443 43c0 orr.w r3, r3, #24576 @ 0x6000 8009cc6: 633b str r3, [r7, #48] @ 0x30 8009cc8: 4a3f ldr r2, [pc, #252] @ (8009dc8 ) 8009cca: 6b3b ldr r3, [r7, #48] @ 0x30 8009ccc: 6053 str r3, [r2, #4] /* CAN1 interrupt Init */ HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 0, 0); 8009cce: 2200 movs r2, #0 8009cd0: 2100 movs r1, #0 8009cd2: 2014 movs r0, #20 8009cd4: f005 fedd bl 800fa92 HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn); 8009cd8: 2014 movs r0, #20 8009cda: f005 fef6 bl 800faca HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); /* USER CODE BEGIN CAN2_MspInit 1 */ /* USER CODE END CAN2_MspInit 1 */ } } 8009cde: e067 b.n 8009db0 else if(canHandle->Instance==CAN2) 8009ce0: 687b ldr r3, [r7, #4] 8009ce2: 681b ldr r3, [r3, #0] 8009ce4: 4a39 ldr r2, [pc, #228] @ (8009dcc ) 8009ce6: 4293 cmp r3, r2 8009ce8: d162 bne.n 8009db0 __HAL_RCC_CAN2_CLK_ENABLE(); 8009cea: 4b35 ldr r3, [pc, #212] @ (8009dc0 ) 8009cec: 69db ldr r3, [r3, #28] 8009cee: 4a34 ldr r2, [pc, #208] @ (8009dc0 ) 8009cf0: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 8009cf4: 61d3 str r3, [r2, #28] 8009cf6: 4b32 ldr r3, [pc, #200] @ (8009dc0 ) 8009cf8: 69db ldr r3, [r3, #28] 8009cfa: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8009cfe: 617b str r3, [r7, #20] 8009d00: 697b ldr r3, [r7, #20] HAL_RCC_CAN1_CLK_ENABLED++; 8009d02: 4b2e ldr r3, [pc, #184] @ (8009dbc ) 8009d04: 681b ldr r3, [r3, #0] 8009d06: 3301 adds r3, #1 8009d08: 4a2c ldr r2, [pc, #176] @ (8009dbc ) 8009d0a: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009d0c: 4b2b ldr r3, [pc, #172] @ (8009dbc ) 8009d0e: 681b ldr r3, [r3, #0] 8009d10: 2b01 cmp r3, #1 8009d12: d10b bne.n 8009d2c __HAL_RCC_CAN1_CLK_ENABLE(); 8009d14: 4b2a ldr r3, [pc, #168] @ (8009dc0 ) 8009d16: 69db ldr r3, [r3, #28] 8009d18: 4a29 ldr r2, [pc, #164] @ (8009dc0 ) 8009d1a: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009d1e: 61d3 str r3, [r2, #28] 8009d20: 4b27 ldr r3, [pc, #156] @ (8009dc0 ) 8009d22: 69db ldr r3, [r3, #28] 8009d24: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009d28: 613b str r3, [r7, #16] 8009d2a: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8009d2c: 4b24 ldr r3, [pc, #144] @ (8009dc0 ) 8009d2e: 699b ldr r3, [r3, #24] 8009d30: 4a23 ldr r2, [pc, #140] @ (8009dc0 ) 8009d32: f043 0308 orr.w r3, r3, #8 8009d36: 6193 str r3, [r2, #24] 8009d38: 4b21 ldr r3, [pc, #132] @ (8009dc0 ) 8009d3a: 699b ldr r3, [r3, #24] 8009d3c: f003 0308 and.w r3, r3, #8 8009d40: 60fb str r3, [r7, #12] 8009d42: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_5; 8009d44: 2320 movs r3, #32 8009d46: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009d48: 2300 movs r3, #0 8009d4a: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009d4c: 2300 movs r3, #0 8009d4e: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009d50: f107 0320 add.w r3, r7, #32 8009d54: 4619 mov r1, r3 8009d56: 481e ldr r0, [pc, #120] @ (8009dd0 ) 8009d58: f006 fb80 bl 801045c GPIO_InitStruct.Pin = GPIO_PIN_6; 8009d5c: 2340 movs r3, #64 @ 0x40 8009d5e: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009d60: 2302 movs r3, #2 8009d62: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009d64: 2303 movs r3, #3 8009d66: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009d68: f107 0320 add.w r3, r7, #32 8009d6c: 4619 mov r1, r3 8009d6e: 4818 ldr r0, [pc, #96] @ (8009dd0 ) 8009d70: f006 fb74 bl 801045c __HAL_AFIO_REMAP_CAN2_ENABLE(); 8009d74: 4b14 ldr r3, [pc, #80] @ (8009dc8 ) 8009d76: 685b ldr r3, [r3, #4] 8009d78: 637b str r3, [r7, #52] @ 0x34 8009d7a: 6b7b ldr r3, [r7, #52] @ 0x34 8009d7c: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009d80: 637b str r3, [r7, #52] @ 0x34 8009d82: 6b7b ldr r3, [r7, #52] @ 0x34 8009d84: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8009d88: 637b str r3, [r7, #52] @ 0x34 8009d8a: 4a0f ldr r2, [pc, #60] @ (8009dc8 ) 8009d8c: 6b7b ldr r3, [r7, #52] @ 0x34 8009d8e: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(CAN2_TX_IRQn, 0, 0); 8009d90: 2200 movs r2, #0 8009d92: 2100 movs r1, #0 8009d94: 203f movs r0, #63 @ 0x3f 8009d96: f005 fe7c bl 800fa92 HAL_NVIC_EnableIRQ(CAN2_TX_IRQn); 8009d9a: 203f movs r0, #63 @ 0x3f 8009d9c: f005 fe95 bl 800faca HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 0, 0); 8009da0: 2200 movs r2, #0 8009da2: 2100 movs r1, #0 8009da4: 2041 movs r0, #65 @ 0x41 8009da6: f005 fe74 bl 800fa92 HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); 8009daa: 2041 movs r0, #65 @ 0x41 8009dac: f005 fe8d bl 800faca } 8009db0: bf00 nop 8009db2: 3738 adds r7, #56 @ 0x38 8009db4: 46bd mov sp, r7 8009db6: bd80 pop {r7, pc} 8009db8: 40006400 .word 0x40006400 8009dbc: 200003ac .word 0x200003ac 8009dc0: 40021000 .word 0x40021000 8009dc4: 40011400 .word 0x40011400 8009dc8: 40010000 .word 0x40010000 8009dcc: 40006800 .word 0x40006800 8009dd0: 40010c00 .word 0x40010c00 08009dd4 : ChargingConnector_t CONN; CONN_State_t connectorState; extern uint8_t config_initialized; void CONN_Init(){ 8009dd4: b480 push {r7} 8009dd6: af00 add r7, sp, #0 CONN.connControl = CMD_NONE; 8009dd8: 4b08 ldr r3, [pc, #32] @ (8009dfc ) 8009dda: 2200 movs r2, #0 8009ddc: 701a strb r2, [r3, #0] CONN.connState = Unknown; 8009dde: 4b07 ldr r3, [pc, #28] @ (8009dfc ) 8009de0: 2200 movs r2, #0 8009de2: 705a strb r2, [r3, #1] CONN.RequestedVoltage = PSU_MIN_VOLTAGE; 8009de4: 4b05 ldr r3, [pc, #20] @ (8009dfc ) 8009de6: 2200 movs r2, #0 8009de8: f062 0269 orn r2, r2, #105 @ 0x69 8009dec: 73da strb r2, [r3, #15] 8009dee: 2200 movs r2, #0 8009df0: 741a strb r2, [r3, #16] } 8009df2: bf00 nop 8009df4: 46bd mov sp, r7 8009df6: bc80 pop {r7} 8009df8: 4770 bx lr 8009dfa: bf00 nop 8009dfc: 200003b0 .word 0x200003b0 08009e00 : void CONN_Loop(){ 8009e00: b580 push {r7, lr} 8009e02: af00 add r7, sp, #0 static CONN_State_t last_connState = Unknown; if(last_connState != CONN.connState){ 8009e04: 4b1a ldr r3, [pc, #104] @ (8009e70 ) 8009e06: 785a ldrb r2, [r3, #1] 8009e08: 4b1a ldr r3, [pc, #104] @ (8009e74 ) 8009e0a: 781b ldrb r3, [r3, #0] 8009e0c: 429a cmp r2, r3 8009e0e: d006 beq.n 8009e1e last_connState = CONN.connState; 8009e10: 4b17 ldr r3, [pc, #92] @ (8009e70 ) 8009e12: 785a ldrb r2, [r3, #1] 8009e14: 4b17 ldr r3, [pc, #92] @ (8009e74 ) 8009e16: 701a strb r2, [r3, #0] CONN.connControl = CMD_NONE; 8009e18: 4b15 ldr r3, [pc, #84] @ (8009e70 ) 8009e1a: 2200 movs r2, #0 8009e1c: 701a strb r2, [r3, #0] } if(PSU0.cont_fault){ 8009e1e: 4b16 ldr r3, [pc, #88] @ (8009e78 ) 8009e20: 7b1b ldrb r3, [r3, #12] 8009e22: 2b00 cmp r3, #0 8009e24: d003 beq.n 8009e2e CONN.chargingError = CONN_ERR_CONTACTOR; 8009e26: 4b12 ldr r3, [pc, #72] @ (8009e70 ) 8009e28: 2207 movs r2, #7 8009e2a: 775a strb r2, [r3, #29] 8009e2c: e00e b.n 8009e4c } else if(PSU0.psu_fault){ 8009e2e: 4b12 ldr r3, [pc, #72] @ (8009e78 ) 8009e30: 7b5b ldrb r3, [r3, #13] 8009e32: 2b00 cmp r3, #0 8009e34: d003 beq.n 8009e3e CONN.chargingError = CONN_ERR_PSU_FAULT; 8009e36: 4b0e ldr r3, [pc, #56] @ (8009e70 ) 8009e38: 220a movs r2, #10 8009e3a: 775a strb r2, [r3, #29] 8009e3c: e006 b.n 8009e4c // } else if(!CTRL.ac_ok) { // CONN.chargingError = CONN_ERR_AC_FAULT; // } else }else if (CONN.EvConnected == 0){ 8009e3e: 4b0c ldr r3, [pc, #48] @ (8009e70 ) 8009e40: 7f9b ldrb r3, [r3, #30] 8009e42: 2b00 cmp r3, #0 8009e44: d102 bne.n 8009e4c CONN.chargingError = CONN_NO_ERROR; 8009e46: 4b0a ldr r3, [pc, #40] @ (8009e70 ) 8009e48: 2200 movs r2, #0 8009e4a: 775a strb r2, [r3, #29] } if(ED_TraceWarning(CONN.chargingError, 0)) printf("CONN%d Error: %d\n", 0, CONN.chargingError); 8009e4c: 4b08 ldr r3, [pc, #32] @ (8009e70 ) 8009e4e: 7f5b ldrb r3, [r3, #29] 8009e50: 2100 movs r1, #0 8009e52: 4618 mov r0, r3 8009e54: f000 fcfc bl 800a850 8009e58: 4603 mov r3, r0 8009e5a: 2b00 cmp r3, #0 8009e5c: d006 beq.n 8009e6c 8009e5e: 4b04 ldr r3, [pc, #16] @ (8009e70 ) 8009e60: 7f5b ldrb r3, [r3, #29] 8009e62: 461a mov r2, r3 8009e64: 2100 movs r1, #0 8009e66: 4805 ldr r0, [pc, #20] @ (8009e7c ) 8009e68: f00a fc56 bl 8014718 } 8009e6c: bf00 nop 8009e6e: bd80 pop {r7, pc} 8009e70: 200003b0 .word 0x200003b0 8009e74: 200003d0 .word 0x200003d0 8009e78: 20000904 .word 0x20000904 8009e7c: 08016990 .word 0x08016990 08009e80 : void CONN_Task(){ 8009e80: b480 push {r7} 8009e82: af00 add r7, sp, #0 /* CCS state machine is handled in serial.c. * Keep this task lightweight for scheduler compatibility. */ return; 8009e84: bf00 nop } 8009e86: 46bd mov sp, r7 8009e88: bc80 pop {r7} 8009e8a: 4770 bx lr 08009e8c : void CONN_SetState(CONN_State_t state){ 8009e8c: b580 push {r7, lr} 8009e8e: b082 sub sp, #8 8009e90: af00 add r7, sp, #0 8009e92: 4603 mov r3, r0 8009e94: 71fb strb r3, [r7, #7] if (connectorState == state) { 8009e96: 4b41 ldr r3, [pc, #260] @ (8009f9c ) 8009e98: 781b ldrb r3, [r3, #0] 8009e9a: 79fa ldrb r2, [r7, #7] 8009e9c: 429a cmp r2, r3 8009e9e: d103 bne.n 8009ea8 CONN.connState = state; 8009ea0: 4a3f ldr r2, [pc, #252] @ (8009fa0 ) 8009ea2: 79fb ldrb r3, [r7, #7] 8009ea4: 7053 strb r3, [r2, #1] return; 8009ea6: e075 b.n 8009f94 } connectorState = state; 8009ea8: 4a3c ldr r2, [pc, #240] @ (8009f9c ) 8009eaa: 79fb ldrb r3, [r7, #7] 8009eac: 7013 strb r3, [r2, #0] if(connectorState == Unknown) log_printf(LOG_INFO, "Connector: Unknown\n"); 8009eae: 4b3b ldr r3, [pc, #236] @ (8009f9c ) 8009eb0: 781b ldrb r3, [r3, #0] 8009eb2: 2b00 cmp r3, #0 8009eb4: d103 bne.n 8009ebe 8009eb6: 493b ldr r1, [pc, #236] @ (8009fa4 ) 8009eb8: 2007 movs r0, #7 8009eba: f000 fb11 bl 800a4e0 if(connectorState == Unplugged) log_printf(LOG_INFO, "Connector: Unplugged\n"); 8009ebe: 4b37 ldr r3, [pc, #220] @ (8009f9c ) 8009ec0: 781b ldrb r3, [r3, #0] 8009ec2: 2b01 cmp r3, #1 8009ec4: d103 bne.n 8009ece 8009ec6: 4938 ldr r1, [pc, #224] @ (8009fa8 ) 8009ec8: 2007 movs r0, #7 8009eca: f000 fb09 bl 800a4e0 if(connectorState == Disabled) log_printf(LOG_INFO, "Connector: Disabled\n"); 8009ece: 4b33 ldr r3, [pc, #204] @ (8009f9c ) 8009ed0: 781b ldrb r3, [r3, #0] 8009ed2: 2b02 cmp r3, #2 8009ed4: d103 bne.n 8009ede 8009ed6: 4935 ldr r1, [pc, #212] @ (8009fac ) 8009ed8: 2007 movs r0, #7 8009eda: f000 fb01 bl 800a4e0 if(connectorState == Preparing) log_printf(LOG_INFO, "Connector: Preparing\n"); 8009ede: 4b2f ldr r3, [pc, #188] @ (8009f9c ) 8009ee0: 781b ldrb r3, [r3, #0] 8009ee2: 2b03 cmp r3, #3 8009ee4: d103 bne.n 8009eee 8009ee6: 4932 ldr r1, [pc, #200] @ (8009fb0 ) 8009ee8: 2007 movs r0, #7 8009eea: f000 faf9 bl 800a4e0 if(connectorState == AuthRequired) log_printf(LOG_INFO, "Connector: AuthRequired\n"); 8009eee: 4b2b ldr r3, [pc, #172] @ (8009f9c ) 8009ef0: 781b ldrb r3, [r3, #0] 8009ef2: 2b04 cmp r3, #4 8009ef4: d103 bne.n 8009efe 8009ef6: 492f ldr r1, [pc, #188] @ (8009fb4 ) 8009ef8: 2007 movs r0, #7 8009efa: f000 faf1 bl 800a4e0 if(connectorState == WaitingForEnergy) log_printf(LOG_INFO, "Connector: WaitingForEnergy\n"); 8009efe: 4b27 ldr r3, [pc, #156] @ (8009f9c ) 8009f00: 781b ldrb r3, [r3, #0] 8009f02: 2b05 cmp r3, #5 8009f04: d103 bne.n 8009f0e 8009f06: 492c ldr r1, [pc, #176] @ (8009fb8 ) 8009f08: 2007 movs r0, #7 8009f0a: f000 fae9 bl 800a4e0 if(connectorState == ChargingPausedEV) log_printf(LOG_INFO, "Connector: ChargingPausedEV\n"); 8009f0e: 4b23 ldr r3, [pc, #140] @ (8009f9c ) 8009f10: 781b ldrb r3, [r3, #0] 8009f12: 2b06 cmp r3, #6 8009f14: d103 bne.n 8009f1e 8009f16: 4929 ldr r1, [pc, #164] @ (8009fbc ) 8009f18: 2007 movs r0, #7 8009f1a: f000 fae1 bl 800a4e0 if(connectorState == ChargingPausedEVSE) log_printf(LOG_INFO, "Connector: ChargingPausedEVSE\n"); 8009f1e: 4b1f ldr r3, [pc, #124] @ (8009f9c ) 8009f20: 781b ldrb r3, [r3, #0] 8009f22: 2b07 cmp r3, #7 8009f24: d103 bne.n 8009f2e 8009f26: 4926 ldr r1, [pc, #152] @ (8009fc0 ) 8009f28: 2007 movs r0, #7 8009f2a: f000 fad9 bl 800a4e0 if(connectorState == Charging) log_printf(LOG_INFO, "Connector: Charging\n"); 8009f2e: 4b1b ldr r3, [pc, #108] @ (8009f9c ) 8009f30: 781b ldrb r3, [r3, #0] 8009f32: 2b08 cmp r3, #8 8009f34: d103 bne.n 8009f3e 8009f36: 4923 ldr r1, [pc, #140] @ (8009fc4 ) 8009f38: 2007 movs r0, #7 8009f3a: f000 fad1 bl 800a4e0 if(connectorState == AuthTimeout) log_printf(LOG_INFO, "Connector: AuthTimeout\n"); 8009f3e: 4b17 ldr r3, [pc, #92] @ (8009f9c ) 8009f40: 781b ldrb r3, [r3, #0] 8009f42: 2b09 cmp r3, #9 8009f44: d103 bne.n 8009f4e 8009f46: 4920 ldr r1, [pc, #128] @ (8009fc8 ) 8009f48: 2007 movs r0, #7 8009f4a: f000 fac9 bl 800a4e0 if(connectorState == Finished) log_printf(LOG_INFO, "Connector: Finished\n"); 8009f4e: 4b13 ldr r3, [pc, #76] @ (8009f9c ) 8009f50: 781b ldrb r3, [r3, #0] 8009f52: 2b0a cmp r3, #10 8009f54: d103 bne.n 8009f5e 8009f56: 491d ldr r1, [pc, #116] @ (8009fcc ) 8009f58: 2007 movs r0, #7 8009f5a: f000 fac1 bl 800a4e0 if(connectorState == FinishedEVSE) log_printf(LOG_INFO, "Connector: FinishedEVSE\n"); 8009f5e: 4b0f ldr r3, [pc, #60] @ (8009f9c ) 8009f60: 781b ldrb r3, [r3, #0] 8009f62: 2b0b cmp r3, #11 8009f64: d103 bne.n 8009f6e 8009f66: 491a ldr r1, [pc, #104] @ (8009fd0 ) 8009f68: 2007 movs r0, #7 8009f6a: f000 fab9 bl 800a4e0 if(connectorState == FinishedEV) log_printf(LOG_INFO, "Connector: FinishedEV\n"); 8009f6e: 4b0b ldr r3, [pc, #44] @ (8009f9c ) 8009f70: 781b ldrb r3, [r3, #0] 8009f72: 2b0c cmp r3, #12 8009f74: d103 bne.n 8009f7e 8009f76: 4917 ldr r1, [pc, #92] @ (8009fd4 ) 8009f78: 2007 movs r0, #7 8009f7a: f000 fab1 bl 800a4e0 if(connectorState == Replugging) log_printf(LOG_INFO, "Connector: Replugging\n"); 8009f7e: 4b07 ldr r3, [pc, #28] @ (8009f9c ) 8009f80: 781b ldrb r3, [r3, #0] 8009f82: 2b0d cmp r3, #13 8009f84: d103 bne.n 8009f8e 8009f86: 4914 ldr r1, [pc, #80] @ (8009fd8 ) 8009f88: 2007 movs r0, #7 8009f8a: f000 faa9 bl 800a4e0 CONN.connState = state; 8009f8e: 4a04 ldr r2, [pc, #16] @ (8009fa0 ) 8009f90: 79fb ldrb r3, [r7, #7] 8009f92: 7053 strb r3, [r2, #1] } 8009f94: 3708 adds r7, #8 8009f96: 46bd mov sp, r7 8009f98: bd80 pop {r7, pc} 8009f9a: bf00 nop 8009f9c: 200003cf .word 0x200003cf 8009fa0: 200003b0 .word 0x200003b0 8009fa4: 080169a4 .word 0x080169a4 8009fa8: 080169b8 .word 0x080169b8 8009fac: 080169d0 .word 0x080169d0 8009fb0: 080169e8 .word 0x080169e8 8009fb4: 08016a00 .word 0x08016a00 8009fb8: 08016a1c .word 0x08016a1c 8009fbc: 08016a3c .word 0x08016a3c 8009fc0: 08016a5c .word 0x08016a5c 8009fc4: 08016a7c .word 0x08016a7c 8009fc8: 08016a94 .word 0x08016a94 8009fcc: 08016aac .word 0x08016aac 8009fd0: 08016ac4 .word 0x08016ac4 8009fd4: 08016ae0 .word 0x08016ae0 8009fd8: 08016af8 .word 0x08016af8 08009fdc : CP_State_t cp_state_buffer = EV_STATE_ACQUIRING; #define VREFINT_CAL_ADDR ((uint16_t*)0x1FFFF7BA) // для STM32F1! static int32_t CP_ReadVoltageMv(void) { 8009fdc: b480 push {r7} 8009fde: b087 sub sp, #28 8009fe0: af00 add r7, sp, #0 uint32_t adc_cp = adc_data.cp_raw; 8009fe2: 4b13 ldr r3, [pc, #76] @ (800a030 ) 8009fe4: 885b ldrh r3, [r3, #2] 8009fe6: b29b uxth r3, r3 8009fe8: 617b str r3, [r7, #20] uint32_t adc_vref = adc_data.vrefint_raw; // нужно измерять! 8009fea: 4b11 ldr r3, [pc, #68] @ (800a030 ) 8009fec: 895b ldrh r3, [r3, #10] 8009fee: b29b uxth r3, r3 8009ff0: 613b str r3, [r7, #16] // VREFINT в мВ (берётся из даташита или калибровки MCU) const int32_t VREFINT_MV = 1210; 8009ff2: f240 43ba movw r3, #1210 @ 0x4ba 8009ff6: 60fb str r3, [r7, #12] // напряжение на входе АЦП int32_t v_adc_mv = (adc_cp * VREFINT_MV) / adc_vref; 8009ff8: 68fb ldr r3, [r7, #12] 8009ffa: 697a ldr r2, [r7, #20] 8009ffc: fb03 f202 mul.w r2, r3, r2 800a000: 693b ldr r3, [r7, #16] 800a002: fbb2 f3f3 udiv r3, r2, r3 800a006: 60bb str r3, [r7, #8] // дальше твоя формула int32_t v_out_mv = ((v_adc_mv - 1723) * 7704) / 1000; 800a008: 68bb ldr r3, [r7, #8] 800a00a: f2a3 63bb subw r3, r3, #1723 @ 0x6bb 800a00e: f641 6218 movw r2, #7704 @ 0x1e18 800a012: fb02 f303 mul.w r3, r2, r3 800a016: 4a07 ldr r2, [pc, #28] @ (800a034 ) 800a018: fb82 1203 smull r1, r2, r2, r3 800a01c: 1192 asrs r2, r2, #6 800a01e: 17db asrs r3, r3, #31 800a020: 1ad3 subs r3, r2, r3 800a022: 607b str r3, [r7, #4] return v_out_mv; 800a024: 687b ldr r3, [r7, #4] } 800a026: 4618 mov r0, r3 800a028: 371c adds r7, #28 800a02a: 46bd mov sp, r7 800a02c: bc80 pop {r7} 800a02e: 4770 bx lr 800a030: 20000280 .word 0x20000280 800a034: 10624dd3 .word 0x10624dd3 0800a038 : void CP_Init(void) { 800a038: b580 push {r7, lr} 800a03a: af00 add r7, sp, #0 /* TIM3_CH2 (PA7): set 1kHz PWM like original CCS logic. */ htim3.Instance->PSC = 160 - 1; 800a03c: 4b0e ldr r3, [pc, #56] @ (800a078 ) 800a03e: 681b ldr r3, [r3, #0] 800a040: 229f movs r2, #159 @ 0x9f 800a042: 629a str r2, [r3, #40] @ 0x28 htim3.Instance->ARR = MAX_DUTY - 1; 800a044: 4b0c ldr r3, [pc, #48] @ (800a078 ) 800a046: 681b ldr r3, [r3, #0] 800a048: f240 12c1 movw r2, #449 @ 0x1c1 800a04c: 62da str r2, [r3, #44] @ 0x2c #if DUTY_INVERT == 0 htim3.Instance->CCR2 = MAX_DUTY; 800a04e: 4b0a ldr r3, [pc, #40] @ (800a078 ) 800a050: 681b ldr r3, [r3, #0] 800a052: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a056: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = MAX_DUTY + 5; 800a058: 4b07 ldr r3, [pc, #28] @ (800a078 ) 800a05a: 681b ldr r3, [r3, #0] 800a05c: f240 12c7 movw r2, #455 @ 0x1c7 800a060: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = 0; htim3.Instance->CCR1 = 0; #endif HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_2); 800a062: 2104 movs r1, #4 800a064: 4804 ldr r0, [pc, #16] @ (800a078 ) 800a066: f007 ff87 bl 8011f78 HAL_TIM_OC_Start(&htim3, TIM_CHANNEL_1); 800a06a: 2100 movs r1, #0 800a06c: 4802 ldr r0, [pc, #8] @ (800a078 ) 800a06e: f007 fe81 bl 8011d74 } 800a072: bf00 nop 800a074: bd80 pop {r7, pc} 800a076: bf00 nop 800a078: 200010c0 .word 0x200010c0 0800a07c : void CP_SetDuty(uint8_t percentage) { 800a07c: b480 push {r7} 800a07e: b085 sub sp, #20 800a080: af00 add r7, sp, #0 800a082: 4603 mov r3, r0 800a084: 71fb strb r3, [r7, #7] uint32_t pwmduty = MAX_DUTY * percentage / 100; 800a086: 79fb ldrb r3, [r7, #7] 800a088: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a08c: fb02 f303 mul.w r3, r2, r3 800a090: 4a0b ldr r2, [pc, #44] @ (800a0c0 ) 800a092: fb82 1203 smull r1, r2, r2, r3 800a096: 1152 asrs r2, r2, #5 800a098: 17db asrs r3, r3, #31 800a09a: 1ad3 subs r3, r2, r3 800a09c: 60fb str r3, [r7, #12] cp_duty = percentage; 800a09e: 4a09 ldr r2, [pc, #36] @ (800a0c4 ) 800a0a0: 79fb ldrb r3, [r7, #7] 800a0a2: 7013 strb r3, [r2, #0] #if DUTY_INVERT == 0 htim3.Instance->CCR2 = pwmduty; 800a0a4: 4b08 ldr r3, [pc, #32] @ (800a0c8 ) 800a0a6: 681b ldr r3, [r3, #0] 800a0a8: 68fa ldr r2, [r7, #12] 800a0aa: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = 0 + 1; 800a0ac: 4b06 ldr r3, [pc, #24] @ (800a0c8 ) 800a0ae: 681b ldr r3, [r3, #0] 800a0b0: 2201 movs r2, #1 800a0b2: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = MAX_DUTY - pwmduty; htim3.Instance->CCR1 = MAX_DUTY - pwmduty + 5; #endif } 800a0b4: bf00 nop 800a0b6: 3714 adds r7, #20 800a0b8: 46bd mov sp, r7 800a0ba: bc80 pop {r7} 800a0bc: 4770 bx lr 800a0be: bf00 nop 800a0c0: 51eb851f .word 0x51eb851f 800a0c4: 200003d8 .word 0x200003d8 800a0c8: 200010c0 .word 0x200010c0 0800a0cc : uint8_t CP_GetDuty(void) { 800a0cc: b480 push {r7} 800a0ce: af00 add r7, sp, #0 return cp_duty; 800a0d0: 4b02 ldr r3, [pc, #8] @ (800a0dc ) 800a0d2: 781b ldrb r3, [r3, #0] } 800a0d4: 4618 mov r0, r3 800a0d6: 46bd mov sp, r7 800a0d8: bc80 pop {r7} 800a0da: 4770 bx lr 800a0dc: 200003d8 .word 0x200003d8 0800a0e0 : int32_t CP_GetVoltage(void) { 800a0e0: b580 push {r7, lr} 800a0e2: af00 add r7, sp, #0 cp_voltage_mv = CP_ReadVoltageMv(); 800a0e4: f7ff ff7a bl 8009fdc 800a0e8: 4603 mov r3, r0 800a0ea: 4a03 ldr r2, [pc, #12] @ (800a0f8 ) 800a0ec: 6013 str r3, [r2, #0] return cp_voltage_mv; 800a0ee: 4b02 ldr r3, [pc, #8] @ (800a0f8 ) 800a0f0: 681b ldr r3, [r3, #0] } 800a0f2: 4618 mov r0, r3 800a0f4: bd80 pop {r7, pc} 800a0f6: bf00 nop 800a0f8: 200003d4 .word 0x200003d4 0800a0fc : CP_State_t CP_GetState(void) { 800a0fc: b580 push {r7, lr} 800a0fe: b082 sub sp, #8 800a100: af00 add r7, sp, #0 int32_t voltage_real = CP_GetVoltage(); 800a102: f7ff ffed bl 800a0e0 800a106: 6078 str r0, [r7, #4] if(fake_cp_state != EV_STATE_ACQUIRING) { 800a108: 4b21 ldr r3, [pc, #132] @ (800a190 ) 800a10a: 781b ldrb r3, [r3, #0] 800a10c: 2b06 cmp r3, #6 800a10e: d002 beq.n 800a116 return fake_cp_state; 800a110: 4b1f ldr r3, [pc, #124] @ (800a190 ) 800a112: 781b ldrb r3, [r3, #0] 800a114: e038 b.n 800a188 } if (voltage_real >= (12000-1000)) { 800a116: 687b ldr r3, [r7, #4] 800a118: f642 22f7 movw r2, #10999 @ 0x2af7 800a11c: 4293 cmp r3, r2 800a11e: dd01 ble.n 800a124 return EV_STATE_A_IDLE; 800a120: 2300 movs r3, #0 800a122: e031 b.n 800a188 } else if (voltage_real >= (9000-1000) && voltage_real <= (9000+1000)) { 800a124: 687b ldr r3, [r7, #4] 800a126: f5b3 5ffa cmp.w r3, #8000 @ 0x1f40 800a12a: db06 blt.n 800a13a 800a12c: 687b ldr r3, [r7, #4] 800a12e: f242 7210 movw r2, #10000 @ 0x2710 800a132: 4293 cmp r3, r2 800a134: dc01 bgt.n 800a13a return EV_STATE_B_CONN_PREP; 800a136: 2301 movs r3, #1 800a138: e026 b.n 800a188 } else if (voltage_real >= (6000-1000) && voltage_real <= (6000+1000)) { 800a13a: 687b ldr r3, [r7, #4] 800a13c: f241 3287 movw r2, #4999 @ 0x1387 800a140: 4293 cmp r3, r2 800a142: dd06 ble.n 800a152 800a144: 687b ldr r3, [r7, #4] 800a146: f641 3258 movw r2, #7000 @ 0x1b58 800a14a: 4293 cmp r3, r2 800a14c: dc01 bgt.n 800a152 return EV_STATE_C_CONN_ACTIVE; 800a14e: 2302 movs r3, #2 800a150: e01a b.n 800a188 } else if (voltage_real >= (3000-1000) && voltage_real <= (3000 + 1000)) { 800a152: 687b ldr r3, [r7, #4] 800a154: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800a158: db05 blt.n 800a166 800a15a: 687b ldr r3, [r7, #4] 800a15c: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800a160: dc01 bgt.n 800a166 return EV_STATE_D_CONN_ACT_VENT; 800a162: 2303 movs r3, #3 800a164: e010 b.n 800a188 } else if (voltage_real >= (0-1000) && voltage_real <= (0+2000)){ 800a166: 687b ldr r3, [r7, #4] 800a168: f513 7f7a cmn.w r3, #1000 @ 0x3e8 800a16c: db05 blt.n 800a17a 800a16e: 687b ldr r3, [r7, #4] 800a170: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800a174: dc01 bgt.n 800a17a return EV_STATE_E_NO_POWER; 800a176: 2304 movs r3, #4 800a178: e006 b.n 800a188 } else if (voltage_real <= (-12000+1000)) { 800a17a: 687b ldr r3, [r7, #4] 800a17c: 4a05 ldr r2, [pc, #20] @ (800a194 ) 800a17e: 4293 cmp r3, r2 800a180: da01 bge.n 800a186 return EV_STATE_F_ERROR; 800a182: 2305 movs r3, #5 800a184: e000 b.n 800a188 } else { return EV_STATE_ACQUIRING; 800a186: 2306 movs r3, #6 } } 800a188: 4618 mov r0, r3 800a18a: 3708 adds r7, #8 800a18c: 46bd mov sp, r7 800a18e: bd80 pop {r7, pc} 800a190: 20000004 .word 0x20000004 800a194: ffffd509 .word 0xffffd509 0800a198 : CP_State_t CP_GetFilteredState(void) { 800a198: b480 push {r7} 800a19a: af00 add r7, sp, #0 return cp_state_buffer; 800a19c: 4b02 ldr r3, [pc, #8] @ (800a1a8 ) 800a19e: 781b ldrb r3, [r3, #0] } 800a1a0: 4618 mov r0, r3 800a1a2: 46bd mov sp, r7 800a1a4: bc80 pop {r7} 800a1a6: 4770 bx lr 800a1a8: 20000005 .word 0x20000005 0800a1ac : void CP_FilterState(void) { 800a1ac: b580 push {r7, lr} 800a1ae: b082 sub sp, #8 800a1b0: af00 add r7, sp, #0 static CP_State_t pending_state = EV_STATE_ACQUIRING; static uint8_t stable_count = 0u; CP_State_t current_state = CP_GetState(); 800a1b2: f7ff ffa3 bl 800a0fc 800a1b6: 4603 mov r3, r0 800a1b8: 71fb strb r3, [r7, #7] /* Keep last accepted state while CP is still acquiring. */ if (current_state == EV_STATE_ACQUIRING) { 800a1ba: 79fb ldrb r3, [r7, #7] 800a1bc: 2b06 cmp r3, #6 800a1be: d106 bne.n 800a1ce pending_state = EV_STATE_ACQUIRING; 800a1c0: 4b13 ldr r3, [pc, #76] @ (800a210 ) 800a1c2: 2206 movs r2, #6 800a1c4: 701a strb r2, [r3, #0] stable_count = 0u; 800a1c6: 4b13 ldr r3, [pc, #76] @ (800a214 ) 800a1c8: 2200 movs r2, #0 800a1ca: 701a strb r2, [r3, #0] return; 800a1cc: e01d b.n 800a20a } if (current_state != pending_state) { 800a1ce: 4b10 ldr r3, [pc, #64] @ (800a210 ) 800a1d0: 781b ldrb r3, [r3, #0] 800a1d2: 79fa ldrb r2, [r7, #7] 800a1d4: 429a cmp r2, r3 800a1d6: d006 beq.n 800a1e6 pending_state = current_state; 800a1d8: 4a0d ldr r2, [pc, #52] @ (800a210 ) 800a1da: 79fb ldrb r3, [r7, #7] 800a1dc: 7013 strb r3, [r2, #0] stable_count = 1u; 800a1de: 4b0d ldr r3, [pc, #52] @ (800a214 ) 800a1e0: 2201 movs r2, #1 800a1e2: 701a strb r2, [r3, #0] return; 800a1e4: e011 b.n 800a20a } if (stable_count < FILTER_ORDER) { 800a1e6: 4b0b ldr r3, [pc, #44] @ (800a214 ) 800a1e8: 781b ldrb r3, [r3, #0] 800a1ea: 2b63 cmp r3, #99 @ 0x63 800a1ec: d805 bhi.n 800a1fa stable_count++; 800a1ee: 4b09 ldr r3, [pc, #36] @ (800a214 ) 800a1f0: 781b ldrb r3, [r3, #0] 800a1f2: 3301 adds r3, #1 800a1f4: b2da uxtb r2, r3 800a1f6: 4b07 ldr r3, [pc, #28] @ (800a214 ) 800a1f8: 701a strb r2, [r3, #0] } if (stable_count >= FILTER_ORDER) { 800a1fa: 4b06 ldr r3, [pc, #24] @ (800a214 ) 800a1fc: 781b ldrb r3, [r3, #0] 800a1fe: 2b63 cmp r3, #99 @ 0x63 800a200: d903 bls.n 800a20a cp_state_buffer = pending_state; 800a202: 4b03 ldr r3, [pc, #12] @ (800a210 ) 800a204: 781a ldrb r2, [r3, #0] 800a206: 4b04 ldr r3, [pc, #16] @ (800a218 ) 800a208: 701a strb r2, [r3, #0] } } 800a20a: 3708 adds r7, #8 800a20c: 46bd mov sp, r7 800a20e: bd80 pop {r7, pc} 800a210: 20000006 .word 0x20000006 800a214: 200003d9 .word 0x200003d9 800a218: 20000005 .word 0x20000005 0800a21c : void CP_Loop(void) { 800a21c: b580 push {r7, lr} 800a21e: b082 sub sp, #8 800a220: af00 add r7, sp, #0 static uint8_t initialized = 0; static CP_State_t prev_state = EV_STATE_ACQUIRING; static uint8_t prev_duty = 0; CP_FilterState(); 800a222: f7ff ffc3 bl 800a1ac CP_State_t current_state = CP_GetFilteredState(); 800a226: f7ff ffb7 bl 800a198 800a22a: 4603 mov r3, r0 800a22c: 71fb strb r3, [r7, #7] uint8_t current_duty = cp_duty; 800a22e: 4b1a ldr r3, [pc, #104] @ (800a298 ) 800a230: 781b ldrb r3, [r3, #0] 800a232: 71bb strb r3, [r7, #6] if (!initialized) { 800a234: 4b19 ldr r3, [pc, #100] @ (800a29c ) 800a236: 781b ldrb r3, [r3, #0] 800a238: 2b00 cmp r3, #0 800a23a: d109 bne.n 800a250 prev_state = current_state; 800a23c: 4a18 ldr r2, [pc, #96] @ (800a2a0 ) 800a23e: 79fb ldrb r3, [r7, #7] 800a240: 7013 strb r3, [r2, #0] prev_duty = current_duty; 800a242: 4a18 ldr r2, [pc, #96] @ (800a2a4 ) 800a244: 79bb ldrb r3, [r7, #6] 800a246: 7013 strb r3, [r2, #0] initialized = 1; 800a248: 4b14 ldr r3, [pc, #80] @ (800a29c ) 800a24a: 2201 movs r2, #1 800a24c: 701a strb r2, [r3, #0] return; 800a24e: e01f b.n 800a290 } if (current_state != prev_state) { 800a250: 4b13 ldr r3, [pc, #76] @ (800a2a0 ) 800a252: 781b ldrb r3, [r3, #0] 800a254: 79fa ldrb r2, [r7, #7] 800a256: 429a cmp r2, r3 800a258: d00a beq.n 800a270 log_printf(LOG_INFO, "CP state changed: %d -> %d\n", prev_state, current_state); 800a25a: 4b11 ldr r3, [pc, #68] @ (800a2a0 ) 800a25c: 781b ldrb r3, [r3, #0] 800a25e: 461a mov r2, r3 800a260: 79fb ldrb r3, [r7, #7] 800a262: 4911 ldr r1, [pc, #68] @ (800a2a8 ) 800a264: 2007 movs r0, #7 800a266: f000 f93b bl 800a4e0 prev_state = current_state; 800a26a: 4a0d ldr r2, [pc, #52] @ (800a2a0 ) 800a26c: 79fb ldrb r3, [r7, #7] 800a26e: 7013 strb r3, [r2, #0] } if (current_duty != prev_duty) { 800a270: 4b0c ldr r3, [pc, #48] @ (800a2a4 ) 800a272: 781b ldrb r3, [r3, #0] 800a274: 79ba ldrb r2, [r7, #6] 800a276: 429a cmp r2, r3 800a278: d00a beq.n 800a290 log_printf(LOG_INFO, "CP duty changed: %u -> %u\n", prev_duty, current_duty); 800a27a: 4b0a ldr r3, [pc, #40] @ (800a2a4 ) 800a27c: 781b ldrb r3, [r3, #0] 800a27e: 461a mov r2, r3 800a280: 79bb ldrb r3, [r7, #6] 800a282: 490a ldr r1, [pc, #40] @ (800a2ac ) 800a284: 2007 movs r0, #7 800a286: f000 f92b bl 800a4e0 prev_duty = current_duty; 800a28a: 4a06 ldr r2, [pc, #24] @ (800a2a4 ) 800a28c: 79bb ldrb r3, [r7, #6] 800a28e: 7013 strb r3, [r2, #0] } } 800a290: 3708 adds r7, #8 800a292: 46bd mov sp, r7 800a294: bd80 pop {r7, pc} 800a296: bf00 nop 800a298: 200003d8 .word 0x200003d8 800a29c: 200003da .word 0x200003da 800a2a0: 20000007 .word 0x20000007 800a2a4: 200003db .word 0x200003db 800a2a8: 08016b44 .word 0x08016b44 800a2ac: 08016b60 .word 0x08016b60 0800a2b0 : CRC_HandleTypeDef hcrc; /* CRC init function */ void MX_CRC_Init(void) { 800a2b0: b580 push {r7, lr} 800a2b2: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 800a2b4: 4b06 ldr r3, [pc, #24] @ (800a2d0 ) 800a2b6: 4a07 ldr r2, [pc, #28] @ (800a2d4 ) 800a2b8: 601a str r2, [r3, #0] if (HAL_CRC_Init(&hcrc) != HAL_OK) 800a2ba: 4805 ldr r0, [pc, #20] @ (800a2d0 ) 800a2bc: f005 fc2d bl 800fb1a 800a2c0: 4603 mov r3, r0 800a2c2: 2b00 cmp r3, #0 800a2c4: d001 beq.n 800a2ca { Error_Handler(); 800a2c6: f000 fc83 bl 800abd0 } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 800a2ca: bf00 nop 800a2cc: bd80 pop {r7, pc} 800a2ce: bf00 nop 800a2d0: 200003dc .word 0x200003dc 800a2d4: 40023000 .word 0x40023000 0800a2d8 : void HAL_CRC_MspInit(CRC_HandleTypeDef* crcHandle) { 800a2d8: b480 push {r7} 800a2da: b085 sub sp, #20 800a2dc: af00 add r7, sp, #0 800a2de: 6078 str r0, [r7, #4] if(crcHandle->Instance==CRC) 800a2e0: 687b ldr r3, [r7, #4] 800a2e2: 681b ldr r3, [r3, #0] 800a2e4: 4a09 ldr r2, [pc, #36] @ (800a30c ) 800a2e6: 4293 cmp r3, r2 800a2e8: d10b bne.n 800a302 { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* CRC clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 800a2ea: 4b09 ldr r3, [pc, #36] @ (800a310 ) 800a2ec: 695b ldr r3, [r3, #20] 800a2ee: 4a08 ldr r2, [pc, #32] @ (800a310 ) 800a2f0: f043 0340 orr.w r3, r3, #64 @ 0x40 800a2f4: 6153 str r3, [r2, #20] 800a2f6: 4b06 ldr r3, [pc, #24] @ (800a310 ) 800a2f8: 695b ldr r3, [r3, #20] 800a2fa: f003 0340 and.w r3, r3, #64 @ 0x40 800a2fe: 60fb str r3, [r7, #12] 800a300: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 800a302: bf00 nop 800a304: 3714 adds r7, #20 800a306: 46bd mov sp, r7 800a308: bc80 pop {r7} 800a30a: 4770 bx lr 800a30c: 40023000 .word 0x40023000 800a310: 40021000 .word 0x40021000 0800a314 <_write>: #if defined(__GNUC__) int _write(int fd, char * ptr, int len) { 800a314: b580 push {r7, lr} 800a316: b084 sub sp, #16 800a318: af00 add r7, sp, #0 800a31a: 60f8 str r0, [r7, #12] 800a31c: 60b9 str r1, [r7, #8] 800a31e: 607a str r2, [r7, #4] debug_buffer_add((const uint8_t*)ptr, len); 800a320: 687b ldr r3, [r7, #4] 800a322: b29b uxth r3, r3 800a324: 4619 mov r1, r3 800a326: 68b8 ldr r0, [r7, #8] 800a328: f000 f806 bl 800a338 return len; 800a32c: 687b ldr r3, [r7, #4] } 800a32e: 4618 mov r0, r3 800a330: 3710 adds r7, #16 800a332: 46bd mov sp, r7 800a334: bd80 pop {r7, pc} ... 0800a338 : #endif // Добавляет данные в кольцевой буфер void debug_buffer_add(const uint8_t* data, uint16_t len) { 800a338: b480 push {r7} 800a33a: b085 sub sp, #20 800a33c: af00 add r7, sp, #0 800a33e: 6078 str r0, [r7, #4] 800a340: 460b mov r3, r1 800a342: 807b strh r3, [r7, #2] \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 800a344: b672 cpsid i } 800a346: bf00 nop __disable_irq(); for (uint16_t i = 0; i < len; i++) { 800a348: 2300 movs r3, #0 800a34a: 81fb strh r3, [r7, #14] 800a34c: e045 b.n 800a3da // Если буфер полон, перезаписываем старые данные if (debug_buffer.count >= DEBUG_BUFFER_SIZE) { 800a34e: 4b28 ldr r3, [pc, #160] @ (800a3f0 ) 800a350: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a354: b29b uxth r3, r3 800a356: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800a35a: d318 bcc.n 800a38e debug_buffer.read_index = (debug_buffer.read_index + 1) % DEBUG_BUFFER_SIZE; 800a35c: 4b24 ldr r3, [pc, #144] @ (800a3f0 ) 800a35e: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a362: b29b uxth r3, r3 800a364: 3301 adds r3, #1 800a366: 425a negs r2, r3 800a368: f3c3 0309 ubfx r3, r3, #0, #10 800a36c: f3c2 0209 ubfx r2, r2, #0, #10 800a370: bf58 it pl 800a372: 4253 negpl r3, r2 800a374: b29a uxth r2, r3 800a376: 4b1e ldr r3, [pc, #120] @ (800a3f0 ) 800a378: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count--; 800a37c: 4b1c ldr r3, [pc, #112] @ (800a3f0 ) 800a37e: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a382: b29b uxth r3, r3 800a384: 3b01 subs r3, #1 800a386: b29a uxth r2, r3 800a388: 4b19 ldr r3, [pc, #100] @ (800a3f0 ) 800a38a: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 } debug_buffer.buffer[debug_buffer.write_index] = data[i]; 800a38e: 89fb ldrh r3, [r7, #14] 800a390: 687a ldr r2, [r7, #4] 800a392: 4413 add r3, r2 800a394: 4a16 ldr r2, [pc, #88] @ (800a3f0 ) 800a396: f8b2 2400 ldrh.w r2, [r2, #1024] @ 0x400 800a39a: b292 uxth r2, r2 800a39c: 7819 ldrb r1, [r3, #0] 800a39e: 4b14 ldr r3, [pc, #80] @ (800a3f0 ) 800a3a0: 5499 strb r1, [r3, r2] debug_buffer.write_index = (debug_buffer.write_index + 1) % DEBUG_BUFFER_SIZE; 800a3a2: 4b13 ldr r3, [pc, #76] @ (800a3f0 ) 800a3a4: f8b3 3400 ldrh.w r3, [r3, #1024] @ 0x400 800a3a8: b29b uxth r3, r3 800a3aa: 3301 adds r3, #1 800a3ac: 425a negs r2, r3 800a3ae: f3c3 0309 ubfx r3, r3, #0, #10 800a3b2: f3c2 0209 ubfx r2, r2, #0, #10 800a3b6: bf58 it pl 800a3b8: 4253 negpl r3, r2 800a3ba: b29a uxth r2, r3 800a3bc: 4b0c ldr r3, [pc, #48] @ (800a3f0 ) 800a3be: f8a3 2400 strh.w r2, [r3, #1024] @ 0x400 debug_buffer.count++; 800a3c2: 4b0b ldr r3, [pc, #44] @ (800a3f0 ) 800a3c4: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a3c8: b29b uxth r3, r3 800a3ca: 3301 adds r3, #1 800a3cc: b29a uxth r2, r3 800a3ce: 4b08 ldr r3, [pc, #32] @ (800a3f0 ) 800a3d0: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 for (uint16_t i = 0; i < len; i++) { 800a3d4: 89fb ldrh r3, [r7, #14] 800a3d6: 3301 adds r3, #1 800a3d8: 81fb strh r3, [r7, #14] 800a3da: 89fa ldrh r2, [r7, #14] 800a3dc: 887b ldrh r3, [r7, #2] 800a3de: 429a cmp r2, r3 800a3e0: d3b5 bcc.n 800a34e __ASM volatile ("cpsie i" : : : "memory"); 800a3e2: b662 cpsie i } 800a3e4: bf00 nop } __enable_irq(); } 800a3e6: bf00 nop 800a3e8: 3714 adds r7, #20 800a3ea: 46bd mov sp, r7 800a3ec: bc80 pop {r7} 800a3ee: 4770 bx lr 800a3f0: 200003e4 .word 0x200003e4 0800a3f4 : // Возвращает количество доступных данных в буфере uint16_t debug_buffer_available(void) { 800a3f4: b480 push {r7} 800a3f6: b083 sub sp, #12 800a3f8: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a3fa: b672 cpsid i } 800a3fc: bf00 nop __disable_irq(); uint16_t count = debug_buffer.count; 800a3fe: 4b06 ldr r3, [pc, #24] @ (800a418 ) 800a400: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a404: 80fb strh r3, [r7, #6] __ASM volatile ("cpsie i" : : : "memory"); 800a406: b662 cpsie i } 800a408: bf00 nop __enable_irq(); return count; 800a40a: 88fb ldrh r3, [r7, #6] } 800a40c: 4618 mov r0, r3 800a40e: 370c adds r7, #12 800a410: 46bd mov sp, r7 800a412: bc80 pop {r7} 800a414: 4770 bx lr 800a416: bf00 nop 800a418: 200003e4 .word 0x200003e4 0800a41c : // Отправляет один пакет данных из буфера через SC_SendPacket (не более 250 байт) void debug_buffer_send(void) { 800a41c: b580 push {r7, lr} 800a41e: b082 sub sp, #8 800a420: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a422: b672 cpsid i } 800a424: bf00 nop __disable_irq(); // Если буфер пуст, ничего не делаем if (debug_buffer.count == 0) { 800a426: 4b2d ldr r3, [pc, #180] @ (800a4dc ) 800a428: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a42c: b29b uxth r3, r3 800a42e: 2b00 cmp r3, #0 800a430: d102 bne.n 800a438 __ASM volatile ("cpsie i" : : : "memory"); 800a432: b662 cpsie i } 800a434: bf00 nop __enable_irq(); return; 800a436: e04e b.n 800a4d6 } // Определяем сколько байт можно отправить (не более 250) uint16_t bytes_to_send = debug_buffer.count; 800a438: 4b28 ldr r3, [pc, #160] @ (800a4dc ) 800a43a: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a43e: 80fb strh r3, [r7, #6] if (bytes_to_send > DEBUG_BUFFER_MAX_COUNT) { 800a440: 88fb ldrh r3, [r7, #6] 800a442: 2b80 cmp r3, #128 @ 0x80 800a444: d901 bls.n 800a44a bytes_to_send = DEBUG_BUFFER_MAX_COUNT; 800a446: 2380 movs r3, #128 @ 0x80 800a448: 80fb strh r3, [r7, #6] } // Вычисляем сколько байт до конца буфера uint16_t bytes_to_end = DEBUG_BUFFER_SIZE - debug_buffer.read_index; 800a44a: 4b24 ldr r3, [pc, #144] @ (800a4dc ) 800a44c: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a450: b29b uxth r3, r3 800a452: f5c3 6380 rsb r3, r3, #1024 @ 0x400 800a456: 80bb strh r3, [r7, #4] // Отправляем только непрерывный блок (до конца буфера или до bytes_to_send) if (bytes_to_send > bytes_to_end) { 800a458: 88fa ldrh r2, [r7, #6] 800a45a: 88bb ldrh r3, [r7, #4] 800a45c: 429a cmp r2, r3 800a45e: d901 bls.n 800a464 bytes_to_send = bytes_to_end; 800a460: 88bb ldrh r3, [r7, #4] 800a462: 80fb strh r3, [r7, #6] } // Отправляем данные напрямую из буфера if(bytes_to_send == debug_buffer.count){ 800a464: 4b1d ldr r3, [pc, #116] @ (800a4dc ) 800a466: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a46a: b29b uxth r3, r3 800a46c: 88fa ldrh r2, [r7, #6] 800a46e: 429a cmp r2, r3 800a470: d10c bne.n 800a48c SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG); 800a472: 4b1a ldr r3, [pc, #104] @ (800a4dc ) 800a474: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a478: b29b uxth r3, r3 800a47a: 461a mov r2, r3 800a47c: 4b17 ldr r3, [pc, #92] @ (800a4dc ) 800a47e: 4413 add r3, r2 800a480: 88f9 ldrh r1, [r7, #6] 800a482: 2250 movs r2, #80 @ 0x50 800a484: 4618 mov r0, r3 800a486: f002 fba7 bl 800cbd8 800a48a: e00b b.n 800a4a4 }else{ SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG_CONTINUE); 800a48c: 4b13 ldr r3, [pc, #76] @ (800a4dc ) 800a48e: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a492: b29b uxth r3, r3 800a494: 461a mov r2, r3 800a496: 4b11 ldr r3, [pc, #68] @ (800a4dc ) 800a498: 4413 add r3, r2 800a49a: 88f9 ldrh r1, [r7, #6] 800a49c: 2251 movs r2, #81 @ 0x51 800a49e: 4618 mov r0, r3 800a4a0: f002 fb9a bl 800cbd8 } debug_buffer.read_index = (debug_buffer.read_index + bytes_to_send) % DEBUG_BUFFER_SIZE; 800a4a4: 4b0d ldr r3, [pc, #52] @ (800a4dc ) 800a4a6: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a4aa: b29a uxth r2, r3 800a4ac: 88fb ldrh r3, [r7, #6] 800a4ae: 4413 add r3, r2 800a4b0: b29b uxth r3, r3 800a4b2: f3c3 0309 ubfx r3, r3, #0, #10 800a4b6: b29a uxth r2, r3 800a4b8: 4b08 ldr r3, [pc, #32] @ (800a4dc ) 800a4ba: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count -= bytes_to_send; 800a4be: 4b07 ldr r3, [pc, #28] @ (800a4dc ) 800a4c0: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a4c4: b29a uxth r2, r3 800a4c6: 88fb ldrh r3, [r7, #6] 800a4c8: 1ad3 subs r3, r2, r3 800a4ca: b29a uxth r2, r3 800a4cc: 4b03 ldr r3, [pc, #12] @ (800a4dc ) 800a4ce: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 __ASM volatile ("cpsie i" : : : "memory"); 800a4d2: b662 cpsie i } 800a4d4: bf00 nop __enable_irq(); } 800a4d6: 3708 adds r7, #8 800a4d8: 46bd mov sp, r7 800a4da: bd80 pop {r7, pc} 800a4dc: 200003e4 .word 0x200003e4 0800a4e0 : #define LOG_BUFFER_SIZE 128 uint8_t log_buffer[LOG_BUFFER_SIZE]; // Кастомный printf с приоритетом лога int log_printf(LogLevel_t level, const char *format, ...) { 800a4e0: b40e push {r1, r2, r3} 800a4e2: b580 push {r7, lr} 800a4e4: b085 sub sp, #20 800a4e6: af00 add r7, sp, #0 800a4e8: 4603 mov r3, r0 800a4ea: 71fb strb r3, [r7, #7] va_list args; int result; // Добавляем приоритет первым байтом log_buffer[0] = (uint8_t)level; 800a4ec: 4a15 ldr r2, [pc, #84] @ (800a544 ) 800a4ee: 79fb ldrb r3, [r7, #7] 800a4f0: 7013 strb r3, [r2, #0] // Форматируем строку начиная со второго байта va_start(args, format); 800a4f2: f107 0320 add.w r3, r7, #32 800a4f6: 60bb str r3, [r7, #8] result = vsnprintf((char*)&log_buffer[1], LOG_BUFFER_SIZE - 2, format, args); 800a4f8: 68bb ldr r3, [r7, #8] 800a4fa: 69fa ldr r2, [r7, #28] 800a4fc: 217e movs r1, #126 @ 0x7e 800a4fe: 4812 ldr r0, [pc, #72] @ (800a548 ) 800a500: f00a f8de bl 80146c0 800a504: 60f8 str r0, [r7, #12] va_end(args); // Проверяем, не переполнился ли буфер if (result < 0) { 800a506: 68fb ldr r3, [r7, #12] 800a508: 2b00 cmp r3, #0 800a50a: da01 bge.n 800a510 return result; 800a50c: 68fb ldr r3, [r7, #12] 800a50e: e012 b.n 800a536 } // Ограничиваем размер, чтобы оставить место для нуль-терминатора if (result >= (LOG_BUFFER_SIZE - 2)) { 800a510: 68fb ldr r3, [r7, #12] 800a512: 2b7d cmp r3, #125 @ 0x7d 800a514: dd01 ble.n 800a51a result = LOG_BUFFER_SIZE - 2; 800a516: 237e movs r3, #126 @ 0x7e 800a518: 60fb str r3, [r7, #12] } // Добавляем нуль-терминатор в конец log_buffer[result + 1] = '\0'; 800a51a: 68fb ldr r3, [r7, #12] 800a51c: 3301 adds r3, #1 800a51e: 4a09 ldr r2, [pc, #36] @ (800a544 ) 800a520: 2100 movs r1, #0 800a522: 54d1 strb r1, [r2, r3] // Отправляем в буфер (приоритет + строка + нуль-терминатор) debug_buffer_add(log_buffer, result + 2); 800a524: 68fb ldr r3, [r7, #12] 800a526: b29b uxth r3, r3 800a528: 3302 adds r3, #2 800a52a: b29b uxth r3, r3 800a52c: 4619 mov r1, r3 800a52e: 4805 ldr r0, [pc, #20] @ (800a544 ) 800a530: f7ff ff02 bl 800a338 return result; 800a534: 68fb ldr r3, [r7, #12] } 800a536: 4618 mov r0, r3 800a538: 3714 adds r7, #20 800a53a: 46bd mov sp, r7 800a53c: e8bd 4080 ldmia.w sp!, {r7, lr} 800a540: b003 add sp, #12 800a542: 4770 bx lr 800a544: 200007ec .word 0x200007ec 800a548: 200007ed .word 0x200007ed 0800a54c : /** * Enable DMA controller clock */ void MX_DMA_Init(void) { 800a54c: b580 push {r7, lr} 800a54e: b082 sub sp, #8 800a550: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 800a552: 4b0c ldr r3, [pc, #48] @ (800a584 ) 800a554: 695b ldr r3, [r3, #20] 800a556: 4a0b ldr r2, [pc, #44] @ (800a584 ) 800a558: f043 0301 orr.w r3, r3, #1 800a55c: 6153 str r3, [r2, #20] 800a55e: 4b09 ldr r3, [pc, #36] @ (800a584 ) 800a560: 695b ldr r3, [r3, #20] 800a562: f003 0301 and.w r3, r3, #1 800a566: 607b str r3, [r7, #4] 800a568: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); 800a56a: 2200 movs r2, #0 800a56c: 2100 movs r1, #0 800a56e: 200b movs r0, #11 800a570: f005 fa8f bl 800fa92 HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 800a574: 200b movs r0, #11 800a576: f005 faa8 bl 800faca } 800a57a: bf00 nop 800a57c: 3708 adds r7, #8 800a57e: 46bd mov sp, r7 800a580: bd80 pop {r7, pc} 800a582: bf00 nop 800a584: 40021000 .word 0x40021000 0800a588 : * EXTI PB8 ------> I2C1_SCL PB9 ------> I2C1_SDA */ void MX_GPIO_Init(void) { 800a588: b580 push {r7, lr} 800a58a: b08a sub sp, #40 @ 0x28 800a58c: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800a58e: f107 0314 add.w r3, r7, #20 800a592: 2200 movs r2, #0 800a594: 601a str r2, [r3, #0] 800a596: 605a str r2, [r3, #4] 800a598: 609a str r2, [r3, #8] 800a59a: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 800a59c: 4b93 ldr r3, [pc, #588] @ (800a7ec ) 800a59e: 699b ldr r3, [r3, #24] 800a5a0: 4a92 ldr r2, [pc, #584] @ (800a7ec ) 800a5a2: f043 0310 orr.w r3, r3, #16 800a5a6: 6193 str r3, [r2, #24] 800a5a8: 4b90 ldr r3, [pc, #576] @ (800a7ec ) 800a5aa: 699b ldr r3, [r3, #24] 800a5ac: f003 0310 and.w r3, r3, #16 800a5b0: 613b str r3, [r7, #16] 800a5b2: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800a5b4: 4b8d ldr r3, [pc, #564] @ (800a7ec ) 800a5b6: 699b ldr r3, [r3, #24] 800a5b8: 4a8c ldr r2, [pc, #560] @ (800a7ec ) 800a5ba: f043 0304 orr.w r3, r3, #4 800a5be: 6193 str r3, [r2, #24] 800a5c0: 4b8a ldr r3, [pc, #552] @ (800a7ec ) 800a5c2: 699b ldr r3, [r3, #24] 800a5c4: f003 0304 and.w r3, r3, #4 800a5c8: 60fb str r3, [r7, #12] 800a5ca: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 800a5cc: 4b87 ldr r3, [pc, #540] @ (800a7ec ) 800a5ce: 699b ldr r3, [r3, #24] 800a5d0: 4a86 ldr r2, [pc, #536] @ (800a7ec ) 800a5d2: f043 0308 orr.w r3, r3, #8 800a5d6: 6193 str r3, [r2, #24] 800a5d8: 4b84 ldr r3, [pc, #528] @ (800a7ec ) 800a5da: 699b ldr r3, [r3, #24] 800a5dc: f003 0308 and.w r3, r3, #8 800a5e0: 60bb str r3, [r7, #8] 800a5e2: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOE_CLK_ENABLE(); 800a5e4: 4b81 ldr r3, [pc, #516] @ (800a7ec ) 800a5e6: 699b ldr r3, [r3, #24] 800a5e8: 4a80 ldr r2, [pc, #512] @ (800a7ec ) 800a5ea: f043 0340 orr.w r3, r3, #64 @ 0x40 800a5ee: 6193 str r3, [r2, #24] 800a5f0: 4b7e ldr r3, [pc, #504] @ (800a7ec ) 800a5f2: 699b ldr r3, [r3, #24] 800a5f4: f003 0340 and.w r3, r3, #64 @ 0x40 800a5f8: 607b str r3, [r7, #4] 800a5fa: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 800a5fc: 4b7b ldr r3, [pc, #492] @ (800a7ec ) 800a5fe: 699b ldr r3, [r3, #24] 800a600: 4a7a ldr r2, [pc, #488] @ (800a7ec ) 800a602: f043 0320 orr.w r3, r3, #32 800a606: 6193 str r3, [r2, #24] 800a608: 4b78 ldr r3, [pc, #480] @ (800a7ec ) 800a60a: 699b ldr r3, [r3, #24] 800a60c: f003 0320 and.w r3, r3, #32 800a610: 603b str r3, [r7, #0] 800a612: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, DBG1_Pin|RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin, GPIO_PIN_RESET); 800a614: 2200 movs r2, #0 800a616: 213c movs r1, #60 @ 0x3c 800a618: 4875 ldr r0, [pc, #468] @ (800a7f0 ) 800a61a: f006 f976 bl 801090a /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, DBG2_Pin|DBG3_Pin|RELAY_CC_Pin, GPIO_PIN_RESET); 800a61e: 2200 movs r2, #0 800a620: f248 0160 movw r1, #32864 @ 0x8060 800a624: 4873 ldr r0, [pc, #460] @ (800a7f4 ) 800a626: f006 f970 bl 801090a /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a62a: 2200 movs r2, #0 800a62c: f44f 51f8 mov.w r1, #7936 @ 0x1f00 800a630: 4871 ldr r0, [pc, #452] @ (800a7f8 ) 800a632: f006 f96a bl 801090a |RELAY5_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, DBG5_Pin|DBG4_Pin|EE_WP_Pin, GPIO_PIN_RESET); 800a636: 2200 movs r2, #0 800a638: f44f 6148 mov.w r1, #3200 @ 0xc80 800a63c: 486f ldr r0, [pc, #444] @ (800a7fc ) 800a63e: f006 f964 bl 801090a /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, RELAY_DC_Pin|USART2_DIR_Pin, GPIO_PIN_RESET); 800a642: 2200 movs r2, #0 800a644: 2118 movs r1, #24 800a646: 486e ldr r0, [pc, #440] @ (800a800 ) 800a648: f006 f95f bl 801090a /*Configure GPIO pin : DBG1_Pin */ GPIO_InitStruct.Pin = DBG1_Pin; 800a64c: 2304 movs r3, #4 800a64e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a650: 2301 movs r3, #1 800a652: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a654: 2300 movs r3, #0 800a656: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a658: 2303 movs r3, #3 800a65a: 623b str r3, [r7, #32] HAL_GPIO_Init(DBG1_GPIO_Port, &GPIO_InitStruct); 800a65c: f107 0314 add.w r3, r7, #20 800a660: 4619 mov r1, r3 800a662: 4863 ldr r0, [pc, #396] @ (800a7f0 ) 800a664: f005 fefa bl 801045c /*Configure GPIO pins : RELAY_CP_Pin LOCK_A_Pin LOCK_B_Pin */ GPIO_InitStruct.Pin = RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin; 800a668: 2338 movs r3, #56 @ 0x38 800a66a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a66c: 2301 movs r3, #1 800a66e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a670: 2300 movs r3, #0 800a672: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a674: 2302 movs r3, #2 800a676: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800a678: f107 0314 add.w r3, r7, #20 800a67c: 4619 mov r1, r3 800a67e: 485c ldr r0, [pc, #368] @ (800a7f0 ) 800a680: f005 feec bl 801045c /*Configure GPIO pin : IN_SW0_Pin */ GPIO_InitStruct.Pin = IN_SW0_Pin; 800a684: 2302 movs r3, #2 800a686: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a688: 2300 movs r3, #0 800a68a: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a68c: 2300 movs r3, #0 800a68e: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW0_GPIO_Port, &GPIO_InitStruct); 800a690: f107 0314 add.w r3, r7, #20 800a694: 4619 mov r1, r3 800a696: 4857 ldr r0, [pc, #348] @ (800a7f4 ) 800a698: f005 fee0 bl 801045c /*Configure GPIO pin : IN_SW1_Pin */ GPIO_InitStruct.Pin = IN_SW1_Pin; 800a69c: 2304 movs r3, #4 800a69e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a6a0: 2300 movs r3, #0 800a6a2: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 800a6a4: 2302 movs r3, #2 800a6a6: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW1_GPIO_Port, &GPIO_InitStruct); 800a6a8: f107 0314 add.w r3, r7, #20 800a6ac: 4619 mov r1, r3 800a6ae: 4851 ldr r0, [pc, #324] @ (800a7f4 ) 800a6b0: f005 fed4 bl 801045c /*Configure GPIO pins : DBG2_Pin DBG3_Pin */ GPIO_InitStruct.Pin = DBG2_Pin|DBG3_Pin; 800a6b4: 2360 movs r3, #96 @ 0x60 800a6b6: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a6b8: 2301 movs r3, #1 800a6ba: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a6bc: 2300 movs r3, #0 800a6be: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a6c0: 2303 movs r3, #3 800a6c2: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800a6c4: f107 0314 add.w r3, r7, #20 800a6c8: 4619 mov r1, r3 800a6ca: 484a ldr r0, [pc, #296] @ (800a7f4 ) 800a6cc: f005 fec6 bl 801045c /*Configure GPIO pins : IN0_Pin AC_OK_Pin ISO_IN_Pin */ GPIO_InitStruct.Pin = IN0_Pin|AC_OK_Pin|ISO_IN_Pin; 800a6d0: f244 0382 movw r3, #16514 @ 0x4082 800a6d4: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a6d6: 2300 movs r3, #0 800a6d8: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a6da: 2300 movs r3, #0 800a6dc: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a6de: f107 0314 add.w r3, r7, #20 800a6e2: 4619 mov r1, r3 800a6e4: 4844 ldr r0, [pc, #272] @ (800a7f8 ) 800a6e6: f005 feb9 bl 801045c /*Configure GPIO pins : RELAY1_Pin RELAY2_Pin RELAY3_Pin RELAY4_Pin RELAY5_Pin */ GPIO_InitStruct.Pin = RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a6ea: f44f 53f8 mov.w r3, #7936 @ 0x1f00 800a6ee: 617b str r3, [r7, #20] |RELAY5_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a6f0: 2301 movs r3, #1 800a6f2: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a6f4: 2300 movs r3, #0 800a6f6: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a6f8: 2302 movs r3, #2 800a6fa: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a6fc: f107 0314 add.w r3, r7, #20 800a700: 4619 mov r1, r3 800a702: 483d ldr r0, [pc, #244] @ (800a7f8 ) 800a704: f005 feaa bl 801045c /*Configure GPIO pins : DBG5_Pin DBG4_Pin */ GPIO_InitStruct.Pin = DBG5_Pin|DBG4_Pin; 800a708: f44f 6340 mov.w r3, #3072 @ 0xc00 800a70c: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a70e: 2301 movs r3, #1 800a710: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a712: 2300 movs r3, #0 800a714: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a716: 2303 movs r3, #3 800a718: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a71a: f107 0314 add.w r3, r7, #20 800a71e: 4619 mov r1, r3 800a720: 4836 ldr r0, [pc, #216] @ (800a7fc ) 800a722: f005 fe9b bl 801045c /*Configure GPIO pin : RELAY_CC_Pin */ GPIO_InitStruct.Pin = RELAY_CC_Pin; 800a726: f44f 4300 mov.w r3, #32768 @ 0x8000 800a72a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a72c: 2301 movs r3, #1 800a72e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a730: 2300 movs r3, #0 800a732: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a734: 2302 movs r3, #2 800a736: 623b str r3, [r7, #32] HAL_GPIO_Init(RELAY_CC_GPIO_Port, &GPIO_InitStruct); 800a738: f107 0314 add.w r3, r7, #20 800a73c: 4619 mov r1, r3 800a73e: 482d ldr r0, [pc, #180] @ (800a7f4 ) 800a740: f005 fe8c bl 801045c /*Configure GPIO pins : RELAY_DC_Pin USART2_DIR_Pin */ GPIO_InitStruct.Pin = RELAY_DC_Pin|USART2_DIR_Pin; 800a744: 2318 movs r3, #24 800a746: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a748: 2301 movs r3, #1 800a74a: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a74c: 2300 movs r3, #0 800a74e: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a750: 2302 movs r3, #2 800a752: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800a754: f107 0314 add.w r3, r7, #20 800a758: 4619 mov r1, r3 800a75a: 4829 ldr r0, [pc, #164] @ (800a800 ) 800a75c: f005 fe7e bl 801045c /*Configure GPIO pin : IN_ESTOP_Pin */ GPIO_InitStruct.Pin = IN_ESTOP_Pin; 800a760: 2380 movs r3, #128 @ 0x80 800a762: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a764: 2300 movs r3, #0 800a766: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a768: 2300 movs r3, #0 800a76a: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_ESTOP_GPIO_Port, &GPIO_InitStruct); 800a76c: f107 0314 add.w r3, r7, #20 800a770: 4619 mov r1, r3 800a772: 4823 ldr r0, [pc, #140] @ (800a800 ) 800a774: f005 fe72 bl 801045c /*Configure GPIO pins : IN_FB2_Pin IN_FB1_Pin */ GPIO_InitStruct.Pin = IN_FB2_Pin|IN_FB1_Pin; 800a778: 2318 movs r3, #24 800a77a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a77c: 2300 movs r3, #0 800a77e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a780: 2300 movs r3, #0 800a782: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a784: f107 0314 add.w r3, r7, #20 800a788: 4619 mov r1, r3 800a78a: 481c ldr r0, [pc, #112] @ (800a7fc ) 800a78c: f005 fe66 bl 801045c /*Configure GPIO pin : EE_WP_Pin */ GPIO_InitStruct.Pin = EE_WP_Pin; 800a790: 2380 movs r3, #128 @ 0x80 800a792: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a794: 2301 movs r3, #1 800a796: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a798: 2300 movs r3, #0 800a79a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a79c: 2302 movs r3, #2 800a79e: 623b str r3, [r7, #32] HAL_GPIO_Init(EE_WP_GPIO_Port, &GPIO_InitStruct); 800a7a0: f107 0314 add.w r3, r7, #20 800a7a4: 4619 mov r1, r3 800a7a6: 4815 ldr r0, [pc, #84] @ (800a7fc ) 800a7a8: f005 fe58 bl 801045c /*Configure GPIO pins : PB8 PB9 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 800a7ac: f44f 7340 mov.w r3, #768 @ 0x300 800a7b0: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 800a7b2: 2312 movs r3, #18 800a7b4: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a7b6: 2303 movs r3, #3 800a7b8: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a7ba: f107 0314 add.w r3, r7, #20 800a7be: 4619 mov r1, r3 800a7c0: 480e ldr r0, [pc, #56] @ (800a7fc ) 800a7c2: f005 fe4b bl 801045c /*Configure peripheral I/O remapping */ __HAL_AFIO_REMAP_I2C1_ENABLE(); 800a7c6: 4b0f ldr r3, [pc, #60] @ (800a804 ) 800a7c8: 685b ldr r3, [r3, #4] 800a7ca: 627b str r3, [r7, #36] @ 0x24 800a7cc: 6a7b ldr r3, [r7, #36] @ 0x24 800a7ce: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800a7d2: 627b str r3, [r7, #36] @ 0x24 800a7d4: 6a7b ldr r3, [r7, #36] @ 0x24 800a7d6: f043 0302 orr.w r3, r3, #2 800a7da: 627b str r3, [r7, #36] @ 0x24 800a7dc: 4a09 ldr r2, [pc, #36] @ (800a804 ) 800a7de: 6a7b ldr r3, [r7, #36] @ 0x24 800a7e0: 6053 str r3, [r2, #4] } 800a7e2: bf00 nop 800a7e4: 3728 adds r7, #40 @ 0x28 800a7e6: 46bd mov sp, r7 800a7e8: bd80 pop {r7, pc} 800a7ea: bf00 nop 800a7ec: 40021000 .word 0x40021000 800a7f0: 40011000 .word 0x40011000 800a7f4: 40010800 .word 0x40010800 800a7f8: 40011800 .word 0x40011800 800a7fc: 40010c00 .word 0x40010c00 800a800: 40011400 .word 0x40011400 800a804: 40010000 .word 0x40010000 0800a808 <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 800a808: b480 push {r7} 800a80a: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 800a80c: f3bf 8f4f dsb sy } 800a810: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800a812: 4b06 ldr r3, [pc, #24] @ (800a82c <__NVIC_SystemReset+0x24>) 800a814: 68db ldr r3, [r3, #12] 800a816: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800a81a: 4904 ldr r1, [pc, #16] @ (800a82c <__NVIC_SystemReset+0x24>) 800a81c: 4b04 ldr r3, [pc, #16] @ (800a830 <__NVIC_SystemReset+0x28>) 800a81e: 4313 orrs r3, r2 800a820: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800a822: f3bf 8f4f dsb sy } 800a826: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 800a828: bf00 nop 800a82a: e7fd b.n 800a828 <__NVIC_SystemReset+0x20> 800a82c: e000ed00 .word 0xe000ed00 800a830: 05fa0004 .word 0x05fa0004 0800a834 : * bootloader before starting this program. Unfortunately, function * SystemInit() overwrites this change again. * @return none. */ static void VectorBase_Config(void) { 800a834: b480 push {r7} 800a836: af00 add r7, sp, #0 * c-startup code. */ extern const unsigned long g_pfnVectors[]; /* Remap the vector table to where the vector table is located for this program. */ SCB->VTOR = (unsigned long)&g_pfnVectors[0]; 800a838: 4b03 ldr r3, [pc, #12] @ (800a848 ) 800a83a: 4a04 ldr r2, [pc, #16] @ (800a84c ) 800a83c: 609a str r2, [r3, #8] } 800a83e: bf00 nop 800a840: 46bd mov sp, r7 800a842: bc80 pop {r7} 800a844: 4770 bx lr 800a846: bf00 nop 800a848: e000ed00 .word 0xe000ed00 800a84c: 08008000 .word 0x08008000 0800a850 : uint8_t ED_TraceWarning(uint8_t flag, uint8_t id){ 800a850: b480 push {r7} 800a852: b085 sub sp, #20 800a854: af00 add r7, sp, #0 800a856: 4603 mov r3, r0 800a858: 460a mov r2, r1 800a85a: 71fb strb r3, [r7, #7] 800a85c: 4613 mov r3, r2 800a85e: 71bb strb r3, [r7, #6] static uint8_t memory[32]; if(id > 31) return 0; 800a860: 79bb ldrb r3, [r7, #6] 800a862: 2b1f cmp r3, #31 800a864: d901 bls.n 800a86a 800a866: 2300 movs r3, #0 800a868: e00e b.n 800a888 uint8_t result = 0; 800a86a: 2300 movs r3, #0 800a86c: 73fb strb r3, [r7, #15] if(memory[id] != flag){ 800a86e: 79bb ldrb r3, [r7, #6] 800a870: 4a08 ldr r2, [pc, #32] @ (800a894 ) 800a872: 5cd3 ldrb r3, [r2, r3] 800a874: 79fa ldrb r2, [r7, #7] 800a876: 429a cmp r2, r3 800a878: d001 beq.n 800a87e result = 1; 800a87a: 2301 movs r3, #1 800a87c: 73fb strb r3, [r7, #15] } memory[id] = flag; 800a87e: 79bb ldrb r3, [r7, #6] 800a880: 4904 ldr r1, [pc, #16] @ (800a894 ) 800a882: 79fa ldrb r2, [r7, #7] 800a884: 54ca strb r2, [r1, r3] return result; 800a886: 7bfb ldrb r3, [r7, #15] } 800a888: 4618 mov r0, r3 800a88a: 3714 adds r7, #20 800a88c: 46bd mov sp, r7 800a88e: bc80 pop {r7} 800a890: 4770 bx lr 800a892: bf00 nop 800a894: 2000086c .word 0x2000086c 0800a898 : void ED_Delay(uint32_t Delay) { 800a898: b580 push {r7, lr} 800a89a: b084 sub sp, #16 800a89c: af00 add r7, sp, #0 800a89e: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800a8a0: f003 fbb8 bl 800e014 800a8a4: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800a8a6: 687b ldr r3, [r7, #4] 800a8a8: 60fb str r3, [r7, #12] if (wait < HAL_MAX_DELAY) 800a8aa: 68fb ldr r3, [r7, #12] 800a8ac: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800a8b0: d012 beq.n 800a8d8 { wait += (uint32_t)(uwTickFreq); 800a8b2: 4b10 ldr r3, [pc, #64] @ (800a8f4 ) 800a8b4: 781b ldrb r3, [r3, #0] 800a8b6: 461a mov r2, r3 800a8b8: 68fb ldr r3, [r7, #12] 800a8ba: 4413 add r3, r2 800a8bc: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait){ 800a8be: e00b b.n 800a8d8 CCS_SerialLoop(); 800a8c0: f001 f9fc bl 800bcbc StopButtonControl(); 800a8c4: f000 f818 bl 800a8f8 CP_Loop(); 800a8c8: f7ff fca8 bl 800a21c CONN_Task(); 800a8cc: f7ff fad8 bl 8009e80 LED_Task(); 800a8d0: f001 f814 bl 800b8fc SC_Task(); 800a8d4: f001 fffc bl 800c8d0 while ((HAL_GetTick() - tickstart) < wait){ 800a8d8: f003 fb9c bl 800e014 800a8dc: 4602 mov r2, r0 800a8de: 68bb ldr r3, [r7, #8] 800a8e0: 1ad3 subs r3, r2, r3 800a8e2: 68fa ldr r2, [r7, #12] 800a8e4: 429a cmp r2, r3 800a8e6: d8eb bhi.n 800a8c0 } } 800a8e8: bf00 nop 800a8ea: bf00 nop 800a8ec: 3710 adds r7, #16 800a8ee: 46bd mov sp, r7 800a8f0: bd80 pop {r7, pc} 800a8f2: bf00 nop 800a8f4: 2000008c .word 0x2000008c 0800a8f8 : void StopButtonControl(){ 800a8f8: b580 push {r7, lr} 800a8fa: b082 sub sp, #8 800a8fc: af00 add r7, sp, #0 static uint32_t tick; static uint32_t hold_time; static uint8_t stop_btn_fault = 1; uint32_t now = HAL_GetTick(); 800a8fe: f003 fb89 bl 800e014 800a902: 6078 str r0, [r7, #4] /* Run no faster than once per 10 ms. */ if((now - tick) < 10){ 800a904: 4b2a ldr r3, [pc, #168] @ (800a9b0 ) 800a906: 681b ldr r3, [r3, #0] 800a908: 687a ldr r2, [r7, #4] 800a90a: 1ad3 subs r3, r2, r3 800a90c: 2b09 cmp r3, #9 800a90e: d949 bls.n 800a9a4 return; } tick = now; 800a910: 4a27 ldr r2, [pc, #156] @ (800a9b0 ) 800a912: 687b ldr r3, [r7, #4] 800a914: 6013 str r3, [r2, #0] uint8_t pressed = !IN_ReadInput(IN_ESTOP); 800a916: 2003 movs r0, #3 800a918: f7fe ffce bl 80098b8 800a91c: 4603 mov r3, r0 800a91e: 2b00 cmp r3, #0 800a920: bf0c ite eq 800a922: 2301 moveq r3, #1 800a924: 2300 movne r3, #0 800a926: b2db uxtb r3, r3 800a928: 70fb strb r3, [r7, #3] if(!pressed){ 800a92a: 78fb ldrb r3, [r7, #3] 800a92c: 2b00 cmp r3, #0 800a92e: d102 bne.n 800a936 stop_btn_fault = 0; 800a930: 4b20 ldr r3, [pc, #128] @ (800a9b4 ) 800a932: 2200 movs r2, #0 800a934: 701a strb r2, [r3, #0] } if(stop_btn_fault){ 800a936: 4b1f ldr r3, [pc, #124] @ (800a9b4 ) 800a938: 781b ldrb r3, [r3, #0] 800a93a: 2b00 cmp r3, #0 800a93c: d134 bne.n 800a9a8 return; } if(pressed){ 800a93e: 78fb ldrb r3, [r7, #3] 800a940: 2b00 cmp r3, #0 800a942: d02b beq.n 800a99c if(hold_time == 0){ 800a944: 4b1c ldr r3, [pc, #112] @ (800a9b8 ) 800a946: 681b ldr r3, [r3, #0] 800a948: 2b00 cmp r3, #0 800a94a: d102 bne.n 800a952 CONN.connControl = CMD_STOP; 800a94c: 4b1b ldr r3, [pc, #108] @ (800a9bc ) 800a94e: 2201 movs r2, #1 800a950: 701a strb r2, [r3, #0] } hold_time += 10; 800a952: 4b19 ldr r3, [pc, #100] @ (800a9b8 ) 800a954: 681b ldr r3, [r3, #0] 800a956: 330a adds r3, #10 800a958: 4a17 ldr r2, [pc, #92] @ (800a9b8 ) 800a95a: 6013 str r3, [r2, #0] if(hold_time == 5000){ 800a95c: 4b16 ldr r3, [pc, #88] @ (800a9b8 ) 800a95e: 681b ldr r3, [r3, #0] 800a960: f241 3288 movw r2, #5000 @ 0x1388 800a964: 4293 cmp r3, r2 800a966: d102 bne.n 800a96e CONN.connControl = CMD_FORCE_UNLOCK; 800a968: 4b14 ldr r3, [pc, #80] @ (800a9bc ) 800a96a: 2203 movs r2, #3 800a96c: 701a strb r2, [r3, #0] } if(hold_time > 40000){ 800a96e: 4b12 ldr r3, [pc, #72] @ (800a9b8 ) 800a970: 681b ldr r3, [r3, #0] 800a972: f649 4240 movw r2, #40000 @ 0x9c40 800a976: 4293 cmp r3, r2 800a978: d917 bls.n 800a9aa SC_SendPacket(NULL, 0, RESP_SUCCESS); 800a97a: 2212 movs r2, #18 800a97c: 2100 movs r1, #0 800a97e: 2000 movs r0, #0 800a980: f002 f92a bl 800cbd8 while(huart2.gState == HAL_UART_STATE_BUSY_TX); 800a984: bf00 nop 800a986: 4b0e ldr r3, [pc, #56] @ (800a9c0 ) 800a988: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800a98c: b2db uxtb r3, r3 800a98e: 2b21 cmp r3, #33 @ 0x21 800a990: d0f9 beq.n 800a986 HAL_Delay(10); 800a992: 200a movs r0, #10 800a994: f003 fb48 bl 800e028 NVIC_SystemReset(); 800a998: f7ff ff36 bl 800a808 <__NVIC_SystemReset> } } else{ hold_time = 0; 800a99c: 4b06 ldr r3, [pc, #24] @ (800a9b8 ) 800a99e: 2200 movs r2, #0 800a9a0: 601a str r2, [r3, #0] 800a9a2: e002 b.n 800a9aa return; 800a9a4: bf00 nop 800a9a6: e000 b.n 800a9aa return; 800a9a8: bf00 nop } } 800a9aa: 3708 adds r7, #8 800a9ac: 46bd mov sp, r7 800a9ae: bd80 pop {r7, pc} 800a9b0: 2000088c .word 0x2000088c 800a9b4: 20000008 .word 0x20000008 800a9b8: 20000890 .word 0x20000890 800a9bc: 200003b0 .word 0x200003b0 800a9c0: 200011e0 .word 0x200011e0 0800a9c4 : uint8_t temp0, temp1; static void CAN1_MinimalReInit(void) { 800a9c4: b580 push {r7, lr} 800a9c6: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan1); 800a9c8: 480b ldr r0, [pc, #44] @ (800a9f8 ) 800a9ca: f004 fab1 bl 800ef30 MX_CAN1_Init(); 800a9ce: f7ff f8b7 bl 8009b40 if (HAL_CAN_Start(&hcan1) != HAL_OK) { 800a9d2: 4809 ldr r0, [pc, #36] @ (800a9f8 ) 800a9d4: f004 fa68 bl 800eea8 800a9d8: 4603 mov r3, r0 800a9da: 2b00 cmp r3, #0 800a9dc: d001 beq.n 800a9e2 Error_Handler(); 800a9de: f000 f8f7 bl 800abd0 } if (HAL_CAN_ActivateNotification(&hcan1, CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) { 800a9e2: 2102 movs r1, #2 800a9e4: 4804 ldr r0, [pc, #16] @ (800a9f8 ) 800a9e6: f004 fd10 bl 800f40a 800a9ea: 4603 mov r3, r0 800a9ec: 2b00 cmp r3, #0 800a9ee: d001 beq.n 800a9f4 Error_Handler(); 800a9f0: f000 f8ee bl 800abd0 } } 800a9f4: bf00 nop 800a9f6: bd80 pop {r7, pc} 800a9f8: 2000035c .word 0x2000035c 0800a9fc
: /** * @brief The application entry point. * @retval int */ int main(void) { 800a9fc: b580 push {r7, lr} 800a9fe: b082 sub sp, #8 800aa00: af02 add r7, sp, #8 /* USER CODE BEGIN 1 */ VectorBase_Config(); 800aa02: f7ff ff17 bl 800a834 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800aa06: f003 faad bl 800df64 /* USER CODE BEGIN Init */ HAL_RCC_DeInit(); 800aa0a: f005 ffa3 bl 8010954 /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800aa0e: f000 f86f bl 800aaf0 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800aa12: f7ff fdb9 bl 800a588 MX_DMA_Init(); 800aa16: f7ff fd99 bl 800a54c MX_ADC1_Init(); 800aa1a: f7fe fdbd bl 8009598 MX_CAN1_Init(); 800aa1e: f7ff f88f bl 8009b40 MX_CAN2_Init(); 800aa22: f7ff f8c3 bl 8009bac MX_RTC_Init(); 800aa26: f001 f807 bl 800ba38 MX_TIM4_Init(); 800aa2a: f002 feed bl 800d808 MX_USART2_UART_Init(); 800aa2e: f003 f86b bl 800db08 MX_CRC_Init(); 800aa32: f7ff fc3d bl 800a2b0 MX_UART5_Init(); 800aa36: f003 f813 bl 800da60 MX_USART1_UART_Init(); 800aa3a: f003 f83b bl 800dab4 MX_USART3_UART_Init(); 800aa3e: f003 f88d bl 800db5c MX_TIM3_Init(); 800aa42: f002 fe53 bl 800d6ec /* USER CODE BEGIN 2 */ Init_Peripheral(); 800aa46: f7fe ff89 bl 800995c LED_Init(); 800aa4a: f000 ff37 bl 800b8bc HAL_Delay(300); 800aa4e: f44f 7096 mov.w r0, #300 @ 0x12c 800aa52: f003 fae9 bl 800e028 CCS_Init(); 800aa56: f001 fbc3 bl 800c1e0 SC_Init(); 800aa5a: f001 ff0d bl 800c878 log_printf(LOG_INFO, "CCS module start\n"); 800aa5e: 491f ldr r1, [pc, #124] @ (800aadc ) 800aa60: 2007 movs r0, #7 800aa62: f7ff fd3d bl 800a4e0 ReadVersion(); 800aa66: f001 fee3 bl 800c830 log_printf(LOG_INFO, "Serial number: %d\n", infoPacket.serialNumber); 800aa6a: 4b1d ldr r3, [pc, #116] @ (800aae0 ) 800aa6c: 881b ldrh r3, [r3, #0] 800aa6e: b29b uxth r3, r3 800aa70: 461a mov r2, r3 800aa72: 491c ldr r1, [pc, #112] @ (800aae4 ) 800aa74: 2007 movs r0, #7 800aa76: f7ff fd33 bl 800a4e0 log_printf(LOG_INFO, "Board revision: %d\n", infoPacket.boardVersion); 800aa7a: 4b19 ldr r3, [pc, #100] @ (800aae0 ) 800aa7c: 789b ldrb r3, [r3, #2] 800aa7e: 461a mov r2, r3 800aa80: 4919 ldr r1, [pc, #100] @ (800aae8 ) 800aa82: 2007 movs r0, #7 800aa84: f7ff fd2c bl 800a4e0 log_printf(LOG_INFO, "FW version: %d.%d.%d\n", infoPacket.fw_version_major, infoPacket.fw_version_minor, infoPacket.fw_version_patch); 800aa88: 4b15 ldr r3, [pc, #84] @ (800aae0 ) 800aa8a: 889b ldrh r3, [r3, #4] 800aa8c: b29b uxth r3, r3 800aa8e: 461a mov r2, r3 800aa90: 4b13 ldr r3, [pc, #76] @ (800aae0 ) 800aa92: 88db ldrh r3, [r3, #6] 800aa94: b29b uxth r3, r3 800aa96: 4619 mov r1, r3 800aa98: 4b11 ldr r3, [pc, #68] @ (800aae0 ) 800aa9a: 891b ldrh r3, [r3, #8] 800aa9c: b29b uxth r3, r3 800aa9e: 9300 str r3, [sp, #0] 800aaa0: 460b mov r3, r1 800aaa2: 4912 ldr r1, [pc, #72] @ (800aaec ) 800aaa4: 2007 movs r0, #7 800aaa6: f7ff fd1b bl 800a4e0 CAN1_MinimalReInit(); 800aaaa: f7ff ff8b bl 800a9c4 PSU_Init(); 800aaae: f000 f9e9 bl 800ae84 CONN_Init(); 800aab2: f7ff f98f bl 8009dd4 /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ PSU_ReadWrite(); 800aab6: f000 faf7 bl 800b0a8 PSU_Task(); 800aaba: f000 fbbb bl 800b234 ED_Delay(10); 800aabe: 200a movs r0, #10 800aac0: f7ff feea bl 800a898 METER_CalculateEnergy(); 800aac4: f000 f88a bl 800abdc CONN_Loop(); 800aac8: f7ff f99a bl 8009e00 LED_Write(); 800aacc: f000 fda8 bl 800b620 ED_Delay(10); 800aad0: 200a movs r0, #10 800aad2: f7ff fee1 bl 800a898 { 800aad6: bf00 nop 800aad8: e7ed b.n 800aab6 800aada: bf00 nop 800aadc: 08016b7c .word 0x08016b7c 800aae0: 200010b0 .word 0x200010b0 800aae4: 08016b90 .word 0x08016b90 800aae8: 08016ba4 .word 0x08016ba4 800aaec: 08016bb8 .word 0x08016bb8 0800aaf0 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800aaf0: b580 push {r7, lr} 800aaf2: b09c sub sp, #112 @ 0x70 800aaf4: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800aaf6: f107 0338 add.w r3, r7, #56 @ 0x38 800aafa: 2238 movs r2, #56 @ 0x38 800aafc: 2100 movs r1, #0 800aafe: 4618 mov r0, r3 800ab00: f009 fe1c bl 801473c RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800ab04: f107 0324 add.w r3, r7, #36 @ 0x24 800ab08: 2200 movs r2, #0 800ab0a: 601a str r2, [r3, #0] 800ab0c: 605a str r2, [r3, #4] 800ab0e: 609a str r2, [r3, #8] 800ab10: 60da str r2, [r3, #12] 800ab12: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 800ab14: 1d3b adds r3, r7, #4 800ab16: 2220 movs r2, #32 800ab18: 2100 movs r1, #0 800ab1a: 4618 mov r0, r3 800ab1c: f009 fe0e bl 801473c /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; 800ab20: 2305 movs r3, #5 800ab22: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 800ab24: f44f 3380 mov.w r3, #65536 @ 0x10000 800ab28: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV5; 800ab2a: 2304 movs r3, #4 800ab2c: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 800ab2e: 2301 movs r3, #1 800ab30: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800ab32: 2301 movs r3, #1 800ab34: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.Prediv1Source = RCC_PREDIV1_SOURCE_PLL2; 800ab36: f44f 3380 mov.w r3, #65536 @ 0x10000 800ab3a: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800ab3c: 2302 movs r3, #2 800ab3e: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800ab40: f44f 3380 mov.w r3, #65536 @ 0x10000 800ab44: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 800ab46: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000 800ab4a: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL2.PLL2State = RCC_PLL2_ON; 800ab4c: 2302 movs r3, #2 800ab4e: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL2.PLL2MUL = RCC_PLL2_MUL8; 800ab50: f44f 63c0 mov.w r3, #1536 @ 0x600 800ab54: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL2.HSEPrediv2Value = RCC_HSE_PREDIV2_DIV5; 800ab56: 2340 movs r3, #64 @ 0x40 800ab58: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800ab5a: f107 0338 add.w r3, r7, #56 @ 0x38 800ab5e: 4618 mov r0, r3 800ab60: f005 ffc8 bl 8010af4 800ab64: 4603 mov r3, r0 800ab66: 2b00 cmp r3, #0 800ab68: d001 beq.n 800ab6e { Error_Handler(); 800ab6a: f000 f831 bl 800abd0 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800ab6e: 230f movs r3, #15 800ab70: 627b str r3, [r7, #36] @ 0x24 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800ab72: 2302 movs r3, #2 800ab74: 62bb str r3, [r7, #40] @ 0x28 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800ab76: 2300 movs r3, #0 800ab78: 62fb str r3, [r7, #44] @ 0x2c RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 800ab7a: f44f 6380 mov.w r3, #1024 @ 0x400 800ab7e: 633b str r3, [r7, #48] @ 0x30 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 800ab80: 2300 movs r3, #0 800ab82: 637b str r3, [r7, #52] @ 0x34 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800ab84: f107 0324 add.w r3, r7, #36 @ 0x24 800ab88: 2102 movs r1, #2 800ab8a: 4618 mov r0, r3 800ab8c: f006 fac8 bl 8011120 800ab90: 4603 mov r3, r0 800ab92: 2b00 cmp r3, #0 800ab94: d001 beq.n 800ab9a { Error_Handler(); 800ab96: f000 f81b bl 800abd0 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC; 800ab9a: 2303 movs r3, #3 800ab9c: 607b str r3, [r7, #4] PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 800ab9e: f44f 7380 mov.w r3, #256 @ 0x100 800aba2: 60bb str r3, [r7, #8] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 800aba4: f44f 4300 mov.w r3, #32768 @ 0x8000 800aba8: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 800abaa: 1d3b adds r3, r7, #4 800abac: 4618 mov r0, r3 800abae: f006 fcad bl 801150c 800abb2: 4603 mov r3, r0 800abb4: 2b00 cmp r3, #0 800abb6: d001 beq.n 800abbc { Error_Handler(); 800abb8: f000 f80a bl 800abd0 } /** Configure the Systick interrupt time */ __HAL_RCC_PLLI2S_ENABLE(); 800abbc: 4b03 ldr r3, [pc, #12] @ (800abcc ) 800abbe: 2201 movs r2, #1 800abc0: 601a str r2, [r3, #0] } 800abc2: bf00 nop 800abc4: 3770 adds r7, #112 @ 0x70 800abc6: 46bd mov sp, r7 800abc8: bd80 pop {r7, pc} 800abca: bf00 nop 800abcc: 42420070 .word 0x42420070 0800abd0 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 800abd0: b480 push {r7} 800abd2: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800abd4: b672 cpsid i } 800abd6: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 800abd8: bf00 nop 800abda: e7fd b.n 800abd8 0800abdc : METER_t METER; // Функция для расчета и накопления энергии c дробной частью без счетчиков void METER_CalculateEnergy() { 800abdc: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} 800abe0: b084 sub sp, #16 800abe2: af00 add r7, sp, #0 // Проверяем, что индекс находится в пределах массива METER.online = 0; 800abe4: 4b2e ldr r3, [pc, #184] @ (800aca0 ) 800abe6: 2200 movs r2, #0 800abe8: 711a strb r2, [r3, #4] if(CONN.connState == Charging){ 800abea: 4b2e ldr r3, [pc, #184] @ (800aca4 ) 800abec: 785b ldrb r3, [r3, #1] 800abee: 2b08 cmp r3, #8 800abf0: d104 bne.n 800abfc METER.enable = 1; 800abf2: 4b2b ldr r3, [pc, #172] @ (800aca0 ) 800abf4: 2201 movs r2, #1 800abf6: f883 2024 strb.w r2, [r3, #36] @ 0x24 800abfa: e003 b.n 800ac04 }else{ METER.enable = 0; 800abfc: 4b28 ldr r3, [pc, #160] @ (800aca0 ) 800abfe: 2200 movs r2, #0 800ac00: f883 2024 strb.w r2, [r3, #36] @ 0x24 } uint32_t currentTick = HAL_GetTick(); // Получаем текущее время в миллисекундах 800ac04: f003 fa06 bl 800e014 800ac08: 60f8 str r0, [r7, #12] uint32_t elapsedTimeMs = currentTick - METER.lastTick; // Вычисляем время, прошедшее с последнего вызова в секундах 800ac0a: 4b25 ldr r3, [pc, #148] @ (800aca0 ) 800ac0c: 689b ldr r3, [r3, #8] 800ac0e: 68fa ldr r2, [r7, #12] 800ac10: 1ad3 subs r3, r2, r3 800ac12: 60bb str r3, [r7, #8] METER.lastTick = currentTick; // Обновляем время последнего вызова для текущего коннектора 800ac14: 4a22 ldr r2, [pc, #136] @ (800aca0 ) 800ac16: 68fb ldr r3, [r7, #12] 800ac18: 6093 str r3, [r2, #8] uint32_t energyWs = CONN.Power * elapsedTimeMs / 1000; // Рассчитываем энергию в ватт-секундах за прошедший промежуток времени 800ac1a: 4b22 ldr r3, [pc, #136] @ (800aca4 ) 800ac1c: f8d3 3003 ldr.w r3, [r3, #3] 800ac20: 68ba ldr r2, [r7, #8] 800ac22: fb02 f303 mul.w r3, r2, r3 800ac26: 4a20 ldr r2, [pc, #128] @ (800aca8 ) 800ac28: fba2 2303 umull r2, r3, r2, r3 800ac2c: 099b lsrs r3, r3, #6 800ac2e: 607b str r3, [r7, #4] //Расчет энергии теперь идет всегда, смещение берем суммарное METER.EnergyPSU_Ws += energyWs; 800ac30: 4b1b ldr r3, [pc, #108] @ (800aca0 ) 800ac32: e9d3 2304 ldrd r2, r3, [r3, #16] 800ac36: 6879 ldr r1, [r7, #4] 800ac38: 2000 movs r0, #0 800ac3a: 460c mov r4, r1 800ac3c: 4605 mov r5, r0 800ac3e: eb12 0804 adds.w r8, r2, r4 800ac42: eb43 0905 adc.w r9, r3, r5 800ac46: 4b16 ldr r3, [pc, #88] @ (800aca0 ) 800ac48: e9c3 8904 strd r8, r9, [r3, #16] // Абсолютное значение энергии разъема складывается из накопленной дробной части и значения со счетчиков METER.AbsoluteEnergy = (uint32_t)METER.EnergyPSU_Ws/3600; //переводим в Вт*час 800ac4c: 4b14 ldr r3, [pc, #80] @ (800aca0 ) 800ac4e: e9d3 2304 ldrd r2, r3, [r3, #16] 800ac52: 4b16 ldr r3, [pc, #88] @ (800acac ) 800ac54: fba3 2302 umull r2, r3, r3, r2 800ac58: 0adb lsrs r3, r3, #11 800ac5a: 4a11 ldr r2, [pc, #68] @ (800aca0 ) 800ac5c: 6193 str r3, [r2, #24] if(METER.enable) { 800ac5e: 4b10 ldr r3, [pc, #64] @ (800aca0 ) 800ac60: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800ac64: 2b00 cmp r3, #0 800ac66: d008 beq.n 800ac7a //enabled state CONN.Energy = METER.AbsoluteEnergy - METER.EnergyOffset;//переводим в Вт*час 800ac68: 4b0d ldr r3, [pc, #52] @ (800aca0 ) 800ac6a: 699a ldr r2, [r3, #24] 800ac6c: 4b0c ldr r3, [pc, #48] @ (800aca0 ) 800ac6e: 69db ldr r3, [r3, #28] 800ac70: 1ad3 subs r3, r2, r3 800ac72: 4a0c ldr r2, [pc, #48] @ (800aca4 ) 800ac74: f8c2 3007 str.w r3, [r2, #7] METER.EnergyOffset = METER.AbsoluteEnergy; } } 800ac78: e00c b.n 800ac94 CONN.Energy = 0; 800ac7a: 4b0a ldr r3, [pc, #40] @ (800aca4 ) 800ac7c: 2200 movs r2, #0 800ac7e: 71da strb r2, [r3, #7] 800ac80: 2200 movs r2, #0 800ac82: 721a strb r2, [r3, #8] 800ac84: 2200 movs r2, #0 800ac86: 725a strb r2, [r3, #9] 800ac88: 2200 movs r2, #0 800ac8a: 729a strb r2, [r3, #10] METER.EnergyOffset = METER.AbsoluteEnergy; 800ac8c: 4b04 ldr r3, [pc, #16] @ (800aca0 ) 800ac8e: 699b ldr r3, [r3, #24] 800ac90: 4a03 ldr r2, [pc, #12] @ (800aca0 ) 800ac92: 61d3 str r3, [r2, #28] } 800ac94: bf00 nop 800ac96: 3710 adds r7, #16 800ac98: 46bd mov sp, r7 800ac9a: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} 800ac9e: bf00 nop 800aca0: 20000898 .word 0x20000898 800aca4: 200003b0 .word 0x200003b0 800aca8: 10624dd3 .word 0x10624dd3 800acac: 91a2b3c5 .word 0x91a2b3c5 0800acb0 : uint32_t can_lastpacket; extern CAN_HandleTypeDef hcan2; static void PSU_SwitchState(PSU_State_t state){ 800acb0: b580 push {r7, lr} 800acb2: b082 sub sp, #8 800acb4: af00 add r7, sp, #0 800acb6: 4603 mov r3, r0 800acb8: 71fb strb r3, [r7, #7] PSU0.state = state; 800acba: 4a06 ldr r2, [pc, #24] @ (800acd4 ) 800acbc: 79fb ldrb r3, [r7, #7] 800acbe: 71d3 strb r3, [r2, #7] PSU0.statetick = HAL_GetTick(); 800acc0: f003 f9a8 bl 800e014 800acc4: 4603 mov r3, r0 800acc6: 4a03 ldr r2, [pc, #12] @ (800acd4 ) 800acc8: 6113 str r3, [r2, #16] } 800acca: bf00 nop 800accc: 3708 adds r7, #8 800acce: 46bd mov sp, r7 800acd0: bd80 pop {r7, pc} 800acd2: bf00 nop 800acd4: 20000904 .word 0x20000904 0800acd8 : static uint32_t PSU_StateTime(void){ 800acd8: b580 push {r7, lr} 800acda: af00 add r7, sp, #0 return HAL_GetTick() - PSU0.statetick; 800acdc: f003 f99a bl 800e014 800ace0: 4602 mov r2, r0 800ace2: 4b02 ldr r3, [pc, #8] @ (800acec ) 800ace4: 691b ldr r3, [r3, #16] 800ace6: 1ad3 subs r3, r2, r3 } 800ace8: 4618 mov r0, r3 800acea: bd80 pop {r7, pc} 800acec: 20000904 .word 0x20000904 0800acf0 : ISR_FAST void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan){ 800acf0: b538 push {r3, r4, r5, lr} static CAN_RxHeaderTypeDef RxHeader; static uint8_t RxData[8] = {0,}; CanId_t CanId; if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO1, &RxHeader, RxData) == HAL_OK) 800acf2: 4c42 ldr r4, [pc, #264] @ (800adfc ) 800acf4: 4d42 ldr r5, [pc, #264] @ (800ae00 ) 800acf6: 4623 mov r3, r4 800acf8: 462a mov r2, r5 800acfa: 2101 movs r1, #1 800acfc: f004 fa64 bl 800f1c8 800ad00: b910 cbnz r0, 800ad08 { memcpy(&CanId, &RxHeader.ExtId, sizeof(CanId_t)); 800ad02: 686d ldr r5, [r5, #4] /* Для DC30 поддерживается только один силовой модуль (source == 0) */ if(CanId.source != 0) return; 800ad04: b2eb uxtb r3, r5 800ad06: b103 cbz r3, 800ad0a CONN.outputEnabled = PSU0.PSU_enabled; } } } } } 800ad08: bd38 pop {r3, r4, r5, pc} can_lastpacket = HAL_GetTick(); 800ad0a: f003 f983 bl 800e014 if(CanId.command==0x02){ 800ad0e: f3c5 4505 ubfx r5, r5, #16, #6 can_lastpacket = HAL_GetTick(); 800ad12: 4b3c ldr r3, [pc, #240] @ (800ae04 ) if(CanId.command==0x02){ 800ad14: 2d02 cmp r5, #2 can_lastpacket = HAL_GetTick(); 800ad16: 6018 str r0, [r3, #0] if(CanId.command==0x02){ 800ad18: d013 beq.n 800ad42 if(CanId.command==0x04){ 800ad1a: 2d04 cmp r5, #4 800ad1c: d117 bne.n 800ad4e memcpy(&PSU_04, RxData, 8); 800ad1e: e894 0003 ldmia.w r4, {r0, r1} 800ad22: 4b39 ldr r3, [pc, #228] @ (800ae08 ) PSU0.tempAmbient = PSU_04.moduleTemperature; 800ad24: 4a39 ldr r2, [pc, #228] @ (800ae0c ) memcpy(&PSU_04, RxData, 8); 800ad26: e883 0003 stmia.w r3, {r0, r1} PSU0.status0.raw = PSU_04.modularForm0; 800ad2a: 7a18 ldrb r0, [r3, #8] PSU0.tempAmbient = PSU_04.moduleTemperature; 800ad2c: 791c ldrb r4, [r3, #4] PSU0.status1.raw = PSU_04.modularForm1; 800ad2e: 79d9 ldrb r1, [r3, #7] PSU0.status2.raw = PSU_04.modularForm2; 800ad30: 799b ldrb r3, [r3, #6] PSU0.tempAmbient = PSU_04.moduleTemperature; 800ad32: 6214 str r4, [r2, #32] PSU0.status0.raw = PSU_04.modularForm0; 800ad34: f882 0024 strb.w r0, [r2, #36] @ 0x24 PSU0.status1.raw = PSU_04.modularForm1; 800ad38: f882 1025 strb.w r1, [r2, #37] @ 0x25 PSU0.status2.raw = PSU_04.modularForm2; 800ad3c: f882 3026 strb.w r3, [r2, #38] @ 0x26 } 800ad40: bd38 pop {r3, r4, r5, pc} memcpy(&PSU_02, RxData, 8); 800ad42: 4b33 ldr r3, [pc, #204] @ (800ae10 ) 800ad44: e894 0003 ldmia.w r4, {r0, r1} 800ad48: e883 0003 stmia.w r3, {r0, r1} } 800ad4c: bd38 pop {r3, r4, r5, pc} if(CanId.command==0x06){ 800ad4e: 2d06 cmp r5, #6 800ad50: d111 bne.n 800ad76 memcpy(&PSU_06, RxData, 8); 800ad52: e894 0003 ldmia.w r4, {r0, r1} 800ad56: 4b2f ldr r3, [pc, #188] @ (800ae14 ) 800ad58: e883 0003 stmia.w r3, {r0, r1} PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800ad5c: 8818 ldrh r0, [r3, #0] PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800ad5e: 8859 ldrh r1, [r3, #2] PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ad60: 889a ldrh r2, [r3, #4] PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800ad62: ba40 rev16 r0, r0 PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800ad64: ba49 rev16 r1, r1 PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ad66: ba52 rev16 r2, r2 PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800ad68: b280 uxth r0, r0 PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800ad6a: b289 uxth r1, r1 PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ad6c: b292 uxth r2, r2 PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800ad6e: e9c3 0102 strd r0, r1, [r3, #8] PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ad72: 611a str r2, [r3, #16] } 800ad74: bd38 pop {r3, r4, r5, pc} if(CanId.command==0x08){ 800ad76: 2d08 cmp r5, #8 800ad78: d03a beq.n 800adf0 if(CanId.command==0x09){ 800ad7a: 2d09 cmp r5, #9 800ad7c: d1c4 bne.n 800ad08 memcpy(&PSU_09, RxData, 8); 800ad7e: e894 0003 ldmia.w r4, {r0, r1} PSU0.temperature = PSU_04.moduleTemperature; 800ad82: 4b21 ldr r3, [pc, #132] @ (800ae08 ) memcpy(&PSU_09, RxData, 8); 800ad84: 4d24 ldr r5, [pc, #144] @ (800ae18 ) PSU0.outputVoltage = v; 800ad86: 4c21 ldr r4, [pc, #132] @ (800ae0c ) PSU0.temperature = PSU_04.moduleTemperature; 800ad88: f893 c004 ldrb.w ip, [r3, #4] uint16_t v = PSU_09.moduleNVoltage / 1000; 800ad8c: 4a23 ldr r2, [pc, #140] @ (800ae1c ) memcpy(&PSU_09, RxData, 8); 800ad8e: e885 0003 stmia.w r5, {r0, r1} PSU_09.moduleNCurrent = PSU_09.moduleNCurrent_[3]; 800ad92: ba00 rev r0, r0 PSU0.temperature = PSU_04.moduleTemperature; 800ad94: f884 c006 strb.w ip, [r4, #6] uint16_t v = PSU_09.moduleNVoltage / 1000; 800ad98: fba2 c200 umull ip, r2, r2, r0 800ad9c: ba09 rev r1, r1 PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[0]<<24; 800ad9e: e9c5 0102 strd r0, r1, [r5, #8] uint16_t v = PSU_09.moduleNVoltage / 1000; 800ada2: f3c2 108f ubfx r0, r2, #6, #16 PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800ada6: 2813 cmp r0, #19 PSU0.online = 1; 800ada8: f04f 0e01 mov.w lr, #1 PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800adac: bf94 ite ls 800adae: 2500 movls r5, #0 800adb0: 2501 movhi r5, #1 int16_t i = PSU_09.moduleNCurrent / 100; 800adb2: 4b1b ldr r3, [pc, #108] @ (800ae20 ) PSU0.online = 1; 800adb4: f884 e008 strb.w lr, [r4, #8] int16_t i = PSU_09.moduleNCurrent / 100; 800adb8: fba3 c301 umull ip, r3, r3, r1 if(PSU0.state >= PSU_READY){ 800adbc: 79e1 ldrb r1, [r4, #7] int16_t i = PSU_09.moduleNCurrent / 100; 800adbe: 095b lsrs r3, r3, #5 if(PSU0.state >= PSU_READY){ 800adc0: 4571 cmp r1, lr PSU0.outputVoltage = v; 800adc2: 8060 strh r0, [r4, #2] int16_t i = PSU_09.moduleNCurrent / 100; 800adc4: 80a3 strh r3, [r4, #4] uint16_t v = PSU_09.moduleNVoltage / 1000; 800adc6: ea4f 1292 mov.w r2, r2, lsr #6 PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800adca: 72a5 strb r5, [r4, #10] if(PSU0.state >= PSU_READY){ 800adcc: d99c bls.n 800ad08 CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800adce: b299 uxth r1, r3 800add0: b292 uxth r2, r2 800add2: fb01 f202 mul.w r2, r1, r2 800add6: 4c13 ldr r4, [pc, #76] @ (800ae24 ) CONN.MeasuredVoltage = PSU0.outputVoltage; 800add8: 4913 ldr r1, [pc, #76] @ (800ae28 ) CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800adda: fba4 4202 umull r4, r2, r4, r2 CONN.MeasuredCurrent = PSU0.outputCurrent; 800adde: f8a1 3015 strh.w r3, [r1, #21] CONN.outputEnabled = PSU0.PSU_enabled; 800ade2: 760d strb r5, [r1, #24] CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800ade4: 08d3 lsrs r3, r2, #3 CONN.MeasuredVoltage = PSU0.outputVoltage; 800ade6: f8a1 0013 strh.w r0, [r1, #19] CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800adea: f8c1 3003 str.w r3, [r1, #3] } 800adee: bd38 pop {r3, r4, r5, pc} memcpy(&PSU_08, RxData, 8); 800adf0: 4b0e ldr r3, [pc, #56] @ (800ae2c ) 800adf2: e894 0003 ldmia.w r4, {r0, r1} 800adf6: e883 0003 stmia.w r3, {r0, r1} } 800adfa: bd38 pop {r3, r4, r5, pc} 800adfc: 2000094c .word 0x2000094c 800ae00: 20000930 .word 0x20000930 800ae04: 2000092c .word 0x2000092c 800ae08: 200008cc .word 0x200008cc 800ae0c: 20000904 .word 0x20000904 800ae10: 200008c0 .word 0x200008c0 800ae14: 200008d8 .word 0x200008d8 800ae18: 200008f4 .word 0x200008f4 800ae1c: 10624dd3 .word 0x10624dd3 800ae20: 51eb851f .word 0x51eb851f 800ae24: cccccccd .word 0xcccccccd 800ae28: 200003b0 .word 0x200003b0 800ae2c: 200008ec .word 0x200008ec 0800ae30 : void PSU_CAN_FilterInit(){ 800ae30: b580 push {r7, lr} 800ae32: b08a sub sp, #40 @ 0x28 800ae34: af00 add r7, sp, #0 CAN_FilterTypeDef sFilterConfig; sFilterConfig.FilterBank = 14; 800ae36: 230e movs r3, #14 800ae38: 617b str r3, [r7, #20] sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; 800ae3a: 2300 movs r3, #0 800ae3c: 61bb str r3, [r7, #24] sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; 800ae3e: 2301 movs r3, #1 800ae40: 61fb str r3, [r7, #28] sFilterConfig.FilterIdHigh = 0x0000; 800ae42: 2300 movs r3, #0 800ae44: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = 0x0000; 800ae46: 2300 movs r3, #0 800ae48: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 800ae4a: 2300 movs r3, #0 800ae4c: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = 0x0000; 800ae4e: 2300 movs r3, #0 800ae50: 60fb str r3, [r7, #12] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; 800ae52: 2300 movs r3, #0 800ae54: 613b str r3, [r7, #16] sFilterConfig.FilterActivation = ENABLE; 800ae56: 2301 movs r3, #1 800ae58: 623b str r3, [r7, #32] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; 800ae5a: 2301 movs r3, #1 800ae5c: 613b str r3, [r7, #16] sFilterConfig.SlaveStartFilterBank = 14; 800ae5e: 230e movs r3, #14 800ae60: 627b str r3, [r7, #36] @ 0x24 if(HAL_CAN_ConfigFilter(&hcan2, &sFilterConfig) != HAL_OK) 800ae62: 463b mov r3, r7 800ae64: 4619 mov r1, r3 800ae66: 4806 ldr r0, [pc, #24] @ (800ae80 ) 800ae68: f003 ff3e bl 800ece8 800ae6c: 4603 mov r3, r0 800ae6e: 2b00 cmp r3, #0 800ae70: d001 beq.n 800ae76 { Error_Handler(); 800ae72: f7ff fead bl 800abd0 } } 800ae76: bf00 nop 800ae78: 3728 adds r7, #40 @ 0x28 800ae7a: 46bd mov sp, r7 800ae7c: bd80 pop {r7, pc} 800ae7e: bf00 nop 800ae80: 20000384 .word 0x20000384 0800ae84 : void PSU_Init(){ 800ae84: b580 push {r7, lr} 800ae86: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan2); 800ae88: 4815 ldr r0, [pc, #84] @ (800aee0 ) 800ae8a: f004 f851 bl 800ef30 MX_CAN2_Init(); 800ae8e: f7fe fe8d bl 8009bac PSU_CAN_FilterInit(); 800ae92: f7ff ffcd bl 800ae30 HAL_CAN_Start(&hcan2); 800ae96: 4812 ldr r0, [pc, #72] @ (800aee0 ) 800ae98: f004 f806 bl 800eea8 HAL_CAN_ActivateNotification(&hcan2, CAN_IT_RX_FIFO1_MSG_PENDING /* | CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | CAN_IT_TX_MAILBOX_EMPTY*/); 800ae9c: 2110 movs r1, #16 800ae9e: 4810 ldr r0, [pc, #64] @ (800aee0 ) 800aea0: f004 fab3 bl 800f40a memset(&PSU0, 0, sizeof(PSU0)); 800aea4: 2228 movs r2, #40 @ 0x28 800aea6: 2100 movs r1, #0 800aea8: 480e ldr r0, [pc, #56] @ (800aee4 ) 800aeaa: f009 fc47 bl 801473c PSU0.state = PSU_UNREADY; 800aeae: 4b0d ldr r3, [pc, #52] @ (800aee4 ) 800aeb0: 2200 movs r2, #0 800aeb2: 71da strb r2, [r3, #7] PSU0.statetick = HAL_GetTick(); 800aeb4: f003 f8ae bl 800e014 800aeb8: 4603 mov r3, r0 800aeba: 4a0a ldr r2, [pc, #40] @ (800aee4 ) 800aebc: 6113 str r3, [r2, #16] PSU0.power_limit = PSU_MAX_POWER; // kW 800aebe: 4b09 ldr r3, [pc, #36] @ (800aee4 ) 800aec0: f247 5230 movw r2, #30000 @ 0x7530 800aec4: 615a str r2, [r3, #20] PSU0.hv_mode = 0; 800aec6: 4b07 ldr r3, [pc, #28] @ (800aee4 ) 800aec8: 2200 movs r2, #0 800aeca: 761a strb r2, [r3, #24] PSU0.hv_tick = 0; 800aecc: 4b05 ldr r3, [pc, #20] @ (800aee4 ) 800aece: 2200 movs r2, #0 800aed0: 61da str r2, [r3, #28] PSU_Enable(0, 0); 800aed2: 2100 movs r1, #0 800aed4: 2000 movs r0, #0 800aed6: f000 f807 bl 800aee8 } 800aeda: bf00 nop 800aedc: bd80 pop {r7, pc} 800aede: bf00 nop 800aee0: 20000384 .word 0x20000384 800aee4: 20000904 .word 0x20000904 0800aee8 : void PSU_Enable(uint8_t addr, uint8_t enable){ 800aee8: b580 push {r7, lr} 800aeea: b084 sub sp, #16 800aeec: af00 add r7, sp, #0 800aeee: 4603 mov r3, r0 800aef0: 460a mov r2, r1 800aef2: 71fb strb r3, [r7, #7] 800aef4: 4613 mov r3, r2 800aef6: 71bb strb r3, [r7, #6] PSU_1A_t data; memset(&data, 0, sizeof(data)); 800aef8: f107 0308 add.w r3, r7, #8 800aefc: 2208 movs r2, #8 800aefe: 2100 movs r1, #0 800af00: 4618 mov r0, r3 800af02: f009 fc1b bl 801473c /* Для DC30 поддерживается только один модуль с адресом 0 */ if(addr != 0) return; 800af06: 79fb ldrb r3, [r7, #7] 800af08: 2b00 cmp r3, #0 800af0a: d115 bne.n 800af38 if(PSU0.online == 0) return; 800af0c: 4b0d ldr r3, [pc, #52] @ (800af44 ) 800af0e: 7a1b ldrb r3, [r3, #8] 800af10: 2b00 cmp r3, #0 800af12: d013 beq.n 800af3c data.enable = !enable; 800af14: 79bb ldrb r3, [r7, #6] 800af16: 2b00 cmp r3, #0 800af18: bf0c ite eq 800af1a: 2301 moveq r3, #1 800af1c: 2300 movne r3, #0 800af1e: b2db uxtb r3, r3 800af20: 723b strb r3, [r7, #8] PSU_SendCmd(0xF0, addr, 0x1A, &data); 800af22: 79f9 ldrb r1, [r7, #7] 800af24: f107 0308 add.w r3, r7, #8 800af28: 221a movs r2, #26 800af2a: 20f0 movs r0, #240 @ 0xf0 800af2c: f000 f866 bl 800affc ED_Delay(CAN_DELAY); 800af30: 2014 movs r0, #20 800af32: f7ff fcb1 bl 800a898 800af36: e002 b.n 800af3e if(addr != 0) return; 800af38: bf00 nop 800af3a: e000 b.n 800af3e if(PSU0.online == 0) return; 800af3c: bf00 nop } 800af3e: 3710 adds r7, #16 800af40: 46bd mov sp, r7 800af42: bd80 pop {r7, pc} 800af44: 20000904 .word 0x20000904 0800af48 : memset(&data, 0, sizeof(data)); data.enable = !enable; if(addr != 0) return; PSU_SendCmd(0xF0, addr, 0x1D, &data); } void PSU_SetVoltageCurrent(uint8_t addr, uint16_t voltage, uint16_t current){ 800af48: b580 push {r7, lr} 800af4a: b086 sub sp, #24 800af4c: af00 add r7, sp, #0 800af4e: 4603 mov r3, r0 800af50: 71fb strb r3, [r7, #7] 800af52: 460b mov r3, r1 800af54: 80bb strh r3, [r7, #4] 800af56: 4613 mov r3, r2 800af58: 807b strh r3, [r7, #2] PSU_1C_t data; memset(&data, 0, sizeof(data)); 800af5a: f107 0308 add.w r3, r7, #8 800af5e: 2208 movs r2, #8 800af60: 2100 movs r1, #0 800af62: 4618 mov r0, r3 800af64: f009 fbea bl 801473c if(addr != 0) return; 800af68: 79fb ldrb r3, [r7, #7] 800af6a: 2b00 cmp r3, #0 800af6c: d140 bne.n 800aff0 if(voltage 800af74: 2396 movs r3, #150 @ 0x96 800af76: 80bb strh r3, [r7, #4] if((PSU0.hv_mode==0) && voltage>499) voltage = 499; 800af78: 4b1f ldr r3, [pc, #124] @ (800aff8 ) 800af7a: 7e1b ldrb r3, [r3, #24] 800af7c: 2b00 cmp r3, #0 800af7e: d106 bne.n 800af8e 800af80: 88bb ldrh r3, [r7, #4] 800af82: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800af86: d302 bcc.n 800af8e 800af88: f240 13f3 movw r3, #499 @ 0x1f3 800af8c: 80bb strh r3, [r7, #4] uint32_t current_ma = current * 100; 800af8e: 887b ldrh r3, [r7, #2] 800af90: 2264 movs r2, #100 @ 0x64 800af92: fb02 f303 mul.w r3, r2, r3 800af96: 617b str r3, [r7, #20] uint32_t voltage_mv = voltage * 1000; 800af98: 88bb ldrh r3, [r7, #4] 800af9a: f44f 727a mov.w r2, #1000 @ 0x3e8 800af9e: fb02 f303 mul.w r3, r2, r3 800afa2: 613b str r3, [r7, #16] data.moduleCurrentTotal[0] = (current_ma >> 24) & 0xFF; 800afa4: 697b ldr r3, [r7, #20] 800afa6: 0e1b lsrs r3, r3, #24 800afa8: b2db uxtb r3, r3 800afaa: 733b strb r3, [r7, #12] data.moduleCurrentTotal[1] = (current_ma >> 16) & 0xFF; 800afac: 697b ldr r3, [r7, #20] 800afae: 0c1b lsrs r3, r3, #16 800afb0: b2db uxtb r3, r3 800afb2: 737b strb r3, [r7, #13] data.moduleCurrentTotal[2] = (current_ma >> 8) & 0xFF; 800afb4: 697b ldr r3, [r7, #20] 800afb6: 0a1b lsrs r3, r3, #8 800afb8: b2db uxtb r3, r3 800afba: 73bb strb r3, [r7, #14] data.moduleCurrentTotal[3] = (current_ma >> 0) & 0xFF; 800afbc: 697b ldr r3, [r7, #20] 800afbe: b2db uxtb r3, r3 800afc0: 73fb strb r3, [r7, #15] data.moduleVoltage[0] = (voltage_mv >> 24) & 0xFF; 800afc2: 693b ldr r3, [r7, #16] 800afc4: 0e1b lsrs r3, r3, #24 800afc6: b2db uxtb r3, r3 800afc8: 723b strb r3, [r7, #8] data.moduleVoltage[1] = (voltage_mv >> 16) & 0xFF; 800afca: 693b ldr r3, [r7, #16] 800afcc: 0c1b lsrs r3, r3, #16 800afce: b2db uxtb r3, r3 800afd0: 727b strb r3, [r7, #9] data.moduleVoltage[2] = (voltage_mv >> 8) & 0xFF; 800afd2: 693b ldr r3, [r7, #16] 800afd4: 0a1b lsrs r3, r3, #8 800afd6: b2db uxtb r3, r3 800afd8: 72bb strb r3, [r7, #10] data.moduleVoltage[3] = (voltage_mv >> 0) & 0xFF; 800afda: 693b ldr r3, [r7, #16] 800afdc: b2db uxtb r3, r3 800afde: 72fb strb r3, [r7, #11] PSU_SendCmd(0xF0, addr, 0x1C, &data); 800afe0: 79f9 ldrb r1, [r7, #7] 800afe2: f107 0308 add.w r3, r7, #8 800afe6: 221c movs r2, #28 800afe8: 20f0 movs r0, #240 @ 0xf0 800afea: f000 f807 bl 800affc 800afee: e000 b.n 800aff2 if(addr != 0) return; 800aff0: bf00 nop } 800aff2: 3718 adds r7, #24 800aff4: 46bd mov sp, r7 800aff6: bd80 pop {r7, pc} 800aff8: 20000904 .word 0x20000904 0800affc : void PSU_SendCmd(uint8_t source, uint8_t destination, uint8_t cmd, void *data){ 800affc: b580 push {r7, lr} 800affe: b08c sub sp, #48 @ 0x30 800b000: af00 add r7, sp, #0 800b002: 603b str r3, [r7, #0] 800b004: 4603 mov r3, r0 800b006: 71fb strb r3, [r7, #7] 800b008: 460b mov r3, r1 800b00a: 71bb strb r3, [r7, #6] 800b00c: 4613 mov r3, r2 800b00e: 717b strb r3, [r7, #5] CanId_t CanId; CanId.source = source; 800b010: 79fb ldrb r3, [r7, #7] 800b012: f887 3028 strb.w r3, [r7, #40] @ 0x28 CanId.destination = destination; 800b016: 79bb ldrb r3, [r7, #6] 800b018: f887 3029 strb.w r3, [r7, #41] @ 0x29 CanId.command = cmd; 800b01c: 797b ldrb r3, [r7, #5] 800b01e: f003 033f and.w r3, r3, #63 @ 0x3f 800b022: b2da uxtb r2, r3 800b024: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 800b028: f362 0305 bfi r3, r2, #0, #6 800b02c: f887 302a strb.w r3, [r7, #42] @ 0x2a CanId.device = 0x0A; 800b030: 8d7b ldrh r3, [r7, #42] @ 0x2a 800b032: 220a movs r2, #10 800b034: f362 1389 bfi r3, r2, #6, #4 800b038: 857b strh r3, [r7, #42] @ 0x2a int8_t retry_counter = 10; 800b03a: 230a movs r3, #10 800b03c: f887 302f strb.w r3, [r7, #47] @ 0x2f CAN_TxHeaderTypeDef tx_header; uint32_t tx_mailbox; HAL_StatusTypeDef CAN_result; memcpy(&tx_header.ExtId, &CanId, sizeof(CanId_t)); 800b040: 6abb ldr r3, [r7, #40] @ 0x28 800b042: 617b str r3, [r7, #20] tx_header.RTR = CAN_RTR_DATA; 800b044: 2300 movs r3, #0 800b046: 61fb str r3, [r7, #28] tx_header.IDE = CAN_ID_EXT; 800b048: 2304 movs r3, #4 800b04a: 61bb str r3, [r7, #24] tx_header.DLC = 8; 800b04c: 2308 movs r3, #8 800b04e: 623b str r3, [r7, #32] while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800b050: e01e b.n 800b090 if (HAL_CAN_GetTxMailboxesFreeLevel(&hcan2) > 0){ 800b052: 4814 ldr r0, [pc, #80] @ (800b0a4 ) 800b054: f004 f884 bl 800f160 800b058: 4603 mov r3, r0 800b05a: 2b00 cmp r3, #0 800b05c: d00e beq.n 800b07c /* отправка сообщения */ CAN_result = HAL_CAN_AddTxMessage(&hcan2, &tx_header, (uint8_t*)data, &tx_mailbox); 800b05e: f107 030c add.w r3, r7, #12 800b062: f107 0110 add.w r1, r7, #16 800b066: 683a ldr r2, [r7, #0] 800b068: 480e ldr r0, [pc, #56] @ (800b0a4 ) 800b06a: f003 ffaa bl 800efc2 800b06e: 4603 mov r3, r0 800b070: f887 302e strb.w r3, [r7, #46] @ 0x2e /* если отправка удалась, выход */ if(CAN_result == HAL_OK) { 800b074: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 800b078: 2b00 cmp r3, #0 800b07a: d00e beq.n 800b09a return; retry_counter = 0; } } ED_Delay(1); 800b07c: 2001 movs r0, #1 800b07e: f7ff fc0b bl 800a898 retry_counter--; 800b082: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800b086: b2db uxtb r3, r3 800b088: 3b01 subs r3, #1 800b08a: b2db uxtb r3, r3 800b08c: f887 302f strb.w r3, [r7, #47] @ 0x2f while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800b090: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800b094: 2b00 cmp r3, #0 800b096: dcdc bgt.n 800b052 800b098: e000 b.n 800b09c return; 800b09a: bf00 nop } } 800b09c: 3730 adds r7, #48 @ 0x30 800b09e: 46bd mov sp, r7 800b0a0: bd80 pop {r7, pc} 800b0a2: bf00 nop 800b0a4: 20000384 .word 0x20000384 0800b0a8 : uint32_t max(uint32_t a, uint32_t b){ if(a>b) return a; else return b; } void PSU_ReadWrite(){ 800b0a8: b580 push {r7, lr} 800b0aa: b082 sub sp, #8 800b0ac: af00 add r7, sp, #0 uint8_t zero_data[8] = {0,0,0,0,0,0,0,0}; 800b0ae: 463b mov r3, r7 800b0b0: 2200 movs r2, #0 800b0b2: 601a str r2, [r3, #0] 800b0b4: 605a str r2, [r3, #4] PSU_SendCmd(0xF0, 0, 0x04, zero_data);ED_Delay(CAN_DELAY); 800b0b6: 463b mov r3, r7 800b0b8: 2204 movs r2, #4 800b0ba: 2100 movs r1, #0 800b0bc: 20f0 movs r0, #240 @ 0xf0 800b0be: f7ff ff9d bl 800affc 800b0c2: 2014 movs r0, #20 800b0c4: f7ff fbe8 bl 800a898 PSU_SendCmd(0xF0, 0, 0x06, zero_data);ED_Delay(CAN_DELAY); 800b0c8: 463b mov r3, r7 800b0ca: 2206 movs r2, #6 800b0cc: 2100 movs r1, #0 800b0ce: 20f0 movs r0, #240 @ 0xf0 800b0d0: f7ff ff94 bl 800affc 800b0d4: 2014 movs r0, #20 800b0d6: f7ff fbdf bl 800a898 // PSU_SendCmd(0xF0, 0, 0x08, zero_data);ED_Delay(CAN_DELAY); PSU_SendCmd(0xF0, 0, 0x09, zero_data);ED_Delay(CAN_DELAY); 800b0da: 463b mov r3, r7 800b0dc: 2209 movs r2, #9 800b0de: 2100 movs r1, #0 800b0e0: 20f0 movs r0, #240 @ 0xf0 800b0e2: f7ff ff8b bl 800affc 800b0e6: 2014 movs r0, #20 800b0e8: f7ff fbd6 bl 800a898 // Power Limit if ((CONN.WantedCurrent/10) * CONN.MeasuredVoltage > PSU0.power_limit){ 800b0ec: 4b4d ldr r3, [pc, #308] @ (800b224 ) 800b0ee: f8b3 301b ldrh.w r3, [r3, #27] 800b0f2: b29b uxth r3, r3 800b0f4: 4a4c ldr r2, [pc, #304] @ (800b228 ) 800b0f6: fba2 2303 umull r2, r3, r2, r3 800b0fa: 08db lsrs r3, r3, #3 800b0fc: b29b uxth r3, r3 800b0fe: 461a mov r2, r3 800b100: 4b48 ldr r3, [pc, #288] @ (800b224 ) 800b102: f8b3 3013 ldrh.w r3, [r3, #19] 800b106: b29b uxth r3, r3 800b108: fb02 f303 mul.w r3, r2, r3 800b10c: 461a mov r2, r3 800b10e: 4b47 ldr r3, [pc, #284] @ (800b22c ) 800b110: 695b ldr r3, [r3, #20] 800b112: 429a cmp r2, r3 800b114: d911 bls.n 800b13a CONN.RequestedCurrent = PSU0.power_limit * 10 / CONN.MeasuredVoltage; 800b116: 4b45 ldr r3, [pc, #276] @ (800b22c ) 800b118: 695a ldr r2, [r3, #20] 800b11a: 4613 mov r3, r2 800b11c: 009b lsls r3, r3, #2 800b11e: 4413 add r3, r2 800b120: 005b lsls r3, r3, #1 800b122: 461a mov r2, r3 800b124: 4b3f ldr r3, [pc, #252] @ (800b224 ) 800b126: f8b3 3013 ldrh.w r3, [r3, #19] 800b12a: b29b uxth r3, r3 800b12c: fbb2 f3f3 udiv r3, r2, r3 800b130: b29a uxth r2, r3 800b132: 4b3c ldr r3, [pc, #240] @ (800b224 ) 800b134: f8a3 2011 strh.w r2, [r3, #17] 800b138: e006 b.n 800b148 }else{ CONN.RequestedCurrent = CONN.WantedCurrent; 800b13a: 4b3a ldr r3, [pc, #232] @ (800b224 ) 800b13c: f8b3 301b ldrh.w r3, [r3, #27] 800b140: b29a uxth r2, r3 800b142: 4b38 ldr r3, [pc, #224] @ (800b224 ) 800b144: f8a3 2011 strh.w r2, [r3, #17] } if(CONN.RequestedCurrent > (PSU_MAX_CURRENT*10)){ 800b148: 4b36 ldr r3, [pc, #216] @ (800b224 ) 800b14a: f8b3 3011 ldrh.w r3, [r3, #17] 800b14e: b29b uxth r3, r3 800b150: f240 5232 movw r2, #1330 @ 0x532 800b154: 4293 cmp r3, r2 800b156: d908 bls.n 800b16a CONN.RequestedCurrent = PSU_MAX_CURRENT*10; 800b158: 4b32 ldr r3, [pc, #200] @ (800b224 ) 800b15a: 2200 movs r2, #0 800b15c: f042 0232 orr.w r2, r2, #50 @ 0x32 800b160: 745a strb r2, [r3, #17] 800b162: 2200 movs r2, #0 800b164: f042 0205 orr.w r2, r2, #5 800b168: 749a strb r2, [r3, #18] } CONN.RequestedPower = CONN.RequestedCurrent * CONN.RequestedVoltage / 10; 800b16a: 4b2e ldr r3, [pc, #184] @ (800b224 ) 800b16c: f8b3 3011 ldrh.w r3, [r3, #17] 800b170: b29b uxth r3, r3 800b172: 461a mov r2, r3 800b174: 4b2b ldr r3, [pc, #172] @ (800b224 ) 800b176: f8b3 300f ldrh.w r3, [r3, #15] 800b17a: b29b uxth r3, r3 800b17c: fb02 f303 mul.w r3, r2, r3 800b180: 4a2b ldr r2, [pc, #172] @ (800b230 ) 800b182: fb82 1203 smull r1, r2, r2, r3 800b186: 1092 asrs r2, r2, #2 800b188: 17db asrs r3, r3, #31 800b18a: 1ad3 subs r3, r2, r3 800b18c: 461a mov r2, r3 800b18e: 4b25 ldr r3, [pc, #148] @ (800b224 ) 800b190: f8c3 200b str.w r2, [r3, #11] if(PSU0.ready){ 800b194: 4b25 ldr r3, [pc, #148] @ (800b22c ) 800b196: 7a5b ldrb r3, [r3, #9] 800b198: 2b00 cmp r3, #0 800b19a: d03e beq.n 800b21a if (CONN.RequestedVoltage == 500) { // fake 800b19c: 4b21 ldr r3, [pc, #132] @ (800b224 ) 800b19e: f8b3 300f ldrh.w r3, [r3, #15] 800b1a2: b29b uxth r3, r3 800b1a4: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b1a8: d106 bne.n 800b1b8 PSU_SetVoltageCurrent(0, 300, 10); // Normal mode 800b1aa: 220a movs r2, #10 800b1ac: f44f 7196 mov.w r1, #300 @ 0x12c 800b1b0: 2000 movs r0, #0 800b1b2: f7ff fec9 bl 800af48 800b1b6: e00b b.n 800b1d0 }else{ PSU_SetVoltageCurrent(0, CONN.RequestedVoltage, CONN.RequestedCurrent); // Normal mode 800b1b8: 4b1a ldr r3, [pc, #104] @ (800b224 ) 800b1ba: f8b3 300f ldrh.w r3, [r3, #15] 800b1be: b29b uxth r3, r3 800b1c0: 4a18 ldr r2, [pc, #96] @ (800b224 ) 800b1c2: f8b2 2011 ldrh.w r2, [r2, #17] 800b1c6: b292 uxth r2, r2 800b1c8: 4619 mov r1, r3 800b1ca: 2000 movs r0, #0 800b1cc: f7ff febc bl 800af48 } ED_Delay(CAN_DELAY); 800b1d0: 2014 movs r0, #20 800b1d2: f7ff fb61 bl 800a898 if(CONN.MeasuredVoltage > 490){ 800b1d6: 4b13 ldr r3, [pc, #76] @ (800b224 ) 800b1d8: f8b3 3013 ldrh.w r3, [r3, #19] 800b1dc: b29b uxth r3, r3 800b1de: f5b3 7ff5 cmp.w r3, #490 @ 0x1ea 800b1e2: d917 bls.n 800b214 if(PSU0.hv_tick == 0){ 800b1e4: 4b11 ldr r3, [pc, #68] @ (800b22c ) 800b1e6: 69db ldr r3, [r3, #28] 800b1e8: 2b00 cmp r3, #0 800b1ea: d105 bne.n 800b1f8 PSU0.hv_tick = HAL_GetTick(); 800b1ec: f002 ff12 bl 800e014 800b1f0: 4603 mov r3, r0 800b1f2: 4a0e ldr r2, [pc, #56] @ (800b22c ) 800b1f4: 61d3 str r3, [r2, #28] } // PSU_SetHVMode(0, PSU0.hv_mode); // auto set, no need // ED_Delay(CAN_DELAY); } 800b1f6: e010 b.n 800b21a }else if((HAL_GetTick() - PSU0.hv_tick) >= 10000){ 800b1f8: f002 ff0c bl 800e014 800b1fc: 4602 mov r2, r0 800b1fe: 4b0b ldr r3, [pc, #44] @ (800b22c ) 800b200: 69db ldr r3, [r3, #28] 800b202: 1ad3 subs r3, r2, r3 800b204: f242 720f movw r2, #9999 @ 0x270f 800b208: 4293 cmp r3, r2 800b20a: d906 bls.n 800b21a PSU0.hv_mode = 1; 800b20c: 4b07 ldr r3, [pc, #28] @ (800b22c ) 800b20e: 2201 movs r2, #1 800b210: 761a strb r2, [r3, #24] } 800b212: e002 b.n 800b21a PSU0.hv_tick = 0; 800b214: 4b05 ldr r3, [pc, #20] @ (800b22c ) 800b216: 2200 movs r2, #0 800b218: 61da str r2, [r3, #28] } 800b21a: bf00 nop 800b21c: 3708 adds r7, #8 800b21e: 46bd mov sp, r7 800b220: bd80 pop {r7, pc} 800b222: bf00 nop 800b224: 200003b0 .word 0x200003b0 800b228: cccccccd .word 0xcccccccd 800b22c: 20000904 .word 0x20000904 800b230: 66666667 .word 0x66666667 0800b234 : void PSU_Task(void){ 800b234: b598 push {r3, r4, r7, lr} 800b236: af00 add r7, sp, #0 static uint32_t psu_on_tick = 0; static uint32_t dc_on_tick = 0; static uint32_t cont_ok_tick = 0; // Обновляем ONLINE/READY по таймауту if((HAL_GetTick() - can_lastpacket) > PSU_ONLINE_TIMEOUT){ 800b238: f002 feec bl 800e014 800b23c: 4602 mov r2, r0 800b23e: 4bb5 ldr r3, [pc, #724] @ (800b514 ) 800b240: 681b ldr r3, [r3, #0] 800b242: 1ad3 subs r3, r2, r3 800b244: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b248: d920 bls.n 800b28c PSU0.online = 0; 800b24a: 4bb3 ldr r3, [pc, #716] @ (800b518 ) 800b24c: 2200 movs r2, #0 800b24e: 721a strb r2, [r3, #8] PSU0.PSU_enabled = 0; 800b250: 4bb1 ldr r3, [pc, #708] @ (800b518 ) 800b252: 2200 movs r2, #0 800b254: 729a strb r2, [r3, #10] PSU_04.moduleTemperature = 0; 800b256: 4bb1 ldr r3, [pc, #708] @ (800b51c ) 800b258: 2200 movs r2, #0 800b25a: 711a strb r2, [r3, #4] PSU_04.modularForm0 = 0; 800b25c: 4baf ldr r3, [pc, #700] @ (800b51c ) 800b25e: 2200 movs r2, #0 800b260: 721a strb r2, [r3, #8] PSU_04.modularForm1 = 0; 800b262: 4bae ldr r3, [pc, #696] @ (800b51c ) 800b264: 2200 movs r2, #0 800b266: 71da strb r2, [r3, #7] PSU_04.modularForm2 = 0; 800b268: 4bac ldr r3, [pc, #688] @ (800b51c ) 800b26a: 2200 movs r2, #0 800b26c: 719a strb r2, [r3, #6] PSU_06.VAB = 0; 800b26e: 4bac ldr r3, [pc, #688] @ (800b520 ) 800b270: 2200 movs r2, #0 800b272: 609a str r2, [r3, #8] PSU_06.VBC = 0; 800b274: 4baa ldr r3, [pc, #680] @ (800b520 ) 800b276: 2200 movs r2, #0 800b278: 60da str r2, [r3, #12] PSU_06.VCA = 0; 800b27a: 4ba9 ldr r3, [pc, #676] @ (800b520 ) 800b27c: 2200 movs r2, #0 800b27e: 611a str r2, [r3, #16] PSU_09.moduleNCurrent = 0; 800b280: 4ba8 ldr r3, [pc, #672] @ (800b524 ) 800b282: 2200 movs r2, #0 800b284: 60da str r2, [r3, #12] PSU_09.moduleNVoltage = 0; 800b286: 4ba7 ldr r3, [pc, #668] @ (800b524 ) 800b288: 2200 movs r2, #0 800b28a: 609a str r2, [r3, #8] } if(!PSU0.online || !PSU0.enableAC){ 800b28c: 4ba2 ldr r3, [pc, #648] @ (800b518 ) 800b28e: 7a1b ldrb r3, [r3, #8] 800b290: 2b00 cmp r3, #0 800b292: d003 beq.n 800b29c 800b294: 4ba0 ldr r3, [pc, #640] @ (800b518 ) 800b296: 781b ldrb r3, [r3, #0] 800b298: 2b00 cmp r3, #0 800b29a: d10c bne.n 800b2b6 CONN.MeasuredVoltage = 0; 800b29c: 4ba2 ldr r3, [pc, #648] @ (800b528 ) 800b29e: 2200 movs r2, #0 800b2a0: 74da strb r2, [r3, #19] 800b2a2: 2200 movs r2, #0 800b2a4: 751a strb r2, [r3, #20] CONN.MeasuredCurrent = 0; 800b2a6: 4ba0 ldr r3, [pc, #640] @ (800b528 ) 800b2a8: 2200 movs r2, #0 800b2aa: 755a strb r2, [r3, #21] 800b2ac: 2200 movs r2, #0 800b2ae: 759a strb r2, [r3, #22] CONN.outputEnabled = 0; 800b2b0: 4b9d ldr r3, [pc, #628] @ (800b528 ) 800b2b2: 2200 movs r2, #0 800b2b4: 761a strb r2, [r3, #24] } // Управление AC-контактором с задержкой отключения 1 минута if(CONN.EvConnected){ 800b2b6: 4b9c ldr r3, [pc, #624] @ (800b528 ) 800b2b8: 7f9b ldrb r3, [r3, #30] 800b2ba: 2b00 cmp r3, #0 800b2bc: d00c beq.n 800b2d8 RELAY_Write(RELAY_AC, 1); 800b2be: 2101 movs r1, #1 800b2c0: 2004 movs r0, #4 800b2c2: f7fe fa79 bl 80097b8 psu_on_tick = HAL_GetTick(); 800b2c6: f002 fea5 bl 800e014 800b2ca: 4603 mov r3, r0 800b2cc: 4a97 ldr r2, [pc, #604] @ (800b52c ) 800b2ce: 6013 str r3, [r2, #0] PSU0.enableAC = 1; 800b2d0: 4b91 ldr r3, [pc, #580] @ (800b518 ) 800b2d2: 2201 movs r2, #1 800b2d4: 701a strb r2, [r3, #0] 800b2d6: e010 b.n 800b2fa }else{ if((HAL_GetTick() - psu_on_tick) > 1 * 60000){ 800b2d8: f002 fe9c bl 800e014 800b2dc: 4602 mov r2, r0 800b2de: 4b93 ldr r3, [pc, #588] @ (800b52c ) 800b2e0: 681b ldr r3, [r3, #0] 800b2e2: 1ad3 subs r3, r2, r3 800b2e4: f64e 2260 movw r2, #60000 @ 0xea60 800b2e8: 4293 cmp r3, r2 800b2ea: d906 bls.n 800b2fa RELAY_Write(RELAY_AC, 0); 800b2ec: 2100 movs r1, #0 800b2ee: 2004 movs r0, #4 800b2f0: f7fe fa62 bl 80097b8 PSU0.enableAC = 0; 800b2f4: 4b88 ldr r3, [pc, #544] @ (800b518 ) 800b2f6: 2200 movs r2, #0 800b2f8: 701a strb r2, [r3, #0] } } // Текущее состояние DC-контактора по обратной связи PSU0.CONT_enabled = IN_ReadInput(IN_CONT_FB_DC); 800b2fa: 2005 movs r0, #5 800b2fc: f7fe fadc bl 80098b8 800b300: 4603 mov r3, r0 800b302: 461a mov r2, r3 800b304: 4b84 ldr r3, [pc, #528] @ (800b518 ) 800b306: 72da strb r2, [r3, #11] // Обновляем ready с учётом ошибок if(PSU0.online && !PSU0.cont_fault && PSU0.enableAC){ 800b308: 4b83 ldr r3, [pc, #524] @ (800b518 ) 800b30a: 7a1b ldrb r3, [r3, #8] 800b30c: 2b00 cmp r3, #0 800b30e: d007 beq.n 800b320 800b310: 4b81 ldr r3, [pc, #516] @ (800b518 ) 800b312: 7b1b ldrb r3, [r3, #12] 800b314: 2b00 cmp r3, #0 800b316: d103 bne.n 800b320 800b318: 4b7f ldr r3, [pc, #508] @ (800b518 ) 800b31a: 781b ldrb r3, [r3, #0] 800b31c: 2b00 cmp r3, #0 800b31e: d102 bne.n 800b326 // PSU0.ready = 1; }else{ PSU0.ready = 0; 800b320: 4b7d ldr r3, [pc, #500] @ (800b518 ) 800b322: 2200 movs r2, #0 800b324: 725a strb r2, [r3, #9] } switch(PSU0.state){ 800b326: 4b7c ldr r3, [pc, #496] @ (800b518 ) 800b328: 79db ldrb r3, [r3, #7] 800b32a: 2b09 cmp r3, #9 800b32c: f200 8157 bhi.w 800b5de 800b330: a201 add r2, pc, #4 @ (adr r2, 800b338 ) 800b332: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b336: bf00 nop 800b338: 0800b361 .word 0x0800b361 800b33c: 0800b395 .word 0x0800b395 800b340: 0800b3b1 .word 0x0800b3b1 800b344: 0800b3ef .word 0x0800b3ef 800b348: 0800b43d .word 0x0800b43d 800b34c: 0800b47f .word 0x0800b47f 800b350: 0800b4e9 .word 0x0800b4e9 800b354: 0800b591 .word 0x0800b591 800b358: 0800b541 .word 0x0800b541 800b35c: 0800b5cb .word 0x0800b5cb case PSU_UNREADY: PSU0.enableOutput = 0; 800b360: 4b6d ldr r3, [pc, #436] @ (800b518 ) 800b362: 2200 movs r2, #0 800b364: 705a strb r2, [r3, #1] RELAY_Write(RELAY_DC, 0); 800b366: 2100 movs r1, #0 800b368: 2003 movs r0, #3 800b36a: f7fe fa25 bl 80097b8 if(PSU0.online && PSU0.enableAC && !PSU0.cont_fault){ 800b36e: 4b6a ldr r3, [pc, #424] @ (800b518 ) 800b370: 7a1b ldrb r3, [r3, #8] 800b372: 2b00 cmp r3, #0 800b374: f000 8137 beq.w 800b5e6 800b378: 4b67 ldr r3, [pc, #412] @ (800b518 ) 800b37a: 781b ldrb r3, [r3, #0] 800b37c: 2b00 cmp r3, #0 800b37e: f000 8132 beq.w 800b5e6 800b382: 4b65 ldr r3, [pc, #404] @ (800b518 ) 800b384: 7b1b ldrb r3, [r3, #12] 800b386: 2b00 cmp r3, #0 800b388: f040 812d bne.w 800b5e6 PSU_SwitchState(PSU_INITIALIZING); 800b38c: 2001 movs r0, #1 800b38e: f7ff fc8f bl 800acb0 } break; 800b392: e128 b.n 800b5e6 case PSU_INITIALIZING: if(PSU_StateTime() > 4000){ // Wait 4s for PSU to initialize 800b394: f7ff fca0 bl 800acd8 800b398: 4603 mov r3, r0 800b39a: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b39e: f240 8124 bls.w 800b5ea PSU0.ready = 1; 800b3a2: 4b5d ldr r3, [pc, #372] @ (800b518 ) 800b3a4: 2201 movs r2, #1 800b3a6: 725a strb r2, [r3, #9] PSU_SwitchState(PSU_READY); 800b3a8: 2002 movs r0, #2 800b3aa: f7ff fc81 bl 800acb0 } break; 800b3ae: e11c b.n 800b5ea case PSU_READY: // модуль готов, но выключен PSU0.hv_mode = 0; 800b3b0: 4b59 ldr r3, [pc, #356] @ (800b518 ) 800b3b2: 2200 movs r2, #0 800b3b4: 761a strb r2, [r3, #24] PSU0.hv_tick = 0; 800b3b6: 4b58 ldr r3, [pc, #352] @ (800b518 ) 800b3b8: 2200 movs r2, #0 800b3ba: 61da str r2, [r3, #28] RELAY_Write(RELAY_DC, 0); 800b3bc: 2100 movs r1, #0 800b3be: 2003 movs r0, #3 800b3c0: f7fe f9fa bl 80097b8 if(!PSU0.ready){ 800b3c4: 4b54 ldr r3, [pc, #336] @ (800b518 ) 800b3c6: 7a5b ldrb r3, [r3, #9] 800b3c8: 2b00 cmp r3, #0 800b3ca: d103 bne.n 800b3d4 PSU_SwitchState(PSU_UNREADY); 800b3cc: 2000 movs r0, #0 800b3ce: f7ff fc6f bl 800acb0 break; 800b3d2: e11b b.n 800b60c } if(CONN.EnableOutput){ 800b3d4: 4b54 ldr r3, [pc, #336] @ (800b528 ) 800b3d6: 7ddb ldrb r3, [r3, #23] 800b3d8: 2b00 cmp r3, #0 800b3da: f000 8108 beq.w 800b5ee PSU_Enable(0, 1); 800b3de: 2101 movs r1, #1 800b3e0: 2000 movs r0, #0 800b3e2: f7ff fd81 bl 800aee8 PSU_SwitchState(PSU_WAIT_ACK_ON); 800b3e6: 2003 movs r0, #3 800b3e8: f7ff fc62 bl 800acb0 } break; 800b3ec: e0ff b.n 800b5ee case PSU_WAIT_ACK_ON: if(PSU0.PSU_enabled && PSU0.ready){ 800b3ee: 4b4a ldr r3, [pc, #296] @ (800b518 ) 800b3f0: 7a9b ldrb r3, [r3, #10] 800b3f2: 2b00 cmp r3, #0 800b3f4: d00c beq.n 800b410 800b3f6: 4b48 ldr r3, [pc, #288] @ (800b518 ) 800b3f8: 7a5b ldrb r3, [r3, #9] 800b3fa: 2b00 cmp r3, #0 800b3fc: d008 beq.n 800b410 dc_on_tick = HAL_GetTick(); 800b3fe: f002 fe09 bl 800e014 800b402: 4603 mov r3, r0 800b404: 4a4a ldr r2, [pc, #296] @ (800b530 ) 800b406: 6013 str r3, [r2, #0] PSU_SwitchState(PSU_CONT_WAIT_ACK_ON); 800b408: 2004 movs r0, #4 800b40a: f7ff fc51 bl 800acb0 PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU on timeout\n"); } break; 800b40e: e0f0 b.n 800b5f2 }else if(PSU_StateTime() > 10000){ 800b410: f7ff fc62 bl 800acd8 800b414: 4603 mov r3, r0 800b416: f242 7210 movw r2, #10000 @ 0x2710 800b41a: 4293 cmp r3, r2 800b41c: f240 80e9 bls.w 800b5f2 PSU0.psu_fault = 1; 800b420: 4b3d ldr r3, [pc, #244] @ (800b518 ) 800b422: 2201 movs r2, #1 800b424: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b426: 4b40 ldr r3, [pc, #256] @ (800b528 ) 800b428: 220a movs r2, #10 800b42a: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b42c: 2000 movs r0, #0 800b42e: f7ff fc3f bl 800acb0 log_printf(LOG_ERR, "PSU on timeout\n"); 800b432: 4940 ldr r1, [pc, #256] @ (800b534 ) 800b434: 2004 movs r0, #4 800b436: f7ff f853 bl 800a4e0 break; 800b43a: e0da b.n 800b5f2 case PSU_CONT_WAIT_ACK_ON: // замыкаем DC-контактор и ждём подтверждение RELAY_Write(RELAY_DC, 1); 800b43c: 2101 movs r1, #1 800b43e: 2003 movs r0, #3 800b440: f7fe f9ba bl 80097b8 if(PSU0.CONT_enabled){ 800b444: 4b34 ldr r3, [pc, #208] @ (800b518 ) 800b446: 7adb ldrb r3, [r3, #11] 800b448: 2b00 cmp r3, #0 800b44a: d003 beq.n 800b454 PSU_SwitchState(PSU_CONNECTED); 800b44c: 2005 movs r0, #5 800b44e: f7ff fc2f bl 800acb0 PSU0.cont_fault = 1; CONN.chargingError = CONN_ERR_CONTACTOR; PSU_SwitchState(PSU_CURRENT_DROP); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b452: e0d0 b.n 800b5f6 }else if(PSU_StateTime() > 1000){ 800b454: f7ff fc40 bl 800acd8 800b458: 4603 mov r3, r0 800b45a: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b45e: f240 80ca bls.w 800b5f6 PSU0.cont_fault = 1; 800b462: 4b2d ldr r3, [pc, #180] @ (800b518 ) 800b464: 2201 movs r2, #1 800b466: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b468: 4b2f ldr r3, [pc, #188] @ (800b528 ) 800b46a: 2207 movs r2, #7 800b46c: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_CURRENT_DROP); 800b46e: 2006 movs r0, #6 800b470: f7ff fc1e bl 800acb0 log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b474: 4930 ldr r1, [pc, #192] @ (800b538 ) 800b476: 2004 movs r0, #4 800b478: f7ff f832 bl 800a4e0 break; 800b47c: e0bb b.n 800b5f6 case PSU_CONNECTED: // Основное рабочее состояние if(!CONN.EnableOutput || !PSU0.ready){ 800b47e: 4b2a ldr r3, [pc, #168] @ (800b528 ) 800b480: 7ddb ldrb r3, [r3, #23] 800b482: 2b00 cmp r3, #0 800b484: d003 beq.n 800b48e 800b486: 4b24 ldr r3, [pc, #144] @ (800b518 ) 800b488: 7a5b ldrb r3, [r3, #9] 800b48a: 2b00 cmp r3, #0 800b48c: d103 bne.n 800b496 PSU_SwitchState(PSU_CURRENT_DROP); 800b48e: 2006 movs r0, #6 800b490: f7ff fc0e bl 800acb0 break; 800b494: e0ba b.n 800b60c } // контроль контактора: 1 c таймаут if (IN_ReadInput(IN_CONT_FB_DC) != RELAY_Read(RELAY_DC)){ 800b496: 2005 movs r0, #5 800b498: f7fe fa0e bl 80098b8 800b49c: 4603 mov r3, r0 800b49e: 461c mov r4, r3 800b4a0: 2003 movs r0, #3 800b4a2: f7fe f9f9 bl 8009898 800b4a6: 4603 mov r3, r0 800b4a8: 429c cmp r4, r3 800b4aa: d017 beq.n 800b4dc if((HAL_GetTick() - cont_ok_tick) > 1000){ 800b4ac: f002 fdb2 bl 800e014 800b4b0: 4602 mov r2, r0 800b4b2: 4b22 ldr r3, [pc, #136] @ (800b53c ) 800b4b4: 681b ldr r3, [r3, #0] 800b4b6: 1ad3 subs r3, r2, r3 800b4b8: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b4bc: f240 809d bls.w 800b5fa CONN.chargingError = CONN_ERR_CONTACTOR; 800b4c0: 4b19 ldr r3, [pc, #100] @ (800b528 ) 800b4c2: 2207 movs r2, #7 800b4c4: 775a strb r2, [r3, #29] PSU0.cont_fault = 1; 800b4c6: 4b14 ldr r3, [pc, #80] @ (800b518 ) 800b4c8: 2201 movs r2, #1 800b4ca: 731a strb r2, [r3, #12] PSU_SwitchState(PSU_CURRENT_DROP); 800b4cc: 2006 movs r0, #6 800b4ce: f7ff fbef bl 800acb0 log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b4d2: 4919 ldr r1, [pc, #100] @ (800b538 ) 800b4d4: 2004 movs r0, #4 800b4d6: f7ff f803 bl 800a4e0 } }else{ cont_ok_tick = HAL_GetTick(); } break; 800b4da: e08e b.n 800b5fa cont_ok_tick = HAL_GetTick(); 800b4dc: f002 fd9a bl 800e014 800b4e0: 4603 mov r3, r0 800b4e2: 4a16 ldr r2, [pc, #88] @ (800b53c ) 800b4e4: 6013 str r3, [r2, #0] break; 800b4e6: e088 b.n 800b5fa case PSU_CURRENT_DROP: // снижаем ток до нуля перед отключением DC CONN.RequestedCurrent = 0; 800b4e8: 4b0f ldr r3, [pc, #60] @ (800b528 ) 800b4ea: 2200 movs r2, #0 800b4ec: 745a strb r2, [r3, #17] 800b4ee: 2200 movs r2, #0 800b4f0: 749a strb r2, [r3, #18] // если ток действительно упал или вышло время, отключаем DC if((CONN.MeasuredCurrent < 30) || (PSU_StateTime() > 5000)){ 800b4f2: 4b0d ldr r3, [pc, #52] @ (800b528 ) 800b4f4: f8b3 3015 ldrh.w r3, [r3, #21] 800b4f8: b29b uxth r3, r3 800b4fa: 2b1d cmp r3, #29 800b4fc: d906 bls.n 800b50c 800b4fe: f7ff fbeb bl 800acd8 800b502: 4603 mov r3, r0 800b504: f241 3288 movw r2, #5000 @ 0x1388 800b508: 4293 cmp r3, r2 800b50a: d978 bls.n 800b5fe PSU_SwitchState(PSU_CONT_WAIT_ACK_OFF); 800b50c: 2008 movs r0, #8 800b50e: f7ff fbcf bl 800acb0 } break; 800b512: e074 b.n 800b5fe 800b514: 2000092c .word 0x2000092c 800b518: 20000904 .word 0x20000904 800b51c: 200008cc .word 0x200008cc 800b520: 200008d8 .word 0x200008d8 800b524: 200008f4 .word 0x200008f4 800b528: 200003b0 .word 0x200003b0 800b52c: 20000954 .word 0x20000954 800b530: 20000958 .word 0x20000958 800b534: 08016bd0 .word 0x08016bd0 800b538: 08016be0 .word 0x08016be0 800b53c: 2000095c .word 0x2000095c case PSU_CONT_WAIT_ACK_OFF: RELAY_Write(RELAY_DC, 0); 800b540: 2100 movs r1, #0 800b542: 2003 movs r0, #3 800b544: f7fe f938 bl 80097b8 if(!PSU0.CONT_enabled){ 800b548: 4b31 ldr r3, [pc, #196] @ (800b610 ) 800b54a: 7adb ldrb r3, [r3, #11] 800b54c: 2b00 cmp r3, #0 800b54e: d107 bne.n 800b560 PSU_Enable(0, 0); 800b550: 2100 movs r1, #0 800b552: 2000 movs r0, #0 800b554: f7ff fcc8 bl 800aee8 PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b558: 2007 movs r0, #7 800b55a: f7ff fba9 bl 800acb0 CONN.chargingError = CONN_ERR_CONTACTOR; PSU_Enable(0, 0); PSU_SwitchState(PSU_WAIT_ACK_OFF); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b55e: e050 b.n 800b602 }else if(PSU_StateTime() > 1000){ 800b560: f7ff fbba bl 800acd8 800b564: 4603 mov r3, r0 800b566: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b56a: d94a bls.n 800b602 PSU0.cont_fault = 1; 800b56c: 4b28 ldr r3, [pc, #160] @ (800b610 ) 800b56e: 2201 movs r2, #1 800b570: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b572: 4b28 ldr r3, [pc, #160] @ (800b614 ) 800b574: 2207 movs r2, #7 800b576: 775a strb r2, [r3, #29] PSU_Enable(0, 0); 800b578: 2100 movs r1, #0 800b57a: 2000 movs r0, #0 800b57c: f7ff fcb4 bl 800aee8 PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b580: 2007 movs r0, #7 800b582: f7ff fb95 bl 800acb0 log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b586: 4924 ldr r1, [pc, #144] @ (800b618 ) 800b588: 2004 movs r0, #4 800b58a: f7fe ffa9 bl 800a4e0 break; 800b58e: e038 b.n 800b602 case PSU_WAIT_ACK_OFF: if(!PSU0.PSU_enabled){ 800b590: 4b1f ldr r3, [pc, #124] @ (800b610 ) 800b592: 7a9b ldrb r3, [r3, #10] 800b594: 2b00 cmp r3, #0 800b596: d103 bne.n 800b5a0 PSU_SwitchState(PSU_OFF_PAUSE); 800b598: 2009 movs r0, #9 800b59a: f7ff fb89 bl 800acb0 PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU off timeout\n"); } break; 800b59e: e032 b.n 800b606 }else if(PSU_StateTime() > 10000){ 800b5a0: f7ff fb9a bl 800acd8 800b5a4: 4603 mov r3, r0 800b5a6: f242 7210 movw r2, #10000 @ 0x2710 800b5aa: 4293 cmp r3, r2 800b5ac: d92b bls.n 800b606 PSU0.psu_fault = 1; 800b5ae: 4b18 ldr r3, [pc, #96] @ (800b610 ) 800b5b0: 2201 movs r2, #1 800b5b2: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b5b4: 4b17 ldr r3, [pc, #92] @ (800b614 ) 800b5b6: 220a movs r2, #10 800b5b8: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b5ba: 2000 movs r0, #0 800b5bc: f7ff fb78 bl 800acb0 log_printf(LOG_ERR, "PSU off timeout\n"); 800b5c0: 4916 ldr r1, [pc, #88] @ (800b61c ) 800b5c2: 2004 movs r0, #4 800b5c4: f7fe ff8c bl 800a4e0 break; 800b5c8: e01d b.n 800b606 case PSU_OFF_PAUSE: if(PSU_StateTime() > 4000){ 800b5ca: f7ff fb85 bl 800acd8 800b5ce: 4603 mov r3, r0 800b5d0: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b5d4: d919 bls.n 800b60a PSU_SwitchState(PSU_READY); 800b5d6: 2002 movs r0, #2 800b5d8: f7ff fb6a bl 800acb0 } break; 800b5dc: e015 b.n 800b60a default: PSU_SwitchState(PSU_UNREADY); 800b5de: 2000 movs r0, #0 800b5e0: f7ff fb66 bl 800acb0 break; 800b5e4: e012 b.n 800b60c break; 800b5e6: bf00 nop 800b5e8: e010 b.n 800b60c break; 800b5ea: bf00 nop 800b5ec: e00e b.n 800b60c break; 800b5ee: bf00 nop 800b5f0: e00c b.n 800b60c break; 800b5f2: bf00 nop 800b5f4: e00a b.n 800b60c break; 800b5f6: bf00 nop 800b5f8: e008 b.n 800b60c break; 800b5fa: bf00 nop 800b5fc: e006 b.n 800b60c break; 800b5fe: bf00 nop 800b600: e004 b.n 800b60c break; 800b602: bf00 nop 800b604: e002 b.n 800b60c break; 800b606: bf00 nop 800b608: e000 b.n 800b60c break; 800b60a: bf00 nop } } 800b60c: bf00 nop 800b60e: bd98 pop {r3, r4, r7, pc} 800b610: 20000904 .word 0x20000904 800b614: 200003b0 .word 0x200003b0 800b618: 08016be0 .word 0x08016be0 800b61c: 08016c00 .word 0x08016c00 0800b620 : .Th = 10, .Tf = 50, .Tl = 0, }; void LED_Write(){ 800b620: b580 push {r7, lr} 800b622: af00 add r7, sp, #0 if(CONN.chargingError != CONN_NO_ERROR){ 800b624: 4b3c ldr r3, [pc, #240] @ (800b718 ) 800b626: 7f5b ldrb r3, [r3, #29] 800b628: 2b00 cmp r3, #0 800b62a: d003 beq.n 800b634 LED_SetColor(&color_error); 800b62c: 483b ldr r0, [pc, #236] @ (800b71c ) 800b62e: f000 f933 bl 800b898 return; 800b632: e06f b.n 800b714 } if(CONN.connControl == CMD_FORCE_UNLOCK){ 800b634: 4b38 ldr r3, [pc, #224] @ (800b718 ) 800b636: 781b ldrb r3, [r3, #0] 800b638: 2b03 cmp r3, #3 800b63a: d103 bne.n 800b644 LED_SetColor(&color_unlock); 800b63c: 4838 ldr r0, [pc, #224] @ (800b720 ) 800b63e: f000 f92b bl 800b898 return; 800b642: e067 b.n 800b714 } if(CONN.connControl == CMD_STOP){ 800b644: 4b34 ldr r3, [pc, #208] @ (800b718 ) 800b646: 781b ldrb r3, [r3, #0] 800b648: 2b01 cmp r3, #1 800b64a: d103 bne.n 800b654 LED_SetColor(&color_estop); 800b64c: 4835 ldr r0, [pc, #212] @ (800b724 ) 800b64e: f000 f923 bl 800b898 return; 800b652: e05f b.n 800b714 } switch(CONN.connState){ 800b654: 4b30 ldr r3, [pc, #192] @ (800b718 ) 800b656: 785b ldrb r3, [r3, #1] 800b658: 2b0d cmp r3, #13 800b65a: d857 bhi.n 800b70c 800b65c: a201 add r2, pc, #4 @ (adr r2, 800b664 ) 800b65e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b662: bf00 nop 800b664: 0800b69d .word 0x0800b69d 800b668: 0800b6a5 .word 0x0800b6a5 800b66c: 0800b6ad .word 0x0800b6ad 800b670: 0800b6b5 .word 0x0800b6b5 800b674: 0800b6bd .word 0x0800b6bd 800b678: 0800b6c5 .word 0x0800b6c5 800b67c: 0800b6cd .word 0x0800b6cd 800b680: 0800b6d5 .word 0x0800b6d5 800b684: 0800b6dd .word 0x0800b6dd 800b688: 0800b6e5 .word 0x0800b6e5 800b68c: 0800b6ed .word 0x0800b6ed 800b690: 0800b6f5 .word 0x0800b6f5 800b694: 0800b6fd .word 0x0800b6fd 800b698: 0800b705 .word 0x0800b705 case Unknown: LED_SetColor(&color_unknown); 800b69c: 4822 ldr r0, [pc, #136] @ (800b728 ) 800b69e: f000 f8fb bl 800b898 break; 800b6a2: e037 b.n 800b714 case Unplugged: LED_SetColor(&color_unplugged); 800b6a4: 4821 ldr r0, [pc, #132] @ (800b72c ) 800b6a6: f000 f8f7 bl 800b898 break; 800b6aa: e033 b.n 800b714 case Disabled: LED_SetColor(&color_error); 800b6ac: 481b ldr r0, [pc, #108] @ (800b71c ) 800b6ae: f000 f8f3 bl 800b898 break; 800b6b2: e02f b.n 800b714 case Preparing: LED_SetColor(&color_preparing); 800b6b4: 481e ldr r0, [pc, #120] @ (800b730 ) 800b6b6: f000 f8ef bl 800b898 break; 800b6ba: e02b b.n 800b714 case AuthRequired: LED_SetColor(&color_preparing); 800b6bc: 481c ldr r0, [pc, #112] @ (800b730 ) 800b6be: f000 f8eb bl 800b898 break; 800b6c2: e027 b.n 800b714 case WaitingForEnergy: LED_SetColor(&color_charging); 800b6c4: 481b ldr r0, [pc, #108] @ (800b734 ) 800b6c6: f000 f8e7 bl 800b898 break; 800b6ca: e023 b.n 800b714 case ChargingPausedEV: LED_SetColor(&color_charging); 800b6cc: 4819 ldr r0, [pc, #100] @ (800b734 ) 800b6ce: f000 f8e3 bl 800b898 break; 800b6d2: e01f b.n 800b714 case ChargingPausedEVSE: LED_SetColor(&color_charging); 800b6d4: 4817 ldr r0, [pc, #92] @ (800b734 ) 800b6d6: f000 f8df bl 800b898 break; 800b6da: e01b b.n 800b714 case Charging: LED_SetColor(&color_charging); 800b6dc: 4815 ldr r0, [pc, #84] @ (800b734 ) 800b6de: f000 f8db bl 800b898 break; 800b6e2: e017 b.n 800b714 case AuthTimeout: LED_SetColor(&color_finished); 800b6e4: 4814 ldr r0, [pc, #80] @ (800b738 ) 800b6e6: f000 f8d7 bl 800b898 break; 800b6ea: e013 b.n 800b714 case Finished: LED_SetColor(&color_finished); 800b6ec: 4812 ldr r0, [pc, #72] @ (800b738 ) 800b6ee: f000 f8d3 bl 800b898 break; 800b6f2: e00f b.n 800b714 case FinishedEVSE: LED_SetColor(&color_finished); 800b6f4: 4810 ldr r0, [pc, #64] @ (800b738 ) 800b6f6: f000 f8cf bl 800b898 break; 800b6fa: e00b b.n 800b714 case FinishedEV: LED_SetColor(&color_finished); 800b6fc: 480e ldr r0, [pc, #56] @ (800b738 ) 800b6fe: f000 f8cb bl 800b898 break; 800b702: e007 b.n 800b714 case Replugging: LED_SetColor(&color_preparing); 800b704: 480a ldr r0, [pc, #40] @ (800b730 ) 800b706: f000 f8c7 bl 800b898 break; 800b70a: e003 b.n 800b714 default: LED_SetColor(&color_unknown); 800b70c: 4806 ldr r0, [pc, #24] @ (800b728 ) 800b70e: f000 f8c3 bl 800b898 break; 800b712: bf00 nop } } 800b714: bd80 pop {r7, pc} 800b716: bf00 nop 800b718: 200003b0 .word 0x200003b0 800b71c: 20000060 .word 0x20000060 800b720: 20000018 .word 0x20000018 800b724: 2000000c .word 0x2000000c 800b728: 20000024 .word 0x20000024 800b72c: 20000030 .word 0x20000030 800b730: 2000003c .word 0x2000003c 800b734: 20000048 .word 0x20000048 800b738: 20000054 .word 0x20000054 0800b73c : void interpolateColors(RGB_t* color1, RGB_t* color2, uint16_t a, uint16_t b, RGB_t *result) { 800b73c: b480 push {r7} 800b73e: b087 sub sp, #28 800b740: af00 add r7, sp, #0 800b742: 60f8 str r0, [r7, #12] 800b744: 60b9 str r1, [r7, #8] 800b746: 4611 mov r1, r2 800b748: 461a mov r2, r3 800b74a: 460b mov r3, r1 800b74c: 80fb strh r3, [r7, #6] 800b74e: 4613 mov r3, r2 800b750: 80bb strh r3, [r7, #4] // Проверяем, чтобы a не выходила за пределы диапазона if (a > b) a = b; 800b752: 88fa ldrh r2, [r7, #6] 800b754: 88bb ldrh r3, [r7, #4] 800b756: 429a cmp r2, r3 800b758: d901 bls.n 800b75e 800b75a: 88bb ldrh r3, [r7, #4] 800b75c: 80fb strh r3, [r7, #6] if(b==0) b = 1; 800b75e: 88bb ldrh r3, [r7, #4] 800b760: 2b00 cmp r3, #0 800b762: d101 bne.n 800b768 800b764: 2301 movs r3, #1 800b766: 80bb strh r3, [r7, #4] // Вычисляем коэффициент смешивания в виде целого числа uint16_t t = (a * 255) / b; // t будет от 0 до 255 800b768: 88fa ldrh r2, [r7, #6] 800b76a: 4613 mov r3, r2 800b76c: 021b lsls r3, r3, #8 800b76e: 1a9a subs r2, r3, r2 800b770: 88bb ldrh r3, [r7, #4] 800b772: fb92 f3f3 sdiv r3, r2, r3 800b776: 82fb strh r3, [r7, #22] // Линейная интерполяция с использованием целых чисел result->R = (color1->R * (255 - t) + color2->R * t) / 255; 800b778: 68fb ldr r3, [r7, #12] 800b77a: 781b ldrb r3, [r3, #0] 800b77c: 461a mov r2, r3 800b77e: 8afb ldrh r3, [r7, #22] 800b780: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b784: fb03 f202 mul.w r2, r3, r2 800b788: 68bb ldr r3, [r7, #8] 800b78a: 781b ldrb r3, [r3, #0] 800b78c: 4619 mov r1, r3 800b78e: 8afb ldrh r3, [r7, #22] 800b790: fb01 f303 mul.w r3, r1, r3 800b794: 4413 add r3, r2 800b796: 4a20 ldr r2, [pc, #128] @ (800b818 ) 800b798: fb82 1203 smull r1, r2, r2, r3 800b79c: 441a add r2, r3 800b79e: 11d2 asrs r2, r2, #7 800b7a0: 17db asrs r3, r3, #31 800b7a2: 1ad3 subs r3, r2, r3 800b7a4: b2da uxtb r2, r3 800b7a6: 6a3b ldr r3, [r7, #32] 800b7a8: 701a strb r2, [r3, #0] result->G = (color1->G * (255 - t) + color2->G * t) / 255; 800b7aa: 68fb ldr r3, [r7, #12] 800b7ac: 785b ldrb r3, [r3, #1] 800b7ae: 461a mov r2, r3 800b7b0: 8afb ldrh r3, [r7, #22] 800b7b2: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b7b6: fb03 f202 mul.w r2, r3, r2 800b7ba: 68bb ldr r3, [r7, #8] 800b7bc: 785b ldrb r3, [r3, #1] 800b7be: 4619 mov r1, r3 800b7c0: 8afb ldrh r3, [r7, #22] 800b7c2: fb01 f303 mul.w r3, r1, r3 800b7c6: 4413 add r3, r2 800b7c8: 4a13 ldr r2, [pc, #76] @ (800b818 ) 800b7ca: fb82 1203 smull r1, r2, r2, r3 800b7ce: 441a add r2, r3 800b7d0: 11d2 asrs r2, r2, #7 800b7d2: 17db asrs r3, r3, #31 800b7d4: 1ad3 subs r3, r2, r3 800b7d6: b2da uxtb r2, r3 800b7d8: 6a3b ldr r3, [r7, #32] 800b7da: 705a strb r2, [r3, #1] result->B = (color1->B * (255 - t) + color2->B * t) / 255; 800b7dc: 68fb ldr r3, [r7, #12] 800b7de: 789b ldrb r3, [r3, #2] 800b7e0: 461a mov r2, r3 800b7e2: 8afb ldrh r3, [r7, #22] 800b7e4: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b7e8: fb03 f202 mul.w r2, r3, r2 800b7ec: 68bb ldr r3, [r7, #8] 800b7ee: 789b ldrb r3, [r3, #2] 800b7f0: 4619 mov r1, r3 800b7f2: 8afb ldrh r3, [r7, #22] 800b7f4: fb01 f303 mul.w r3, r1, r3 800b7f8: 4413 add r3, r2 800b7fa: 4a07 ldr r2, [pc, #28] @ (800b818 ) 800b7fc: fb82 1203 smull r1, r2, r2, r3 800b800: 441a add r2, r3 800b802: 11d2 asrs r2, r2, #7 800b804: 17db asrs r3, r3, #31 800b806: 1ad3 subs r3, r2, r3 800b808: b2da uxtb r2, r3 800b80a: 6a3b ldr r3, [r7, #32] 800b80c: 709a strb r2, [r3, #2] } 800b80e: bf00 nop 800b810: 371c adds r7, #28 800b812: 46bd mov sp, r7 800b814: bc80 pop {r7} 800b816: 4770 bx lr 800b818: 80808081 .word 0x80808081 0800b81c : void RGB_SetColor(RGB_t *color){ 800b81c: b480 push {r7} 800b81e: b083 sub sp, #12 800b820: af00 add r7, sp, #0 800b822: 6078 str r0, [r7, #4] htim4.Instance->CCR2 = color->R * 100 / 255; 800b824: 687b ldr r3, [r7, #4] 800b826: 781b ldrb r3, [r3, #0] 800b828: 461a mov r2, r3 800b82a: 2364 movs r3, #100 @ 0x64 800b82c: fb02 f303 mul.w r3, r2, r3 800b830: 4a17 ldr r2, [pc, #92] @ (800b890 ) 800b832: fb82 1203 smull r1, r2, r2, r3 800b836: 441a add r2, r3 800b838: 11d2 asrs r2, r2, #7 800b83a: 17db asrs r3, r3, #31 800b83c: 1ad2 subs r2, r2, r3 800b83e: 4b15 ldr r3, [pc, #84] @ (800b894 ) 800b840: 681b ldr r3, [r3, #0] 800b842: 639a str r2, [r3, #56] @ 0x38 htim4.Instance->CCR3 = color->G * 100 / 255; 800b844: 687b ldr r3, [r7, #4] 800b846: 785b ldrb r3, [r3, #1] 800b848: 461a mov r2, r3 800b84a: 2364 movs r3, #100 @ 0x64 800b84c: fb02 f303 mul.w r3, r2, r3 800b850: 4a0f ldr r2, [pc, #60] @ (800b890 ) 800b852: fb82 1203 smull r1, r2, r2, r3 800b856: 441a add r2, r3 800b858: 11d2 asrs r2, r2, #7 800b85a: 17db asrs r3, r3, #31 800b85c: 1ad2 subs r2, r2, r3 800b85e: 4b0d ldr r3, [pc, #52] @ (800b894 ) 800b860: 681b ldr r3, [r3, #0] 800b862: 63da str r2, [r3, #60] @ 0x3c htim4.Instance->CCR4 = color->B * 100 / 255; 800b864: 687b ldr r3, [r7, #4] 800b866: 789b ldrb r3, [r3, #2] 800b868: 461a mov r2, r3 800b86a: 2364 movs r3, #100 @ 0x64 800b86c: fb02 f303 mul.w r3, r2, r3 800b870: 4a07 ldr r2, [pc, #28] @ (800b890 ) 800b872: fb82 1203 smull r1, r2, r2, r3 800b876: 441a add r2, r3 800b878: 11d2 asrs r2, r2, #7 800b87a: 17db asrs r3, r3, #31 800b87c: 1ad2 subs r2, r2, r3 800b87e: 4b05 ldr r3, [pc, #20] @ (800b894 ) 800b880: 681b ldr r3, [r3, #0] 800b882: 641a str r2, [r3, #64] @ 0x40 } 800b884: bf00 nop 800b886: 370c adds r7, #12 800b888: 46bd mov sp, r7 800b88a: bc80 pop {r7} 800b88c: 4770 bx lr 800b88e: bf00 nop 800b890: 80808081 .word 0x80808081 800b894: 20001108 .word 0x20001108 0800b898 : void LED_SetColor(RGB_Cycle_t *color){ 800b898: b480 push {r7} 800b89a: b083 sub sp, #12 800b89c: af00 add r7, sp, #0 800b89e: 6078 str r0, [r7, #4] memcpy(&LED_Cycle, color, sizeof(RGB_Cycle_t)); 800b8a0: 4b05 ldr r3, [pc, #20] @ (800b8b8 ) 800b8a2: 687a ldr r2, [r7, #4] 800b8a4: 6810 ldr r0, [r2, #0] 800b8a6: 6851 ldr r1, [r2, #4] 800b8a8: c303 stmia r3!, {r0, r1} 800b8aa: 8912 ldrh r2, [r2, #8] 800b8ac: 801a strh r2, [r3, #0] } 800b8ae: bf00 nop 800b8b0: 370c adds r7, #12 800b8b2: 46bd mov sp, r7 800b8b4: bc80 pop {r7} 800b8b6: 4770 bx lr 800b8b8: 20000968 .word 0x20000968 0800b8bc : void LED_Init(){ 800b8bc: b580 push {r7, lr} 800b8be: b082 sub sp, #8 800b8c0: af00 add r7, sp, #0 RGB_t color = {.R=0, .G=0, .B=0}; 800b8c2: 2300 movs r3, #0 800b8c4: 713b strb r3, [r7, #4] 800b8c6: 2300 movs r3, #0 800b8c8: 717b strb r3, [r7, #5] 800b8ca: 2300 movs r3, #0 800b8cc: 71bb strb r3, [r7, #6] HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_2); 800b8ce: 2104 movs r1, #4 800b8d0: 4809 ldr r0, [pc, #36] @ (800b8f8 ) 800b8d2: f006 fb51 bl 8011f78 HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); 800b8d6: 2108 movs r1, #8 800b8d8: 4807 ldr r0, [pc, #28] @ (800b8f8 ) 800b8da: f006 fb4d bl 8011f78 HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_4); 800b8de: 210c movs r1, #12 800b8e0: 4805 ldr r0, [pc, #20] @ (800b8f8 ) 800b8e2: f006 fb49 bl 8011f78 RGB_SetColor(&color); 800b8e6: 1d3b adds r3, r7, #4 800b8e8: 4618 mov r0, r3 800b8ea: f7ff ff97 bl 800b81c } 800b8ee: bf00 nop 800b8f0: 3708 adds r7, #8 800b8f2: 46bd mov sp, r7 800b8f4: bd80 pop {r7, pc} 800b8f6: bf00 nop 800b8f8: 20001108 .word 0x20001108 0800b8fc : // } // } // } // } void LED_Task(){ 800b8fc: b580 push {r7, lr} 800b8fe: b082 sub sp, #8 800b900: af02 add r7, sp, #8 static uint32_t led_tick; if((HAL_GetTick() - led_tick) > 20){ 800b902: f002 fb87 bl 800e014 800b906: 4602 mov r2, r0 800b908: 4b46 ldr r3, [pc, #280] @ (800ba24 ) 800b90a: 681b ldr r3, [r3, #0] 800b90c: 1ad3 subs r3, r2, r3 800b90e: 2b14 cmp r3, #20 800b910: f240 8085 bls.w 800ba1e led_tick = HAL_GetTick(); 800b914: f002 fb7e bl 800e014 800b918: 4603 mov r3, r0 800b91a: 4a42 ldr r2, [pc, #264] @ (800ba24 ) 800b91c: 6013 str r3, [r2, #0] LED_State.tick++; 800b91e: 4b42 ldr r3, [pc, #264] @ (800ba28 ) 800b920: 885b ldrh r3, [r3, #2] 800b922: 3301 adds r3, #1 800b924: b29a uxth r2, r3 800b926: 4b40 ldr r3, [pc, #256] @ (800ba28 ) 800b928: 805a strh r2, [r3, #2] // LED_PhaseSync(led_n); switch(LED_State.state){ 800b92a: 4b3f ldr r3, [pc, #252] @ (800ba28 ) 800b92c: 781b ldrb r3, [r3, #0] 800b92e: 2b03 cmp r3, #3 800b930: d867 bhi.n 800ba02 800b932: a201 add r2, pc, #4 @ (adr r2, 800b938 ) 800b934: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b938: 0800b949 .word 0x0800b949 800b93c: 0800b97b .word 0x0800b97b 800b940: 0800b9a7 .word 0x0800b9a7 800b944: 0800b9d9 .word 0x0800b9d9 case LED_RISING: interpolateColors(&LED_Cycle.Color2, &LED_Cycle.Color1, LED_State.tick, LED_Cycle.Tr, &LED_State.color); 800b948: 4b37 ldr r3, [pc, #220] @ (800ba28 ) 800b94a: 885a ldrh r2, [r3, #2] 800b94c: 4b37 ldr r3, [pc, #220] @ (800ba2c ) 800b94e: 78db ldrb r3, [r3, #3] 800b950: 4619 mov r1, r3 800b952: 4b37 ldr r3, [pc, #220] @ (800ba30 ) 800b954: 9300 str r3, [sp, #0] 800b956: 460b mov r3, r1 800b958: 4934 ldr r1, [pc, #208] @ (800ba2c ) 800b95a: 4836 ldr r0, [pc, #216] @ (800ba34 ) 800b95c: f7ff feee bl 800b73c if(LED_State.tick>LED_Cycle.Tr){ 800b960: 4b31 ldr r3, [pc, #196] @ (800ba28 ) 800b962: 885b ldrh r3, [r3, #2] 800b964: 4a31 ldr r2, [pc, #196] @ (800ba2c ) 800b966: 78d2 ldrb r2, [r2, #3] 800b968: 4293 cmp r3, r2 800b96a: d94e bls.n 800ba0a LED_State.state = LED_HIGH; 800b96c: 4b2e ldr r3, [pc, #184] @ (800ba28 ) 800b96e: 2201 movs r2, #1 800b970: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b972: 4b2d ldr r3, [pc, #180] @ (800ba28 ) 800b974: 2200 movs r2, #0 800b976: 805a strh r2, [r3, #2] } break; 800b978: e047 b.n 800ba0a case LED_HIGH: memcpy(&LED_State.color, &LED_Cycle.Color1, sizeof(RGB_t)); 800b97a: 4b2b ldr r3, [pc, #172] @ (800ba28 ) 800b97c: 4a2b ldr r2, [pc, #172] @ (800ba2c ) 800b97e: 3304 adds r3, #4 800b980: 6812 ldr r2, [r2, #0] 800b982: 4611 mov r1, r2 800b984: 8019 strh r1, [r3, #0] 800b986: 3302 adds r3, #2 800b988: 0c12 lsrs r2, r2, #16 800b98a: 701a strb r2, [r3, #0] if(LED_State.tick>LED_Cycle.Th){ 800b98c: 4b26 ldr r3, [pc, #152] @ (800ba28 ) 800b98e: 885b ldrh r3, [r3, #2] 800b990: 4a26 ldr r2, [pc, #152] @ (800ba2c ) 800b992: 7912 ldrb r2, [r2, #4] 800b994: 4293 cmp r3, r2 800b996: d93a bls.n 800ba0e LED_State.state = LED_FALLING; 800b998: 4b23 ldr r3, [pc, #140] @ (800ba28 ) 800b99a: 2202 movs r2, #2 800b99c: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b99e: 4b22 ldr r3, [pc, #136] @ (800ba28 ) 800b9a0: 2200 movs r2, #0 800b9a2: 805a strh r2, [r3, #2] } break; 800b9a4: e033 b.n 800ba0e case LED_FALLING: interpolateColors(&LED_Cycle.Color1, &LED_Cycle.Color2, LED_State.tick, LED_Cycle.Tf, &LED_State.color); 800b9a6: 4b20 ldr r3, [pc, #128] @ (800ba28 ) 800b9a8: 885a ldrh r2, [r3, #2] 800b9aa: 4b20 ldr r3, [pc, #128] @ (800ba2c ) 800b9ac: 795b ldrb r3, [r3, #5] 800b9ae: 4619 mov r1, r3 800b9b0: 4b1f ldr r3, [pc, #124] @ (800ba30 ) 800b9b2: 9300 str r3, [sp, #0] 800b9b4: 460b mov r3, r1 800b9b6: 491f ldr r1, [pc, #124] @ (800ba34 ) 800b9b8: 481c ldr r0, [pc, #112] @ (800ba2c ) 800b9ba: f7ff febf bl 800b73c if(LED_State.tick>LED_Cycle.Tf){ 800b9be: 4b1a ldr r3, [pc, #104] @ (800ba28 ) 800b9c0: 885b ldrh r3, [r3, #2] 800b9c2: 4a1a ldr r2, [pc, #104] @ (800ba2c ) 800b9c4: 7952 ldrb r2, [r2, #5] 800b9c6: 4293 cmp r3, r2 800b9c8: d923 bls.n 800ba12 LED_State.state = LED_LOW; 800b9ca: 4b17 ldr r3, [pc, #92] @ (800ba28 ) 800b9cc: 2203 movs r2, #3 800b9ce: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b9d0: 4b15 ldr r3, [pc, #84] @ (800ba28 ) 800b9d2: 2200 movs r2, #0 800b9d4: 805a strh r2, [r3, #2] } break; 800b9d6: e01c b.n 800ba12 case LED_LOW: memcpy(&LED_State.color, &LED_Cycle.Color2, sizeof(RGB_t)); 800b9d8: 4b13 ldr r3, [pc, #76] @ (800ba28 ) 800b9da: 4a14 ldr r2, [pc, #80] @ (800ba2c ) 800b9dc: 3304 adds r3, #4 800b9de: 3207 adds r2, #7 800b9e0: 8811 ldrh r1, [r2, #0] 800b9e2: 7892 ldrb r2, [r2, #2] 800b9e4: 8019 strh r1, [r3, #0] 800b9e6: 709a strb r2, [r3, #2] if(LED_State.tick>LED_Cycle.Tl){ 800b9e8: 4b0f ldr r3, [pc, #60] @ (800ba28 ) 800b9ea: 885b ldrh r3, [r3, #2] 800b9ec: 4a0f ldr r2, [pc, #60] @ (800ba2c ) 800b9ee: 7992 ldrb r2, [r2, #6] 800b9f0: 4293 cmp r3, r2 800b9f2: d910 bls.n 800ba16 LED_State.state = LED_RISING; 800b9f4: 4b0c ldr r3, [pc, #48] @ (800ba28 ) 800b9f6: 2200 movs r2, #0 800b9f8: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b9fa: 4b0b ldr r3, [pc, #44] @ (800ba28 ) 800b9fc: 2200 movs r2, #0 800b9fe: 805a strh r2, [r3, #2] } break; 800ba00: e009 b.n 800ba16 default: LED_State.state = LED_RISING; 800ba02: 4b09 ldr r3, [pc, #36] @ (800ba28 ) 800ba04: 2200 movs r2, #0 800ba06: 701a strb r2, [r3, #0] 800ba08: e006 b.n 800ba18 break; 800ba0a: bf00 nop 800ba0c: e004 b.n 800ba18 break; 800ba0e: bf00 nop 800ba10: e002 b.n 800ba18 break; 800ba12: bf00 nop 800ba14: e000 b.n 800ba18 break; 800ba16: bf00 nop } RGB_SetColor(&LED_State.color); 800ba18: 4805 ldr r0, [pc, #20] @ (800ba30 ) 800ba1a: f7ff feff bl 800b81c } } 800ba1e: bf00 nop 800ba20: 46bd mov sp, r7 800ba22: bd80 pop {r7, pc} 800ba24: 20000974 .word 0x20000974 800ba28: 20000960 .word 0x20000960 800ba2c: 20000968 .word 0x20000968 800ba30: 20000964 .word 0x20000964 800ba34: 2000096f .word 0x2000096f 0800ba38 : RTC_HandleTypeDef hrtc; /* RTC init function */ void MX_RTC_Init(void) { 800ba38: b580 push {r7, lr} 800ba3a: af00 add r7, sp, #0 /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; 800ba3c: 4b0a ldr r3, [pc, #40] @ (800ba68 ) 800ba3e: 4a0b ldr r2, [pc, #44] @ (800ba6c ) 800ba40: 601a str r2, [r3, #0] hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; 800ba42: 4b09 ldr r3, [pc, #36] @ (800ba68 ) 800ba44: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800ba48: 605a str r2, [r3, #4] hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM; 800ba4a: 4b07 ldr r3, [pc, #28] @ (800ba68 ) 800ba4c: f44f 7280 mov.w r2, #256 @ 0x100 800ba50: 609a str r2, [r3, #8] if (HAL_RTC_Init(&hrtc) != HAL_OK) 800ba52: 4805 ldr r0, [pc, #20] @ (800ba68 ) 800ba54: f005 ffde bl 8011a14 800ba58: 4603 mov r3, r0 800ba5a: 2b00 cmp r3, #0 800ba5c: d001 beq.n 800ba62 { Error_Handler(); 800ba5e: f7ff f8b7 bl 800abd0 } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } 800ba62: bf00 nop 800ba64: bd80 pop {r7, pc} 800ba66: bf00 nop 800ba68: 20000978 .word 0x20000978 800ba6c: 40002800 .word 0x40002800 0800ba70 : void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) { 800ba70: b580 push {r7, lr} 800ba72: b084 sub sp, #16 800ba74: af00 add r7, sp, #0 800ba76: 6078 str r0, [r7, #4] if(rtcHandle->Instance==RTC) 800ba78: 687b ldr r3, [r7, #4] 800ba7a: 681b ldr r3, [r3, #0] 800ba7c: 4a0b ldr r2, [pc, #44] @ (800baac ) 800ba7e: 4293 cmp r3, r2 800ba80: d110 bne.n 800baa4 { /* USER CODE BEGIN RTC_MspInit 0 */ /* USER CODE END RTC_MspInit 0 */ HAL_PWR_EnableBkUpAccess(); 800ba82: f004 ff5b bl 801093c /* Enable BKP CLK enable for backup registers */ __HAL_RCC_BKP_CLK_ENABLE(); 800ba86: 4b0a ldr r3, [pc, #40] @ (800bab0 ) 800ba88: 69db ldr r3, [r3, #28] 800ba8a: 4a09 ldr r2, [pc, #36] @ (800bab0 ) 800ba8c: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800ba90: 61d3 str r3, [r2, #28] 800ba92: 4b07 ldr r3, [pc, #28] @ (800bab0 ) 800ba94: 69db ldr r3, [r3, #28] 800ba96: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800ba9a: 60fb str r3, [r7, #12] 800ba9c: 68fb ldr r3, [r7, #12] /* RTC clock enable */ __HAL_RCC_RTC_ENABLE(); 800ba9e: 4b05 ldr r3, [pc, #20] @ (800bab4 ) 800baa0: 2201 movs r2, #1 800baa2: 601a str r2, [r3, #0] /* USER CODE BEGIN RTC_MspInit 1 */ /* USER CODE END RTC_MspInit 1 */ } } 800baa4: bf00 nop 800baa6: 3710 adds r7, #16 800baa8: 46bd mov sp, r7 800baaa: bd80 pop {r7, pc} 800baac: 40002800 .word 0x40002800 800bab0: 40021000 .word 0x40021000 800bab4: 4242043c .word 0x4242043c 0800bab8 : CCS_ConnectorState_t CCS_ConnectorState = CCS_UNKNOWN; ISR_FAST static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len); static void CCS_UART3_Watchdog(void); ISR_FAST static void uart3_log_hal_error(uint8_t uart_num, uint32_t err) { 800bab8: 4602 mov r2, r0 if (err == HAL_UART_ERROR_NONE) { 800baba: b359 cbz r1, 800bb14 ISR_FAST static void uart3_log_hal_error(uint8_t uart_num, uint32_t err) { 800babc: b570 push {r4, r5, r6, lr} 800babe: 460c mov r4, r1 log_printf(LOG_ERR, "UART%u HAL error decode: NONE\n", uart_num); return; } log_printf(LOG_ERR, "UART%u HAL error decode: %s%s%s%s%s%s raw=0x%08lx\n", 800bac0: 07cb lsls r3, r1, #31 800bac2: bf58 it pl 800bac4: 4915 ldrpl r1, [pc, #84] @ (800bb1c ) 800bac6: 4d15 ldr r5, [pc, #84] @ (800bb1c ) 800bac8: bf48 it mi 800baca: 4914 ldrmi r1, [pc, #80] @ (800bb1c ) ISR_FAST static void uart3_log_hal_error(uint8_t uart_num, uint32_t err) { 800bacc: b086 sub sp, #24 log_printf(LOG_ERR, "UART%u HAL error decode: %s%s%s%s%s%s raw=0x%08lx\n", 800bace: bf54 ite pl 800bad0: 460b movpl r3, r1 800bad2: 4b13 ldrmi r3, [pc, #76] @ (800bb20 ) 800bad4: f014 0f02 tst.w r4, #2 800bad8: 9104 str r1, [sp, #16] 800bada: 4912 ldr r1, [pc, #72] @ (800bb24 ) 800badc: bf08 it eq 800bade: 4629 moveq r1, r5 800bae0: f014 0f04 tst.w r4, #4 800bae4: 4810 ldr r0, [pc, #64] @ (800bb28 ) 800bae6: bf08 it eq 800bae8: 4628 moveq r0, r5 800baea: f014 0f08 tst.w r4, #8 800baee: 9001 str r0, [sp, #4] 800baf0: 480e ldr r0, [pc, #56] @ (800bb2c ) 800baf2: 4e0f ldr r6, [pc, #60] @ (800bb30 ) 800baf4: bf08 it eq 800baf6: 462e moveq r6, r5 800baf8: f014 0f10 tst.w r4, #16 800bafc: bf18 it ne 800bafe: 4605 movne r5, r0 800bb00: 9100 str r1, [sp, #0] 800bb02: e9cd 6502 strd r6, r5, [sp, #8] 800bb06: 490b ldr r1, [pc, #44] @ (800bb34 ) 800bb08: 9405 str r4, [sp, #20] 800bb0a: 2004 movs r0, #4 800bb0c: f7fe fce8 bl 800a4e0 (err & HAL_UART_ERROR_INVALID_CALLBACK) ? "INV_CB " : "", #else "", #endif (unsigned long)err); } 800bb10: b006 add sp, #24 800bb12: bd70 pop {r4, r5, r6, pc} log_printf(LOG_ERR, "UART%u HAL error decode: NONE\n", uart_num); 800bb14: 2004 movs r0, #4 800bb16: 4908 ldr r1, [pc, #32] @ (800bb38 ) 800bb18: f7fe bce2 b.w 800a4e0 800bb1c: 08016fbc .word 0x08016fbc 800bb20: 08016c14 .word 0x08016c14 800bb24: 08016c18 .word 0x08016c18 800bb28: 08016c1c .word 0x08016c1c 800bb2c: 08016c28 .word 0x08016c28 800bb30: 08016c20 .word 0x08016c20 800bb34: 08016c50 .word 0x08016c50 800bb38: 08016c30 .word 0x08016c30 0800bb3c : ISR_FAST static void uart3_arm_rx_or_log(const char *where) { 800bb3c: b530 push {r4, r5, lr} HAL_StatusTypeDef st = HAL_UARTEx_ReceiveToIdle_IT(&huart3, rx_buffer, sizeof(rx_buffer)); 800bb3e: f44f 7280 mov.w r2, #256 @ 0x100 ISR_FAST static void uart3_arm_rx_or_log(const char *where) { 800bb42: 4605 mov r5, r0 800bb44: b083 sub sp, #12 HAL_StatusTypeDef st = HAL_UARTEx_ReceiveToIdle_IT(&huart3, rx_buffer, sizeof(rx_buffer)); 800bb46: 4910 ldr r1, [pc, #64] @ (800bb88 ) 800bb48: 4810 ldr r0, [pc, #64] @ (800bb8c ) 800bb4a: f007 f9aa bl 8012ea2 if (st == HAL_OK) { 800bb4e: b908 cbnz r0, 800bb54 where, (int)st, (unsigned long)err_after); uart3_log_hal_error(3u, err_after); if (err_after != HAL_UART_ERROR_NONE) { (void)HAL_UART_Abort_IT(&huart3); } } 800bb50: b003 add sp, #12 800bb52: bd30 pop {r4, r5, pc} uint32_t err_after = HAL_UART_GetError(&huart3); 800bb54: 4604 mov r4, r0 800bb56: 480d ldr r0, [pc, #52] @ (800bb8c ) 800bb58: f007 fdb8 bl 80136cc 800bb5c: 4602 mov r2, r0 log_printf(LOG_ERR, 800bb5e: 4623 mov r3, r4 uint32_t err_after = HAL_UART_GetError(&huart3); 800bb60: 4614 mov r4, r2 log_printf(LOG_ERR, 800bb62: 490b ldr r1, [pc, #44] @ (800bb90 ) 800bb64: 2004 movs r0, #4 800bb66: 462a mov r2, r5 800bb68: 9400 str r4, [sp, #0] 800bb6a: f7fe fcb9 bl 800a4e0 uart3_log_hal_error(3u, err_after); 800bb6e: 4621 mov r1, r4 800bb70: 2003 movs r0, #3 800bb72: f7ff ffa1 bl 800bab8 if (err_after != HAL_UART_ERROR_NONE) { 800bb76: 2c00 cmp r4, #0 800bb78: d0ea beq.n 800bb50 (void)HAL_UART_Abort_IT(&huart3); 800bb7a: 4804 ldr r0, [pc, #16] @ (800bb8c ) } 800bb7c: b003 add sp, #12 800bb7e: e8bd 4030 ldmia.w sp!, {r4, r5, lr} (void)HAL_UART_Abort_IT(&huart3); 800bb82: f007 b9eb b.w 8012f5c 800bb86: bf00 nop 800bb88: 200009b0 .word 0x200009b0 800bb8c: 20001228 .word 0x20001228 800bb90: 08016c84 .word 0x08016c84 0800bb94 : ISR_FAST void CCS_RxEventCallback(UART_HandleTypeDef *huart, uint16_t size) { 800bb94: b538 push {r3, r4, r5, lr} if (huart != &huart3) { 800bb96: 4b1a ldr r3, [pc, #104] @ (800bc00 ) ISR_FAST void CCS_RxEventCallback(UART_HandleTypeDef *huart, uint16_t size) { 800bb98: 460c mov r4, r1 if (huart != &huart3) { 800bb9a: 4283 cmp r3, r0 800bb9c: d113 bne.n 800bbc6 log_printf(LOG_WARN, "UART3 RX drop: wrong huart in RxEventCallback (size=%u)\n", (unsigned)size); return; } if (size == 0u) { 800bb9e: b329 cbz r1, 800bbec log_printf(LOG_WARN, "UART3 RX drop: RxEvent size=0 (idle, no payload)\n"); uart3_arm_rx_or_log("RxEventCallback"); return; } if (size > sizeof(rx_buffer)) { 800bba0: f5b1 7f80 cmp.w r1, #256 @ 0x100 800bba4: d816 bhi.n 800bbd4 log_printf(LOG_ERR, "UART3 RX drop: size=%u > rx_buffer %u (overflow, not parsed)\n", (unsigned)size, (unsigned)sizeof(rx_buffer)); uart3_arm_rx_or_log("RxEventCallback"); return; } uart3_last_packet_tick = HAL_GetTick(); 800bba6: f002 fa35 bl 800e014 800bbaa: 4603 mov r3, r0 800bbac: 4d15 ldr r5, [pc, #84] @ (800bc04 ) uart3_last_reinit_tick = uart3_last_packet_tick; 800bbae: 4a16 ldr r2, [pc, #88] @ (800bc08 ) process_received_packet(rx_buffer, size); 800bbb0: 4621 mov r1, r4 800bbb2: 4816 ldr r0, [pc, #88] @ (800bc0c ) uart3_last_packet_tick = HAL_GetTick(); 800bbb4: 602b str r3, [r5, #0] uart3_last_reinit_tick = uart3_last_packet_tick; 800bbb6: 6013 str r3, [r2, #0] process_received_packet(rx_buffer, size); 800bbb8: f000 fd8e bl 800c6d8 uart3_arm_rx_or_log("RxEventCallback"); } 800bbbc: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} uart3_arm_rx_or_log("RxEventCallback"); 800bbc0: 4813 ldr r0, [pc, #76] @ (800bc10 ) 800bbc2: f7ff bfbb b.w 800bb3c log_printf(LOG_WARN, "UART3 RX drop: wrong huart in RxEventCallback (size=%u)\n", 800bbc6: 460a mov r2, r1 } 800bbc8: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} log_printf(LOG_WARN, "UART3 RX drop: wrong huart in RxEventCallback (size=%u)\n", 800bbcc: 2005 movs r0, #5 800bbce: 4911 ldr r1, [pc, #68] @ (800bc14 ) 800bbd0: f7fe bc86 b.w 800a4e0 log_printf(LOG_ERR, "UART3 RX drop: size=%u > rx_buffer %u (overflow, not parsed)\n", 800bbd4: f44f 7380 mov.w r3, #256 @ 0x100 800bbd8: 460a mov r2, r1 800bbda: 2004 movs r0, #4 800bbdc: 490e ldr r1, [pc, #56] @ (800bc18 ) 800bbde: f7fe fc7f bl 800a4e0 } 800bbe2: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} uart3_arm_rx_or_log("RxEventCallback"); 800bbe6: 480a ldr r0, [pc, #40] @ (800bc10 ) 800bbe8: f7ff bfa8 b.w 800bb3c log_printf(LOG_WARN, "UART3 RX drop: RxEvent size=0 (idle, no payload)\n"); 800bbec: 2005 movs r0, #5 800bbee: 490b ldr r1, [pc, #44] @ (800bc1c ) 800bbf0: f7fe fc76 bl 800a4e0 } 800bbf4: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} uart3_arm_rx_or_log("RxEventCallback"); 800bbf8: 4805 ldr r0, [pc, #20] @ (800bc10 ) 800bbfa: f7ff bf9f b.w 800bb3c 800bbfe: bf00 nop 800bc00: 20001228 .word 0x20001228 800bc04: 20000bbc .word 0x20000bbc 800bc08: 20000bc0 .word 0x20000bc0 800bc0c: 200009b0 .word 0x200009b0 800bc10: 08016d30 .word 0x08016d30 800bc14: 08016cc0 .word 0x08016cc0 800bc18: 08016d40 .word 0x08016d40 800bc1c: 08016cfc .word 0x08016cfc 0800bc20 : ISR_FAST void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 800bc20: b5f8 push {r3, r4, r5, r6, r7, lr} 800bc22: 4604 mov r4, r0 uint32_t error = HAL_UART_GetError(huart); 800bc24: f007 fd52 bl 80136cc uint8_t uart_num = 800bc28: 4b1f ldr r3, [pc, #124] @ (800bca8 ) uint32_t error = HAL_UART_GetError(huart); 800bc2a: 4605 mov r5, r0 uint8_t uart_num = 800bc2c: 429c cmp r4, r3 800bc2e: d014 beq.n 800bc5a 800bc30: 4e1e ldr r6, [pc, #120] @ (800bcac ) 800bc32: 42b4 cmp r4, r6 800bc34: d023 beq.n 800bc7e 800bc36: 4b1e ldr r3, [pc, #120] @ (800bcb0 ) 800bc38: 429c cmp r4, r3 800bc3a: d032 beq.n 800bca2 (huart == &huart2) ? 2 : (huart == &huart3) ? 3 : (huart == &huart5) ? 5 : 0; log_printf(LOG_ERR, 800bc3c: 4603 mov r3, r0 800bc3e: 2200 movs r2, #0 800bc40: 491c ldr r1, [pc, #112] @ (800bcb4 ) 800bc42: 2004 movs r0, #4 800bc44: f7fe fc4c bl 800a4e0 "UART%u HAL error (ISR): raw=0x%08lx — RX may be corrupted until re-arm\n", uart_num, (unsigned long)error); uart3_log_hal_error(uart_num, error); 800bc48: 4629 mov r1, r5 800bc4a: 2000 movs r0, #0 800bc4c: f7ff ff34 bl 800bab8 (void)HAL_UART_Abort_IT(huart); 800bc50: 4620 mov r0, r4 if (huart == &huart3) { uart3_arm_rx_or_log("ErrorCallback"); } } 800bc52: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} (void)HAL_UART_Abort_IT(huart); 800bc56: f007 b981 b.w 8012f5c 800bc5a: 2202 movs r2, #2 uint8_t uart_num = 800bc5c: 4617 mov r7, r2 800bc5e: 4e13 ldr r6, [pc, #76] @ (800bcac ) log_printf(LOG_ERR, 800bc60: 462b mov r3, r5 800bc62: 4914 ldr r1, [pc, #80] @ (800bcb4 ) 800bc64: 2004 movs r0, #4 800bc66: f7fe fc3b bl 800a4e0 uart3_log_hal_error(uart_num, error); 800bc6a: 4629 mov r1, r5 800bc6c: 4638 mov r0, r7 800bc6e: f7ff ff23 bl 800bab8 (void)HAL_UART_Abort_IT(huart); 800bc72: 4620 mov r0, r4 800bc74: f007 f972 bl 8012f5c if (huart == &huart3) { 800bc78: 42b4 cmp r4, r6 800bc7a: d00d beq.n 800bc98 } 800bc7c: bdf8 pop {r3, r4, r5, r6, r7, pc} log_printf(LOG_ERR, 800bc7e: 4603 mov r3, r0 800bc80: 2203 movs r2, #3 800bc82: 490c ldr r1, [pc, #48] @ (800bcb4 ) 800bc84: 2004 movs r0, #4 800bc86: f7fe fc2b bl 800a4e0 uart3_log_hal_error(uart_num, error); 800bc8a: 2003 movs r0, #3 800bc8c: 4629 mov r1, r5 800bc8e: f7ff ff13 bl 800bab8 (void)HAL_UART_Abort_IT(huart); 800bc92: 4620 mov r0, r4 800bc94: f007 f962 bl 8012f5c } 800bc98: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} uart3_arm_rx_or_log("ErrorCallback"); 800bc9c: 4806 ldr r0, [pc, #24] @ (800bcb8 ) 800bc9e: f7ff bf4d b.w 800bb3c 800bca2: 2205 movs r2, #5 uint8_t uart_num = 800bca4: 4617 mov r7, r2 800bca6: e7db b.n 800bc60 800bca8: 200011e0 .word 0x200011e0 800bcac: 20001228 .word 0x20001228 800bcb0: 20001150 .word 0x20001150 800bcb4: 08016d80 .word 0x08016d80 800bcb8: 08016dcc .word 0x08016dcc 0800bcbc : void CCS_SerialLoop(void) { 800bcbc: b580 push {r7, lr} 800bcbe: b082 sub sp, #8 800bcc0: af00 add r7, sp, #0 static uint32_t replug_watchdog1_tick = 0; static uint32_t last_state_sent = 0; static uint32_t force_unlock_tick = 0; static uint32_t stop_tick = 0; if ((&huart3)->RxState == HAL_UART_STATE_READY) { 800bcc2: 4ba3 ldr r3, [pc, #652] @ (800bf50 ) 800bcc4: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800bcc8: b2db uxtb r3, r3 800bcca: 2b20 cmp r3, #32 800bccc: d102 bne.n 800bcd4 uart3_arm_rx_or_log("SerialLoop"); 800bcce: 48a1 ldr r0, [pc, #644] @ (800bf54 ) 800bcd0: f7ff ff34 bl 800bb3c } CCS_UART3_Watchdog(); 800bcd4: f000 fd6e bl 800c7b4 if (CONN.connControl != CMD_NONE) { 800bcd8: 4b9f ldr r3, [pc, #636] @ (800bf58 ) 800bcda: 781b ldrb r3, [r3, #0] 800bcdc: 2b00 cmp r3, #0 800bcde: d003 beq.n 800bce8 last_cmd = CONN.connControl; 800bce0: 4b9d ldr r3, [pc, #628] @ (800bf58 ) 800bce2: 781a ldrb r2, [r3, #0] 800bce4: 4b9d ldr r3, [pc, #628] @ (800bf5c ) 800bce6: 701a strb r2, [r3, #0] } if (CONN.connControl == CMD_FORCE_UNLOCK) { 800bce8: 4b9b ldr r3, [pc, #620] @ (800bf58 ) 800bcea: 781b ldrb r3, [r3, #0] 800bcec: 2b03 cmp r3, #3 800bcee: d11a bne.n 800bd26 if (force_unlock_tick == 0) { 800bcf0: 4b9b ldr r3, [pc, #620] @ (800bf60 ) 800bcf2: 681b ldr r3, [r3, #0] 800bcf4: 2b00 cmp r3, #0 800bcf6: d105 bne.n 800bd04 force_unlock_tick = HAL_GetTick(); 800bcf8: f002 f98c bl 800e014 800bcfc: 4603 mov r3, r0 800bcfe: 4a98 ldr r2, [pc, #608] @ (800bf60 ) 800bd00: 6013 str r3, [r2, #0] 800bd02: e013 b.n 800bd2c } else if ((HAL_GetTick() - force_unlock_tick) >= 10000) { 800bd04: f002 f986 bl 800e014 800bd08: 4602 mov r2, r0 800bd0a: 4b95 ldr r3, [pc, #596] @ (800bf60 ) 800bd0c: 681b ldr r3, [r3, #0] 800bd0e: 1ad3 subs r3, r2, r3 800bd10: f242 720f movw r2, #9999 @ 0x270f 800bd14: 4293 cmp r3, r2 800bd16: d909 bls.n 800bd2c CONN.connControl = CMD_NONE; 800bd18: 4b8f ldr r3, [pc, #572] @ (800bf58 ) 800bd1a: 2200 movs r2, #0 800bd1c: 701a strb r2, [r3, #0] force_unlock_tick = 0; 800bd1e: 4b90 ldr r3, [pc, #576] @ (800bf60 ) 800bd20: 2200 movs r2, #0 800bd22: 601a str r2, [r3, #0] 800bd24: e002 b.n 800bd2c } } else { force_unlock_tick = 0; 800bd26: 4b8e ldr r3, [pc, #568] @ (800bf60 ) 800bd28: 2200 movs r2, #0 800bd2a: 601a str r2, [r3, #0] } if (CONN.connControl == CMD_STOP) { 800bd2c: 4b8a ldr r3, [pc, #552] @ (800bf58 ) 800bd2e: 781b ldrb r3, [r3, #0] 800bd30: 2b01 cmp r3, #1 800bd32: d119 bne.n 800bd68 if (stop_tick == 0) { 800bd34: 4b8b ldr r3, [pc, #556] @ (800bf64 ) 800bd36: 681b ldr r3, [r3, #0] 800bd38: 2b00 cmp r3, #0 800bd3a: d105 bne.n 800bd48 stop_tick = HAL_GetTick(); 800bd3c: f002 f96a bl 800e014 800bd40: 4603 mov r3, r0 800bd42: 4a88 ldr r2, [pc, #544] @ (800bf64 ) 800bd44: 6013 str r3, [r2, #0] 800bd46: e012 b.n 800bd6e } else if ((HAL_GetTick() - stop_tick) >= 1000) { 800bd48: f002 f964 bl 800e014 800bd4c: 4602 mov r2, r0 800bd4e: 4b85 ldr r3, [pc, #532] @ (800bf64 ) 800bd50: 681b ldr r3, [r3, #0] 800bd52: 1ad3 subs r3, r2, r3 800bd54: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bd58: d309 bcc.n 800bd6e CONN.connControl = CMD_NONE; 800bd5a: 4b7f ldr r3, [pc, #508] @ (800bf58 ) 800bd5c: 2200 movs r2, #0 800bd5e: 701a strb r2, [r3, #0] stop_tick = 0; 800bd60: 4b80 ldr r3, [pc, #512] @ (800bf64 ) 800bd62: 2200 movs r2, #0 800bd64: 601a str r2, [r3, #0] 800bd66: e002 b.n 800bd6e } } else { stop_tick = 0; 800bd68: 4b7e ldr r3, [pc, #504] @ (800bf64 ) 800bd6a: 2200 movs r2, #0 800bd6c: 601a str r2, [r3, #0] } if((HAL_GetTick() - last_cmd_sent) > CMD_INTERVAL){ 800bd6e: f002 f951 bl 800e014 800bd72: 4602 mov r2, r0 800bd74: 4b7c ldr r3, [pc, #496] @ (800bf68 ) 800bd76: 681b ldr r3, [r3, #0] 800bd78: 1ad3 subs r3, r2, r3 800bd7a: 2b0a cmp r3, #10 800bd7c: d95e bls.n 800be3c if ((HAL_GetTick() - last_state_sent) >= 200) { 800bd7e: f002 f949 bl 800e014 800bd82: 4602 mov r2, r0 800bd84: 4b79 ldr r3, [pc, #484] @ (800bf6c ) 800bd86: 681b ldr r3, [r3, #0] 800bd88: 1ad3 subs r3, r2, r3 800bd8a: 2bc7 cmp r3, #199 @ 0xc7 800bd8c: d906 bls.n 800bd9c send_state(); 800bd8e: f000 fb73 bl 800c478 last_state_sent = HAL_GetTick(); 800bd92: f002 f93f bl 800e014 800bd96: 4603 mov r3, r0 800bd98: 4a74 ldr r2, [pc, #464] @ (800bf6c ) 800bd9a: 6013 str r3, [r2, #0] } if (ESTOP) { 800bd9c: 4b74 ldr r3, [pc, #464] @ (800bf70 ) 800bd9e: 781b ldrb r3, [r3, #0] 800bda0: 2b00 cmp r3, #0 800bda2: d008 beq.n 800bdb6 log_printf(LOG_ERR, "ESTOP triggered\n"); 800bda4: 4973 ldr r1, [pc, #460] @ (800bf74 ) 800bda6: 2004 movs r0, #4 800bda8: f7fe fb9a bl 800a4e0 CCS_SendEmergencyStop(); 800bdac: f000 fb04 bl 800c3b8 ESTOP = 0; 800bdb0: 4b6f ldr r3, [pc, #444] @ (800bf70 ) 800bdb2: 2200 movs r2, #0 800bdb4: 701a strb r2, [r3, #0] } if (((CONN.connControl == CMD_STOP) || 800bdb6: 4b68 ldr r3, [pc, #416] @ (800bf58 ) 800bdb8: 781b ldrb r3, [r3, #0] 800bdba: 2b01 cmp r3, #1 800bdbc: d007 beq.n 800bdce (CONN.connControl == CMD_FORCE_UNLOCK) || 800bdbe: 4b66 ldr r3, [pc, #408] @ (800bf58 ) 800bdc0: 781b ldrb r3, [r3, #0] if (((CONN.connControl == CMD_STOP) || 800bdc2: 2b03 cmp r3, #3 800bdc4: d003 beq.n 800bdce (CONN.chargingError != CONN_NO_ERROR)) && 800bdc6: 4b64 ldr r3, [pc, #400] @ (800bf58 ) 800bdc8: 7f5b ldrb r3, [r3, #29] (CONN.connControl == CMD_FORCE_UNLOCK) || 800bdca: 2b00 cmp r3, #0 800bdcc: d01a beq.n 800be04 ((HAL_GetTick() - last_stop_sent) > 1000)) { 800bdce: f002 f921 bl 800e014 800bdd2: 4602 mov r2, r0 800bdd4: 4b68 ldr r3, [pc, #416] @ (800bf78 ) 800bdd6: 681b ldr r3, [r3, #0] 800bdd8: 1ad3 subs r3, r2, r3 (CONN.chargingError != CONN_NO_ERROR)) && 800bdda: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bdde: d911 bls.n 800be04 last_stop_sent = HAL_GetTick(); 800bde0: f002 f918 bl 800e014 800bde4: 4603 mov r3, r0 800bde6: 4a64 ldr r2, [pc, #400] @ (800bf78 ) 800bde8: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "Stopping charging...\n"); 800bdea: 4964 ldr r1, [pc, #400] @ (800bf7c ) 800bdec: 2005 movs r0, #5 800bdee: f7fe fb77 bl 800a4e0 if (CONN.connControl == CMD_FORCE_UNLOCK) { 800bdf2: 4b59 ldr r3, [pc, #356] @ (800bf58 ) 800bdf4: 781b ldrb r3, [r3, #0] 800bdf6: 2b03 cmp r3, #3 800bdf8: d102 bne.n 800be00 CP_SetDuty(100); 800bdfa: 2064 movs r0, #100 @ 0x64 800bdfc: f7fe f93e bl 800a07c } CCS_SendEmergencyStop(); 800be00: f000 fada bl 800c3b8 } if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800be04: 4b5e ldr r3, [pc, #376] @ (800bf80 ) 800be06: 781b ldrb r3, [r3, #0] 800be08: 2b0c cmp r3, #12 800be0a: d003 beq.n 800be14 800be0c: 4b5c ldr r3, [pc, #368] @ (800bf80 ) 800be0e: 781b ldrb r3, [r3, #0] 800be10: 2b0b cmp r3, #11 800be12: d113 bne.n 800be3c ((HAL_GetTick() - last_stop_sent) > 1000)) { 800be14: f002 f8fe bl 800e014 800be18: 4602 mov r2, r0 800be1a: 4b57 ldr r3, [pc, #348] @ (800bf78 ) 800be1c: 681b ldr r3, [r3, #0] 800be1e: 1ad3 subs r3, r2, r3 if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800be20: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800be24: d90a bls.n 800be3c last_stop_sent = HAL_GetTick(); 800be26: f002 f8f5 bl 800e014 800be2a: 4603 mov r3, r0 800be2c: 4a52 ldr r2, [pc, #328] @ (800bf78 ) 800be2e: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "FinishedEV, stopping...\n"); 800be30: 4954 ldr r1, [pc, #336] @ (800bf84 ) 800be32: 2005 movs r0, #5 800be34: f7fe fb54 bl 800a4e0 CCS_SendEmergencyStop(); 800be38: f000 fabe bl 800c3b8 } (void)replug_watchdog_tick; (void)replug_watchdog1_tick; uint32_t now = HAL_GetTick(); 800be3c: f002 f8ea bl 800e014 800be40: 6078 str r0, [r7, #4] uint8_t host_timeout_warn = (last_host_seen > 0 && (now - last_host_seen) > EVEREST_TIMEOUT_WARN_MS); 800be42: 4b51 ldr r3, [pc, #324] @ (800bf88 ) 800be44: 681b ldr r3, [r3, #0] 800be46: 2b00 cmp r3, #0 800be48: d009 beq.n 800be5e 800be4a: 4b4f ldr r3, [pc, #316] @ (800bf88 ) 800be4c: 681b ldr r3, [r3, #0] 800be4e: 687a ldr r2, [r7, #4] 800be50: 1ad3 subs r3, r2, r3 800be52: f241 3288 movw r2, #5000 @ 0x1388 800be56: 4293 cmp r3, r2 800be58: d901 bls.n 800be5e 800be5a: 2301 movs r3, #1 800be5c: e000 b.n 800be60 800be5e: 2300 movs r3, #0 800be60: 70fb strb r3, [r7, #3] uint8_t host_timeout_stop = (last_host_seen > 0 && (now - last_host_seen) > EVEREST_TIMEOUT_STOP_MS); 800be62: 4b49 ldr r3, [pc, #292] @ (800bf88 ) 800be64: 681b ldr r3, [r3, #0] 800be66: 2b00 cmp r3, #0 800be68: d009 beq.n 800be7e 800be6a: 4b47 ldr r3, [pc, #284] @ (800bf88 ) 800be6c: 681b ldr r3, [r3, #0] 800be6e: 687a ldr r2, [r7, #4] 800be70: 1ad3 subs r3, r2, r3 800be72: f242 7210 movw r2, #10000 @ 0x2710 800be76: 4293 cmp r3, r2 800be78: d901 bls.n 800be7e 800be7a: 2301 movs r3, #1 800be7c: e000 b.n 800be80 800be7e: 2300 movs r3, #0 800be80: 70bb strb r3, [r7, #2] uint8_t host_timed_out = host_timeout_stop; 800be82: 78bb ldrb r3, [r7, #2] 800be84: 707b strb r3, [r7, #1] if (host_timeout_warn && !everest_timeout_warn_latched) { 800be86: 78fb ldrb r3, [r7, #3] 800be88: 2b00 cmp r3, #0 800be8a: d00a beq.n 800bea2 800be8c: 4b3f ldr r3, [pc, #252] @ (800bf8c ) 800be8e: 781b ldrb r3, [r3, #0] 800be90: 2b00 cmp r3, #0 800be92: d106 bne.n 800bea2 log_printf(LOG_ERR, "Everest timeout\n"); 800be94: 493e ldr r1, [pc, #248] @ (800bf90 ) 800be96: 2004 movs r0, #4 800be98: f7fe fb22 bl 800a4e0 everest_timeout_warn_latched = 1; 800be9c: 4b3b ldr r3, [pc, #236] @ (800bf8c ) 800be9e: 2201 movs r2, #1 800bea0: 701a strb r2, [r3, #0] } if (host_timeout_stop && !everest_timeout_stop_latched) { 800bea2: 78bb ldrb r3, [r7, #2] 800bea4: 2b00 cmp r3, #0 800bea6: d00a beq.n 800bebe 800bea8: 4b3a ldr r3, [pc, #232] @ (800bf94 ) 800beaa: 781b ldrb r3, [r3, #0] 800beac: 2b00 cmp r3, #0 800beae: d106 bne.n 800bebe log_printf(LOG_ERR, "Everest timeout, stopping charging...\n"); 800beb0: 4939 ldr r1, [pc, #228] @ (800bf98 ) 800beb2: 2004 movs r0, #4 800beb4: f7fe fb14 bl 800a4e0 everest_timeout_stop_latched = 1; 800beb8: 4b36 ldr r3, [pc, #216] @ (800bf94 ) 800beba: 2201 movs r2, #1 800bebc: 701a strb r2, [r3, #0] } if (!host_timeout_warn) { 800bebe: 78fb ldrb r3, [r7, #3] 800bec0: 2b00 cmp r3, #0 800bec2: d105 bne.n 800bed0 everest_timeout_warn_latched = 0; 800bec4: 4b31 ldr r3, [pc, #196] @ (800bf8c ) 800bec6: 2200 movs r2, #0 800bec8: 701a strb r2, [r3, #0] everest_timeout_stop_latched = 0; 800beca: 4b32 ldr r3, [pc, #200] @ (800bf94 ) 800becc: 2200 movs r2, #0 800bece: 701a strb r2, [r3, #0] } everest_timed_out = host_timeout_stop; 800bed0: 4a32 ldr r2, [pc, #200] @ (800bf9c ) 800bed2: 78bb ldrb r3, [r7, #2] 800bed4: 7013 strb r3, [r2, #0] switch(CCS_ConnectorState){ 800bed6: 4b32 ldr r3, [pc, #200] @ (800bfa0 ) 800bed8: 781b ldrb r3, [r3, #0] 800beda: 2b05 cmp r3, #5 800bedc: f200 8116 bhi.w 800c10c 800bee0: a201 add r2, pc, #4 @ (adr r2, 800bee8 ) 800bee2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800bee6: bf00 nop 800bee8: 0800bf01 .word 0x0800bf01 800beec: 0800bf29 .word 0x0800bf29 800bef0: 0800bfa9 .word 0x0800bfa9 800bef4: 0800bfed .word 0x0800bfed 800bef8: 0800c029 .word 0x0800c029 800befc: 0800c081 .word 0x0800c081 case CCS_UNKNOWN: RELAY_Write(RELAY_CP, 0); 800bf00: 2100 movs r1, #0 800bf02: 2005 movs r0, #5 800bf04: f7fd fc58 bl 80097b8 CONN_SetState(Unknown); 800bf08: 2000 movs r0, #0 800bf0a: f7fd ffbf bl 8009e8c if (config_initialized && !host_timed_out) { 800bf0e: 4b25 ldr r3, [pc, #148] @ (800bfa4 ) 800bf10: 781b ldrb r3, [r3, #0] 800bf12: 2b00 cmp r3, #0 800bf14: f000 80ef beq.w 800c0f6 800bf18: 787b ldrb r3, [r7, #1] 800bf1a: 2b00 cmp r3, #0 800bf1c: f040 80eb bne.w 800c0f6 CCS_ConnectorState = CCS_UNPLUGGED; 800bf20: 4b1f ldr r3, [pc, #124] @ (800bfa0 ) 800bf22: 2202 movs r2, #2 800bf24: 701a strb r2, [r3, #0] } break; 800bf26: e0e6 b.n 800c0f6 case CCS_DISABLED: RELAY_Write(RELAY_CP, 0); 800bf28: 2100 movs r1, #0 800bf2a: 2005 movs r0, #5 800bf2c: f7fd fc44 bl 80097b8 CONN_SetState(Disabled); 800bf30: 2002 movs r0, #2 800bf32: f7fd ffab bl 8009e8c if ((CONN.chargingError == CONN_NO_ERROR) && !host_timed_out){ 800bf36: 4b08 ldr r3, [pc, #32] @ (800bf58 ) 800bf38: 7f5b ldrb r3, [r3, #29] 800bf3a: 2b00 cmp r3, #0 800bf3c: f040 80dd bne.w 800c0fa 800bf40: 787b ldrb r3, [r7, #1] 800bf42: 2b00 cmp r3, #0 800bf44: f040 80d9 bne.w 800c0fa CCS_ConnectorState = CCS_UNPLUGGED; 800bf48: 4b15 ldr r3, [pc, #84] @ (800bfa0 ) 800bf4a: 2202 movs r2, #2 800bf4c: 701a strb r2, [r3, #0] } break; 800bf4e: e0d4 b.n 800c0fa 800bf50: 20001228 .word 0x20001228 800bf54: 08016ddc .word 0x08016ddc 800bf58: 200003b0 .word 0x200003b0 800bf5c: 200009ac .word 0x200009ac 800bf60: 20000c14 .word 0x20000c14 800bf64: 20000c18 .word 0x20000c18 800bf68: 200009a4 .word 0x200009a4 800bf6c: 20000c1c .word 0x20000c1c 800bf70: 20000bb0 .word 0x20000bb0 800bf74: 08016de8 .word 0x08016de8 800bf78: 200009a8 .word 0x200009a8 800bf7c: 08016dfc .word 0x08016dfc 800bf80: 20000c10 .word 0x20000c10 800bf84: 08016e14 .word 0x08016e14 800bf88: 20000bb4 .word 0x20000bb4 800bf8c: 20000bba .word 0x20000bba 800bf90: 08016e30 .word 0x08016e30 800bf94: 20000bbb .word 0x20000bbb 800bf98: 08016e44 .word 0x08016e44 800bf9c: 20000bb9 .word 0x20000bb9 800bfa0: 20000c11 .word 0x20000c11 800bfa4: 200010ba .word 0x200010ba case CCS_UNPLUGGED: RELAY_Write(RELAY_CP, 1); 800bfa8: 2101 movs r1, #1 800bfaa: 2005 movs r0, #5 800bfac: f7fd fc04 bl 80097b8 CONN_SetState(Unplugged); 800bfb0: 2001 movs r0, #1 800bfb2: f7fd ff6b bl 8009e8c if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || (cp_state_buffer == EV_STATE_C_CONN_ACTIVE)){ 800bfb6: 4b7c ldr r3, [pc, #496] @ (800c1a8 ) 800bfb8: 781b ldrb r3, [r3, #0] 800bfba: 2b01 cmp r3, #1 800bfbc: d003 beq.n 800bfc6 800bfbe: 4b7a ldr r3, [pc, #488] @ (800c1a8 ) 800bfc0: 781b ldrb r3, [r3, #0] 800bfc2: 2b02 cmp r3, #2 800bfc4: d102 bne.n 800bfcc CCS_ConnectorState = CCS_AUTH_REQUIRED; 800bfc6: 4b79 ldr r3, [pc, #484] @ (800c1ac ) 800bfc8: 2203 movs r2, #3 800bfca: 701a strb r2, [r3, #0] } if (CONN.chargingError != CONN_NO_ERROR){ 800bfcc: 4b78 ldr r3, [pc, #480] @ (800c1b0 ) 800bfce: 7f5b ldrb r3, [r3, #29] 800bfd0: 2b00 cmp r3, #0 800bfd2: f000 8094 beq.w 800c0fe log_printf(LOG_ERR, "Charging error %d, state -> disabled\n", CONN.chargingError); 800bfd6: 4b76 ldr r3, [pc, #472] @ (800c1b0 ) 800bfd8: 7f5b ldrb r3, [r3, #29] 800bfda: 461a mov r2, r3 800bfdc: 4975 ldr r1, [pc, #468] @ (800c1b4 ) 800bfde: 2004 movs r0, #4 800bfe0: f7fe fa7e bl 800a4e0 CCS_ConnectorState = CCS_DISABLED; 800bfe4: 4b71 ldr r3, [pc, #452] @ (800c1ac ) 800bfe6: 2201 movs r2, #1 800bfe8: 701a strb r2, [r3, #0] } break; 800bfea: e088 b.n 800c0fe case CCS_AUTH_REQUIRED: RELAY_Write(RELAY_CP, 1); 800bfec: 2101 movs r1, #1 800bfee: 2005 movs r0, #5 800bff0: f7fd fbe2 bl 80097b8 CONN_SetState(AuthRequired); 800bff4: 2004 movs r0, #4 800bff6: f7fd ff49 bl 8009e8c if(CONN.connControl == CMD_START){ 800bffa: 4b6d ldr r3, [pc, #436] @ (800c1b0 ) 800bffc: 781b ldrb r3, [r3, #0] 800bffe: 2b02 cmp r3, #2 800c000: d106 bne.n 800c010 log_printf(LOG_INFO, "Charging permitted, start charging\n"); 800c002: 496d ldr r1, [pc, #436] @ (800c1b8 ) 800c004: 2007 movs r0, #7 800c006: f7fe fa6b bl 800a4e0 CCS_ConnectorState = CCS_CONNECTED; 800c00a: 4b68 ldr r3, [pc, #416] @ (800c1ac ) 800c00c: 2204 movs r2, #4 800c00e: 701a strb r2, [r3, #0] } if (cp_state_buffer == EV_STATE_A_IDLE){ 800c010: 4b65 ldr r3, [pc, #404] @ (800c1a8 ) 800c012: 781b ldrb r3, [r3, #0] 800c014: 2b00 cmp r3, #0 800c016: d174 bne.n 800c102 log_printf(LOG_INFO, "Car unplugged\n"); 800c018: 4968 ldr r1, [pc, #416] @ (800c1bc ) 800c01a: 2007 movs r0, #7 800c01c: f7fe fa60 bl 800a4e0 CCS_ConnectorState = CCS_UNPLUGGED; 800c020: 4b62 ldr r3, [pc, #392] @ (800c1ac ) 800c022: 2202 movs r2, #2 800c024: 701a strb r2, [r3, #0] } break; 800c026: e06c b.n 800c102 case CCS_CONNECTED: RELAY_Write(RELAY_CP, 1); 800c028: 2101 movs r1, #1 800c02a: 2005 movs r0, #5 800c02c: f7fd fbc4 bl 80097b8 if((CCS_EvseState < Preparing) || (CCS_EvseState == AuthRequired)) { 800c030: 4b63 ldr r3, [pc, #396] @ (800c1c0 ) 800c032: 781b ldrb r3, [r3, #0] 800c034: 2b02 cmp r3, #2 800c036: d903 bls.n 800c040 800c038: 4b61 ldr r3, [pc, #388] @ (800c1c0 ) 800c03a: 781b ldrb r3, [r3, #0] 800c03c: 2b04 cmp r3, #4 800c03e: d103 bne.n 800c048 CONN_SetState(Preparing); 800c040: 2003 movs r0, #3 800c042: f7fd ff23 bl 8009e8c 800c046: e004 b.n 800c052 } else { CONN_SetState(CCS_EvseState); 800c048: 4b5d ldr r3, [pc, #372] @ (800c1c0 ) 800c04a: 781b ldrb r3, [r3, #0] 800c04c: 4618 mov r0, r3 800c04e: f7fd ff1d bl 8009e8c } if (cp_state_buffer == EV_STATE_A_IDLE){ 800c052: 4b55 ldr r3, [pc, #340] @ (800c1a8 ) 800c054: 781b ldrb r3, [r3, #0] 800c056: 2b00 cmp r3, #0 800c058: d106 bne.n 800c068 log_printf(LOG_INFO, "Car unplugged\n"); 800c05a: 4958 ldr r1, [pc, #352] @ (800c1bc ) 800c05c: 2007 movs r0, #7 800c05e: f7fe fa3f bl 800a4e0 CCS_ConnectorState = CCS_UNPLUGGED; 800c062: 4b52 ldr r3, [pc, #328] @ (800c1ac ) 800c064: 2202 movs r2, #2 800c066: 701a strb r2, [r3, #0] } if(REPLUG > 0){ 800c068: 4b56 ldr r3, [pc, #344] @ (800c1c4 ) 800c06a: 781b ldrb r3, [r3, #0] 800c06c: 2b00 cmp r3, #0 800c06e: d04a beq.n 800c106 log_printf(LOG_INFO, "Replugging...\n"); 800c070: 4955 ldr r1, [pc, #340] @ (800c1c8 ) 800c072: 2007 movs r0, #7 800c074: f7fe fa34 bl 800a4e0 CCS_ConnectorState = CCS_REPLUGGING; 800c078: 4b4c ldr r3, [pc, #304] @ (800c1ac ) 800c07a: 2205 movs r2, #5 800c07c: 701a strb r2, [r3, #0] } break; 800c07e: e042 b.n 800c106 case CCS_REPLUGGING: RELAY_Write(RELAY_CP, 0); 800c080: 2100 movs r1, #0 800c082: 2005 movs r0, #5 800c084: f7fd fb98 bl 80097b8 CONN_SetState(Replugging); 800c088: 200d movs r0, #13 800c08a: f7fd feff bl 8009e8c if((HAL_GetTick() - replug_tick) > 1000){ 800c08e: f001 ffc1 bl 800e014 800c092: 4602 mov r2, r0 800c094: 4b4d ldr r3, [pc, #308] @ (800c1cc ) 800c096: 681b ldr r3, [r3, #0] 800c098: 1ad3 subs r3, r2, r3 800c09a: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800c09e: d91a bls.n 800c0d6 replug_tick = HAL_GetTick(); 800c0a0: f001 ffb8 bl 800e014 800c0a4: 4603 mov r3, r0 800c0a6: 4a49 ldr r2, [pc, #292] @ (800c1cc ) 800c0a8: 6013 str r3, [r2, #0] if(REPLUG > 0){ 800c0aa: 4b46 ldr r3, [pc, #280] @ (800c1c4 ) 800c0ac: 781b ldrb r3, [r3, #0] 800c0ae: 2b00 cmp r3, #0 800c0b0: d00a beq.n 800c0c8 if (REPLUG != 0xFF) REPLUG--; 800c0b2: 4b44 ldr r3, [pc, #272] @ (800c1c4 ) 800c0b4: 781b ldrb r3, [r3, #0] 800c0b6: 2bff cmp r3, #255 @ 0xff 800c0b8: d00d beq.n 800c0d6 800c0ba: 4b42 ldr r3, [pc, #264] @ (800c1c4 ) 800c0bc: 781b ldrb r3, [r3, #0] 800c0be: 3b01 subs r3, #1 800c0c0: b2da uxtb r2, r3 800c0c2: 4b40 ldr r3, [pc, #256] @ (800c1c4 ) 800c0c4: 701a strb r2, [r3, #0] 800c0c6: e006 b.n 800c0d6 } else { log_printf(LOG_INFO, "Replugging finished, but car unplugged\n"); 800c0c8: 4941 ldr r1, [pc, #260] @ (800c1d0 ) 800c0ca: 2007 movs r0, #7 800c0cc: f7fe fa08 bl 800a4e0 CCS_ConnectorState = CCS_UNPLUGGED; 800c0d0: 4b36 ldr r3, [pc, #216] @ (800c1ac ) 800c0d2: 2202 movs r2, #2 800c0d4: 701a strb r2, [r3, #0] } } if(REPLUG == 0){ 800c0d6: 4b3b ldr r3, [pc, #236] @ (800c1c4 ) 800c0d8: 781b ldrb r3, [r3, #0] 800c0da: 2b00 cmp r3, #0 800c0dc: d115 bne.n 800c10a if(cp_state_buffer == EV_STATE_B_CONN_PREP){ 800c0de: 4b32 ldr r3, [pc, #200] @ (800c1a8 ) 800c0e0: 781b ldrb r3, [r3, #0] 800c0e2: 2b01 cmp r3, #1 800c0e4: d111 bne.n 800c10a log_printf(LOG_INFO, "Replugging finished, car plugged, state -> auth required\n"); 800c0e6: 493b ldr r1, [pc, #236] @ (800c1d4 ) 800c0e8: 2007 movs r0, #7 800c0ea: f7fe f9f9 bl 800a4e0 CCS_ConnectorState = CCS_AUTH_REQUIRED; 800c0ee: 4b2f ldr r3, [pc, #188] @ (800c1ac ) 800c0f0: 2203 movs r2, #3 800c0f2: 701a strb r2, [r3, #0] } } break; 800c0f4: e009 b.n 800c10a break; 800c0f6: bf00 nop 800c0f8: e008 b.n 800c10c break; 800c0fa: bf00 nop 800c0fc: e006 b.n 800c10c break; 800c0fe: bf00 nop 800c100: e004 b.n 800c10c break; 800c102: bf00 nop 800c104: e002 b.n 800c10c break; 800c106: bf00 nop 800c108: e000 b.n 800c10c break; 800c10a: bf00 nop } // 10s timeout: enforce safe-state until host communication recovers. if (host_timeout_stop) { 800c10c: 78bb ldrb r3, [r7, #2] 800c10e: 2b00 cmp r3, #0 800c110: d014 beq.n 800c13c CONN.EnableOutput = 0; 800c112: 4b27 ldr r3, [pc, #156] @ (800c1b0 ) 800c114: 2200 movs r2, #0 800c116: 75da strb r2, [r3, #23] CCS_EvseState = Unknown; 800c118: 4b29 ldr r3, [pc, #164] @ (800c1c0 ) 800c11a: 2200 movs r2, #0 800c11c: 701a strb r2, [r3, #0] CP_SetDuty(100); 800c11e: 2064 movs r0, #100 @ 0x64 800c120: f7fd ffac bl 800a07c if (CCS_ConnectorState != CCS_DISABLED && CCS_ConnectorState != CCS_UNKNOWN) { 800c124: 4b21 ldr r3, [pc, #132] @ (800c1ac ) 800c126: 781b ldrb r3, [r3, #0] 800c128: 2b01 cmp r3, #1 800c12a: d024 beq.n 800c176 800c12c: 4b1f ldr r3, [pc, #124] @ (800c1ac ) 800c12e: 781b ldrb r3, [r3, #0] 800c130: 2b00 cmp r3, #0 800c132: d020 beq.n 800c176 CCS_ConnectorState = CCS_DISABLED; 800c134: 4b1d ldr r3, [pc, #116] @ (800c1ac ) 800c136: 2201 movs r2, #1 800c138: 701a strb r2, [r3, #0] 800c13a: e01c b.n 800c176 } } else { if (last_cmd == CMD_STOP) { 800c13c: 4b26 ldr r3, [pc, #152] @ (800c1d8 ) 800c13e: 781b ldrb r3, [r3, #0] 800c140: 2b01 cmp r3, #1 800c142: d103 bne.n 800c14c CONN.EnableOutput = 0; 800c144: 4b1a ldr r3, [pc, #104] @ (800c1b0 ) 800c146: 2200 movs r2, #0 800c148: 75da strb r2, [r3, #23] 800c14a: e014 b.n 800c176 } else { CONN.EnableOutput = ev_enable_output ? 1 : 0; 800c14c: 4b23 ldr r3, [pc, #140] @ (800c1dc ) 800c14e: 781b ldrb r3, [r3, #0] 800c150: 2b00 cmp r3, #0 800c152: bf14 ite ne 800c154: 2301 movne r3, #1 800c156: 2300 moveq r3, #0 800c158: b2db uxtb r3, r3 800c15a: 461a mov r2, r3 800c15c: 4b14 ldr r3, [pc, #80] @ (800c1b0 ) 800c15e: 75da strb r2, [r3, #23] if((CONN.EnableOutput == 0) && (CONN.connState == Preparing)){ 800c160: 4b13 ldr r3, [pc, #76] @ (800c1b0 ) 800c162: 7ddb ldrb r3, [r3, #23] 800c164: 2b00 cmp r3, #0 800c166: d106 bne.n 800c176 800c168: 4b11 ldr r3, [pc, #68] @ (800c1b0 ) 800c16a: 785b ldrb r3, [r3, #1] 800c16c: 2b03 cmp r3, #3 800c16e: d102 bne.n 800c176 CONN.EnableOutput = 0; 800c170: 4b0f ldr r3, [pc, #60] @ (800c1b0 ) 800c172: 2200 movs r2, #0 800c174: 75da strb r2, [r3, #23] } } } if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800c176: 4b0c ldr r3, [pc, #48] @ (800c1a8 ) 800c178: 781b ldrb r3, [r3, #0] 800c17a: 2b01 cmp r3, #1 800c17c: d007 beq.n 800c18e (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800c17e: 4b0a ldr r3, [pc, #40] @ (800c1a8 ) 800c180: 781b ldrb r3, [r3, #0] if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800c182: 2b02 cmp r3, #2 800c184: d003 beq.n 800c18e (cp_state_buffer == EV_STATE_D_CONN_ACT_VENT)) { 800c186: 4b08 ldr r3, [pc, #32] @ (800c1a8 ) 800c188: 781b ldrb r3, [r3, #0] (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800c18a: 2b03 cmp r3, #3 800c18c: d103 bne.n 800c196 CONN.EvConnected = 1; 800c18e: 4b08 ldr r3, [pc, #32] @ (800c1b0 ) 800c190: 2201 movs r2, #1 800c192: 779a strb r2, [r3, #30] 800c194: e003 b.n 800c19e } else { CONN.EvConnected = 0; 800c196: 4b06 ldr r3, [pc, #24] @ (800c1b0 ) 800c198: 2200 movs r2, #0 800c19a: 779a strb r2, [r3, #30] } } 800c19c: bf00 nop 800c19e: bf00 nop 800c1a0: 3708 adds r7, #8 800c1a2: 46bd mov sp, r7 800c1a4: bd80 pop {r7, pc} 800c1a6: bf00 nop 800c1a8: 20000005 .word 0x20000005 800c1ac: 20000c11 .word 0x20000c11 800c1b0: 200003b0 .word 0x200003b0 800c1b4: 08016e6c .word 0x08016e6c 800c1b8: 08016e94 .word 0x08016e94 800c1bc: 08016eb8 .word 0x08016eb8 800c1c0: 20000c10 .word 0x20000c10 800c1c4: 20000bb1 .word 0x20000bb1 800c1c8: 08016ec8 .word 0x08016ec8 800c1cc: 20000c20 .word 0x20000c20 800c1d0: 08016ed8 .word 0x08016ed8 800c1d4: 08016f00 .word 0x08016f00 800c1d8: 200009ac .word 0x200009ac 800c1dc: 200009ad .word 0x200009ad 0800c1e0 : void CCS_Init(void){ 800c1e0: b580 push {r7, lr} 800c1e2: af00 add r7, sp, #0 CP_Init(); 800c1e4: f7fd ff28 bl 800a038 CP_SetDuty(100); 800c1e8: 2064 movs r0, #100 @ 0x64 800c1ea: f7fd ff47 bl 800a07c CCS_MaxLoad.maxVoltage = PSU_MAX_VOLTAGE; // 1000V 800c1ee: 4b11 ldr r3, [pc, #68] @ (800c234 ) 800c1f0: f44f 727a mov.w r2, #1000 @ 0x3e8 800c1f4: 801a strh r2, [r3, #0] CCS_MaxLoad.minVoltage = PSU_MIN_VOLTAGE; //150V 800c1f6: 4b0f ldr r3, [pc, #60] @ (800c234 ) 800c1f8: 2296 movs r2, #150 @ 0x96 800c1fa: 805a strh r2, [r3, #2] CCS_MaxLoad.maxCurrent = PSU_MAX_CURRENT*10; //100A 800c1fc: 4b0d ldr r3, [pc, #52] @ (800c234 ) 800c1fe: f240 5232 movw r2, #1330 @ 0x532 800c202: 809a strh r2, [r3, #4] CCS_MaxLoad.minCurrent = PSU_MIN_CURRENT*10; //1A 800c204: 4b0b ldr r3, [pc, #44] @ (800c234 ) 800c206: 220a movs r2, #10 800c208: 80da strh r2, [r3, #6] CCS_MaxLoad.maxPower = PSU_MAX_POWER; //30000W 800c20a: 4b0a ldr r3, [pc, #40] @ (800c234 ) 800c20c: f247 5230 movw r2, #30000 @ 0x7530 800c210: 609a str r2, [r3, #8] uart3_last_packet_tick = HAL_GetTick(); 800c212: f001 feff bl 800e014 800c216: 4603 mov r3, r0 800c218: 4a07 ldr r2, [pc, #28] @ (800c238 ) 800c21a: 6013 str r3, [r2, #0] uart3_last_reinit_tick = uart3_last_packet_tick; 800c21c: 4b06 ldr r3, [pc, #24] @ (800c238 ) 800c21e: 681b ldr r3, [r3, #0] 800c220: 4a06 ldr r2, [pc, #24] @ (800c23c ) 800c222: 6013 str r3, [r2, #0] CCS_SendResetReason(); 800c224: f000 f8be bl 800c3a4 log_printf(LOG_INFO, "CCS init\n"); 800c228: 4905 ldr r1, [pc, #20] @ (800c240 ) 800c22a: 2007 movs r0, #7 800c22c: f7fe f958 bl 800a4e0 } 800c230: bf00 nop 800c232: bd80 pop {r7, pc} 800c234: 2000098c .word 0x2000098c 800c238: 20000bbc .word 0x20000bbc 800c23c: 20000bc0 .word 0x20000bc0 800c240: 08016f3c .word 0x08016f3c 0800c244 : ISR_FAST static uint16_t crc16_ibm(const uint8_t* data, uint16_t length) { uint16_t crc = 0xFFFFu; for (uint16_t i = 0; i < length; i++) { 800c244: b3e9 cbz r1, 800c2c2 800c246: 4684 mov ip, r0 ISR_FAST static uint16_t crc16_ibm(const uint8_t* data, uint16_t length) { 800c248: b500 push {lr} 800c24a: 468e mov lr, r1 uint16_t crc = 0xFFFFu; 800c24c: f64f 70ff movw r0, #65535 @ 0xffff crc ^= data[i]; for (uint8_t j = 0; j < 8; j++) { if (crc & 1u) { 800c250: 491d ldr r1, [pc, #116] @ (800c2c8 ) 800c252: 44e6 add lr, ip crc ^= data[i]; 800c254: f81c 2b01 ldrb.w r2, [ip], #1 800c258: 4042 eors r2, r0 if (crc & 1u) { 800c25a: f342 0300 sbfx r3, r2, #0, #1 800c25e: 400b ands r3, r1 800c260: ea83 0352 eor.w r3, r3, r2, lsr #1 800c264: f343 0200 sbfx r2, r3, #0, #1 800c268: 400a ands r2, r1 crc = (crc >> 1) ^ 0xA001u; } else { crc >>= 1; 800c26a: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c26e: 405a eors r2, r3 800c270: f342 0300 sbfx r3, r2, #0, #1 800c274: 400b ands r3, r1 crc >>= 1; 800c276: f3c2 024e ubfx r2, r2, #1, #15 if (crc & 1u) { 800c27a: 4053 eors r3, r2 800c27c: f343 0200 sbfx r2, r3, #0, #1 800c280: 400a ands r2, r1 crc >>= 1; 800c282: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c286: 405a eors r2, r3 800c288: f342 0300 sbfx r3, r2, #0, #1 800c28c: 400b ands r3, r1 crc >>= 1; 800c28e: f3c2 024e ubfx r2, r2, #1, #15 if (crc & 1u) { 800c292: 4053 eors r3, r2 800c294: f343 0200 sbfx r2, r3, #0, #1 800c298: 400a ands r2, r1 crc >>= 1; 800c29a: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c29e: 405a eors r2, r3 800c2a0: f342 0300 sbfx r3, r2, #0, #1 800c2a4: 400b ands r3, r1 crc >>= 1; 800c2a6: f3c2 024e ubfx r2, r2, #1, #15 if (crc & 1u) { 800c2aa: 4053 eors r3, r2 800c2ac: f343 0000 sbfx r0, r3, #0, #1 800c2b0: 4008 ands r0, r1 crc >>= 1; 800c2b2: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c2b6: 4058 eors r0, r3 for (uint16_t i = 0; i < length; i++) { 800c2b8: 45e6 cmp lr, ip if (crc & 1u) { 800c2ba: b280 uxth r0, r0 for (uint16_t i = 0; i < length; i++) { 800c2bc: d1ca bne.n 800c254 } } } return crc; } 800c2be: f85d fb04 ldr.w pc, [sp], #4 uint16_t crc = 0xFFFFu; 800c2c2: f64f 70ff movw r0, #65535 @ 0xffff } 800c2c6: 4770 bx lr 800c2c8: ffffa001 .word 0xffffa001 0800c2cc : static uint16_t CCS_BuildPacket(uint8_t cmd, const void* payload, uint16_t payload_len, uint8_t* out, uint16_t out_max) { 800c2cc: b580 push {r7, lr} 800c2ce: b086 sub sp, #24 800c2d0: af00 add r7, sp, #0 800c2d2: 60b9 str r1, [r7, #8] 800c2d4: 607b str r3, [r7, #4] 800c2d6: 4603 mov r3, r0 800c2d8: 73fb strb r3, [r7, #15] 800c2da: 4613 mov r3, r2 800c2dc: 81bb strh r3, [r7, #12] uint16_t total_len = (uint16_t)(1u + payload_len + 2u); 800c2de: 89bb ldrh r3, [r7, #12] 800c2e0: 3303 adds r3, #3 800c2e2: 82fb strh r3, [r7, #22] if (total_len > out_max) return 0; 800c2e4: 8afa ldrh r2, [r7, #22] 800c2e6: 8c3b ldrh r3, [r7, #32] 800c2e8: 429a cmp r2, r3 800c2ea: d901 bls.n 800c2f0 800c2ec: 2300 movs r3, #0 800c2ee: e029 b.n 800c344 out[0] = cmd; 800c2f0: 687b ldr r3, [r7, #4] 800c2f2: 7bfa ldrb r2, [r7, #15] 800c2f4: 701a strb r2, [r3, #0] if (payload_len && payload != NULL) { 800c2f6: 89bb ldrh r3, [r7, #12] 800c2f8: 2b00 cmp r3, #0 800c2fa: d009 beq.n 800c310 800c2fc: 68bb ldr r3, [r7, #8] 800c2fe: 2b00 cmp r3, #0 800c300: d006 beq.n 800c310 memcpy(&out[1], payload, payload_len); 800c302: 687b ldr r3, [r7, #4] 800c304: 3301 adds r3, #1 800c306: 89ba ldrh r2, [r7, #12] 800c308: 68b9 ldr r1, [r7, #8] 800c30a: 4618 mov r0, r3 800c30c: f008 fa5e bl 80147cc } uint16_t crc = crc16_ibm(out, (uint16_t)(1u + payload_len)); 800c310: 89bb ldrh r3, [r7, #12] 800c312: 3301 adds r3, #1 800c314: b29b uxth r3, r3 800c316: 4619 mov r1, r3 800c318: 6878 ldr r0, [r7, #4] 800c31a: f7ff ff93 bl 800c244 800c31e: 4603 mov r3, r0 800c320: 82bb strh r3, [r7, #20] out[1u + payload_len] = (uint8_t)(crc & 0xFFu); 800c322: 89bb ldrh r3, [r7, #12] 800c324: 3301 adds r3, #1 800c326: 687a ldr r2, [r7, #4] 800c328: 4413 add r3, r2 800c32a: 8aba ldrh r2, [r7, #20] 800c32c: b2d2 uxtb r2, r2 800c32e: 701a strb r2, [r3, #0] out[1u + payload_len + 1u] = (uint8_t)((crc >> 8) & 0xFFu); 800c330: 8abb ldrh r3, [r7, #20] 800c332: 0a1b lsrs r3, r3, #8 800c334: b299 uxth r1, r3 800c336: 89bb ldrh r3, [r7, #12] 800c338: 3302 adds r3, #2 800c33a: 687a ldr r2, [r7, #4] 800c33c: 4413 add r3, r2 800c33e: b2ca uxtb r2, r1 800c340: 701a strb r2, [r3, #0] return total_len; 800c342: 8afb ldrh r3, [r7, #22] } 800c344: 4618 mov r0, r3 800c346: 3718 adds r7, #24 800c348: 46bd mov sp, r7 800c34a: bd80 pop {r7, pc} 0800c34c : static void CCS_SendPacket(uint8_t cmd, const void* payload, uint16_t payload_len) { 800c34c: b580 push {r7, lr} 800c34e: b086 sub sp, #24 800c350: af02 add r7, sp, #8 800c352: 4603 mov r3, r0 800c354: 6039 str r1, [r7, #0] 800c356: 71fb strb r3, [r7, #7] 800c358: 4613 mov r3, r2 800c35a: 80bb strh r3, [r7, #4] uint16_t len = CCS_BuildPacket(cmd, payload, payload_len, tx_buffer, sizeof(tx_buffer)); 800c35c: 88ba ldrh r2, [r7, #4] 800c35e: 79f8 ldrb r0, [r7, #7] 800c360: f44f 7380 mov.w r3, #256 @ 0x100 800c364: 9300 str r3, [sp, #0] 800c366: 4b0c ldr r3, [pc, #48] @ (800c398 ) 800c368: 6839 ldr r1, [r7, #0] 800c36a: f7ff ffaf bl 800c2cc 800c36e: 4603 mov r3, r0 800c370: 81fb strh r3, [r7, #14] if (len > 0) { 800c372: 89fb ldrh r3, [r7, #14] 800c374: 2b00 cmp r3, #0 800c376: d005 beq.n 800c384 HAL_UART_Transmit_IT(&huart3, tx_buffer, len); 800c378: 89fb ldrh r3, [r7, #14] 800c37a: 461a mov r2, r3 800c37c: 4906 ldr r1, [pc, #24] @ (800c398 ) 800c37e: 4807 ldr r0, [pc, #28] @ (800c39c ) 800c380: f006 fd5a bl 8012e38 } last_cmd_sent = HAL_GetTick(); 800c384: f001 fe46 bl 800e014 800c388: 4603 mov r3, r0 800c38a: 4a05 ldr r2, [pc, #20] @ (800c3a0 ) 800c38c: 6013 str r3, [r2, #0] } 800c38e: bf00 nop 800c390: 3710 adds r7, #16 800c392: 46bd mov sp, r7 800c394: bd80 pop {r7, pc} 800c396: bf00 nop 800c398: 20000ab0 .word 0x20000ab0 800c39c: 20001228 .word 0x20001228 800c3a0: 200009a4 .word 0x200009a4 0800c3a4 : static void CCS_SendResetReason(void) { 800c3a4: b580 push {r7, lr} 800c3a6: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_RESET, NULL, 0); 800c3a8: 2200 movs r2, #0 800c3aa: 2100 movs r1, #0 800c3ac: 2052 movs r0, #82 @ 0x52 800c3ae: f7ff ffcd bl 800c34c } 800c3b2: bf00 nop 800c3b4: bd80 pop {r7, pc} 800c3b6: bf00 nop 0800c3b8 : void CCS_SendEmergencyStop(void) { 800c3b8: b580 push {r7, lr} 800c3ba: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_ESTOP, NULL, 0); 800c3bc: 2200 movs r2, #0 800c3be: 2100 movs r1, #0 800c3c0: 2053 movs r0, #83 @ 0x53 800c3c2: f7ff ffc3 bl 800c34c } 800c3c6: bf00 nop 800c3c8: bd80 pop {r7, pc} 800c3ca: bf00 nop 0800c3cc : void CCS_SendStart(void) { CCS_SendPacket(CMD_M2E_START, NULL, 0); } static void CCS_CalculateEnergy(void) { 800c3cc: b580 push {r7, lr} 800c3ce: b082 sub sp, #8 800c3d0: af00 add r7, sp, #0 static uint32_t lastTick = 0; uint32_t currentTick = HAL_GetTick(); 800c3d2: f001 fe1f bl 800e014 800c3d6: 6078 str r0, [r7, #4] uint32_t elapsedTimeMs = currentTick - lastTick; 800c3d8: 4b1e ldr r3, [pc, #120] @ (800c454 ) 800c3da: 681b ldr r3, [r3, #0] 800c3dc: 687a ldr r2, [r7, #4] 800c3de: 1ad3 subs r3, r2, r3 800c3e0: 603b str r3, [r7, #0] lastTick = currentTick; 800c3e2: 4a1c ldr r2, [pc, #112] @ (800c454 ) 800c3e4: 687b ldr r3, [r7, #4] 800c3e6: 6013 str r3, [r2, #0] CCS_Power = CONN.MeasuredVoltage * CONN.MeasuredCurrent / 10; 800c3e8: 4b1b ldr r3, [pc, #108] @ (800c458 ) 800c3ea: f8b3 3013 ldrh.w r3, [r3, #19] 800c3ee: b29b uxth r3, r3 800c3f0: 461a mov r2, r3 800c3f2: 4b19 ldr r3, [pc, #100] @ (800c458 ) 800c3f4: f8b3 3015 ldrh.w r3, [r3, #21] 800c3f8: b29b uxth r3, r3 800c3fa: fb02 f303 mul.w r3, r2, r3 800c3fe: 4a17 ldr r2, [pc, #92] @ (800c45c ) 800c400: fb82 1203 smull r1, r2, r2, r3 800c404: 1092 asrs r2, r2, #2 800c406: 17db asrs r3, r3, #31 800c408: 1ad3 subs r3, r2, r3 800c40a: 461a mov r2, r3 800c40c: 4b14 ldr r3, [pc, #80] @ (800c460 ) 800c40e: 601a str r2, [r3, #0] CCS_EnergyWs += (CCS_Power * elapsedTimeMs) / 1000; 800c410: 4b13 ldr r3, [pc, #76] @ (800c460 ) 800c412: 681b ldr r3, [r3, #0] 800c414: 683a ldr r2, [r7, #0] 800c416: fb02 f303 mul.w r3, r2, r3 800c41a: 4a12 ldr r2, [pc, #72] @ (800c464 ) 800c41c: fba2 2303 umull r2, r3, r2, r3 800c420: 099a lsrs r2, r3, #6 800c422: 4b11 ldr r3, [pc, #68] @ (800c468 ) 800c424: 681b ldr r3, [r3, #0] 800c426: 4413 add r3, r2 800c428: 4a0f ldr r2, [pc, #60] @ (800c468 ) 800c42a: 6013 str r3, [r2, #0] if(CCS_EvseState == Unplugged) { 800c42c: 4b0f ldr r3, [pc, #60] @ (800c46c ) 800c42e: 781b ldrb r3, [r3, #0] 800c430: 2b01 cmp r3, #1 800c432: d102 bne.n 800c43a CCS_EnergyWs = 0; 800c434: 4b0c ldr r3, [pc, #48] @ (800c468 ) 800c436: 2200 movs r2, #0 800c438: 601a str r2, [r3, #0] } CCS_Energy = CCS_EnergyWs / 3600; 800c43a: 4b0b ldr r3, [pc, #44] @ (800c468 ) 800c43c: 681b ldr r3, [r3, #0] 800c43e: 4a0c ldr r2, [pc, #48] @ (800c470 ) 800c440: fba2 2303 umull r2, r3, r2, r3 800c444: 0adb lsrs r3, r3, #11 800c446: 4a0b ldr r2, [pc, #44] @ (800c474 ) 800c448: 6013 str r3, [r2, #0] } 800c44a: bf00 nop 800c44c: 3708 adds r7, #8 800c44e: 46bd mov sp, r7 800c450: bd80 pop {r7, pc} 800c452: bf00 nop 800c454: 20000c24 .word 0x20000c24 800c458: 200003b0 .word 0x200003b0 800c45c: 66666667 .word 0x66666667 800c460: 20000998 .word 0x20000998 800c464: 10624dd3 .word 0x10624dd3 800c468: 2000099c .word 0x2000099c 800c46c: 20000c10 .word 0x20000c10 800c470: 91a2b3c5 .word 0x91a2b3c5 800c474: 200009a0 .word 0x200009a0 0800c478 : static void send_state(void) { 800c478: b580 push {r7, lr} 800c47a: af00 add r7, sp, #0 CCS_CalculateEnergy(); 800c47c: f7ff ffa6 bl 800c3cc CCS_State.DutyCycle = CP_GetDuty(); 800c480: f7fd fe24 bl 800a0cc 800c484: 4603 mov r3, r0 800c486: 461a mov r2, r3 800c488: 4b2e ldr r3, [pc, #184] @ (800c544 ) 800c48a: 701a strb r2, [r3, #0] CCS_State.OutputEnabled = PSU0.CONT_enabled; 800c48c: 4b2e ldr r3, [pc, #184] @ (800c548 ) 800c48e: 7ada ldrb r2, [r3, #11] 800c490: 4b2c ldr r3, [pc, #176] @ (800c544 ) 800c492: 705a strb r2, [r3, #1] CCS_State.MeasuredVoltage = (uint16_t)CONN.MeasuredVoltage; 800c494: 4b2d ldr r3, [pc, #180] @ (800c54c ) 800c496: f8b3 3013 ldrh.w r3, [r3, #19] 800c49a: b29a uxth r2, r3 800c49c: 4b29 ldr r3, [pc, #164] @ (800c544 ) 800c49e: 805a strh r2, [r3, #2] if (fake_500_voltage_mode) { 800c4a0: 4b2b ldr r3, [pc, #172] @ (800c550 ) 800c4a2: 781b ldrb r3, [r3, #0] 800c4a4: 2b00 cmp r3, #0 800c4a6: d003 beq.n 800c4b0 CCS_State.MeasuredVoltage = FAKE_EVREQ_VOLTAGE_V; 800c4a8: 4b26 ldr r3, [pc, #152] @ (800c544 ) 800c4aa: f44f 72fa mov.w r2, #500 @ 0x1f4 800c4ae: 805a strh r2, [r3, #2] } CCS_State.MeasuredCurrent = (uint16_t)CONN.MeasuredCurrent; 800c4b0: 4b26 ldr r3, [pc, #152] @ (800c54c ) 800c4b2: f8b3 3015 ldrh.w r3, [r3, #21] 800c4b6: b29a uxth r2, r3 800c4b8: 4b22 ldr r3, [pc, #136] @ (800c544 ) 800c4ba: 809a strh r2, [r3, #4] CCS_State.Power = CCS_Power; 800c4bc: 4b25 ldr r3, [pc, #148] @ (800c554 ) 800c4be: 681b ldr r3, [r3, #0] 800c4c0: 4a20 ldr r2, [pc, #128] @ (800c544 ) 800c4c2: f8c2 3006 str.w r3, [r2, #6] CCS_State.Energy = CCS_Energy; 800c4c6: 4b24 ldr r3, [pc, #144] @ (800c558 ) 800c4c8: 681b ldr r3, [r3, #0] 800c4ca: 4a1e ldr r2, [pc, #120] @ (800c544 ) 800c4cc: f8c2 300a str.w r3, [r2, #10] if(CCS_ConnectorState == CCS_CONNECTED){ 800c4d0: 4b22 ldr r3, [pc, #136] @ (800c55c ) 800c4d2: 781b ldrb r3, [r3, #0] 800c4d4: 2b04 cmp r3, #4 800c4d6: d104 bne.n 800c4e2 CCS_State.CpState = cp_state_buffer; 800c4d8: 4b21 ldr r3, [pc, #132] @ (800c560 ) 800c4da: 781a ldrb r2, [r3, #0] 800c4dc: 4b19 ldr r3, [pc, #100] @ (800c544 ) 800c4de: 74da strb r2, [r3, #19] 800c4e0: e002 b.n 800c4e8 } else { CCS_State.CpState = EV_STATE_A_IDLE; 800c4e2: 4b18 ldr r3, [pc, #96] @ (800c544 ) 800c4e4: 2200 movs r2, #0 800c4e6: 74da strb r2, [r3, #19] } CCS_State.MaxVoltage = CCS_MaxLoad.maxVoltage; 800c4e8: 4b1e ldr r3, [pc, #120] @ (800c564 ) 800c4ea: 881a ldrh r2, [r3, #0] 800c4ec: 4b15 ldr r3, [pc, #84] @ (800c544 ) 800c4ee: 829a strh r2, [r3, #20] CCS_State.MinVoltage = CCS_MaxLoad.minVoltage; 800c4f0: 4b1c ldr r3, [pc, #112] @ (800c564 ) 800c4f2: 885a ldrh r2, [r3, #2] 800c4f4: 4b13 ldr r3, [pc, #76] @ (800c544 ) 800c4f6: 82da strh r2, [r3, #22] CCS_State.MaxCurrent = CCS_MaxLoad.maxCurrent; 800c4f8: 4b1a ldr r3, [pc, #104] @ (800c564 ) 800c4fa: 889a ldrh r2, [r3, #4] 800c4fc: 4b11 ldr r3, [pc, #68] @ (800c544 ) 800c4fe: 831a strh r2, [r3, #24] CCS_State.MinCurrent = CCS_MaxLoad.minCurrent; 800c500: 4b18 ldr r3, [pc, #96] @ (800c564 ) 800c502: 88da ldrh r2, [r3, #6] 800c504: 4b0f ldr r3, [pc, #60] @ (800c544 ) 800c506: 835a strh r2, [r3, #26] CCS_State.MaxPower = CCS_MaxLoad.maxPower; 800c508: 4b16 ldr r3, [pc, #88] @ (800c564 ) 800c50a: 689b ldr r3, [r3, #8] 800c50c: 4a0d ldr r2, [pc, #52] @ (800c544 ) 800c50e: 61d3 str r3, [r2, #28] CCS_State.IsolationValid = isolation_enable; 800c510: 4b15 ldr r3, [pc, #84] @ (800c568 ) 800c512: 781a ldrb r2, [r3, #0] 800c514: 4b0b ldr r3, [pc, #44] @ (800c544 ) 800c516: 749a strb r2, [r3, #18] CCS_State.IsolationResistance = 900000; 800c518: 4a0a ldr r2, [pc, #40] @ (800c544 ) 800c51a: 2300 movs r3, #0 800c51c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800c520: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800c524: f443 433b orr.w r3, r3, #47872 @ 0xbb00 800c528: f043 03a0 orr.w r3, r3, #160 @ 0xa0 800c52c: 81d3 strh r3, [r2, #14] 800c52e: 2300 movs r3, #0 800c530: f043 030d orr.w r3, r3, #13 800c534: 8213 strh r3, [r2, #16] CCS_SendPacket(CMD_M2E_STATE, &CCS_State, sizeof(CCS_State)); 800c536: 2220 movs r2, #32 800c538: 4902 ldr r1, [pc, #8] @ (800c544 ) 800c53a: 2050 movs r0, #80 @ 0x50 800c53c: f7ff ff06 bl 800c34c } 800c540: bf00 nop 800c542: bd80 pop {r7, pc} 800c544: 20000bc4 .word 0x20000bc4 800c548: 20000904 .word 0x20000904 800c54c: 200003b0 .word 0x200003b0 800c550: 20000bb8 .word 0x20000bb8 800c554: 20000998 .word 0x20000998 800c558: 200009a0 .word 0x200009a0 800c55c: 20000c11 .word 0x20000c11 800c560: 20000005 .word 0x20000005 800c564: 2000098c .word 0x2000098c 800c568: 20000bb3 .word 0x20000bb3 0800c56c : ISR_FAST static uint16_t expected_payload_len(uint8_t cmd) { switch (cmd) { 800c56c: 3840 subs r0, #64 @ 0x40 800c56e: b2c0 uxtb r0, r0 800c570: 2809 cmp r0, #9 800c572: bf9a itte ls 800c574: 4b02 ldrls r3, [pc, #8] @ (800c580 ) 800c576: f833 0010 ldrhls.w r0, [r3, r0, lsl #1] ISR_FAST static uint16_t expected_payload_len(uint8_t cmd) { 800c57a: f64f 70ff movwhi r0, #65535 @ 0xffff case CMD_E2M_EV_INFO: return sizeof(CCS_EvInfo_t); case CMD_E2M_EVSE_STATE: return sizeof(CONN_State_t); case CMD_E2M_KEEP_ALIVE: return 0; default: return 0xFFFFu; } } 800c57e: 4770 bx lr 800c580: 08017210 .word 0x08017210 0800c584 : ISR_FAST static void apply_command(uint8_t cmd, const uint8_t* payload, uint16_t payload_len) { 800c584: b5f8 push {r3, r4, r5, r6, r7, lr} 800c586: 4604 mov r4, r0 800c588: 460d mov r5, r1 (void)payload_len; last_host_seen = HAL_GetTick(); 800c58a: f001 fd43 bl 800e014 everest_timed_out = 0; 800c58e: 2300 movs r3, #0 800c590: 4a42 ldr r2, [pc, #264] @ (800c69c ) last_host_seen = HAL_GetTick(); 800c592: 4e43 ldr r6, [pc, #268] @ (800c6a0 ) everest_timed_out = 0; 800c594: 7013 strb r3, [r2, #0] everest_timeout_warn_latched = 0; 800c596: 4a43 ldr r2, [pc, #268] @ (800c6a4 ) last_host_seen = HAL_GetTick(); 800c598: 6030 str r0, [r6, #0] everest_timeout_warn_latched = 0; 800c59a: 7013 strb r3, [r2, #0] everest_timeout_stop_latched = 0; 800c59c: 4a42 ldr r2, [pc, #264] @ (800c6a8 ) 800c59e: 7013 strb r3, [r2, #0] switch (cmd) { 800c5a0: f1a4 0340 sub.w r3, r4, #64 @ 0x40 800c5a4: 2b09 cmp r3, #9 800c5a6: d871 bhi.n 800c68c 800c5a8: e8df f003 tbb [pc, r3] 800c5ac: 4e5b1409 .word 0x4e5b1409 800c5b0: 2e2a1b55 .word 0x2e2a1b55 800c5b4: 054a .short 0x054a (void)payload; CP_SetDuty(pwm_duty_percent); break; } case CMD_E2M_KEEP_ALIVE: { last_host_seen = HAL_GetTick(); 800c5b6: f001 fd2d bl 800e014 800c5ba: 6030 str r0, [r6, #0] log_printf(LOG_WARN, "UART3 RX warn: cmd 0x%02x CRC/len OK but no switch case (expected_payload vs apply_command)\n", cmd); break; } } 800c5bc: bdf8 pop {r3, r4, r5, r6, r7, pc} if (duty > 100) duty = 100; 800c5be: 7828 ldrb r0, [r5, #0] if (CONN.connControl != CMD_FORCE_UNLOCK) { 800c5c0: 4b3a ldr r3, [pc, #232] @ (800c6ac ) if (duty > 100) duty = 100; 800c5c2: 2864 cmp r0, #100 @ 0x64 800c5c4: bf28 it cs 800c5c6: 2064 movcs r0, #100 @ 0x64 if (CONN.connControl != CMD_FORCE_UNLOCK) { 800c5c8: 781b ldrb r3, [r3, #0] pwm_duty_percent = duty; 800c5ca: 4a39 ldr r2, [pc, #228] @ (800c6b0 ) if (CONN.connControl != CMD_FORCE_UNLOCK) { 800c5cc: 2b03 cmp r3, #3 pwm_duty_percent = duty; 800c5ce: 7010 strb r0, [r2, #0] if (CONN.connControl != CMD_FORCE_UNLOCK) { 800c5d0: d143 bne.n 800c65a } 800c5d2: bdf8 pop {r3, r4, r5, r6, r7, pc} ev_enable_output = (p->enable_output != 0); 800c5d4: 782b ldrb r3, [r5, #0] 800c5d6: 4a37 ldr r2, [pc, #220] @ (800c6b4 ) 800c5d8: 3b00 subs r3, #0 800c5da: bf18 it ne 800c5dc: 2301 movne r3, #1 800c5de: 7013 strb r3, [r2, #0] } 800c5e0: bdf8 pop {r3, r4, r5, r6, r7, pc} if (p->voltage_V == FAKE_EVREQ_VOLTAGE_V) { 800c5e2: 882b ldrh r3, [r5, #0] 800c5e4: b29a uxth r2, r3 800c5e6: f5b2 7ffa cmp.w r2, #500 @ 0x1f4 800c5ea: d043 beq.n 800c674 fake_500_voltage_mode = 0u; 800c5ec: 2000 movs r0, #0 CONN.RequestedVoltage = p->voltage_V; 800c5ee: 4a2f ldr r2, [pc, #188] @ (800c6ac ) fake_500_voltage_mode = 0u; 800c5f0: 4931 ldr r1, [pc, #196] @ (800c6b8 ) CONN.RequestedVoltage = p->voltage_V; 800c5f2: f8a2 300f strh.w r3, [r2, #15] fake_500_voltage_mode = 0u; 800c5f6: 7008 strb r0, [r1, #0] CONN.WantedCurrent = p->current_0p1A; 800c5f8: 886b ldrh r3, [r5, #2] 800c5fa: f8a2 301b strh.w r3, [r2, #27] } 800c5fe: bdf8 pop {r3, r4, r5, r6, r7, pc} isolation_enable = p->command; 800c600: 782a ldrb r2, [r5, #0] 800c602: 4b2e ldr r3, [pc, #184] @ (800c6bc ) 800c604: 701a strb r2, [r3, #0] } 800c606: bdf8 pop {r3, r4, r5, r6, r7, pc} memcpy(&CCS_EvInfo, payload, sizeof(CCS_EvInfo_t)); 800c608: 4f2d ldr r7, [pc, #180] @ (800c6c0 ) 800c60a: 462c mov r4, r5 800c60c: 463e mov r6, r7 800c60e: f105 0c20 add.w ip, r5, #32 800c612: 4635 mov r5, r6 800c614: 6820 ldr r0, [r4, #0] 800c616: 6861 ldr r1, [r4, #4] 800c618: 68a2 ldr r2, [r4, #8] 800c61a: 68e3 ldr r3, [r4, #12] 800c61c: 3410 adds r4, #16 800c61e: 4564 cmp r4, ip 800c620: c50f stmia r5!, {r0, r1, r2, r3} 800c622: f106 0610 add.w r6, r6, #16 800c626: d1f4 bne.n 800c612 800c628: 6861 ldr r1, [r4, #4] 800c62a: 68a2 ldr r2, [r4, #8] 800c62c: 6820 ldr r0, [r4, #0] 800c62e: c607 stmia r6!, {r0, r1, r2} CONN.SOC = (uint8_t)(CCS_EvInfo.soc / 10); 800c630: 4a24 ldr r2, [pc, #144] @ (800c6c4 ) 800c632: 887b ldrh r3, [r7, #2] 800c634: 491d ldr r1, [pc, #116] @ (800c6ac ) 800c636: fba2 2303 umull r2, r3, r2, r3 800c63a: 08db lsrs r3, r3, #3 800c63c: 708b strb r3, [r1, #2] } 800c63e: bdf8 pop {r3, r4, r5, r6, r7, pc} CCS_EvseState = (CONN_State_t)payload[0]; 800c640: 782a ldrb r2, [r5, #0] 800c642: 4b21 ldr r3, [pc, #132] @ (800c6c8 ) 800c644: 701a strb r2, [r3, #0] } 800c646: bdf8 pop {r3, r4, r5, r6, r7, pc} enabled = (p->enable != 0); 800c648: 782b ldrb r3, [r5, #0] 800c64a: 4a20 ldr r2, [pc, #128] @ (800c6cc ) 800c64c: 3b00 subs r3, #0 800c64e: bf18 it ne 800c650: 2301 movne r3, #1 800c652: 7013 strb r3, [r2, #0] } 800c654: bdf8 pop {r3, r4, r5, r6, r7, pc} CP_SetDuty(pwm_duty_percent); 800c656: 4b16 ldr r3, [pc, #88] @ (800c6b0 ) 800c658: 7818 ldrb r0, [r3, #0] } 800c65a: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} CP_SetDuty(pwm_duty_percent); 800c65e: f7fd bd0d b.w 800a07c if (p->reset) { 800c662: 782b ldrb r3, [r5, #0] 800c664: 2b00 cmp r3, #0 800c666: d0a9 beq.n 800c5bc } 800c668: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} log_printf(LOG_WARN, "Everest reset command\n"); 800c66c: 2005 movs r0, #5 800c66e: 4918 ldr r1, [pc, #96] @ (800c6d0 ) 800c670: f7fd bf36 b.w 800a4e0 fake_500_voltage_mode = 1u; 800c674: 2201 movs r2, #1 CONN.RequestedVoltage = FAKE_PSU_VOLTAGE_V; 800c676: 2100 movs r1, #0 800c678: 242c movs r4, #44 @ 0x2c CONN.WantedCurrent = FAKE_PSU_CURRENT_0P1A; 800c67a: 200a movs r0, #10 fake_500_voltage_mode = 1u; 800c67c: 4d0e ldr r5, [pc, #56] @ (800c6b8 ) CONN.RequestedVoltage = FAKE_PSU_VOLTAGE_V; 800c67e: 4b0b ldr r3, [pc, #44] @ (800c6ac ) fake_500_voltage_mode = 1u; 800c680: 702a strb r2, [r5, #0] CONN.RequestedVoltage = FAKE_PSU_VOLTAGE_V; 800c682: 741a strb r2, [r3, #16] 800c684: 73dc strb r4, [r3, #15] CONN.WantedCurrent = FAKE_PSU_CURRENT_0P1A; 800c686: 76d8 strb r0, [r3, #27] 800c688: 7719 strb r1, [r3, #28] } 800c68a: bdf8 pop {r3, r4, r5, r6, r7, pc} log_printf(LOG_WARN, 800c68c: 4622 mov r2, r4 } 800c68e: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} log_printf(LOG_WARN, 800c692: 2005 movs r0, #5 800c694: 490f ldr r1, [pc, #60] @ (800c6d4 ) 800c696: f7fd bf23 b.w 800a4e0 800c69a: bf00 nop 800c69c: 20000bb9 .word 0x20000bb9 800c6a0: 20000bb4 .word 0x20000bb4 800c6a4: 20000bba .word 0x20000bba 800c6a8: 20000bbb .word 0x20000bbb 800c6ac: 200003b0 .word 0x200003b0 800c6b0: 2000006a .word 0x2000006a 800c6b4: 200009ad .word 0x200009ad 800c6b8: 20000bb8 .word 0x20000bb8 800c6bc: 20000bb3 .word 0x20000bb3 800c6c0: 20000be4 .word 0x20000be4 800c6c4: cccccccd .word 0xcccccccd 800c6c8: 20000c10 .word 0x20000c10 800c6cc: 20000bb2 .word 0x20000bb2 800c6d0: 08016f48 .word 0x08016f48 800c6d4: 08016f60 .word 0x08016f60 0800c6d8 : ISR_FAST static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len) { 800c6d8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} if (packet_len < 3u) { 800c6dc: 2902 cmp r1, #2 ISR_FAST static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len) { 800c6de: 460c mov r4, r1 800c6e0: 4605 mov r5, r0 800c6e2: b084 sub sp, #16 if (packet_len < 3u) { 800c6e4: d930 bls.n 800c748 uint8_t cmd = packet[0]; uint16_t payload_len = (uint16_t)(packet_len - 3u); uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | (uint16_t)packet[packet_len - 1u] << 8; 800c6e6: 1843 adds r3, r0, r1 uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800c6e8: f813 2c01 ldrb.w r2, [r3, #-1] 800c6ec: f813 7c02 ldrb.w r7, [r3, #-2] uint16_t payload_len = (uint16_t)(packet_len - 3u); 800c6f0: 1ece subs r6, r1, #3 uint16_t calculated_crc = crc16_ibm(packet, (uint16_t)(1u + payload_len)); 800c6f2: 3902 subs r1, #2 800c6f4: b289 uxth r1, r1 uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800c6f6: ea47 2702 orr.w r7, r7, r2, lsl #8 uint8_t cmd = packet[0]; 800c6fa: f890 8000 ldrb.w r8, [r0] uint16_t calculated_crc = crc16_ibm(packet, (uint16_t)(1u + payload_len)); 800c6fe: f7ff fda1 bl 800c244 if (received_crc != calculated_crc) { 800c702: 4287 cmp r7, r0 uint16_t payload_len = (uint16_t)(packet_len - 3u); 800c704: b2b6 uxth r6, r6 if (received_crc != calculated_crc) { 800c706: d112 bne.n 800c72e cmd, (unsigned)packet_len, (unsigned)payload_len, (unsigned)received_crc, (unsigned)calculated_crc); return 0; } uint16_t expected_len = expected_payload_len(cmd); 800c708: 4640 mov r0, r8 800c70a: f7ff ff2f bl 800c56c if (expected_len == 0xFFFFu) { 800c70e: f64f 72ff movw r2, #65535 @ 0xffff 800c712: 4290 cmp r0, r2 800c714: d03a beq.n 800c78c log_printf(LOG_WARN, "UART3 RX drop: unknown_cmd cmd=0x%02x total_len=%u payload_len=%u\n", cmd, (unsigned)packet_len, (unsigned)payload_len); return 0; } if (expected_len != payload_len) { 800c716: 4286 cmp r6, r0 800c718: d12a bne.n 800c770 cmd, (unsigned)expected_len, (unsigned)payload_len, (unsigned)packet_len); return 0; } if (payload_len > 0) { apply_command(cmd, &packet[1], payload_len); 800c71a: 4632 mov r2, r6 if (payload_len > 0) { 800c71c: b9fe cbnz r6, 800c75e } else { apply_command(cmd, NULL, 0); 800c71e: 4631 mov r1, r6 800c720: 4640 mov r0, r8 800c722: f7ff ff2f bl 800c584 } return 1; 800c726: 2001 movs r0, #1 } 800c728: b004 add sp, #16 800c72a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} log_printf(LOG_ERR, 800c72e: 9002 str r0, [sp, #8] 800c730: 4623 mov r3, r4 800c732: 4642 mov r2, r8 800c734: 2004 movs r0, #4 800c736: e9cd 6700 strd r6, r7, [sp] 800c73a: 4918 ldr r1, [pc, #96] @ (800c79c ) 800c73c: f7fd fed0 bl 800a4e0 return 0; 800c740: 2000 movs r0, #0 } 800c742: b004 add sp, #16 800c744: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} if (packet_len == 0u) { 800c748: b1d9 cbz r1, 800c782 } else if (packet_len == 1u) { 800c74a: 2901 cmp r1, #1 log_printf(LOG_WARN, "UART3 RX drop: too_short len=1 b0=0x%02x\n", packet[0]); 800c74c: 7802 ldrb r2, [r0, #0] 800c74e: f04f 0005 mov.w r0, #5 } else if (packet_len == 1u) { 800c752: d009 beq.n 800c768 log_printf(LOG_WARN, "UART3 RX drop: too_short len=2 b0=0x%02x b1=0x%02x\n", 800c754: 786b ldrb r3, [r5, #1] 800c756: 4912 ldr r1, [pc, #72] @ (800c7a0 ) 800c758: f7fd fec2 bl 800a4e0 800c75c: e7f0 b.n 800c740 apply_command(cmd, &packet[1], payload_len); 800c75e: 4640 mov r0, r8 800c760: 1c69 adds r1, r5, #1 800c762: f7ff ff0f bl 800c584 800c766: e7de b.n 800c726 log_printf(LOG_WARN, "UART3 RX drop: too_short len=1 b0=0x%02x\n", packet[0]); 800c768: 490e ldr r1, [pc, #56] @ (800c7a4 ) 800c76a: f7fd feb9 bl 800a4e0 800c76e: e7e7 b.n 800c740 log_printf(LOG_ERR, 800c770: 4603 mov r3, r0 800c772: 4642 mov r2, r8 800c774: e9cd 6400 strd r6, r4, [sp] 800c778: 490b ldr r1, [pc, #44] @ (800c7a8 ) 800c77a: 2004 movs r0, #4 800c77c: f7fd feb0 bl 800a4e0 return 0; 800c780: e7de b.n 800c740 log_printf(LOG_WARN, "UART3 RX drop: too_short len=0 (empty chunk)\n"); 800c782: 490a ldr r1, [pc, #40] @ (800c7ac ) 800c784: 2005 movs r0, #5 800c786: f7fd feab bl 800a4e0 800c78a: e7d9 b.n 800c740 log_printf(LOG_WARN, 800c78c: 4623 mov r3, r4 800c78e: 4642 mov r2, r8 800c790: 4907 ldr r1, [pc, #28] @ (800c7b0 ) 800c792: 9600 str r6, [sp, #0] 800c794: 2005 movs r0, #5 800c796: f7fd fea3 bl 800a4e0 return 0; 800c79a: e7d1 b.n 800c740 800c79c: 08017050 .word 0x08017050 800c7a0: 0801701c .word 0x0801701c 800c7a4: 08016ff0 .word 0x08016ff0 800c7a8: 080170f8 .word 0x080170f8 800c7ac: 08016fc0 .word 0x08016fc0 800c7b0: 080170b4 .word 0x080170b4 0800c7b4 : static void CCS_UART3_Watchdog(void) { 800c7b4: b580 push {r7, lr} 800c7b6: b082 sub sp, #8 800c7b8: af00 add r7, sp, #0 const uint32_t now = HAL_GetTick(); 800c7ba: f001 fc2b bl 800e014 800c7be: 6078 str r0, [r7, #4] const uint32_t since_last_packet = now - uart3_last_packet_tick; 800c7c0: 4b16 ldr r3, [pc, #88] @ (800c81c ) 800c7c2: 681b ldr r3, [r3, #0] 800c7c4: 687a ldr r2, [r7, #4] 800c7c6: 1ad3 subs r3, r2, r3 800c7c8: 603b str r3, [r7, #0] if ((since_last_packet >= UART3_REINIT_TIMEOUT_MS) && 800c7ca: 683b ldr r3, [r7, #0] 800c7cc: f240 52db movw r2, #1499 @ 0x5db 800c7d0: 4293 cmp r3, r2 800c7d2: d91f bls.n 800c814 ((now - uart3_last_reinit_tick) >= UART3_REINIT_TIMEOUT_MS)) { 800c7d4: 4b12 ldr r3, [pc, #72] @ (800c820 ) 800c7d6: 681b ldr r3, [r3, #0] 800c7d8: 687a ldr r2, [r7, #4] 800c7da: 1ad3 subs r3, r2, r3 if ((since_last_packet >= UART3_REINIT_TIMEOUT_MS) && 800c7dc: f240 52db movw r2, #1499 @ 0x5db 800c7e0: 4293 cmp r3, r2 800c7e2: d917 bls.n 800c814 (void)HAL_UART_Abort_IT(&huart3); 800c7e4: 480f ldr r0, [pc, #60] @ (800c824 ) 800c7e6: f006 fbb9 bl 8012f5c (void)HAL_UART_DeInit(&huart3); 800c7ea: 480e ldr r0, [pc, #56] @ (800c824 ) 800c7ec: f006 faf2 bl 8012dd4 (void)HAL_UART_Init(&huart3); 800c7f0: 480c ldr r0, [pc, #48] @ (800c824 ) 800c7f2: f006 fa9f bl 8012d34 (void)HAL_UARTEx_ReceiveToIdle_IT(&huart3, rx_buffer, sizeof(rx_buffer)); 800c7f6: f44f 7280 mov.w r2, #256 @ 0x100 800c7fa: 490b ldr r1, [pc, #44] @ (800c828 ) 800c7fc: 4809 ldr r0, [pc, #36] @ (800c824 ) 800c7fe: f006 fb50 bl 8012ea2 log_printf(LOG_ERR, 800c802: f240 52dc movw r2, #1500 @ 0x5dc 800c806: 4909 ldr r1, [pc, #36] @ (800c82c ) 800c808: 2004 movs r0, #4 800c80a: f7fd fe69 bl 800a4e0 "UART3 RX recover: stalled (no RxEvent data for %ums), hard reinit\n", (unsigned)UART3_REINIT_TIMEOUT_MS); uart3_last_reinit_tick = now; 800c80e: 4a04 ldr r2, [pc, #16] @ (800c820 ) 800c810: 687b ldr r3, [r7, #4] 800c812: 6013 str r3, [r2, #0] } } 800c814: bf00 nop 800c816: 3708 adds r7, #8 800c818: 46bd mov sp, r7 800c81a: bd80 pop {r7, pc} 800c81c: 20000bbc .word 0x20000bbc 800c820: 20000bc0 .word 0x20000bc0 800c824: 20001228 .word 0x20001228 800c828: 200009b0 .word 0x200009b0 800c82c: 08017150 .word 0x08017150 0800c830 : .fw_version_major = 0, .fw_version_minor = 0, .fw_version_patch = 0, }; void ReadVersion(){ 800c830: b480 push {r7} 800c832: af00 add r7, sp, #0 infoPacket.serialNumber = InfoBlock->serialNumber; 800c834: 4b0e ldr r3, [pc, #56] @ (800c870 ) 800c836: 681b ldr r3, [r3, #0] 800c838: 681b ldr r3, [r3, #0] 800c83a: b29a uxth r2, r3 800c83c: 4b0d ldr r3, [pc, #52] @ (800c874 ) 800c83e: 801a strh r2, [r3, #0] infoPacket.boardVersion = InfoBlock->boardVersion; 800c840: 4b0b ldr r3, [pc, #44] @ (800c870 ) 800c842: 681b ldr r3, [r3, #0] 800c844: 795a ldrb r2, [r3, #5] 800c846: 4b0b ldr r3, [pc, #44] @ (800c874 ) 800c848: 709a strb r2, [r3, #2] infoPacket.stationType = InfoBlock->stationType; 800c84a: 4b09 ldr r3, [pc, #36] @ (800c870 ) 800c84c: 681b ldr r3, [r3, #0] 800c84e: 791a ldrb r2, [r3, #4] 800c850: 4b08 ldr r3, [pc, #32] @ (800c874 ) 800c852: 70da strb r2, [r3, #3] infoPacket.fw_version_major = FW_VERSION_MAJOR; 800c854: 4b07 ldr r3, [pc, #28] @ (800c874 ) 800c856: 2201 movs r2, #1 800c858: 809a strh r2, [r3, #4] infoPacket.fw_version_minor = FW_VERSION_MINOR; 800c85a: 4b06 ldr r3, [pc, #24] @ (800c874 ) 800c85c: 2200 movs r2, #0 800c85e: 80da strh r2, [r3, #6] infoPacket.fw_version_patch = FW_VERSION_PATCH; 800c860: 4b04 ldr r3, [pc, #16] @ (800c874 ) 800c862: 2211 movs r2, #17 800c864: 811a strh r2, [r3, #8] } 800c866: bf00 nop 800c868: 46bd mov sp, r7 800c86a: bc80 pop {r7} 800c86c: 4770 bx lr 800c86e: bf00 nop 800c870: 20000000 .word 0x20000000 800c874: 200010b0 .word 0x200010b0 0800c878 : // Внешняя функция обработки команд (определена в serial_handler.c) extern void SC_CommandHandler(ReceivedCommand_t* cmd); void SC_Init() { 800c878: b580 push {r7, lr} 800c87a: af00 add r7, sp, #0 // Обнуляем структуру memset(&serial_control, 0, sizeof(SerialControl_t)); 800c87c: f44f 7204 mov.w r2, #528 @ 0x210 800c880: 2100 movs r1, #0 800c882: 480d ldr r0, [pc, #52] @ (800c8b8 ) 800c884: f007 ff5a bl 801473c memset(&serial_iso, 0, sizeof(serial_iso)); 800c888: f44f 7204 mov.w r2, #528 @ 0x210 800c88c: 2100 movs r1, #0 800c88e: 480b ldr r0, [pc, #44] @ (800c8bc ) 800c890: f007 ff54 bl 801473c sc_uart2_timed_out = 0; 800c894: 4b0a ldr r3, [pc, #40] @ (800c8c0 ) 800c896: 2200 movs r2, #0 800c898: 701a strb r2, [r3, #0] sc_uart2_last_packet_tick = HAL_GetTick(); 800c89a: f001 fbbb bl 800e014 800c89e: 4603 mov r3, r0 800c8a0: 4a08 ldr r2, [pc, #32] @ (800c8c4 ) 800c8a2: 6013 str r3, [r2, #0] sc_uart2_last_reinit_tick = sc_uart2_last_packet_tick; 800c8a4: 4b07 ldr r3, [pc, #28] @ (800c8c4 ) 800c8a6: 681b ldr r3, [r3, #0] 800c8a8: 4a07 ldr r2, [pc, #28] @ (800c8c8 ) 800c8aa: 6013 str r3, [r2, #0] sc_uart2_rx_during_tx = 0; 800c8ac: 4b07 ldr r3, [pc, #28] @ (800c8cc ) 800c8ae: 2200 movs r2, #0 800c8b0: 701a strb r2, [r3, #0] } 800c8b2: bf00 nop 800c8b4: bd80 pop {r7, pc} 800c8b6: bf00 nop 800c8b8: 20000c28 .word 0x20000c28 800c8bc: 20000e38 .word 0x20000e38 800c8c0: 20001049 .word 0x20001049 800c8c4: 2000104c .word 0x2000104c 800c8c8: 20001050 .word 0x20001050 800c8cc: 20001054 .word 0x20001054 0800c8d0 : void SC_Task() { 800c8d0: b580 push {r7, lr} 800c8d2: af00 add r7, sp, #0 SC_UART2_Watchdog(); 800c8d4: f000 f9e8 bl 800cca8 // Запуск приема в режиме прерывания с ожиданием idle if ((huart2.RxState == HAL_UART_STATE_READY) && (serial_control.command_ready == 0)) { 800c8d8: 4b3c ldr r3, [pc, #240] @ (800c9cc ) 800c8da: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800c8de: b2db uxtb r3, r3 800c8e0: 2b20 cmp r3, #32 800c8e2: d116 bne.n 800c912 800c8e4: 4b3a ldr r3, [pc, #232] @ (800c9d0 ) 800c8e6: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800c8ea: b2db uxtb r3, r3 800c8ec: 2b00 cmp r3, #0 800c8ee: d110 bne.n 800c912 if ((HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1) != HAL_OK) && 800c8f0: 22ff movs r2, #255 @ 0xff 800c8f2: 4938 ldr r1, [pc, #224] @ (800c9d4 ) 800c8f4: 4835 ldr r0, [pc, #212] @ (800c9cc ) 800c8f6: f006 fad4 bl 8012ea2 800c8fa: 4603 mov r3, r0 800c8fc: 2b00 cmp r3, #0 800c8fe: d008 beq.n 800c912 (HAL_UART_GetError(&huart2) != HAL_UART_ERROR_NONE)) { 800c900: 4832 ldr r0, [pc, #200] @ (800c9cc ) 800c902: f006 fee3 bl 80136cc 800c906: 4603 mov r3, r0 if ((HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1) != HAL_OK) && 800c908: 2b00 cmp r3, #0 800c90a: d002 beq.n 800c912 (void)HAL_UART_Abort_IT(&huart2); 800c90c: 482f ldr r0, [pc, #188] @ (800c9cc ) 800c90e: f006 fb25 bl 8012f5c } } if (huart5.RxState == HAL_UART_STATE_READY) { 800c912: 4b31 ldr r3, [pc, #196] @ (800c9d8 ) 800c914: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800c918: b2db uxtb r3, r3 800c91a: 2b20 cmp r3, #32 800c91c: d110 bne.n 800c940 if ((HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1) != HAL_OK) && 800c91e: 22ff movs r2, #255 @ 0xff 800c920: 492e ldr r1, [pc, #184] @ (800c9dc ) 800c922: 482d ldr r0, [pc, #180] @ (800c9d8 ) 800c924: f006 fabd bl 8012ea2 800c928: 4603 mov r3, r0 800c92a: 2b00 cmp r3, #0 800c92c: d008 beq.n 800c940 (HAL_UART_GetError(&huart5) != HAL_UART_ERROR_NONE)) { 800c92e: 482a ldr r0, [pc, #168] @ (800c9d8 ) 800c930: f006 fecc bl 80136cc 800c934: 4603 mov r3, r0 if ((HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1) != HAL_OK) && 800c936: 2b00 cmp r3, #0 800c938: d002 beq.n 800c940 (void)HAL_UART_Abort_IT(&huart5); 800c93a: 4827 ldr r0, [pc, #156] @ (800c9d8 ) 800c93c: f006 fb0e bl 8012f5c } } // Проверка таймаута отправки пакета (больше 100 мс) if (huart2.gState == HAL_UART_STATE_BUSY_TX && serial_control.tx_tick != 0) { 800c940: 4b22 ldr r3, [pc, #136] @ (800c9cc ) 800c942: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800c946: b2db uxtb r3, r3 800c948: 2b21 cmp r3, #33 @ 0x21 800c94a: d119 bne.n 800c980 800c94c: 4b20 ldr r3, [pc, #128] @ (800c9d0 ) 800c94e: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c 800c952: 2b00 cmp r3, #0 800c954: d014 beq.n 800c980 if ((HAL_GetTick() - serial_control.tx_tick) > 100) { 800c956: f001 fb5d bl 800e014 800c95a: 4602 mov r2, r0 800c95c: 4b1c ldr r3, [pc, #112] @ (800c9d0 ) 800c95e: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c 800c962: 1ad3 subs r3, r2, r3 800c964: 2b64 cmp r3, #100 @ 0x64 800c966: d90b bls.n 800c980 // Таймаут: принудительно сбрасываем передачу HAL_UART_Abort_IT(&huart2); 800c968: 4818 ldr r0, [pc, #96] @ (800c9cc ) 800c96a: f006 faf7 bl 8012f5c // Выключаем DIR при сбросе передачи HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800c96e: 2200 movs r2, #0 800c970: 2110 movs r1, #16 800c972: 481b ldr r0, [pc, #108] @ (800c9e0 ) 800c974: f003 ffc9 bl 801090a serial_control.tx_tick = 0; // Сбрасываем tick 800c978: 4b15 ldr r3, [pc, #84] @ (800c9d0 ) 800c97a: 2200 movs r2, #0 800c97c: f8c3 220c str.w r2, [r3, #524] @ 0x20c } } // Проверка наличия принятой команды для обработки if (serial_control.command_ready && (huart2.gState != HAL_UART_STATE_BUSY_TX)) { 800c980: 4b13 ldr r3, [pc, #76] @ (800c9d0 ) 800c982: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800c986: b2db uxtb r3, r3 800c988: 2b00 cmp r3, #0 800c98a: d01d beq.n 800c9c8 800c98c: 4b0f ldr r3, [pc, #60] @ (800c9cc ) 800c98e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800c992: b2db uxtb r3, r3 800c994: 2b21 cmp r3, #33 @ 0x21 800c996: d017 beq.n 800c9c8 // HAL_Delay(2); SC_CommandHandler(&serial_control.received_command); 800c998: 4812 ldr r0, [pc, #72] @ (800c9e4 ) 800c99a: f000 fa25 bl 800cde8 if ((HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1) != HAL_OK) && 800c99e: 22ff movs r2, #255 @ 0xff 800c9a0: 490c ldr r1, [pc, #48] @ (800c9d4 ) 800c9a2: 480a ldr r0, [pc, #40] @ (800c9cc ) 800c9a4: f006 fa7d bl 8012ea2 800c9a8: 4603 mov r3, r0 800c9aa: 2b00 cmp r3, #0 800c9ac: d008 beq.n 800c9c0 (HAL_UART_GetError(&huart2) != HAL_UART_ERROR_NONE)) { 800c9ae: 4807 ldr r0, [pc, #28] @ (800c9cc ) 800c9b0: f006 fe8c bl 80136cc 800c9b4: 4603 mov r3, r0 if ((HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1) != HAL_OK) && 800c9b6: 2b00 cmp r3, #0 800c9b8: d002 beq.n 800c9c0 (void)HAL_UART_Abort_IT(&huart2); 800c9ba: 4804 ldr r0, [pc, #16] @ (800c9cc ) 800c9bc: f006 face bl 8012f5c } serial_control.command_ready = 0; // Сбрасываем флаг 800c9c0: 4b03 ldr r3, [pc, #12] @ (800c9d0 ) 800c9c2: 2200 movs r2, #0 800c9c4: f883 2208 strb.w r2, [r3, #520] @ 0x208 } } 800c9c8: bf00 nop 800c9ca: bd80 pop {r7, pc} 800c9cc: 200011e0 .word 0x200011e0 800c9d0: 20000c28 .word 0x20000c28 800c9d4: 20000d28 .word 0x20000d28 800c9d8: 20001150 .word 0x20001150 800c9dc: 20000f38 .word 0x20000f38 800c9e0: 40011400 .word 0x40011400 800c9e4: 20000e28 .word 0x20000e28 0800c9e8 : ISR_FAST void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800c9e8: b570 push {r4, r5, r6, lr} if (huart->Instance == huart2.Instance) { 800c9ea: 4c28 ldr r4, [pc, #160] @ (800ca8c ) 800c9ec: 6803 ldr r3, [r0, #0] 800c9ee: 6822 ldr r2, [r4, #0] ISR_FAST void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800c9f0: 460d mov r5, r1 if (huart->Instance == huart2.Instance) { 800c9f2: 4293 cmp r3, r2 800c9f4: d008 beq.n 800ca08 if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ SC_SendPacket(NULL, 0, RESP_INVALID); } g_sc_command_source = SC_SOURCE_UART2; HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); } else if (huart->Instance == huart5.Instance) { 800c9f6: 4a26 ldr r2, [pc, #152] @ (800ca90 ) 800c9f8: 6812 ldr r2, [r2, #0] 800c9fa: 4293 cmp r3, r2 800c9fc: d02c beq.n 800ca58 if (process_received_packet(&serial_iso, serial_iso.rx_buffer, Size)) { g_sc_command_source = SC_SOURCE_UART5; SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); } HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1); } else if (huart->Instance == huart3.Instance) { 800c9fe: 4a25 ldr r2, [pc, #148] @ (800ca94 ) 800ca00: 6812 ldr r2, [r2, #0] 800ca02: 4293 cmp r3, r2 800ca04: d024 beq.n 800ca50 CCS_RxEventCallback(huart, Size); } } 800ca06: bd70 pop {r4, r5, r6, pc} if (huart2.gState == HAL_UART_STATE_BUSY_TX) { 800ca08: f894 3041 ldrb.w r3, [r4, #65] @ 0x41 800ca0c: 2b21 cmp r3, #33 @ 0x21 800ca0e: d01b beq.n 800ca48 sc_uart2_last_packet_tick = HAL_GetTick(); 800ca10: f001 fb00 bl 800e014 sc_uart2_timed_out = 0; 800ca14: 2200 movs r2, #0 800ca16: 4b20 ldr r3, [pc, #128] @ (800ca98 ) if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800ca18: 4920 ldr r1, [pc, #128] @ (800ca9c ) sc_uart2_timed_out = 0; 800ca1a: 701a strb r2, [r3, #0] sc_uart2_last_packet_tick = HAL_GetTick(); 800ca1c: 4603 mov r3, r0 800ca1e: 4e20 ldr r6, [pc, #128] @ (800caa0 ) sc_uart2_last_reinit_tick = sc_uart2_last_packet_tick; 800ca20: 4c20 ldr r4, [pc, #128] @ (800caa4 ) if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800ca22: f5a1 7080 sub.w r0, r1, #256 @ 0x100 800ca26: 462a mov r2, r5 sc_uart2_last_packet_tick = HAL_GetTick(); 800ca28: 6033 str r3, [r6, #0] sc_uart2_last_reinit_tick = sc_uart2_last_packet_tick; 800ca2a: 6023 str r3, [r4, #0] if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800ca2c: f000 f92e bl 800cc8c 800ca30: 4601 mov r1, r0 800ca32: b1f8 cbz r0, 800ca74 g_sc_command_source = SC_SOURCE_UART2; 800ca34: 2400 movs r4, #0 800ca36: 4b1c ldr r3, [pc, #112] @ (800caa8 ) HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800ca38: 22ff movs r2, #255 @ 0xff g_sc_command_source = SC_SOURCE_UART2; 800ca3a: 701c strb r4, [r3, #0] HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800ca3c: 4917 ldr r1, [pc, #92] @ (800ca9c ) 800ca3e: 4813 ldr r0, [pc, #76] @ (800ca8c ) } 800ca40: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800ca44: f006 ba2d b.w 8012ea2 sc_uart2_rx_during_tx = 1u; 800ca48: 2201 movs r2, #1 800ca4a: 4b18 ldr r3, [pc, #96] @ (800caac ) 800ca4c: 701a strb r2, [r3, #0] 800ca4e: e7df b.n 800ca10 } 800ca50: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} CCS_RxEventCallback(huart, Size); 800ca54: f7ff b89e b.w 800bb94 if (process_received_packet(&serial_iso, serial_iso.rx_buffer, Size)) { 800ca58: 4915 ldr r1, [pc, #84] @ (800cab0 ) 800ca5a: 462a mov r2, r5 800ca5c: f5a1 7080 sub.w r0, r1, #256 @ 0x100 800ca60: f000 f914 bl 800cc8c 800ca64: b950 cbnz r0, 800ca7c } 800ca66: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800ca6a: 22ff movs r2, #255 @ 0xff 800ca6c: 4910 ldr r1, [pc, #64] @ (800cab0 ) 800ca6e: 4808 ldr r0, [pc, #32] @ (800ca90 ) 800ca70: f006 ba17 b.w 8012ea2 SC_SendPacket(NULL, 0, RESP_INVALID); 800ca74: 2214 movs r2, #20 800ca76: f000 f8af bl 800cbd8 800ca7a: e7db b.n 800ca34 g_sc_command_source = SC_SOURCE_UART5; 800ca7c: 2201 movs r2, #1 800ca7e: 4b0a ldr r3, [pc, #40] @ (800caa8 ) SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); 800ca80: 480c ldr r0, [pc, #48] @ (800cab4 ) g_sc_command_source = SC_SOURCE_UART5; 800ca82: 701a strb r2, [r3, #0] SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); 800ca84: f000 f9b0 bl 800cde8 800ca88: e7ed b.n 800ca66 800ca8a: bf00 nop 800ca8c: 200011e0 .word 0x200011e0 800ca90: 20001150 .word 0x20001150 800ca94: 20001228 .word 0x20001228 800ca98: 20001049 .word 0x20001049 800ca9c: 20000d28 .word 0x20000d28 800caa0: 2000104c .word 0x2000104c 800caa4: 20001050 .word 0x20001050 800caa8: 20001048 .word 0x20001048 800caac: 20001054 .word 0x20001054 800cab0: 20000f38 .word 0x20000f38 800cab4: 20001038 .word 0x20001038 0800cab8 : ISR_FAST void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 800cab8: b508 push {r3, lr} if (huart->Instance == huart2.Instance) { 800caba: 4b08 ldr r3, [pc, #32] @ (800cadc ) 800cabc: 6802 ldr r2, [r0, #0] 800cabe: 681b ldr r3, [r3, #0] 800cac0: 429a cmp r2, r3 800cac2: d000 beq.n 800cac6 HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); serial_control.tx_tick = 0; } } 800cac4: bd08 pop {r3, pc} HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800cac6: 2200 movs r2, #0 800cac8: 2110 movs r1, #16 800caca: 4805 ldr r0, [pc, #20] @ (800cae0 ) 800cacc: f003 ff1d bl 801090a serial_control.tx_tick = 0; 800cad0: 2200 movs r2, #0 800cad2: 4b04 ldr r3, [pc, #16] @ (800cae4 ) 800cad4: f8c3 220c str.w r2, [r3, #524] @ 0x20c } 800cad8: bd08 pop {r3, pc} 800cada: bf00 nop 800cadc: 200011e0 .word 0x200011e0 800cae0: 40011400 .word 0x40011400 800cae4: 20000c28 .word 0x20000c28 0800cae8 : // Полностью программная реализация CRC-32 (полином CRC32_POLYNOMIAL, порядок little-endian) ISR_FAST static uint32_t calculate_crc32(const uint8_t* data, uint16_t length) { uint32_t crc = 0xFFFFFFFFu; for (uint16_t i = 0; i < length; i++) { 800cae8: b3c9 cbz r1, 800cb5e uint32_t crc = 0xFFFFFFFFu; 800caea: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff ISR_FAST static uint32_t calculate_crc32(const uint8_t* data, uint16_t length) { 800caee: b500 push {lr} crc ^= data[i]; for (uint8_t bit = 0; bit < 8; bit++) { if (crc & 0x1u) { 800caf0: 4a1c ldr r2, [pc, #112] @ (800cb64 ) 800caf2: 4401 add r1, r0 crc ^= data[i]; 800caf4: f810 eb01 ldrb.w lr, [r0], #1 800caf8: ea8e 0e03 eor.w lr, lr, r3 if (crc & 0x1u) { 800cafc: f34e 0300 sbfx r3, lr, #0, #1 800cb00: f34e 0c40 sbfx ip, lr, #1, #1 800cb04: 4013 ands r3, r2 800cb06: ea83 035e eor.w r3, r3, lr, lsr #1 800cb0a: ea0c 0c02 and.w ip, ip, r2 800cb0e: ea8c 0c53 eor.w ip, ip, r3, lsr #1 800cb12: f343 0340 sbfx r3, r3, #1, #1 800cb16: f34c 0e40 sbfx lr, ip, #1, #1 800cb1a: 4013 ands r3, r2 800cb1c: ea83 035c eor.w r3, r3, ip, lsr #1 800cb20: ea0e 0e02 and.w lr, lr, r2 800cb24: ea8e 0e53 eor.w lr, lr, r3, lsr #1 800cb28: f343 0340 sbfx r3, r3, #1, #1 800cb2c: f34e 0c40 sbfx ip, lr, #1, #1 800cb30: 4013 ands r3, r2 800cb32: ea83 035e eor.w r3, r3, lr, lsr #1 800cb36: ea0c 0c02 and.w ip, ip, r2 800cb3a: ea8c 0c53 eor.w ip, ip, r3, lsr #1 800cb3e: f343 0340 sbfx r3, r3, #1, #1 800cb42: 4013 ands r3, r2 800cb44: f34c 0e40 sbfx lr, ip, #1, #1 800cb48: ea83 035c eor.w r3, r3, ip, lsr #1 for (uint16_t i = 0; i < length; i++) { 800cb4c: 4281 cmp r1, r0 if (crc & 0x1u) { 800cb4e: ea0e 0c02 and.w ip, lr, r2 800cb52: ea8c 0353 eor.w r3, ip, r3, lsr #1 for (uint16_t i = 0; i < length; i++) { 800cb56: d1cd bne.n 800caf4 crc >>= 1; } } } return crc ^ 0xFFFFFFFFu; 800cb58: 43d8 mvns r0, r3 } 800cb5a: f85d fb04 ldr.w pc, [sp], #4 for (uint16_t i = 0; i < length; i++) { 800cb5e: 4608 mov r0, r1 } 800cb60: 4770 bx lr 800cb62: bf00 nop 800cb64: edb88320 .word 0xedb88320 0800cb68 : ISR_FAST static uint16_t encode_packet(const uint8_t* payload, uint16_t payload_len, uint8_t* output, uint8_t response_code) { 800cb68: b570 push {r4, r5, r6, lr} 800cb6a: 4615 mov r5, r2 uint16_t out_index = 0; output[out_index++] = response_code; 800cb6c: 7013 strb r3, [r2, #0] if (payload != NULL) { 800cb6e: b360 cbz r0, 800cbca // Просто копируем полезную нагрузку без какого‑либо экранирования for (uint16_t i = 0; i < payload_len; i++) { 800cb70: b359 cbz r1, 800cbca output[out_index++] = payload[i]; 800cb72: 4694 mov ip, r2 800cb74: 2302 movs r3, #2 800cb76: 7802 ldrb r2, [r0, #0] 800cb78: 1e4c subs r4, r1, #1 800cb7a: b2a4 uxth r4, r4 800cb7c: 441c add r4, r3 800cb7e: f80c 2f01 strb.w r2, [ip, #1]! // Проверка переполнения if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800cb82: e005 b.n 800cb90 output[out_index++] = payload[i]; 800cb84: f810 1f01 ldrb.w r1, [r0, #1]! if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800cb88: 2bfb cmp r3, #251 @ 0xfb output[out_index++] = payload[i]; 800cb8a: f80c 1f01 strb.w r1, [ip, #1]! if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800cb8e: d020 beq.n 800cbd2 for (uint16_t i = 0; i < payload_len; i++) { 800cb90: 42a3 cmp r3, r4 if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800cb92: f103 0301 add.w r3, r3, #1 for (uint16_t i = 0; i < payload_len; i++) { 800cb96: d1f5 bne.n 800cb84 800cb98: b2a1 uxth r1, r4 output[out_index++] = payload[i]; 800cb9a: 1c4e adds r6, r1, #1 800cb9c: b2b6 uxth r6, r6 } } } // Вычисляем CRC для всего содержимого (код ответа + полезная нагрузка) uint32_t crc = calculate_crc32(output, out_index); 800cb9e: 4628 mov r0, r5 800cba0: f7ff ffa2 bl 800cae8 800cba4: 4603 mov r3, r0 uint8_t* crc_bytes = (uint8_t*)&crc; // Добавляем CRC без экранирования for (int i = 0; i < 4; i++) { output[out_index++] = crc_bytes[i]; 800cba6: 1c71 adds r1, r6, #1 800cba8: 1cb2 adds r2, r6, #2 800cbaa: 552b strb r3, [r5, r4] 800cbac: f3c3 2c07 ubfx ip, r3, #8, #8 800cbb0: f3c3 4407 ubfx r4, r3, #16, #8 800cbb4: b289 uxth r1, r1 800cbb6: b292 uxth r2, r2 800cbb8: f3c3 6307 ubfx r3, r3, #24, #8 800cbbc: f805 c006 strb.w ip, [r5, r6] 800cbc0: 1cf0 adds r0, r6, #3 800cbc2: 546c strb r4, [r5, r1] 800cbc4: 54ab strb r3, [r5, r2] 800cbc6: b280 uxth r0, r0 return 0; } } return out_index; } 800cbc8: bd70 pop {r4, r5, r6, pc} for (uint16_t i = 0; i < payload_len; i++) { 800cbca: 2401 movs r4, #1 800cbcc: 2602 movs r6, #2 output[out_index++] = response_code; 800cbce: 4621 mov r1, r4 800cbd0: e7e5 b.n 800cb9e return 0; 800cbd2: 2000 movs r0, #0 } 800cbd4: bd70 pop {r4, r5, r6, pc} 800cbd6: bf00 nop 0800cbd8 : ISR_FAST void SC_SendPacket(const uint8_t* payload, uint16_t payload_len, uint8_t response_code) { 800cbd8: b538 push {r3, r4, r5, lr} 800cbda: 4613 mov r3, r2 uint16_t packet_len = encode_packet(payload, payload_len, serial_control.tx_buffer, response_code); 800cbdc: 4a13 ldr r2, [pc, #76] @ (800cc2c ) 800cbde: f7ff ffc3 bl 800cb68 if (packet_len > 0) { 800cbe2: b1c8 cbz r0, 800cc18 if (huart2.gState == HAL_UART_STATE_BUSY_TX) { 800cbe4: 4604 mov r4, r0 800cbe6: 4812 ldr r0, [pc, #72] @ (800cc30 ) 800cbe8: f890 3041 ldrb.w r3, [r0, #65] @ 0x41 800cbec: 2b21 cmp r3, #33 @ 0x21 800cbee: d014 beq.n 800cc1a HAL_UART_Abort_IT(&huart2); HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); } HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_SET); 800cbf0: 2201 movs r2, #1 800cbf2: 2110 movs r1, #16 800cbf4: 480f ldr r0, [pc, #60] @ (800cc34 ) 800cbf6: f003 fe88 bl 801090a sc_uart2_rx_during_tx = 0u; 800cbfa: f04f 0c00 mov.w ip, #0 HAL_UART_Transmit_IT(&huart2, serial_control.tx_buffer, packet_len); 800cbfe: 4d0b ldr r5, [pc, #44] @ (800cc2c ) sc_uart2_rx_during_tx = 0u; 800cc00: 4b0d ldr r3, [pc, #52] @ (800cc38 ) HAL_UART_Transmit_IT(&huart2, serial_control.tx_buffer, packet_len); 800cc02: 4629 mov r1, r5 800cc04: 4622 mov r2, r4 800cc06: 480a ldr r0, [pc, #40] @ (800cc30 ) sc_uart2_rx_during_tx = 0u; 800cc08: f883 c000 strb.w ip, [r3] HAL_UART_Transmit_IT(&huart2, serial_control.tx_buffer, packet_len); 800cc0c: f006 f914 bl 8012e38 serial_control.tx_tick = HAL_GetTick(); 800cc10: f001 fa00 bl 800e014 800cc14: f8c5 020c str.w r0, [r5, #524] @ 0x20c } } 800cc18: bd38 pop {r3, r4, r5, pc} HAL_UART_Abort_IT(&huart2); 800cc1a: f006 f99f bl 8012f5c HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800cc1e: 2200 movs r2, #0 800cc20: 2110 movs r1, #16 800cc22: 4804 ldr r0, [pc, #16] @ (800cc34 ) 800cc24: f003 fe71 bl 801090a 800cc28: e7e2 b.n 800cbf0 800cc2a: bf00 nop 800cc2c: 20000c28 .word 0x20000c28 800cc30: 200011e0 .word 0x200011e0 800cc34: 40011400 .word 0x40011400 800cc38: 20001054 .word 0x20001054 0800cc3c : ISR_FAST static uint8_t parse_packet(const uint8_t* packet_data, uint16_t packet_len, ReceivedCommand_t* out_cmd) { 800cc3c: e92d 4178 stmdb sp!, {r3, r4, r5, r6, r8, lr} // }else{ // test_crc_invalid = 5; // } // Минимальный размер: 1 байт команды + 4 байта CRC if (packet_len < 5) return 0; 800cc40: 1f4b subs r3, r1, #5 800cc42: 2bfb cmp r3, #251 @ 0xfb 800cc44: d813 bhi.n 800cc6e if (packet_len > MAX_RX_BUFFER_SIZE) return 0; uint16_t payload_length = packet_len - 4; 800cc46: 3904 subs r1, #4 800cc48: b28c uxth r4, r1 // Извлекаем принятую CRC (последние 4 байта, little-endian) uint32_t received_checksum = ((uint32_t)packet_data[payload_length] << 0) | ((uint32_t)packet_data[payload_length + 1] << 8) | 800cc4a: 1903 adds r3, r0, r4 ((uint32_t)packet_data[payload_length + 2] << 16) | 800cc4c: 789d ldrb r5, [r3, #2] 800cc4e: 4690 mov r8, r2 ((uint32_t)packet_data[payload_length + 1] << 8) | 800cc50: 785a ldrb r2, [r3, #1] ((uint32_t)packet_data[payload_length + 2] << 16) | 800cc52: 042d lsls r5, r5, #16 ((uint32_t)packet_data[payload_length + 1] << 8) | 800cc54: ea45 2502 orr.w r5, r5, r2, lsl #8 ((uint32_t)packet_data[payload_length] << 0) | 800cc58: 5d02 ldrb r2, [r0, r4] ((uint32_t)packet_data[payload_length + 3] << 24); 800cc5a: 78db ldrb r3, [r3, #3] ((uint32_t)packet_data[payload_length + 1] << 8) | 800cc5c: 4315 orrs r5, r2 // Вычисляем CRC для полезной нагрузки uint32_t calculated_checksum = calculate_crc32(packet_data, payload_length); 800cc5e: 4621 mov r1, r4 uint32_t received_checksum = 800cc60: ea45 6503 orr.w r5, r5, r3, lsl #24 uint32_t calculated_checksum = calculate_crc32(packet_data, payload_length); 800cc64: 4606 mov r6, r0 800cc66: f7ff ff3f bl 800cae8 if (received_checksum != calculated_checksum) return 0; // CRC не совпадает 800cc6a: 4285 cmp r5, r0 800cc6c: d002 beq.n 800cc74 if (packet_len < 5) return 0; 800cc6e: 2000 movs r0, #0 out_cmd->argument = (void *)&packet_data[1]; out_cmd->command = packet_data[0]; out_cmd->argument_length = (uint8_t)(payload_length - 1); return 1; } 800cc70: e8bd 8178 ldmia.w sp!, {r3, r4, r5, r6, r8, pc} out_cmd->argument = (void *)&packet_data[1]; 800cc74: 1c73 adds r3, r6, #1 800cc76: f8c8 3004 str.w r3, [r8, #4] out_cmd->command = packet_data[0]; 800cc7a: 7833 ldrb r3, [r6, #0] out_cmd->argument_length = (uint8_t)(payload_length - 1); 800cc7c: 3c01 subs r4, #1 out_cmd->command = packet_data[0]; 800cc7e: f888 3000 strb.w r3, [r8] out_cmd->argument_length = (uint8_t)(payload_length - 1); 800cc82: f888 4001 strb.w r4, [r8, #1] return 1; 800cc86: 2001 movs r0, #1 } 800cc88: e8bd 8178 ldmia.w sp!, {r3, r4, r5, r6, r8, pc} 0800cc8c : ISR_FAST static uint8_t process_received_packet(SerialControl_t *ctx, const uint8_t* packet_data, uint16_t packet_len) { 800cc8c: b510 push {r4, lr} 800cc8e: 4604 mov r4, r0 if (!parse_packet(packet_data, packet_len, (ReceivedCommand_t *)&ctx->received_command)) { 800cc90: 4608 mov r0, r1 800cc92: 4611 mov r1, r2 800cc94: f504 7200 add.w r2, r4, #512 @ 0x200 800cc98: f7ff ffd0 bl 800cc3c 800cc9c: b118 cbz r0, 800cca6 return 0; } ctx->command_ready = 1; 800cc9e: 2301 movs r3, #1 return 1; 800cca0: 4618 mov r0, r3 ctx->command_ready = 1; 800cca2: f884 3208 strb.w r3, [r4, #520] @ 0x208 } 800cca6: bd10 pop {r4, pc} 0800cca8 : static void SC_UART2_Watchdog(void) { 800cca8: b580 push {r7, lr} 800ccaa: b082 sub sp, #8 800ccac: af00 add r7, sp, #0 const uint32_t now = HAL_GetTick(); 800ccae: f001 f9b1 bl 800e014 800ccb2: 6078 str r0, [r7, #4] const uint32_t since_last_packet = now - sc_uart2_last_packet_tick; 800ccb4: 4b37 ldr r3, [pc, #220] @ (800cd94 ) 800ccb6: 681b ldr r3, [r3, #0] 800ccb8: 687a ldr r2, [r7, #4] 800ccba: 1ad3 subs r3, r2, r3 800ccbc: 603b str r3, [r7, #0] if ((huart2.gState == HAL_UART_STATE_BUSY_TX) && (sc_uart2_rx_during_tx != 0u)) { 800ccbe: 4b36 ldr r3, [pc, #216] @ (800cd98 ) 800ccc0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800ccc4: b2db uxtb r3, r3 800ccc6: 2b21 cmp r3, #33 @ 0x21 800ccc8: d126 bne.n 800cd18 800ccca: 4b34 ldr r3, [pc, #208] @ (800cd9c ) 800cccc: 781b ldrb r3, [r3, #0] 800ccce: b2db uxtb r3, r3 800ccd0: 2b00 cmp r3, #0 800ccd2: d021 beq.n 800cd18 HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800ccd4: 2200 movs r2, #0 800ccd6: 2110 movs r1, #16 800ccd8: 4831 ldr r0, [pc, #196] @ (800cda0 ) 800ccda: f003 fe16 bl 801090a (void)HAL_UART_Abort_IT(&huart2); 800ccde: 482e ldr r0, [pc, #184] @ (800cd98 ) 800cce0: f006 f93c bl 8012f5c (void)HAL_UART_DeInit(&huart2); 800cce4: 482c ldr r0, [pc, #176] @ (800cd98 ) 800cce6: f006 f875 bl 8012dd4 (void)HAL_UART_Init(&huart2); 800ccea: 482b ldr r0, [pc, #172] @ (800cd98 ) 800ccec: f006 f822 bl 8012d34 (void)HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800ccf0: 22ff movs r2, #255 @ 0xff 800ccf2: 492c ldr r1, [pc, #176] @ (800cda4 ) 800ccf4: 4828 ldr r0, [pc, #160] @ (800cd98 ) 800ccf6: f006 f8d4 bl 8012ea2 serial_control.tx_tick = 0; 800ccfa: 4b2b ldr r3, [pc, #172] @ (800cda8 ) 800ccfc: 2200 movs r2, #0 800ccfe: f8c3 220c str.w r2, [r3, #524] @ 0x20c sc_uart2_rx_during_tx = 0u; 800cd02: 4b26 ldr r3, [pc, #152] @ (800cd9c ) 800cd04: 2200 movs r2, #0 800cd06: 701a strb r2, [r3, #0] sc_uart2_last_reinit_tick = now; 800cd08: 4a28 ldr r2, [pc, #160] @ (800cdac ) 800cd0a: 687b ldr r3, [r7, #4] 800cd0c: 6013 str r3, [r2, #0] log_printf(LOG_ERR, "USART2 BUSY_TX: hard reinit\n"); 800cd0e: 4928 ldr r1, [pc, #160] @ (800cdb0 ) 800cd10: 2004 movs r0, #4 800cd12: f7fd fbe5 bl 800a4e0 return; 800cd16: e039 b.n 800cd8c } if (since_last_packet >= SC_UART2_PACKET_TIMEOUT_MS) { 800cd18: 683b ldr r3, [r7, #0] 800cd1a: f241 3287 movw r2, #4999 @ 0x1387 800cd1e: 4293 cmp r3, r2 800cd20: d90c bls.n 800cd3c if (sc_uart2_timed_out == 0u) { 800cd22: 4b24 ldr r3, [pc, #144] @ (800cdb4 ) 800cd24: 781b ldrb r3, [r3, #0] 800cd26: b2db uxtb r3, r3 800cd28: 2b00 cmp r3, #0 800cd2a: d103 bne.n 800cd34 serial_control.command_ready = 0; 800cd2c: 4b1e ldr r3, [pc, #120] @ (800cda8 ) 800cd2e: 2200 movs r2, #0 800cd30: f883 2208 strb.w r2, [r3, #520] @ 0x208 } sc_uart2_timed_out = 1; 800cd34: 4b1f ldr r3, [pc, #124] @ (800cdb4 ) 800cd36: 2201 movs r2, #1 800cd38: 701a strb r2, [r3, #0] 800cd3a: e002 b.n 800cd42 } else { sc_uart2_timed_out = 0; 800cd3c: 4b1d ldr r3, [pc, #116] @ (800cdb4 ) 800cd3e: 2200 movs r2, #0 800cd40: 701a strb r2, [r3, #0] } if ((since_last_packet >= SC_UART2_REINIT_TIMEOUT_MS) && 800cd42: 683b ldr r3, [r7, #0] 800cd44: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800cd48: d320 bcc.n 800cd8c ((now - sc_uart2_last_reinit_tick) >= SC_UART2_REINIT_TIMEOUT_MS)) { 800cd4a: 4b18 ldr r3, [pc, #96] @ (800cdac ) 800cd4c: 681b ldr r3, [r3, #0] 800cd4e: 687a ldr r2, [r7, #4] 800cd50: 1ad3 subs r3, r2, r3 if ((since_last_packet >= SC_UART2_REINIT_TIMEOUT_MS) && 800cd52: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800cd56: d319 bcc.n 800cd8c HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800cd58: 2200 movs r2, #0 800cd5a: 2110 movs r1, #16 800cd5c: 4810 ldr r0, [pc, #64] @ (800cda0 ) 800cd5e: f003 fdd4 bl 801090a (void)HAL_UART_Abort_IT(&huart2); 800cd62: 480d ldr r0, [pc, #52] @ (800cd98 ) 800cd64: f006 f8fa bl 8012f5c (void)HAL_UART_DeInit(&huart2); 800cd68: 480b ldr r0, [pc, #44] @ (800cd98 ) 800cd6a: f006 f833 bl 8012dd4 (void)HAL_UART_Init(&huart2); 800cd6e: 480a ldr r0, [pc, #40] @ (800cd98 ) 800cd70: f005 ffe0 bl 8012d34 (void)HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800cd74: 22ff movs r2, #255 @ 0xff 800cd76: 490b ldr r1, [pc, #44] @ (800cda4 ) 800cd78: 4807 ldr r0, [pc, #28] @ (800cd98 ) 800cd7a: f006 f892 bl 8012ea2 sc_uart2_last_reinit_tick = now; 800cd7e: 4a0b ldr r2, [pc, #44] @ (800cdac ) 800cd80: 687b ldr r3, [r7, #4] 800cd82: 6013 str r3, [r2, #0] log_printf(LOG_ERR, "USART2 stalled: hard reinit\n"); 800cd84: 490c ldr r1, [pc, #48] @ (800cdb8 ) 800cd86: 2004 movs r0, #4 800cd88: f7fd fbaa bl 800a4e0 } } 800cd8c: 3708 adds r7, #8 800cd8e: 46bd mov sp, r7 800cd90: bd80 pop {r7, pc} 800cd92: bf00 nop 800cd94: 2000104c .word 0x2000104c 800cd98: 200011e0 .word 0x200011e0 800cd9c: 20001054 .word 0x20001054 800cda0: 40011400 .word 0x40011400 800cda4: 20000d28 .word 0x20000d28 800cda8: 20000c28 .word 0x20000c28 800cdac: 20001050 .word 0x20001050 800cdb0: 08017194 .word 0x08017194 800cdb4: 20001049 .word 0x20001049 800cdb8: 080171b4 .word 0x080171b4 0800cdbc <__NVIC_SystemReset>: { 800cdbc: b480 push {r7} 800cdbe: af00 add r7, sp, #0 __ASM volatile ("dsb 0xF":::"memory"); 800cdc0: f3bf 8f4f dsb sy } 800cdc4: bf00 nop (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800cdc6: 4b06 ldr r3, [pc, #24] @ (800cde0 <__NVIC_SystemReset+0x24>) 800cdc8: 68db ldr r3, [r3, #12] 800cdca: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800cdce: 4904 ldr r1, [pc, #16] @ (800cde0 <__NVIC_SystemReset+0x24>) 800cdd0: 4b04 ldr r3, [pc, #16] @ (800cde4 <__NVIC_SystemReset+0x28>) 800cdd2: 4313 orrs r3, r2 800cdd4: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800cdd6: f3bf 8f4f dsb sy } 800cdda: bf00 nop __NOP(); 800cddc: bf00 nop 800cdde: e7fd b.n 800cddc <__NVIC_SystemReset+0x20> 800cde0: e000ed00 .word 0xe000ed00 800cde4: 05fa0004 .word 0x05fa0004 0800cde8 : .chargerNumber = 00001, .unixTime = 1721651966, }; // Единая функция-обработчик всех команд со switch-case void SC_CommandHandler(ReceivedCommand_t* cmd) { 800cde8: b580 push {r7, lr} 800cdea: b084 sub sp, #16 800cdec: af00 add r7, sp, #0 800cdee: 6078 str r0, [r7, #4] uint8_t response_code = RESP_FAILED; 800cdf0: 2313 movs r3, #19 800cdf2: 73fb strb r3, [r7, #15] switch (cmd->command) { 800cdf4: 687b ldr r3, [r7, #4] 800cdf6: 781b ldrb r3, [r3, #0] 800cdf8: 2bc2 cmp r3, #194 @ 0xc2 800cdfa: f300 80cc bgt.w 800cf96 800cdfe: 2bb0 cmp r3, #176 @ 0xb0 800ce00: da0f bge.n 800ce22 800ce02: 2b60 cmp r3, #96 @ 0x60 800ce04: d042 beq.n 800ce8c 800ce06: 2b60 cmp r3, #96 @ 0x60 800ce08: f300 80c5 bgt.w 800cf96 800ce0c: 2b50 cmp r3, #80 @ 0x50 800ce0e: d043 beq.n 800ce98 800ce10: 2b50 cmp r3, #80 @ 0x50 800ce12: f300 80c0 bgt.w 800cf96 800ce16: 2b01 cmp r3, #1 800ce18: f000 80a6 beq.w 800cf68 800ce1c: 2b40 cmp r3, #64 @ 0x40 800ce1e: d02d beq.n 800ce7c 800ce20: e0b9 b.n 800cf96 800ce22: 3bb0 subs r3, #176 @ 0xb0 800ce24: 2b12 cmp r3, #18 800ce26: f200 80b6 bhi.w 800cf96 800ce2a: a201 add r2, pc, #4 @ (adr r2, 800ce30 ) 800ce2c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ce30: 0800ce9f .word 0x0800ce9f 800ce34: 0800cf97 .word 0x0800cf97 800ce38: 0800cf97 .word 0x0800cf97 800ce3c: 0800cf97 .word 0x0800cf97 800ce40: 0800cf97 .word 0x0800cf97 800ce44: 0800cf47 .word 0x0800cf47 800ce48: 0800cf97 .word 0x0800cf97 800ce4c: 0800cf97 .word 0x0800cf97 800ce50: 0800cf97 .word 0x0800cf97 800ce54: 0800cf97 .word 0x0800cf97 800ce58: 0800cf97 .word 0x0800cf97 800ce5c: 0800cf97 .word 0x0800cf97 800ce60: 0800cf97 .word 0x0800cf97 800ce64: 0800cf97 .word 0x0800cf97 800ce68: 0800cf97 .word 0x0800cf97 800ce6c: 0800cf97 .word 0x0800cf97 800ce70: 0800cedd .word 0x0800cedd 800ce74: 0800cf41 .word 0x0800cf41 800ce78: 0800cf15 .word 0x0800cf15 // Команды БЕЗ аргументов case CMD_GET_STATUS: // Логика получения информации monitoring_data_callback(); 800ce7c: f000 f8b2 bl 800cfe4 // Отправляем с нормальным приоритетом SC_SendPacket((uint8_t*)&statusPacket, sizeof(statusPacket), CMD_GET_STATUS); 800ce80: 2240 movs r2, #64 @ 0x40 800ce82: 2158 movs r1, #88 @ 0x58 800ce84: 484b ldr r0, [pc, #300] @ (800cfb4 ) 800ce86: f7ff fea7 bl 800cbd8 return; // Специальный ответ уже отправлен 800ce8a: e08f b.n 800cfac case CMD_GET_INFO: SC_SendPacket((uint8_t*)&infoPacket, sizeof(infoPacket), CMD_GET_INFO); 800ce8c: 2260 movs r2, #96 @ 0x60 800ce8e: 210a movs r1, #10 800ce90: 4849 ldr r0, [pc, #292] @ (800cfb8 ) 800ce92: f7ff fea1 bl 800cbd8 return; 800ce96: e089 b.n 800cfac case CMD_GET_LOG: debug_buffer_send(); 800ce98: f7fd fac0 bl 800a41c return; // Ответ формируется внутри debug_buffer_send 800ce9c: e086 b.n 800cfac // Команды С аргументами case CMD_SET_CONFIG: if (cmd->argument_length == sizeof(ConfigBlock_t)) { 800ce9e: 687b ldr r3, [r7, #4] 800cea0: 785b ldrb r3, [r3, #1] 800cea2: 2b0b cmp r3, #11 800cea4: d117 bne.n 800ced6 memcpy(&config, cmd->argument, sizeof(ConfigBlock_t)); 800cea6: 687b ldr r3, [r7, #4] 800cea8: 685a ldr r2, [r3, #4] 800ceaa: 4b44 ldr r3, [pc, #272] @ (800cfbc ) 800ceac: 6810 ldr r0, [r2, #0] 800ceae: 6851 ldr r1, [r2, #4] 800ceb0: c303 stmia r3!, {r0, r1} 800ceb2: 8911 ldrh r1, [r2, #8] 800ceb4: 7a92 ldrb r2, [r2, #10] 800ceb6: 8019 strh r1, [r3, #0] 800ceb8: 709a strb r2, [r3, #2] config_initialized = 1; 800ceba: 4b41 ldr r3, [pc, #260] @ (800cfc0 ) 800cebc: 2201 movs r2, #1 800cebe: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Set Config: %s %d\n", config.location, config.chargerNumber); 800cec0: 4b3e ldr r3, [pc, #248] @ (800cfbc ) 800cec2: f8d3 3003 ldr.w r3, [r3, #3] 800cec6: 4a3d ldr r2, [pc, #244] @ (800cfbc ) 800cec8: 493e ldr r1, [pc, #248] @ (800cfc4 ) 800ceca: 2007 movs r0, #7 800cecc: f7fd fb08 bl 800a4e0 response_code = RESP_SUCCESS; 800ced0: 2312 movs r3, #18 800ced2: 73fb strb r3, [r7, #15] break; 800ced4: e062 b.n 800cf9c } response_code = RESP_FAILED; 800ced6: 2313 movs r3, #19 800ced8: 73fb strb r3, [r7, #15] break; 800ceda: e05f b.n 800cf9c case CMD_SET_POWER_LIMIT: if (cmd->argument_length == 1) { 800cedc: 687b ldr r3, [r7, #4] 800cede: 785b ldrb r3, [r3, #1] 800cee0: 2b01 cmp r3, #1 800cee2: d114 bne.n 800cf0e PSU0.power_limit = ((uint8_t*)cmd->argument)[0] * 1000; 800cee4: 687b ldr r3, [r7, #4] 800cee6: 685b ldr r3, [r3, #4] 800cee8: 781b ldrb r3, [r3, #0] 800ceea: 461a mov r2, r3 800ceec: f44f 737a mov.w r3, #1000 @ 0x3e8 800cef0: fb02 f303 mul.w r3, r2, r3 800cef4: 461a mov r2, r3 800cef6: 4b34 ldr r3, [pc, #208] @ (800cfc8 ) 800cef8: 615a str r2, [r3, #20] log_printf(LOG_INFO, "Power limit: %d\n", PSU0.power_limit); 800cefa: 4b33 ldr r3, [pc, #204] @ (800cfc8 ) 800cefc: 695b ldr r3, [r3, #20] 800cefe: 461a mov r2, r3 800cf00: 4932 ldr r1, [pc, #200] @ (800cfcc ) 800cf02: 2007 movs r0, #7 800cf04: f7fd faec bl 800a4e0 //CONN.connState = (((uint8_t*)cmd->argument)[0])/4; response_code = RESP_SUCCESS; 800cf08: 2312 movs r3, #18 800cf0a: 73fb strb r3, [r7, #15] break; 800cf0c: e046 b.n 800cf9c } response_code = RESP_FAILED; 800cf0e: 2313 movs r3, #19 800cf10: 73fb strb r3, [r7, #15] break; 800cf12: e043 b.n 800cf9c case CMD_CHARGE_PERMIT: if (cmd->argument_length == 1) { 800cf14: 687b ldr r3, [r7, #4] 800cf16: 785b ldrb r3, [r3, #1] 800cf18: 2b01 cmp r3, #1 800cf1a: d10e bne.n 800cf3a CONN.connControl = ((uint8_t*)cmd->argument)[0]; 800cf1c: 687b ldr r3, [r7, #4] 800cf1e: 685b ldr r3, [r3, #4] 800cf20: 781a ldrb r2, [r3, #0] 800cf22: 4b2b ldr r3, [pc, #172] @ (800cfd0 ) 800cf24: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Charge permit: %d\n", CONN.connControl); 800cf26: 4b2a ldr r3, [pc, #168] @ (800cfd0 ) 800cf28: 781b ldrb r3, [r3, #0] 800cf2a: 461a mov r2, r3 800cf2c: 4929 ldr r1, [pc, #164] @ (800cfd4 ) 800cf2e: 2007 movs r0, #7 800cf30: f7fd fad6 bl 800a4e0 response_code = RESP_SUCCESS; 800cf34: 2312 movs r3, #18 800cf36: 73fb strb r3, [r7, #15] break; 800cf38: e030 b.n 800cf9c } response_code = RESP_FAILED; 800cf3a: 2313 movs r3, #19 800cf3c: 73fb strb r3, [r7, #15] break; 800cf3e: e02d b.n 800cf9c // memcpy(&PSU_TestMode, cmd->argument, sizeof(PSU_TestMode_t)); // log_printf(LOG_INFO, "Test PSU: %d %d %d\n", PSU_TestMode.enable, PSU_TestMode.voltage, PSU_TestMode.current); // response_code = RESP_SUCCESS; // break; // } response_code = RESP_FAILED; 800cf40: 2313 movs r3, #19 800cf42: 73fb strb r3, [r7, #15] break; 800cf44: e02a b.n 800cf9c case CMD_DEVICE_RESET: // 2. Отправляем SUCCESS (хост может успеть получить его перед ребутом) SC_SendPacket(NULL, 0, RESP_SUCCESS); 800cf46: 2212 movs r2, #18 800cf48: 2100 movs r1, #0 800cf4a: 2000 movs r0, #0 800cf4c: f7ff fe44 bl 800cbd8 while(huart2.gState == HAL_UART_STATE_BUSY_TX); // Ожидание завершения передачи 800cf50: bf00 nop 800cf52: 4b21 ldr r3, [pc, #132] @ (800cfd8 ) 800cf54: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800cf58: b2db uxtb r3, r3 800cf5a: 2b21 cmp r3, #33 @ 0x21 800cf5c: d0f9 beq.n 800cf52 HAL_Delay(10); 800cf5e: 200a movs r0, #10 800cf60: f001 f862 bl 800e028 // 3. Выполняем программный сброс NVIC_SystemReset(); 800cf64: f7ff ff2a bl 800cdbc <__NVIC_SystemReset> return; // Сюда код уже не дойдет, но для компилятора нxужно case CMD_ISOLATION_STATUS: if (cmd->argument_length == sizeof(IsolationStatusPacket_t)) { 800cf68: 687b ldr r3, [r7, #4] 800cf6a: 785b ldrb r3, [r3, #1] 800cf6c: 2b09 cmp r3, #9 800cf6e: d10f bne.n 800cf90 memcpy(&ISO, cmd->argument, sizeof(IsolationStatusPacket_t)); 800cf70: 687b ldr r3, [r7, #4] 800cf72: 685a ldr r2, [r3, #4] 800cf74: 4b19 ldr r3, [pc, #100] @ (800cfdc ) 800cf76: 6810 ldr r0, [r2, #0] 800cf78: 6851 ldr r1, [r2, #4] 800cf7a: c303 stmia r3!, {r0, r1} 800cf7c: 7a12 ldrb r2, [r2, #8] 800cf7e: 701a strb r2, [r3, #0] // Для однонаправленного UART5 ответ не нужен if (g_sc_command_source == SC_SOURCE_UART5) { 800cf80: 4b17 ldr r3, [pc, #92] @ (800cfe0 ) 800cf82: 781b ldrb r3, [r3, #0] 800cf84: b2db uxtb r3, r3 800cf86: 2b01 cmp r3, #1 800cf88: d00f beq.n 800cfaa return; } response_code = RESP_SUCCESS; 800cf8a: 2312 movs r3, #18 800cf8c: 73fb strb r3, [r7, #15] break; 800cf8e: e005 b.n 800cf9c } response_code = RESP_FAILED; 800cf90: 2313 movs r3, #19 800cf92: 73fb strb r3, [r7, #15] break; 800cf94: e002 b.n 800cf9c default: // Неизвестная команда response_code = RESP_FAILED; 800cf96: 2313 movs r3, #19 800cf98: 73fb strb r3, [r7, #15] break; 800cf9a: bf00 nop } // Отправляем финальный ответ (для команд без собственного ответа) SC_SendPacket(NULL, 0, response_code); 800cf9c: 7bfb ldrb r3, [r7, #15] 800cf9e: 461a mov r2, r3 800cfa0: 2100 movs r1, #0 800cfa2: 2000 movs r0, #0 800cfa4: f7ff fe18 bl 800cbd8 800cfa8: e000 b.n 800cfac return; 800cfaa: bf00 nop } 800cfac: 3710 adds r7, #16 800cfae: 46bd mov sp, r7 800cfb0: bd80 pop {r7, pc} 800cfb2: bf00 nop 800cfb4: 20001058 .word 0x20001058 800cfb8: 200010b0 .word 0x200010b0 800cfbc: 20000078 .word 0x20000078 800cfc0: 200010ba .word 0x200010ba 800cfc4: 080171d4 .word 0x080171d4 800cfc8: 20000904 .word 0x20000904 800cfcc: 080171e8 .word 0x080171e8 800cfd0: 200003b0 .word 0x200003b0 800cfd4: 080171fc .word 0x080171fc 800cfd8: 200011e0 .word 0x200011e0 800cfdc: 2000006c .word 0x2000006c 800cfe0: 20001048 .word 0x20001048 0800cfe4 : // Колбэк для заполнения данных мониторинга void monitoring_data_callback() { 800cfe4: b580 push {r7, lr} 800cfe6: af00 add r7, sp, #0 // Информация о зарядной сессии statusPacket.SOC = CONN.SOC; 800cfe8: 4b8f ldr r3, [pc, #572] @ (800d228 ) 800cfea: 789a ldrb r2, [r3, #2] 800cfec: 4b8f ldr r3, [pc, #572] @ (800d22c ) 800cfee: 709a strb r2, [r3, #2] statusPacket.Energy = CONN.Energy; 800cff0: 4b8d ldr r3, [pc, #564] @ (800d228 ) 800cff2: f8d3 3007 ldr.w r3, [r3, #7] 800cff6: 4a8d ldr r2, [pc, #564] @ (800d22c ) 800cff8: f8c2 3003 str.w r3, [r2, #3] statusPacket.RequestedVoltage = CONN.RequestedVoltage; 800cffc: 4b8a ldr r3, [pc, #552] @ (800d228 ) 800cffe: f8b3 300f ldrh.w r3, [r3, #15] 800d002: b29a uxth r2, r3 800d004: 4b89 ldr r3, [pc, #548] @ (800d22c ) 800d006: f8a3 2007 strh.w r2, [r3, #7] statusPacket.RequestedCurrent = CONN.WantedCurrent; 800d00a: 4b87 ldr r3, [pc, #540] @ (800d228 ) 800d00c: f8b3 301b ldrh.w r3, [r3, #27] 800d010: b29a uxth r2, r3 800d012: 4b86 ldr r3, [pc, #536] @ (800d22c ) 800d014: f8a3 2009 strh.w r2, [r3, #9] statusPacket.MeasuredVoltage = CONN.MeasuredVoltage; 800d018: 4b83 ldr r3, [pc, #524] @ (800d228 ) 800d01a: f8b3 3013 ldrh.w r3, [r3, #19] 800d01e: b29a uxth r2, r3 800d020: 4b82 ldr r3, [pc, #520] @ (800d22c ) 800d022: f8a3 200b strh.w r2, [r3, #11] statusPacket.MeasuredCurrent = CONN.MeasuredCurrent; 800d026: 4b80 ldr r3, [pc, #512] @ (800d228 ) 800d028: f8b3 3015 ldrh.w r3, [r3, #21] 800d02c: b29a uxth r2, r3 800d02e: 4b7f ldr r3, [pc, #508] @ (800d22c ) 800d030: f8a3 200d strh.w r2, [r3, #13] statusPacket.outputEnabled = CONN.outputEnabled; 800d034: 4b7c ldr r3, [pc, #496] @ (800d228 ) 800d036: 7e1a ldrb r2, [r3, #24] 800d038: 4b7c ldr r3, [pc, #496] @ (800d22c ) 800d03a: 73da strb r2, [r3, #15] statusPacket.chargingError = CONN.chargingError; 800d03c: 4b7a ldr r3, [pc, #488] @ (800d228 ) 800d03e: 7f5a ldrb r2, [r3, #29] 800d040: 4b7a ldr r3, [pc, #488] @ (800d22c ) 800d042: 705a strb r2, [r3, #1] statusPacket.connState = CONN.connState; 800d044: 4b78 ldr r3, [pc, #480] @ (800d228 ) 800d046: 785a ldrb r2, [r3, #1] 800d048: 4b78 ldr r3, [pc, #480] @ (800d22c ) 800d04a: 701a strb r2, [r3, #0] statusPacket.chargingElapsedTimeMin = 0; 800d04c: 4b77 ldr r3, [pc, #476] @ (800d22c ) 800d04e: 2200 movs r2, #0 800d050: 741a strb r2, [r3, #16] 800d052: 2200 movs r2, #0 800d054: 745a strb r2, [r3, #17] statusPacket.chargingElapsedTimeSec = 0; 800d056: 4b75 ldr r3, [pc, #468] @ (800d22c ) 800d058: 2200 movs r2, #0 800d05a: 749a strb r2, [r3, #18] statusPacket.estimatedRemainingChargingTime = 0; 800d05c: 4b73 ldr r3, [pc, #460] @ (800d22c ) 800d05e: 2200 movs r2, #0 800d060: 74da strb r2, [r3, #19] 800d062: 2200 movs r2, #0 800d064: 751a strb r2, [r3, #20] // состояние зарядной станции statusPacket.relayAC = RELAY_Read(RELAY_AC); 800d066: 2004 movs r0, #4 800d068: f7fc fc16 bl 8009898 800d06c: 4603 mov r3, r0 800d06e: f003 0301 and.w r3, r3, #1 800d072: b2d9 uxtb r1, r3 800d074: 4a6d ldr r2, [pc, #436] @ (800d22c ) 800d076: 7d53 ldrb r3, [r2, #21] 800d078: f361 0300 bfi r3, r1, #0, #1 800d07c: 7553 strb r3, [r2, #21] statusPacket.relayDC = RELAY_Read(RELAY_DC); 800d07e: 2003 movs r0, #3 800d080: f7fc fc0a bl 8009898 800d084: 4603 mov r3, r0 800d086: f003 0301 and.w r3, r3, #1 800d08a: b2d9 uxtb r1, r3 800d08c: 4a67 ldr r2, [pc, #412] @ (800d22c ) 800d08e: 7d53 ldrb r3, [r2, #21] 800d090: f361 0341 bfi r3, r1, #1, #1 800d094: 7553 strb r3, [r2, #21] statusPacket.relayAUX = RELAY_Read(RELAY_AUX0); 800d096: 2000 movs r0, #0 800d098: f7fc fbfe bl 8009898 800d09c: 4603 mov r3, r0 800d09e: f003 0301 and.w r3, r3, #1 800d0a2: b2d9 uxtb r1, r3 800d0a4: 4a61 ldr r2, [pc, #388] @ (800d22c ) 800d0a6: 7d53 ldrb r3, [r2, #21] 800d0a8: f361 0382 bfi r3, r1, #2, #1 800d0ac: 7553 strb r3, [r2, #21] statusPacket.lockState = 0; 800d0ae: 4a5f ldr r2, [pc, #380] @ (800d22c ) 800d0b0: 7d53 ldrb r3, [r2, #21] 800d0b2: f023 0308 bic.w r3, r3, #8 800d0b6: 7553 strb r3, [r2, #21] statusPacket.stopButton = !IN_ReadInput(IN_ESTOP); 800d0b8: 2003 movs r0, #3 800d0ba: f7fc fbfd bl 80098b8 800d0be: 4603 mov r3, r0 800d0c0: 2b00 cmp r3, #0 800d0c2: bf0c ite eq 800d0c4: 2301 moveq r3, #1 800d0c6: 2300 movne r3, #0 800d0c8: b2d9 uxtb r1, r3 800d0ca: 4a58 ldr r2, [pc, #352] @ (800d22c ) 800d0cc: 7d53 ldrb r3, [r2, #21] 800d0ce: f361 1304 bfi r3, r1, #4, #1 800d0d2: 7553 strb r3, [r2, #21] statusPacket.logAvailable = (debug_buffer_available()>0)?1:0; 800d0d4: f7fd f98e bl 800a3f4 800d0d8: 4603 mov r3, r0 800d0da: 2b00 cmp r3, #0 800d0dc: bf14 ite ne 800d0de: 2301 movne r3, #1 800d0e0: 2300 moveq r3, #0 800d0e2: b2d9 uxtb r1, r3 800d0e4: 4a51 ldr r2, [pc, #324] @ (800d22c ) 800d0e6: 7d53 ldrb r3, [r2, #21] 800d0e8: f361 1345 bfi r3, r1, #5, #1 800d0ec: 7553 strb r3, [r2, #21] statusPacket.evInfoAvailable = 0; 800d0ee: 4a4f ldr r2, [pc, #316] @ (800d22c ) 800d0f0: 7d53 ldrb r3, [r2, #21] 800d0f2: f023 0340 bic.w r3, r3, #64 @ 0x40 800d0f6: 7553 strb r3, [r2, #21] statusPacket.psuOnline = PSU0.online; 800d0f8: 4b4d ldr r3, [pc, #308] @ (800d230 ) 800d0fa: 7a1b ldrb r3, [r3, #8] 800d0fc: f003 0301 and.w r3, r3, #1 800d100: b2d9 uxtb r1, r3 800d102: 4a4a ldr r2, [pc, #296] @ (800d22c ) 800d104: 7d53 ldrb r3, [r2, #21] 800d106: f361 13c7 bfi r3, r1, #7, #1 800d10a: 7553 strb r3, [r2, #21] statusPacket.tempConnector0 = CONN_ReadTemp(0); // температура коннектора 800d10c: 2000 movs r0, #0 800d10e: f7fc fcc9 bl 8009aa4 800d112: 4603 mov r3, r0 800d114: b25a sxtb r2, r3 800d116: 4b45 ldr r3, [pc, #276] @ (800d22c ) 800d118: 765a strb r2, [r3, #25] statusPacket.tempConnector1 = CONN_ReadTemp(1); 800d11a: 2001 movs r0, #1 800d11c: f7fc fcc2 bl 8009aa4 800d120: 4603 mov r3, r0 800d122: b25a sxtb r2, r3 800d124: 4b41 ldr r3, [pc, #260] @ (800d22c ) 800d126: 769a strb r2, [r3, #26] statusPacket.tempAmbient = PSU0.tempAmbient; // температура окружающего воздуха 800d128: 4b41 ldr r3, [pc, #260] @ (800d230 ) 800d12a: 6a1b ldr r3, [r3, #32] 800d12c: b25a sxtb r2, r3 800d12e: 4b3f ldr r3, [pc, #252] @ (800d22c ) 800d130: 76da strb r2, [r3, #27] statusPacket.tempBatteryMax = 0; 800d132: 4b3e ldr r3, [pc, #248] @ (800d22c ) 800d134: 2200 movs r2, #0 800d136: 771a strb r2, [r3, #28] statusPacket.tempBatteryMin = 0; 800d138: 4b3c ldr r3, [pc, #240] @ (800d22c ) 800d13a: 2200 movs r2, #0 800d13c: 775a strb r2, [r3, #29] statusPacket.highestVoltageOfBatteryCell = 0; 800d13e: 4b3b ldr r3, [pc, #236] @ (800d22c ) 800d140: 2200 movs r2, #0 800d142: 779a strb r2, [r3, #30] 800d144: 2200 movs r2, #0 800d146: 77da strb r2, [r3, #31] statusPacket.batteryStatus = 0; 800d148: 4b38 ldr r3, [pc, #224] @ (800d22c ) 800d14a: 2200 movs r2, #0 800d14c: f883 2020 strb.w r2, [r3, #32] statusPacket.phaseVoltageAB = PSU_06.VAB; 800d150: 4b38 ldr r3, [pc, #224] @ (800d234 ) 800d152: 689b ldr r3, [r3, #8] 800d154: b29a uxth r2, r3 800d156: 4b35 ldr r3, [pc, #212] @ (800d22c ) 800d158: f8a3 2021 strh.w r2, [r3, #33] @ 0x21 statusPacket.phaseVoltageBC = PSU_06.VBC; 800d15c: 4b35 ldr r3, [pc, #212] @ (800d234 ) 800d15e: 68db ldr r3, [r3, #12] 800d160: b29a uxth r2, r3 800d162: 4b32 ldr r3, [pc, #200] @ (800d22c ) 800d164: f8a3 2023 strh.w r2, [r3, #35] @ 0x23 statusPacket.phaseVoltageCA = PSU_06.VCA; 800d168: 4b32 ldr r3, [pc, #200] @ (800d234 ) 800d16a: 691b ldr r3, [r3, #16] 800d16c: b29a uxth r2, r3 800d16e: 4b2f ldr r3, [pc, #188] @ (800d22c ) 800d170: f8a3 2025 strh.w r2, [r3, #37] @ 0x25 // GBT TODO memset(statusPacket.VIN, 0, sizeof(statusPacket.VIN)); 800d174: 2211 movs r2, #17 800d176: 2100 movs r1, #0 800d178: 482f ldr r0, [pc, #188] @ (800d238 ) 800d17a: f007 fadf bl 801473c // GBT TODO statusPacket.batteryType = 0; 800d17e: 4b2b ldr r3, [pc, #172] @ (800d22c ) 800d180: 2200 movs r2, #0 800d182: f883 2038 strb.w r2, [r3, #56] @ 0x38 statusPacket.batteryCapacity = 0; 800d186: 4b29 ldr r3, [pc, #164] @ (800d22c ) 800d188: 2200 movs r2, #0 800d18a: f883 2039 strb.w r2, [r3, #57] @ 0x39 800d18e: 2200 movs r2, #0 800d190: f883 203a strb.w r2, [r3, #58] @ 0x3a statusPacket.batteryVoltage = 0; 800d194: 4b25 ldr r3, [pc, #148] @ (800d22c ) 800d196: 2200 movs r2, #0 800d198: f883 203b strb.w r2, [r3, #59] @ 0x3b 800d19c: 2200 movs r2, #0 800d19e: f883 203c strb.w r2, [r3, #60] @ 0x3c memset(statusPacket.batteryVendor, 0, sizeof(statusPacket.batteryVendor)); 800d1a2: 2204 movs r2, #4 800d1a4: 2100 movs r1, #0 800d1a6: 4825 ldr r0, [pc, #148] @ (800d23c ) 800d1a8: f007 fac8 bl 801473c statusPacket.batterySN = 0; 800d1ac: 4b1f ldr r3, [pc, #124] @ (800d22c ) 800d1ae: 2200 movs r2, #0 800d1b0: f883 2041 strb.w r2, [r3, #65] @ 0x41 800d1b4: 2200 movs r2, #0 800d1b6: f883 2042 strb.w r2, [r3, #66] @ 0x42 800d1ba: 2200 movs r2, #0 800d1bc: f883 2043 strb.w r2, [r3, #67] @ 0x43 800d1c0: 2200 movs r2, #0 800d1c2: f883 2044 strb.w r2, [r3, #68] @ 0x44 statusPacket.batteryManuD = 0; 800d1c6: 4b19 ldr r3, [pc, #100] @ (800d22c ) 800d1c8: 2200 movs r2, #0 800d1ca: f883 2047 strb.w r2, [r3, #71] @ 0x47 statusPacket.batteryManuM = 0; 800d1ce: 4b17 ldr r3, [pc, #92] @ (800d22c ) 800d1d0: 2200 movs r2, #0 800d1d2: f883 2046 strb.w r2, [r3, #70] @ 0x46 statusPacket.batteryManuY = 0; 800d1d6: 4b15 ldr r3, [pc, #84] @ (800d22c ) 800d1d8: 2200 movs r2, #0 800d1da: f883 2045 strb.w r2, [r3, #69] @ 0x45 statusPacket.batteryCycleCount = 0; 800d1de: 4b13 ldr r3, [pc, #76] @ (800d22c ) 800d1e0: 2200 movs r2, #0 800d1e2: f883 2048 strb.w r2, [r3, #72] @ 0x48 800d1e6: 2200 movs r2, #0 800d1e8: f883 2049 strb.w r2, [r3, #73] @ 0x49 statusPacket.ownAuto = 0; 800d1ec: 4b0f ldr r3, [pc, #60] @ (800d22c ) 800d1ee: 2200 movs r2, #0 800d1f0: f883 204a strb.w r2, [r3, #74] @ 0x4a memset(statusPacket.EV_SW_VER, 0, sizeof(statusPacket.EV_SW_VER)); 800d1f4: 2208 movs r2, #8 800d1f6: 2100 movs r1, #0 800d1f8: 4811 ldr r0, [pc, #68] @ (800d240 ) 800d1fa: f007 fa9f bl 801473c statusPacket.testMode = 0; 800d1fe: 4b0b ldr r3, [pc, #44] @ (800d22c ) 800d200: 2200 movs r2, #0 800d202: f883 2053 strb.w r2, [r3, #83] @ 0x53 statusPacket.testVoltage = 0; 800d206: 4b09 ldr r3, [pc, #36] @ (800d22c ) 800d208: 2200 movs r2, #0 800d20a: f883 2054 strb.w r2, [r3, #84] @ 0x54 800d20e: 2200 movs r2, #0 800d210: f883 2055 strb.w r2, [r3, #85] @ 0x55 statusPacket.testCurrent = 0; 800d214: 4b05 ldr r3, [pc, #20] @ (800d22c ) 800d216: 2200 movs r2, #0 800d218: f883 2056 strb.w r2, [r3, #86] @ 0x56 800d21c: 2200 movs r2, #0 800d21e: f883 2057 strb.w r2, [r3, #87] @ 0x57 // В debug.c есть CONN_SetState, предполагаем наличие CONN_GetState() // Если такой функции нет, закомментируйте следующую строку: // statusPacket.connState = CONN_GetState(); } 800d222: bf00 nop 800d224: bd80 pop {r7, pc} 800d226: bf00 nop 800d228: 200003b0 .word 0x200003b0 800d22c: 20001058 .word 0x20001058 800d230: 20000904 .word 0x20000904 800d234: 200008d8 .word 0x200008d8 800d238: 2000107f .word 0x2000107f 800d23c: 20001095 .word 0x20001095 800d240: 200010a3 .word 0x200010a3 0800d244 : #include "sma_filter.h" void SMAFilter_Init(SMAFilter_t* f) { 800d244: b480 push {r7} 800d246: b085 sub sp, #20 800d248: af00 add r7, sp, #0 800d24a: 6078 str r0, [r7, #4] if (f == 0) return; 800d24c: 687b ldr r3, [r7, #4] 800d24e: 2b00 cmp r3, #0 800d250: d018 beq.n 800d284 f->sum = 0; 800d252: 687b ldr r3, [r7, #4] 800d254: 2200 movs r2, #0 800d256: 601a str r2, [r3, #0] f->idx = 0; 800d258: 687b ldr r3, [r7, #4] 800d25a: 2200 movs r2, #0 800d25c: 809a strh r2, [r3, #4] f->count = 0; 800d25e: 687b ldr r3, [r7, #4] 800d260: 2200 movs r2, #0 800d262: 80da strh r2, [r3, #6] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800d264: 2300 movs r3, #0 800d266: 81fb strh r3, [r7, #14] 800d268: e008 b.n 800d27c f->buffer[i] = 0; 800d26a: 89fa ldrh r2, [r7, #14] 800d26c: 687b ldr r3, [r7, #4] 800d26e: 3202 adds r2, #2 800d270: 2100 movs r1, #0 800d272: f843 1022 str.w r1, [r3, r2, lsl #2] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800d276: 89fb ldrh r3, [r7, #14] 800d278: 3301 adds r3, #1 800d27a: 81fb strh r3, [r7, #14] 800d27c: 89fb ldrh r3, [r7, #14] 800d27e: 2b07 cmp r3, #7 800d280: d9f3 bls.n 800d26a 800d282: e000 b.n 800d286 if (f == 0) return; 800d284: bf00 nop } } 800d286: 3714 adds r7, #20 800d288: 46bd mov sp, r7 800d28a: bc80 pop {r7} 800d28c: 4770 bx lr 0800d28e : int32_t SMAFilter_Update(SMAFilter_t* f, int32_t x) { 800d28e: b480 push {r7} 800d290: b085 sub sp, #20 800d292: af00 add r7, sp, #0 800d294: 6078 str r0, [r7, #4] 800d296: 6039 str r1, [r7, #0] if (f == 0) return x; 800d298: 687b ldr r3, [r7, #4] 800d29a: 2b00 cmp r3, #0 800d29c: d101 bne.n 800d2a2 800d29e: 683b ldr r3, [r7, #0] 800d2a0: e056 b.n 800d350 // Пока окно не заполнено полностью, делим по фактическому count. if (f->count < SMA_FILTER_WINDOW) { 800d2a2: 687b ldr r3, [r7, #4] 800d2a4: 88db ldrh r3, [r3, #6] 800d2a6: 2b07 cmp r3, #7 800d2a8: d827 bhi.n 800d2fa f->buffer[f->idx] = x; 800d2aa: 687b ldr r3, [r7, #4] 800d2ac: 889b ldrh r3, [r3, #4] 800d2ae: 461a mov r2, r3 800d2b0: 687b ldr r3, [r7, #4] 800d2b2: 3202 adds r2, #2 800d2b4: 6839 ldr r1, [r7, #0] 800d2b6: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += x; 800d2ba: 687b ldr r3, [r7, #4] 800d2bc: 681a ldr r2, [r3, #0] 800d2be: 683b ldr r3, [r7, #0] 800d2c0: 441a add r2, r3 800d2c2: 687b ldr r3, [r7, #4] 800d2c4: 601a str r2, [r3, #0] f->idx++; 800d2c6: 687b ldr r3, [r7, #4] 800d2c8: 889b ldrh r3, [r3, #4] 800d2ca: 3301 adds r3, #1 800d2cc: b29a uxth r2, r3 800d2ce: 687b ldr r3, [r7, #4] 800d2d0: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800d2d2: 687b ldr r3, [r7, #4] 800d2d4: 889b ldrh r3, [r3, #4] 800d2d6: 2b07 cmp r3, #7 800d2d8: d902 bls.n 800d2e0 800d2da: 687b ldr r3, [r7, #4] 800d2dc: 2200 movs r2, #0 800d2de: 809a strh r2, [r3, #4] f->count++; 800d2e0: 687b ldr r3, [r7, #4] 800d2e2: 88db ldrh r3, [r3, #6] 800d2e4: 3301 adds r3, #1 800d2e6: b29a uxth r2, r3 800d2e8: 687b ldr r3, [r7, #4] 800d2ea: 80da strh r2, [r3, #6] return (int32_t)(f->sum / (int32_t)f->count); 800d2ec: 687b ldr r3, [r7, #4] 800d2ee: 681b ldr r3, [r3, #0] 800d2f0: 687a ldr r2, [r7, #4] 800d2f2: 88d2 ldrh r2, [r2, #6] 800d2f4: fb93 f3f2 sdiv r3, r3, r2 800d2f8: e02a b.n 800d350 } // Окно заполнено: "вычитаем старое + добавляем новое". int32_t old = f->buffer[f->idx]; 800d2fa: 687b ldr r3, [r7, #4] 800d2fc: 889b ldrh r3, [r3, #4] 800d2fe: 461a mov r2, r3 800d300: 687b ldr r3, [r7, #4] 800d302: 3202 adds r2, #2 800d304: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800d308: 60fb str r3, [r7, #12] f->buffer[f->idx] = x; 800d30a: 687b ldr r3, [r7, #4] 800d30c: 889b ldrh r3, [r3, #4] 800d30e: 461a mov r2, r3 800d310: 687b ldr r3, [r7, #4] 800d312: 3202 adds r2, #2 800d314: 6839 ldr r1, [r7, #0] 800d316: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += (x - old); 800d31a: 687b ldr r3, [r7, #4] 800d31c: 681a ldr r2, [r3, #0] 800d31e: 6839 ldr r1, [r7, #0] 800d320: 68fb ldr r3, [r7, #12] 800d322: 1acb subs r3, r1, r3 800d324: 441a add r2, r3 800d326: 687b ldr r3, [r7, #4] 800d328: 601a str r2, [r3, #0] f->idx++; 800d32a: 687b ldr r3, [r7, #4] 800d32c: 889b ldrh r3, [r3, #4] 800d32e: 3301 adds r3, #1 800d330: b29a uxth r2, r3 800d332: 687b ldr r3, [r7, #4] 800d334: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800d336: 687b ldr r3, [r7, #4] 800d338: 889b ldrh r3, [r3, #4] 800d33a: 2b07 cmp r3, #7 800d33c: d902 bls.n 800d344 800d33e: 687b ldr r3, [r7, #4] 800d340: 2200 movs r2, #0 800d342: 809a strh r2, [r3, #4] return (int32_t)(f->sum / (int32_t)SMA_FILTER_WINDOW); 800d344: 687b ldr r3, [r7, #4] 800d346: 681b ldr r3, [r3, #0] 800d348: 2b00 cmp r3, #0 800d34a: da00 bge.n 800d34e 800d34c: 3307 adds r3, #7 800d34e: 10db asrs r3, r3, #3 } 800d350: 4618 mov r0, r3 800d352: 3714 adds r7, #20 800d354: 46bd mov sp, r7 800d356: bc80 pop {r7} 800d358: 4770 bx lr ... 0800d35c : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800d35c: b480 push {r7} 800d35e: b085 sub sp, #20 800d360: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 800d362: 4b15 ldr r3, [pc, #84] @ (800d3b8 ) 800d364: 699b ldr r3, [r3, #24] 800d366: 4a14 ldr r2, [pc, #80] @ (800d3b8 ) 800d368: f043 0301 orr.w r3, r3, #1 800d36c: 6193 str r3, [r2, #24] 800d36e: 4b12 ldr r3, [pc, #72] @ (800d3b8 ) 800d370: 699b ldr r3, [r3, #24] 800d372: f003 0301 and.w r3, r3, #1 800d376: 60bb str r3, [r7, #8] 800d378: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800d37a: 4b0f ldr r3, [pc, #60] @ (800d3b8 ) 800d37c: 69db ldr r3, [r3, #28] 800d37e: 4a0e ldr r2, [pc, #56] @ (800d3b8 ) 800d380: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800d384: 61d3 str r3, [r2, #28] 800d386: 4b0c ldr r3, [pc, #48] @ (800d3b8 ) 800d388: 69db ldr r3, [r3, #28] 800d38a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800d38e: 607b str r3, [r7, #4] 800d390: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 800d392: 4b0a ldr r3, [pc, #40] @ (800d3bc ) 800d394: 685b ldr r3, [r3, #4] 800d396: 60fb str r3, [r7, #12] 800d398: 68fb ldr r3, [r7, #12] 800d39a: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 800d39e: 60fb str r3, [r7, #12] 800d3a0: 68fb ldr r3, [r7, #12] 800d3a2: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 800d3a6: 60fb str r3, [r7, #12] 800d3a8: 4a04 ldr r2, [pc, #16] @ (800d3bc ) 800d3aa: 68fb ldr r3, [r7, #12] 800d3ac: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800d3ae: bf00 nop 800d3b0: 3714 adds r7, #20 800d3b2: 46bd mov sp, r7 800d3b4: bc80 pop {r7} 800d3b6: 4770 bx lr 800d3b8: 40021000 .word 0x40021000 800d3bc: 40010000 .word 0x40010000 0800d3c0 : { /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800d3c0: e7fe b.n 800d3c0 800d3c2: bf00 nop 0800d3c4 : void HardFault_Handler(void) { /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800d3c4: e7fe b.n 800d3c4 800d3c6: bf00 nop 0800d3c8 : void MemManage_Handler(void) { /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800d3c8: e7fe b.n 800d3c8 800d3ca: bf00 nop 0800d3cc : void BusFault_Handler(void) { /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800d3cc: e7fe b.n 800d3cc 800d3ce: bf00 nop 0800d3d0 : void UsageFault_Handler(void) { /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 800d3d0: e7fe b.n 800d3d0 800d3d2: bf00 nop 0800d3d4 : /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800d3d4: 4770 bx lr 800d3d6: bf00 nop 0800d3d8 : /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800d3d8: 4770 bx lr 800d3da: bf00 nop 0800d3dc : /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800d3dc: 4770 bx lr 800d3de: bf00 nop 0800d3e0 : void SysTick_Handler(void) { /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800d3e0: f000 be06 b.w 800dff0 0800d3e4 : /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { 800d3e4: b510 push {r4, lr} /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_SET); 800d3e6: 4c09 ldr r4, [pc, #36] @ (800d40c ) 800d3e8: 2201 movs r2, #1 800d3ea: f44f 6100 mov.w r1, #2048 @ 0x800 800d3ee: 4620 mov r0, r4 800d3f0: f003 fa8b bl 801090a /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 800d3f4: 4806 ldr r0, [pc, #24] @ (800d410 ) 800d3f6: f002 fdc7 bl 800ff88 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d3fa: 4620 mov r0, r4 /* USER CODE END DMA1_Channel1_IRQn 1 */ } 800d3fc: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d400: 2200 movs r2, #0 800d402: f44f 6100 mov.w r1, #2048 @ 0x800 800d406: f003 ba80 b.w 801090a 800d40a: bf00 nop 800d40c: 40010c00 .word 0x40010c00 800d410: 200002c0 .word 0x200002c0 0800d414 : /** * @brief This function handles ADC1 and ADC2 global interrupts. */ void ADC1_2_IRQHandler(void) { 800d414: b510 push {r4, lr} /* USER CODE BEGIN ADC1_2_IRQn 0 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_SET); 800d416: 4c09 ldr r4, [pc, #36] @ (800d43c ) 800d418: 2201 movs r2, #1 800d41a: f44f 6100 mov.w r1, #2048 @ 0x800 800d41e: 4620 mov r0, r4 800d420: f003 fa73 bl 801090a /* USER CODE END ADC1_2_IRQn 0 */ HAL_ADC_IRQHandler(&hadc1); 800d424: 4806 ldr r0, [pc, #24] @ (800d440 ) 800d426: f000 ffd9 bl 800e3dc /* USER CODE BEGIN ADC1_2_IRQn 1 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d42a: 4620 mov r0, r4 /* USER CODE END ADC1_2_IRQn 1 */ } 800d42c: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d430: 2200 movs r2, #0 800d432: f44f 6100 mov.w r1, #2048 @ 0x800 800d436: f003 ba68 b.w 801090a 800d43a: bf00 nop 800d43c: 40010c00 .word 0x40010c00 800d440: 20000290 .word 0x20000290 0800d444 : /** * @brief This function handles CAN1 RX0 interrupt. */ void CAN1_RX0_IRQHandler(void) { 800d444: b510 push {r4, lr} /* USER CODE BEGIN CAN1_RX0_IRQn 0 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_SET); 800d446: 4c09 ldr r4, [pc, #36] @ (800d46c ) 800d448: 2201 movs r2, #1 800d44a: f44f 6180 mov.w r1, #1024 @ 0x400 800d44e: 4620 mov r0, r4 800d450: f003 fa5b bl 801090a /* USER CODE END CAN1_RX0_IRQn 0 */ HAL_CAN_IRQHandler(&hcan1); 800d454: 4806 ldr r0, [pc, #24] @ (800d470 ) 800d456: f001 fffd bl 800f454 /* USER CODE BEGIN CAN1_RX0_IRQn 1 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d45a: 4620 mov r0, r4 /* USER CODE END CAN1_RX0_IRQn 1 */ } 800d45c: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d460: 2200 movs r2, #0 800d462: f44f 6180 mov.w r1, #1024 @ 0x400 800d466: f003 ba50 b.w 801090a 800d46a: bf00 nop 800d46c: 40010c00 .word 0x40010c00 800d470: 2000035c .word 0x2000035c 0800d474 : /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 800d474: b510 push {r4, lr} /* USER CODE BEGIN TIM3_IRQn 0 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_SET); 800d476: 4c09 ldr r4, [pc, #36] @ (800d49c ) 800d478: 2201 movs r2, #1 800d47a: f44f 6100 mov.w r1, #2048 @ 0x800 800d47e: 4620 mov r0, r4 800d480: f003 fa43 bl 801090a /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); 800d484: 4806 ldr r0, [pc, #24] @ (800d4a0 ) 800d486: f004 fe21 bl 80120cc /* USER CODE BEGIN TIM3_IRQn 1 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d48a: 4620 mov r0, r4 /* USER CODE END TIM3_IRQn 1 */ } 800d48c: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d490: 2200 movs r2, #0 800d492: f44f 6100 mov.w r1, #2048 @ 0x800 800d496: f003 ba38 b.w 801090a 800d49a: bf00 nop 800d49c: 40010c00 .word 0x40010c00 800d4a0: 200010c0 .word 0x200010c0 0800d4a4 : void USART1_IRQHandler(void) { /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 800d4a4: 4801 ldr r0, [pc, #4] @ (800d4ac ) 800d4a6: f005 be6d b.w 8013184 800d4aa: bf00 nop 800d4ac: 20001198 .word 0x20001198 0800d4b0 : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 800d4b0: b510 push {r4, lr} /* USER CODE BEGIN USART2_IRQn 0 */ HAL_GPIO_WritePin(DBG2_GPIO_Port, DBG2_Pin, GPIO_PIN_SET); 800d4b2: 4c08 ldr r4, [pc, #32] @ (800d4d4 ) 800d4b4: 2201 movs r2, #1 800d4b6: 2120 movs r1, #32 800d4b8: 4620 mov r0, r4 800d4ba: f003 fa26 bl 801090a /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 800d4be: 4806 ldr r0, [pc, #24] @ (800d4d8 ) 800d4c0: f005 fe60 bl 8013184 /* USER CODE BEGIN USART2_IRQn 1 */ HAL_GPIO_WritePin(DBG2_GPIO_Port, DBG2_Pin, GPIO_PIN_RESET); 800d4c4: 4620 mov r0, r4 /* USER CODE END USART2_IRQn 1 */ } 800d4c6: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG2_GPIO_Port, DBG2_Pin, GPIO_PIN_RESET); 800d4ca: 2200 movs r2, #0 800d4cc: 2120 movs r1, #32 800d4ce: f003 ba1c b.w 801090a 800d4d2: bf00 nop 800d4d4: 40010800 .word 0x40010800 800d4d8: 200011e0 .word 0x200011e0 0800d4dc : /** * @brief This function handles USART3 global interrupt. */ void USART3_IRQHandler(void) { 800d4dc: b510 push {r4, lr} /* USER CODE BEGIN USART3_IRQn 0 */ HAL_GPIO_WritePin(DBG3_GPIO_Port, DBG3_Pin, GPIO_PIN_SET); 800d4de: 4c08 ldr r4, [pc, #32] @ (800d500 ) 800d4e0: 2201 movs r2, #1 800d4e2: 2140 movs r1, #64 @ 0x40 800d4e4: 4620 mov r0, r4 800d4e6: f003 fa10 bl 801090a /* USER CODE END USART3_IRQn 0 */ HAL_UART_IRQHandler(&huart3); 800d4ea: 4806 ldr r0, [pc, #24] @ (800d504 ) 800d4ec: f005 fe4a bl 8013184 /* USER CODE BEGIN USART3_IRQn 1 */ HAL_GPIO_WritePin(DBG3_GPIO_Port, DBG3_Pin, GPIO_PIN_RESET); 800d4f0: 4620 mov r0, r4 /* USER CODE END USART3_IRQn 1 */ } 800d4f2: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG3_GPIO_Port, DBG3_Pin, GPIO_PIN_RESET); 800d4f6: 2200 movs r2, #0 800d4f8: 2140 movs r1, #64 @ 0x40 800d4fa: f003 ba06 b.w 801090a 800d4fe: bf00 nop 800d500: 40010800 .word 0x40010800 800d504: 20001228 .word 0x20001228 0800d508 : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 800d508: b510 push {r4, lr} /* USER CODE BEGIN UART5_IRQn 0 */ HAL_GPIO_WritePin(DBG1_GPIO_Port, DBG1_Pin, GPIO_PIN_SET); 800d50a: 4c08 ldr r4, [pc, #32] @ (800d52c ) 800d50c: 2201 movs r2, #1 800d50e: 2104 movs r1, #4 800d510: 4620 mov r0, r4 800d512: f003 f9fa bl 801090a /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 800d516: 4806 ldr r0, [pc, #24] @ (800d530 ) 800d518: f005 fe34 bl 8013184 /* USER CODE BEGIN UART5_IRQn 1 */ HAL_GPIO_WritePin(DBG1_GPIO_Port, DBG1_Pin, GPIO_PIN_RESET); 800d51c: 4620 mov r0, r4 /* USER CODE END UART5_IRQn 1 */ } 800d51e: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG1_GPIO_Port, DBG1_Pin, GPIO_PIN_RESET); 800d522: 2200 movs r2, #0 800d524: 2104 movs r1, #4 800d526: f003 b9f0 b.w 801090a 800d52a: bf00 nop 800d52c: 40011000 .word 0x40011000 800d530: 20001150 .word 0x20001150 0800d534 : /** * @brief This function handles CAN2 TX interrupt. */ void CAN2_TX_IRQHandler(void) { 800d534: b510 push {r4, lr} /* USER CODE BEGIN CAN2_TX_IRQn 0 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_SET); 800d536: 4c09 ldr r4, [pc, #36] @ (800d55c ) 800d538: 2201 movs r2, #1 800d53a: f44f 6180 mov.w r1, #1024 @ 0x400 800d53e: 4620 mov r0, r4 800d540: f003 f9e3 bl 801090a /* USER CODE END CAN2_TX_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800d544: 4806 ldr r0, [pc, #24] @ (800d560 ) 800d546: f001 ff85 bl 800f454 /* USER CODE BEGIN CAN2_TX_IRQn 1 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d54a: 4620 mov r0, r4 /* USER CODE END CAN2_TX_IRQn 1 */ } 800d54c: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d550: 2200 movs r2, #0 800d552: f44f 6180 mov.w r1, #1024 @ 0x400 800d556: f003 b9d8 b.w 801090a 800d55a: bf00 nop 800d55c: 40010c00 .word 0x40010c00 800d560: 20000384 .word 0x20000384 0800d564 : /** * @brief This function handles CAN2 RX1 interrupt. */ void CAN2_RX1_IRQHandler(void) { 800d564: b510 push {r4, lr} /* USER CODE BEGIN CAN2_RX1_IRQn 0 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_SET); 800d566: 4c09 ldr r4, [pc, #36] @ (800d58c ) 800d568: 2201 movs r2, #1 800d56a: f44f 6180 mov.w r1, #1024 @ 0x400 800d56e: 4620 mov r0, r4 800d570: f003 f9cb bl 801090a /* USER CODE END CAN2_RX1_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800d574: 4806 ldr r0, [pc, #24] @ (800d590 ) 800d576: f001 ff6d bl 800f454 /* USER CODE BEGIN CAN2_RX1_IRQn 1 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d57a: 4620 mov r0, r4 /* USER CODE END CAN2_RX1_IRQn 1 */ } 800d57c: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d580: 2200 movs r2, #0 800d582: f44f 6180 mov.w r1, #1024 @ 0x400 800d586: f003 b9c0 b.w 801090a 800d58a: bf00 nop 800d58c: 40010c00 .word 0x40010c00 800d590: 20000384 .word 0x20000384 0800d594 <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 800d594: b480 push {r7} 800d596: af00 add r7, sp, #0 return 1; 800d598: 2301 movs r3, #1 } 800d59a: 4618 mov r0, r3 800d59c: 46bd mov sp, r7 800d59e: bc80 pop {r7} 800d5a0: 4770 bx lr 0800d5a2 <_kill>: int _kill(int pid, int sig) { 800d5a2: b580 push {r7, lr} 800d5a4: b082 sub sp, #8 800d5a6: af00 add r7, sp, #0 800d5a8: 6078 str r0, [r7, #4] 800d5aa: 6039 str r1, [r7, #0] (void)pid; (void)sig; errno = EINVAL; 800d5ac: f007 f8ce bl 801474c <__errno> 800d5b0: 4603 mov r3, r0 800d5b2: 2216 movs r2, #22 800d5b4: 601a str r2, [r3, #0] return -1; 800d5b6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800d5ba: 4618 mov r0, r3 800d5bc: 3708 adds r7, #8 800d5be: 46bd mov sp, r7 800d5c0: bd80 pop {r7, pc} 0800d5c2 <_exit>: void _exit (int status) { 800d5c2: b580 push {r7, lr} 800d5c4: b082 sub sp, #8 800d5c6: af00 add r7, sp, #0 800d5c8: 6078 str r0, [r7, #4] _kill(status, -1); 800d5ca: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800d5ce: 6878 ldr r0, [r7, #4] 800d5d0: f7ff ffe7 bl 800d5a2 <_kill> while (1) {} /* Make sure we hang here */ 800d5d4: bf00 nop 800d5d6: e7fd b.n 800d5d4 <_exit+0x12> 0800d5d8 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 800d5d8: b580 push {r7, lr} 800d5da: b086 sub sp, #24 800d5dc: af00 add r7, sp, #0 800d5de: 60f8 str r0, [r7, #12] 800d5e0: 60b9 str r1, [r7, #8] 800d5e2: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800d5e4: 2300 movs r3, #0 800d5e6: 617b str r3, [r7, #20] 800d5e8: e00a b.n 800d600 <_read+0x28> { *ptr++ = __io_getchar(); 800d5ea: f3af 8000 nop.w 800d5ee: 4601 mov r1, r0 800d5f0: 68bb ldr r3, [r7, #8] 800d5f2: 1c5a adds r2, r3, #1 800d5f4: 60ba str r2, [r7, #8] 800d5f6: b2ca uxtb r2, r1 800d5f8: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 800d5fa: 697b ldr r3, [r7, #20] 800d5fc: 3301 adds r3, #1 800d5fe: 617b str r3, [r7, #20] 800d600: 697a ldr r2, [r7, #20] 800d602: 687b ldr r3, [r7, #4] 800d604: 429a cmp r2, r3 800d606: dbf0 blt.n 800d5ea <_read+0x12> } return len; 800d608: 687b ldr r3, [r7, #4] } 800d60a: 4618 mov r0, r3 800d60c: 3718 adds r7, #24 800d60e: 46bd mov sp, r7 800d610: bd80 pop {r7, pc} 0800d612 <_close>: } return len; } int _close(int file) { 800d612: b480 push {r7} 800d614: b083 sub sp, #12 800d616: af00 add r7, sp, #0 800d618: 6078 str r0, [r7, #4] (void)file; return -1; 800d61a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800d61e: 4618 mov r0, r3 800d620: 370c adds r7, #12 800d622: 46bd mov sp, r7 800d624: bc80 pop {r7} 800d626: 4770 bx lr 0800d628 <_fstat>: int _fstat(int file, struct stat *st) { 800d628: b480 push {r7} 800d62a: b083 sub sp, #12 800d62c: af00 add r7, sp, #0 800d62e: 6078 str r0, [r7, #4] 800d630: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 800d632: 683b ldr r3, [r7, #0] 800d634: f44f 5200 mov.w r2, #8192 @ 0x2000 800d638: 605a str r2, [r3, #4] return 0; 800d63a: 2300 movs r3, #0 } 800d63c: 4618 mov r0, r3 800d63e: 370c adds r7, #12 800d640: 46bd mov sp, r7 800d642: bc80 pop {r7} 800d644: 4770 bx lr 0800d646 <_isatty>: int _isatty(int file) { 800d646: b480 push {r7} 800d648: b083 sub sp, #12 800d64a: af00 add r7, sp, #0 800d64c: 6078 str r0, [r7, #4] (void)file; return 1; 800d64e: 2301 movs r3, #1 } 800d650: 4618 mov r0, r3 800d652: 370c adds r7, #12 800d654: 46bd mov sp, r7 800d656: bc80 pop {r7} 800d658: 4770 bx lr 0800d65a <_lseek>: int _lseek(int file, int ptr, int dir) { 800d65a: b480 push {r7} 800d65c: b085 sub sp, #20 800d65e: af00 add r7, sp, #0 800d660: 60f8 str r0, [r7, #12] 800d662: 60b9 str r1, [r7, #8] 800d664: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 800d666: 2300 movs r3, #0 } 800d668: 4618 mov r0, r3 800d66a: 3714 adds r7, #20 800d66c: 46bd mov sp, r7 800d66e: bc80 pop {r7} 800d670: 4770 bx lr ... 0800d674 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 800d674: b580 push {r7, lr} 800d676: b086 sub sp, #24 800d678: af00 add r7, sp, #0 800d67a: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 800d67c: 4a14 ldr r2, [pc, #80] @ (800d6d0 <_sbrk+0x5c>) 800d67e: 4b15 ldr r3, [pc, #84] @ (800d6d4 <_sbrk+0x60>) 800d680: 1ad3 subs r3, r2, r3 800d682: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 800d684: 697b ldr r3, [r7, #20] 800d686: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 800d688: 4b13 ldr r3, [pc, #76] @ (800d6d8 <_sbrk+0x64>) 800d68a: 681b ldr r3, [r3, #0] 800d68c: 2b00 cmp r3, #0 800d68e: d102 bne.n 800d696 <_sbrk+0x22> { __sbrk_heap_end = &_end; 800d690: 4b11 ldr r3, [pc, #68] @ (800d6d8 <_sbrk+0x64>) 800d692: 4a12 ldr r2, [pc, #72] @ (800d6dc <_sbrk+0x68>) 800d694: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 800d696: 4b10 ldr r3, [pc, #64] @ (800d6d8 <_sbrk+0x64>) 800d698: 681a ldr r2, [r3, #0] 800d69a: 687b ldr r3, [r7, #4] 800d69c: 4413 add r3, r2 800d69e: 693a ldr r2, [r7, #16] 800d6a0: 429a cmp r2, r3 800d6a2: d207 bcs.n 800d6b4 <_sbrk+0x40> { errno = ENOMEM; 800d6a4: f007 f852 bl 801474c <__errno> 800d6a8: 4603 mov r3, r0 800d6aa: 220c movs r2, #12 800d6ac: 601a str r2, [r3, #0] return (void *)-1; 800d6ae: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800d6b2: e009 b.n 800d6c8 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 800d6b4: 4b08 ldr r3, [pc, #32] @ (800d6d8 <_sbrk+0x64>) 800d6b6: 681b ldr r3, [r3, #0] 800d6b8: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 800d6ba: 4b07 ldr r3, [pc, #28] @ (800d6d8 <_sbrk+0x64>) 800d6bc: 681a ldr r2, [r3, #0] 800d6be: 687b ldr r3, [r7, #4] 800d6c0: 4413 add r3, r2 800d6c2: 4a05 ldr r2, [pc, #20] @ (800d6d8 <_sbrk+0x64>) 800d6c4: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 800d6c6: 68fb ldr r3, [r7, #12] } 800d6c8: 4618 mov r0, r3 800d6ca: 3718 adds r7, #24 800d6cc: 46bd mov sp, r7 800d6ce: bd80 pop {r7, pc} 800d6d0: 20010000 .word 0x20010000 800d6d4: 00000400 .word 0x00000400 800d6d8: 200010bc .word 0x200010bc 800d6dc: 200013c0 .word 0x200013c0 0800d6e0 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 800d6e0: b480 push {r7} 800d6e2: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 800d6e4: bf00 nop 800d6e6: 46bd mov sp, r7 800d6e8: bc80 pop {r7} 800d6ea: 4770 bx lr 0800d6ec : TIM_HandleTypeDef htim3; TIM_HandleTypeDef htim4; /* TIM3 init function */ void MX_TIM3_Init(void) { 800d6ec: b580 push {r7, lr} 800d6ee: b08e sub sp, #56 @ 0x38 800d6f0: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800d6f2: f107 0328 add.w r3, r7, #40 @ 0x28 800d6f6: 2200 movs r2, #0 800d6f8: 601a str r2, [r3, #0] 800d6fa: 605a str r2, [r3, #4] 800d6fc: 609a str r2, [r3, #8] 800d6fe: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800d700: f107 0320 add.w r3, r7, #32 800d704: 2200 movs r2, #0 800d706: 601a str r2, [r3, #0] 800d708: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800d70a: 1d3b adds r3, r7, #4 800d70c: 2200 movs r2, #0 800d70e: 601a str r2, [r3, #0] 800d710: 605a str r2, [r3, #4] 800d712: 609a str r2, [r3, #8] 800d714: 60da str r2, [r3, #12] 800d716: 611a str r2, [r3, #16] 800d718: 615a str r2, [r3, #20] 800d71a: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 800d71c: 4b38 ldr r3, [pc, #224] @ (800d800 ) 800d71e: 4a39 ldr r2, [pc, #228] @ (800d804 ) 800d720: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 800d722: 4b37 ldr r3, [pc, #220] @ (800d800 ) 800d724: 2200 movs r2, #0 800d726: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 800d728: 4b35 ldr r3, [pc, #212] @ (800d800 ) 800d72a: 2200 movs r2, #0 800d72c: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 800d72e: 4b34 ldr r3, [pc, #208] @ (800d800 ) 800d730: f64f 72ff movw r2, #65535 @ 0xffff 800d734: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800d736: 4b32 ldr r3, [pc, #200] @ (800d800 ) 800d738: 2200 movs r2, #0 800d73a: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800d73c: 4b30 ldr r3, [pc, #192] @ (800d800 ) 800d73e: 2200 movs r2, #0 800d740: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 800d742: 482f ldr r0, [pc, #188] @ (800d800 ) 800d744: f004 fa6f bl 8011c26 800d748: 4603 mov r3, r0 800d74a: 2b00 cmp r3, #0 800d74c: d001 beq.n 800d752 { Error_Handler(); 800d74e: f7fd fa3f bl 800abd0 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800d752: f44f 5380 mov.w r3, #4096 @ 0x1000 800d756: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 800d758: f107 0328 add.w r3, r7, #40 @ 0x28 800d75c: 4619 mov r1, r3 800d75e: 4828 ldr r0, [pc, #160] @ (800d800 ) 800d760: f004 fec2 bl 80124e8 800d764: 4603 mov r3, r0 800d766: 2b00 cmp r3, #0 800d768: d001 beq.n 800d76e { Error_Handler(); 800d76a: f7fd fa31 bl 800abd0 } if (HAL_TIM_OC_Init(&htim3) != HAL_OK) 800d76e: 4824 ldr r0, [pc, #144] @ (800d800 ) 800d770: f004 faa8 bl 8011cc4 800d774: 4603 mov r3, r0 800d776: 2b00 cmp r3, #0 800d778: d001 beq.n 800d77e { Error_Handler(); 800d77a: f7fd fa29 bl 800abd0 } if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 800d77e: 4820 ldr r0, [pc, #128] @ (800d800 ) 800d780: f004 fba2 bl 8011ec8 800d784: 4603 mov r3, r0 800d786: 2b00 cmp r3, #0 800d788: d001 beq.n 800d78e { Error_Handler(); 800d78a: f7fd fa21 bl 800abd0 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_OC1; 800d78e: 2330 movs r3, #48 @ 0x30 800d790: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800d792: 2300 movs r3, #0 800d794: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800d796: f107 0320 add.w r3, r7, #32 800d79a: 4619 mov r1, r3 800d79c: 4818 ldr r0, [pc, #96] @ (800d800 ) 800d79e: f005 fa51 bl 8012c44 800d7a2: 4603 mov r3, r0 800d7a4: 2b00 cmp r3, #0 800d7a6: d001 beq.n 800d7ac { Error_Handler(); 800d7a8: f7fd fa12 bl 800abd0 } sConfigOC.OCMode = TIM_OCMODE_TIMING; 800d7ac: 2300 movs r3, #0 800d7ae: 607b str r3, [r7, #4] sConfigOC.Pulse = 1; 800d7b0: 2301 movs r3, #1 800d7b2: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800d7b4: 2300 movs r3, #0 800d7b6: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800d7b8: 2300 movs r3, #0 800d7ba: 617b str r3, [r7, #20] if (HAL_TIM_OC_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 800d7bc: 1d3b adds r3, r7, #4 800d7be: 2200 movs r2, #0 800d7c0: 4619 mov r1, r3 800d7c2: 480f ldr r0, [pc, #60] @ (800d800 ) 800d7c4: f004 fd72 bl 80122ac 800d7c8: 4603 mov r3, r0 800d7ca: 2b00 cmp r3, #0 800d7cc: d001 beq.n 800d7d2 { Error_Handler(); 800d7ce: f7fd f9ff bl 800abd0 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800d7d2: 2360 movs r3, #96 @ 0x60 800d7d4: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800d7d6: 2300 movs r3, #0 800d7d8: 60bb str r3, [r7, #8] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800d7da: 1d3b adds r3, r7, #4 800d7dc: 2204 movs r2, #4 800d7de: 4619 mov r1, r3 800d7e0: 4807 ldr r0, [pc, #28] @ (800d800 ) 800d7e2: f004 fdbf bl 8012364 800d7e6: 4603 mov r3, r0 800d7e8: 2b00 cmp r3, #0 800d7ea: d001 beq.n 800d7f0 { Error_Handler(); 800d7ec: f7fd f9f0 bl 800abd0 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 800d7f0: 4803 ldr r0, [pc, #12] @ (800d800 ) 800d7f2: f000 f8cf bl 800d994 } 800d7f6: bf00 nop 800d7f8: 3738 adds r7, #56 @ 0x38 800d7fa: 46bd mov sp, r7 800d7fc: bd80 pop {r7, pc} 800d7fe: bf00 nop 800d800: 200010c0 .word 0x200010c0 800d804: 40000400 .word 0x40000400 0800d808 : /* TIM4 init function */ void MX_TIM4_Init(void) { 800d808: b580 push {r7, lr} 800d80a: b08e sub sp, #56 @ 0x38 800d80c: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800d80e: f107 0328 add.w r3, r7, #40 @ 0x28 800d812: 2200 movs r2, #0 800d814: 601a str r2, [r3, #0] 800d816: 605a str r2, [r3, #4] 800d818: 609a str r2, [r3, #8] 800d81a: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800d81c: f107 0320 add.w r3, r7, #32 800d820: 2200 movs r2, #0 800d822: 601a str r2, [r3, #0] 800d824: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800d826: 1d3b adds r3, r7, #4 800d828: 2200 movs r2, #0 800d82a: 601a str r2, [r3, #0] 800d82c: 605a str r2, [r3, #4] 800d82e: 609a str r2, [r3, #8] 800d830: 60da str r2, [r3, #12] 800d832: 611a str r2, [r3, #16] 800d834: 615a str r2, [r3, #20] 800d836: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM4_Init 1 */ /* USER CODE END TIM4_Init 1 */ htim4.Instance = TIM4; 800d838: 4b37 ldr r3, [pc, #220] @ (800d918 ) 800d83a: 4a38 ldr r2, [pc, #224] @ (800d91c ) 800d83c: 601a str r2, [r3, #0] htim4.Init.Prescaler = 720; 800d83e: 4b36 ldr r3, [pc, #216] @ (800d918 ) 800d840: f44f 7234 mov.w r2, #720 @ 0x2d0 800d844: 605a str r2, [r3, #4] htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 800d846: 4b34 ldr r3, [pc, #208] @ (800d918 ) 800d848: 2200 movs r2, #0 800d84a: 609a str r2, [r3, #8] htim4.Init.Period = 100; 800d84c: 4b32 ldr r3, [pc, #200] @ (800d918 ) 800d84e: 2264 movs r2, #100 @ 0x64 800d850: 60da str r2, [r3, #12] htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800d852: 4b31 ldr r3, [pc, #196] @ (800d918 ) 800d854: 2200 movs r2, #0 800d856: 611a str r2, [r3, #16] htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800d858: 4b2f ldr r3, [pc, #188] @ (800d918 ) 800d85a: 2200 movs r2, #0 800d85c: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 800d85e: 482e ldr r0, [pc, #184] @ (800d918 ) 800d860: f004 f9e1 bl 8011c26 800d864: 4603 mov r3, r0 800d866: 2b00 cmp r3, #0 800d868: d001 beq.n 800d86e { Error_Handler(); 800d86a: f7fd f9b1 bl 800abd0 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800d86e: f44f 5380 mov.w r3, #4096 @ 0x1000 800d872: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 800d874: f107 0328 add.w r3, r7, #40 @ 0x28 800d878: 4619 mov r1, r3 800d87a: 4827 ldr r0, [pc, #156] @ (800d918 ) 800d87c: f004 fe34 bl 80124e8 800d880: 4603 mov r3, r0 800d882: 2b00 cmp r3, #0 800d884: d001 beq.n 800d88a { Error_Handler(); 800d886: f7fd f9a3 bl 800abd0 } if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) 800d88a: 4823 ldr r0, [pc, #140] @ (800d918 ) 800d88c: f004 fb1c bl 8011ec8 800d890: 4603 mov r3, r0 800d892: 2b00 cmp r3, #0 800d894: d001 beq.n 800d89a { Error_Handler(); 800d896: f7fd f99b bl 800abd0 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800d89a: 2300 movs r3, #0 800d89c: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800d89e: 2300 movs r3, #0 800d8a0: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 800d8a2: f107 0320 add.w r3, r7, #32 800d8a6: 4619 mov r1, r3 800d8a8: 481b ldr r0, [pc, #108] @ (800d918 ) 800d8aa: f005 f9cb bl 8012c44 800d8ae: 4603 mov r3, r0 800d8b0: 2b00 cmp r3, #0 800d8b2: d001 beq.n 800d8b8 { Error_Handler(); 800d8b4: f7fd f98c bl 800abd0 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800d8b8: 2360 movs r3, #96 @ 0x60 800d8ba: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800d8bc: 2300 movs r3, #0 800d8be: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800d8c0: 2300 movs r3, #0 800d8c2: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800d8c4: 2300 movs r3, #0 800d8c6: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800d8c8: 1d3b adds r3, r7, #4 800d8ca: 2204 movs r2, #4 800d8cc: 4619 mov r1, r3 800d8ce: 4812 ldr r0, [pc, #72] @ (800d918 ) 800d8d0: f004 fd48 bl 8012364 800d8d4: 4603 mov r3, r0 800d8d6: 2b00 cmp r3, #0 800d8d8: d001 beq.n 800d8de { Error_Handler(); 800d8da: f7fd f979 bl 800abd0 } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 800d8de: 1d3b adds r3, r7, #4 800d8e0: 2208 movs r2, #8 800d8e2: 4619 mov r1, r3 800d8e4: 480c ldr r0, [pc, #48] @ (800d918 ) 800d8e6: f004 fd3d bl 8012364 800d8ea: 4603 mov r3, r0 800d8ec: 2b00 cmp r3, #0 800d8ee: d001 beq.n 800d8f4 { Error_Handler(); 800d8f0: f7fd f96e bl 800abd0 } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 800d8f4: 1d3b adds r3, r7, #4 800d8f6: 220c movs r2, #12 800d8f8: 4619 mov r1, r3 800d8fa: 4807 ldr r0, [pc, #28] @ (800d918 ) 800d8fc: f004 fd32 bl 8012364 800d900: 4603 mov r3, r0 800d902: 2b00 cmp r3, #0 800d904: d001 beq.n 800d90a { Error_Handler(); 800d906: f7fd f963 bl 800abd0 } /* USER CODE BEGIN TIM4_Init 2 */ /* USER CODE END TIM4_Init 2 */ HAL_TIM_MspPostInit(&htim4); 800d90a: 4803 ldr r0, [pc, #12] @ (800d918 ) 800d90c: f000 f842 bl 800d994 } 800d910: bf00 nop 800d912: 3738 adds r7, #56 @ 0x38 800d914: 46bd mov sp, r7 800d916: bd80 pop {r7, pc} 800d918: 20001108 .word 0x20001108 800d91c: 40000800 .word 0x40000800 0800d920 : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 800d920: b580 push {r7, lr} 800d922: b084 sub sp, #16 800d924: af00 add r7, sp, #0 800d926: 6078 str r0, [r7, #4] if(tim_baseHandle->Instance==TIM3) 800d928: 687b ldr r3, [r7, #4] 800d92a: 681b ldr r3, [r3, #0] 800d92c: 4a16 ldr r2, [pc, #88] @ (800d988 ) 800d92e: 4293 cmp r3, r2 800d930: d114 bne.n 800d95c { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 800d932: 4b16 ldr r3, [pc, #88] @ (800d98c ) 800d934: 69db ldr r3, [r3, #28] 800d936: 4a15 ldr r2, [pc, #84] @ (800d98c ) 800d938: f043 0302 orr.w r3, r3, #2 800d93c: 61d3 str r3, [r2, #28] 800d93e: 4b13 ldr r3, [pc, #76] @ (800d98c ) 800d940: 69db ldr r3, [r3, #28] 800d942: f003 0302 and.w r3, r3, #2 800d946: 60fb str r3, [r7, #12] 800d948: 68fb ldr r3, [r7, #12] /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0); 800d94a: 2200 movs r2, #0 800d94c: 2100 movs r1, #0 800d94e: 201d movs r0, #29 800d950: f002 f89f bl 800fa92 HAL_NVIC_EnableIRQ(TIM3_IRQn); 800d954: 201d movs r0, #29 800d956: f002 f8b8 bl 800faca __HAL_RCC_TIM4_CLK_ENABLE(); /* USER CODE BEGIN TIM4_MspInit 1 */ /* USER CODE END TIM4_MspInit 1 */ } } 800d95a: e010 b.n 800d97e else if(tim_baseHandle->Instance==TIM4) 800d95c: 687b ldr r3, [r7, #4] 800d95e: 681b ldr r3, [r3, #0] 800d960: 4a0b ldr r2, [pc, #44] @ (800d990 ) 800d962: 4293 cmp r3, r2 800d964: d10b bne.n 800d97e __HAL_RCC_TIM4_CLK_ENABLE(); 800d966: 4b09 ldr r3, [pc, #36] @ (800d98c ) 800d968: 69db ldr r3, [r3, #28] 800d96a: 4a08 ldr r2, [pc, #32] @ (800d98c ) 800d96c: f043 0304 orr.w r3, r3, #4 800d970: 61d3 str r3, [r2, #28] 800d972: 4b06 ldr r3, [pc, #24] @ (800d98c ) 800d974: 69db ldr r3, [r3, #28] 800d976: f003 0304 and.w r3, r3, #4 800d97a: 60bb str r3, [r7, #8] 800d97c: 68bb ldr r3, [r7, #8] } 800d97e: bf00 nop 800d980: 3710 adds r7, #16 800d982: 46bd mov sp, r7 800d984: bd80 pop {r7, pc} 800d986: bf00 nop 800d988: 40000400 .word 0x40000400 800d98c: 40021000 .word 0x40021000 800d990: 40000800 .word 0x40000800 0800d994 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 800d994: b580 push {r7, lr} 800d996: b08a sub sp, #40 @ 0x28 800d998: af00 add r7, sp, #0 800d99a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800d99c: f107 0314 add.w r3, r7, #20 800d9a0: 2200 movs r2, #0 800d9a2: 601a str r2, [r3, #0] 800d9a4: 605a str r2, [r3, #4] 800d9a6: 609a str r2, [r3, #8] 800d9a8: 60da str r2, [r3, #12] if(timHandle->Instance==TIM3) 800d9aa: 687b ldr r3, [r7, #4] 800d9ac: 681b ldr r3, [r3, #0] 800d9ae: 4a26 ldr r2, [pc, #152] @ (800da48 ) 800d9b0: 4293 cmp r3, r2 800d9b2: d118 bne.n 800d9e6 { /* USER CODE BEGIN TIM3_MspPostInit 0 */ /* USER CODE END TIM3_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800d9b4: 4b25 ldr r3, [pc, #148] @ (800da4c ) 800d9b6: 699b ldr r3, [r3, #24] 800d9b8: 4a24 ldr r2, [pc, #144] @ (800da4c ) 800d9ba: f043 0304 orr.w r3, r3, #4 800d9be: 6193 str r3, [r2, #24] 800d9c0: 4b22 ldr r3, [pc, #136] @ (800da4c ) 800d9c2: 699b ldr r3, [r3, #24] 800d9c4: f003 0304 and.w r3, r3, #4 800d9c8: 613b str r3, [r7, #16] 800d9ca: 693b ldr r3, [r7, #16] /**TIM3 GPIO Configuration PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = CP_PWM_Pin; 800d9cc: 2380 movs r3, #128 @ 0x80 800d9ce: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d9d0: 2302 movs r3, #2 800d9d2: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800d9d4: 2302 movs r3, #2 800d9d6: 623b str r3, [r7, #32] HAL_GPIO_Init(CP_PWM_GPIO_Port, &GPIO_InitStruct); 800d9d8: f107 0314 add.w r3, r7, #20 800d9dc: 4619 mov r1, r3 800d9de: 481c ldr r0, [pc, #112] @ (800da50 ) 800d9e0: f002 fd3c bl 801045c /* USER CODE BEGIN TIM4_MspPostInit 1 */ /* USER CODE END TIM4_MspPostInit 1 */ } } 800d9e4: e02b b.n 800da3e else if(timHandle->Instance==TIM4) 800d9e6: 687b ldr r3, [r7, #4] 800d9e8: 681b ldr r3, [r3, #0] 800d9ea: 4a1a ldr r2, [pc, #104] @ (800da54 ) 800d9ec: 4293 cmp r3, r2 800d9ee: d126 bne.n 800da3e __HAL_RCC_GPIOD_CLK_ENABLE(); 800d9f0: 4b16 ldr r3, [pc, #88] @ (800da4c ) 800d9f2: 699b ldr r3, [r3, #24] 800d9f4: 4a15 ldr r2, [pc, #84] @ (800da4c ) 800d9f6: f043 0320 orr.w r3, r3, #32 800d9fa: 6193 str r3, [r2, #24] 800d9fc: 4b13 ldr r3, [pc, #76] @ (800da4c ) 800d9fe: 699b ldr r3, [r3, #24] 800da00: f003 0320 and.w r3, r3, #32 800da04: 60fb str r3, [r7, #12] 800da06: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; 800da08: f44f 4360 mov.w r3, #57344 @ 0xe000 800da0c: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800da0e: 2302 movs r3, #2 800da10: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800da12: 2302 movs r3, #2 800da14: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800da16: f107 0314 add.w r3, r7, #20 800da1a: 4619 mov r1, r3 800da1c: 480e ldr r0, [pc, #56] @ (800da58 ) 800da1e: f002 fd1d bl 801045c __HAL_AFIO_REMAP_TIM4_ENABLE(); 800da22: 4b0e ldr r3, [pc, #56] @ (800da5c ) 800da24: 685b ldr r3, [r3, #4] 800da26: 627b str r3, [r7, #36] @ 0x24 800da28: 6a7b ldr r3, [r7, #36] @ 0x24 800da2a: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800da2e: 627b str r3, [r7, #36] @ 0x24 800da30: 6a7b ldr r3, [r7, #36] @ 0x24 800da32: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800da36: 627b str r3, [r7, #36] @ 0x24 800da38: 4a08 ldr r2, [pc, #32] @ (800da5c ) 800da3a: 6a7b ldr r3, [r7, #36] @ 0x24 800da3c: 6053 str r3, [r2, #4] } 800da3e: bf00 nop 800da40: 3728 adds r7, #40 @ 0x28 800da42: 46bd mov sp, r7 800da44: bd80 pop {r7, pc} 800da46: bf00 nop 800da48: 40000400 .word 0x40000400 800da4c: 40021000 .word 0x40021000 800da50: 40010800 .word 0x40010800 800da54: 40000800 .word 0x40000800 800da58: 40011400 .word 0x40011400 800da5c: 40010000 .word 0x40010000 0800da60 : UART_HandleTypeDef huart2; UART_HandleTypeDef huart3; /* UART5 init function */ void MX_UART5_Init(void) { 800da60: b580 push {r7, lr} 800da62: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 800da64: 4b11 ldr r3, [pc, #68] @ (800daac ) 800da66: 4a12 ldr r2, [pc, #72] @ (800dab0 ) 800da68: 601a str r2, [r3, #0] huart5.Init.BaudRate = 9600; 800da6a: 4b10 ldr r3, [pc, #64] @ (800daac ) 800da6c: f44f 5216 mov.w r2, #9600 @ 0x2580 800da70: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 800da72: 4b0e ldr r3, [pc, #56] @ (800daac ) 800da74: 2200 movs r2, #0 800da76: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 800da78: 4b0c ldr r3, [pc, #48] @ (800daac ) 800da7a: 2200 movs r2, #0 800da7c: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 800da7e: 4b0b ldr r3, [pc, #44] @ (800daac ) 800da80: 2200 movs r2, #0 800da82: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 800da84: 4b09 ldr r3, [pc, #36] @ (800daac ) 800da86: 220c movs r2, #12 800da88: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800da8a: 4b08 ldr r3, [pc, #32] @ (800daac ) 800da8c: 2200 movs r2, #0 800da8e: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 800da90: 4b06 ldr r3, [pc, #24] @ (800daac ) 800da92: 2200 movs r2, #0 800da94: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 800da96: 4805 ldr r0, [pc, #20] @ (800daac ) 800da98: f005 f94c bl 8012d34 800da9c: 4603 mov r3, r0 800da9e: 2b00 cmp r3, #0 800daa0: d001 beq.n 800daa6 { Error_Handler(); 800daa2: f7fd f895 bl 800abd0 } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 800daa6: bf00 nop 800daa8: bd80 pop {r7, pc} 800daaa: bf00 nop 800daac: 20001150 .word 0x20001150 800dab0: 40005000 .word 0x40005000 0800dab4 : /* USART1 init function */ void MX_USART1_UART_Init(void) { 800dab4: b580 push {r7, lr} 800dab6: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 800dab8: 4b11 ldr r3, [pc, #68] @ (800db00 ) 800daba: 4a12 ldr r2, [pc, #72] @ (800db04 ) 800dabc: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800dabe: 4b10 ldr r3, [pc, #64] @ (800db00 ) 800dac0: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800dac4: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800dac6: 4b0e ldr r3, [pc, #56] @ (800db00 ) 800dac8: 2200 movs r2, #0 800daca: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 800dacc: 4b0c ldr r3, [pc, #48] @ (800db00 ) 800dace: 2200 movs r2, #0 800dad0: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800dad2: 4b0b ldr r3, [pc, #44] @ (800db00 ) 800dad4: 2200 movs r2, #0 800dad6: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 800dad8: 4b09 ldr r3, [pc, #36] @ (800db00 ) 800dada: 220c movs r2, #12 800dadc: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800dade: 4b08 ldr r3, [pc, #32] @ (800db00 ) 800dae0: 2200 movs r2, #0 800dae2: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 800dae4: 4b06 ldr r3, [pc, #24] @ (800db00 ) 800dae6: 2200 movs r2, #0 800dae8: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 800daea: 4805 ldr r0, [pc, #20] @ (800db00 ) 800daec: f005 f922 bl 8012d34 800daf0: 4603 mov r3, r0 800daf2: 2b00 cmp r3, #0 800daf4: d001 beq.n 800dafa { Error_Handler(); 800daf6: f7fd f86b bl 800abd0 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 800dafa: bf00 nop 800dafc: bd80 pop {r7, pc} 800dafe: bf00 nop 800db00: 20001198 .word 0x20001198 800db04: 40013800 .word 0x40013800 0800db08 : /* USART2 init function */ void MX_USART2_UART_Init(void) { 800db08: b580 push {r7, lr} 800db0a: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 800db0c: 4b11 ldr r3, [pc, #68] @ (800db54 ) 800db0e: 4a12 ldr r2, [pc, #72] @ (800db58 ) 800db10: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 800db12: 4b10 ldr r3, [pc, #64] @ (800db54 ) 800db14: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800db18: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 800db1a: 4b0e ldr r3, [pc, #56] @ (800db54 ) 800db1c: 2200 movs r2, #0 800db1e: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 800db20: 4b0c ldr r3, [pc, #48] @ (800db54 ) 800db22: 2200 movs r2, #0 800db24: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 800db26: 4b0b ldr r3, [pc, #44] @ (800db54 ) 800db28: 2200 movs r2, #0 800db2a: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 800db2c: 4b09 ldr r3, [pc, #36] @ (800db54 ) 800db2e: 220c movs r2, #12 800db30: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800db32: 4b08 ldr r3, [pc, #32] @ (800db54 ) 800db34: 2200 movs r2, #0 800db36: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 800db38: 4b06 ldr r3, [pc, #24] @ (800db54 ) 800db3a: 2200 movs r2, #0 800db3c: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 800db3e: 4805 ldr r0, [pc, #20] @ (800db54 ) 800db40: f005 f8f8 bl 8012d34 800db44: 4603 mov r3, r0 800db46: 2b00 cmp r3, #0 800db48: d001 beq.n 800db4e { Error_Handler(); 800db4a: f7fd f841 bl 800abd0 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 800db4e: bf00 nop 800db50: bd80 pop {r7, pc} 800db52: bf00 nop 800db54: 200011e0 .word 0x200011e0 800db58: 40004400 .word 0x40004400 0800db5c : /* USART3 init function */ void MX_USART3_UART_Init(void) { 800db5c: b580 push {r7, lr} 800db5e: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 800db60: 4b11 ldr r3, [pc, #68] @ (800dba8 ) 800db62: 4a12 ldr r2, [pc, #72] @ (800dbac ) 800db64: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 800db66: 4b10 ldr r3, [pc, #64] @ (800dba8 ) 800db68: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800db6c: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 800db6e: 4b0e ldr r3, [pc, #56] @ (800dba8 ) 800db70: 2200 movs r2, #0 800db72: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 800db74: 4b0c ldr r3, [pc, #48] @ (800dba8 ) 800db76: 2200 movs r2, #0 800db78: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 800db7a: 4b0b ldr r3, [pc, #44] @ (800dba8 ) 800db7c: 2200 movs r2, #0 800db7e: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 800db80: 4b09 ldr r3, [pc, #36] @ (800dba8 ) 800db82: 220c movs r2, #12 800db84: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800db86: 4b08 ldr r3, [pc, #32] @ (800dba8 ) 800db88: 2200 movs r2, #0 800db8a: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 800db8c: 4b06 ldr r3, [pc, #24] @ (800dba8 ) 800db8e: 2200 movs r2, #0 800db90: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart3) != HAL_OK) 800db92: 4805 ldr r0, [pc, #20] @ (800dba8 ) 800db94: f005 f8ce bl 8012d34 800db98: 4603 mov r3, r0 800db9a: 2b00 cmp r3, #0 800db9c: d001 beq.n 800dba2 { Error_Handler(); 800db9e: f7fd f817 bl 800abd0 } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 800dba2: bf00 nop 800dba4: bd80 pop {r7, pc} 800dba6: bf00 nop 800dba8: 20001228 .word 0x20001228 800dbac: 40004800 .word 0x40004800 0800dbb0 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 800dbb0: b580 push {r7, lr} 800dbb2: b092 sub sp, #72 @ 0x48 800dbb4: af00 add r7, sp, #0 800dbb6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800dbb8: f107 0330 add.w r3, r7, #48 @ 0x30 800dbbc: 2200 movs r2, #0 800dbbe: 601a str r2, [r3, #0] 800dbc0: 605a str r2, [r3, #4] 800dbc2: 609a str r2, [r3, #8] 800dbc4: 60da str r2, [r3, #12] if(uartHandle->Instance==UART5) 800dbc6: 687b ldr r3, [r7, #4] 800dbc8: 681b ldr r3, [r3, #0] 800dbca: 4a95 ldr r2, [pc, #596] @ (800de20 ) 800dbcc: 4293 cmp r3, r2 800dbce: d145 bne.n 800dc5c { /* USER CODE BEGIN UART5_MspInit 0 */ /* USER CODE END UART5_MspInit 0 */ /* UART5 clock enable */ __HAL_RCC_UART5_CLK_ENABLE(); 800dbd0: 4b94 ldr r3, [pc, #592] @ (800de24 ) 800dbd2: 69db ldr r3, [r3, #28] 800dbd4: 4a93 ldr r2, [pc, #588] @ (800de24 ) 800dbd6: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800dbda: 61d3 str r3, [r2, #28] 800dbdc: 4b91 ldr r3, [pc, #580] @ (800de24 ) 800dbde: 69db ldr r3, [r3, #28] 800dbe0: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800dbe4: 62fb str r3, [r7, #44] @ 0x2c 800dbe6: 6afb ldr r3, [r7, #44] @ 0x2c __HAL_RCC_GPIOC_CLK_ENABLE(); 800dbe8: 4b8e ldr r3, [pc, #568] @ (800de24 ) 800dbea: 699b ldr r3, [r3, #24] 800dbec: 4a8d ldr r2, [pc, #564] @ (800de24 ) 800dbee: f043 0310 orr.w r3, r3, #16 800dbf2: 6193 str r3, [r2, #24] 800dbf4: 4b8b ldr r3, [pc, #556] @ (800de24 ) 800dbf6: 699b ldr r3, [r3, #24] 800dbf8: f003 0310 and.w r3, r3, #16 800dbfc: 62bb str r3, [r7, #40] @ 0x28 800dbfe: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOD_CLK_ENABLE(); 800dc00: 4b88 ldr r3, [pc, #544] @ (800de24 ) 800dc02: 699b ldr r3, [r3, #24] 800dc04: 4a87 ldr r2, [pc, #540] @ (800de24 ) 800dc06: f043 0320 orr.w r3, r3, #32 800dc0a: 6193 str r3, [r2, #24] 800dc0c: 4b85 ldr r3, [pc, #532] @ (800de24 ) 800dc0e: 699b ldr r3, [r3, #24] 800dc10: f003 0320 and.w r3, r3, #32 800dc14: 627b str r3, [r7, #36] @ 0x24 800dc16: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART5 GPIO Configuration PC12 ------> UART5_TX PD2 ------> UART5_RX */ GPIO_InitStruct.Pin = GPIO_PIN_12; 800dc18: f44f 5380 mov.w r3, #4096 @ 0x1000 800dc1c: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800dc1e: 2302 movs r3, #2 800dc20: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800dc22: 2303 movs r3, #3 800dc24: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800dc26: f107 0330 add.w r3, r7, #48 @ 0x30 800dc2a: 4619 mov r1, r3 800dc2c: 487e ldr r0, [pc, #504] @ (800de28 ) 800dc2e: f002 fc15 bl 801045c GPIO_InitStruct.Pin = GPIO_PIN_2; 800dc32: 2304 movs r3, #4 800dc34: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800dc36: 2300 movs r3, #0 800dc38: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800dc3a: 2300 movs r3, #0 800dc3c: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800dc3e: f107 0330 add.w r3, r7, #48 @ 0x30 800dc42: 4619 mov r1, r3 800dc44: 4879 ldr r0, [pc, #484] @ (800de2c ) 800dc46: f002 fc09 bl 801045c /* UART5 interrupt Init */ HAL_NVIC_SetPriority(UART5_IRQn, 0, 0); 800dc4a: 2200 movs r2, #0 800dc4c: 2100 movs r1, #0 800dc4e: 2035 movs r0, #53 @ 0x35 800dc50: f001 ff1f bl 800fa92 HAL_NVIC_EnableIRQ(UART5_IRQn); 800dc54: 2035 movs r0, #53 @ 0x35 800dc56: f001 ff38 bl 800faca HAL_NVIC_EnableIRQ(USART3_IRQn); /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } 800dc5a: e0dc b.n 800de16 else if(uartHandle->Instance==USART1) 800dc5c: 687b ldr r3, [r7, #4] 800dc5e: 681b ldr r3, [r3, #0] 800dc60: 4a73 ldr r2, [pc, #460] @ (800de30 ) 800dc62: 4293 cmp r3, r2 800dc64: d13a bne.n 800dcdc __HAL_RCC_USART1_CLK_ENABLE(); 800dc66: 4b6f ldr r3, [pc, #444] @ (800de24 ) 800dc68: 699b ldr r3, [r3, #24] 800dc6a: 4a6e ldr r2, [pc, #440] @ (800de24 ) 800dc6c: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800dc70: 6193 str r3, [r2, #24] 800dc72: 4b6c ldr r3, [pc, #432] @ (800de24 ) 800dc74: 699b ldr r3, [r3, #24] 800dc76: f403 4380 and.w r3, r3, #16384 @ 0x4000 800dc7a: 623b str r3, [r7, #32] 800dc7c: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOA_CLK_ENABLE(); 800dc7e: 4b69 ldr r3, [pc, #420] @ (800de24 ) 800dc80: 699b ldr r3, [r3, #24] 800dc82: 4a68 ldr r2, [pc, #416] @ (800de24 ) 800dc84: f043 0304 orr.w r3, r3, #4 800dc88: 6193 str r3, [r2, #24] 800dc8a: 4b66 ldr r3, [pc, #408] @ (800de24 ) 800dc8c: 699b ldr r3, [r3, #24] 800dc8e: f003 0304 and.w r3, r3, #4 800dc92: 61fb str r3, [r7, #28] 800dc94: 69fb ldr r3, [r7, #28] GPIO_InitStruct.Pin = GPIO_PIN_9; 800dc96: f44f 7300 mov.w r3, #512 @ 0x200 800dc9a: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800dc9c: 2302 movs r3, #2 800dc9e: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800dca0: 2303 movs r3, #3 800dca2: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800dca4: f107 0330 add.w r3, r7, #48 @ 0x30 800dca8: 4619 mov r1, r3 800dcaa: 4862 ldr r0, [pc, #392] @ (800de34 ) 800dcac: f002 fbd6 bl 801045c GPIO_InitStruct.Pin = GPIO_PIN_10; 800dcb0: f44f 6380 mov.w r3, #1024 @ 0x400 800dcb4: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800dcb6: 2300 movs r3, #0 800dcb8: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800dcba: 2300 movs r3, #0 800dcbc: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800dcbe: f107 0330 add.w r3, r7, #48 @ 0x30 800dcc2: 4619 mov r1, r3 800dcc4: 485b ldr r0, [pc, #364] @ (800de34 ) 800dcc6: f002 fbc9 bl 801045c HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 800dcca: 2200 movs r2, #0 800dccc: 2100 movs r1, #0 800dcce: 2025 movs r0, #37 @ 0x25 800dcd0: f001 fedf bl 800fa92 HAL_NVIC_EnableIRQ(USART1_IRQn); 800dcd4: 2025 movs r0, #37 @ 0x25 800dcd6: f001 fef8 bl 800faca } 800dcda: e09c b.n 800de16 else if(uartHandle->Instance==USART2) 800dcdc: 687b ldr r3, [r7, #4] 800dcde: 681b ldr r3, [r3, #0] 800dce0: 4a55 ldr r2, [pc, #340] @ (800de38 ) 800dce2: 4293 cmp r3, r2 800dce4: d146 bne.n 800dd74 __HAL_RCC_USART2_CLK_ENABLE(); 800dce6: 4b4f ldr r3, [pc, #316] @ (800de24 ) 800dce8: 69db ldr r3, [r3, #28] 800dcea: 4a4e ldr r2, [pc, #312] @ (800de24 ) 800dcec: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800dcf0: 61d3 str r3, [r2, #28] 800dcf2: 4b4c ldr r3, [pc, #304] @ (800de24 ) 800dcf4: 69db ldr r3, [r3, #28] 800dcf6: f403 3300 and.w r3, r3, #131072 @ 0x20000 800dcfa: 61bb str r3, [r7, #24] 800dcfc: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOD_CLK_ENABLE(); 800dcfe: 4b49 ldr r3, [pc, #292] @ (800de24 ) 800dd00: 699b ldr r3, [r3, #24] 800dd02: 4a48 ldr r2, [pc, #288] @ (800de24 ) 800dd04: f043 0320 orr.w r3, r3, #32 800dd08: 6193 str r3, [r2, #24] 800dd0a: 4b46 ldr r3, [pc, #280] @ (800de24 ) 800dd0c: 699b ldr r3, [r3, #24] 800dd0e: f003 0320 and.w r3, r3, #32 800dd12: 617b str r3, [r7, #20] 800dd14: 697b ldr r3, [r7, #20] GPIO_InitStruct.Pin = GPIO_PIN_5; 800dd16: 2320 movs r3, #32 800dd18: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800dd1a: 2302 movs r3, #2 800dd1c: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800dd1e: 2303 movs r3, #3 800dd20: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800dd22: f107 0330 add.w r3, r7, #48 @ 0x30 800dd26: 4619 mov r1, r3 800dd28: 4840 ldr r0, [pc, #256] @ (800de2c ) 800dd2a: f002 fb97 bl 801045c GPIO_InitStruct.Pin = GPIO_PIN_6; 800dd2e: 2340 movs r3, #64 @ 0x40 800dd30: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800dd32: 2300 movs r3, #0 800dd34: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800dd36: 2300 movs r3, #0 800dd38: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800dd3a: f107 0330 add.w r3, r7, #48 @ 0x30 800dd3e: 4619 mov r1, r3 800dd40: 483a ldr r0, [pc, #232] @ (800de2c ) 800dd42: f002 fb8b bl 801045c __HAL_AFIO_REMAP_USART2_ENABLE(); 800dd46: 4b3d ldr r3, [pc, #244] @ (800de3c ) 800dd48: 685b ldr r3, [r3, #4] 800dd4a: 643b str r3, [r7, #64] @ 0x40 800dd4c: 6c3b ldr r3, [r7, #64] @ 0x40 800dd4e: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800dd52: 643b str r3, [r7, #64] @ 0x40 800dd54: 6c3b ldr r3, [r7, #64] @ 0x40 800dd56: f043 0308 orr.w r3, r3, #8 800dd5a: 643b str r3, [r7, #64] @ 0x40 800dd5c: 4a37 ldr r2, [pc, #220] @ (800de3c ) 800dd5e: 6c3b ldr r3, [r7, #64] @ 0x40 800dd60: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); 800dd62: 2200 movs r2, #0 800dd64: 2100 movs r1, #0 800dd66: 2026 movs r0, #38 @ 0x26 800dd68: f001 fe93 bl 800fa92 HAL_NVIC_EnableIRQ(USART2_IRQn); 800dd6c: 2026 movs r0, #38 @ 0x26 800dd6e: f001 feac bl 800faca } 800dd72: e050 b.n 800de16 else if(uartHandle->Instance==USART3) 800dd74: 687b ldr r3, [r7, #4] 800dd76: 681b ldr r3, [r3, #0] 800dd78: 4a31 ldr r2, [pc, #196] @ (800de40 ) 800dd7a: 4293 cmp r3, r2 800dd7c: d14b bne.n 800de16 __HAL_RCC_USART3_CLK_ENABLE(); 800dd7e: 4b29 ldr r3, [pc, #164] @ (800de24 ) 800dd80: 69db ldr r3, [r3, #28] 800dd82: 4a28 ldr r2, [pc, #160] @ (800de24 ) 800dd84: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800dd88: 61d3 str r3, [r2, #28] 800dd8a: 4b26 ldr r3, [pc, #152] @ (800de24 ) 800dd8c: 69db ldr r3, [r3, #28] 800dd8e: f403 2380 and.w r3, r3, #262144 @ 0x40000 800dd92: 613b str r3, [r7, #16] 800dd94: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 800dd96: 4b23 ldr r3, [pc, #140] @ (800de24 ) 800dd98: 699b ldr r3, [r3, #24] 800dd9a: 4a22 ldr r2, [pc, #136] @ (800de24 ) 800dd9c: f043 0310 orr.w r3, r3, #16 800dda0: 6193 str r3, [r2, #24] 800dda2: 4b20 ldr r3, [pc, #128] @ (800de24 ) 800dda4: 699b ldr r3, [r3, #24] 800dda6: f003 0310 and.w r3, r3, #16 800ddaa: 60fb str r3, [r7, #12] 800ddac: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_10; 800ddae: f44f 6380 mov.w r3, #1024 @ 0x400 800ddb2: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800ddb4: 2302 movs r3, #2 800ddb6: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800ddb8: 2303 movs r3, #3 800ddba: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800ddbc: f107 0330 add.w r3, r7, #48 @ 0x30 800ddc0: 4619 mov r1, r3 800ddc2: 4819 ldr r0, [pc, #100] @ (800de28 ) 800ddc4: f002 fb4a bl 801045c GPIO_InitStruct.Pin = GPIO_PIN_11; 800ddc8: f44f 6300 mov.w r3, #2048 @ 0x800 800ddcc: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800ddce: 2300 movs r3, #0 800ddd0: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800ddd2: 2300 movs r3, #0 800ddd4: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800ddd6: f107 0330 add.w r3, r7, #48 @ 0x30 800ddda: 4619 mov r1, r3 800dddc: 4812 ldr r0, [pc, #72] @ (800de28 ) 800ddde: f002 fb3d bl 801045c __HAL_AFIO_REMAP_USART3_PARTIAL(); 800dde2: 4b16 ldr r3, [pc, #88] @ (800de3c ) 800dde4: 685b ldr r3, [r3, #4] 800dde6: 647b str r3, [r7, #68] @ 0x44 800dde8: 6c7b ldr r3, [r7, #68] @ 0x44 800ddea: f023 0330 bic.w r3, r3, #48 @ 0x30 800ddee: 647b str r3, [r7, #68] @ 0x44 800ddf0: 6c7b ldr r3, [r7, #68] @ 0x44 800ddf2: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800ddf6: 647b str r3, [r7, #68] @ 0x44 800ddf8: 6c7b ldr r3, [r7, #68] @ 0x44 800ddfa: f043 0310 orr.w r3, r3, #16 800ddfe: 647b str r3, [r7, #68] @ 0x44 800de00: 4a0e ldr r2, [pc, #56] @ (800de3c ) 800de02: 6c7b ldr r3, [r7, #68] @ 0x44 800de04: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); 800de06: 2200 movs r2, #0 800de08: 2100 movs r1, #0 800de0a: 2027 movs r0, #39 @ 0x27 800de0c: f001 fe41 bl 800fa92 HAL_NVIC_EnableIRQ(USART3_IRQn); 800de10: 2027 movs r0, #39 @ 0x27 800de12: f001 fe5a bl 800faca } 800de16: bf00 nop 800de18: 3748 adds r7, #72 @ 0x48 800de1a: 46bd mov sp, r7 800de1c: bd80 pop {r7, pc} 800de1e: bf00 nop 800de20: 40005000 .word 0x40005000 800de24: 40021000 .word 0x40021000 800de28: 40011000 .word 0x40011000 800de2c: 40011400 .word 0x40011400 800de30: 40013800 .word 0x40013800 800de34: 40010800 .word 0x40010800 800de38: 40004400 .word 0x40004400 800de3c: 40010000 .word 0x40010000 800de40: 40004800 .word 0x40004800 0800de44 : void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) { 800de44: b580 push {r7, lr} 800de46: b082 sub sp, #8 800de48: af00 add r7, sp, #0 800de4a: 6078 str r0, [r7, #4] if(uartHandle->Instance==UART5) 800de4c: 687b ldr r3, [r7, #4] 800de4e: 681b ldr r3, [r3, #0] 800de50: 4a29 ldr r2, [pc, #164] @ (800def8 ) 800de52: 4293 cmp r3, r2 800de54: d112 bne.n 800de7c { /* USER CODE BEGIN UART5_MspDeInit 0 */ /* USER CODE END UART5_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_UART5_CLK_DISABLE(); 800de56: 4b29 ldr r3, [pc, #164] @ (800defc ) 800de58: 69db ldr r3, [r3, #28] 800de5a: 4a28 ldr r2, [pc, #160] @ (800defc ) 800de5c: f423 1380 bic.w r3, r3, #1048576 @ 0x100000 800de60: 61d3 str r3, [r2, #28] /**UART5 GPIO Configuration PC12 ------> UART5_TX PD2 ------> UART5_RX */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12); 800de62: f44f 5180 mov.w r1, #4096 @ 0x1000 800de66: 4826 ldr r0, [pc, #152] @ (800df00 ) 800de68: f002 fc7c bl 8010764 HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); 800de6c: 2104 movs r1, #4 800de6e: 4825 ldr r0, [pc, #148] @ (800df04 ) 800de70: f002 fc78 bl 8010764 /* UART5 interrupt Deinit */ HAL_NVIC_DisableIRQ(UART5_IRQn); 800de74: 2035 movs r0, #53 @ 0x35 800de76: f001 fe36 bl 800fae6 HAL_NVIC_DisableIRQ(USART3_IRQn); /* USER CODE BEGIN USART3_MspDeInit 1 */ /* USER CODE END USART3_MspDeInit 1 */ } } 800de7a: e039 b.n 800def0 else if(uartHandle->Instance==USART1) 800de7c: 687b ldr r3, [r7, #4] 800de7e: 681b ldr r3, [r3, #0] 800de80: 4a21 ldr r2, [pc, #132] @ (800df08 ) 800de82: 4293 cmp r3, r2 800de84: d10e bne.n 800dea4 __HAL_RCC_USART1_CLK_DISABLE(); 800de86: 4b1d ldr r3, [pc, #116] @ (800defc ) 800de88: 699b ldr r3, [r3, #24] 800de8a: 4a1c ldr r2, [pc, #112] @ (800defc ) 800de8c: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800de90: 6193 str r3, [r2, #24] HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); 800de92: f44f 61c0 mov.w r1, #1536 @ 0x600 800de96: 481d ldr r0, [pc, #116] @ (800df0c ) 800de98: f002 fc64 bl 8010764 HAL_NVIC_DisableIRQ(USART1_IRQn); 800de9c: 2025 movs r0, #37 @ 0x25 800de9e: f001 fe22 bl 800fae6 } 800dea2: e025 b.n 800def0 else if(uartHandle->Instance==USART2) 800dea4: 687b ldr r3, [r7, #4] 800dea6: 681b ldr r3, [r3, #0] 800dea8: 4a19 ldr r2, [pc, #100] @ (800df10 ) 800deaa: 4293 cmp r3, r2 800deac: d10d bne.n 800deca __HAL_RCC_USART2_CLK_DISABLE(); 800deae: 4b13 ldr r3, [pc, #76] @ (800defc ) 800deb0: 69db ldr r3, [r3, #28] 800deb2: 4a12 ldr r2, [pc, #72] @ (800defc ) 800deb4: f423 3300 bic.w r3, r3, #131072 @ 0x20000 800deb8: 61d3 str r3, [r2, #28] HAL_GPIO_DeInit(GPIOD, GPIO_PIN_5|GPIO_PIN_6); 800deba: 2160 movs r1, #96 @ 0x60 800debc: 4811 ldr r0, [pc, #68] @ (800df04 ) 800debe: f002 fc51 bl 8010764 HAL_NVIC_DisableIRQ(USART2_IRQn); 800dec2: 2026 movs r0, #38 @ 0x26 800dec4: f001 fe0f bl 800fae6 } 800dec8: e012 b.n 800def0 else if(uartHandle->Instance==USART3) 800deca: 687b ldr r3, [r7, #4] 800decc: 681b ldr r3, [r3, #0] 800dece: 4a11 ldr r2, [pc, #68] @ (800df14 ) 800ded0: 4293 cmp r3, r2 800ded2: d10d bne.n 800def0 __HAL_RCC_USART3_CLK_DISABLE(); 800ded4: 4b09 ldr r3, [pc, #36] @ (800defc ) 800ded6: 69db ldr r3, [r3, #28] 800ded8: 4a08 ldr r2, [pc, #32] @ (800defc ) 800deda: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800dede: 61d3 str r3, [r2, #28] HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11); 800dee0: f44f 6140 mov.w r1, #3072 @ 0xc00 800dee4: 4806 ldr r0, [pc, #24] @ (800df00 ) 800dee6: f002 fc3d bl 8010764 HAL_NVIC_DisableIRQ(USART3_IRQn); 800deea: 2027 movs r0, #39 @ 0x27 800deec: f001 fdfb bl 800fae6 } 800def0: bf00 nop 800def2: 3708 adds r7, #8 800def4: 46bd mov sp, r7 800def6: bd80 pop {r7, pc} 800def8: 40005000 .word 0x40005000 800defc: 40021000 .word 0x40021000 800df00: 40011000 .word 0x40011000 800df04: 40011400 .word 0x40011400 800df08: 40013800 .word 0x40013800 800df0c: 40010800 .word 0x40010800 800df10: 40004400 .word 0x40004400 800df14: 40004800 .word 0x40004800 0800df18 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 800df18: f7ff fbe2 bl 800d6e0 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 800df1c: 480b ldr r0, [pc, #44] @ (800df4c ) ldr r1, =_edata 800df1e: 490c ldr r1, [pc, #48] @ (800df50 ) ldr r2, =_sidata 800df20: 4a0c ldr r2, [pc, #48] @ (800df54 ) movs r3, #0 800df22: 2300 movs r3, #0 b LoopCopyDataInit 800df24: e002 b.n 800df2c 0800df26 : CopyDataInit: ldr r4, [r2, r3] 800df26: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800df28: 50c4 str r4, [r0, r3] adds r3, r3, #4 800df2a: 3304 adds r3, #4 0800df2c : LoopCopyDataInit: adds r4, r0, r3 800df2c: 18c4 adds r4, r0, r3 cmp r4, r1 800df2e: 428c cmp r4, r1 bcc CopyDataInit 800df30: d3f9 bcc.n 800df26 /* Zero fill the bss segment. */ ldr r2, =_sbss 800df32: 4a09 ldr r2, [pc, #36] @ (800df58 ) ldr r4, =_ebss 800df34: 4c09 ldr r4, [pc, #36] @ (800df5c ) movs r3, #0 800df36: 2300 movs r3, #0 b LoopFillZerobss 800df38: e001 b.n 800df3e 0800df3a : FillZerobss: str r3, [r2] 800df3a: 6013 str r3, [r2, #0] adds r2, r2, #4 800df3c: 3204 adds r2, #4 0800df3e : LoopFillZerobss: cmp r2, r4 800df3e: 42a2 cmp r2, r4 bcc FillZerobss 800df40: d3fb bcc.n 800df3a /* Call static constructors */ bl __libc_init_array 800df42: f006 fc09 bl 8014758 <__libc_init_array> /* Call the application's entry point.*/ bl main 800df46: f7fc fd59 bl 800a9fc
bx lr 800df4a: 4770 bx lr ldr r0, =_sdata 800df4c: 20000000 .word 0x20000000 ldr r1, =_edata 800df50: 20000258 .word 0x20000258 ldr r2, =_sidata 800df54: 08017604 .word 0x08017604 ldr r2, =_sbss 800df58: 20000258 .word 0x20000258 ldr r4, =_ebss 800df5c: 200013c0 .word 0x200013c0 0800df60 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 800df60: e7fe b.n 800df60 ... 0800df64 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800df64: b580 push {r7, lr} 800df66: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 800df68: 4b08 ldr r3, [pc, #32] @ (800df8c ) 800df6a: 681b ldr r3, [r3, #0] 800df6c: 4a07 ldr r2, [pc, #28] @ (800df8c ) 800df6e: f043 0310 orr.w r3, r3, #16 800df72: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800df74: 2003 movs r0, #3 800df76: f001 fd81 bl 800fa7c /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800df7a: 200f movs r0, #15 800df7c: f000 f808 bl 800df90 /* Init the low level hardware */ HAL_MspInit(); 800df80: f7ff f9ec bl 800d35c /* Return function status */ return HAL_OK; 800df84: 2300 movs r3, #0 } 800df86: 4618 mov r0, r3 800df88: bd80 pop {r7, pc} 800df8a: bf00 nop 800df8c: 40022000 .word 0x40022000 0800df90 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800df90: b580 push {r7, lr} 800df92: b082 sub sp, #8 800df94: af00 add r7, sp, #0 800df96: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 800df98: 4b12 ldr r3, [pc, #72] @ (800dfe4 ) 800df9a: 681a ldr r2, [r3, #0] 800df9c: 4b12 ldr r3, [pc, #72] @ (800dfe8 ) 800df9e: 781b ldrb r3, [r3, #0] 800dfa0: 4619 mov r1, r3 800dfa2: f44f 737a mov.w r3, #1000 @ 0x3e8 800dfa6: fbb3 f3f1 udiv r3, r3, r1 800dfaa: fbb2 f3f3 udiv r3, r2, r3 800dfae: 4618 mov r0, r3 800dfb0: f001 fda7 bl 800fb02 800dfb4: 4603 mov r3, r0 800dfb6: 2b00 cmp r3, #0 800dfb8: d001 beq.n 800dfbe { return HAL_ERROR; 800dfba: 2301 movs r3, #1 800dfbc: e00e b.n 800dfdc } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800dfbe: 687b ldr r3, [r7, #4] 800dfc0: 2b0f cmp r3, #15 800dfc2: d80a bhi.n 800dfda { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800dfc4: 2200 movs r2, #0 800dfc6: 6879 ldr r1, [r7, #4] 800dfc8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800dfcc: f001 fd61 bl 800fa92 uwTickPrio = TickPriority; 800dfd0: 4a06 ldr r2, [pc, #24] @ (800dfec ) 800dfd2: 687b ldr r3, [r7, #4] 800dfd4: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800dfd6: 2300 movs r3, #0 800dfd8: e000 b.n 800dfdc return HAL_ERROR; 800dfda: 2301 movs r3, #1 } 800dfdc: 4618 mov r0, r3 800dfde: 3708 adds r7, #8 800dfe0: 46bd mov sp, r7 800dfe2: bd80 pop {r7, pc} 800dfe4: 20000084 .word 0x20000084 800dfe8: 2000008c .word 0x2000008c 800dfec: 20000088 .word 0x20000088 0800dff0 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800dff0: b480 push {r7} 800dff2: af00 add r7, sp, #0 uwTick += uwTickFreq; 800dff4: 4b05 ldr r3, [pc, #20] @ (800e00c ) 800dff6: 781b ldrb r3, [r3, #0] 800dff8: 461a mov r2, r3 800dffa: 4b05 ldr r3, [pc, #20] @ (800e010 ) 800dffc: 681b ldr r3, [r3, #0] 800dffe: 4413 add r3, r2 800e000: 4a03 ldr r2, [pc, #12] @ (800e010 ) 800e002: 6013 str r3, [r2, #0] } 800e004: bf00 nop 800e006: 46bd mov sp, r7 800e008: bc80 pop {r7} 800e00a: 4770 bx lr 800e00c: 2000008c .word 0x2000008c 800e010: 20001270 .word 0x20001270 0800e014 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 800e014: b480 push {r7} 800e016: af00 add r7, sp, #0 return uwTick; 800e018: 4b02 ldr r3, [pc, #8] @ (800e024 ) 800e01a: 681b ldr r3, [r3, #0] } 800e01c: 4618 mov r0, r3 800e01e: 46bd mov sp, r7 800e020: bc80 pop {r7} 800e022: 4770 bx lr 800e024: 20001270 .word 0x20001270 0800e028 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 800e028: b580 push {r7, lr} 800e02a: b084 sub sp, #16 800e02c: af00 add r7, sp, #0 800e02e: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800e030: f7ff fff0 bl 800e014 800e034: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800e036: 687b ldr r3, [r7, #4] 800e038: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800e03a: 68fb ldr r3, [r7, #12] 800e03c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800e040: d005 beq.n 800e04e { wait += (uint32_t)(uwTickFreq); 800e042: 4b0a ldr r3, [pc, #40] @ (800e06c ) 800e044: 781b ldrb r3, [r3, #0] 800e046: 461a mov r2, r3 800e048: 68fb ldr r3, [r7, #12] 800e04a: 4413 add r3, r2 800e04c: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 800e04e: bf00 nop 800e050: f7ff ffe0 bl 800e014 800e054: 4602 mov r2, r0 800e056: 68bb ldr r3, [r7, #8] 800e058: 1ad3 subs r3, r2, r3 800e05a: 68fa ldr r2, [r7, #12] 800e05c: 429a cmp r2, r3 800e05e: d8f7 bhi.n 800e050 { } } 800e060: bf00 nop 800e062: bf00 nop 800e064: 3710 adds r7, #16 800e066: 46bd mov sp, r7 800e068: bd80 pop {r7, pc} 800e06a: bf00 nop 800e06c: 2000008c .word 0x2000008c 0800e070 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 800e070: b580 push {r7, lr} 800e072: b086 sub sp, #24 800e074: af00 add r7, sp, #0 800e076: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e078: 2300 movs r3, #0 800e07a: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 800e07c: 2300 movs r3, #0 800e07e: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 800e080: 2300 movs r3, #0 800e082: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 800e084: 2300 movs r3, #0 800e086: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 800e088: 687b ldr r3, [r7, #4] 800e08a: 2b00 cmp r3, #0 800e08c: d101 bne.n 800e092 { return HAL_ERROR; 800e08e: 2301 movs r3, #1 800e090: e0be b.n 800e210 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 800e092: 687b ldr r3, [r7, #4] 800e094: 689b ldr r3, [r3, #8] 800e096: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 800e098: 687b ldr r3, [r7, #4] 800e09a: 6a9b ldr r3, [r3, #40] @ 0x28 800e09c: 2b00 cmp r3, #0 800e09e: d109 bne.n 800e0b4 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 800e0a0: 687b ldr r3, [r7, #4] 800e0a2: 2200 movs r2, #0 800e0a4: 62da str r2, [r3, #44] @ 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 800e0a6: 687b ldr r3, [r7, #4] 800e0a8: 2200 movs r2, #0 800e0aa: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800e0ae: 6878 ldr r0, [r7, #4] 800e0b0: f7fb faf8 bl 80096a4 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800e0b4: 6878 ldr r0, [r7, #4] 800e0b6: f000 fbbd bl 800e834 800e0ba: 4603 mov r3, r0 800e0bc: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 800e0be: 687b ldr r3, [r7, #4] 800e0c0: 6a9b ldr r3, [r3, #40] @ 0x28 800e0c2: f003 0310 and.w r3, r3, #16 800e0c6: 2b00 cmp r3, #0 800e0c8: f040 8099 bne.w 800e1fe 800e0cc: 7dfb ldrb r3, [r7, #23] 800e0ce: 2b00 cmp r3, #0 800e0d0: f040 8095 bne.w 800e1fe (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e0d4: 687b ldr r3, [r7, #4] 800e0d6: 6a9b ldr r3, [r3, #40] @ 0x28 800e0d8: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800e0dc: f023 0302 bic.w r3, r3, #2 800e0e0: f043 0202 orr.w r2, r3, #2 800e0e4: 687b ldr r3, [r7, #4] 800e0e6: 629a str r2, [r3, #40] @ 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 800e0e8: 687b ldr r3, [r7, #4] 800e0ea: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800e0ec: 687b ldr r3, [r7, #4] 800e0ee: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 800e0f0: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 800e0f2: 687b ldr r3, [r7, #4] 800e0f4: 7b1b ldrb r3, [r3, #12] 800e0f6: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800e0f8: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 800e0fa: 68ba ldr r2, [r7, #8] 800e0fc: 4313 orrs r3, r2 800e0fe: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 800e100: 687b ldr r3, [r7, #4] 800e102: 689b ldr r3, [r3, #8] 800e104: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e108: d003 beq.n 800e112 800e10a: 687b ldr r3, [r7, #4] 800e10c: 689b ldr r3, [r3, #8] 800e10e: 2b01 cmp r3, #1 800e110: d102 bne.n 800e118 800e112: f44f 7380 mov.w r3, #256 @ 0x100 800e116: e000 b.n 800e11a 800e118: 2300 movs r3, #0 800e11a: 693a ldr r2, [r7, #16] 800e11c: 4313 orrs r3, r2 800e11e: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 800e120: 687b ldr r3, [r7, #4] 800e122: 7d1b ldrb r3, [r3, #20] 800e124: 2b01 cmp r3, #1 800e126: d119 bne.n 800e15c { if (hadc->Init.ContinuousConvMode == DISABLE) 800e128: 687b ldr r3, [r7, #4] 800e12a: 7b1b ldrb r3, [r3, #12] 800e12c: 2b00 cmp r3, #0 800e12e: d109 bne.n 800e144 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 800e130: 687b ldr r3, [r7, #4] 800e132: 699b ldr r3, [r3, #24] 800e134: 3b01 subs r3, #1 800e136: 035a lsls r2, r3, #13 800e138: 693b ldr r3, [r7, #16] 800e13a: 4313 orrs r3, r2 800e13c: f443 6300 orr.w r3, r3, #2048 @ 0x800 800e140: 613b str r3, [r7, #16] 800e142: e00b b.n 800e15c { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800e144: 687b ldr r3, [r7, #4] 800e146: 6a9b ldr r3, [r3, #40] @ 0x28 800e148: f043 0220 orr.w r2, r3, #32 800e14c: 687b ldr r3, [r7, #4] 800e14e: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e150: 687b ldr r3, [r7, #4] 800e152: 6adb ldr r3, [r3, #44] @ 0x2c 800e154: f043 0201 orr.w r2, r3, #1 800e158: 687b ldr r3, [r7, #4] 800e15a: 62da str r2, [r3, #44] @ 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 800e15c: 687b ldr r3, [r7, #4] 800e15e: 681b ldr r3, [r3, #0] 800e160: 685b ldr r3, [r3, #4] 800e162: f423 4169 bic.w r1, r3, #59648 @ 0xe900 800e166: 687b ldr r3, [r7, #4] 800e168: 681b ldr r3, [r3, #0] 800e16a: 693a ldr r2, [r7, #16] 800e16c: 430a orrs r2, r1 800e16e: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 800e170: 687b ldr r3, [r7, #4] 800e172: 681b ldr r3, [r3, #0] 800e174: 689a ldr r2, [r3, #8] 800e176: 4b28 ldr r3, [pc, #160] @ (800e218 ) 800e178: 4013 ands r3, r2 800e17a: 687a ldr r2, [r7, #4] 800e17c: 6812 ldr r2, [r2, #0] 800e17e: 68b9 ldr r1, [r7, #8] 800e180: 430b orrs r3, r1 800e182: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 800e184: 687b ldr r3, [r7, #4] 800e186: 689b ldr r3, [r3, #8] 800e188: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e18c: d003 beq.n 800e196 800e18e: 687b ldr r3, [r7, #4] 800e190: 689b ldr r3, [r3, #8] 800e192: 2b01 cmp r3, #1 800e194: d104 bne.n 800e1a0 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 800e196: 687b ldr r3, [r7, #4] 800e198: 691b ldr r3, [r3, #16] 800e19a: 3b01 subs r3, #1 800e19c: 051b lsls r3, r3, #20 800e19e: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 800e1a0: 687b ldr r3, [r7, #4] 800e1a2: 681b ldr r3, [r3, #0] 800e1a4: 6adb ldr r3, [r3, #44] @ 0x2c 800e1a6: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 800e1aa: 687b ldr r3, [r7, #4] 800e1ac: 681b ldr r3, [r3, #0] 800e1ae: 68fa ldr r2, [r7, #12] 800e1b0: 430a orrs r2, r1 800e1b2: 62da str r2, [r3, #44] @ 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800e1b4: 687b ldr r3, [r7, #4] 800e1b6: 681b ldr r3, [r3, #0] 800e1b8: 689a ldr r2, [r3, #8] 800e1ba: 4b18 ldr r3, [pc, #96] @ (800e21c ) 800e1bc: 4013 ands r3, r2 800e1be: 68ba ldr r2, [r7, #8] 800e1c0: 429a cmp r2, r3 800e1c2: d10b bne.n 800e1dc ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 800e1c4: 687b ldr r3, [r7, #4] 800e1c6: 2200 movs r2, #0 800e1c8: 62da str r2, [r3, #44] @ 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e1ca: 687b ldr r3, [r7, #4] 800e1cc: 6a9b ldr r3, [r3, #40] @ 0x28 800e1ce: f023 0303 bic.w r3, r3, #3 800e1d2: f043 0201 orr.w r2, r3, #1 800e1d6: 687b ldr r3, [r7, #4] 800e1d8: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800e1da: e018 b.n 800e20e HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800e1dc: 687b ldr r3, [r7, #4] 800e1de: 6a9b ldr r3, [r3, #40] @ 0x28 800e1e0: f023 0312 bic.w r3, r3, #18 800e1e4: f043 0210 orr.w r2, r3, #16 800e1e8: 687b ldr r3, [r7, #4] 800e1ea: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e1ec: 687b ldr r3, [r7, #4] 800e1ee: 6adb ldr r3, [r3, #44] @ 0x2c 800e1f0: f043 0201 orr.w r2, r3, #1 800e1f4: 687b ldr r3, [r7, #4] 800e1f6: 62da str r2, [r3, #44] @ 0x2c tmp_hal_status = HAL_ERROR; 800e1f8: 2301 movs r3, #1 800e1fa: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800e1fc: e007 b.n 800e20e } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800e1fe: 687b ldr r3, [r7, #4] 800e200: 6a9b ldr r3, [r3, #40] @ 0x28 800e202: f043 0210 orr.w r2, r3, #16 800e206: 687b ldr r3, [r7, #4] 800e208: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800e20a: 2301 movs r3, #1 800e20c: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800e20e: 7dfb ldrb r3, [r7, #23] } 800e210: 4618 mov r0, r3 800e212: 3718 adds r7, #24 800e214: 46bd mov sp, r7 800e216: bd80 pop {r7, pc} 800e218: ffe1f7fd .word 0xffe1f7fd 800e21c: ff1f0efe .word 0xff1f0efe 0800e220 : * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { 800e220: b580 push {r7, lr} 800e222: b086 sub sp, #24 800e224: af00 add r7, sp, #0 800e226: 60f8 str r0, [r7, #12] 800e228: 60b9 str r1, [r7, #8] 800e22a: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e22c: 2300 movs r3, #0 800e22e: 75fb strb r3, [r7, #23] assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); /* Verification if multimode is disabled (for devices with several ADC) */ /* If multimode is enabled, dedicated function multimode conversion */ /* start DMA must be used. */ if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) 800e230: 68fb ldr r3, [r7, #12] 800e232: 681b ldr r3, [r3, #0] 800e234: 4a64 ldr r2, [pc, #400] @ (800e3c8 ) 800e236: 4293 cmp r3, r2 800e238: d004 beq.n 800e244 800e23a: 68fb ldr r3, [r7, #12] 800e23c: 681b ldr r3, [r3, #0] 800e23e: 4a63 ldr r2, [pc, #396] @ (800e3cc ) 800e240: 4293 cmp r3, r2 800e242: d106 bne.n 800e252 800e244: 4b60 ldr r3, [pc, #384] @ (800e3c8 ) 800e246: 685b ldr r3, [r3, #4] 800e248: f403 2370 and.w r3, r3, #983040 @ 0xf0000 800e24c: 2b00 cmp r3, #0 800e24e: f040 80b3 bne.w 800e3b8 { /* Process locked */ __HAL_LOCK(hadc); 800e252: 68fb ldr r3, [r7, #12] 800e254: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800e258: 2b01 cmp r3, #1 800e25a: d101 bne.n 800e260 800e25c: 2302 movs r3, #2 800e25e: e0ae b.n 800e3be 800e260: 68fb ldr r3, [r7, #12] 800e262: 2201 movs r2, #1 800e264: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 800e268: 68f8 ldr r0, [r7, #12] 800e26a: f000 fa89 bl 800e780 800e26e: 4603 mov r3, r0 800e270: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800e272: 7dfb ldrb r3, [r7, #23] 800e274: 2b00 cmp r3, #0 800e276: f040 809a bne.w 800e3ae { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 800e27a: 68fb ldr r3, [r7, #12] 800e27c: 6a9b ldr r3, [r3, #40] @ 0x28 800e27e: f423 6370 bic.w r3, r3, #3840 @ 0xf00 800e282: f023 0301 bic.w r3, r3, #1 800e286: f443 7280 orr.w r2, r3, #256 @ 0x100 800e28a: 68fb ldr r3, [r7, #12] 800e28c: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 800e28e: 68fb ldr r3, [r7, #12] 800e290: 681b ldr r3, [r3, #0] 800e292: 4a4e ldr r2, [pc, #312] @ (800e3cc ) 800e294: 4293 cmp r3, r2 800e296: d105 bne.n 800e2a4 800e298: 4b4b ldr r3, [pc, #300] @ (800e3c8 ) 800e29a: 685b ldr r3, [r3, #4] 800e29c: f403 2370 and.w r3, r3, #983040 @ 0xf0000 800e2a0: 2b00 cmp r3, #0 800e2a2: d115 bne.n 800e2d0 { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800e2a4: 68fb ldr r3, [r7, #12] 800e2a6: 6a9b ldr r3, [r3, #40] @ 0x28 800e2a8: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 800e2ac: 68fb ldr r3, [r7, #12] 800e2ae: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800e2b0: 68fb ldr r3, [r7, #12] 800e2b2: 681b ldr r3, [r3, #0] 800e2b4: 685b ldr r3, [r3, #4] 800e2b6: f403 6380 and.w r3, r3, #1024 @ 0x400 800e2ba: 2b00 cmp r3, #0 800e2bc: d026 beq.n 800e30c { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800e2be: 68fb ldr r3, [r7, #12] 800e2c0: 6a9b ldr r3, [r3, #40] @ 0x28 800e2c2: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800e2c6: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800e2ca: 68fb ldr r3, [r7, #12] 800e2cc: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800e2ce: e01d b.n 800e30c } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800e2d0: 68fb ldr r3, [r7, #12] 800e2d2: 6a9b ldr r3, [r3, #40] @ 0x28 800e2d4: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800e2d8: 68fb ldr r3, [r7, #12] 800e2da: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 800e2dc: 68fb ldr r3, [r7, #12] 800e2de: 681b ldr r3, [r3, #0] 800e2e0: 4a39 ldr r2, [pc, #228] @ (800e3c8 ) 800e2e2: 4293 cmp r3, r2 800e2e4: d004 beq.n 800e2f0 800e2e6: 68fb ldr r3, [r7, #12] 800e2e8: 681b ldr r3, [r3, #0] 800e2ea: 4a38 ldr r2, [pc, #224] @ (800e3cc ) 800e2ec: 4293 cmp r3, r2 800e2ee: d10d bne.n 800e30c 800e2f0: 4b35 ldr r3, [pc, #212] @ (800e3c8 ) 800e2f2: 685b ldr r3, [r3, #4] 800e2f4: f403 6380 and.w r3, r3, #1024 @ 0x400 800e2f8: 2b00 cmp r3, #0 800e2fa: d007 beq.n 800e30c { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800e2fc: 68fb ldr r3, [r7, #12] 800e2fe: 6a9b ldr r3, [r3, #40] @ 0x28 800e300: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800e304: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800e308: 68fb ldr r3, [r7, #12] 800e30a: 629a str r2, [r3, #40] @ 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800e30c: 68fb ldr r3, [r7, #12] 800e30e: 6a9b ldr r3, [r3, #40] @ 0x28 800e310: f403 5380 and.w r3, r3, #4096 @ 0x1000 800e314: 2b00 cmp r3, #0 800e316: d006 beq.n 800e326 { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 800e318: 68fb ldr r3, [r7, #12] 800e31a: 6adb ldr r3, [r3, #44] @ 0x2c 800e31c: f023 0206 bic.w r2, r3, #6 800e320: 68fb ldr r3, [r7, #12] 800e322: 62da str r2, [r3, #44] @ 0x2c 800e324: e002 b.n 800e32c } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 800e326: 68fb ldr r3, [r7, #12] 800e328: 2200 movs r2, #0 800e32a: 62da str r2, [r3, #44] @ 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 800e32c: 68fb ldr r3, [r7, #12] 800e32e: 2200 movs r2, #0 800e330: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 800e334: 68fb ldr r3, [r7, #12] 800e336: 6a1b ldr r3, [r3, #32] 800e338: 4a25 ldr r2, [pc, #148] @ (800e3d0 ) 800e33a: 629a str r2, [r3, #40] @ 0x28 /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 800e33c: 68fb ldr r3, [r7, #12] 800e33e: 6a1b ldr r3, [r3, #32] 800e340: 4a24 ldr r2, [pc, #144] @ (800e3d4 ) 800e342: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 800e344: 68fb ldr r3, [r7, #12] 800e346: 6a1b ldr r3, [r3, #32] 800e348: 4a23 ldr r2, [pc, #140] @ (800e3d8 ) 800e34a: 631a str r2, [r3, #48] @ 0x30 /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 800e34c: 68fb ldr r3, [r7, #12] 800e34e: 681b ldr r3, [r3, #0] 800e350: f06f 0202 mvn.w r2, #2 800e354: 601a str r2, [r3, #0] /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); 800e356: 68fb ldr r3, [r7, #12] 800e358: 681b ldr r3, [r3, #0] 800e35a: 689a ldr r2, [r3, #8] 800e35c: 68fb ldr r3, [r7, #12] 800e35e: 681b ldr r3, [r3, #0] 800e360: f442 7280 orr.w r2, r2, #256 @ 0x100 800e364: 609a str r2, [r3, #8] /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 800e366: 68fb ldr r3, [r7, #12] 800e368: 6a18 ldr r0, [r3, #32] 800e36a: 68fb ldr r3, [r7, #12] 800e36c: 681b ldr r3, [r3, #0] 800e36e: 334c adds r3, #76 @ 0x4c 800e370: 4619 mov r1, r3 800e372: 68ba ldr r2, [r7, #8] 800e374: 687b ldr r3, [r7, #4] 800e376: f001 fc63 bl 800fc40 /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) 800e37a: 68fb ldr r3, [r7, #12] 800e37c: 681b ldr r3, [r3, #0] 800e37e: 689b ldr r3, [r3, #8] 800e380: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800e384: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e388: d108 bne.n 800e39c { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 800e38a: 68fb ldr r3, [r7, #12] 800e38c: 681b ldr r3, [r3, #0] 800e38e: 689a ldr r2, [r3, #8] 800e390: 68fb ldr r3, [r7, #12] 800e392: 681b ldr r3, [r3, #0] 800e394: f442 02a0 orr.w r2, r2, #5242880 @ 0x500000 800e398: 609a str r2, [r3, #8] if (tmp_hal_status == HAL_OK) 800e39a: e00f b.n 800e3bc } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 800e39c: 68fb ldr r3, [r7, #12] 800e39e: 681b ldr r3, [r3, #0] 800e3a0: 689a ldr r2, [r3, #8] 800e3a2: 68fb ldr r3, [r7, #12] 800e3a4: 681b ldr r3, [r3, #0] 800e3a6: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 800e3aa: 609a str r2, [r3, #8] if (tmp_hal_status == HAL_OK) 800e3ac: e006 b.n 800e3bc } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 800e3ae: 68fb ldr r3, [r7, #12] 800e3b0: 2200 movs r2, #0 800e3b2: f883 2024 strb.w r2, [r3, #36] @ 0x24 if (tmp_hal_status == HAL_OK) 800e3b6: e001 b.n 800e3bc } } else { tmp_hal_status = HAL_ERROR; 800e3b8: 2301 movs r3, #1 800e3ba: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800e3bc: 7dfb ldrb r3, [r7, #23] } 800e3be: 4618 mov r0, r3 800e3c0: 3718 adds r7, #24 800e3c2: 46bd mov sp, r7 800e3c4: bd80 pop {r7, pc} 800e3c6: bf00 nop 800e3c8: 40012400 .word 0x40012400 800e3cc: 40012800 .word 0x40012800 800e3d0: 0800e8b7 .word 0x0800e8b7 800e3d4: 0800e933 .word 0x0800e933 800e3d8: 0800e94f .word 0x0800e94f 0800e3dc : * @brief Handles ADC interrupt request * @param hadc: ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { 800e3dc: b580 push {r7, lr} 800e3de: b084 sub sp, #16 800e3e0: af00 add r7, sp, #0 800e3e2: 6078 str r0, [r7, #4] uint32_t tmp_sr = hadc->Instance->SR; 800e3e4: 687b ldr r3, [r7, #4] 800e3e6: 681b ldr r3, [r3, #0] 800e3e8: 681b ldr r3, [r3, #0] 800e3ea: 60fb str r3, [r7, #12] uint32_t tmp_cr1 = hadc->Instance->CR1; 800e3ec: 687b ldr r3, [r7, #4] 800e3ee: 681b ldr r3, [r3, #0] 800e3f0: 685b ldr r3, [r3, #4] 800e3f2: 60bb str r3, [r7, #8] assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); /* ========== Check End of Conversion flag for regular group ========== */ if((tmp_cr1 & ADC_IT_EOC) == ADC_IT_EOC) 800e3f4: 68bb ldr r3, [r7, #8] 800e3f6: f003 0320 and.w r3, r3, #32 800e3fa: 2b00 cmp r3, #0 800e3fc: d03e beq.n 800e47c { if((tmp_sr & ADC_FLAG_EOC) == ADC_FLAG_EOC) 800e3fe: 68fb ldr r3, [r7, #12] 800e400: f003 0302 and.w r3, r3, #2 800e404: 2b00 cmp r3, #0 800e406: d039 beq.n 800e47c { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 800e408: 687b ldr r3, [r7, #4] 800e40a: 6a9b ldr r3, [r3, #40] @ 0x28 800e40c: f003 0310 and.w r3, r3, #16 800e410: 2b00 cmp r3, #0 800e412: d105 bne.n 800e420 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800e414: 687b ldr r3, [r7, #4] 800e416: 6a9b ldr r3, [r3, #40] @ 0x28 800e418: f443 7200 orr.w r2, r3, #512 @ 0x200 800e41c: 687b ldr r3, [r7, #4] 800e41e: 629a str r2, [r3, #40] @ 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e420: 687b ldr r3, [r7, #4] 800e422: 681b ldr r3, [r3, #0] 800e424: 689b ldr r3, [r3, #8] 800e426: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800e42a: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e42e: d11d bne.n 800e46c (hadc->Init.ContinuousConvMode == DISABLE) ) 800e430: 687b ldr r3, [r7, #4] 800e432: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e434: 2b00 cmp r3, #0 800e436: d119 bne.n 800e46c { /* Disable ADC end of conversion interrupt on group regular */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); 800e438: 687b ldr r3, [r7, #4] 800e43a: 681b ldr r3, [r3, #0] 800e43c: 685a ldr r2, [r3, #4] 800e43e: 687b ldr r3, [r7, #4] 800e440: 681b ldr r3, [r3, #0] 800e442: f022 0220 bic.w r2, r2, #32 800e446: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800e448: 687b ldr r3, [r7, #4] 800e44a: 6a9b ldr r3, [r3, #40] @ 0x28 800e44c: f423 7280 bic.w r2, r3, #256 @ 0x100 800e450: 687b ldr r3, [r7, #4] 800e452: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800e454: 687b ldr r3, [r7, #4] 800e456: 6a9b ldr r3, [r3, #40] @ 0x28 800e458: f403 5380 and.w r3, r3, #4096 @ 0x1000 800e45c: 2b00 cmp r3, #0 800e45e: d105 bne.n 800e46c { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800e460: 687b ldr r3, [r7, #4] 800e462: 6a9b ldr r3, [r3, #40] @ 0x28 800e464: f043 0201 orr.w r2, r3, #1 800e468: 687b ldr r3, [r7, #4] 800e46a: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800e46c: 6878 ldr r0, [r7, #4] 800e46e: f7fb f86d bl 800954c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 800e472: 687b ldr r3, [r7, #4] 800e474: 681b ldr r3, [r3, #0] 800e476: f06f 0212 mvn.w r2, #18 800e47a: 601a str r2, [r3, #0] } } /* ========== Check End of Conversion flag for injected group ========== */ if((tmp_cr1 & ADC_IT_JEOC) == ADC_IT_JEOC) 800e47c: 68bb ldr r3, [r7, #8] 800e47e: f003 0380 and.w r3, r3, #128 @ 0x80 800e482: 2b00 cmp r3, #0 800e484: d04d beq.n 800e522 { if((tmp_sr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) 800e486: 68fb ldr r3, [r7, #12] 800e488: f003 0304 and.w r3, r3, #4 800e48c: 2b00 cmp r3, #0 800e48e: d048 beq.n 800e522 { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 800e490: 687b ldr r3, [r7, #4] 800e492: 6a9b ldr r3, [r3, #40] @ 0x28 800e494: f003 0310 and.w r3, r3, #16 800e498: 2b00 cmp r3, #0 800e49a: d105 bne.n 800e4a8 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 800e49c: 687b ldr r3, [r7, #4] 800e49e: 6a9b ldr r3, [r3, #40] @ 0x28 800e4a0: f443 5200 orr.w r2, r3, #8192 @ 0x2000 800e4a4: 687b ldr r3, [r7, #4] 800e4a6: 629a str r2, [r3, #40] @ 0x28 /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 800e4a8: 687b ldr r3, [r7, #4] 800e4aa: 681b ldr r3, [r3, #0] 800e4ac: 689b ldr r3, [r3, #8] 800e4ae: f403 43e0 and.w r3, r3, #28672 @ 0x7000 800e4b2: f5b3 4fe0 cmp.w r3, #28672 @ 0x7000 800e4b6: d012 beq.n 800e4de (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 800e4b8: 687b ldr r3, [r7, #4] 800e4ba: 681b ldr r3, [r3, #0] 800e4bc: 685b ldr r3, [r3, #4] 800e4be: f403 6380 and.w r3, r3, #1024 @ 0x400 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 800e4c2: 2b00 cmp r3, #0 800e4c4: d125 bne.n 800e512 (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e4c6: 687b ldr r3, [r7, #4] 800e4c8: 681b ldr r3, [r3, #0] 800e4ca: 689b ldr r3, [r3, #8] 800e4cc: f403 2360 and.w r3, r3, #917504 @ 0xe0000 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 800e4d0: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e4d4: d11d bne.n 800e512 (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) 800e4d6: 687b ldr r3, [r7, #4] 800e4d8: 7b1b ldrb r3, [r3, #12] (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e4da: 2b00 cmp r3, #0 800e4dc: d119 bne.n 800e512 { /* Disable ADC end of conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); 800e4de: 687b ldr r3, [r7, #4] 800e4e0: 681b ldr r3, [r3, #0] 800e4e2: 685a ldr r2, [r3, #4] 800e4e4: 687b ldr r3, [r7, #4] 800e4e6: 681b ldr r3, [r3, #0] 800e4e8: f022 0280 bic.w r2, r2, #128 @ 0x80 800e4ec: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 800e4ee: 687b ldr r3, [r7, #4] 800e4f0: 6a9b ldr r3, [r3, #40] @ 0x28 800e4f2: f423 5280 bic.w r2, r3, #4096 @ 0x1000 800e4f6: 687b ldr r3, [r7, #4] 800e4f8: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 800e4fa: 687b ldr r3, [r7, #4] 800e4fc: 6a9b ldr r3, [r3, #40] @ 0x28 800e4fe: f403 7380 and.w r3, r3, #256 @ 0x100 800e502: 2b00 cmp r3, #0 800e504: d105 bne.n 800e512 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800e506: 687b ldr r3, [r7, #4] 800e508: 6a9b ldr r3, [r3, #40] @ 0x28 800e50a: f043 0201 orr.w r2, r3, #1 800e50e: 687b ldr r3, [r7, #4] 800e510: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); 800e512: 6878 ldr r0, [r7, #4] 800e514: f000 fae4 bl 800eae0 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); 800e518: 687b ldr r3, [r7, #4] 800e51a: 681b ldr r3, [r3, #0] 800e51c: f06f 020c mvn.w r2, #12 800e520: 601a str r2, [r3, #0] } } /* ========== Check Analog watchdog flags ========== */ if((tmp_cr1 & ADC_IT_AWD) == ADC_IT_AWD) 800e522: 68bb ldr r3, [r7, #8] 800e524: f003 0340 and.w r3, r3, #64 @ 0x40 800e528: 2b00 cmp r3, #0 800e52a: d012 beq.n 800e552 { if((tmp_sr & ADC_FLAG_AWD) == ADC_FLAG_AWD) 800e52c: 68fb ldr r3, [r7, #12] 800e52e: f003 0301 and.w r3, r3, #1 800e532: 2b00 cmp r3, #0 800e534: d00d beq.n 800e552 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); 800e536: 687b ldr r3, [r7, #4] 800e538: 6a9b ldr r3, [r3, #40] @ 0x28 800e53a: f443 3280 orr.w r2, r3, #65536 @ 0x10000 800e53e: 687b ldr r3, [r7, #4] 800e540: 629a str r2, [r3, #40] @ 0x28 /* Level out of window callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); 800e542: 6878 ldr r0, [r7, #4] 800e544: f000 f812 bl 800e56c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear the ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); 800e548: 687b ldr r3, [r7, #4] 800e54a: 681b ldr r3, [r3, #0] 800e54c: f06f 0201 mvn.w r2, #1 800e550: 601a str r2, [r3, #0] } } } 800e552: bf00 nop 800e554: 3710 adds r7, #16 800e556: 46bd mov sp, r7 800e558: bd80 pop {r7, pc} 0800e55a : * @brief Conversion DMA half-transfer callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) { 800e55a: b480 push {r7} 800e55c: b083 sub sp, #12 800e55e: af00 add r7, sp, #0 800e560: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 800e562: bf00 nop 800e564: 370c adds r7, #12 800e566: 46bd mov sp, r7 800e568: bc80 pop {r7} 800e56a: 4770 bx lr 0800e56c : * @brief Analog watchdog callback in non blocking mode. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { 800e56c: b480 push {r7} 800e56e: b083 sub sp, #12 800e570: af00 add r7, sp, #0 800e572: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ } 800e574: bf00 nop 800e576: 370c adds r7, #12 800e578: 46bd mov sp, r7 800e57a: bc80 pop {r7} 800e57c: 4770 bx lr 0800e57e : * (ADC conversion with interruption or transfer by DMA) * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 800e57e: b480 push {r7} 800e580: b083 sub sp, #12 800e582: af00 add r7, sp, #0 800e584: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 800e586: bf00 nop 800e588: 370c adds r7, #12 800e58a: 46bd mov sp, r7 800e58c: bc80 pop {r7} 800e58e: 4770 bx lr 0800e590 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 800e590: b480 push {r7} 800e592: b085 sub sp, #20 800e594: af00 add r7, sp, #0 800e596: 6078 str r0, [r7, #4] 800e598: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e59a: 2300 movs r3, #0 800e59c: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 800e59e: 2300 movs r3, #0 800e5a0: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 800e5a2: 687b ldr r3, [r7, #4] 800e5a4: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800e5a8: 2b01 cmp r3, #1 800e5aa: d101 bne.n 800e5b0 800e5ac: 2302 movs r3, #2 800e5ae: e0dc b.n 800e76a 800e5b0: 687b ldr r3, [r7, #4] 800e5b2: 2201 movs r2, #1 800e5b4: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 800e5b8: 683b ldr r3, [r7, #0] 800e5ba: 685b ldr r3, [r3, #4] 800e5bc: 2b06 cmp r3, #6 800e5be: d81c bhi.n 800e5fa { MODIFY_REG(hadc->Instance->SQR3 , 800e5c0: 687b ldr r3, [r7, #4] 800e5c2: 681b ldr r3, [r3, #0] 800e5c4: 6b59 ldr r1, [r3, #52] @ 0x34 800e5c6: 683b ldr r3, [r7, #0] 800e5c8: 685a ldr r2, [r3, #4] 800e5ca: 4613 mov r3, r2 800e5cc: 009b lsls r3, r3, #2 800e5ce: 4413 add r3, r2 800e5d0: 3b05 subs r3, #5 800e5d2: 221f movs r2, #31 800e5d4: fa02 f303 lsl.w r3, r2, r3 800e5d8: 43db mvns r3, r3 800e5da: 4019 ands r1, r3 800e5dc: 683b ldr r3, [r7, #0] 800e5de: 6818 ldr r0, [r3, #0] 800e5e0: 683b ldr r3, [r7, #0] 800e5e2: 685a ldr r2, [r3, #4] 800e5e4: 4613 mov r3, r2 800e5e6: 009b lsls r3, r3, #2 800e5e8: 4413 add r3, r2 800e5ea: 3b05 subs r3, #5 800e5ec: fa00 f203 lsl.w r2, r0, r3 800e5f0: 687b ldr r3, [r7, #4] 800e5f2: 681b ldr r3, [r3, #0] 800e5f4: 430a orrs r2, r1 800e5f6: 635a str r2, [r3, #52] @ 0x34 800e5f8: e03c b.n 800e674 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 800e5fa: 683b ldr r3, [r7, #0] 800e5fc: 685b ldr r3, [r3, #4] 800e5fe: 2b0c cmp r3, #12 800e600: d81c bhi.n 800e63c { MODIFY_REG(hadc->Instance->SQR2 , 800e602: 687b ldr r3, [r7, #4] 800e604: 681b ldr r3, [r3, #0] 800e606: 6b19 ldr r1, [r3, #48] @ 0x30 800e608: 683b ldr r3, [r7, #0] 800e60a: 685a ldr r2, [r3, #4] 800e60c: 4613 mov r3, r2 800e60e: 009b lsls r3, r3, #2 800e610: 4413 add r3, r2 800e612: 3b23 subs r3, #35 @ 0x23 800e614: 221f movs r2, #31 800e616: fa02 f303 lsl.w r3, r2, r3 800e61a: 43db mvns r3, r3 800e61c: 4019 ands r1, r3 800e61e: 683b ldr r3, [r7, #0] 800e620: 6818 ldr r0, [r3, #0] 800e622: 683b ldr r3, [r7, #0] 800e624: 685a ldr r2, [r3, #4] 800e626: 4613 mov r3, r2 800e628: 009b lsls r3, r3, #2 800e62a: 4413 add r3, r2 800e62c: 3b23 subs r3, #35 @ 0x23 800e62e: fa00 f203 lsl.w r2, r0, r3 800e632: 687b ldr r3, [r7, #4] 800e634: 681b ldr r3, [r3, #0] 800e636: 430a orrs r2, r1 800e638: 631a str r2, [r3, #48] @ 0x30 800e63a: e01b b.n 800e674 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 800e63c: 687b ldr r3, [r7, #4] 800e63e: 681b ldr r3, [r3, #0] 800e640: 6ad9 ldr r1, [r3, #44] @ 0x2c 800e642: 683b ldr r3, [r7, #0] 800e644: 685a ldr r2, [r3, #4] 800e646: 4613 mov r3, r2 800e648: 009b lsls r3, r3, #2 800e64a: 4413 add r3, r2 800e64c: 3b41 subs r3, #65 @ 0x41 800e64e: 221f movs r2, #31 800e650: fa02 f303 lsl.w r3, r2, r3 800e654: 43db mvns r3, r3 800e656: 4019 ands r1, r3 800e658: 683b ldr r3, [r7, #0] 800e65a: 6818 ldr r0, [r3, #0] 800e65c: 683b ldr r3, [r7, #0] 800e65e: 685a ldr r2, [r3, #4] 800e660: 4613 mov r3, r2 800e662: 009b lsls r3, r3, #2 800e664: 4413 add r3, r2 800e666: 3b41 subs r3, #65 @ 0x41 800e668: fa00 f203 lsl.w r2, r0, r3 800e66c: 687b ldr r3, [r7, #4] 800e66e: 681b ldr r3, [r3, #0] 800e670: 430a orrs r2, r1 800e672: 62da str r2, [r3, #44] @ 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 800e674: 683b ldr r3, [r7, #0] 800e676: 681b ldr r3, [r3, #0] 800e678: 2b09 cmp r3, #9 800e67a: d91c bls.n 800e6b6 { MODIFY_REG(hadc->Instance->SMPR1 , 800e67c: 687b ldr r3, [r7, #4] 800e67e: 681b ldr r3, [r3, #0] 800e680: 68d9 ldr r1, [r3, #12] 800e682: 683b ldr r3, [r7, #0] 800e684: 681a ldr r2, [r3, #0] 800e686: 4613 mov r3, r2 800e688: 005b lsls r3, r3, #1 800e68a: 4413 add r3, r2 800e68c: 3b1e subs r3, #30 800e68e: 2207 movs r2, #7 800e690: fa02 f303 lsl.w r3, r2, r3 800e694: 43db mvns r3, r3 800e696: 4019 ands r1, r3 800e698: 683b ldr r3, [r7, #0] 800e69a: 6898 ldr r0, [r3, #8] 800e69c: 683b ldr r3, [r7, #0] 800e69e: 681a ldr r2, [r3, #0] 800e6a0: 4613 mov r3, r2 800e6a2: 005b lsls r3, r3, #1 800e6a4: 4413 add r3, r2 800e6a6: 3b1e subs r3, #30 800e6a8: fa00 f203 lsl.w r2, r0, r3 800e6ac: 687b ldr r3, [r7, #4] 800e6ae: 681b ldr r3, [r3, #0] 800e6b0: 430a orrs r2, r1 800e6b2: 60da str r2, [r3, #12] 800e6b4: e019 b.n 800e6ea ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 800e6b6: 687b ldr r3, [r7, #4] 800e6b8: 681b ldr r3, [r3, #0] 800e6ba: 6919 ldr r1, [r3, #16] 800e6bc: 683b ldr r3, [r7, #0] 800e6be: 681a ldr r2, [r3, #0] 800e6c0: 4613 mov r3, r2 800e6c2: 005b lsls r3, r3, #1 800e6c4: 4413 add r3, r2 800e6c6: 2207 movs r2, #7 800e6c8: fa02 f303 lsl.w r3, r2, r3 800e6cc: 43db mvns r3, r3 800e6ce: 4019 ands r1, r3 800e6d0: 683b ldr r3, [r7, #0] 800e6d2: 6898 ldr r0, [r3, #8] 800e6d4: 683b ldr r3, [r7, #0] 800e6d6: 681a ldr r2, [r3, #0] 800e6d8: 4613 mov r3, r2 800e6da: 005b lsls r3, r3, #1 800e6dc: 4413 add r3, r2 800e6de: fa00 f203 lsl.w r2, r0, r3 800e6e2: 687b ldr r3, [r7, #4] 800e6e4: 681b ldr r3, [r3, #0] 800e6e6: 430a orrs r2, r1 800e6e8: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800e6ea: 683b ldr r3, [r7, #0] 800e6ec: 681b ldr r3, [r3, #0] 800e6ee: 2b10 cmp r3, #16 800e6f0: d003 beq.n 800e6fa (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 800e6f2: 683b ldr r3, [r7, #0] 800e6f4: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800e6f6: 2b11 cmp r3, #17 800e6f8: d132 bne.n 800e760 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 800e6fa: 687b ldr r3, [r7, #4] 800e6fc: 681b ldr r3, [r3, #0] 800e6fe: 4a1d ldr r2, [pc, #116] @ (800e774 ) 800e700: 4293 cmp r3, r2 800e702: d125 bne.n 800e750 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 800e704: 687b ldr r3, [r7, #4] 800e706: 681b ldr r3, [r3, #0] 800e708: 689b ldr r3, [r3, #8] 800e70a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800e70e: 2b00 cmp r3, #0 800e710: d126 bne.n 800e760 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 800e712: 687b ldr r3, [r7, #4] 800e714: 681b ldr r3, [r3, #0] 800e716: 689a ldr r2, [r3, #8] 800e718: 687b ldr r3, [r7, #4] 800e71a: 681b ldr r3, [r3, #0] 800e71c: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 800e720: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 800e722: 683b ldr r3, [r7, #0] 800e724: 681b ldr r3, [r3, #0] 800e726: 2b10 cmp r3, #16 800e728: d11a bne.n 800e760 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 800e72a: 4b13 ldr r3, [pc, #76] @ (800e778 ) 800e72c: 681b ldr r3, [r3, #0] 800e72e: 4a13 ldr r2, [pc, #76] @ (800e77c ) 800e730: fba2 2303 umull r2, r3, r2, r3 800e734: 0c9a lsrs r2, r3, #18 800e736: 4613 mov r3, r2 800e738: 009b lsls r3, r3, #2 800e73a: 4413 add r3, r2 800e73c: 005b lsls r3, r3, #1 800e73e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e740: e002 b.n 800e748 { wait_loop_index--; 800e742: 68bb ldr r3, [r7, #8] 800e744: 3b01 subs r3, #1 800e746: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e748: 68bb ldr r3, [r7, #8] 800e74a: 2b00 cmp r3, #0 800e74c: d1f9 bne.n 800e742 800e74e: e007 b.n 800e760 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800e750: 687b ldr r3, [r7, #4] 800e752: 6a9b ldr r3, [r3, #40] @ 0x28 800e754: f043 0220 orr.w r2, r3, #32 800e758: 687b ldr r3, [r7, #4] 800e75a: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800e75c: 2301 movs r3, #1 800e75e: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 800e760: 687b ldr r3, [r7, #4] 800e762: 2200 movs r2, #0 800e764: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800e768: 7bfb ldrb r3, [r7, #15] } 800e76a: 4618 mov r0, r3 800e76c: 3714 adds r7, #20 800e76e: 46bd mov sp, r7 800e770: bc80 pop {r7} 800e772: 4770 bx lr 800e774: 40012400 .word 0x40012400 800e778: 20000084 .word 0x20000084 800e77c: 431bde83 .word 0x431bde83 0800e780 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 800e780: b580 push {r7, lr} 800e782: b084 sub sp, #16 800e784: af00 add r7, sp, #0 800e786: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800e788: 2300 movs r3, #0 800e78a: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 800e78c: 2300 movs r3, #0 800e78e: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 800e790: 687b ldr r3, [r7, #4] 800e792: 681b ldr r3, [r3, #0] 800e794: 689b ldr r3, [r3, #8] 800e796: f003 0301 and.w r3, r3, #1 800e79a: 2b01 cmp r3, #1 800e79c: d040 beq.n 800e820 { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 800e79e: 687b ldr r3, [r7, #4] 800e7a0: 681b ldr r3, [r3, #0] 800e7a2: 689a ldr r2, [r3, #8] 800e7a4: 687b ldr r3, [r7, #4] 800e7a6: 681b ldr r3, [r3, #0] 800e7a8: f042 0201 orr.w r2, r2, #1 800e7ac: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 800e7ae: 4b1f ldr r3, [pc, #124] @ (800e82c ) 800e7b0: 681b ldr r3, [r3, #0] 800e7b2: 4a1f ldr r2, [pc, #124] @ (800e830 ) 800e7b4: fba2 2303 umull r2, r3, r2, r3 800e7b8: 0c9b lsrs r3, r3, #18 800e7ba: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e7bc: e002 b.n 800e7c4 { wait_loop_index--; 800e7be: 68bb ldr r3, [r7, #8] 800e7c0: 3b01 subs r3, #1 800e7c2: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e7c4: 68bb ldr r3, [r7, #8] 800e7c6: 2b00 cmp r3, #0 800e7c8: d1f9 bne.n 800e7be } /* Get tick count */ tickstart = HAL_GetTick(); 800e7ca: f7ff fc23 bl 800e014 800e7ce: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 800e7d0: e01f b.n 800e812 { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 800e7d2: f7ff fc1f bl 800e014 800e7d6: 4602 mov r2, r0 800e7d8: 68fb ldr r3, [r7, #12] 800e7da: 1ad3 subs r3, r2, r3 800e7dc: 2b02 cmp r3, #2 800e7de: d918 bls.n 800e812 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) 800e7e0: 687b ldr r3, [r7, #4] 800e7e2: 681b ldr r3, [r3, #0] 800e7e4: 689b ldr r3, [r3, #8] 800e7e6: f003 0301 and.w r3, r3, #1 800e7ea: 2b01 cmp r3, #1 800e7ec: d011 beq.n 800e812 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800e7ee: 687b ldr r3, [r7, #4] 800e7f0: 6a9b ldr r3, [r3, #40] @ 0x28 800e7f2: f043 0210 orr.w r2, r3, #16 800e7f6: 687b ldr r3, [r7, #4] 800e7f8: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e7fa: 687b ldr r3, [r7, #4] 800e7fc: 6adb ldr r3, [r3, #44] @ 0x2c 800e7fe: f043 0201 orr.w r2, r3, #1 800e802: 687b ldr r3, [r7, #4] 800e804: 62da str r2, [r3, #44] @ 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 800e806: 687b ldr r3, [r7, #4] 800e808: 2200 movs r2, #0 800e80a: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e80e: 2301 movs r3, #1 800e810: e007 b.n 800e822 while(ADC_IS_ENABLE(hadc) == RESET) 800e812: 687b ldr r3, [r7, #4] 800e814: 681b ldr r3, [r3, #0] 800e816: 689b ldr r3, [r3, #8] 800e818: f003 0301 and.w r3, r3, #1 800e81c: 2b01 cmp r3, #1 800e81e: d1d8 bne.n 800e7d2 } } } /* Return HAL status */ return HAL_OK; 800e820: 2300 movs r3, #0 } 800e822: 4618 mov r0, r3 800e824: 3710 adds r7, #16 800e826: 46bd mov sp, r7 800e828: bd80 pop {r7, pc} 800e82a: bf00 nop 800e82c: 20000084 .word 0x20000084 800e830: 431bde83 .word 0x431bde83 0800e834 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 800e834: b580 push {r7, lr} 800e836: b084 sub sp, #16 800e838: af00 add r7, sp, #0 800e83a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800e83c: 2300 movs r3, #0 800e83e: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 800e840: 687b ldr r3, [r7, #4] 800e842: 681b ldr r3, [r3, #0] 800e844: 689b ldr r3, [r3, #8] 800e846: f003 0301 and.w r3, r3, #1 800e84a: 2b01 cmp r3, #1 800e84c: d12e bne.n 800e8ac { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 800e84e: 687b ldr r3, [r7, #4] 800e850: 681b ldr r3, [r3, #0] 800e852: 689a ldr r2, [r3, #8] 800e854: 687b ldr r3, [r7, #4] 800e856: 681b ldr r3, [r3, #0] 800e858: f022 0201 bic.w r2, r2, #1 800e85c: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 800e85e: f7ff fbd9 bl 800e014 800e862: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 800e864: e01b b.n 800e89e { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800e866: f7ff fbd5 bl 800e014 800e86a: 4602 mov r2, r0 800e86c: 68fb ldr r3, [r7, #12] 800e86e: 1ad3 subs r3, r2, r3 800e870: 2b02 cmp r3, #2 800e872: d914 bls.n 800e89e { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 800e874: 687b ldr r3, [r7, #4] 800e876: 681b ldr r3, [r3, #0] 800e878: 689b ldr r3, [r3, #8] 800e87a: f003 0301 and.w r3, r3, #1 800e87e: 2b01 cmp r3, #1 800e880: d10d bne.n 800e89e { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800e882: 687b ldr r3, [r7, #4] 800e884: 6a9b ldr r3, [r3, #40] @ 0x28 800e886: f043 0210 orr.w r2, r3, #16 800e88a: 687b ldr r3, [r7, #4] 800e88c: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e88e: 687b ldr r3, [r7, #4] 800e890: 6adb ldr r3, [r3, #44] @ 0x2c 800e892: f043 0201 orr.w r2, r3, #1 800e896: 687b ldr r3, [r7, #4] 800e898: 62da str r2, [r3, #44] @ 0x2c return HAL_ERROR; 800e89a: 2301 movs r3, #1 800e89c: e007 b.n 800e8ae while(ADC_IS_ENABLE(hadc) != RESET) 800e89e: 687b ldr r3, [r7, #4] 800e8a0: 681b ldr r3, [r3, #0] 800e8a2: 689b ldr r3, [r3, #8] 800e8a4: f003 0301 and.w r3, r3, #1 800e8a8: 2b01 cmp r3, #1 800e8aa: d0dc beq.n 800e866 } } } /* Return HAL status */ return HAL_OK; 800e8ac: 2300 movs r3, #0 } 800e8ae: 4618 mov r0, r3 800e8b0: 3710 adds r7, #16 800e8b2: 46bd mov sp, r7 800e8b4: bd80 pop {r7, pc} 0800e8b6 : * @brief DMA transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 800e8b6: b580 push {r7, lr} 800e8b8: b084 sub sp, #16 800e8ba: af00 add r7, sp, #0 800e8bc: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800e8be: 687b ldr r3, [r7, #4] 800e8c0: 6a5b ldr r3, [r3, #36] @ 0x24 800e8c2: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) 800e8c4: 68fb ldr r3, [r7, #12] 800e8c6: 6a9b ldr r3, [r3, #40] @ 0x28 800e8c8: f003 0350 and.w r3, r3, #80 @ 0x50 800e8cc: 2b00 cmp r3, #0 800e8ce: d127 bne.n 800e920 { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800e8d0: 68fb ldr r3, [r7, #12] 800e8d2: 6a9b ldr r3, [r3, #40] @ 0x28 800e8d4: f443 7200 orr.w r2, r3, #512 @ 0x200 800e8d8: 68fb ldr r3, [r7, #12] 800e8da: 629a str r2, [r3, #40] @ 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e8dc: 68fb ldr r3, [r7, #12] 800e8de: 681b ldr r3, [r3, #0] 800e8e0: 689b ldr r3, [r3, #8] 800e8e2: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800e8e6: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e8ea: d115 bne.n 800e918 (hadc->Init.ContinuousConvMode == DISABLE) ) 800e8ec: 68fb ldr r3, [r7, #12] 800e8ee: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e8f0: 2b00 cmp r3, #0 800e8f2: d111 bne.n 800e918 { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800e8f4: 68fb ldr r3, [r7, #12] 800e8f6: 6a9b ldr r3, [r3, #40] @ 0x28 800e8f8: f423 7280 bic.w r2, r3, #256 @ 0x100 800e8fc: 68fb ldr r3, [r7, #12] 800e8fe: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800e900: 68fb ldr r3, [r7, #12] 800e902: 6a9b ldr r3, [r3, #40] @ 0x28 800e904: f403 5380 and.w r3, r3, #4096 @ 0x1000 800e908: 2b00 cmp r3, #0 800e90a: d105 bne.n 800e918 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800e90c: 68fb ldr r3, [r7, #12] 800e90e: 6a9b ldr r3, [r3, #40] @ 0x28 800e910: f043 0201 orr.w r2, r3, #1 800e914: 68fb ldr r3, [r7, #12] 800e916: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800e918: 68f8 ldr r0, [r7, #12] 800e91a: f7fa fe17 bl 800954c else { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } 800e91e: e004 b.n 800e92a hadc->DMA_Handle->XferErrorCallback(hdma); 800e920: 68fb ldr r3, [r7, #12] 800e922: 6a1b ldr r3, [r3, #32] 800e924: 6b1b ldr r3, [r3, #48] @ 0x30 800e926: 6878 ldr r0, [r7, #4] 800e928: 4798 blx r3 } 800e92a: bf00 nop 800e92c: 3710 adds r7, #16 800e92e: 46bd mov sp, r7 800e930: bd80 pop {r7, pc} 0800e932 : * @brief DMA half transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 800e932: b580 push {r7, lr} 800e934: b084 sub sp, #16 800e936: af00 add r7, sp, #0 800e938: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800e93a: 687b ldr r3, [r7, #4] 800e93c: 6a5b ldr r3, [r3, #36] @ 0x24 800e93e: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 800e940: 68f8 ldr r0, [r7, #12] 800e942: f7ff fe0a bl 800e55a #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800e946: bf00 nop 800e948: 3710 adds r7, #16 800e94a: 46bd mov sp, r7 800e94c: bd80 pop {r7, pc} 0800e94e : * @brief DMA error callback * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 800e94e: b580 push {r7, lr} 800e950: b084 sub sp, #16 800e952: af00 add r7, sp, #0 800e954: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800e956: 687b ldr r3, [r7, #4] 800e958: 6a5b ldr r3, [r3, #36] @ 0x24 800e95a: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 800e95c: 68fb ldr r3, [r7, #12] 800e95e: 6a9b ldr r3, [r3, #40] @ 0x28 800e960: f043 0240 orr.w r2, r3, #64 @ 0x40 800e964: 68fb ldr r3, [r7, #12] 800e966: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 800e968: 68fb ldr r3, [r7, #12] 800e96a: 6adb ldr r3, [r3, #44] @ 0x2c 800e96c: f043 0204 orr.w r2, r3, #4 800e970: 68fb ldr r3, [r7, #12] 800e972: 62da str r2, [r3, #44] @ 0x2c /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 800e974: 68f8 ldr r0, [r7, #12] 800e976: f7ff fe02 bl 800e57e #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800e97a: bf00 nop 800e97c: 3710 adds r7, #16 800e97e: 46bd mov sp, r7 800e980: bd80 pop {r7, pc} ... 0800e984 : * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { 800e984: b590 push {r4, r7, lr} 800e986: b087 sub sp, #28 800e988: af00 add r7, sp, #0 800e98a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e98c: 2300 movs r3, #0 800e98e: 75fb strb r3, [r7, #23] uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; 800e990: 2300 movs r3, #0 800e992: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800e994: 687b ldr r3, [r7, #4] 800e996: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800e99a: 2b01 cmp r3, #1 800e99c: d101 bne.n 800e9a2 800e99e: 2302 movs r3, #2 800e9a0: e097 b.n 800ead2 800e9a2: 687b ldr r3, [r7, #4] 800e9a4: 2201 movs r2, #1 800e9a6: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* 1. Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800e9aa: 6878 ldr r0, [r7, #4] 800e9ac: f7ff ff42 bl 800e834 800e9b0: 4603 mov r3, r0 800e9b2: 75fb strb r3, [r7, #23] /* 2. Calibration prerequisite delay before starting the calibration. */ /* - ADC must be enabled for at least two ADC clock cycles */ tmp_hal_status = ADC_Enable(hadc); 800e9b4: 6878 ldr r0, [r7, #4] 800e9b6: f7ff fee3 bl 800e780 800e9ba: 4603 mov r3, r0 800e9bc: 75fb strb r3, [r7, #23] /* Check if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800e9be: 7dfb ldrb r3, [r7, #23] 800e9c0: 2b00 cmp r3, #0 800e9c2: f040 8081 bne.w 800eac8 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e9c6: 687b ldr r3, [r7, #4] 800e9c8: 6a9b ldr r3, [r3, #40] @ 0x28 800e9ca: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800e9ce: f023 0302 bic.w r3, r3, #2 800e9d2: f043 0202 orr.w r2, r3, #2 800e9d6: 687b ldr r3, [r7, #4] 800e9d8: 629a str r2, [r3, #40] @ 0x28 /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 800e9da: 4b40 ldr r3, [pc, #256] @ (800eadc ) 800e9dc: 681c ldr r4, [r3, #0] 800e9de: 2002 movs r0, #2 800e9e0: f002 fec6 bl 8011770 800e9e4: 4603 mov r3, r0 800e9e6: fbb4 f3f3 udiv r3, r4, r3 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); 800e9ea: 005b lsls r3, r3, #1 wait_loop_index = ((SystemCoreClock 800e9ec: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800e9ee: e002 b.n 800e9f6 { wait_loop_index--; 800e9f0: 68fb ldr r3, [r7, #12] 800e9f2: 3b01 subs r3, #1 800e9f4: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800e9f6: 68fb ldr r3, [r7, #12] 800e9f8: 2b00 cmp r3, #0 800e9fa: d1f9 bne.n 800e9f0 } /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); 800e9fc: 687b ldr r3, [r7, #4] 800e9fe: 681b ldr r3, [r3, #0] 800ea00: 689a ldr r2, [r3, #8] 800ea02: 687b ldr r3, [r7, #4] 800ea04: 681b ldr r3, [r3, #0] 800ea06: f042 0208 orr.w r2, r2, #8 800ea0a: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800ea0c: f7ff fb02 bl 800e014 800ea10: 6138 str r0, [r7, #16] /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800ea12: e01b b.n 800ea4c { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800ea14: f7ff fafe bl 800e014 800ea18: 4602 mov r2, r0 800ea1a: 693b ldr r3, [r7, #16] 800ea1c: 1ad3 subs r3, r2, r3 800ea1e: 2b0a cmp r3, #10 800ea20: d914 bls.n 800ea4c { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800ea22: 687b ldr r3, [r7, #4] 800ea24: 681b ldr r3, [r3, #0] 800ea26: 689b ldr r3, [r3, #8] 800ea28: f003 0308 and.w r3, r3, #8 800ea2c: 2b00 cmp r3, #0 800ea2e: d00d beq.n 800ea4c { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800ea30: 687b ldr r3, [r7, #4] 800ea32: 6a9b ldr r3, [r3, #40] @ 0x28 800ea34: f023 0312 bic.w r3, r3, #18 800ea38: f043 0210 orr.w r2, r3, #16 800ea3c: 687b ldr r3, [r7, #4] 800ea3e: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800ea40: 687b ldr r3, [r7, #4] 800ea42: 2200 movs r2, #0 800ea44: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ea48: 2301 movs r3, #1 800ea4a: e042 b.n 800ead2 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800ea4c: 687b ldr r3, [r7, #4] 800ea4e: 681b ldr r3, [r3, #0] 800ea50: 689b ldr r3, [r3, #8] 800ea52: f003 0308 and.w r3, r3, #8 800ea56: 2b00 cmp r3, #0 800ea58: d1dc bne.n 800ea14 } } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); 800ea5a: 687b ldr r3, [r7, #4] 800ea5c: 681b ldr r3, [r3, #0] 800ea5e: 689a ldr r2, [r3, #8] 800ea60: 687b ldr r3, [r7, #4] 800ea62: 681b ldr r3, [r3, #0] 800ea64: f042 0204 orr.w r2, r2, #4 800ea68: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800ea6a: f7ff fad3 bl 800e014 800ea6e: 6138 str r0, [r7, #16] /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800ea70: e01b b.n 800eaaa { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800ea72: f7ff facf bl 800e014 800ea76: 4602 mov r2, r0 800ea78: 693b ldr r3, [r7, #16] 800ea7a: 1ad3 subs r3, r2, r3 800ea7c: 2b0a cmp r3, #10 800ea7e: d914 bls.n 800eaaa { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800ea80: 687b ldr r3, [r7, #4] 800ea82: 681b ldr r3, [r3, #0] 800ea84: 689b ldr r3, [r3, #8] 800ea86: f003 0304 and.w r3, r3, #4 800ea8a: 2b00 cmp r3, #0 800ea8c: d00d beq.n 800eaaa { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800ea8e: 687b ldr r3, [r7, #4] 800ea90: 6a9b ldr r3, [r3, #40] @ 0x28 800ea92: f023 0312 bic.w r3, r3, #18 800ea96: f043 0210 orr.w r2, r3, #16 800ea9a: 687b ldr r3, [r7, #4] 800ea9c: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800ea9e: 687b ldr r3, [r7, #4] 800eaa0: 2200 movs r2, #0 800eaa2: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800eaa6: 2301 movs r3, #1 800eaa8: e013 b.n 800ead2 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800eaaa: 687b ldr r3, [r7, #4] 800eaac: 681b ldr r3, [r3, #0] 800eaae: 689b ldr r3, [r3, #8] 800eab0: f003 0304 and.w r3, r3, #4 800eab4: 2b00 cmp r3, #0 800eab6: d1dc bne.n 800ea72 } } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800eab8: 687b ldr r3, [r7, #4] 800eaba: 6a9b ldr r3, [r3, #40] @ 0x28 800eabc: f023 0303 bic.w r3, r3, #3 800eac0: f043 0201 orr.w r2, r3, #1 800eac4: 687b ldr r3, [r7, #4] 800eac6: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 800eac8: 687b ldr r3, [r7, #4] 800eaca: 2200 movs r2, #0 800eacc: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800ead0: 7dfb ldrb r3, [r7, #23] } 800ead2: 4618 mov r0, r3 800ead4: 371c adds r7, #28 800ead6: 46bd mov sp, r7 800ead8: bd90 pop {r4, r7, pc} 800eada: bf00 nop 800eadc: 20000084 .word 0x20000084 0800eae0 : * @brief Injected conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { 800eae0: b480 push {r7} 800eae2: b083 sub sp, #12 800eae4: af00 add r7, sp, #0 800eae6: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } 800eae8: bf00 nop 800eaea: 370c adds r7, #12 800eaec: 46bd mov sp, r7 800eaee: bc80 pop {r7} 800eaf0: 4770 bx lr 0800eaf2 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { 800eaf2: b580 push {r7, lr} 800eaf4: b084 sub sp, #16 800eaf6: af00 add r7, sp, #0 800eaf8: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) 800eafa: 687b ldr r3, [r7, #4] 800eafc: 2b00 cmp r3, #0 800eafe: d101 bne.n 800eb04 { return HAL_ERROR; 800eb00: 2301 movs r3, #1 800eb02: e0ed b.n 800ece0 /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); } #else if (hcan->State == HAL_CAN_STATE_RESET) 800eb04: 687b ldr r3, [r7, #4] 800eb06: f893 3020 ldrb.w r3, [r3, #32] 800eb0a: b2db uxtb r3, r3 800eb0c: 2b00 cmp r3, #0 800eb0e: d102 bne.n 800eb16 { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); 800eb10: 6878 ldr r0, [r7, #4] 800eb12: f7fb f881 bl 8009c18 } #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800eb16: 687b ldr r3, [r7, #4] 800eb18: 681b ldr r3, [r3, #0] 800eb1a: 681a ldr r2, [r3, #0] 800eb1c: 687b ldr r3, [r7, #4] 800eb1e: 681b ldr r3, [r3, #0] 800eb20: f042 0201 orr.w r2, r2, #1 800eb24: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800eb26: f7ff fa75 bl 800e014 800eb2a: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800eb2c: e012 b.n 800eb54 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800eb2e: f7ff fa71 bl 800e014 800eb32: 4602 mov r2, r0 800eb34: 68fb ldr r3, [r7, #12] 800eb36: 1ad3 subs r3, r2, r3 800eb38: 2b0a cmp r3, #10 800eb3a: d90b bls.n 800eb54 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800eb3c: 687b ldr r3, [r7, #4] 800eb3e: 6a5b ldr r3, [r3, #36] @ 0x24 800eb40: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800eb44: 687b ldr r3, [r7, #4] 800eb46: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800eb48: 687b ldr r3, [r7, #4] 800eb4a: 2205 movs r2, #5 800eb4c: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800eb50: 2301 movs r3, #1 800eb52: e0c5 b.n 800ece0 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800eb54: 687b ldr r3, [r7, #4] 800eb56: 681b ldr r3, [r3, #0] 800eb58: 685b ldr r3, [r3, #4] 800eb5a: f003 0301 and.w r3, r3, #1 800eb5e: 2b00 cmp r3, #0 800eb60: d0e5 beq.n 800eb2e } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800eb62: 687b ldr r3, [r7, #4] 800eb64: 681b ldr r3, [r3, #0] 800eb66: 681a ldr r2, [r3, #0] 800eb68: 687b ldr r3, [r7, #4] 800eb6a: 681b ldr r3, [r3, #0] 800eb6c: f022 0202 bic.w r2, r2, #2 800eb70: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800eb72: f7ff fa4f bl 800e014 800eb76: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800eb78: e012 b.n 800eba0 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800eb7a: f7ff fa4b bl 800e014 800eb7e: 4602 mov r2, r0 800eb80: 68fb ldr r3, [r7, #12] 800eb82: 1ad3 subs r3, r2, r3 800eb84: 2b0a cmp r3, #10 800eb86: d90b bls.n 800eba0 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800eb88: 687b ldr r3, [r7, #4] 800eb8a: 6a5b ldr r3, [r3, #36] @ 0x24 800eb8c: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800eb90: 687b ldr r3, [r7, #4] 800eb92: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800eb94: 687b ldr r3, [r7, #4] 800eb96: 2205 movs r2, #5 800eb98: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800eb9c: 2301 movs r3, #1 800eb9e: e09f b.n 800ece0 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800eba0: 687b ldr r3, [r7, #4] 800eba2: 681b ldr r3, [r3, #0] 800eba4: 685b ldr r3, [r3, #4] 800eba6: f003 0302 and.w r3, r3, #2 800ebaa: 2b00 cmp r3, #0 800ebac: d1e5 bne.n 800eb7a } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) 800ebae: 687b ldr r3, [r7, #4] 800ebb0: 7e1b ldrb r3, [r3, #24] 800ebb2: 2b01 cmp r3, #1 800ebb4: d108 bne.n 800ebc8 { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800ebb6: 687b ldr r3, [r7, #4] 800ebb8: 681b ldr r3, [r3, #0] 800ebba: 681a ldr r2, [r3, #0] 800ebbc: 687b ldr r3, [r7, #4] 800ebbe: 681b ldr r3, [r3, #0] 800ebc0: f042 0280 orr.w r2, r2, #128 @ 0x80 800ebc4: 601a str r2, [r3, #0] 800ebc6: e007 b.n 800ebd8 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800ebc8: 687b ldr r3, [r7, #4] 800ebca: 681b ldr r3, [r3, #0] 800ebcc: 681a ldr r2, [r3, #0] 800ebce: 687b ldr r3, [r7, #4] 800ebd0: 681b ldr r3, [r3, #0] 800ebd2: f022 0280 bic.w r2, r2, #128 @ 0x80 800ebd6: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) 800ebd8: 687b ldr r3, [r7, #4] 800ebda: 7e5b ldrb r3, [r3, #25] 800ebdc: 2b01 cmp r3, #1 800ebde: d108 bne.n 800ebf2 { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800ebe0: 687b ldr r3, [r7, #4] 800ebe2: 681b ldr r3, [r3, #0] 800ebe4: 681a ldr r2, [r3, #0] 800ebe6: 687b ldr r3, [r7, #4] 800ebe8: 681b ldr r3, [r3, #0] 800ebea: f042 0240 orr.w r2, r2, #64 @ 0x40 800ebee: 601a str r2, [r3, #0] 800ebf0: e007 b.n 800ec02 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800ebf2: 687b ldr r3, [r7, #4] 800ebf4: 681b ldr r3, [r3, #0] 800ebf6: 681a ldr r2, [r3, #0] 800ebf8: 687b ldr r3, [r7, #4] 800ebfa: 681b ldr r3, [r3, #0] 800ebfc: f022 0240 bic.w r2, r2, #64 @ 0x40 800ec00: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) 800ec02: 687b ldr r3, [r7, #4] 800ec04: 7e9b ldrb r3, [r3, #26] 800ec06: 2b01 cmp r3, #1 800ec08: d108 bne.n 800ec1c { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800ec0a: 687b ldr r3, [r7, #4] 800ec0c: 681b ldr r3, [r3, #0] 800ec0e: 681a ldr r2, [r3, #0] 800ec10: 687b ldr r3, [r7, #4] 800ec12: 681b ldr r3, [r3, #0] 800ec14: f042 0220 orr.w r2, r2, #32 800ec18: 601a str r2, [r3, #0] 800ec1a: e007 b.n 800ec2c } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800ec1c: 687b ldr r3, [r7, #4] 800ec1e: 681b ldr r3, [r3, #0] 800ec20: 681a ldr r2, [r3, #0] 800ec22: 687b ldr r3, [r7, #4] 800ec24: 681b ldr r3, [r3, #0] 800ec26: f022 0220 bic.w r2, r2, #32 800ec2a: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) 800ec2c: 687b ldr r3, [r7, #4] 800ec2e: 7edb ldrb r3, [r3, #27] 800ec30: 2b01 cmp r3, #1 800ec32: d108 bne.n 800ec46 { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800ec34: 687b ldr r3, [r7, #4] 800ec36: 681b ldr r3, [r3, #0] 800ec38: 681a ldr r2, [r3, #0] 800ec3a: 687b ldr r3, [r7, #4] 800ec3c: 681b ldr r3, [r3, #0] 800ec3e: f022 0210 bic.w r2, r2, #16 800ec42: 601a str r2, [r3, #0] 800ec44: e007 b.n 800ec56 } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800ec46: 687b ldr r3, [r7, #4] 800ec48: 681b ldr r3, [r3, #0] 800ec4a: 681a ldr r2, [r3, #0] 800ec4c: 687b ldr r3, [r7, #4] 800ec4e: 681b ldr r3, [r3, #0] 800ec50: f042 0210 orr.w r2, r2, #16 800ec54: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) 800ec56: 687b ldr r3, [r7, #4] 800ec58: 7f1b ldrb r3, [r3, #28] 800ec5a: 2b01 cmp r3, #1 800ec5c: d108 bne.n 800ec70 { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800ec5e: 687b ldr r3, [r7, #4] 800ec60: 681b ldr r3, [r3, #0] 800ec62: 681a ldr r2, [r3, #0] 800ec64: 687b ldr r3, [r7, #4] 800ec66: 681b ldr r3, [r3, #0] 800ec68: f042 0208 orr.w r2, r2, #8 800ec6c: 601a str r2, [r3, #0] 800ec6e: e007 b.n 800ec80 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800ec70: 687b ldr r3, [r7, #4] 800ec72: 681b ldr r3, [r3, #0] 800ec74: 681a ldr r2, [r3, #0] 800ec76: 687b ldr r3, [r7, #4] 800ec78: 681b ldr r3, [r3, #0] 800ec7a: f022 0208 bic.w r2, r2, #8 800ec7e: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) 800ec80: 687b ldr r3, [r7, #4] 800ec82: 7f5b ldrb r3, [r3, #29] 800ec84: 2b01 cmp r3, #1 800ec86: d108 bne.n 800ec9a { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800ec88: 687b ldr r3, [r7, #4] 800ec8a: 681b ldr r3, [r3, #0] 800ec8c: 681a ldr r2, [r3, #0] 800ec8e: 687b ldr r3, [r7, #4] 800ec90: 681b ldr r3, [r3, #0] 800ec92: f042 0204 orr.w r2, r2, #4 800ec96: 601a str r2, [r3, #0] 800ec98: e007 b.n 800ecaa } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800ec9a: 687b ldr r3, [r7, #4] 800ec9c: 681b ldr r3, [r3, #0] 800ec9e: 681a ldr r2, [r3, #0] 800eca0: 687b ldr r3, [r7, #4] 800eca2: 681b ldr r3, [r3, #0] 800eca4: f022 0204 bic.w r2, r2, #4 800eca8: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | 800ecaa: 687b ldr r3, [r7, #4] 800ecac: 689a ldr r2, [r3, #8] 800ecae: 687b ldr r3, [r7, #4] 800ecb0: 68db ldr r3, [r3, #12] 800ecb2: 431a orrs r2, r3 800ecb4: 687b ldr r3, [r7, #4] 800ecb6: 691b ldr r3, [r3, #16] 800ecb8: 431a orrs r2, r3 800ecba: 687b ldr r3, [r7, #4] 800ecbc: 695b ldr r3, [r3, #20] 800ecbe: ea42 0103 orr.w r1, r2, r3 800ecc2: 687b ldr r3, [r7, #4] 800ecc4: 685b ldr r3, [r3, #4] 800ecc6: 1e5a subs r2, r3, #1 800ecc8: 687b ldr r3, [r7, #4] 800ecca: 681b ldr r3, [r3, #0] 800eccc: 430a orrs r2, r1 800ecce: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800ecd0: 687b ldr r3, [r7, #4] 800ecd2: 2200 movs r2, #0 800ecd4: 625a str r2, [r3, #36] @ 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; 800ecd6: 687b ldr r3, [r7, #4] 800ecd8: 2201 movs r2, #1 800ecda: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800ecde: 2300 movs r3, #0 } 800ece0: 4618 mov r0, r3 800ece2: 3710 adds r7, #16 800ece4: 46bd mov sp, r7 800ece6: bd80 pop {r7, pc} 0800ece8 : * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) { 800ece8: b480 push {r7} 800ecea: b087 sub sp, #28 800ecec: af00 add r7, sp, #0 800ecee: 6078 str r0, [r7, #4] 800ecf0: 6039 str r1, [r7, #0] uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; 800ecf2: 687b ldr r3, [r7, #4] 800ecf4: 681b ldr r3, [r3, #0] 800ecf6: 617b str r3, [r7, #20] HAL_CAN_StateTypeDef state = hcan->State; 800ecf8: 687b ldr r3, [r7, #4] 800ecfa: f893 3020 ldrb.w r3, [r3, #32] 800ecfe: 74fb strb r3, [r7, #19] if ((state == HAL_CAN_STATE_READY) || 800ed00: 7cfb ldrb r3, [r7, #19] 800ed02: 2b01 cmp r3, #1 800ed04: d003 beq.n 800ed0e 800ed06: 7cfb ldrb r3, [r7, #19] 800ed08: 2b02 cmp r3, #2 800ed0a: f040 80be bne.w 800ee8a assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); #if defined(CAN2) /* CAN1 and CAN2 are dual instances with 28 common filters banks */ /* Select master instance to access the filter banks */ can_ip = CAN1; 800ed0e: 4b65 ldr r3, [pc, #404] @ (800eea4 ) 800ed10: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); #endif /* CAN3 */ /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); 800ed12: 697b ldr r3, [r7, #20] 800ed14: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800ed18: f043 0201 orr.w r2, r3, #1 800ed1c: 697b ldr r3, [r7, #20] 800ed1e: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #if defined(CAN2) /* Select the start filter number of CAN2 slave instance */ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); 800ed22: 697b ldr r3, [r7, #20] 800ed24: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800ed28: f423 527c bic.w r2, r3, #16128 @ 0x3f00 800ed2c: 697b ldr r3, [r7, #20] 800ed2e: f8c3 2200 str.w r2, [r3, #512] @ 0x200 SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); 800ed32: 697b ldr r3, [r7, #20] 800ed34: f8d3 2200 ldr.w r2, [r3, #512] @ 0x200 800ed38: 683b ldr r3, [r7, #0] 800ed3a: 6a5b ldr r3, [r3, #36] @ 0x24 800ed3c: 021b lsls r3, r3, #8 800ed3e: 431a orrs r2, r3 800ed40: 697b ldr r3, [r7, #20] 800ed42: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #endif /* CAN3 */ /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); 800ed46: 683b ldr r3, [r7, #0] 800ed48: 695b ldr r3, [r3, #20] 800ed4a: f003 031f and.w r3, r3, #31 800ed4e: 2201 movs r2, #1 800ed50: fa02 f303 lsl.w r3, r2, r3 800ed54: 60fb str r3, [r7, #12] /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); 800ed56: 697b ldr r3, [r7, #20] 800ed58: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800ed5c: 68fb ldr r3, [r7, #12] 800ed5e: 43db mvns r3, r3 800ed60: 401a ands r2, r3 800ed62: 697b ldr r3, [r7, #20] 800ed64: f8c3 221c str.w r2, [r3, #540] @ 0x21c /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) 800ed68: 683b ldr r3, [r7, #0] 800ed6a: 69db ldr r3, [r3, #28] 800ed6c: 2b00 cmp r3, #0 800ed6e: d123 bne.n 800edb8 { /* 16-bit scale for the filter */ CLEAR_BIT(can_ip->FS1R, filternbrbitpos); 800ed70: 697b ldr r3, [r7, #20] 800ed72: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800ed76: 68fb ldr r3, [r7, #12] 800ed78: 43db mvns r3, r3 800ed7a: 401a ands r2, r3 800ed7c: 697b ldr r3, [r7, #20] 800ed7e: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800ed82: 683b ldr r3, [r7, #0] 800ed84: 68db ldr r3, [r3, #12] 800ed86: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800ed88: 683b ldr r3, [r7, #0] 800ed8a: 685b ldr r3, [r3, #4] 800ed8c: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800ed8e: 683a ldr r2, [r7, #0] 800ed90: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800ed92: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800ed94: 697b ldr r3, [r7, #20] 800ed96: 3248 adds r2, #72 @ 0x48 800ed98: f843 1032 str.w r1, [r3, r2, lsl #3] /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800ed9c: 683b ldr r3, [r7, #0] 800ed9e: 689b ldr r3, [r3, #8] 800eda0: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); 800eda2: 683b ldr r3, [r7, #0] 800eda4: 681b ldr r3, [r3, #0] 800eda6: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800eda8: 683b ldr r3, [r7, #0] 800edaa: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800edac: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800edae: 6979 ldr r1, [r7, #20] 800edb0: 3348 adds r3, #72 @ 0x48 800edb2: 00db lsls r3, r3, #3 800edb4: 440b add r3, r1 800edb6: 605a str r2, [r3, #4] } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) 800edb8: 683b ldr r3, [r7, #0] 800edba: 69db ldr r3, [r3, #28] 800edbc: 2b01 cmp r3, #1 800edbe: d122 bne.n 800ee06 { /* 32-bit scale for the filter */ SET_BIT(can_ip->FS1R, filternbrbitpos); 800edc0: 697b ldr r3, [r7, #20] 800edc2: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800edc6: 68fb ldr r3, [r7, #12] 800edc8: 431a orrs r2, r3 800edca: 697b ldr r3, [r7, #20] 800edcc: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* 32-bit identifier or First 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800edd0: 683b ldr r3, [r7, #0] 800edd2: 681b ldr r3, [r3, #0] 800edd4: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800edd6: 683b ldr r3, [r7, #0] 800edd8: 685b ldr r3, [r3, #4] 800edda: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800eddc: 683a ldr r2, [r7, #0] 800edde: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800ede0: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800ede2: 697b ldr r3, [r7, #20] 800ede4: 3248 adds r2, #72 @ 0x48 800ede6: f843 1032 str.w r1, [r3, r2, lsl #3] /* 32-bit mask or Second 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800edea: 683b ldr r3, [r7, #0] 800edec: 689b ldr r3, [r3, #8] 800edee: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); 800edf0: 683b ldr r3, [r7, #0] 800edf2: 68db ldr r3, [r3, #12] 800edf4: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800edf6: 683b ldr r3, [r7, #0] 800edf8: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800edfa: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800edfc: 6979 ldr r1, [r7, #20] 800edfe: 3348 adds r3, #72 @ 0x48 800ee00: 00db lsls r3, r3, #3 800ee02: 440b add r3, r1 800ee04: 605a str r2, [r3, #4] } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) 800ee06: 683b ldr r3, [r7, #0] 800ee08: 699b ldr r3, [r3, #24] 800ee0a: 2b00 cmp r3, #0 800ee0c: d109 bne.n 800ee22 { /* Id/Mask mode for the filter*/ CLEAR_BIT(can_ip->FM1R, filternbrbitpos); 800ee0e: 697b ldr r3, [r7, #20] 800ee10: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800ee14: 68fb ldr r3, [r7, #12] 800ee16: 43db mvns r3, r3 800ee18: 401a ands r2, r3 800ee1a: 697b ldr r3, [r7, #20] 800ee1c: f8c3 2204 str.w r2, [r3, #516] @ 0x204 800ee20: e007 b.n 800ee32 } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /* Identifier list mode for the filter*/ SET_BIT(can_ip->FM1R, filternbrbitpos); 800ee22: 697b ldr r3, [r7, #20] 800ee24: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800ee28: 68fb ldr r3, [r7, #12] 800ee2a: 431a orrs r2, r3 800ee2c: 697b ldr r3, [r7, #20] 800ee2e: f8c3 2204 str.w r2, [r3, #516] @ 0x204 } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) 800ee32: 683b ldr r3, [r7, #0] 800ee34: 691b ldr r3, [r3, #16] 800ee36: 2b00 cmp r3, #0 800ee38: d109 bne.n 800ee4e { /* FIFO 0 assignation for the filter */ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); 800ee3a: 697b ldr r3, [r7, #20] 800ee3c: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800ee40: 68fb ldr r3, [r7, #12] 800ee42: 43db mvns r3, r3 800ee44: 401a ands r2, r3 800ee46: 697b ldr r3, [r7, #20] 800ee48: f8c3 2214 str.w r2, [r3, #532] @ 0x214 800ee4c: e007 b.n 800ee5e } else { /* FIFO 1 assignation for the filter */ SET_BIT(can_ip->FFA1R, filternbrbitpos); 800ee4e: 697b ldr r3, [r7, #20] 800ee50: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800ee54: 68fb ldr r3, [r7, #12] 800ee56: 431a orrs r2, r3 800ee58: 697b ldr r3, [r7, #20] 800ee5a: f8c3 2214 str.w r2, [r3, #532] @ 0x214 } /* Filter activation */ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) 800ee5e: 683b ldr r3, [r7, #0] 800ee60: 6a1b ldr r3, [r3, #32] 800ee62: 2b01 cmp r3, #1 800ee64: d107 bne.n 800ee76 { SET_BIT(can_ip->FA1R, filternbrbitpos); 800ee66: 697b ldr r3, [r7, #20] 800ee68: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800ee6c: 68fb ldr r3, [r7, #12] 800ee6e: 431a orrs r2, r3 800ee70: 697b ldr r3, [r7, #20] 800ee72: f8c3 221c str.w r2, [r3, #540] @ 0x21c } /* Leave the initialisation mode for the filter */ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); 800ee76: 697b ldr r3, [r7, #20] 800ee78: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800ee7c: f023 0201 bic.w r2, r3, #1 800ee80: 697b ldr r3, [r7, #20] 800ee82: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Return function status */ return HAL_OK; 800ee86: 2300 movs r3, #0 800ee88: e006 b.n 800ee98 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800ee8a: 687b ldr r3, [r7, #4] 800ee8c: 6a5b ldr r3, [r3, #36] @ 0x24 800ee8e: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800ee92: 687b ldr r3, [r7, #4] 800ee94: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ee96: 2301 movs r3, #1 } } 800ee98: 4618 mov r0, r3 800ee9a: 371c adds r7, #28 800ee9c: 46bd mov sp, r7 800ee9e: bc80 pop {r7} 800eea0: 4770 bx lr 800eea2: bf00 nop 800eea4: 40006400 .word 0x40006400 0800eea8 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { 800eea8: b580 push {r7, lr} 800eeaa: b084 sub sp, #16 800eeac: af00 add r7, sp, #0 800eeae: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) 800eeb0: 687b ldr r3, [r7, #4] 800eeb2: f893 3020 ldrb.w r3, [r3, #32] 800eeb6: b2db uxtb r3, r3 800eeb8: 2b01 cmp r3, #1 800eeba: d12e bne.n 800ef1a { /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_LISTENING; 800eebc: 687b ldr r3, [r7, #4] 800eebe: 2202 movs r2, #2 800eec0: f883 2020 strb.w r2, [r3, #32] /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800eec4: 687b ldr r3, [r7, #4] 800eec6: 681b ldr r3, [r3, #0] 800eec8: 681a ldr r2, [r3, #0] 800eeca: 687b ldr r3, [r7, #4] 800eecc: 681b ldr r3, [r3, #0] 800eece: f022 0201 bic.w r2, r2, #1 800eed2: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800eed4: f7ff f89e bl 800e014 800eed8: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800eeda: e012 b.n 800ef02 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800eedc: f7ff f89a bl 800e014 800eee0: 4602 mov r2, r0 800eee2: 68fb ldr r3, [r7, #12] 800eee4: 1ad3 subs r3, r2, r3 800eee6: 2b0a cmp r3, #10 800eee8: d90b bls.n 800ef02 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800eeea: 687b ldr r3, [r7, #4] 800eeec: 6a5b ldr r3, [r3, #36] @ 0x24 800eeee: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800eef2: 687b ldr r3, [r7, #4] 800eef4: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800eef6: 687b ldr r3, [r7, #4] 800eef8: 2205 movs r2, #5 800eefa: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800eefe: 2301 movs r3, #1 800ef00: e012 b.n 800ef28 while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800ef02: 687b ldr r3, [r7, #4] 800ef04: 681b ldr r3, [r3, #0] 800ef06: 685b ldr r3, [r3, #4] 800ef08: f003 0301 and.w r3, r3, #1 800ef0c: 2b00 cmp r3, #0 800ef0e: d1e5 bne.n 800eedc } } /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800ef10: 687b ldr r3, [r7, #4] 800ef12: 2200 movs r2, #0 800ef14: 625a str r2, [r3, #36] @ 0x24 /* Return function status */ return HAL_OK; 800ef16: 2300 movs r3, #0 800ef18: e006 b.n 800ef28 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; 800ef1a: 687b ldr r3, [r7, #4] 800ef1c: 6a5b ldr r3, [r3, #36] @ 0x24 800ef1e: f443 2200 orr.w r2, r3, #524288 @ 0x80000 800ef22: 687b ldr r3, [r7, #4] 800ef24: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ef26: 2301 movs r3, #1 } } 800ef28: 4618 mov r0, r3 800ef2a: 3710 adds r7, #16 800ef2c: 46bd mov sp, r7 800ef2e: bd80 pop {r7, pc} 0800ef30 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { 800ef30: b580 push {r7, lr} 800ef32: b084 sub sp, #16 800ef34: af00 add r7, sp, #0 800ef36: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_LISTENING) 800ef38: 687b ldr r3, [r7, #4] 800ef3a: f893 3020 ldrb.w r3, [r3, #32] 800ef3e: b2db uxtb r3, r3 800ef40: 2b02 cmp r3, #2 800ef42: d133 bne.n 800efac { /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800ef44: 687b ldr r3, [r7, #4] 800ef46: 681b ldr r3, [r3, #0] 800ef48: 681a ldr r2, [r3, #0] 800ef4a: 687b ldr r3, [r7, #4] 800ef4c: 681b ldr r3, [r3, #0] 800ef4e: f042 0201 orr.w r2, r2, #1 800ef52: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800ef54: f7ff f85e bl 800e014 800ef58: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800ef5a: e012 b.n 800ef82 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800ef5c: f7ff f85a bl 800e014 800ef60: 4602 mov r2, r0 800ef62: 68fb ldr r3, [r7, #12] 800ef64: 1ad3 subs r3, r2, r3 800ef66: 2b0a cmp r3, #10 800ef68: d90b bls.n 800ef82 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800ef6a: 687b ldr r3, [r7, #4] 800ef6c: 6a5b ldr r3, [r3, #36] @ 0x24 800ef6e: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800ef72: 687b ldr r3, [r7, #4] 800ef74: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800ef76: 687b ldr r3, [r7, #4] 800ef78: 2205 movs r2, #5 800ef7a: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800ef7e: 2301 movs r3, #1 800ef80: e01b b.n 800efba while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800ef82: 687b ldr r3, [r7, #4] 800ef84: 681b ldr r3, [r3, #0] 800ef86: 685b ldr r3, [r3, #4] 800ef88: f003 0301 and.w r3, r3, #1 800ef8c: 2b00 cmp r3, #0 800ef8e: d0e5 beq.n 800ef5c } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800ef90: 687b ldr r3, [r7, #4] 800ef92: 681b ldr r3, [r3, #0] 800ef94: 681a ldr r2, [r3, #0] 800ef96: 687b ldr r3, [r7, #4] 800ef98: 681b ldr r3, [r3, #0] 800ef9a: f022 0202 bic.w r2, r2, #2 800ef9e: 601a str r2, [r3, #0] /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_READY; 800efa0: 687b ldr r3, [r7, #4] 800efa2: 2201 movs r2, #1 800efa4: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800efa8: 2300 movs r3, #0 800efaa: e006 b.n 800efba } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; 800efac: 687b ldr r3, [r7, #4] 800efae: 6a5b ldr r3, [r3, #36] @ 0x24 800efb0: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800efb4: 687b ldr r3, [r7, #4] 800efb6: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800efb8: 2301 movs r3, #1 } } 800efba: 4618 mov r0, r3 800efbc: 3710 adds r7, #16 800efbe: 46bd mov sp, r7 800efc0: bd80 pop {r7, pc} 0800efc2 : * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, const uint8_t aData[], uint32_t *pTxMailbox) { 800efc2: b480 push {r7} 800efc4: b089 sub sp, #36 @ 0x24 800efc6: af00 add r7, sp, #0 800efc8: 60f8 str r0, [r7, #12] 800efca: 60b9 str r1, [r7, #8] 800efcc: 607a str r2, [r7, #4] 800efce: 603b str r3, [r7, #0] uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; 800efd0: 68fb ldr r3, [r7, #12] 800efd2: f893 3020 ldrb.w r3, [r3, #32] 800efd6: 77fb strb r3, [r7, #31] uint32_t tsr = READ_REG(hcan->Instance->TSR); 800efd8: 68fb ldr r3, [r7, #12] 800efda: 681b ldr r3, [r3, #0] 800efdc: 689b ldr r3, [r3, #8] 800efde: 61bb str r3, [r7, #24] { assert_param(IS_CAN_EXTID(pHeader->ExtId)); } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); if ((state == HAL_CAN_STATE_READY) || 800efe0: 7ffb ldrb r3, [r7, #31] 800efe2: 2b01 cmp r3, #1 800efe4: d003 beq.n 800efee 800efe6: 7ffb ldrb r3, [r7, #31] 800efe8: 2b02 cmp r3, #2 800efea: f040 80ad bne.w 800f148 (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ if (((tsr & CAN_TSR_TME0) != 0U) || 800efee: 69bb ldr r3, [r7, #24] 800eff0: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800eff4: 2b00 cmp r3, #0 800eff6: d10a bne.n 800f00e ((tsr & CAN_TSR_TME1) != 0U) || 800eff8: 69bb ldr r3, [r7, #24] 800effa: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 if (((tsr & CAN_TSR_TME0) != 0U) || 800effe: 2b00 cmp r3, #0 800f000: d105 bne.n 800f00e ((tsr & CAN_TSR_TME2) != 0U)) 800f002: 69bb ldr r3, [r7, #24] 800f004: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 ((tsr & CAN_TSR_TME1) != 0U) || 800f008: 2b00 cmp r3, #0 800f00a: f000 8095 beq.w 800f138 { /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; 800f00e: 69bb ldr r3, [r7, #24] 800f010: 0e1b lsrs r3, r3, #24 800f012: f003 0303 and.w r3, r3, #3 800f016: 617b str r3, [r7, #20] /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; 800f018: 2201 movs r2, #1 800f01a: 697b ldr r3, [r7, #20] 800f01c: 409a lsls r2, r3 800f01e: 683b ldr r3, [r7, #0] 800f020: 601a str r2, [r3, #0] /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) 800f022: 68bb ldr r3, [r7, #8] 800f024: 689b ldr r3, [r3, #8] 800f026: 2b00 cmp r3, #0 800f028: d10d bne.n 800f046 { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800f02a: 68bb ldr r3, [r7, #8] 800f02c: 681b ldr r3, [r3, #0] 800f02e: 055a lsls r2, r3, #21 pHeader->RTR); 800f030: 68bb ldr r3, [r7, #8] 800f032: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800f034: 68f9 ldr r1, [r7, #12] 800f036: 6809 ldr r1, [r1, #0] 800f038: 431a orrs r2, r3 800f03a: 697b ldr r3, [r7, #20] 800f03c: 3318 adds r3, #24 800f03e: 011b lsls r3, r3, #4 800f040: 440b add r3, r1 800f042: 601a str r2, [r3, #0] 800f044: e00f b.n 800f066 } else { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f046: 68bb ldr r3, [r7, #8] 800f048: 685b ldr r3, [r3, #4] 800f04a: 00da lsls r2, r3, #3 pHeader->IDE | 800f04c: 68bb ldr r3, [r7, #8] 800f04e: 689b ldr r3, [r3, #8] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f050: 431a orrs r2, r3 pHeader->RTR); 800f052: 68bb ldr r3, [r7, #8] 800f054: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f056: 68f9 ldr r1, [r7, #12] 800f058: 6809 ldr r1, [r1, #0] pHeader->IDE | 800f05a: 431a orrs r2, r3 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f05c: 697b ldr r3, [r7, #20] 800f05e: 3318 adds r3, #24 800f060: 011b lsls r3, r3, #4 800f062: 440b add r3, r1 800f064: 601a str r2, [r3, #0] } /* Set up the DLC */ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); 800f066: 68fb ldr r3, [r7, #12] 800f068: 6819 ldr r1, [r3, #0] 800f06a: 68bb ldr r3, [r7, #8] 800f06c: 691a ldr r2, [r3, #16] 800f06e: 697b ldr r3, [r7, #20] 800f070: 3318 adds r3, #24 800f072: 011b lsls r3, r3, #4 800f074: 440b add r3, r1 800f076: 3304 adds r3, #4 800f078: 601a str r2, [r3, #0] /* Set up the Transmit Global Time mode */ if (pHeader->TransmitGlobalTime == ENABLE) 800f07a: 68bb ldr r3, [r7, #8] 800f07c: 7d1b ldrb r3, [r3, #20] 800f07e: 2b01 cmp r3, #1 800f080: d111 bne.n 800f0a6 { SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); 800f082: 68fb ldr r3, [r7, #12] 800f084: 681a ldr r2, [r3, #0] 800f086: 697b ldr r3, [r7, #20] 800f088: 3318 adds r3, #24 800f08a: 011b lsls r3, r3, #4 800f08c: 4413 add r3, r2 800f08e: 3304 adds r3, #4 800f090: 681b ldr r3, [r3, #0] 800f092: 68fa ldr r2, [r7, #12] 800f094: 6811 ldr r1, [r2, #0] 800f096: f443 7280 orr.w r2, r3, #256 @ 0x100 800f09a: 697b ldr r3, [r7, #20] 800f09c: 3318 adds r3, #24 800f09e: 011b lsls r3, r3, #4 800f0a0: 440b add r3, r1 800f0a2: 3304 adds r3, #4 800f0a4: 601a str r2, [r3, #0] } /* Set up the data field */ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, 800f0a6: 687b ldr r3, [r7, #4] 800f0a8: 3307 adds r3, #7 800f0aa: 781b ldrb r3, [r3, #0] 800f0ac: 061a lsls r2, r3, #24 800f0ae: 687b ldr r3, [r7, #4] 800f0b0: 3306 adds r3, #6 800f0b2: 781b ldrb r3, [r3, #0] 800f0b4: 041b lsls r3, r3, #16 800f0b6: 431a orrs r2, r3 800f0b8: 687b ldr r3, [r7, #4] 800f0ba: 3305 adds r3, #5 800f0bc: 781b ldrb r3, [r3, #0] 800f0be: 021b lsls r3, r3, #8 800f0c0: 4313 orrs r3, r2 800f0c2: 687a ldr r2, [r7, #4] 800f0c4: 3204 adds r2, #4 800f0c6: 7812 ldrb r2, [r2, #0] 800f0c8: 4610 mov r0, r2 800f0ca: 68fa ldr r2, [r7, #12] 800f0cc: 6811 ldr r1, [r2, #0] 800f0ce: ea43 0200 orr.w r2, r3, r0 800f0d2: 697b ldr r3, [r7, #20] 800f0d4: 011b lsls r3, r3, #4 800f0d6: 440b add r3, r1 800f0d8: f503 73c6 add.w r3, r3, #396 @ 0x18c 800f0dc: 601a str r2, [r3, #0] ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, 800f0de: 687b ldr r3, [r7, #4] 800f0e0: 3303 adds r3, #3 800f0e2: 781b ldrb r3, [r3, #0] 800f0e4: 061a lsls r2, r3, #24 800f0e6: 687b ldr r3, [r7, #4] 800f0e8: 3302 adds r3, #2 800f0ea: 781b ldrb r3, [r3, #0] 800f0ec: 041b lsls r3, r3, #16 800f0ee: 431a orrs r2, r3 800f0f0: 687b ldr r3, [r7, #4] 800f0f2: 3301 adds r3, #1 800f0f4: 781b ldrb r3, [r3, #0] 800f0f6: 021b lsls r3, r3, #8 800f0f8: 4313 orrs r3, r2 800f0fa: 687a ldr r2, [r7, #4] 800f0fc: 7812 ldrb r2, [r2, #0] 800f0fe: 4610 mov r0, r2 800f100: 68fa ldr r2, [r7, #12] 800f102: 6811 ldr r1, [r2, #0] 800f104: ea43 0200 orr.w r2, r3, r0 800f108: 697b ldr r3, [r7, #20] 800f10a: 011b lsls r3, r3, #4 800f10c: 440b add r3, r1 800f10e: f503 73c4 add.w r3, r3, #392 @ 0x188 800f112: 601a str r2, [r3, #0] ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); 800f114: 68fb ldr r3, [r7, #12] 800f116: 681a ldr r2, [r3, #0] 800f118: 697b ldr r3, [r7, #20] 800f11a: 3318 adds r3, #24 800f11c: 011b lsls r3, r3, #4 800f11e: 4413 add r3, r2 800f120: 681b ldr r3, [r3, #0] 800f122: 68fa ldr r2, [r7, #12] 800f124: 6811 ldr r1, [r2, #0] 800f126: f043 0201 orr.w r2, r3, #1 800f12a: 697b ldr r3, [r7, #20] 800f12c: 3318 adds r3, #24 800f12e: 011b lsls r3, r3, #4 800f130: 440b add r3, r1 800f132: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 800f134: 2300 movs r3, #0 800f136: e00e b.n 800f156 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800f138: 68fb ldr r3, [r7, #12] 800f13a: 6a5b ldr r3, [r3, #36] @ 0x24 800f13c: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800f140: 68fb ldr r3, [r7, #12] 800f142: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f144: 2301 movs r3, #1 800f146: e006 b.n 800f156 } } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f148: 68fb ldr r3, [r7, #12] 800f14a: 6a5b ldr r3, [r3, #36] @ 0x24 800f14c: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f150: 68fb ldr r3, [r7, #12] 800f152: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f154: 2301 movs r3, #1 } } 800f156: 4618 mov r0, r3 800f158: 3724 adds r7, #36 @ 0x24 800f15a: 46bd mov sp, r7 800f15c: bc80 pop {r7} 800f15e: 4770 bx lr 0800f160 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval Number of free Tx Mailboxes. */ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) { 800f160: b480 push {r7} 800f162: b085 sub sp, #20 800f164: af00 add r7, sp, #0 800f166: 6078 str r0, [r7, #4] uint32_t freelevel = 0U; 800f168: 2300 movs r3, #0 800f16a: 60fb str r3, [r7, #12] HAL_CAN_StateTypeDef state = hcan->State; 800f16c: 687b ldr r3, [r7, #4] 800f16e: f893 3020 ldrb.w r3, [r3, #32] 800f172: 72fb strb r3, [r7, #11] if ((state == HAL_CAN_STATE_READY) || 800f174: 7afb ldrb r3, [r7, #11] 800f176: 2b01 cmp r3, #1 800f178: d002 beq.n 800f180 800f17a: 7afb ldrb r3, [r7, #11] 800f17c: 2b02 cmp r3, #2 800f17e: d11d bne.n 800f1bc (state == HAL_CAN_STATE_LISTENING)) { /* Check Tx Mailbox 0 status */ if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) 800f180: 687b ldr r3, [r7, #4] 800f182: 681b ldr r3, [r3, #0] 800f184: 689b ldr r3, [r3, #8] 800f186: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800f18a: 2b00 cmp r3, #0 800f18c: d002 beq.n 800f194 { freelevel++; 800f18e: 68fb ldr r3, [r7, #12] 800f190: 3301 adds r3, #1 800f192: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 1 status */ if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) 800f194: 687b ldr r3, [r7, #4] 800f196: 681b ldr r3, [r3, #0] 800f198: 689b ldr r3, [r3, #8] 800f19a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800f19e: 2b00 cmp r3, #0 800f1a0: d002 beq.n 800f1a8 { freelevel++; 800f1a2: 68fb ldr r3, [r7, #12] 800f1a4: 3301 adds r3, #1 800f1a6: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 2 status */ if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) 800f1a8: 687b ldr r3, [r7, #4] 800f1aa: 681b ldr r3, [r3, #0] 800f1ac: 689b ldr r3, [r3, #8] 800f1ae: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800f1b2: 2b00 cmp r3, #0 800f1b4: d002 beq.n 800f1bc { freelevel++; 800f1b6: 68fb ldr r3, [r7, #12] 800f1b8: 3301 adds r3, #1 800f1ba: 60fb str r3, [r7, #12] } } /* Return Tx Mailboxes free level */ return freelevel; 800f1bc: 68fb ldr r3, [r7, #12] } 800f1be: 4618 mov r0, r3 800f1c0: 3714 adds r7, #20 800f1c2: 46bd mov sp, r7 800f1c4: bc80 pop {r7} 800f1c6: 4770 bx lr 0800f1c8 : * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { 800f1c8: b480 push {r7} 800f1ca: b087 sub sp, #28 800f1cc: af00 add r7, sp, #0 800f1ce: 60f8 str r0, [r7, #12] 800f1d0: 60b9 str r1, [r7, #8] 800f1d2: 607a str r2, [r7, #4] 800f1d4: 603b str r3, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800f1d6: 68fb ldr r3, [r7, #12] 800f1d8: f893 3020 ldrb.w r3, [r3, #32] 800f1dc: 75fb strb r3, [r7, #23] assert_param(IS_CAN_RX_FIFO(RxFifo)); if ((state == HAL_CAN_STATE_READY) || 800f1de: 7dfb ldrb r3, [r7, #23] 800f1e0: 2b01 cmp r3, #1 800f1e2: d003 beq.n 800f1ec 800f1e4: 7dfb ldrb r3, [r7, #23] 800f1e6: 2b02 cmp r3, #2 800f1e8: f040 8103 bne.w 800f3f2 (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800f1ec: 68bb ldr r3, [r7, #8] 800f1ee: 2b00 cmp r3, #0 800f1f0: d10e bne.n 800f210 { /* Check that the Rx FIFO 0 is not empty */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) 800f1f2: 68fb ldr r3, [r7, #12] 800f1f4: 681b ldr r3, [r3, #0] 800f1f6: 68db ldr r3, [r3, #12] 800f1f8: f003 0303 and.w r3, r3, #3 800f1fc: 2b00 cmp r3, #0 800f1fe: d116 bne.n 800f22e { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800f200: 68fb ldr r3, [r7, #12] 800f202: 6a5b ldr r3, [r3, #36] @ 0x24 800f204: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800f208: 68fb ldr r3, [r7, #12] 800f20a: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f20c: 2301 movs r3, #1 800f20e: e0f7 b.n 800f400 } } else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) 800f210: 68fb ldr r3, [r7, #12] 800f212: 681b ldr r3, [r3, #0] 800f214: 691b ldr r3, [r3, #16] 800f216: f003 0303 and.w r3, r3, #3 800f21a: 2b00 cmp r3, #0 800f21c: d107 bne.n 800f22e { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800f21e: 68fb ldr r3, [r7, #12] 800f220: 6a5b ldr r3, [r3, #36] @ 0x24 800f222: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800f226: 68fb ldr r3, [r7, #12] 800f228: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f22a: 2301 movs r3, #1 800f22c: e0e8 b.n 800f400 } } /* Get the header */ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; 800f22e: 68fb ldr r3, [r7, #12] 800f230: 681a ldr r2, [r3, #0] 800f232: 68bb ldr r3, [r7, #8] 800f234: 331b adds r3, #27 800f236: 011b lsls r3, r3, #4 800f238: 4413 add r3, r2 800f23a: 681b ldr r3, [r3, #0] 800f23c: f003 0204 and.w r2, r3, #4 800f240: 687b ldr r3, [r7, #4] 800f242: 609a str r2, [r3, #8] if (pHeader->IDE == CAN_ID_STD) 800f244: 687b ldr r3, [r7, #4] 800f246: 689b ldr r3, [r3, #8] 800f248: 2b00 cmp r3, #0 800f24a: d10c bne.n 800f266 { pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; 800f24c: 68fb ldr r3, [r7, #12] 800f24e: 681a ldr r2, [r3, #0] 800f250: 68bb ldr r3, [r7, #8] 800f252: 331b adds r3, #27 800f254: 011b lsls r3, r3, #4 800f256: 4413 add r3, r2 800f258: 681b ldr r3, [r3, #0] 800f25a: 0d5b lsrs r3, r3, #21 800f25c: f3c3 020a ubfx r2, r3, #0, #11 800f260: 687b ldr r3, [r7, #4] 800f262: 601a str r2, [r3, #0] 800f264: e00b b.n 800f27e } else { pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; 800f266: 68fb ldr r3, [r7, #12] 800f268: 681a ldr r2, [r3, #0] 800f26a: 68bb ldr r3, [r7, #8] 800f26c: 331b adds r3, #27 800f26e: 011b lsls r3, r3, #4 800f270: 4413 add r3, r2 800f272: 681b ldr r3, [r3, #0] 800f274: 08db lsrs r3, r3, #3 800f276: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & 800f27a: 687b ldr r3, [r7, #4] 800f27c: 605a str r2, [r3, #4] } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); 800f27e: 68fb ldr r3, [r7, #12] 800f280: 681a ldr r2, [r3, #0] 800f282: 68bb ldr r3, [r7, #8] 800f284: 331b adds r3, #27 800f286: 011b lsls r3, r3, #4 800f288: 4413 add r3, r2 800f28a: 681b ldr r3, [r3, #0] 800f28c: f003 0202 and.w r2, r3, #2 800f290: 687b ldr r3, [r7, #4] 800f292: 60da str r2, [r3, #12] if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) 800f294: 68fb ldr r3, [r7, #12] 800f296: 681a ldr r2, [r3, #0] 800f298: 68bb ldr r3, [r7, #8] 800f29a: 331b adds r3, #27 800f29c: 011b lsls r3, r3, #4 800f29e: 4413 add r3, r2 800f2a0: 3304 adds r3, #4 800f2a2: 681b ldr r3, [r3, #0] 800f2a4: f003 0308 and.w r3, r3, #8 800f2a8: 2b00 cmp r3, #0 800f2aa: d003 beq.n 800f2b4 { /* Truncate DLC to 8 if received field is over range */ pHeader->DLC = 8U; 800f2ac: 687b ldr r3, [r7, #4] 800f2ae: 2208 movs r2, #8 800f2b0: 611a str r2, [r3, #16] 800f2b2: e00b b.n 800f2cc } else { pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; 800f2b4: 68fb ldr r3, [r7, #12] 800f2b6: 681a ldr r2, [r3, #0] 800f2b8: 68bb ldr r3, [r7, #8] 800f2ba: 331b adds r3, #27 800f2bc: 011b lsls r3, r3, #4 800f2be: 4413 add r3, r2 800f2c0: 3304 adds r3, #4 800f2c2: 681b ldr r3, [r3, #0] 800f2c4: f003 020f and.w r2, r3, #15 800f2c8: 687b ldr r3, [r7, #4] 800f2ca: 611a str r2, [r3, #16] } pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; 800f2cc: 68fb ldr r3, [r7, #12] 800f2ce: 681a ldr r2, [r3, #0] 800f2d0: 68bb ldr r3, [r7, #8] 800f2d2: 331b adds r3, #27 800f2d4: 011b lsls r3, r3, #4 800f2d6: 4413 add r3, r2 800f2d8: 3304 adds r3, #4 800f2da: 681b ldr r3, [r3, #0] 800f2dc: 0a1b lsrs r3, r3, #8 800f2de: b2da uxtb r2, r3 800f2e0: 687b ldr r3, [r7, #4] 800f2e2: 619a str r2, [r3, #24] pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; 800f2e4: 68fb ldr r3, [r7, #12] 800f2e6: 681a ldr r2, [r3, #0] 800f2e8: 68bb ldr r3, [r7, #8] 800f2ea: 331b adds r3, #27 800f2ec: 011b lsls r3, r3, #4 800f2ee: 4413 add r3, r2 800f2f0: 3304 adds r3, #4 800f2f2: 681b ldr r3, [r3, #0] 800f2f4: 0c1b lsrs r3, r3, #16 800f2f6: b29a uxth r2, r3 800f2f8: 687b ldr r3, [r7, #4] 800f2fa: 615a str r2, [r3, #20] /* Get the data */ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); 800f2fc: 68fb ldr r3, [r7, #12] 800f2fe: 681a ldr r2, [r3, #0] 800f300: 68bb ldr r3, [r7, #8] 800f302: 011b lsls r3, r3, #4 800f304: 4413 add r3, r2 800f306: f503 73dc add.w r3, r3, #440 @ 0x1b8 800f30a: 681b ldr r3, [r3, #0] 800f30c: b2da uxtb r2, r3 800f30e: 683b ldr r3, [r7, #0] 800f310: 701a strb r2, [r3, #0] aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); 800f312: 68fb ldr r3, [r7, #12] 800f314: 681a ldr r2, [r3, #0] 800f316: 68bb ldr r3, [r7, #8] 800f318: 011b lsls r3, r3, #4 800f31a: 4413 add r3, r2 800f31c: f503 73dc add.w r3, r3, #440 @ 0x1b8 800f320: 681b ldr r3, [r3, #0] 800f322: 0a1a lsrs r2, r3, #8 800f324: 683b ldr r3, [r7, #0] 800f326: 3301 adds r3, #1 800f328: b2d2 uxtb r2, r2 800f32a: 701a strb r2, [r3, #0] aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); 800f32c: 68fb ldr r3, [r7, #12] 800f32e: 681a ldr r2, [r3, #0] 800f330: 68bb ldr r3, [r7, #8] 800f332: 011b lsls r3, r3, #4 800f334: 4413 add r3, r2 800f336: f503 73dc add.w r3, r3, #440 @ 0x1b8 800f33a: 681b ldr r3, [r3, #0] 800f33c: 0c1a lsrs r2, r3, #16 800f33e: 683b ldr r3, [r7, #0] 800f340: 3302 adds r3, #2 800f342: b2d2 uxtb r2, r2 800f344: 701a strb r2, [r3, #0] aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); 800f346: 68fb ldr r3, [r7, #12] 800f348: 681a ldr r2, [r3, #0] 800f34a: 68bb ldr r3, [r7, #8] 800f34c: 011b lsls r3, r3, #4 800f34e: 4413 add r3, r2 800f350: f503 73dc add.w r3, r3, #440 @ 0x1b8 800f354: 681b ldr r3, [r3, #0] 800f356: 0e1a lsrs r2, r3, #24 800f358: 683b ldr r3, [r7, #0] 800f35a: 3303 adds r3, #3 800f35c: b2d2 uxtb r2, r2 800f35e: 701a strb r2, [r3, #0] aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); 800f360: 68fb ldr r3, [r7, #12] 800f362: 681a ldr r2, [r3, #0] 800f364: 68bb ldr r3, [r7, #8] 800f366: 011b lsls r3, r3, #4 800f368: 4413 add r3, r2 800f36a: f503 73de add.w r3, r3, #444 @ 0x1bc 800f36e: 681a ldr r2, [r3, #0] 800f370: 683b ldr r3, [r7, #0] 800f372: 3304 adds r3, #4 800f374: b2d2 uxtb r2, r2 800f376: 701a strb r2, [r3, #0] aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); 800f378: 68fb ldr r3, [r7, #12] 800f37a: 681a ldr r2, [r3, #0] 800f37c: 68bb ldr r3, [r7, #8] 800f37e: 011b lsls r3, r3, #4 800f380: 4413 add r3, r2 800f382: f503 73de add.w r3, r3, #444 @ 0x1bc 800f386: 681b ldr r3, [r3, #0] 800f388: 0a1a lsrs r2, r3, #8 800f38a: 683b ldr r3, [r7, #0] 800f38c: 3305 adds r3, #5 800f38e: b2d2 uxtb r2, r2 800f390: 701a strb r2, [r3, #0] aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); 800f392: 68fb ldr r3, [r7, #12] 800f394: 681a ldr r2, [r3, #0] 800f396: 68bb ldr r3, [r7, #8] 800f398: 011b lsls r3, r3, #4 800f39a: 4413 add r3, r2 800f39c: f503 73de add.w r3, r3, #444 @ 0x1bc 800f3a0: 681b ldr r3, [r3, #0] 800f3a2: 0c1a lsrs r2, r3, #16 800f3a4: 683b ldr r3, [r7, #0] 800f3a6: 3306 adds r3, #6 800f3a8: b2d2 uxtb r2, r2 800f3aa: 701a strb r2, [r3, #0] aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); 800f3ac: 68fb ldr r3, [r7, #12] 800f3ae: 681a ldr r2, [r3, #0] 800f3b0: 68bb ldr r3, [r7, #8] 800f3b2: 011b lsls r3, r3, #4 800f3b4: 4413 add r3, r2 800f3b6: f503 73de add.w r3, r3, #444 @ 0x1bc 800f3ba: 681b ldr r3, [r3, #0] 800f3bc: 0e1a lsrs r2, r3, #24 800f3be: 683b ldr r3, [r7, #0] 800f3c0: 3307 adds r3, #7 800f3c2: b2d2 uxtb r2, r2 800f3c4: 701a strb r2, [r3, #0] /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800f3c6: 68bb ldr r3, [r7, #8] 800f3c8: 2b00 cmp r3, #0 800f3ca: d108 bne.n 800f3de { /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); 800f3cc: 68fb ldr r3, [r7, #12] 800f3ce: 681b ldr r3, [r3, #0] 800f3d0: 68da ldr r2, [r3, #12] 800f3d2: 68fb ldr r3, [r7, #12] 800f3d4: 681b ldr r3, [r3, #0] 800f3d6: f042 0220 orr.w r2, r2, #32 800f3da: 60da str r2, [r3, #12] 800f3dc: e007 b.n 800f3ee } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); 800f3de: 68fb ldr r3, [r7, #12] 800f3e0: 681b ldr r3, [r3, #0] 800f3e2: 691a ldr r2, [r3, #16] 800f3e4: 68fb ldr r3, [r7, #12] 800f3e6: 681b ldr r3, [r3, #0] 800f3e8: f042 0220 orr.w r2, r2, #32 800f3ec: 611a str r2, [r3, #16] } /* Return function status */ return HAL_OK; 800f3ee: 2300 movs r3, #0 800f3f0: e006 b.n 800f400 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f3f2: 68fb ldr r3, [r7, #12] 800f3f4: 6a5b ldr r3, [r3, #36] @ 0x24 800f3f6: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f3fa: 68fb ldr r3, [r7, #12] 800f3fc: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f3fe: 2301 movs r3, #1 } } 800f400: 4618 mov r0, r3 800f402: 371c adds r7, #28 800f404: 46bd mov sp, r7 800f406: bc80 pop {r7} 800f408: 4770 bx lr 0800f40a : * @param ActiveITs indicates which interrupts will be enabled. * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { 800f40a: b480 push {r7} 800f40c: b085 sub sp, #20 800f40e: af00 add r7, sp, #0 800f410: 6078 str r0, [r7, #4] 800f412: 6039 str r1, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800f414: 687b ldr r3, [r7, #4] 800f416: f893 3020 ldrb.w r3, [r3, #32] 800f41a: 73fb strb r3, [r7, #15] /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); if ((state == HAL_CAN_STATE_READY) || 800f41c: 7bfb ldrb r3, [r7, #15] 800f41e: 2b01 cmp r3, #1 800f420: d002 beq.n 800f428 800f422: 7bfb ldrb r3, [r7, #15] 800f424: 2b02 cmp r3, #2 800f426: d109 bne.n 800f43c (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); 800f428: 687b ldr r3, [r7, #4] 800f42a: 681b ldr r3, [r3, #0] 800f42c: 6959 ldr r1, [r3, #20] 800f42e: 687b ldr r3, [r7, #4] 800f430: 681b ldr r3, [r3, #0] 800f432: 683a ldr r2, [r7, #0] 800f434: 430a orrs r2, r1 800f436: 615a str r2, [r3, #20] /* Return function status */ return HAL_OK; 800f438: 2300 movs r3, #0 800f43a: e006 b.n 800f44a } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f43c: 687b ldr r3, [r7, #4] 800f43e: 6a5b ldr r3, [r3, #36] @ 0x24 800f440: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f444: 687b ldr r3, [r7, #4] 800f446: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f448: 2301 movs r3, #1 } } 800f44a: 4618 mov r0, r3 800f44c: 3714 adds r7, #20 800f44e: 46bd mov sp, r7 800f450: bc80 pop {r7} 800f452: 4770 bx lr 0800f454 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { 800f454: b580 push {r7, lr} 800f456: b08a sub sp, #40 @ 0x28 800f458: af00 add r7, sp, #0 800f45a: 6078 str r0, [r7, #4] uint32_t errorcode = HAL_CAN_ERROR_NONE; 800f45c: 2300 movs r3, #0 800f45e: 627b str r3, [r7, #36] @ 0x24 uint32_t interrupts = READ_REG(hcan->Instance->IER); 800f460: 687b ldr r3, [r7, #4] 800f462: 681b ldr r3, [r3, #0] 800f464: 695b ldr r3, [r3, #20] 800f466: 623b str r3, [r7, #32] uint32_t msrflags = READ_REG(hcan->Instance->MSR); 800f468: 687b ldr r3, [r7, #4] 800f46a: 681b ldr r3, [r3, #0] 800f46c: 685b ldr r3, [r3, #4] 800f46e: 61fb str r3, [r7, #28] uint32_t tsrflags = READ_REG(hcan->Instance->TSR); 800f470: 687b ldr r3, [r7, #4] 800f472: 681b ldr r3, [r3, #0] 800f474: 689b ldr r3, [r3, #8] 800f476: 61bb str r3, [r7, #24] uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); 800f478: 687b ldr r3, [r7, #4] 800f47a: 681b ldr r3, [r3, #0] 800f47c: 68db ldr r3, [r3, #12] 800f47e: 617b str r3, [r7, #20] uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); 800f480: 687b ldr r3, [r7, #4] 800f482: 681b ldr r3, [r3, #0] 800f484: 691b ldr r3, [r3, #16] 800f486: 613b str r3, [r7, #16] uint32_t esrflags = READ_REG(hcan->Instance->ESR); 800f488: 687b ldr r3, [r7, #4] 800f48a: 681b ldr r3, [r3, #0] 800f48c: 699b ldr r3, [r3, #24] 800f48e: 60fb str r3, [r7, #12] /* Transmit Mailbox empty interrupt management *****************************/ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) 800f490: 6a3b ldr r3, [r7, #32] 800f492: f003 0301 and.w r3, r3, #1 800f496: 2b00 cmp r3, #0 800f498: d07c beq.n 800f594 { /* Transmit Mailbox 0 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP0) != 0U) 800f49a: 69bb ldr r3, [r7, #24] 800f49c: f003 0301 and.w r3, r3, #1 800f4a0: 2b00 cmp r3, #0 800f4a2: d023 beq.n 800f4ec { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); 800f4a4: 687b ldr r3, [r7, #4] 800f4a6: 681b ldr r3, [r3, #0] 800f4a8: 2201 movs r2, #1 800f4aa: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK0) != 0U) 800f4ac: 69bb ldr r3, [r7, #24] 800f4ae: f003 0302 and.w r3, r3, #2 800f4b2: 2b00 cmp r3, #0 800f4b4: d003 beq.n 800f4be #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); 800f4b6: 6878 ldr r0, [r7, #4] 800f4b8: f000 f983 bl 800f7c2 800f4bc: e016 b.n 800f4ec #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST0) != 0U) 800f4be: 69bb ldr r3, [r7, #24] 800f4c0: f003 0304 and.w r3, r3, #4 800f4c4: 2b00 cmp r3, #0 800f4c6: d004 beq.n 800f4d2 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; 800f4c8: 6a7b ldr r3, [r7, #36] @ 0x24 800f4ca: f443 6300 orr.w r3, r3, #2048 @ 0x800 800f4ce: 627b str r3, [r7, #36] @ 0x24 800f4d0: e00c b.n 800f4ec } else if ((tsrflags & CAN_TSR_TERR0) != 0U) 800f4d2: 69bb ldr r3, [r7, #24] 800f4d4: f003 0308 and.w r3, r3, #8 800f4d8: 2b00 cmp r3, #0 800f4da: d004 beq.n 800f4e6 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; 800f4dc: 6a7b ldr r3, [r7, #36] @ 0x24 800f4de: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800f4e2: 627b str r3, [r7, #36] @ 0x24 800f4e4: e002 b.n 800f4ec #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); 800f4e6: 6878 ldr r0, [r7, #4] 800f4e8: f000 f986 bl 800f7f8 } } } /* Transmit Mailbox 1 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP1) != 0U) 800f4ec: 69bb ldr r3, [r7, #24] 800f4ee: f403 7380 and.w r3, r3, #256 @ 0x100 800f4f2: 2b00 cmp r3, #0 800f4f4: d024 beq.n 800f540 { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); 800f4f6: 687b ldr r3, [r7, #4] 800f4f8: 681b ldr r3, [r3, #0] 800f4fa: f44f 7280 mov.w r2, #256 @ 0x100 800f4fe: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK1) != 0U) 800f500: 69bb ldr r3, [r7, #24] 800f502: f403 7300 and.w r3, r3, #512 @ 0x200 800f506: 2b00 cmp r3, #0 800f508: d003 beq.n 800f512 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); 800f50a: 6878 ldr r0, [r7, #4] 800f50c: f000 f962 bl 800f7d4 800f510: e016 b.n 800f540 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST1) != 0U) 800f512: 69bb ldr r3, [r7, #24] 800f514: f403 6380 and.w r3, r3, #1024 @ 0x400 800f518: 2b00 cmp r3, #0 800f51a: d004 beq.n 800f526 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; 800f51c: 6a7b ldr r3, [r7, #36] @ 0x24 800f51e: f443 5300 orr.w r3, r3, #8192 @ 0x2000 800f522: 627b str r3, [r7, #36] @ 0x24 800f524: e00c b.n 800f540 } else if ((tsrflags & CAN_TSR_TERR1) != 0U) 800f526: 69bb ldr r3, [r7, #24] 800f528: f403 6300 and.w r3, r3, #2048 @ 0x800 800f52c: 2b00 cmp r3, #0 800f52e: d004 beq.n 800f53a { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; 800f530: 6a7b ldr r3, [r7, #36] @ 0x24 800f532: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800f536: 627b str r3, [r7, #36] @ 0x24 800f538: e002 b.n 800f540 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); 800f53a: 6878 ldr r0, [r7, #4] 800f53c: f000 f965 bl 800f80a } } } /* Transmit Mailbox 2 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP2) != 0U) 800f540: 69bb ldr r3, [r7, #24] 800f542: f403 3380 and.w r3, r3, #65536 @ 0x10000 800f546: 2b00 cmp r3, #0 800f548: d024 beq.n 800f594 { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); 800f54a: 687b ldr r3, [r7, #4] 800f54c: 681b ldr r3, [r3, #0] 800f54e: f44f 3280 mov.w r2, #65536 @ 0x10000 800f552: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK2) != 0U) 800f554: 69bb ldr r3, [r7, #24] 800f556: f403 3300 and.w r3, r3, #131072 @ 0x20000 800f55a: 2b00 cmp r3, #0 800f55c: d003 beq.n 800f566 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); 800f55e: 6878 ldr r0, [r7, #4] 800f560: f000 f941 bl 800f7e6 800f564: e016 b.n 800f594 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST2) != 0U) 800f566: 69bb ldr r3, [r7, #24] 800f568: f403 2380 and.w r3, r3, #262144 @ 0x40000 800f56c: 2b00 cmp r3, #0 800f56e: d004 beq.n 800f57a { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; 800f570: 6a7b ldr r3, [r7, #36] @ 0x24 800f572: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f576: 627b str r3, [r7, #36] @ 0x24 800f578: e00c b.n 800f594 } else if ((tsrflags & CAN_TSR_TERR2) != 0U) 800f57a: 69bb ldr r3, [r7, #24] 800f57c: f403 2300 and.w r3, r3, #524288 @ 0x80000 800f580: 2b00 cmp r3, #0 800f582: d004 beq.n 800f58e { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; 800f584: 6a7b ldr r3, [r7, #36] @ 0x24 800f586: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800f58a: 627b str r3, [r7, #36] @ 0x24 800f58c: e002 b.n 800f594 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); 800f58e: 6878 ldr r0, [r7, #4] 800f590: f000 f944 bl 800f81c } } } /* Receive FIFO 0 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) 800f594: 6a3b ldr r3, [r7, #32] 800f596: f003 0308 and.w r3, r3, #8 800f59a: 2b00 cmp r3, #0 800f59c: d00c beq.n 800f5b8 { if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) 800f59e: 697b ldr r3, [r7, #20] 800f5a0: f003 0310 and.w r3, r3, #16 800f5a4: 2b00 cmp r3, #0 800f5a6: d007 beq.n 800f5b8 { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; 800f5a8: 6a7b ldr r3, [r7, #36] @ 0x24 800f5aa: f443 7300 orr.w r3, r3, #512 @ 0x200 800f5ae: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO0 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); 800f5b0: 687b ldr r3, [r7, #4] 800f5b2: 681b ldr r3, [r3, #0] 800f5b4: 2210 movs r2, #16 800f5b6: 60da str r2, [r3, #12] } } /* Receive FIFO 0 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) 800f5b8: 6a3b ldr r3, [r7, #32] 800f5ba: f003 0304 and.w r3, r3, #4 800f5be: 2b00 cmp r3, #0 800f5c0: d00b beq.n 800f5da { if ((rf0rflags & CAN_RF0R_FULL0) != 0U) 800f5c2: 697b ldr r3, [r7, #20] 800f5c4: f003 0308 and.w r3, r3, #8 800f5c8: 2b00 cmp r3, #0 800f5ca: d006 beq.n 800f5da { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); 800f5cc: 687b ldr r3, [r7, #4] 800f5ce: 681b ldr r3, [r3, #0] 800f5d0: 2208 movs r2, #8 800f5d2: 60da str r2, [r3, #12] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); 800f5d4: 6878 ldr r0, [r7, #4] 800f5d6: f000 f933 bl 800f840 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) 800f5da: 6a3b ldr r3, [r7, #32] 800f5dc: f003 0302 and.w r3, r3, #2 800f5e0: 2b00 cmp r3, #0 800f5e2: d009 beq.n 800f5f8 { /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) 800f5e4: 687b ldr r3, [r7, #4] 800f5e6: 681b ldr r3, [r3, #0] 800f5e8: 68db ldr r3, [r3, #12] 800f5ea: f003 0303 and.w r3, r3, #3 800f5ee: 2b00 cmp r3, #0 800f5f0: d002 beq.n 800f5f8 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); 800f5f2: 6878 ldr r0, [r7, #4] 800f5f4: f000 f91b bl 800f82e #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) 800f5f8: 6a3b ldr r3, [r7, #32] 800f5fa: f003 0340 and.w r3, r3, #64 @ 0x40 800f5fe: 2b00 cmp r3, #0 800f600: d00c beq.n 800f61c { if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) 800f602: 693b ldr r3, [r7, #16] 800f604: f003 0310 and.w r3, r3, #16 800f608: 2b00 cmp r3, #0 800f60a: d007 beq.n 800f61c { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; 800f60c: 6a7b ldr r3, [r7, #36] @ 0x24 800f60e: f443 6380 orr.w r3, r3, #1024 @ 0x400 800f612: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO1 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); 800f614: 687b ldr r3, [r7, #4] 800f616: 681b ldr r3, [r3, #0] 800f618: 2210 movs r2, #16 800f61a: 611a str r2, [r3, #16] } } /* Receive FIFO 1 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) 800f61c: 6a3b ldr r3, [r7, #32] 800f61e: f003 0320 and.w r3, r3, #32 800f622: 2b00 cmp r3, #0 800f624: d00b beq.n 800f63e { if ((rf1rflags & CAN_RF1R_FULL1) != 0U) 800f626: 693b ldr r3, [r7, #16] 800f628: f003 0308 and.w r3, r3, #8 800f62c: 2b00 cmp r3, #0 800f62e: d006 beq.n 800f63e { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); 800f630: 687b ldr r3, [r7, #4] 800f632: 681b ldr r3, [r3, #0] 800f634: 2208 movs r2, #8 800f636: 611a str r2, [r3, #16] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); 800f638: 6878 ldr r0, [r7, #4] 800f63a: f000 f90a bl 800f852 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) 800f63e: 6a3b ldr r3, [r7, #32] 800f640: f003 0310 and.w r3, r3, #16 800f644: 2b00 cmp r3, #0 800f646: d009 beq.n 800f65c { /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) 800f648: 687b ldr r3, [r7, #4] 800f64a: 681b ldr r3, [r3, #0] 800f64c: 691b ldr r3, [r3, #16] 800f64e: f003 0303 and.w r3, r3, #3 800f652: 2b00 cmp r3, #0 800f654: d002 beq.n 800f65c #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); 800f656: 6878 ldr r0, [r7, #4] 800f658: f7fb fb4a bl 800acf0 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) 800f65c: 6a3b ldr r3, [r7, #32] 800f65e: f403 3300 and.w r3, r3, #131072 @ 0x20000 800f662: 2b00 cmp r3, #0 800f664: d00b beq.n 800f67e { if ((msrflags & CAN_MSR_SLAKI) != 0U) 800f666: 69fb ldr r3, [r7, #28] 800f668: f003 0310 and.w r3, r3, #16 800f66c: 2b00 cmp r3, #0 800f66e: d006 beq.n 800f67e { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); 800f670: 687b ldr r3, [r7, #4] 800f672: 681b ldr r3, [r3, #0] 800f674: 2210 movs r2, #16 800f676: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->SleepCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); 800f678: 6878 ldr r0, [r7, #4] 800f67a: f000 f8f3 bl 800f864 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ if ((interrupts & CAN_IT_WAKEUP) != 0U) 800f67e: 6a3b ldr r3, [r7, #32] 800f680: f403 3380 and.w r3, r3, #65536 @ 0x10000 800f684: 2b00 cmp r3, #0 800f686: d00b beq.n 800f6a0 { if ((msrflags & CAN_MSR_WKUI) != 0U) 800f688: 69fb ldr r3, [r7, #28] 800f68a: f003 0308 and.w r3, r3, #8 800f68e: 2b00 cmp r3, #0 800f690: d006 beq.n 800f6a0 { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); 800f692: 687b ldr r3, [r7, #4] 800f694: 681b ldr r3, [r3, #0] 800f696: 2208 movs r2, #8 800f698: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->WakeUpFromRxMsgCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); 800f69a: 6878 ldr r0, [r7, #4] 800f69c: f000 f8eb bl 800f876 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ if ((interrupts & CAN_IT_ERROR) != 0U) 800f6a0: 6a3b ldr r3, [r7, #32] 800f6a2: f403 4300 and.w r3, r3, #32768 @ 0x8000 800f6a6: 2b00 cmp r3, #0 800f6a8: d07b beq.n 800f7a2 { if ((msrflags & CAN_MSR_ERRI) != 0U) 800f6aa: 69fb ldr r3, [r7, #28] 800f6ac: f003 0304 and.w r3, r3, #4 800f6b0: 2b00 cmp r3, #0 800f6b2: d072 beq.n 800f79a { /* Check Error Warning Flag */ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800f6b4: 6a3b ldr r3, [r7, #32] 800f6b6: f403 7380 and.w r3, r3, #256 @ 0x100 800f6ba: 2b00 cmp r3, #0 800f6bc: d008 beq.n 800f6d0 ((esrflags & CAN_ESR_EWGF) != 0U)) 800f6be: 68fb ldr r3, [r7, #12] 800f6c0: f003 0301 and.w r3, r3, #1 if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800f6c4: 2b00 cmp r3, #0 800f6c6: d003 beq.n 800f6d0 { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; 800f6c8: 6a7b ldr r3, [r7, #36] @ 0x24 800f6ca: f043 0301 orr.w r3, r3, #1 800f6ce: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Warning Flag as read-only */ } /* Check Error Passive Flag */ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800f6d0: 6a3b ldr r3, [r7, #32] 800f6d2: f403 7300 and.w r3, r3, #512 @ 0x200 800f6d6: 2b00 cmp r3, #0 800f6d8: d008 beq.n 800f6ec ((esrflags & CAN_ESR_EPVF) != 0U)) 800f6da: 68fb ldr r3, [r7, #12] 800f6dc: f003 0302 and.w r3, r3, #2 if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800f6e0: 2b00 cmp r3, #0 800f6e2: d003 beq.n 800f6ec { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; 800f6e4: 6a7b ldr r3, [r7, #36] @ 0x24 800f6e6: f043 0302 orr.w r3, r3, #2 800f6ea: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-off Flag */ if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800f6ec: 6a3b ldr r3, [r7, #32] 800f6ee: f403 6380 and.w r3, r3, #1024 @ 0x400 800f6f2: 2b00 cmp r3, #0 800f6f4: d008 beq.n 800f708 ((esrflags & CAN_ESR_BOFF) != 0U)) 800f6f6: 68fb ldr r3, [r7, #12] 800f6f8: f003 0304 and.w r3, r3, #4 if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800f6fc: 2b00 cmp r3, #0 800f6fe: d003 beq.n 800f708 { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; 800f700: 6a7b ldr r3, [r7, #36] @ 0x24 800f702: f043 0304 orr.w r3, r3, #4 800f706: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Bus-Off as read-only */ } /* Check Last Error Code Flag */ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800f708: 6a3b ldr r3, [r7, #32] 800f70a: f403 6300 and.w r3, r3, #2048 @ 0x800 800f70e: 2b00 cmp r3, #0 800f710: d043 beq.n 800f79a ((esrflags & CAN_ESR_LEC) != 0U)) 800f712: 68fb ldr r3, [r7, #12] 800f714: f003 0370 and.w r3, r3, #112 @ 0x70 if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800f718: 2b00 cmp r3, #0 800f71a: d03e beq.n 800f79a { switch (esrflags & CAN_ESR_LEC) 800f71c: 68fb ldr r3, [r7, #12] 800f71e: f003 0370 and.w r3, r3, #112 @ 0x70 800f722: 2b60 cmp r3, #96 @ 0x60 800f724: d02b beq.n 800f77e 800f726: 2b60 cmp r3, #96 @ 0x60 800f728: d82e bhi.n 800f788 800f72a: 2b50 cmp r3, #80 @ 0x50 800f72c: d022 beq.n 800f774 800f72e: 2b50 cmp r3, #80 @ 0x50 800f730: d82a bhi.n 800f788 800f732: 2b40 cmp r3, #64 @ 0x40 800f734: d019 beq.n 800f76a 800f736: 2b40 cmp r3, #64 @ 0x40 800f738: d826 bhi.n 800f788 800f73a: 2b30 cmp r3, #48 @ 0x30 800f73c: d010 beq.n 800f760 800f73e: 2b30 cmp r3, #48 @ 0x30 800f740: d822 bhi.n 800f788 800f742: 2b10 cmp r3, #16 800f744: d002 beq.n 800f74c 800f746: 2b20 cmp r3, #32 800f748: d005 beq.n 800f756 case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): /* Set CAN error code to CRC error */ errorcode |= HAL_CAN_ERROR_CRC; break; default: break; 800f74a: e01d b.n 800f788 errorcode |= HAL_CAN_ERROR_STF; 800f74c: 6a7b ldr r3, [r7, #36] @ 0x24 800f74e: f043 0308 orr.w r3, r3, #8 800f752: 627b str r3, [r7, #36] @ 0x24 break; 800f754: e019 b.n 800f78a errorcode |= HAL_CAN_ERROR_FOR; 800f756: 6a7b ldr r3, [r7, #36] @ 0x24 800f758: f043 0310 orr.w r3, r3, #16 800f75c: 627b str r3, [r7, #36] @ 0x24 break; 800f75e: e014 b.n 800f78a errorcode |= HAL_CAN_ERROR_ACK; 800f760: 6a7b ldr r3, [r7, #36] @ 0x24 800f762: f043 0320 orr.w r3, r3, #32 800f766: 627b str r3, [r7, #36] @ 0x24 break; 800f768: e00f b.n 800f78a errorcode |= HAL_CAN_ERROR_BR; 800f76a: 6a7b ldr r3, [r7, #36] @ 0x24 800f76c: f043 0340 orr.w r3, r3, #64 @ 0x40 800f770: 627b str r3, [r7, #36] @ 0x24 break; 800f772: e00a b.n 800f78a errorcode |= HAL_CAN_ERROR_BD; 800f774: 6a7b ldr r3, [r7, #36] @ 0x24 800f776: f043 0380 orr.w r3, r3, #128 @ 0x80 800f77a: 627b str r3, [r7, #36] @ 0x24 break; 800f77c: e005 b.n 800f78a errorcode |= HAL_CAN_ERROR_CRC; 800f77e: 6a7b ldr r3, [r7, #36] @ 0x24 800f780: f443 7380 orr.w r3, r3, #256 @ 0x100 800f784: 627b str r3, [r7, #36] @ 0x24 break; 800f786: e000 b.n 800f78a break; 800f788: bf00 nop } /* Clear Last error code Flag */ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); 800f78a: 687b ldr r3, [r7, #4] 800f78c: 681b ldr r3, [r3, #0] 800f78e: 699a ldr r2, [r3, #24] 800f790: 687b ldr r3, [r7, #4] 800f792: 681b ldr r3, [r3, #0] 800f794: f022 0270 bic.w r2, r2, #112 @ 0x70 800f798: 619a str r2, [r3, #24] } } /* Clear ERRI Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); 800f79a: 687b ldr r3, [r7, #4] 800f79c: 681b ldr r3, [r3, #0] 800f79e: 2204 movs r2, #4 800f7a0: 605a str r2, [r3, #4] } /* Call the Error call Back in case of Errors */ if (errorcode != HAL_CAN_ERROR_NONE) 800f7a2: 6a7b ldr r3, [r7, #36] @ 0x24 800f7a4: 2b00 cmp r3, #0 800f7a6: d008 beq.n 800f7ba { /* Update error code in handle */ hcan->ErrorCode |= errorcode; 800f7a8: 687b ldr r3, [r7, #4] 800f7aa: 6a5a ldr r2, [r3, #36] @ 0x24 800f7ac: 6a7b ldr r3, [r7, #36] @ 0x24 800f7ae: 431a orrs r2, r3 800f7b0: 687b ldr r3, [r7, #4] 800f7b2: 625a str r2, [r3, #36] @ 0x24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->ErrorCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); 800f7b4: 6878 ldr r0, [r7, #4] 800f7b6: f000 f867 bl 800f888 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } 800f7ba: bf00 nop 800f7bc: 3728 adds r7, #40 @ 0x28 800f7be: 46bd mov sp, r7 800f7c0: bd80 pop {r7, pc} 0800f7c2 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { 800f7c2: b480 push {r7} 800f7c4: b083 sub sp, #12 800f7c6: af00 add r7, sp, #0 800f7c8: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the user file */ } 800f7ca: bf00 nop 800f7cc: 370c adds r7, #12 800f7ce: 46bd mov sp, r7 800f7d0: bc80 pop {r7} 800f7d2: 4770 bx lr 0800f7d4 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { 800f7d4: b480 push {r7} 800f7d6: b083 sub sp, #12 800f7d8: af00 add r7, sp, #0 800f7da: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the user file */ } 800f7dc: bf00 nop 800f7de: 370c adds r7, #12 800f7e0: 46bd mov sp, r7 800f7e2: bc80 pop {r7} 800f7e4: 4770 bx lr 0800f7e6 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) { 800f7e6: b480 push {r7} 800f7e8: b083 sub sp, #12 800f7ea: af00 add r7, sp, #0 800f7ec: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the user file */ } 800f7ee: bf00 nop 800f7f0: 370c adds r7, #12 800f7f2: 46bd mov sp, r7 800f7f4: bc80 pop {r7} 800f7f6: 4770 bx lr 0800f7f8 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { 800f7f8: b480 push {r7} 800f7fa: b083 sub sp, #12 800f7fc: af00 add r7, sp, #0 800f7fe: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0AbortCallback could be implemented in the user file */ } 800f800: bf00 nop 800f802: 370c adds r7, #12 800f804: 46bd mov sp, r7 800f806: bc80 pop {r7} 800f808: 4770 bx lr 0800f80a : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { 800f80a: b480 push {r7} 800f80c: b083 sub sp, #12 800f80e: af00 add r7, sp, #0 800f810: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1AbortCallback could be implemented in the user file */ } 800f812: bf00 nop 800f814: 370c adds r7, #12 800f816: 46bd mov sp, r7 800f818: bc80 pop {r7} 800f81a: 4770 bx lr 0800f81c : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { 800f81c: b480 push {r7} 800f81e: b083 sub sp, #12 800f820: af00 add r7, sp, #0 800f822: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2AbortCallback could be implemented in the user file */ } 800f824: bf00 nop 800f826: 370c adds r7, #12 800f828: 46bd mov sp, r7 800f82a: bc80 pop {r7} 800f82c: 4770 bx lr 0800f82e : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) { 800f82e: b480 push {r7} 800f830: b083 sub sp, #12 800f832: af00 add r7, sp, #0 800f834: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the user file */ } 800f836: bf00 nop 800f838: 370c adds r7, #12 800f83a: 46bd mov sp, r7 800f83c: bc80 pop {r7} 800f83e: 4770 bx lr 0800f840 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { 800f840: b480 push {r7} 800f842: b083 sub sp, #12 800f844: af00 add r7, sp, #0 800f846: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0FullCallback could be implemented in the user file */ } 800f848: bf00 nop 800f84a: 370c adds r7, #12 800f84c: 46bd mov sp, r7 800f84e: bc80 pop {r7} 800f850: 4770 bx lr 0800f852 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { 800f852: b480 push {r7} 800f854: b083 sub sp, #12 800f856: af00 add r7, sp, #0 800f858: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1FullCallback could be implemented in the user file */ } 800f85a: bf00 nop 800f85c: 370c adds r7, #12 800f85e: 46bd mov sp, r7 800f860: bc80 pop {r7} 800f862: 4770 bx lr 0800f864 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { 800f864: b480 push {r7} 800f866: b083 sub sp, #12 800f868: af00 add r7, sp, #0 800f86a: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_SleepCallback could be implemented in the user file */ } 800f86c: bf00 nop 800f86e: 370c adds r7, #12 800f870: 46bd mov sp, r7 800f872: bc80 pop {r7} 800f874: 4770 bx lr 0800f876 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { 800f876: b480 push {r7} 800f878: b083 sub sp, #12 800f87a: af00 add r7, sp, #0 800f87c: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the user file */ } 800f87e: bf00 nop 800f880: 370c adds r7, #12 800f882: 46bd mov sp, r7 800f884: bc80 pop {r7} 800f886: 4770 bx lr 0800f888 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { 800f888: b480 push {r7} 800f88a: b083 sub sp, #12 800f88c: af00 add r7, sp, #0 800f88e: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } 800f890: bf00 nop 800f892: 370c adds r7, #12 800f894: 46bd mov sp, r7 800f896: bc80 pop {r7} 800f898: 4770 bx lr ... 0800f89c <__NVIC_SetPriorityGrouping>: { 800f89c: b480 push {r7} 800f89e: b085 sub sp, #20 800f8a0: af00 add r7, sp, #0 800f8a2: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800f8a4: 687b ldr r3, [r7, #4] 800f8a6: f003 0307 and.w r3, r3, #7 800f8aa: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 800f8ac: 4b0c ldr r3, [pc, #48] @ (800f8e0 <__NVIC_SetPriorityGrouping+0x44>) 800f8ae: 68db ldr r3, [r3, #12] 800f8b0: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800f8b2: 68ba ldr r2, [r7, #8] 800f8b4: f64f 03ff movw r3, #63743 @ 0xf8ff 800f8b8: 4013 ands r3, r2 800f8ba: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 800f8bc: 68fb ldr r3, [r7, #12] 800f8be: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800f8c0: 68bb ldr r3, [r7, #8] 800f8c2: 4313 orrs r3, r2 reg_value = (reg_value | 800f8c4: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 800f8c8: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800f8cc: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800f8ce: 4a04 ldr r2, [pc, #16] @ (800f8e0 <__NVIC_SetPriorityGrouping+0x44>) 800f8d0: 68bb ldr r3, [r7, #8] 800f8d2: 60d3 str r3, [r2, #12] } 800f8d4: bf00 nop 800f8d6: 3714 adds r7, #20 800f8d8: 46bd mov sp, r7 800f8da: bc80 pop {r7} 800f8dc: 4770 bx lr 800f8de: bf00 nop 800f8e0: e000ed00 .word 0xe000ed00 0800f8e4 <__NVIC_GetPriorityGrouping>: { 800f8e4: b480 push {r7} 800f8e6: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800f8e8: 4b04 ldr r3, [pc, #16] @ (800f8fc <__NVIC_GetPriorityGrouping+0x18>) 800f8ea: 68db ldr r3, [r3, #12] 800f8ec: 0a1b lsrs r3, r3, #8 800f8ee: f003 0307 and.w r3, r3, #7 } 800f8f2: 4618 mov r0, r3 800f8f4: 46bd mov sp, r7 800f8f6: bc80 pop {r7} 800f8f8: 4770 bx lr 800f8fa: bf00 nop 800f8fc: e000ed00 .word 0xe000ed00 0800f900 <__NVIC_EnableIRQ>: { 800f900: b480 push {r7} 800f902: b083 sub sp, #12 800f904: af00 add r7, sp, #0 800f906: 4603 mov r3, r0 800f908: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800f90a: f997 3007 ldrsb.w r3, [r7, #7] 800f90e: 2b00 cmp r3, #0 800f910: db0b blt.n 800f92a <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800f912: 79fb ldrb r3, [r7, #7] 800f914: f003 021f and.w r2, r3, #31 800f918: 4906 ldr r1, [pc, #24] @ (800f934 <__NVIC_EnableIRQ+0x34>) 800f91a: f997 3007 ldrsb.w r3, [r7, #7] 800f91e: 095b lsrs r3, r3, #5 800f920: 2001 movs r0, #1 800f922: fa00 f202 lsl.w r2, r0, r2 800f926: f841 2023 str.w r2, [r1, r3, lsl #2] } 800f92a: bf00 nop 800f92c: 370c adds r7, #12 800f92e: 46bd mov sp, r7 800f930: bc80 pop {r7} 800f932: 4770 bx lr 800f934: e000e100 .word 0xe000e100 0800f938 <__NVIC_DisableIRQ>: { 800f938: b480 push {r7} 800f93a: b083 sub sp, #12 800f93c: af00 add r7, sp, #0 800f93e: 4603 mov r3, r0 800f940: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800f942: f997 3007 ldrsb.w r3, [r7, #7] 800f946: 2b00 cmp r3, #0 800f948: db12 blt.n 800f970 <__NVIC_DisableIRQ+0x38> NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800f94a: 79fb ldrb r3, [r7, #7] 800f94c: f003 021f and.w r2, r3, #31 800f950: 490a ldr r1, [pc, #40] @ (800f97c <__NVIC_DisableIRQ+0x44>) 800f952: f997 3007 ldrsb.w r3, [r7, #7] 800f956: 095b lsrs r3, r3, #5 800f958: 2001 movs r0, #1 800f95a: fa00 f202 lsl.w r2, r0, r2 800f95e: 3320 adds r3, #32 800f960: f841 2023 str.w r2, [r1, r3, lsl #2] __ASM volatile ("dsb 0xF":::"memory"); 800f964: f3bf 8f4f dsb sy } 800f968: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 800f96a: f3bf 8f6f isb sy } 800f96e: bf00 nop } 800f970: bf00 nop 800f972: 370c adds r7, #12 800f974: 46bd mov sp, r7 800f976: bc80 pop {r7} 800f978: 4770 bx lr 800f97a: bf00 nop 800f97c: e000e100 .word 0xe000e100 0800f980 <__NVIC_SetPriority>: { 800f980: b480 push {r7} 800f982: b083 sub sp, #12 800f984: af00 add r7, sp, #0 800f986: 4603 mov r3, r0 800f988: 6039 str r1, [r7, #0] 800f98a: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800f98c: f997 3007 ldrsb.w r3, [r7, #7] 800f990: 2b00 cmp r3, #0 800f992: db0a blt.n 800f9aa <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800f994: 683b ldr r3, [r7, #0] 800f996: b2da uxtb r2, r3 800f998: 490c ldr r1, [pc, #48] @ (800f9cc <__NVIC_SetPriority+0x4c>) 800f99a: f997 3007 ldrsb.w r3, [r7, #7] 800f99e: 0112 lsls r2, r2, #4 800f9a0: b2d2 uxtb r2, r2 800f9a2: 440b add r3, r1 800f9a4: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 800f9a8: e00a b.n 800f9c0 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800f9aa: 683b ldr r3, [r7, #0] 800f9ac: b2da uxtb r2, r3 800f9ae: 4908 ldr r1, [pc, #32] @ (800f9d0 <__NVIC_SetPriority+0x50>) 800f9b0: 79fb ldrb r3, [r7, #7] 800f9b2: f003 030f and.w r3, r3, #15 800f9b6: 3b04 subs r3, #4 800f9b8: 0112 lsls r2, r2, #4 800f9ba: b2d2 uxtb r2, r2 800f9bc: 440b add r3, r1 800f9be: 761a strb r2, [r3, #24] } 800f9c0: bf00 nop 800f9c2: 370c adds r7, #12 800f9c4: 46bd mov sp, r7 800f9c6: bc80 pop {r7} 800f9c8: 4770 bx lr 800f9ca: bf00 nop 800f9cc: e000e100 .word 0xe000e100 800f9d0: e000ed00 .word 0xe000ed00 0800f9d4 : { 800f9d4: b480 push {r7} 800f9d6: b089 sub sp, #36 @ 0x24 800f9d8: af00 add r7, sp, #0 800f9da: 60f8 str r0, [r7, #12] 800f9dc: 60b9 str r1, [r7, #8] 800f9de: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800f9e0: 68fb ldr r3, [r7, #12] 800f9e2: f003 0307 and.w r3, r3, #7 800f9e6: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 800f9e8: 69fb ldr r3, [r7, #28] 800f9ea: f1c3 0307 rsb r3, r3, #7 800f9ee: 2b04 cmp r3, #4 800f9f0: bf28 it cs 800f9f2: 2304 movcs r3, #4 800f9f4: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800f9f6: 69fb ldr r3, [r7, #28] 800f9f8: 3304 adds r3, #4 800f9fa: 2b06 cmp r3, #6 800f9fc: d902 bls.n 800fa04 800f9fe: 69fb ldr r3, [r7, #28] 800fa00: 3b03 subs r3, #3 800fa02: e000 b.n 800fa06 800fa04: 2300 movs r3, #0 800fa06: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800fa08: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800fa0c: 69bb ldr r3, [r7, #24] 800fa0e: fa02 f303 lsl.w r3, r2, r3 800fa12: 43da mvns r2, r3 800fa14: 68bb ldr r3, [r7, #8] 800fa16: 401a ands r2, r3 800fa18: 697b ldr r3, [r7, #20] 800fa1a: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 800fa1c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800fa20: 697b ldr r3, [r7, #20] 800fa22: fa01 f303 lsl.w r3, r1, r3 800fa26: 43d9 mvns r1, r3 800fa28: 687b ldr r3, [r7, #4] 800fa2a: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800fa2c: 4313 orrs r3, r2 } 800fa2e: 4618 mov r0, r3 800fa30: 3724 adds r7, #36 @ 0x24 800fa32: 46bd mov sp, r7 800fa34: bc80 pop {r7} 800fa36: 4770 bx lr 0800fa38 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800fa38: b580 push {r7, lr} 800fa3a: b082 sub sp, #8 800fa3c: af00 add r7, sp, #0 800fa3e: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 800fa40: 687b ldr r3, [r7, #4] 800fa42: 3b01 subs r3, #1 800fa44: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800fa48: d301 bcc.n 800fa4e { return (1UL); /* Reload value impossible */ 800fa4a: 2301 movs r3, #1 800fa4c: e00f b.n 800fa6e } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800fa4e: 4a0a ldr r2, [pc, #40] @ (800fa78 ) 800fa50: 687b ldr r3, [r7, #4] 800fa52: 3b01 subs r3, #1 800fa54: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800fa56: 210f movs r1, #15 800fa58: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800fa5c: f7ff ff90 bl 800f980 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 800fa60: 4b05 ldr r3, [pc, #20] @ (800fa78 ) 800fa62: 2200 movs r2, #0 800fa64: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800fa66: 4b04 ldr r3, [pc, #16] @ (800fa78 ) 800fa68: 2207 movs r2, #7 800fa6a: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 800fa6c: 2300 movs r3, #0 } 800fa6e: 4618 mov r0, r3 800fa70: 3708 adds r7, #8 800fa72: 46bd mov sp, r7 800fa74: bd80 pop {r7, pc} 800fa76: bf00 nop 800fa78: e000e010 .word 0xe000e010 0800fa7c : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 800fa7c: b580 push {r7, lr} 800fa7e: b082 sub sp, #8 800fa80: af00 add r7, sp, #0 800fa82: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800fa84: 6878 ldr r0, [r7, #4] 800fa86: f7ff ff09 bl 800f89c <__NVIC_SetPriorityGrouping> } 800fa8a: bf00 nop 800fa8c: 3708 adds r7, #8 800fa8e: 46bd mov sp, r7 800fa90: bd80 pop {r7, pc} 0800fa92 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800fa92: b580 push {r7, lr} 800fa94: b086 sub sp, #24 800fa96: af00 add r7, sp, #0 800fa98: 4603 mov r3, r0 800fa9a: 60b9 str r1, [r7, #8] 800fa9c: 607a str r2, [r7, #4] 800fa9e: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 800faa0: 2300 movs r3, #0 800faa2: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800faa4: f7ff ff1e bl 800f8e4 <__NVIC_GetPriorityGrouping> 800faa8: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 800faaa: 687a ldr r2, [r7, #4] 800faac: 68b9 ldr r1, [r7, #8] 800faae: 6978 ldr r0, [r7, #20] 800fab0: f7ff ff90 bl 800f9d4 800fab4: 4602 mov r2, r0 800fab6: f997 300f ldrsb.w r3, [r7, #15] 800faba: 4611 mov r1, r2 800fabc: 4618 mov r0, r3 800fabe: f7ff ff5f bl 800f980 <__NVIC_SetPriority> } 800fac2: bf00 nop 800fac4: 3718 adds r7, #24 800fac6: 46bd mov sp, r7 800fac8: bd80 pop {r7, pc} 0800faca : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 800faca: b580 push {r7, lr} 800facc: b082 sub sp, #8 800face: af00 add r7, sp, #0 800fad0: 4603 mov r3, r0 800fad2: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800fad4: f997 3007 ldrsb.w r3, [r7, #7] 800fad8: 4618 mov r0, r3 800fada: f7ff ff11 bl 800f900 <__NVIC_EnableIRQ> } 800fade: bf00 nop 800fae0: 3708 adds r7, #8 800fae2: 46bd mov sp, r7 800fae4: bd80 pop {r7, pc} 0800fae6 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) { 800fae6: b580 push {r7, lr} 800fae8: b082 sub sp, #8 800faea: af00 add r7, sp, #0 800faec: 4603 mov r3, r0 800faee: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Disable interrupt */ NVIC_DisableIRQ(IRQn); 800faf0: f997 3007 ldrsb.w r3, [r7, #7] 800faf4: 4618 mov r0, r3 800faf6: f7ff ff1f bl 800f938 <__NVIC_DisableIRQ> } 800fafa: bf00 nop 800fafc: 3708 adds r7, #8 800fafe: 46bd mov sp, r7 800fb00: bd80 pop {r7, pc} 0800fb02 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800fb02: b580 push {r7, lr} 800fb04: b082 sub sp, #8 800fb06: af00 add r7, sp, #0 800fb08: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800fb0a: 6878 ldr r0, [r7, #4] 800fb0c: f7ff ff94 bl 800fa38 800fb10: 4603 mov r3, r0 } 800fb12: 4618 mov r0, r3 800fb14: 3708 adds r7, #8 800fb16: 46bd mov sp, r7 800fb18: bd80 pop {r7, pc} 0800fb1a : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 800fb1a: b580 push {r7, lr} 800fb1c: b082 sub sp, #8 800fb1e: af00 add r7, sp, #0 800fb20: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 800fb22: 687b ldr r3, [r7, #4] 800fb24: 2b00 cmp r3, #0 800fb26: d101 bne.n 800fb2c { return HAL_ERROR; 800fb28: 2301 movs r3, #1 800fb2a: e00e b.n 800fb4a } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 800fb2c: 687b ldr r3, [r7, #4] 800fb2e: 795b ldrb r3, [r3, #5] 800fb30: b2db uxtb r3, r3 800fb32: 2b00 cmp r3, #0 800fb34: d105 bne.n 800fb42 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 800fb36: 687b ldr r3, [r7, #4] 800fb38: 2200 movs r2, #0 800fb3a: 711a strb r2, [r3, #4] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 800fb3c: 6878 ldr r0, [r7, #4] 800fb3e: f7fa fbcb bl 800a2d8 } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 800fb42: 687b ldr r3, [r7, #4] 800fb44: 2201 movs r2, #1 800fb46: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 800fb48: 2300 movs r3, #0 } 800fb4a: 4618 mov r0, r3 800fb4c: 3708 adds r7, #8 800fb4e: 46bd mov sp, r7 800fb50: bd80 pop {r7, pc} ... 0800fb54 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 800fb54: b480 push {r7} 800fb56: b085 sub sp, #20 800fb58: af00 add r7, sp, #0 800fb5a: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 800fb5c: 2300 movs r3, #0 800fb5e: 60fb str r3, [r7, #12] /* Check the DMA handle allocation */ if(hdma == NULL) 800fb60: 687b ldr r3, [r7, #4] 800fb62: 2b00 cmp r3, #0 800fb64: d101 bne.n 800fb6a { return HAL_ERROR; 800fb66: 2301 movs r3, #1 800fb68: e059 b.n 800fc1e assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); #if defined (DMA2) /* calculation of the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 800fb6a: 687b ldr r3, [r7, #4] 800fb6c: 681b ldr r3, [r3, #0] 800fb6e: 461a mov r2, r3 800fb70: 4b2d ldr r3, [pc, #180] @ (800fc28 ) 800fb72: 429a cmp r2, r3 800fb74: d80f bhi.n 800fb96 { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 800fb76: 687b ldr r3, [r7, #4] 800fb78: 681b ldr r3, [r3, #0] 800fb7a: 461a mov r2, r3 800fb7c: 4b2b ldr r3, [pc, #172] @ (800fc2c ) 800fb7e: 4413 add r3, r2 800fb80: 4a2b ldr r2, [pc, #172] @ (800fc30 ) 800fb82: fba2 2303 umull r2, r3, r2, r3 800fb86: 091b lsrs r3, r3, #4 800fb88: 009a lsls r2, r3, #2 800fb8a: 687b ldr r3, [r7, #4] 800fb8c: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA1; 800fb8e: 687b ldr r3, [r7, #4] 800fb90: 4a28 ldr r2, [pc, #160] @ (800fc34 ) 800fb92: 63da str r2, [r3, #60] @ 0x3c 800fb94: e00e b.n 800fbb4 } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; 800fb96: 687b ldr r3, [r7, #4] 800fb98: 681b ldr r3, [r3, #0] 800fb9a: 461a mov r2, r3 800fb9c: 4b26 ldr r3, [pc, #152] @ (800fc38 ) 800fb9e: 4413 add r3, r2 800fba0: 4a23 ldr r2, [pc, #140] @ (800fc30 ) 800fba2: fba2 2303 umull r2, r3, r2, r3 800fba6: 091b lsrs r3, r3, #4 800fba8: 009a lsls r2, r3, #2 800fbaa: 687b ldr r3, [r7, #4] 800fbac: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA2; 800fbae: 687b ldr r3, [r7, #4] 800fbb0: 4a22 ldr r2, [pc, #136] @ (800fc3c ) 800fbb2: 63da str r2, [r3, #60] @ 0x3c hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; #endif /* DMA2 */ /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 800fbb4: 687b ldr r3, [r7, #4] 800fbb6: 2202 movs r2, #2 800fbb8: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Get the CR register value */ tmp = hdma->Instance->CCR; 800fbbc: 687b ldr r3, [r7, #4] 800fbbe: 681b ldr r3, [r3, #0] 800fbc0: 681b ldr r3, [r3, #0] 800fbc2: 60fb str r3, [r7, #12] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 800fbc4: 68fb ldr r3, [r7, #12] 800fbc6: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 800fbca: f023 0330 bic.w r3, r3, #48 @ 0x30 800fbce: 60fb str r3, [r7, #12] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 800fbd0: 687b ldr r3, [r7, #4] 800fbd2: 685a ldr r2, [r3, #4] hdma->Init.PeriphInc | hdma->Init.MemInc | 800fbd4: 687b ldr r3, [r7, #4] 800fbd6: 689b ldr r3, [r3, #8] tmp |= hdma->Init.Direction | 800fbd8: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 800fbda: 687b ldr r3, [r7, #4] 800fbdc: 68db ldr r3, [r3, #12] 800fbde: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800fbe0: 687b ldr r3, [r7, #4] 800fbe2: 691b ldr r3, [r3, #16] hdma->Init.PeriphInc | hdma->Init.MemInc | 800fbe4: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800fbe6: 687b ldr r3, [r7, #4] 800fbe8: 695b ldr r3, [r3, #20] 800fbea: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800fbec: 687b ldr r3, [r7, #4] 800fbee: 699b ldr r3, [r3, #24] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800fbf0: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800fbf2: 687b ldr r3, [r7, #4] 800fbf4: 69db ldr r3, [r3, #28] 800fbf6: 4313 orrs r3, r2 tmp |= hdma->Init.Direction | 800fbf8: 68fa ldr r2, [r7, #12] 800fbfa: 4313 orrs r3, r2 800fbfc: 60fb str r3, [r7, #12] /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; 800fbfe: 687b ldr r3, [r7, #4] 800fc00: 681b ldr r3, [r3, #0] 800fc02: 68fa ldr r2, [r7, #12] 800fc04: 601a str r2, [r3, #0] /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800fc06: 687b ldr r3, [r7, #4] 800fc08: 2200 movs r2, #0 800fc0a: 639a str r2, [r3, #56] @ 0x38 /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 800fc0c: 687b ldr r3, [r7, #4] 800fc0e: 2201 movs r2, #1 800fc10: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; 800fc14: 687b ldr r3, [r7, #4] 800fc16: 2200 movs r2, #0 800fc18: f883 2020 strb.w r2, [r3, #32] return HAL_OK; 800fc1c: 2300 movs r3, #0 } 800fc1e: 4618 mov r0, r3 800fc20: 3714 adds r7, #20 800fc22: 46bd mov sp, r7 800fc24: bc80 pop {r7} 800fc26: 4770 bx lr 800fc28: 40020407 .word 0x40020407 800fc2c: bffdfff8 .word 0xbffdfff8 800fc30: cccccccd .word 0xcccccccd 800fc34: 40020000 .word 0x40020000 800fc38: bffdfbf8 .word 0xbffdfbf8 800fc3c: 40020400 .word 0x40020400 0800fc40 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 800fc40: b580 push {r7, lr} 800fc42: b086 sub sp, #24 800fc44: af00 add r7, sp, #0 800fc46: 60f8 str r0, [r7, #12] 800fc48: 60b9 str r1, [r7, #8] 800fc4a: 607a str r2, [r7, #4] 800fc4c: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800fc4e: 2300 movs r3, #0 800fc50: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 800fc52: 68fb ldr r3, [r7, #12] 800fc54: f893 3020 ldrb.w r3, [r3, #32] 800fc58: 2b01 cmp r3, #1 800fc5a: d101 bne.n 800fc60 800fc5c: 2302 movs r3, #2 800fc5e: e04b b.n 800fcf8 800fc60: 68fb ldr r3, [r7, #12] 800fc62: 2201 movs r2, #1 800fc64: f883 2020 strb.w r2, [r3, #32] if(HAL_DMA_STATE_READY == hdma->State) 800fc68: 68fb ldr r3, [r7, #12] 800fc6a: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800fc6e: b2db uxtb r3, r3 800fc70: 2b01 cmp r3, #1 800fc72: d13a bne.n 800fcea { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 800fc74: 68fb ldr r3, [r7, #12] 800fc76: 2202 movs r2, #2 800fc78: f883 2021 strb.w r2, [r3, #33] @ 0x21 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800fc7c: 68fb ldr r3, [r7, #12] 800fc7e: 2200 movs r2, #0 800fc80: 639a str r2, [r3, #56] @ 0x38 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 800fc82: 68fb ldr r3, [r7, #12] 800fc84: 681b ldr r3, [r3, #0] 800fc86: 681a ldr r2, [r3, #0] 800fc88: 68fb ldr r3, [r7, #12] 800fc8a: 681b ldr r3, [r3, #0] 800fc8c: f022 0201 bic.w r2, r2, #1 800fc90: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 800fc92: 683b ldr r3, [r7, #0] 800fc94: 687a ldr r2, [r7, #4] 800fc96: 68b9 ldr r1, [r7, #8] 800fc98: 68f8 ldr r0, [r7, #12] 800fc9a: f000 fbb1 bl 8010400 /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if(NULL != hdma->XferHalfCpltCallback) 800fc9e: 68fb ldr r3, [r7, #12] 800fca0: 6adb ldr r3, [r3, #44] @ 0x2c 800fca2: 2b00 cmp r3, #0 800fca4: d008 beq.n 800fcb8 { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800fca6: 68fb ldr r3, [r7, #12] 800fca8: 681b ldr r3, [r3, #0] 800fcaa: 681a ldr r2, [r3, #0] 800fcac: 68fb ldr r3, [r7, #12] 800fcae: 681b ldr r3, [r3, #0] 800fcb0: f042 020e orr.w r2, r2, #14 800fcb4: 601a str r2, [r3, #0] 800fcb6: e00f b.n 800fcd8 } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800fcb8: 68fb ldr r3, [r7, #12] 800fcba: 681b ldr r3, [r3, #0] 800fcbc: 681a ldr r2, [r3, #0] 800fcbe: 68fb ldr r3, [r7, #12] 800fcc0: 681b ldr r3, [r3, #0] 800fcc2: f022 0204 bic.w r2, r2, #4 800fcc6: 601a str r2, [r3, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 800fcc8: 68fb ldr r3, [r7, #12] 800fcca: 681b ldr r3, [r3, #0] 800fccc: 681a ldr r2, [r3, #0] 800fcce: 68fb ldr r3, [r7, #12] 800fcd0: 681b ldr r3, [r3, #0] 800fcd2: f042 020a orr.w r2, r2, #10 800fcd6: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 800fcd8: 68fb ldr r3, [r7, #12] 800fcda: 681b ldr r3, [r3, #0] 800fcdc: 681a ldr r2, [r3, #0] 800fcde: 68fb ldr r3, [r7, #12] 800fce0: 681b ldr r3, [r3, #0] 800fce2: f042 0201 orr.w r2, r2, #1 800fce6: 601a str r2, [r3, #0] 800fce8: e005 b.n 800fcf6 } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); 800fcea: 68fb ldr r3, [r7, #12] 800fcec: 2200 movs r2, #0 800fcee: f883 2020 strb.w r2, [r3, #32] /* Remain BUSY */ status = HAL_BUSY; 800fcf2: 2302 movs r3, #2 800fcf4: 75fb strb r3, [r7, #23] } return status; 800fcf6: 7dfb ldrb r3, [r7, #23] } 800fcf8: 4618 mov r0, r3 800fcfa: 3718 adds r7, #24 800fcfc: 46bd mov sp, r7 800fcfe: bd80 pop {r7, pc} 0800fd00 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 800fd00: b480 push {r7} 800fd02: b085 sub sp, #20 800fd04: af00 add r7, sp, #0 800fd06: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800fd08: 2300 movs r3, #0 800fd0a: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 800fd0c: 687b ldr r3, [r7, #4] 800fd0e: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800fd12: b2db uxtb r3, r3 800fd14: 2b02 cmp r3, #2 800fd16: d008 beq.n 800fd2a { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800fd18: 687b ldr r3, [r7, #4] 800fd1a: 2204 movs r2, #4 800fd1c: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800fd1e: 687b ldr r3, [r7, #4] 800fd20: 2200 movs r2, #0 800fd22: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800fd26: 2301 movs r3, #1 800fd28: e020 b.n 800fd6c } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800fd2a: 687b ldr r3, [r7, #4] 800fd2c: 681b ldr r3, [r3, #0] 800fd2e: 681a ldr r2, [r3, #0] 800fd30: 687b ldr r3, [r7, #4] 800fd32: 681b ldr r3, [r3, #0] 800fd34: f022 020e bic.w r2, r2, #14 800fd38: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800fd3a: 687b ldr r3, [r7, #4] 800fd3c: 681b ldr r3, [r3, #0] 800fd3e: 681a ldr r2, [r3, #0] 800fd40: 687b ldr r3, [r7, #4] 800fd42: 681b ldr r3, [r3, #0] 800fd44: f022 0201 bic.w r2, r2, #1 800fd48: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 800fd4a: 687b ldr r3, [r7, #4] 800fd4c: 6c1a ldr r2, [r3, #64] @ 0x40 800fd4e: 687b ldr r3, [r7, #4] 800fd50: 6bdb ldr r3, [r3, #60] @ 0x3c 800fd52: 2101 movs r1, #1 800fd54: fa01 f202 lsl.w r2, r1, r2 800fd58: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800fd5a: 687b ldr r3, [r7, #4] 800fd5c: 2201 movs r2, #1 800fd5e: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800fd62: 687b ldr r3, [r7, #4] 800fd64: 2200 movs r2, #0 800fd66: f883 2020 strb.w r2, [r3, #32] return status; 800fd6a: 7bfb ldrb r3, [r7, #15] } 800fd6c: 4618 mov r0, r3 800fd6e: 3714 adds r7, #20 800fd70: 46bd mov sp, r7 800fd72: bc80 pop {r7} 800fd74: 4770 bx lr ... 0800fd78 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 800fd78: b580 push {r7, lr} 800fd7a: b084 sub sp, #16 800fd7c: af00 add r7, sp, #0 800fd7e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800fd80: 2300 movs r3, #0 800fd82: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 800fd84: 687b ldr r3, [r7, #4] 800fd86: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800fd8a: b2db uxtb r3, r3 800fd8c: 2b02 cmp r3, #2 800fd8e: d005 beq.n 800fd9c { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800fd90: 687b ldr r3, [r7, #4] 800fd92: 2204 movs r2, #4 800fd94: 639a str r2, [r3, #56] @ 0x38 status = HAL_ERROR; 800fd96: 2301 movs r3, #1 800fd98: 73fb strb r3, [r7, #15] 800fd9a: e0d6 b.n 800ff4a } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800fd9c: 687b ldr r3, [r7, #4] 800fd9e: 681b ldr r3, [r3, #0] 800fda0: 681a ldr r2, [r3, #0] 800fda2: 687b ldr r3, [r7, #4] 800fda4: 681b ldr r3, [r3, #0] 800fda6: f022 020e bic.w r2, r2, #14 800fdaa: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800fdac: 687b ldr r3, [r7, #4] 800fdae: 681b ldr r3, [r3, #0] 800fdb0: 681a ldr r2, [r3, #0] 800fdb2: 687b ldr r3, [r7, #4] 800fdb4: 681b ldr r3, [r3, #0] 800fdb6: f022 0201 bic.w r2, r2, #1 800fdba: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 800fdbc: 687b ldr r3, [r7, #4] 800fdbe: 681b ldr r3, [r3, #0] 800fdc0: 461a mov r2, r3 800fdc2: 4b64 ldr r3, [pc, #400] @ (800ff54 ) 800fdc4: 429a cmp r2, r3 800fdc6: d958 bls.n 800fe7a 800fdc8: 687b ldr r3, [r7, #4] 800fdca: 681b ldr r3, [r3, #0] 800fdcc: 4a62 ldr r2, [pc, #392] @ (800ff58 ) 800fdce: 4293 cmp r3, r2 800fdd0: d04f beq.n 800fe72 800fdd2: 687b ldr r3, [r7, #4] 800fdd4: 681b ldr r3, [r3, #0] 800fdd6: 4a61 ldr r2, [pc, #388] @ (800ff5c ) 800fdd8: 4293 cmp r3, r2 800fdda: d048 beq.n 800fe6e 800fddc: 687b ldr r3, [r7, #4] 800fdde: 681b ldr r3, [r3, #0] 800fde0: 4a5f ldr r2, [pc, #380] @ (800ff60 ) 800fde2: 4293 cmp r3, r2 800fde4: d040 beq.n 800fe68 800fde6: 687b ldr r3, [r7, #4] 800fde8: 681b ldr r3, [r3, #0] 800fdea: 4a5e ldr r2, [pc, #376] @ (800ff64 ) 800fdec: 4293 cmp r3, r2 800fdee: d038 beq.n 800fe62 800fdf0: 687b ldr r3, [r7, #4] 800fdf2: 681b ldr r3, [r3, #0] 800fdf4: 4a5c ldr r2, [pc, #368] @ (800ff68 ) 800fdf6: 4293 cmp r3, r2 800fdf8: d030 beq.n 800fe5c 800fdfa: 687b ldr r3, [r7, #4] 800fdfc: 681b ldr r3, [r3, #0] 800fdfe: 4a5b ldr r2, [pc, #364] @ (800ff6c ) 800fe00: 4293 cmp r3, r2 800fe02: d028 beq.n 800fe56 800fe04: 687b ldr r3, [r7, #4] 800fe06: 681b ldr r3, [r3, #0] 800fe08: 4a52 ldr r2, [pc, #328] @ (800ff54 ) 800fe0a: 4293 cmp r3, r2 800fe0c: d020 beq.n 800fe50 800fe0e: 687b ldr r3, [r7, #4] 800fe10: 681b ldr r3, [r3, #0] 800fe12: 4a57 ldr r2, [pc, #348] @ (800ff70 ) 800fe14: 4293 cmp r3, r2 800fe16: d019 beq.n 800fe4c 800fe18: 687b ldr r3, [r7, #4] 800fe1a: 681b ldr r3, [r3, #0] 800fe1c: 4a55 ldr r2, [pc, #340] @ (800ff74 ) 800fe1e: 4293 cmp r3, r2 800fe20: d012 beq.n 800fe48 800fe22: 687b ldr r3, [r7, #4] 800fe24: 681b ldr r3, [r3, #0] 800fe26: 4a54 ldr r2, [pc, #336] @ (800ff78 ) 800fe28: 4293 cmp r3, r2 800fe2a: d00a beq.n 800fe42 800fe2c: 687b ldr r3, [r7, #4] 800fe2e: 681b ldr r3, [r3, #0] 800fe30: 4a52 ldr r2, [pc, #328] @ (800ff7c ) 800fe32: 4293 cmp r3, r2 800fe34: d102 bne.n 800fe3c 800fe36: f44f 5380 mov.w r3, #4096 @ 0x1000 800fe3a: e01b b.n 800fe74 800fe3c: f44f 3380 mov.w r3, #65536 @ 0x10000 800fe40: e018 b.n 800fe74 800fe42: f44f 7380 mov.w r3, #256 @ 0x100 800fe46: e015 b.n 800fe74 800fe48: 2310 movs r3, #16 800fe4a: e013 b.n 800fe74 800fe4c: 2301 movs r3, #1 800fe4e: e011 b.n 800fe74 800fe50: f04f 7380 mov.w r3, #16777216 @ 0x1000000 800fe54: e00e b.n 800fe74 800fe56: f44f 1380 mov.w r3, #1048576 @ 0x100000 800fe5a: e00b b.n 800fe74 800fe5c: f44f 3380 mov.w r3, #65536 @ 0x10000 800fe60: e008 b.n 800fe74 800fe62: f44f 5380 mov.w r3, #4096 @ 0x1000 800fe66: e005 b.n 800fe74 800fe68: f44f 7380 mov.w r3, #256 @ 0x100 800fe6c: e002 b.n 800fe74 800fe6e: 2310 movs r3, #16 800fe70: e000 b.n 800fe74 800fe72: 2301 movs r3, #1 800fe74: 4a42 ldr r2, [pc, #264] @ (800ff80 ) 800fe76: 6053 str r3, [r2, #4] 800fe78: e057 b.n 800ff2a 800fe7a: 687b ldr r3, [r7, #4] 800fe7c: 681b ldr r3, [r3, #0] 800fe7e: 4a36 ldr r2, [pc, #216] @ (800ff58 ) 800fe80: 4293 cmp r3, r2 800fe82: d04f beq.n 800ff24 800fe84: 687b ldr r3, [r7, #4] 800fe86: 681b ldr r3, [r3, #0] 800fe88: 4a34 ldr r2, [pc, #208] @ (800ff5c ) 800fe8a: 4293 cmp r3, r2 800fe8c: d048 beq.n 800ff20 800fe8e: 687b ldr r3, [r7, #4] 800fe90: 681b ldr r3, [r3, #0] 800fe92: 4a33 ldr r2, [pc, #204] @ (800ff60 ) 800fe94: 4293 cmp r3, r2 800fe96: d040 beq.n 800ff1a 800fe98: 687b ldr r3, [r7, #4] 800fe9a: 681b ldr r3, [r3, #0] 800fe9c: 4a31 ldr r2, [pc, #196] @ (800ff64 ) 800fe9e: 4293 cmp r3, r2 800fea0: d038 beq.n 800ff14 800fea2: 687b ldr r3, [r7, #4] 800fea4: 681b ldr r3, [r3, #0] 800fea6: 4a30 ldr r2, [pc, #192] @ (800ff68 ) 800fea8: 4293 cmp r3, r2 800feaa: d030 beq.n 800ff0e 800feac: 687b ldr r3, [r7, #4] 800feae: 681b ldr r3, [r3, #0] 800feb0: 4a2e ldr r2, [pc, #184] @ (800ff6c ) 800feb2: 4293 cmp r3, r2 800feb4: d028 beq.n 800ff08 800feb6: 687b ldr r3, [r7, #4] 800feb8: 681b ldr r3, [r3, #0] 800feba: 4a26 ldr r2, [pc, #152] @ (800ff54 ) 800febc: 4293 cmp r3, r2 800febe: d020 beq.n 800ff02 800fec0: 687b ldr r3, [r7, #4] 800fec2: 681b ldr r3, [r3, #0] 800fec4: 4a2a ldr r2, [pc, #168] @ (800ff70 ) 800fec6: 4293 cmp r3, r2 800fec8: d019 beq.n 800fefe 800feca: 687b ldr r3, [r7, #4] 800fecc: 681b ldr r3, [r3, #0] 800fece: 4a29 ldr r2, [pc, #164] @ (800ff74 ) 800fed0: 4293 cmp r3, r2 800fed2: d012 beq.n 800fefa 800fed4: 687b ldr r3, [r7, #4] 800fed6: 681b ldr r3, [r3, #0] 800fed8: 4a27 ldr r2, [pc, #156] @ (800ff78 ) 800feda: 4293 cmp r3, r2 800fedc: d00a beq.n 800fef4 800fede: 687b ldr r3, [r7, #4] 800fee0: 681b ldr r3, [r3, #0] 800fee2: 4a26 ldr r2, [pc, #152] @ (800ff7c ) 800fee4: 4293 cmp r3, r2 800fee6: d102 bne.n 800feee 800fee8: f44f 5380 mov.w r3, #4096 @ 0x1000 800feec: e01b b.n 800ff26 800feee: f44f 3380 mov.w r3, #65536 @ 0x10000 800fef2: e018 b.n 800ff26 800fef4: f44f 7380 mov.w r3, #256 @ 0x100 800fef8: e015 b.n 800ff26 800fefa: 2310 movs r3, #16 800fefc: e013 b.n 800ff26 800fefe: 2301 movs r3, #1 800ff00: e011 b.n 800ff26 800ff02: f04f 7380 mov.w r3, #16777216 @ 0x1000000 800ff06: e00e b.n 800ff26 800ff08: f44f 1380 mov.w r3, #1048576 @ 0x100000 800ff0c: e00b b.n 800ff26 800ff0e: f44f 3380 mov.w r3, #65536 @ 0x10000 800ff12: e008 b.n 800ff26 800ff14: f44f 5380 mov.w r3, #4096 @ 0x1000 800ff18: e005 b.n 800ff26 800ff1a: f44f 7380 mov.w r3, #256 @ 0x100 800ff1e: e002 b.n 800ff26 800ff20: 2310 movs r3, #16 800ff22: e000 b.n 800ff26 800ff24: 2301 movs r3, #1 800ff26: 4a17 ldr r2, [pc, #92] @ (800ff84 ) 800ff28: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800ff2a: 687b ldr r3, [r7, #4] 800ff2c: 2201 movs r2, #1 800ff2e: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800ff32: 687b ldr r3, [r7, #4] 800ff34: 2200 movs r2, #0 800ff36: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 800ff3a: 687b ldr r3, [r7, #4] 800ff3c: 6b5b ldr r3, [r3, #52] @ 0x34 800ff3e: 2b00 cmp r3, #0 800ff40: d003 beq.n 800ff4a { hdma->XferAbortCallback(hdma); 800ff42: 687b ldr r3, [r7, #4] 800ff44: 6b5b ldr r3, [r3, #52] @ 0x34 800ff46: 6878 ldr r0, [r7, #4] 800ff48: 4798 blx r3 } } return status; 800ff4a: 7bfb ldrb r3, [r7, #15] } 800ff4c: 4618 mov r0, r3 800ff4e: 3710 adds r7, #16 800ff50: 46bd mov sp, r7 800ff52: bd80 pop {r7, pc} 800ff54: 40020080 .word 0x40020080 800ff58: 40020008 .word 0x40020008 800ff5c: 4002001c .word 0x4002001c 800ff60: 40020030 .word 0x40020030 800ff64: 40020044 .word 0x40020044 800ff68: 40020058 .word 0x40020058 800ff6c: 4002006c .word 0x4002006c 800ff70: 40020408 .word 0x40020408 800ff74: 4002041c .word 0x4002041c 800ff78: 40020430 .word 0x40020430 800ff7c: 40020444 .word 0x40020444 800ff80: 40020400 .word 0x40020400 800ff84: 40020000 .word 0x40020000 0800ff88 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 800ff88: b580 push {r7, lr} 800ff8a: b084 sub sp, #16 800ff8c: af00 add r7, sp, #0 800ff8e: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; 800ff90: 687b ldr r3, [r7, #4] 800ff92: 6bdb ldr r3, [r3, #60] @ 0x3c 800ff94: 681b ldr r3, [r3, #0] 800ff96: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; 800ff98: 687b ldr r3, [r7, #4] 800ff9a: 681b ldr r3, [r3, #0] 800ff9c: 681b ldr r3, [r3, #0] 800ff9e: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 800ffa0: 687b ldr r3, [r7, #4] 800ffa2: 6c1b ldr r3, [r3, #64] @ 0x40 800ffa4: 2204 movs r2, #4 800ffa6: 409a lsls r2, r3 800ffa8: 68fb ldr r3, [r7, #12] 800ffaa: 4013 ands r3, r2 800ffac: 2b00 cmp r3, #0 800ffae: f000 80f1 beq.w 8010194 800ffb2: 68bb ldr r3, [r7, #8] 800ffb4: f003 0304 and.w r3, r3, #4 800ffb8: 2b00 cmp r3, #0 800ffba: f000 80eb beq.w 8010194 { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 800ffbe: 687b ldr r3, [r7, #4] 800ffc0: 681b ldr r3, [r3, #0] 800ffc2: 681b ldr r3, [r3, #0] 800ffc4: f003 0320 and.w r3, r3, #32 800ffc8: 2b00 cmp r3, #0 800ffca: d107 bne.n 800ffdc { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800ffcc: 687b ldr r3, [r7, #4] 800ffce: 681b ldr r3, [r3, #0] 800ffd0: 681a ldr r2, [r3, #0] 800ffd2: 687b ldr r3, [r7, #4] 800ffd4: 681b ldr r3, [r3, #0] 800ffd6: f022 0204 bic.w r2, r2, #4 800ffda: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); 800ffdc: 687b ldr r3, [r7, #4] 800ffde: 681b ldr r3, [r3, #0] 800ffe0: 461a mov r2, r3 800ffe2: 4b5f ldr r3, [pc, #380] @ (8010160 ) 800ffe4: 429a cmp r2, r3 800ffe6: d958 bls.n 801009a 800ffe8: 687b ldr r3, [r7, #4] 800ffea: 681b ldr r3, [r3, #0] 800ffec: 4a5d ldr r2, [pc, #372] @ (8010164 ) 800ffee: 4293 cmp r3, r2 800fff0: d04f beq.n 8010092 800fff2: 687b ldr r3, [r7, #4] 800fff4: 681b ldr r3, [r3, #0] 800fff6: 4a5c ldr r2, [pc, #368] @ (8010168 ) 800fff8: 4293 cmp r3, r2 800fffa: d048 beq.n 801008e 800fffc: 687b ldr r3, [r7, #4] 800fffe: 681b ldr r3, [r3, #0] 8010000: 4a5a ldr r2, [pc, #360] @ (801016c ) 8010002: 4293 cmp r3, r2 8010004: d040 beq.n 8010088 8010006: 687b ldr r3, [r7, #4] 8010008: 681b ldr r3, [r3, #0] 801000a: 4a59 ldr r2, [pc, #356] @ (8010170 ) 801000c: 4293 cmp r3, r2 801000e: d038 beq.n 8010082 8010010: 687b ldr r3, [r7, #4] 8010012: 681b ldr r3, [r3, #0] 8010014: 4a57 ldr r2, [pc, #348] @ (8010174 ) 8010016: 4293 cmp r3, r2 8010018: d030 beq.n 801007c 801001a: 687b ldr r3, [r7, #4] 801001c: 681b ldr r3, [r3, #0] 801001e: 4a56 ldr r2, [pc, #344] @ (8010178 ) 8010020: 4293 cmp r3, r2 8010022: d028 beq.n 8010076 8010024: 687b ldr r3, [r7, #4] 8010026: 681b ldr r3, [r3, #0] 8010028: 4a4d ldr r2, [pc, #308] @ (8010160 ) 801002a: 4293 cmp r3, r2 801002c: d020 beq.n 8010070 801002e: 687b ldr r3, [r7, #4] 8010030: 681b ldr r3, [r3, #0] 8010032: 4a52 ldr r2, [pc, #328] @ (801017c ) 8010034: 4293 cmp r3, r2 8010036: d019 beq.n 801006c 8010038: 687b ldr r3, [r7, #4] 801003a: 681b ldr r3, [r3, #0] 801003c: 4a50 ldr r2, [pc, #320] @ (8010180 ) 801003e: 4293 cmp r3, r2 8010040: d012 beq.n 8010068 8010042: 687b ldr r3, [r7, #4] 8010044: 681b ldr r3, [r3, #0] 8010046: 4a4f ldr r2, [pc, #316] @ (8010184 ) 8010048: 4293 cmp r3, r2 801004a: d00a beq.n 8010062 801004c: 687b ldr r3, [r7, #4] 801004e: 681b ldr r3, [r3, #0] 8010050: 4a4d ldr r2, [pc, #308] @ (8010188 ) 8010052: 4293 cmp r3, r2 8010054: d102 bne.n 801005c 8010056: f44f 4380 mov.w r3, #16384 @ 0x4000 801005a: e01b b.n 8010094 801005c: f44f 2380 mov.w r3, #262144 @ 0x40000 8010060: e018 b.n 8010094 8010062: f44f 6380 mov.w r3, #1024 @ 0x400 8010066: e015 b.n 8010094 8010068: 2340 movs r3, #64 @ 0x40 801006a: e013 b.n 8010094 801006c: 2304 movs r3, #4 801006e: e011 b.n 8010094 8010070: f04f 6380 mov.w r3, #67108864 @ 0x4000000 8010074: e00e b.n 8010094 8010076: f44f 0380 mov.w r3, #4194304 @ 0x400000 801007a: e00b b.n 8010094 801007c: f44f 2380 mov.w r3, #262144 @ 0x40000 8010080: e008 b.n 8010094 8010082: f44f 4380 mov.w r3, #16384 @ 0x4000 8010086: e005 b.n 8010094 8010088: f44f 6380 mov.w r3, #1024 @ 0x400 801008c: e002 b.n 8010094 801008e: 2340 movs r3, #64 @ 0x40 8010090: e000 b.n 8010094 8010092: 2304 movs r3, #4 8010094: 4a3d ldr r2, [pc, #244] @ (801018c ) 8010096: 6053 str r3, [r2, #4] 8010098: e057 b.n 801014a 801009a: 687b ldr r3, [r7, #4] 801009c: 681b ldr r3, [r3, #0] 801009e: 4a31 ldr r2, [pc, #196] @ (8010164 ) 80100a0: 4293 cmp r3, r2 80100a2: d04f beq.n 8010144 80100a4: 687b ldr r3, [r7, #4] 80100a6: 681b ldr r3, [r3, #0] 80100a8: 4a2f ldr r2, [pc, #188] @ (8010168 ) 80100aa: 4293 cmp r3, r2 80100ac: d048 beq.n 8010140 80100ae: 687b ldr r3, [r7, #4] 80100b0: 681b ldr r3, [r3, #0] 80100b2: 4a2e ldr r2, [pc, #184] @ (801016c ) 80100b4: 4293 cmp r3, r2 80100b6: d040 beq.n 801013a 80100b8: 687b ldr r3, [r7, #4] 80100ba: 681b ldr r3, [r3, #0] 80100bc: 4a2c ldr r2, [pc, #176] @ (8010170 ) 80100be: 4293 cmp r3, r2 80100c0: d038 beq.n 8010134 80100c2: 687b ldr r3, [r7, #4] 80100c4: 681b ldr r3, [r3, #0] 80100c6: 4a2b ldr r2, [pc, #172] @ (8010174 ) 80100c8: 4293 cmp r3, r2 80100ca: d030 beq.n 801012e 80100cc: 687b ldr r3, [r7, #4] 80100ce: 681b ldr r3, [r3, #0] 80100d0: 4a29 ldr r2, [pc, #164] @ (8010178 ) 80100d2: 4293 cmp r3, r2 80100d4: d028 beq.n 8010128 80100d6: 687b ldr r3, [r7, #4] 80100d8: 681b ldr r3, [r3, #0] 80100da: 4a21 ldr r2, [pc, #132] @ (8010160 ) 80100dc: 4293 cmp r3, r2 80100de: d020 beq.n 8010122 80100e0: 687b ldr r3, [r7, #4] 80100e2: 681b ldr r3, [r3, #0] 80100e4: 4a25 ldr r2, [pc, #148] @ (801017c ) 80100e6: 4293 cmp r3, r2 80100e8: d019 beq.n 801011e 80100ea: 687b ldr r3, [r7, #4] 80100ec: 681b ldr r3, [r3, #0] 80100ee: 4a24 ldr r2, [pc, #144] @ (8010180 ) 80100f0: 4293 cmp r3, r2 80100f2: d012 beq.n 801011a 80100f4: 687b ldr r3, [r7, #4] 80100f6: 681b ldr r3, [r3, #0] 80100f8: 4a22 ldr r2, [pc, #136] @ (8010184 ) 80100fa: 4293 cmp r3, r2 80100fc: d00a beq.n 8010114 80100fe: 687b ldr r3, [r7, #4] 8010100: 681b ldr r3, [r3, #0] 8010102: 4a21 ldr r2, [pc, #132] @ (8010188 ) 8010104: 4293 cmp r3, r2 8010106: d102 bne.n 801010e 8010108: f44f 4380 mov.w r3, #16384 @ 0x4000 801010c: e01b b.n 8010146 801010e: f44f 2380 mov.w r3, #262144 @ 0x40000 8010112: e018 b.n 8010146 8010114: f44f 6380 mov.w r3, #1024 @ 0x400 8010118: e015 b.n 8010146 801011a: 2340 movs r3, #64 @ 0x40 801011c: e013 b.n 8010146 801011e: 2304 movs r3, #4 8010120: e011 b.n 8010146 8010122: f04f 6380 mov.w r3, #67108864 @ 0x4000000 8010126: e00e b.n 8010146 8010128: f44f 0380 mov.w r3, #4194304 @ 0x400000 801012c: e00b b.n 8010146 801012e: f44f 2380 mov.w r3, #262144 @ 0x40000 8010132: e008 b.n 8010146 8010134: f44f 4380 mov.w r3, #16384 @ 0x4000 8010138: e005 b.n 8010146 801013a: f44f 6380 mov.w r3, #1024 @ 0x400 801013e: e002 b.n 8010146 8010140: 2340 movs r3, #64 @ 0x40 8010142: e000 b.n 8010146 8010144: 2304 movs r3, #4 8010146: 4a12 ldr r2, [pc, #72] @ (8010190 ) 8010148: 6053 str r3, [r2, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 801014a: 687b ldr r3, [r7, #4] 801014c: 6adb ldr r3, [r3, #44] @ 0x2c 801014e: 2b00 cmp r3, #0 8010150: f000 8136 beq.w 80103c0 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8010154: 687b ldr r3, [r7, #4] 8010156: 6adb ldr r3, [r3, #44] @ 0x2c 8010158: 6878 ldr r0, [r7, #4] 801015a: 4798 blx r3 if(hdma->XferHalfCpltCallback != NULL) 801015c: e130 b.n 80103c0 801015e: bf00 nop 8010160: 40020080 .word 0x40020080 8010164: 40020008 .word 0x40020008 8010168: 4002001c .word 0x4002001c 801016c: 40020030 .word 0x40020030 8010170: 40020044 .word 0x40020044 8010174: 40020058 .word 0x40020058 8010178: 4002006c .word 0x4002006c 801017c: 40020408 .word 0x40020408 8010180: 4002041c .word 0x4002041c 8010184: 40020430 .word 0x40020430 8010188: 40020444 .word 0x40020444 801018c: 40020400 .word 0x40020400 8010190: 40020000 .word 0x40020000 } } /* Transfer Complete Interrupt management ***********************************/ else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) 8010194: 687b ldr r3, [r7, #4] 8010196: 6c1b ldr r3, [r3, #64] @ 0x40 8010198: 2202 movs r2, #2 801019a: 409a lsls r2, r3 801019c: 68fb ldr r3, [r7, #12] 801019e: 4013 ands r3, r2 80101a0: 2b00 cmp r3, #0 80101a2: f000 80dd beq.w 8010360 80101a6: 68bb ldr r3, [r7, #8] 80101a8: f003 0302 and.w r3, r3, #2 80101ac: 2b00 cmp r3, #0 80101ae: f000 80d7 beq.w 8010360 { if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 80101b2: 687b ldr r3, [r7, #4] 80101b4: 681b ldr r3, [r3, #0] 80101b6: 681b ldr r3, [r3, #0] 80101b8: f003 0320 and.w r3, r3, #32 80101bc: 2b00 cmp r3, #0 80101be: d10b bne.n 80101d8 { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 80101c0: 687b ldr r3, [r7, #4] 80101c2: 681b ldr r3, [r3, #0] 80101c4: 681a ldr r2, [r3, #0] 80101c6: 687b ldr r3, [r7, #4] 80101c8: 681b ldr r3, [r3, #0] 80101ca: f022 020a bic.w r2, r2, #10 80101ce: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80101d0: 687b ldr r3, [r7, #4] 80101d2: 2201 movs r2, #1 80101d4: f883 2021 strb.w r2, [r3, #33] @ 0x21 } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); 80101d8: 687b ldr r3, [r7, #4] 80101da: 681b ldr r3, [r3, #0] 80101dc: 461a mov r2, r3 80101de: 4b7b ldr r3, [pc, #492] @ (80103cc ) 80101e0: 429a cmp r2, r3 80101e2: d958 bls.n 8010296 80101e4: 687b ldr r3, [r7, #4] 80101e6: 681b ldr r3, [r3, #0] 80101e8: 4a79 ldr r2, [pc, #484] @ (80103d0 ) 80101ea: 4293 cmp r3, r2 80101ec: d04f beq.n 801028e 80101ee: 687b ldr r3, [r7, #4] 80101f0: 681b ldr r3, [r3, #0] 80101f2: 4a78 ldr r2, [pc, #480] @ (80103d4 ) 80101f4: 4293 cmp r3, r2 80101f6: d048 beq.n 801028a 80101f8: 687b ldr r3, [r7, #4] 80101fa: 681b ldr r3, [r3, #0] 80101fc: 4a76 ldr r2, [pc, #472] @ (80103d8 ) 80101fe: 4293 cmp r3, r2 8010200: d040 beq.n 8010284 8010202: 687b ldr r3, [r7, #4] 8010204: 681b ldr r3, [r3, #0] 8010206: 4a75 ldr r2, [pc, #468] @ (80103dc ) 8010208: 4293 cmp r3, r2 801020a: d038 beq.n 801027e 801020c: 687b ldr r3, [r7, #4] 801020e: 681b ldr r3, [r3, #0] 8010210: 4a73 ldr r2, [pc, #460] @ (80103e0 ) 8010212: 4293 cmp r3, r2 8010214: d030 beq.n 8010278 8010216: 687b ldr r3, [r7, #4] 8010218: 681b ldr r3, [r3, #0] 801021a: 4a72 ldr r2, [pc, #456] @ (80103e4 ) 801021c: 4293 cmp r3, r2 801021e: d028 beq.n 8010272 8010220: 687b ldr r3, [r7, #4] 8010222: 681b ldr r3, [r3, #0] 8010224: 4a69 ldr r2, [pc, #420] @ (80103cc ) 8010226: 4293 cmp r3, r2 8010228: d020 beq.n 801026c 801022a: 687b ldr r3, [r7, #4] 801022c: 681b ldr r3, [r3, #0] 801022e: 4a6e ldr r2, [pc, #440] @ (80103e8 ) 8010230: 4293 cmp r3, r2 8010232: d019 beq.n 8010268 8010234: 687b ldr r3, [r7, #4] 8010236: 681b ldr r3, [r3, #0] 8010238: 4a6c ldr r2, [pc, #432] @ (80103ec ) 801023a: 4293 cmp r3, r2 801023c: d012 beq.n 8010264 801023e: 687b ldr r3, [r7, #4] 8010240: 681b ldr r3, [r3, #0] 8010242: 4a6b ldr r2, [pc, #428] @ (80103f0 ) 8010244: 4293 cmp r3, r2 8010246: d00a beq.n 801025e 8010248: 687b ldr r3, [r7, #4] 801024a: 681b ldr r3, [r3, #0] 801024c: 4a69 ldr r2, [pc, #420] @ (80103f4 ) 801024e: 4293 cmp r3, r2 8010250: d102 bne.n 8010258 8010252: f44f 5300 mov.w r3, #8192 @ 0x2000 8010256: e01b b.n 8010290 8010258: f44f 3300 mov.w r3, #131072 @ 0x20000 801025c: e018 b.n 8010290 801025e: f44f 7300 mov.w r3, #512 @ 0x200 8010262: e015 b.n 8010290 8010264: 2320 movs r3, #32 8010266: e013 b.n 8010290 8010268: 2302 movs r3, #2 801026a: e011 b.n 8010290 801026c: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8010270: e00e b.n 8010290 8010272: f44f 1300 mov.w r3, #2097152 @ 0x200000 8010276: e00b b.n 8010290 8010278: f44f 3300 mov.w r3, #131072 @ 0x20000 801027c: e008 b.n 8010290 801027e: f44f 5300 mov.w r3, #8192 @ 0x2000 8010282: e005 b.n 8010290 8010284: f44f 7300 mov.w r3, #512 @ 0x200 8010288: e002 b.n 8010290 801028a: 2320 movs r3, #32 801028c: e000 b.n 8010290 801028e: 2302 movs r3, #2 8010290: 4a59 ldr r2, [pc, #356] @ (80103f8 ) 8010292: 6053 str r3, [r2, #4] 8010294: e057 b.n 8010346 8010296: 687b ldr r3, [r7, #4] 8010298: 681b ldr r3, [r3, #0] 801029a: 4a4d ldr r2, [pc, #308] @ (80103d0 ) 801029c: 4293 cmp r3, r2 801029e: d04f beq.n 8010340 80102a0: 687b ldr r3, [r7, #4] 80102a2: 681b ldr r3, [r3, #0] 80102a4: 4a4b ldr r2, [pc, #300] @ (80103d4 ) 80102a6: 4293 cmp r3, r2 80102a8: d048 beq.n 801033c 80102aa: 687b ldr r3, [r7, #4] 80102ac: 681b ldr r3, [r3, #0] 80102ae: 4a4a ldr r2, [pc, #296] @ (80103d8 ) 80102b0: 4293 cmp r3, r2 80102b2: d040 beq.n 8010336 80102b4: 687b ldr r3, [r7, #4] 80102b6: 681b ldr r3, [r3, #0] 80102b8: 4a48 ldr r2, [pc, #288] @ (80103dc ) 80102ba: 4293 cmp r3, r2 80102bc: d038 beq.n 8010330 80102be: 687b ldr r3, [r7, #4] 80102c0: 681b ldr r3, [r3, #0] 80102c2: 4a47 ldr r2, [pc, #284] @ (80103e0 ) 80102c4: 4293 cmp r3, r2 80102c6: d030 beq.n 801032a 80102c8: 687b ldr r3, [r7, #4] 80102ca: 681b ldr r3, [r3, #0] 80102cc: 4a45 ldr r2, [pc, #276] @ (80103e4 ) 80102ce: 4293 cmp r3, r2 80102d0: d028 beq.n 8010324 80102d2: 687b ldr r3, [r7, #4] 80102d4: 681b ldr r3, [r3, #0] 80102d6: 4a3d ldr r2, [pc, #244] @ (80103cc ) 80102d8: 4293 cmp r3, r2 80102da: d020 beq.n 801031e 80102dc: 687b ldr r3, [r7, #4] 80102de: 681b ldr r3, [r3, #0] 80102e0: 4a41 ldr r2, [pc, #260] @ (80103e8 ) 80102e2: 4293 cmp r3, r2 80102e4: d019 beq.n 801031a 80102e6: 687b ldr r3, [r7, #4] 80102e8: 681b ldr r3, [r3, #0] 80102ea: 4a40 ldr r2, [pc, #256] @ (80103ec ) 80102ec: 4293 cmp r3, r2 80102ee: d012 beq.n 8010316 80102f0: 687b ldr r3, [r7, #4] 80102f2: 681b ldr r3, [r3, #0] 80102f4: 4a3e ldr r2, [pc, #248] @ (80103f0 ) 80102f6: 4293 cmp r3, r2 80102f8: d00a beq.n 8010310 80102fa: 687b ldr r3, [r7, #4] 80102fc: 681b ldr r3, [r3, #0] 80102fe: 4a3d ldr r2, [pc, #244] @ (80103f4 ) 8010300: 4293 cmp r3, r2 8010302: d102 bne.n 801030a 8010304: f44f 5300 mov.w r3, #8192 @ 0x2000 8010308: e01b b.n 8010342 801030a: f44f 3300 mov.w r3, #131072 @ 0x20000 801030e: e018 b.n 8010342 8010310: f44f 7300 mov.w r3, #512 @ 0x200 8010314: e015 b.n 8010342 8010316: 2320 movs r3, #32 8010318: e013 b.n 8010342 801031a: 2302 movs r3, #2 801031c: e011 b.n 8010342 801031e: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8010322: e00e b.n 8010342 8010324: f44f 1300 mov.w r3, #2097152 @ 0x200000 8010328: e00b b.n 8010342 801032a: f44f 3300 mov.w r3, #131072 @ 0x20000 801032e: e008 b.n 8010342 8010330: f44f 5300 mov.w r3, #8192 @ 0x2000 8010334: e005 b.n 8010342 8010336: f44f 7300 mov.w r3, #512 @ 0x200 801033a: e002 b.n 8010342 801033c: 2320 movs r3, #32 801033e: e000 b.n 8010342 8010340: 2302 movs r3, #2 8010342: 4a2e ldr r2, [pc, #184] @ (80103fc ) 8010344: 6053 str r3, [r2, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); 8010346: 687b ldr r3, [r7, #4] 8010348: 2200 movs r2, #0 801034a: f883 2020 strb.w r2, [r3, #32] if(hdma->XferCpltCallback != NULL) 801034e: 687b ldr r3, [r7, #4] 8010350: 6a9b ldr r3, [r3, #40] @ 0x28 8010352: 2b00 cmp r3, #0 8010354: d034 beq.n 80103c0 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8010356: 687b ldr r3, [r7, #4] 8010358: 6a9b ldr r3, [r3, #40] @ 0x28 801035a: 6878 ldr r0, [r7, #4] 801035c: 4798 blx r3 if(hdma->XferCpltCallback != NULL) 801035e: e02f b.n 80103c0 } } /* Transfer Error Interrupt management **************************************/ else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) 8010360: 687b ldr r3, [r7, #4] 8010362: 6c1b ldr r3, [r3, #64] @ 0x40 8010364: 2208 movs r2, #8 8010366: 409a lsls r2, r3 8010368: 68fb ldr r3, [r7, #12] 801036a: 4013 ands r3, r2 801036c: 2b00 cmp r3, #0 801036e: d028 beq.n 80103c2 8010370: 68bb ldr r3, [r7, #8] 8010372: f003 0308 and.w r3, r3, #8 8010376: 2b00 cmp r3, #0 8010378: d023 beq.n 80103c2 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 801037a: 687b ldr r3, [r7, #4] 801037c: 681b ldr r3, [r3, #0] 801037e: 681a ldr r2, [r3, #0] 8010380: 687b ldr r3, [r7, #4] 8010382: 681b ldr r3, [r3, #0] 8010384: f022 020e bic.w r2, r2, #14 8010388: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 801038a: 687b ldr r3, [r7, #4] 801038c: 6c1a ldr r2, [r3, #64] @ 0x40 801038e: 687b ldr r3, [r7, #4] 8010390: 6bdb ldr r3, [r3, #60] @ 0x3c 8010392: 2101 movs r1, #1 8010394: fa01 f202 lsl.w r2, r1, r2 8010398: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 801039a: 687b ldr r3, [r7, #4] 801039c: 2201 movs r2, #1 801039e: 639a str r2, [r3, #56] @ 0x38 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80103a0: 687b ldr r3, [r7, #4] 80103a2: 2201 movs r2, #1 80103a4: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80103a8: 687b ldr r3, [r7, #4] 80103aa: 2200 movs r2, #0 80103ac: f883 2020 strb.w r2, [r3, #32] if (hdma->XferErrorCallback != NULL) 80103b0: 687b ldr r3, [r7, #4] 80103b2: 6b1b ldr r3, [r3, #48] @ 0x30 80103b4: 2b00 cmp r3, #0 80103b6: d004 beq.n 80103c2 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 80103b8: 687b ldr r3, [r7, #4] 80103ba: 6b1b ldr r3, [r3, #48] @ 0x30 80103bc: 6878 ldr r0, [r7, #4] 80103be: 4798 blx r3 } } return; 80103c0: bf00 nop 80103c2: bf00 nop } 80103c4: 3710 adds r7, #16 80103c6: 46bd mov sp, r7 80103c8: bd80 pop {r7, pc} 80103ca: bf00 nop 80103cc: 40020080 .word 0x40020080 80103d0: 40020008 .word 0x40020008 80103d4: 4002001c .word 0x4002001c 80103d8: 40020030 .word 0x40020030 80103dc: 40020044 .word 0x40020044 80103e0: 40020058 .word 0x40020058 80103e4: 4002006c .word 0x4002006c 80103e8: 40020408 .word 0x40020408 80103ec: 4002041c .word 0x4002041c 80103f0: 40020430 .word 0x40020430 80103f4: 40020444 .word 0x40020444 80103f8: 40020400 .word 0x40020400 80103fc: 40020000 .word 0x40020000 08010400 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8010400: b480 push {r7} 8010402: b085 sub sp, #20 8010404: af00 add r7, sp, #0 8010406: 60f8 str r0, [r7, #12] 8010408: 60b9 str r1, [r7, #8] 801040a: 607a str r2, [r7, #4] 801040c: 603b str r3, [r7, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 801040e: 68fb ldr r3, [r7, #12] 8010410: 6c1a ldr r2, [r3, #64] @ 0x40 8010412: 68fb ldr r3, [r7, #12] 8010414: 6bdb ldr r3, [r3, #60] @ 0x3c 8010416: 2101 movs r1, #1 8010418: fa01 f202 lsl.w r2, r1, r2 801041c: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 801041e: 68fb ldr r3, [r7, #12] 8010420: 681b ldr r3, [r3, #0] 8010422: 683a ldr r2, [r7, #0] 8010424: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8010426: 68fb ldr r3, [r7, #12] 8010428: 685b ldr r3, [r3, #4] 801042a: 2b10 cmp r3, #16 801042c: d108 bne.n 8010440 { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 801042e: 68fb ldr r3, [r7, #12] 8010430: 681b ldr r3, [r3, #0] 8010432: 687a ldr r2, [r7, #4] 8010434: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; 8010436: 68fb ldr r3, [r7, #12] 8010438: 681b ldr r3, [r3, #0] 801043a: 68ba ldr r2, [r7, #8] 801043c: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } 801043e: e007 b.n 8010450 hdma->Instance->CPAR = SrcAddress; 8010440: 68fb ldr r3, [r7, #12] 8010442: 681b ldr r3, [r3, #0] 8010444: 68ba ldr r2, [r7, #8] 8010446: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; 8010448: 68fb ldr r3, [r7, #12] 801044a: 681b ldr r3, [r3, #0] 801044c: 687a ldr r2, [r7, #4] 801044e: 60da str r2, [r3, #12] } 8010450: bf00 nop 8010452: 3714 adds r7, #20 8010454: 46bd mov sp, r7 8010456: bc80 pop {r7} 8010458: 4770 bx lr ... 0801045c : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 801045c: b480 push {r7} 801045e: b08b sub sp, #44 @ 0x2c 8010460: af00 add r7, sp, #0 8010462: 6078 str r0, [r7, #4] 8010464: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8010466: 2300 movs r3, #0 8010468: 627b str r3, [r7, #36] @ 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 801046a: 2300 movs r3, #0 801046c: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 801046e: e169 b.n 8010744 { /* Get the IO position */ ioposition = (0x01uL << position); 8010470: 2201 movs r2, #1 8010472: 6a7b ldr r3, [r7, #36] @ 0x24 8010474: fa02 f303 lsl.w r3, r2, r3 8010478: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 801047a: 683b ldr r3, [r7, #0] 801047c: 681b ldr r3, [r3, #0] 801047e: 69fa ldr r2, [r7, #28] 8010480: 4013 ands r3, r2 8010482: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8010484: 69ba ldr r2, [r7, #24] 8010486: 69fb ldr r3, [r7, #28] 8010488: 429a cmp r2, r3 801048a: f040 8158 bne.w 801073e { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 801048e: 683b ldr r3, [r7, #0] 8010490: 685b ldr r3, [r3, #4] 8010492: 4a9a ldr r2, [pc, #616] @ (80106fc ) 8010494: 4293 cmp r3, r2 8010496: d05e beq.n 8010556 8010498: 4a98 ldr r2, [pc, #608] @ (80106fc ) 801049a: 4293 cmp r3, r2 801049c: d875 bhi.n 801058a 801049e: 4a98 ldr r2, [pc, #608] @ (8010700 ) 80104a0: 4293 cmp r3, r2 80104a2: d058 beq.n 8010556 80104a4: 4a96 ldr r2, [pc, #600] @ (8010700 ) 80104a6: 4293 cmp r3, r2 80104a8: d86f bhi.n 801058a 80104aa: 4a96 ldr r2, [pc, #600] @ (8010704 ) 80104ac: 4293 cmp r3, r2 80104ae: d052 beq.n 8010556 80104b0: 4a94 ldr r2, [pc, #592] @ (8010704 ) 80104b2: 4293 cmp r3, r2 80104b4: d869 bhi.n 801058a 80104b6: 4a94 ldr r2, [pc, #592] @ (8010708 ) 80104b8: 4293 cmp r3, r2 80104ba: d04c beq.n 8010556 80104bc: 4a92 ldr r2, [pc, #584] @ (8010708 ) 80104be: 4293 cmp r3, r2 80104c0: d863 bhi.n 801058a 80104c2: 4a92 ldr r2, [pc, #584] @ (801070c ) 80104c4: 4293 cmp r3, r2 80104c6: d046 beq.n 8010556 80104c8: 4a90 ldr r2, [pc, #576] @ (801070c ) 80104ca: 4293 cmp r3, r2 80104cc: d85d bhi.n 801058a 80104ce: 2b12 cmp r3, #18 80104d0: d82a bhi.n 8010528 80104d2: 2b12 cmp r3, #18 80104d4: d859 bhi.n 801058a 80104d6: a201 add r2, pc, #4 @ (adr r2, 80104dc ) 80104d8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80104dc: 08010557 .word 0x08010557 80104e0: 08010531 .word 0x08010531 80104e4: 08010543 .word 0x08010543 80104e8: 08010585 .word 0x08010585 80104ec: 0801058b .word 0x0801058b 80104f0: 0801058b .word 0x0801058b 80104f4: 0801058b .word 0x0801058b 80104f8: 0801058b .word 0x0801058b 80104fc: 0801058b .word 0x0801058b 8010500: 0801058b .word 0x0801058b 8010504: 0801058b .word 0x0801058b 8010508: 0801058b .word 0x0801058b 801050c: 0801058b .word 0x0801058b 8010510: 0801058b .word 0x0801058b 8010514: 0801058b .word 0x0801058b 8010518: 0801058b .word 0x0801058b 801051c: 0801058b .word 0x0801058b 8010520: 08010539 .word 0x08010539 8010524: 0801054d .word 0x0801054d 8010528: 4a79 ldr r2, [pc, #484] @ (8010710 ) 801052a: 4293 cmp r3, r2 801052c: d013 beq.n 8010556 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 801052e: e02c b.n 801058a config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8010530: 683b ldr r3, [r7, #0] 8010532: 68db ldr r3, [r3, #12] 8010534: 623b str r3, [r7, #32] break; 8010536: e029 b.n 801058c config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8010538: 683b ldr r3, [r7, #0] 801053a: 68db ldr r3, [r3, #12] 801053c: 3304 adds r3, #4 801053e: 623b str r3, [r7, #32] break; 8010540: e024 b.n 801058c config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8010542: 683b ldr r3, [r7, #0] 8010544: 68db ldr r3, [r3, #12] 8010546: 3308 adds r3, #8 8010548: 623b str r3, [r7, #32] break; 801054a: e01f b.n 801058c config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 801054c: 683b ldr r3, [r7, #0] 801054e: 68db ldr r3, [r3, #12] 8010550: 330c adds r3, #12 8010552: 623b str r3, [r7, #32] break; 8010554: e01a b.n 801058c if (GPIO_Init->Pull == GPIO_NOPULL) 8010556: 683b ldr r3, [r7, #0] 8010558: 689b ldr r3, [r3, #8] 801055a: 2b00 cmp r3, #0 801055c: d102 bne.n 8010564 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 801055e: 2304 movs r3, #4 8010560: 623b str r3, [r7, #32] break; 8010562: e013 b.n 801058c else if (GPIO_Init->Pull == GPIO_PULLUP) 8010564: 683b ldr r3, [r7, #0] 8010566: 689b ldr r3, [r3, #8] 8010568: 2b01 cmp r3, #1 801056a: d105 bne.n 8010578 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 801056c: 2308 movs r3, #8 801056e: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8010570: 687b ldr r3, [r7, #4] 8010572: 69fa ldr r2, [r7, #28] 8010574: 611a str r2, [r3, #16] break; 8010576: e009 b.n 801058c config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8010578: 2308 movs r3, #8 801057a: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 801057c: 687b ldr r3, [r7, #4] 801057e: 69fa ldr r2, [r7, #28] 8010580: 615a str r2, [r3, #20] break; 8010582: e003 b.n 801058c config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8010584: 2300 movs r3, #0 8010586: 623b str r3, [r7, #32] break; 8010588: e000 b.n 801058c break; 801058a: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 801058c: 69bb ldr r3, [r7, #24] 801058e: 2bff cmp r3, #255 @ 0xff 8010590: d801 bhi.n 8010596 8010592: 687b ldr r3, [r7, #4] 8010594: e001 b.n 801059a 8010596: 687b ldr r3, [r7, #4] 8010598: 3304 adds r3, #4 801059a: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 801059c: 69bb ldr r3, [r7, #24] 801059e: 2bff cmp r3, #255 @ 0xff 80105a0: d802 bhi.n 80105a8 80105a2: 6a7b ldr r3, [r7, #36] @ 0x24 80105a4: 009b lsls r3, r3, #2 80105a6: e002 b.n 80105ae 80105a8: 6a7b ldr r3, [r7, #36] @ 0x24 80105aa: 3b08 subs r3, #8 80105ac: 009b lsls r3, r3, #2 80105ae: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 80105b0: 697b ldr r3, [r7, #20] 80105b2: 681a ldr r2, [r3, #0] 80105b4: 210f movs r1, #15 80105b6: 693b ldr r3, [r7, #16] 80105b8: fa01 f303 lsl.w r3, r1, r3 80105bc: 43db mvns r3, r3 80105be: 401a ands r2, r3 80105c0: 6a39 ldr r1, [r7, #32] 80105c2: 693b ldr r3, [r7, #16] 80105c4: fa01 f303 lsl.w r3, r1, r3 80105c8: 431a orrs r2, r3 80105ca: 697b ldr r3, [r7, #20] 80105cc: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 80105ce: 683b ldr r3, [r7, #0] 80105d0: 685b ldr r3, [r3, #4] 80105d2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80105d6: 2b00 cmp r3, #0 80105d8: f000 80b1 beq.w 801073e { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 80105dc: 4b4d ldr r3, [pc, #308] @ (8010714 ) 80105de: 699b ldr r3, [r3, #24] 80105e0: 4a4c ldr r2, [pc, #304] @ (8010714 ) 80105e2: f043 0301 orr.w r3, r3, #1 80105e6: 6193 str r3, [r2, #24] 80105e8: 4b4a ldr r3, [pc, #296] @ (8010714 ) 80105ea: 699b ldr r3, [r3, #24] 80105ec: f003 0301 and.w r3, r3, #1 80105f0: 60bb str r3, [r7, #8] 80105f2: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 80105f4: 4a48 ldr r2, [pc, #288] @ (8010718 ) 80105f6: 6a7b ldr r3, [r7, #36] @ 0x24 80105f8: 089b lsrs r3, r3, #2 80105fa: 3302 adds r3, #2 80105fc: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8010600: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8010602: 6a7b ldr r3, [r7, #36] @ 0x24 8010604: f003 0303 and.w r3, r3, #3 8010608: 009b lsls r3, r3, #2 801060a: 220f movs r2, #15 801060c: fa02 f303 lsl.w r3, r2, r3 8010610: 43db mvns r3, r3 8010612: 68fa ldr r2, [r7, #12] 8010614: 4013 ands r3, r2 8010616: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8010618: 687b ldr r3, [r7, #4] 801061a: 4a40 ldr r2, [pc, #256] @ (801071c ) 801061c: 4293 cmp r3, r2 801061e: d013 beq.n 8010648 8010620: 687b ldr r3, [r7, #4] 8010622: 4a3f ldr r2, [pc, #252] @ (8010720 ) 8010624: 4293 cmp r3, r2 8010626: d00d beq.n 8010644 8010628: 687b ldr r3, [r7, #4] 801062a: 4a3e ldr r2, [pc, #248] @ (8010724 ) 801062c: 4293 cmp r3, r2 801062e: d007 beq.n 8010640 8010630: 687b ldr r3, [r7, #4] 8010632: 4a3d ldr r2, [pc, #244] @ (8010728 ) 8010634: 4293 cmp r3, r2 8010636: d101 bne.n 801063c 8010638: 2303 movs r3, #3 801063a: e006 b.n 801064a 801063c: 2304 movs r3, #4 801063e: e004 b.n 801064a 8010640: 2302 movs r3, #2 8010642: e002 b.n 801064a 8010644: 2301 movs r3, #1 8010646: e000 b.n 801064a 8010648: 2300 movs r3, #0 801064a: 6a7a ldr r2, [r7, #36] @ 0x24 801064c: f002 0203 and.w r2, r2, #3 8010650: 0092 lsls r2, r2, #2 8010652: 4093 lsls r3, r2 8010654: 68fa ldr r2, [r7, #12] 8010656: 4313 orrs r3, r2 8010658: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 801065a: 492f ldr r1, [pc, #188] @ (8010718 ) 801065c: 6a7b ldr r3, [r7, #36] @ 0x24 801065e: 089b lsrs r3, r3, #2 8010660: 3302 adds r3, #2 8010662: 68fa ldr r2, [r7, #12] 8010664: f841 2023 str.w r2, [r1, r3, lsl #2] /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8010668: 683b ldr r3, [r7, #0] 801066a: 685b ldr r3, [r3, #4] 801066c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8010670: 2b00 cmp r3, #0 8010672: d006 beq.n 8010682 { SET_BIT(EXTI->RTSR, iocurrent); 8010674: 4b2d ldr r3, [pc, #180] @ (801072c ) 8010676: 689a ldr r2, [r3, #8] 8010678: 492c ldr r1, [pc, #176] @ (801072c ) 801067a: 69bb ldr r3, [r7, #24] 801067c: 4313 orrs r3, r2 801067e: 608b str r3, [r1, #8] 8010680: e006 b.n 8010690 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8010682: 4b2a ldr r3, [pc, #168] @ (801072c ) 8010684: 689a ldr r2, [r3, #8] 8010686: 69bb ldr r3, [r7, #24] 8010688: 43db mvns r3, r3 801068a: 4928 ldr r1, [pc, #160] @ (801072c ) 801068c: 4013 ands r3, r2 801068e: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8010690: 683b ldr r3, [r7, #0] 8010692: 685b ldr r3, [r3, #4] 8010694: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8010698: 2b00 cmp r3, #0 801069a: d006 beq.n 80106aa { SET_BIT(EXTI->FTSR, iocurrent); 801069c: 4b23 ldr r3, [pc, #140] @ (801072c ) 801069e: 68da ldr r2, [r3, #12] 80106a0: 4922 ldr r1, [pc, #136] @ (801072c ) 80106a2: 69bb ldr r3, [r7, #24] 80106a4: 4313 orrs r3, r2 80106a6: 60cb str r3, [r1, #12] 80106a8: e006 b.n 80106b8 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 80106aa: 4b20 ldr r3, [pc, #128] @ (801072c ) 80106ac: 68da ldr r2, [r3, #12] 80106ae: 69bb ldr r3, [r7, #24] 80106b0: 43db mvns r3, r3 80106b2: 491e ldr r1, [pc, #120] @ (801072c ) 80106b4: 4013 ands r3, r2 80106b6: 60cb str r3, [r1, #12] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 80106b8: 683b ldr r3, [r7, #0] 80106ba: 685b ldr r3, [r3, #4] 80106bc: f403 3300 and.w r3, r3, #131072 @ 0x20000 80106c0: 2b00 cmp r3, #0 80106c2: d006 beq.n 80106d2 { SET_BIT(EXTI->EMR, iocurrent); 80106c4: 4b19 ldr r3, [pc, #100] @ (801072c ) 80106c6: 685a ldr r2, [r3, #4] 80106c8: 4918 ldr r1, [pc, #96] @ (801072c ) 80106ca: 69bb ldr r3, [r7, #24] 80106cc: 4313 orrs r3, r2 80106ce: 604b str r3, [r1, #4] 80106d0: e006 b.n 80106e0 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 80106d2: 4b16 ldr r3, [pc, #88] @ (801072c ) 80106d4: 685a ldr r2, [r3, #4] 80106d6: 69bb ldr r3, [r7, #24] 80106d8: 43db mvns r3, r3 80106da: 4914 ldr r1, [pc, #80] @ (801072c ) 80106dc: 4013 ands r3, r2 80106de: 604b str r3, [r1, #4] } /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 80106e0: 683b ldr r3, [r7, #0] 80106e2: 685b ldr r3, [r3, #4] 80106e4: f403 3380 and.w r3, r3, #65536 @ 0x10000 80106e8: 2b00 cmp r3, #0 80106ea: d021 beq.n 8010730 { SET_BIT(EXTI->IMR, iocurrent); 80106ec: 4b0f ldr r3, [pc, #60] @ (801072c ) 80106ee: 681a ldr r2, [r3, #0] 80106f0: 490e ldr r1, [pc, #56] @ (801072c ) 80106f2: 69bb ldr r3, [r7, #24] 80106f4: 4313 orrs r3, r2 80106f6: 600b str r3, [r1, #0] 80106f8: e021 b.n 801073e 80106fa: bf00 nop 80106fc: 10320000 .word 0x10320000 8010700: 10310000 .word 0x10310000 8010704: 10220000 .word 0x10220000 8010708: 10210000 .word 0x10210000 801070c: 10120000 .word 0x10120000 8010710: 10110000 .word 0x10110000 8010714: 40021000 .word 0x40021000 8010718: 40010000 .word 0x40010000 801071c: 40010800 .word 0x40010800 8010720: 40010c00 .word 0x40010c00 8010724: 40011000 .word 0x40011000 8010728: 40011400 .word 0x40011400 801072c: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8010730: 4b0b ldr r3, [pc, #44] @ (8010760 ) 8010732: 681a ldr r2, [r3, #0] 8010734: 69bb ldr r3, [r7, #24] 8010736: 43db mvns r3, r3 8010738: 4909 ldr r1, [pc, #36] @ (8010760 ) 801073a: 4013 ands r3, r2 801073c: 600b str r3, [r1, #0] } } } position++; 801073e: 6a7b ldr r3, [r7, #36] @ 0x24 8010740: 3301 adds r3, #1 8010742: 627b str r3, [r7, #36] @ 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8010744: 683b ldr r3, [r7, #0] 8010746: 681a ldr r2, [r3, #0] 8010748: 6a7b ldr r3, [r7, #36] @ 0x24 801074a: fa22 f303 lsr.w r3, r2, r3 801074e: 2b00 cmp r3, #0 8010750: f47f ae8e bne.w 8010470 } } 8010754: bf00 nop 8010756: bf00 nop 8010758: 372c adds r7, #44 @ 0x2c 801075a: 46bd mov sp, r7 801075c: bc80 pop {r7} 801075e: 4770 bx lr 8010760: 40010400 .word 0x40010400 08010764 : * @param GPIO_Pin: specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { 8010764: b480 push {r7} 8010766: b089 sub sp, #36 @ 0x24 8010768: af00 add r7, sp, #0 801076a: 6078 str r0, [r7, #4] 801076c: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 801076e: 2300 movs r3, #0 8010770: 61fb str r3, [r7, #28] /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Configure the port pins */ while ((GPIO_Pin >> position) != 0u) 8010772: e09a b.n 80108aa { /* Get current io position */ iocurrent = (GPIO_Pin) & (1uL << position); 8010774: 2201 movs r2, #1 8010776: 69fb ldr r3, [r7, #28] 8010778: fa02 f303 lsl.w r3, r2, r3 801077c: 683a ldr r2, [r7, #0] 801077e: 4013 ands r3, r2 8010780: 61bb str r3, [r7, #24] if (iocurrent) 8010782: 69bb ldr r3, [r7, #24] 8010784: 2b00 cmp r3, #0 8010786: f000 808d beq.w 80108a4 { /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ tmp = AFIO->EXTICR[position >> 2u]; 801078a: 4a4e ldr r2, [pc, #312] @ (80108c4 ) 801078c: 69fb ldr r3, [r7, #28] 801078e: 089b lsrs r3, r3, #2 8010790: 3302 adds r3, #2 8010792: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8010796: 617b str r3, [r7, #20] tmp &= 0x0FuL << (4u * (position & 0x03u)); 8010798: 69fb ldr r3, [r7, #28] 801079a: f003 0303 and.w r3, r3, #3 801079e: 009b lsls r3, r3, #2 80107a0: 220f movs r2, #15 80107a2: fa02 f303 lsl.w r3, r2, r3 80107a6: 697a ldr r2, [r7, #20] 80107a8: 4013 ands r3, r2 80107aa: 617b str r3, [r7, #20] if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) 80107ac: 687b ldr r3, [r7, #4] 80107ae: 4a46 ldr r2, [pc, #280] @ (80108c8 ) 80107b0: 4293 cmp r3, r2 80107b2: d013 beq.n 80107dc 80107b4: 687b ldr r3, [r7, #4] 80107b6: 4a45 ldr r2, [pc, #276] @ (80108cc ) 80107b8: 4293 cmp r3, r2 80107ba: d00d beq.n 80107d8 80107bc: 687b ldr r3, [r7, #4] 80107be: 4a44 ldr r2, [pc, #272] @ (80108d0 ) 80107c0: 4293 cmp r3, r2 80107c2: d007 beq.n 80107d4 80107c4: 687b ldr r3, [r7, #4] 80107c6: 4a43 ldr r2, [pc, #268] @ (80108d4 ) 80107c8: 4293 cmp r3, r2 80107ca: d101 bne.n 80107d0 80107cc: 2303 movs r3, #3 80107ce: e006 b.n 80107de 80107d0: 2304 movs r3, #4 80107d2: e004 b.n 80107de 80107d4: 2302 movs r3, #2 80107d6: e002 b.n 80107de 80107d8: 2301 movs r3, #1 80107da: e000 b.n 80107de 80107dc: 2300 movs r3, #0 80107de: 69fa ldr r2, [r7, #28] 80107e0: f002 0203 and.w r2, r2, #3 80107e4: 0092 lsls r2, r2, #2 80107e6: 4093 lsls r3, r2 80107e8: 697a ldr r2, [r7, #20] 80107ea: 429a cmp r2, r3 80107ec: d132 bne.n 8010854 { /* Clear EXTI line configuration */ CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); 80107ee: 4b3a ldr r3, [pc, #232] @ (80108d8 ) 80107f0: 681a ldr r2, [r3, #0] 80107f2: 69bb ldr r3, [r7, #24] 80107f4: 43db mvns r3, r3 80107f6: 4938 ldr r1, [pc, #224] @ (80108d8 ) 80107f8: 4013 ands r3, r2 80107fa: 600b str r3, [r1, #0] CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); 80107fc: 4b36 ldr r3, [pc, #216] @ (80108d8 ) 80107fe: 685a ldr r2, [r3, #4] 8010800: 69bb ldr r3, [r7, #24] 8010802: 43db mvns r3, r3 8010804: 4934 ldr r1, [pc, #208] @ (80108d8 ) 8010806: 4013 ands r3, r2 8010808: 604b str r3, [r1, #4] /* Clear Rising Falling edge configuration */ CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); 801080a: 4b33 ldr r3, [pc, #204] @ (80108d8 ) 801080c: 68da ldr r2, [r3, #12] 801080e: 69bb ldr r3, [r7, #24] 8010810: 43db mvns r3, r3 8010812: 4931 ldr r1, [pc, #196] @ (80108d8 ) 8010814: 4013 ands r3, r2 8010816: 60cb str r3, [r1, #12] CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); 8010818: 4b2f ldr r3, [pc, #188] @ (80108d8 ) 801081a: 689a ldr r2, [r3, #8] 801081c: 69bb ldr r3, [r7, #24] 801081e: 43db mvns r3, r3 8010820: 492d ldr r1, [pc, #180] @ (80108d8 ) 8010822: 4013 ands r3, r2 8010824: 608b str r3, [r1, #8] tmp = 0x0FuL << (4u * (position & 0x03u)); 8010826: 69fb ldr r3, [r7, #28] 8010828: f003 0303 and.w r3, r3, #3 801082c: 009b lsls r3, r3, #2 801082e: 220f movs r2, #15 8010830: fa02 f303 lsl.w r3, r2, r3 8010834: 617b str r3, [r7, #20] CLEAR_BIT(AFIO->EXTICR[position >> 2u], tmp); 8010836: 4a23 ldr r2, [pc, #140] @ (80108c4 ) 8010838: 69fb ldr r3, [r7, #28] 801083a: 089b lsrs r3, r3, #2 801083c: 3302 adds r3, #2 801083e: f852 1023 ldr.w r1, [r2, r3, lsl #2] 8010842: 697b ldr r3, [r7, #20] 8010844: 43da mvns r2, r3 8010846: 481f ldr r0, [pc, #124] @ (80108c4 ) 8010848: 69fb ldr r3, [r7, #28] 801084a: 089b lsrs r3, r3, #2 801084c: 400a ands r2, r1 801084e: 3302 adds r3, #2 8010850: f840 2023 str.w r2, [r0, r3, lsl #2] } /*------------------------- GPIO Mode Configuration --------------------*/ /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register */ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8010854: 69bb ldr r3, [r7, #24] 8010856: 2bff cmp r3, #255 @ 0xff 8010858: d801 bhi.n 801085e 801085a: 687b ldr r3, [r7, #4] 801085c: e001 b.n 8010862 801085e: 687b ldr r3, [r7, #4] 8010860: 3304 adds r3, #4 8010862: 613b str r3, [r7, #16] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8010864: 69bb ldr r3, [r7, #24] 8010866: 2bff cmp r3, #255 @ 0xff 8010868: d802 bhi.n 8010870 801086a: 69fb ldr r3, [r7, #28] 801086c: 009b lsls r3, r3, #2 801086e: e002 b.n 8010876 8010870: 69fb ldr r3, [r7, #28] 8010872: 3b08 subs r3, #8 8010874: 009b lsls r3, r3, #2 8010876: 60fb str r3, [r7, #12] /* CRL/CRH default value is floating input(0x04) shifted to correct position */ MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), GPIO_CRL_CNF0_0 << registeroffset); 8010878: 693b ldr r3, [r7, #16] 801087a: 681a ldr r2, [r3, #0] 801087c: 210f movs r1, #15 801087e: 68fb ldr r3, [r7, #12] 8010880: fa01 f303 lsl.w r3, r1, r3 8010884: 43db mvns r3, r3 8010886: 401a ands r2, r3 8010888: 2104 movs r1, #4 801088a: 68fb ldr r3, [r7, #12] 801088c: fa01 f303 lsl.w r3, r1, r3 8010890: 431a orrs r2, r3 8010892: 693b ldr r3, [r7, #16] 8010894: 601a str r2, [r3, #0] /* ODR default value is 0 */ CLEAR_BIT(GPIOx->ODR, iocurrent); 8010896: 687b ldr r3, [r7, #4] 8010898: 68da ldr r2, [r3, #12] 801089a: 69bb ldr r3, [r7, #24] 801089c: 43db mvns r3, r3 801089e: 401a ands r2, r3 80108a0: 687b ldr r3, [r7, #4] 80108a2: 60da str r2, [r3, #12] } position++; 80108a4: 69fb ldr r3, [r7, #28] 80108a6: 3301 adds r3, #1 80108a8: 61fb str r3, [r7, #28] while ((GPIO_Pin >> position) != 0u) 80108aa: 683a ldr r2, [r7, #0] 80108ac: 69fb ldr r3, [r7, #28] 80108ae: fa22 f303 lsr.w r3, r2, r3 80108b2: 2b00 cmp r3, #0 80108b4: f47f af5e bne.w 8010774 } } 80108b8: bf00 nop 80108ba: bf00 nop 80108bc: 3724 adds r7, #36 @ 0x24 80108be: 46bd mov sp, r7 80108c0: bc80 pop {r7} 80108c2: 4770 bx lr 80108c4: 40010000 .word 0x40010000 80108c8: 40010800 .word 0x40010800 80108cc: 40010c00 .word 0x40010c00 80108d0: 40011000 .word 0x40011000 80108d4: 40011400 .word 0x40011400 80108d8: 40010400 .word 0x40010400 080108dc : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 80108dc: b480 push {r7} 80108de: b085 sub sp, #20 80108e0: af00 add r7, sp, #0 80108e2: 6078 str r0, [r7, #4] 80108e4: 460b mov r3, r1 80108e6: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 80108e8: 687b ldr r3, [r7, #4] 80108ea: 689a ldr r2, [r3, #8] 80108ec: 887b ldrh r3, [r7, #2] 80108ee: 4013 ands r3, r2 80108f0: 2b00 cmp r3, #0 80108f2: d002 beq.n 80108fa { bitstatus = GPIO_PIN_SET; 80108f4: 2301 movs r3, #1 80108f6: 73fb strb r3, [r7, #15] 80108f8: e001 b.n 80108fe } else { bitstatus = GPIO_PIN_RESET; 80108fa: 2300 movs r3, #0 80108fc: 73fb strb r3, [r7, #15] } return bitstatus; 80108fe: 7bfb ldrb r3, [r7, #15] } 8010900: 4618 mov r0, r3 8010902: 3714 adds r7, #20 8010904: 46bd mov sp, r7 8010906: bc80 pop {r7} 8010908: 4770 bx lr 0801090a : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 801090a: b480 push {r7} 801090c: b083 sub sp, #12 801090e: af00 add r7, sp, #0 8010910: 6078 str r0, [r7, #4] 8010912: 460b mov r3, r1 8010914: 807b strh r3, [r7, #2] 8010916: 4613 mov r3, r2 8010918: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 801091a: 787b ldrb r3, [r7, #1] 801091c: 2b00 cmp r3, #0 801091e: d003 beq.n 8010928 { GPIOx->BSRR = GPIO_Pin; 8010920: 887a ldrh r2, [r7, #2] 8010922: 687b ldr r3, [r7, #4] 8010924: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 8010926: e003 b.n 8010930 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 8010928: 887b ldrh r3, [r7, #2] 801092a: 041a lsls r2, r3, #16 801092c: 687b ldr r3, [r7, #4] 801092e: 611a str r2, [r3, #16] } 8010930: bf00 nop 8010932: 370c adds r7, #12 8010934: 46bd mov sp, r7 8010936: bc80 pop {r7} 8010938: 4770 bx lr ... 0801093c : * @note If the HSE divided by 128 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { 801093c: b480 push {r7} 801093e: af00 add r7, sp, #0 /* Enable access to RTC and backup registers */ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 8010940: 4b03 ldr r3, [pc, #12] @ (8010950 ) 8010942: 2201 movs r2, #1 8010944: 601a str r2, [r3, #0] } 8010946: bf00 nop 8010948: 46bd mov sp, r7 801094a: bc80 pop {r7} 801094c: 4770 bx lr 801094e: bf00 nop 8010950: 420e0020 .word 0x420e0020 08010954 : * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval HAL_StatusTypeDef */ HAL_StatusTypeDef HAL_RCC_DeInit(void) { 8010954: b580 push {r7, lr} 8010956: b082 sub sp, #8 8010958: af00 add r7, sp, #0 uint32_t tickstart; /* Get Start Tick */ tickstart = HAL_GetTick(); 801095a: f7fd fb5b bl 800e014 801095e: 6078 str r0, [r7, #4] /* Set HSION bit */ SET_BIT(RCC->CR, RCC_CR_HSION); 8010960: 4b60 ldr r3, [pc, #384] @ (8010ae4 ) 8010962: 681b ldr r3, [r3, #0] 8010964: 4a5f ldr r2, [pc, #380] @ (8010ae4 ) 8010966: f043 0301 orr.w r3, r3, #1 801096a: 6013 str r3, [r2, #0] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 801096c: e008 b.n 8010980 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 801096e: f7fd fb51 bl 800e014 8010972: 4602 mov r2, r0 8010974: 687b ldr r3, [r7, #4] 8010976: 1ad3 subs r3, r2, r3 8010978: 2b02 cmp r3, #2 801097a: d901 bls.n 8010980 { return HAL_TIMEOUT; 801097c: 2303 movs r3, #3 801097e: e0ac b.n 8010ada while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 8010980: 4b58 ldr r3, [pc, #352] @ (8010ae4 ) 8010982: 681b ldr r3, [r3, #0] 8010984: f003 0302 and.w r3, r3, #2 8010988: 2b00 cmp r3, #0 801098a: d0f0 beq.n 801096e } } /* Set HSITRIM bits to the reset value */ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos)); 801098c: 4b55 ldr r3, [pc, #340] @ (8010ae4 ) 801098e: 681b ldr r3, [r3, #0] 8010990: f023 03f8 bic.w r3, r3, #248 @ 0xf8 8010994: 4a53 ldr r2, [pc, #332] @ (8010ae4 ) 8010996: f043 0380 orr.w r3, r3, #128 @ 0x80 801099a: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 801099c: f7fd fb3a bl 800e014 80109a0: 6078 str r0, [r7, #4] /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); 80109a2: 4b50 ldr r3, [pc, #320] @ (8010ae4 ) 80109a4: 2200 movs r2, #0 80109a6: 605a str r2, [r3, #4] /* Wait till clock switch is ready */ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 80109a8: e00a b.n 80109c0 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80109aa: f7fd fb33 bl 800e014 80109ae: 4602 mov r2, r0 80109b0: 687b ldr r3, [r7, #4] 80109b2: 1ad3 subs r3, r2, r3 80109b4: f241 3288 movw r2, #5000 @ 0x1388 80109b8: 4293 cmp r3, r2 80109ba: d901 bls.n 80109c0 { return HAL_TIMEOUT; 80109bc: 2303 movs r3, #3 80109be: e08c b.n 8010ada while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 80109c0: 4b48 ldr r3, [pc, #288] @ (8010ae4 ) 80109c2: 685b ldr r3, [r3, #4] 80109c4: f003 030c and.w r3, r3, #12 80109c8: 2b00 cmp r3, #0 80109ca: d1ee bne.n 80109aa } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HSI_VALUE; 80109cc: 4b46 ldr r3, [pc, #280] @ (8010ae8 ) 80109ce: 4a47 ldr r2, [pc, #284] @ (8010aec ) 80109d0: 601a str r2, [r3, #0] /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 80109d2: 4b47 ldr r3, [pc, #284] @ (8010af0 ) 80109d4: 681b ldr r3, [r3, #0] 80109d6: 4618 mov r0, r3 80109d8: f7fd fada bl 800df90 80109dc: 4603 mov r3, r0 80109de: 2b00 cmp r3, #0 80109e0: d001 beq.n 80109e6 { return HAL_ERROR; 80109e2: 2301 movs r3, #1 80109e4: e079 b.n 8010ada } /* Get Start Tick */ tickstart = HAL_GetTick(); 80109e6: f7fd fb15 bl 800e014 80109ea: 6078 str r0, [r7, #4] /* Second step is to clear PLLON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 80109ec: 4b3d ldr r3, [pc, #244] @ (8010ae4 ) 80109ee: 681b ldr r3, [r3, #0] 80109f0: 4a3c ldr r2, [pc, #240] @ (8010ae4 ) 80109f2: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 80109f6: 6013 str r3, [r2, #0] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 80109f8: e008 b.n 8010a0c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80109fa: f7fd fb0b bl 800e014 80109fe: 4602 mov r2, r0 8010a00: 687b ldr r3, [r7, #4] 8010a02: 1ad3 subs r3, r2, r3 8010a04: 2b02 cmp r3, #2 8010a06: d901 bls.n 8010a0c { return HAL_TIMEOUT; 8010a08: 2303 movs r3, #3 8010a0a: e066 b.n 8010ada while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 8010a0c: 4b35 ldr r3, [pc, #212] @ (8010ae4 ) 8010a0e: 681b ldr r3, [r3, #0] 8010a10: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8010a14: 2b00 cmp r3, #0 8010a16: d1f0 bne.n 80109fa } } /* Ensure to reset PLLSRC and PLLMUL bits */ CLEAR_REG(RCC->CFGR); 8010a18: 4b32 ldr r3, [pc, #200] @ (8010ae4 ) 8010a1a: 2200 movs r2, #0 8010a1c: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010a1e: f7fd faf9 bl 800e014 8010a22: 6078 str r0, [r7, #4] /* Reset HSEON & CSSON bits */ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON); 8010a24: 4b2f ldr r3, [pc, #188] @ (8010ae4 ) 8010a26: 681b ldr r3, [r3, #0] 8010a28: 4a2e ldr r2, [pc, #184] @ (8010ae4 ) 8010a2a: f423 2310 bic.w r3, r3, #589824 @ 0x90000 8010a2e: 6013 str r3, [r2, #0] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 8010a30: e008 b.n 8010a44 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8010a32: f7fd faef bl 800e014 8010a36: 4602 mov r2, r0 8010a38: 687b ldr r3, [r7, #4] 8010a3a: 1ad3 subs r3, r2, r3 8010a3c: 2b64 cmp r3, #100 @ 0x64 8010a3e: d901 bls.n 8010a44 { return HAL_TIMEOUT; 8010a40: 2303 movs r3, #3 8010a42: e04a b.n 8010ada while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 8010a44: 4b27 ldr r3, [pc, #156] @ (8010ae4 ) 8010a46: 681b ldr r3, [r3, #0] 8010a48: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010a4c: 2b00 cmp r3, #0 8010a4e: d1f0 bne.n 8010a32 } } /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 8010a50: 4b24 ldr r3, [pc, #144] @ (8010ae4 ) 8010a52: 681b ldr r3, [r3, #0] 8010a54: 4a23 ldr r2, [pc, #140] @ (8010ae4 ) 8010a56: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010a5a: 6013 str r3, [r2, #0] #if defined(RCC_PLL2_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 8010a5c: f7fd fada bl 800e014 8010a60: 6078 str r0, [r7, #4] /* Clear PLL2ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); 8010a62: 4b20 ldr r3, [pc, #128] @ (8010ae4 ) 8010a64: 681b ldr r3, [r3, #0] 8010a66: 4a1f ldr r2, [pc, #124] @ (8010ae4 ) 8010a68: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8010a6c: 6013 str r3, [r2, #0] /* Wait till PLL2 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 8010a6e: e008 b.n 8010a82 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8010a70: f7fd fad0 bl 800e014 8010a74: 4602 mov r2, r0 8010a76: 687b ldr r3, [r7, #4] 8010a78: 1ad3 subs r3, r2, r3 8010a7a: 2b64 cmp r3, #100 @ 0x64 8010a7c: d901 bls.n 8010a82 { return HAL_TIMEOUT; 8010a7e: 2303 movs r3, #3 8010a80: e02b b.n 8010ada while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 8010a82: 4b18 ldr r3, [pc, #96] @ (8010ae4 ) 8010a84: 681b ldr r3, [r3, #0] 8010a86: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8010a8a: 2b00 cmp r3, #0 8010a8c: d1f0 bne.n 8010a70 } #endif /* RCC_PLL2_SUPPORT */ #if defined(RCC_PLLI2S_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 8010a8e: f7fd fac1 bl 800e014 8010a92: 6078 str r0, [r7, #4] /* Clear PLL3ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); 8010a94: 4b13 ldr r3, [pc, #76] @ (8010ae4 ) 8010a96: 681b ldr r3, [r3, #0] 8010a98: 4a12 ldr r2, [pc, #72] @ (8010ae4 ) 8010a9a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8010a9e: 6013 str r3, [r2, #0] /* Wait till PLL3 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 8010aa0: e008 b.n 8010ab4 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8010aa2: f7fd fab7 bl 800e014 8010aa6: 4602 mov r2, r0 8010aa8: 687b ldr r3, [r7, #4] 8010aaa: 1ad3 subs r3, r2, r3 8010aac: 2b64 cmp r3, #100 @ 0x64 8010aae: d901 bls.n 8010ab4 { return HAL_TIMEOUT; 8010ab0: 2303 movs r3, #3 8010ab2: e012 b.n 8010ada while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 8010ab4: 4b0b ldr r3, [pc, #44] @ (8010ae4 ) 8010ab6: 681b ldr r3, [r3, #0] 8010ab8: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8010abc: 2b00 cmp r3, #0 8010abe: d1f0 bne.n 8010aa2 } #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_CFGR2_PREDIV1) /* Reset CFGR2 register */ CLEAR_REG(RCC->CFGR2); 8010ac0: 4b08 ldr r3, [pc, #32] @ (8010ae4 ) 8010ac2: 2200 movs r2, #0 8010ac4: 62da str r2, [r3, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1 */ /* Reset all CSR flags */ SET_BIT(RCC->CSR, RCC_CSR_RMVF); 8010ac6: 4b07 ldr r3, [pc, #28] @ (8010ae4 ) 8010ac8: 6a5b ldr r3, [r3, #36] @ 0x24 8010aca: 4a06 ldr r2, [pc, #24] @ (8010ae4 ) 8010acc: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8010ad0: 6253 str r3, [r2, #36] @ 0x24 /* Disable all interrupts */ CLEAR_REG(RCC->CIR); 8010ad2: 4b04 ldr r3, [pc, #16] @ (8010ae4 ) 8010ad4: 2200 movs r2, #0 8010ad6: 609a str r2, [r3, #8] return HAL_OK; 8010ad8: 2300 movs r3, #0 } 8010ada: 4618 mov r0, r3 8010adc: 3708 adds r7, #8 8010ade: 46bd mov sp, r7 8010ae0: bd80 pop {r7, pc} 8010ae2: bf00 nop 8010ae4: 40021000 .word 0x40021000 8010ae8: 20000084 .word 0x20000084 8010aec: 007a1200 .word 0x007a1200 8010af0: 20000088 .word 0x20000088 08010af4 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8010af4: b580 push {r7, lr} 8010af6: b086 sub sp, #24 8010af8: af00 add r7, sp, #0 8010afa: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8010afc: 687b ldr r3, [r7, #4] 8010afe: 2b00 cmp r3, #0 8010b00: d101 bne.n 8010b06 { return HAL_ERROR; 8010b02: 2301 movs r3, #1 8010b04: e304 b.n 8011110 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8010b06: 687b ldr r3, [r7, #4] 8010b08: 681b ldr r3, [r3, #0] 8010b0a: f003 0301 and.w r3, r3, #1 8010b0e: 2b00 cmp r3, #0 8010b10: f000 8087 beq.w 8010c22 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8010b14: 4b92 ldr r3, [pc, #584] @ (8010d60 ) 8010b16: 685b ldr r3, [r3, #4] 8010b18: f003 030c and.w r3, r3, #12 8010b1c: 2b04 cmp r3, #4 8010b1e: d00c beq.n 8010b3a || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8010b20: 4b8f ldr r3, [pc, #572] @ (8010d60 ) 8010b22: 685b ldr r3, [r3, #4] 8010b24: f003 030c and.w r3, r3, #12 8010b28: 2b08 cmp r3, #8 8010b2a: d112 bne.n 8010b52 8010b2c: 4b8c ldr r3, [pc, #560] @ (8010d60 ) 8010b2e: 685b ldr r3, [r3, #4] 8010b30: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010b34: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010b38: d10b bne.n 8010b52 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8010b3a: 4b89 ldr r3, [pc, #548] @ (8010d60 ) 8010b3c: 681b ldr r3, [r3, #0] 8010b3e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010b42: 2b00 cmp r3, #0 8010b44: d06c beq.n 8010c20 8010b46: 687b ldr r3, [r7, #4] 8010b48: 689b ldr r3, [r3, #8] 8010b4a: 2b00 cmp r3, #0 8010b4c: d168 bne.n 8010c20 { return HAL_ERROR; 8010b4e: 2301 movs r3, #1 8010b50: e2de b.n 8011110 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8010b52: 687b ldr r3, [r7, #4] 8010b54: 689b ldr r3, [r3, #8] 8010b56: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010b5a: d106 bne.n 8010b6a 8010b5c: 4b80 ldr r3, [pc, #512] @ (8010d60 ) 8010b5e: 681b ldr r3, [r3, #0] 8010b60: 4a7f ldr r2, [pc, #508] @ (8010d60 ) 8010b62: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8010b66: 6013 str r3, [r2, #0] 8010b68: e02e b.n 8010bc8 8010b6a: 687b ldr r3, [r7, #4] 8010b6c: 689b ldr r3, [r3, #8] 8010b6e: 2b00 cmp r3, #0 8010b70: d10c bne.n 8010b8c 8010b72: 4b7b ldr r3, [pc, #492] @ (8010d60 ) 8010b74: 681b ldr r3, [r3, #0] 8010b76: 4a7a ldr r2, [pc, #488] @ (8010d60 ) 8010b78: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8010b7c: 6013 str r3, [r2, #0] 8010b7e: 4b78 ldr r3, [pc, #480] @ (8010d60 ) 8010b80: 681b ldr r3, [r3, #0] 8010b82: 4a77 ldr r2, [pc, #476] @ (8010d60 ) 8010b84: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010b88: 6013 str r3, [r2, #0] 8010b8a: e01d b.n 8010bc8 8010b8c: 687b ldr r3, [r7, #4] 8010b8e: 689b ldr r3, [r3, #8] 8010b90: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8010b94: d10c bne.n 8010bb0 8010b96: 4b72 ldr r3, [pc, #456] @ (8010d60 ) 8010b98: 681b ldr r3, [r3, #0] 8010b9a: 4a71 ldr r2, [pc, #452] @ (8010d60 ) 8010b9c: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8010ba0: 6013 str r3, [r2, #0] 8010ba2: 4b6f ldr r3, [pc, #444] @ (8010d60 ) 8010ba4: 681b ldr r3, [r3, #0] 8010ba6: 4a6e ldr r2, [pc, #440] @ (8010d60 ) 8010ba8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8010bac: 6013 str r3, [r2, #0] 8010bae: e00b b.n 8010bc8 8010bb0: 4b6b ldr r3, [pc, #428] @ (8010d60 ) 8010bb2: 681b ldr r3, [r3, #0] 8010bb4: 4a6a ldr r2, [pc, #424] @ (8010d60 ) 8010bb6: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8010bba: 6013 str r3, [r2, #0] 8010bbc: 4b68 ldr r3, [pc, #416] @ (8010d60 ) 8010bbe: 681b ldr r3, [r3, #0] 8010bc0: 4a67 ldr r2, [pc, #412] @ (8010d60 ) 8010bc2: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010bc6: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8010bc8: 687b ldr r3, [r7, #4] 8010bca: 689b ldr r3, [r3, #8] 8010bcc: 2b00 cmp r3, #0 8010bce: d013 beq.n 8010bf8 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8010bd0: f7fd fa20 bl 800e014 8010bd4: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8010bd6: e008 b.n 8010bea { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8010bd8: f7fd fa1c bl 800e014 8010bdc: 4602 mov r2, r0 8010bde: 693b ldr r3, [r7, #16] 8010be0: 1ad3 subs r3, r2, r3 8010be2: 2b64 cmp r3, #100 @ 0x64 8010be4: d901 bls.n 8010bea { return HAL_TIMEOUT; 8010be6: 2303 movs r3, #3 8010be8: e292 b.n 8011110 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8010bea: 4b5d ldr r3, [pc, #372] @ (8010d60 ) 8010bec: 681b ldr r3, [r3, #0] 8010bee: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010bf2: 2b00 cmp r3, #0 8010bf4: d0f0 beq.n 8010bd8 8010bf6: e014 b.n 8010c22 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8010bf8: f7fd fa0c bl 800e014 8010bfc: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8010bfe: e008 b.n 8010c12 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8010c00: f7fd fa08 bl 800e014 8010c04: 4602 mov r2, r0 8010c06: 693b ldr r3, [r7, #16] 8010c08: 1ad3 subs r3, r2, r3 8010c0a: 2b64 cmp r3, #100 @ 0x64 8010c0c: d901 bls.n 8010c12 { return HAL_TIMEOUT; 8010c0e: 2303 movs r3, #3 8010c10: e27e b.n 8011110 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8010c12: 4b53 ldr r3, [pc, #332] @ (8010d60 ) 8010c14: 681b ldr r3, [r3, #0] 8010c16: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010c1a: 2b00 cmp r3, #0 8010c1c: d1f0 bne.n 8010c00 8010c1e: e000 b.n 8010c22 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8010c20: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8010c22: 687b ldr r3, [r7, #4] 8010c24: 681b ldr r3, [r3, #0] 8010c26: f003 0302 and.w r3, r3, #2 8010c2a: 2b00 cmp r3, #0 8010c2c: d063 beq.n 8010cf6 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8010c2e: 4b4c ldr r3, [pc, #304] @ (8010d60 ) 8010c30: 685b ldr r3, [r3, #4] 8010c32: f003 030c and.w r3, r3, #12 8010c36: 2b00 cmp r3, #0 8010c38: d00b beq.n 8010c52 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 8010c3a: 4b49 ldr r3, [pc, #292] @ (8010d60 ) 8010c3c: 685b ldr r3, [r3, #4] 8010c3e: f003 030c and.w r3, r3, #12 8010c42: 2b08 cmp r3, #8 8010c44: d11c bne.n 8010c80 8010c46: 4b46 ldr r3, [pc, #280] @ (8010d60 ) 8010c48: 685b ldr r3, [r3, #4] 8010c4a: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010c4e: 2b00 cmp r3, #0 8010c50: d116 bne.n 8010c80 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8010c52: 4b43 ldr r3, [pc, #268] @ (8010d60 ) 8010c54: 681b ldr r3, [r3, #0] 8010c56: f003 0302 and.w r3, r3, #2 8010c5a: 2b00 cmp r3, #0 8010c5c: d005 beq.n 8010c6a 8010c5e: 687b ldr r3, [r7, #4] 8010c60: 695b ldr r3, [r3, #20] 8010c62: 2b01 cmp r3, #1 8010c64: d001 beq.n 8010c6a { return HAL_ERROR; 8010c66: 2301 movs r3, #1 8010c68: e252 b.n 8011110 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8010c6a: 4b3d ldr r3, [pc, #244] @ (8010d60 ) 8010c6c: 681b ldr r3, [r3, #0] 8010c6e: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8010c72: 687b ldr r3, [r7, #4] 8010c74: 699b ldr r3, [r3, #24] 8010c76: 00db lsls r3, r3, #3 8010c78: 4939 ldr r1, [pc, #228] @ (8010d60 ) 8010c7a: 4313 orrs r3, r2 8010c7c: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8010c7e: e03a b.n 8010cf6 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8010c80: 687b ldr r3, [r7, #4] 8010c82: 695b ldr r3, [r3, #20] 8010c84: 2b00 cmp r3, #0 8010c86: d020 beq.n 8010cca { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8010c88: 4b36 ldr r3, [pc, #216] @ (8010d64 ) 8010c8a: 2201 movs r2, #1 8010c8c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010c8e: f7fd f9c1 bl 800e014 8010c92: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8010c94: e008 b.n 8010ca8 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8010c96: f7fd f9bd bl 800e014 8010c9a: 4602 mov r2, r0 8010c9c: 693b ldr r3, [r7, #16] 8010c9e: 1ad3 subs r3, r2, r3 8010ca0: 2b02 cmp r3, #2 8010ca2: d901 bls.n 8010ca8 { return HAL_TIMEOUT; 8010ca4: 2303 movs r3, #3 8010ca6: e233 b.n 8011110 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8010ca8: 4b2d ldr r3, [pc, #180] @ (8010d60 ) 8010caa: 681b ldr r3, [r3, #0] 8010cac: f003 0302 and.w r3, r3, #2 8010cb0: 2b00 cmp r3, #0 8010cb2: d0f0 beq.n 8010c96 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8010cb4: 4b2a ldr r3, [pc, #168] @ (8010d60 ) 8010cb6: 681b ldr r3, [r3, #0] 8010cb8: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8010cbc: 687b ldr r3, [r7, #4] 8010cbe: 699b ldr r3, [r3, #24] 8010cc0: 00db lsls r3, r3, #3 8010cc2: 4927 ldr r1, [pc, #156] @ (8010d60 ) 8010cc4: 4313 orrs r3, r2 8010cc6: 600b str r3, [r1, #0] 8010cc8: e015 b.n 8010cf6 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8010cca: 4b26 ldr r3, [pc, #152] @ (8010d64 ) 8010ccc: 2200 movs r2, #0 8010cce: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010cd0: f7fd f9a0 bl 800e014 8010cd4: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8010cd6: e008 b.n 8010cea { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8010cd8: f7fd f99c bl 800e014 8010cdc: 4602 mov r2, r0 8010cde: 693b ldr r3, [r7, #16] 8010ce0: 1ad3 subs r3, r2, r3 8010ce2: 2b02 cmp r3, #2 8010ce4: d901 bls.n 8010cea { return HAL_TIMEOUT; 8010ce6: 2303 movs r3, #3 8010ce8: e212 b.n 8011110 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8010cea: 4b1d ldr r3, [pc, #116] @ (8010d60 ) 8010cec: 681b ldr r3, [r3, #0] 8010cee: f003 0302 and.w r3, r3, #2 8010cf2: 2b00 cmp r3, #0 8010cf4: d1f0 bne.n 8010cd8 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8010cf6: 687b ldr r3, [r7, #4] 8010cf8: 681b ldr r3, [r3, #0] 8010cfa: f003 0308 and.w r3, r3, #8 8010cfe: 2b00 cmp r3, #0 8010d00: d03a beq.n 8010d78 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8010d02: 687b ldr r3, [r7, #4] 8010d04: 69db ldr r3, [r3, #28] 8010d06: 2b00 cmp r3, #0 8010d08: d019 beq.n 8010d3e { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8010d0a: 4b17 ldr r3, [pc, #92] @ (8010d68 ) 8010d0c: 2201 movs r2, #1 8010d0e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010d10: f7fd f980 bl 800e014 8010d14: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8010d16: e008 b.n 8010d2a { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8010d18: f7fd f97c bl 800e014 8010d1c: 4602 mov r2, r0 8010d1e: 693b ldr r3, [r7, #16] 8010d20: 1ad3 subs r3, r2, r3 8010d22: 2b02 cmp r3, #2 8010d24: d901 bls.n 8010d2a { return HAL_TIMEOUT; 8010d26: 2303 movs r3, #3 8010d28: e1f2 b.n 8011110 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8010d2a: 4b0d ldr r3, [pc, #52] @ (8010d60 ) 8010d2c: 6a5b ldr r3, [r3, #36] @ 0x24 8010d2e: f003 0302 and.w r3, r3, #2 8010d32: 2b00 cmp r3, #0 8010d34: d0f0 beq.n 8010d18 } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 8010d36: 2001 movs r0, #1 8010d38: f000 fbca bl 80114d0 8010d3c: e01c b.n 8010d78 } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8010d3e: 4b0a ldr r3, [pc, #40] @ (8010d68 ) 8010d40: 2200 movs r2, #0 8010d42: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010d44: f7fd f966 bl 800e014 8010d48: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8010d4a: e00f b.n 8010d6c { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8010d4c: f7fd f962 bl 800e014 8010d50: 4602 mov r2, r0 8010d52: 693b ldr r3, [r7, #16] 8010d54: 1ad3 subs r3, r2, r3 8010d56: 2b02 cmp r3, #2 8010d58: d908 bls.n 8010d6c { return HAL_TIMEOUT; 8010d5a: 2303 movs r3, #3 8010d5c: e1d8 b.n 8011110 8010d5e: bf00 nop 8010d60: 40021000 .word 0x40021000 8010d64: 42420000 .word 0x42420000 8010d68: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8010d6c: 4b9b ldr r3, [pc, #620] @ (8010fdc ) 8010d6e: 6a5b ldr r3, [r3, #36] @ 0x24 8010d70: f003 0302 and.w r3, r3, #2 8010d74: 2b00 cmp r3, #0 8010d76: d1e9 bne.n 8010d4c } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8010d78: 687b ldr r3, [r7, #4] 8010d7a: 681b ldr r3, [r3, #0] 8010d7c: f003 0304 and.w r3, r3, #4 8010d80: 2b00 cmp r3, #0 8010d82: f000 80a6 beq.w 8010ed2 { FlagStatus pwrclkchanged = RESET; 8010d86: 2300 movs r3, #0 8010d88: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8010d8a: 4b94 ldr r3, [pc, #592] @ (8010fdc ) 8010d8c: 69db ldr r3, [r3, #28] 8010d8e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010d92: 2b00 cmp r3, #0 8010d94: d10d bne.n 8010db2 { __HAL_RCC_PWR_CLK_ENABLE(); 8010d96: 4b91 ldr r3, [pc, #580] @ (8010fdc ) 8010d98: 69db ldr r3, [r3, #28] 8010d9a: 4a90 ldr r2, [pc, #576] @ (8010fdc ) 8010d9c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8010da0: 61d3 str r3, [r2, #28] 8010da2: 4b8e ldr r3, [pc, #568] @ (8010fdc ) 8010da4: 69db ldr r3, [r3, #28] 8010da6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010daa: 60bb str r3, [r7, #8] 8010dac: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8010dae: 2301 movs r3, #1 8010db0: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010db2: 4b8b ldr r3, [pc, #556] @ (8010fe0 ) 8010db4: 681b ldr r3, [r3, #0] 8010db6: f403 7380 and.w r3, r3, #256 @ 0x100 8010dba: 2b00 cmp r3, #0 8010dbc: d118 bne.n 8010df0 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8010dbe: 4b88 ldr r3, [pc, #544] @ (8010fe0 ) 8010dc0: 681b ldr r3, [r3, #0] 8010dc2: 4a87 ldr r2, [pc, #540] @ (8010fe0 ) 8010dc4: f443 7380 orr.w r3, r3, #256 @ 0x100 8010dc8: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8010dca: f7fd f923 bl 800e014 8010dce: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010dd0: e008 b.n 8010de4 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8010dd2: f7fd f91f bl 800e014 8010dd6: 4602 mov r2, r0 8010dd8: 693b ldr r3, [r7, #16] 8010dda: 1ad3 subs r3, r2, r3 8010ddc: 2b64 cmp r3, #100 @ 0x64 8010dde: d901 bls.n 8010de4 { return HAL_TIMEOUT; 8010de0: 2303 movs r3, #3 8010de2: e195 b.n 8011110 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010de4: 4b7e ldr r3, [pc, #504] @ (8010fe0 ) 8010de6: 681b ldr r3, [r3, #0] 8010de8: f403 7380 and.w r3, r3, #256 @ 0x100 8010dec: 2b00 cmp r3, #0 8010dee: d0f0 beq.n 8010dd2 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8010df0: 687b ldr r3, [r7, #4] 8010df2: 691b ldr r3, [r3, #16] 8010df4: 2b01 cmp r3, #1 8010df6: d106 bne.n 8010e06 8010df8: 4b78 ldr r3, [pc, #480] @ (8010fdc ) 8010dfa: 6a1b ldr r3, [r3, #32] 8010dfc: 4a77 ldr r2, [pc, #476] @ (8010fdc ) 8010dfe: f043 0301 orr.w r3, r3, #1 8010e02: 6213 str r3, [r2, #32] 8010e04: e02d b.n 8010e62 8010e06: 687b ldr r3, [r7, #4] 8010e08: 691b ldr r3, [r3, #16] 8010e0a: 2b00 cmp r3, #0 8010e0c: d10c bne.n 8010e28 8010e0e: 4b73 ldr r3, [pc, #460] @ (8010fdc ) 8010e10: 6a1b ldr r3, [r3, #32] 8010e12: 4a72 ldr r2, [pc, #456] @ (8010fdc ) 8010e14: f023 0301 bic.w r3, r3, #1 8010e18: 6213 str r3, [r2, #32] 8010e1a: 4b70 ldr r3, [pc, #448] @ (8010fdc ) 8010e1c: 6a1b ldr r3, [r3, #32] 8010e1e: 4a6f ldr r2, [pc, #444] @ (8010fdc ) 8010e20: f023 0304 bic.w r3, r3, #4 8010e24: 6213 str r3, [r2, #32] 8010e26: e01c b.n 8010e62 8010e28: 687b ldr r3, [r7, #4] 8010e2a: 691b ldr r3, [r3, #16] 8010e2c: 2b05 cmp r3, #5 8010e2e: d10c bne.n 8010e4a 8010e30: 4b6a ldr r3, [pc, #424] @ (8010fdc ) 8010e32: 6a1b ldr r3, [r3, #32] 8010e34: 4a69 ldr r2, [pc, #420] @ (8010fdc ) 8010e36: f043 0304 orr.w r3, r3, #4 8010e3a: 6213 str r3, [r2, #32] 8010e3c: 4b67 ldr r3, [pc, #412] @ (8010fdc ) 8010e3e: 6a1b ldr r3, [r3, #32] 8010e40: 4a66 ldr r2, [pc, #408] @ (8010fdc ) 8010e42: f043 0301 orr.w r3, r3, #1 8010e46: 6213 str r3, [r2, #32] 8010e48: e00b b.n 8010e62 8010e4a: 4b64 ldr r3, [pc, #400] @ (8010fdc ) 8010e4c: 6a1b ldr r3, [r3, #32] 8010e4e: 4a63 ldr r2, [pc, #396] @ (8010fdc ) 8010e50: f023 0301 bic.w r3, r3, #1 8010e54: 6213 str r3, [r2, #32] 8010e56: 4b61 ldr r3, [pc, #388] @ (8010fdc ) 8010e58: 6a1b ldr r3, [r3, #32] 8010e5a: 4a60 ldr r2, [pc, #384] @ (8010fdc ) 8010e5c: f023 0304 bic.w r3, r3, #4 8010e60: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8010e62: 687b ldr r3, [r7, #4] 8010e64: 691b ldr r3, [r3, #16] 8010e66: 2b00 cmp r3, #0 8010e68: d015 beq.n 8010e96 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8010e6a: f7fd f8d3 bl 800e014 8010e6e: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8010e70: e00a b.n 8010e88 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8010e72: f7fd f8cf bl 800e014 8010e76: 4602 mov r2, r0 8010e78: 693b ldr r3, [r7, #16] 8010e7a: 1ad3 subs r3, r2, r3 8010e7c: f241 3288 movw r2, #5000 @ 0x1388 8010e80: 4293 cmp r3, r2 8010e82: d901 bls.n 8010e88 { return HAL_TIMEOUT; 8010e84: 2303 movs r3, #3 8010e86: e143 b.n 8011110 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8010e88: 4b54 ldr r3, [pc, #336] @ (8010fdc ) 8010e8a: 6a1b ldr r3, [r3, #32] 8010e8c: f003 0302 and.w r3, r3, #2 8010e90: 2b00 cmp r3, #0 8010e92: d0ee beq.n 8010e72 8010e94: e014 b.n 8010ec0 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8010e96: f7fd f8bd bl 800e014 8010e9a: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8010e9c: e00a b.n 8010eb4 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8010e9e: f7fd f8b9 bl 800e014 8010ea2: 4602 mov r2, r0 8010ea4: 693b ldr r3, [r7, #16] 8010ea6: 1ad3 subs r3, r2, r3 8010ea8: f241 3288 movw r2, #5000 @ 0x1388 8010eac: 4293 cmp r3, r2 8010eae: d901 bls.n 8010eb4 { return HAL_TIMEOUT; 8010eb0: 2303 movs r3, #3 8010eb2: e12d b.n 8011110 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8010eb4: 4b49 ldr r3, [pc, #292] @ (8010fdc ) 8010eb6: 6a1b ldr r3, [r3, #32] 8010eb8: f003 0302 and.w r3, r3, #2 8010ebc: 2b00 cmp r3, #0 8010ebe: d1ee bne.n 8010e9e } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8010ec0: 7dfb ldrb r3, [r7, #23] 8010ec2: 2b01 cmp r3, #1 8010ec4: d105 bne.n 8010ed2 { __HAL_RCC_PWR_CLK_DISABLE(); 8010ec6: 4b45 ldr r3, [pc, #276] @ (8010fdc ) 8010ec8: 69db ldr r3, [r3, #28] 8010eca: 4a44 ldr r2, [pc, #272] @ (8010fdc ) 8010ecc: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8010ed0: 61d3 str r3, [r2, #28] #if defined(RCC_CR_PLL2ON) /*-------------------------------- PLL2 Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) 8010ed2: 687b ldr r3, [r7, #4] 8010ed4: 6adb ldr r3, [r3, #44] @ 0x2c 8010ed6: 2b00 cmp r3, #0 8010ed8: f000 808c beq.w 8010ff4 { /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 8010edc: 4b3f ldr r3, [pc, #252] @ (8010fdc ) 8010ede: 685b ldr r3, [r3, #4] 8010ee0: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010ee4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010ee8: d10e bne.n 8010f08 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 8010eea: 4b3c ldr r3, [pc, #240] @ (8010fdc ) 8010eec: 685b ldr r3, [r3, #4] 8010eee: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 8010ef2: 2b08 cmp r3, #8 8010ef4: d108 bne.n 8010f08 ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) 8010ef6: 4b39 ldr r3, [pc, #228] @ (8010fdc ) 8010ef8: 6adb ldr r3, [r3, #44] @ 0x2c 8010efa: f403 3380 and.w r3, r3, #65536 @ 0x10000 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 8010efe: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010f02: d101 bne.n 8010f08 { return HAL_ERROR; 8010f04: 2301 movs r3, #1 8010f06: e103 b.n 8011110 } else { if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) 8010f08: 687b ldr r3, [r7, #4] 8010f0a: 6adb ldr r3, [r3, #44] @ 0x2c 8010f0c: 2b02 cmp r3, #2 8010f0e: d14e bne.n 8010fae assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); /* Prediv2 can be written only when the PLLI2S is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 8010f10: 4b32 ldr r3, [pc, #200] @ (8010fdc ) 8010f12: 681b ldr r3, [r3, #0] 8010f14: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010f18: 2b00 cmp r3, #0 8010f1a: d009 beq.n 8010f30 (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) 8010f1c: 4b2f ldr r3, [pc, #188] @ (8010fdc ) 8010f1e: 6adb ldr r3, [r3, #44] @ 0x2c 8010f20: f003 02f0 and.w r2, r3, #240 @ 0xf0 8010f24: 687b ldr r3, [r7, #4] 8010f26: 6b5b ldr r3, [r3, #52] @ 0x34 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 8010f28: 429a cmp r2, r3 8010f2a: d001 beq.n 8010f30 { return HAL_ERROR; 8010f2c: 2301 movs r3, #1 8010f2e: e0ef b.n 8011110 } /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 8010f30: 4b2c ldr r3, [pc, #176] @ (8010fe4 ) 8010f32: 2200 movs r2, #0 8010f34: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010f36: f7fd f86d bl 800e014 8010f3a: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8010f3c: e008 b.n 8010f50 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8010f3e: f7fd f869 bl 800e014 8010f42: 4602 mov r2, r0 8010f44: 693b ldr r3, [r7, #16] 8010f46: 1ad3 subs r3, r2, r3 8010f48: 2b64 cmp r3, #100 @ 0x64 8010f4a: d901 bls.n 8010f50 { return HAL_TIMEOUT; 8010f4c: 2303 movs r3, #3 8010f4e: e0df b.n 8011110 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8010f50: 4b22 ldr r3, [pc, #136] @ (8010fdc ) 8010f52: 681b ldr r3, [r3, #0] 8010f54: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8010f58: 2b00 cmp r3, #0 8010f5a: d1f0 bne.n 8010f3e } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); 8010f5c: 4b1f ldr r3, [pc, #124] @ (8010fdc ) 8010f5e: 6adb ldr r3, [r3, #44] @ 0x2c 8010f60: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8010f64: 687b ldr r3, [r7, #4] 8010f66: 6b5b ldr r3, [r3, #52] @ 0x34 8010f68: 491c ldr r1, [pc, #112] @ (8010fdc ) 8010f6a: 4313 orrs r3, r2 8010f6c: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); 8010f6e: 4b1b ldr r3, [pc, #108] @ (8010fdc ) 8010f70: 6adb ldr r3, [r3, #44] @ 0x2c 8010f72: f423 6270 bic.w r2, r3, #3840 @ 0xf00 8010f76: 687b ldr r3, [r7, #4] 8010f78: 6b1b ldr r3, [r3, #48] @ 0x30 8010f7a: 4918 ldr r1, [pc, #96] @ (8010fdc ) 8010f7c: 4313 orrs r3, r2 8010f7e: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); 8010f80: 4b18 ldr r3, [pc, #96] @ (8010fe4 ) 8010f82: 2201 movs r2, #1 8010f84: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010f86: f7fd f845 bl 800e014 8010f8a: 6138 str r0, [r7, #16] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 8010f8c: e008 b.n 8010fa0 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8010f8e: f7fd f841 bl 800e014 8010f92: 4602 mov r2, r0 8010f94: 693b ldr r3, [r7, #16] 8010f96: 1ad3 subs r3, r2, r3 8010f98: 2b64 cmp r3, #100 @ 0x64 8010f9a: d901 bls.n 8010fa0 { return HAL_TIMEOUT; 8010f9c: 2303 movs r3, #3 8010f9e: e0b7 b.n 8011110 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 8010fa0: 4b0e ldr r3, [pc, #56] @ (8010fdc ) 8010fa2: 681b ldr r3, [r3, #0] 8010fa4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8010fa8: 2b00 cmp r3, #0 8010faa: d0f0 beq.n 8010f8e 8010fac: e022 b.n 8010ff4 } } else { /* Set PREDIV1 source to HSE */ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); 8010fae: 4b0b ldr r3, [pc, #44] @ (8010fdc ) 8010fb0: 6adb ldr r3, [r3, #44] @ 0x2c 8010fb2: 4a0a ldr r2, [pc, #40] @ (8010fdc ) 8010fb4: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8010fb8: 62d3 str r3, [r2, #44] @ 0x2c /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 8010fba: 4b0a ldr r3, [pc, #40] @ (8010fe4 ) 8010fbc: 2200 movs r2, #0 8010fbe: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010fc0: f7fd f828 bl 800e014 8010fc4: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8010fc6: e00f b.n 8010fe8 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8010fc8: f7fd f824 bl 800e014 8010fcc: 4602 mov r2, r0 8010fce: 693b ldr r3, [r7, #16] 8010fd0: 1ad3 subs r3, r2, r3 8010fd2: 2b64 cmp r3, #100 @ 0x64 8010fd4: d908 bls.n 8010fe8 { return HAL_TIMEOUT; 8010fd6: 2303 movs r3, #3 8010fd8: e09a b.n 8011110 8010fda: bf00 nop 8010fdc: 40021000 .word 0x40021000 8010fe0: 40007000 .word 0x40007000 8010fe4: 42420068 .word 0x42420068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8010fe8: 4b4b ldr r3, [pc, #300] @ (8011118 ) 8010fea: 681b ldr r3, [r3, #0] 8010fec: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8010ff0: 2b00 cmp r3, #0 8010ff2: d1e9 bne.n 8010fc8 #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8010ff4: 687b ldr r3, [r7, #4] 8010ff6: 6a1b ldr r3, [r3, #32] 8010ff8: 2b00 cmp r3, #0 8010ffa: f000 8088 beq.w 801110e { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8010ffe: 4b46 ldr r3, [pc, #280] @ (8011118 ) 8011000: 685b ldr r3, [r3, #4] 8011002: f003 030c and.w r3, r3, #12 8011006: 2b08 cmp r3, #8 8011008: d068 beq.n 80110dc { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 801100a: 687b ldr r3, [r7, #4] 801100c: 6a1b ldr r3, [r3, #32] 801100e: 2b02 cmp r3, #2 8011010: d14d bne.n 80110ae /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8011012: 4b42 ldr r3, [pc, #264] @ (801111c ) 8011014: 2200 movs r2, #0 8011016: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8011018: f7fc fffc bl 800e014 801101c: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 801101e: e008 b.n 8011032 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8011020: f7fc fff8 bl 800e014 8011024: 4602 mov r2, r0 8011026: 693b ldr r3, [r7, #16] 8011028: 1ad3 subs r3, r2, r3 801102a: 2b02 cmp r3, #2 801102c: d901 bls.n 8011032 { return HAL_TIMEOUT; 801102e: 2303 movs r3, #3 8011030: e06e b.n 8011110 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8011032: 4b39 ldr r3, [pc, #228] @ (8011118 ) 8011034: 681b ldr r3, [r3, #0] 8011036: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 801103a: 2b00 cmp r3, #0 801103c: d1f0 bne.n 8011020 } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 801103e: 687b ldr r3, [r7, #4] 8011040: 6a5b ldr r3, [r3, #36] @ 0x24 8011042: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8011046: d10f bne.n 8011068 assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); #if defined(RCC_CFGR2_PREDIV1SRC) assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); 8011048: 4b33 ldr r3, [pc, #204] @ (8011118 ) 801104a: 6ada ldr r2, [r3, #44] @ 0x2c 801104c: 687b ldr r3, [r7, #4] 801104e: 685b ldr r3, [r3, #4] 8011050: 4931 ldr r1, [pc, #196] @ (8011118 ) 8011052: 4313 orrs r3, r2 8011054: 62cb str r3, [r1, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 8011056: 4b30 ldr r3, [pc, #192] @ (8011118 ) 8011058: 6adb ldr r3, [r3, #44] @ 0x2c 801105a: f023 020f bic.w r2, r3, #15 801105e: 687b ldr r3, [r7, #4] 8011060: 68db ldr r3, [r3, #12] 8011062: 492d ldr r1, [pc, #180] @ (8011118 ) 8011064: 4313 orrs r3, r2 8011066: 62cb str r3, [r1, #44] @ 0x2c } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8011068: 4b2b ldr r3, [pc, #172] @ (8011118 ) 801106a: 685b ldr r3, [r3, #4] 801106c: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 8011070: 687b ldr r3, [r7, #4] 8011072: 6a59 ldr r1, [r3, #36] @ 0x24 8011074: 687b ldr r3, [r7, #4] 8011076: 6a9b ldr r3, [r3, #40] @ 0x28 8011078: 430b orrs r3, r1 801107a: 4927 ldr r1, [pc, #156] @ (8011118 ) 801107c: 4313 orrs r3, r2 801107e: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8011080: 4b26 ldr r3, [pc, #152] @ (801111c ) 8011082: 2201 movs r2, #1 8011084: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8011086: f7fc ffc5 bl 800e014 801108a: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 801108c: e008 b.n 80110a0 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 801108e: f7fc ffc1 bl 800e014 8011092: 4602 mov r2, r0 8011094: 693b ldr r3, [r7, #16] 8011096: 1ad3 subs r3, r2, r3 8011098: 2b02 cmp r3, #2 801109a: d901 bls.n 80110a0 { return HAL_TIMEOUT; 801109c: 2303 movs r3, #3 801109e: e037 b.n 8011110 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80110a0: 4b1d ldr r3, [pc, #116] @ (8011118 ) 80110a2: 681b ldr r3, [r3, #0] 80110a4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80110a8: 2b00 cmp r3, #0 80110aa: d0f0 beq.n 801108e 80110ac: e02f b.n 801110e } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80110ae: 4b1b ldr r3, [pc, #108] @ (801111c ) 80110b0: 2200 movs r2, #0 80110b2: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80110b4: f7fc ffae bl 800e014 80110b8: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80110ba: e008 b.n 80110ce { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80110bc: f7fc ffaa bl 800e014 80110c0: 4602 mov r2, r0 80110c2: 693b ldr r3, [r7, #16] 80110c4: 1ad3 subs r3, r2, r3 80110c6: 2b02 cmp r3, #2 80110c8: d901 bls.n 80110ce { return HAL_TIMEOUT; 80110ca: 2303 movs r3, #3 80110cc: e020 b.n 8011110 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80110ce: 4b12 ldr r3, [pc, #72] @ (8011118 ) 80110d0: 681b ldr r3, [r3, #0] 80110d2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80110d6: 2b00 cmp r3, #0 80110d8: d1f0 bne.n 80110bc 80110da: e018 b.n 801110e } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 80110dc: 687b ldr r3, [r7, #4] 80110de: 6a1b ldr r3, [r3, #32] 80110e0: 2b01 cmp r3, #1 80110e2: d101 bne.n 80110e8 { return HAL_ERROR; 80110e4: 2301 movs r3, #1 80110e6: e013 b.n 8011110 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 80110e8: 4b0b ldr r3, [pc, #44] @ (8011118 ) 80110ea: 685b ldr r3, [r3, #4] 80110ec: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80110ee: 68fb ldr r3, [r7, #12] 80110f0: f403 3280 and.w r2, r3, #65536 @ 0x10000 80110f4: 687b ldr r3, [r7, #4] 80110f6: 6a5b ldr r3, [r3, #36] @ 0x24 80110f8: 429a cmp r2, r3 80110fa: d106 bne.n 801110a (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 80110fc: 68fb ldr r3, [r7, #12] 80110fe: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 8011102: 687b ldr r3, [r7, #4] 8011104: 6a9b ldr r3, [r3, #40] @ 0x28 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8011106: 429a cmp r2, r3 8011108: d001 beq.n 801110e { return HAL_ERROR; 801110a: 2301 movs r3, #1 801110c: e000 b.n 8011110 } } } } return HAL_OK; 801110e: 2300 movs r3, #0 } 8011110: 4618 mov r0, r3 8011112: 3718 adds r7, #24 8011114: 46bd mov sp, r7 8011116: bd80 pop {r7, pc} 8011118: 40021000 .word 0x40021000 801111c: 42420060 .word 0x42420060 08011120 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8011120: b580 push {r7, lr} 8011122: b084 sub sp, #16 8011124: af00 add r7, sp, #0 8011126: 6078 str r0, [r7, #4] 8011128: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 801112a: 687b ldr r3, [r7, #4] 801112c: 2b00 cmp r3, #0 801112e: d101 bne.n 8011134 { return HAL_ERROR; 8011130: 2301 movs r3, #1 8011132: e0d0 b.n 80112d6 must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8011134: 4b6a ldr r3, [pc, #424] @ (80112e0 ) 8011136: 681b ldr r3, [r3, #0] 8011138: f003 0307 and.w r3, r3, #7 801113c: 683a ldr r2, [r7, #0] 801113e: 429a cmp r2, r3 8011140: d910 bls.n 8011164 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8011142: 4b67 ldr r3, [pc, #412] @ (80112e0 ) 8011144: 681b ldr r3, [r3, #0] 8011146: f023 0207 bic.w r2, r3, #7 801114a: 4965 ldr r1, [pc, #404] @ (80112e0 ) 801114c: 683b ldr r3, [r7, #0] 801114e: 4313 orrs r3, r2 8011150: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8011152: 4b63 ldr r3, [pc, #396] @ (80112e0 ) 8011154: 681b ldr r3, [r3, #0] 8011156: f003 0307 and.w r3, r3, #7 801115a: 683a ldr r2, [r7, #0] 801115c: 429a cmp r2, r3 801115e: d001 beq.n 8011164 { return HAL_ERROR; 8011160: 2301 movs r3, #1 8011162: e0b8 b.n 80112d6 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8011164: 687b ldr r3, [r7, #4] 8011166: 681b ldr r3, [r3, #0] 8011168: f003 0302 and.w r3, r3, #2 801116c: 2b00 cmp r3, #0 801116e: d020 beq.n 80111b2 { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8011170: 687b ldr r3, [r7, #4] 8011172: 681b ldr r3, [r3, #0] 8011174: f003 0304 and.w r3, r3, #4 8011178: 2b00 cmp r3, #0 801117a: d005 beq.n 8011188 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 801117c: 4b59 ldr r3, [pc, #356] @ (80112e4 ) 801117e: 685b ldr r3, [r3, #4] 8011180: 4a58 ldr r2, [pc, #352] @ (80112e4 ) 8011182: f443 63e0 orr.w r3, r3, #1792 @ 0x700 8011186: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8011188: 687b ldr r3, [r7, #4] 801118a: 681b ldr r3, [r3, #0] 801118c: f003 0308 and.w r3, r3, #8 8011190: 2b00 cmp r3, #0 8011192: d005 beq.n 80111a0 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8011194: 4b53 ldr r3, [pc, #332] @ (80112e4 ) 8011196: 685b ldr r3, [r3, #4] 8011198: 4a52 ldr r2, [pc, #328] @ (80112e4 ) 801119a: f443 5360 orr.w r3, r3, #14336 @ 0x3800 801119e: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 80111a0: 4b50 ldr r3, [pc, #320] @ (80112e4 ) 80111a2: 685b ldr r3, [r3, #4] 80111a4: f023 02f0 bic.w r2, r3, #240 @ 0xf0 80111a8: 687b ldr r3, [r7, #4] 80111aa: 689b ldr r3, [r3, #8] 80111ac: 494d ldr r1, [pc, #308] @ (80112e4 ) 80111ae: 4313 orrs r3, r2 80111b0: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80111b2: 687b ldr r3, [r7, #4] 80111b4: 681b ldr r3, [r3, #0] 80111b6: f003 0301 and.w r3, r3, #1 80111ba: 2b00 cmp r3, #0 80111bc: d040 beq.n 8011240 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80111be: 687b ldr r3, [r7, #4] 80111c0: 685b ldr r3, [r3, #4] 80111c2: 2b01 cmp r3, #1 80111c4: d107 bne.n 80111d6 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80111c6: 4b47 ldr r3, [pc, #284] @ (80112e4 ) 80111c8: 681b ldr r3, [r3, #0] 80111ca: f403 3300 and.w r3, r3, #131072 @ 0x20000 80111ce: 2b00 cmp r3, #0 80111d0: d115 bne.n 80111fe { return HAL_ERROR; 80111d2: 2301 movs r3, #1 80111d4: e07f b.n 80112d6 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 80111d6: 687b ldr r3, [r7, #4] 80111d8: 685b ldr r3, [r3, #4] 80111da: 2b02 cmp r3, #2 80111dc: d107 bne.n 80111ee { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80111de: 4b41 ldr r3, [pc, #260] @ (80112e4 ) 80111e0: 681b ldr r3, [r3, #0] 80111e2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80111e6: 2b00 cmp r3, #0 80111e8: d109 bne.n 80111fe { return HAL_ERROR; 80111ea: 2301 movs r3, #1 80111ec: e073 b.n 80112d6 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80111ee: 4b3d ldr r3, [pc, #244] @ (80112e4 ) 80111f0: 681b ldr r3, [r3, #0] 80111f2: f003 0302 and.w r3, r3, #2 80111f6: 2b00 cmp r3, #0 80111f8: d101 bne.n 80111fe { return HAL_ERROR; 80111fa: 2301 movs r3, #1 80111fc: e06b b.n 80112d6 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 80111fe: 4b39 ldr r3, [pc, #228] @ (80112e4 ) 8011200: 685b ldr r3, [r3, #4] 8011202: f023 0203 bic.w r2, r3, #3 8011206: 687b ldr r3, [r7, #4] 8011208: 685b ldr r3, [r3, #4] 801120a: 4936 ldr r1, [pc, #216] @ (80112e4 ) 801120c: 4313 orrs r3, r2 801120e: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8011210: f7fc ff00 bl 800e014 8011214: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8011216: e00a b.n 801122e { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8011218: f7fc fefc bl 800e014 801121c: 4602 mov r2, r0 801121e: 68fb ldr r3, [r7, #12] 8011220: 1ad3 subs r3, r2, r3 8011222: f241 3288 movw r2, #5000 @ 0x1388 8011226: 4293 cmp r3, r2 8011228: d901 bls.n 801122e { return HAL_TIMEOUT; 801122a: 2303 movs r3, #3 801122c: e053 b.n 80112d6 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 801122e: 4b2d ldr r3, [pc, #180] @ (80112e4 ) 8011230: 685b ldr r3, [r3, #4] 8011232: f003 020c and.w r2, r3, #12 8011236: 687b ldr r3, [r7, #4] 8011238: 685b ldr r3, [r3, #4] 801123a: 009b lsls r3, r3, #2 801123c: 429a cmp r2, r3 801123e: d1eb bne.n 8011218 } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8011240: 4b27 ldr r3, [pc, #156] @ (80112e0 ) 8011242: 681b ldr r3, [r3, #0] 8011244: f003 0307 and.w r3, r3, #7 8011248: 683a ldr r2, [r7, #0] 801124a: 429a cmp r2, r3 801124c: d210 bcs.n 8011270 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 801124e: 4b24 ldr r3, [pc, #144] @ (80112e0 ) 8011250: 681b ldr r3, [r3, #0] 8011252: f023 0207 bic.w r2, r3, #7 8011256: 4922 ldr r1, [pc, #136] @ (80112e0 ) 8011258: 683b ldr r3, [r7, #0] 801125a: 4313 orrs r3, r2 801125c: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 801125e: 4b20 ldr r3, [pc, #128] @ (80112e0 ) 8011260: 681b ldr r3, [r3, #0] 8011262: f003 0307 and.w r3, r3, #7 8011266: 683a ldr r2, [r7, #0] 8011268: 429a cmp r2, r3 801126a: d001 beq.n 8011270 { return HAL_ERROR; 801126c: 2301 movs r3, #1 801126e: e032 b.n 80112d6 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8011270: 687b ldr r3, [r7, #4] 8011272: 681b ldr r3, [r3, #0] 8011274: f003 0304 and.w r3, r3, #4 8011278: 2b00 cmp r3, #0 801127a: d008 beq.n 801128e { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 801127c: 4b19 ldr r3, [pc, #100] @ (80112e4 ) 801127e: 685b ldr r3, [r3, #4] 8011280: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8011284: 687b ldr r3, [r7, #4] 8011286: 68db ldr r3, [r3, #12] 8011288: 4916 ldr r1, [pc, #88] @ (80112e4 ) 801128a: 4313 orrs r3, r2 801128c: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 801128e: 687b ldr r3, [r7, #4] 8011290: 681b ldr r3, [r3, #0] 8011292: f003 0308 and.w r3, r3, #8 8011296: 2b00 cmp r3, #0 8011298: d009 beq.n 80112ae { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 801129a: 4b12 ldr r3, [pc, #72] @ (80112e4 ) 801129c: 685b ldr r3, [r3, #4] 801129e: f423 5260 bic.w r2, r3, #14336 @ 0x3800 80112a2: 687b ldr r3, [r7, #4] 80112a4: 691b ldr r3, [r3, #16] 80112a6: 00db lsls r3, r3, #3 80112a8: 490e ldr r1, [pc, #56] @ (80112e4 ) 80112aa: 4313 orrs r3, r2 80112ac: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 80112ae: f000 f821 bl 80112f4 80112b2: 4602 mov r2, r0 80112b4: 4b0b ldr r3, [pc, #44] @ (80112e4 ) 80112b6: 685b ldr r3, [r3, #4] 80112b8: 091b lsrs r3, r3, #4 80112ba: f003 030f and.w r3, r3, #15 80112be: 490a ldr r1, [pc, #40] @ (80112e8 ) 80112c0: 5ccb ldrb r3, [r1, r3] 80112c2: fa22 f303 lsr.w r3, r2, r3 80112c6: 4a09 ldr r2, [pc, #36] @ (80112ec ) 80112c8: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 80112ca: 4b09 ldr r3, [pc, #36] @ (80112f0 ) 80112cc: 681b ldr r3, [r3, #0] 80112ce: 4618 mov r0, r3 80112d0: f7fc fe5e bl 800df90 return HAL_OK; 80112d4: 2300 movs r3, #0 } 80112d6: 4618 mov r0, r3 80112d8: 3710 adds r7, #16 80112da: 46bd mov sp, r7 80112dc: bd80 pop {r7, pc} 80112de: bf00 nop 80112e0: 40022000 .word 0x40022000 80112e4: 40021000 .word 0x40021000 80112e8: 08017224 .word 0x08017224 80112ec: 20000084 .word 0x20000084 80112f0: 20000088 .word 0x20000088 080112f4 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 80112f4: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 80112f8: b08e sub sp, #56 @ 0x38 80112fa: af00 add r7, sp, #0 #else static const uint8_t aPredivFactorTable[2U] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 80112fc: 2300 movs r3, #0 80112fe: 62fb str r3, [r7, #44] @ 0x2c 8011300: 2300 movs r3, #0 8011302: 62bb str r3, [r7, #40] @ 0x28 8011304: 2300 movs r3, #0 8011306: 637b str r3, [r7, #52] @ 0x34 8011308: 2300 movs r3, #0 801130a: 627b str r3, [r7, #36] @ 0x24 uint32_t sysclockfreq = 0U; 801130c: 2300 movs r3, #0 801130e: 633b str r3, [r7, #48] @ 0x30 #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; 8011310: 2300 movs r3, #0 8011312: 623b str r3, [r7, #32] 8011314: 2300 movs r3, #0 8011316: 61fb str r3, [r7, #28] #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 8011318: 4b4e ldr r3, [pc, #312] @ (8011454 ) 801131a: 685b ldr r3, [r3, #4] 801131c: 62fb str r3, [r7, #44] @ 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 801131e: 6afb ldr r3, [r7, #44] @ 0x2c 8011320: f003 030c and.w r3, r3, #12 8011324: 2b04 cmp r3, #4 8011326: d002 beq.n 801132e 8011328: 2b08 cmp r3, #8 801132a: d003 beq.n 8011334 801132c: e089 b.n 8011442 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 801132e: 4b4a ldr r3, [pc, #296] @ (8011458 ) 8011330: 633b str r3, [r7, #48] @ 0x30 break; 8011332: e089 b.n 8011448 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8011334: 6afb ldr r3, [r7, #44] @ 0x2c 8011336: 0c9b lsrs r3, r3, #18 8011338: f003 020f and.w r2, r3, #15 801133c: 4b47 ldr r3, [pc, #284] @ (801145c ) 801133e: 5c9b ldrb r3, [r3, r2] 8011340: 627b str r3, [r7, #36] @ 0x24 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8011342: 6afb ldr r3, [r7, #44] @ 0x2c 8011344: f403 3380 and.w r3, r3, #65536 @ 0x10000 8011348: 2b00 cmp r3, #0 801134a: d072 beq.n 8011432 { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 801134c: 4b41 ldr r3, [pc, #260] @ (8011454 ) 801134e: 6adb ldr r3, [r3, #44] @ 0x2c 8011350: f003 020f and.w r2, r3, #15 8011354: 4b42 ldr r3, [pc, #264] @ (8011460 ) 8011356: 5c9b ldrb r3, [r3, r2] 8011358: 62bb str r3, [r7, #40] @ 0x28 #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /*RCC_CFGR2_PREDIV1*/ #if defined(RCC_CFGR2_PREDIV1SRC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 801135a: 4b3e ldr r3, [pc, #248] @ (8011454 ) 801135c: 6adb ldr r3, [r3, #44] @ 0x2c 801135e: f403 3380 and.w r3, r3, #65536 @ 0x10000 8011362: 2b00 cmp r3, #0 8011364: d053 beq.n 801140e { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8011366: 4b3b ldr r3, [pc, #236] @ (8011454 ) 8011368: 6adb ldr r3, [r3, #44] @ 0x2c 801136a: 091b lsrs r3, r3, #4 801136c: f003 030f and.w r3, r3, #15 8011370: 3301 adds r3, #1 8011372: 623b str r3, [r7, #32] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 8011374: 4b37 ldr r3, [pc, #220] @ (8011454 ) 8011376: 6adb ldr r3, [r3, #44] @ 0x2c 8011378: 0a1b lsrs r3, r3, #8 801137a: f003 030f and.w r3, r3, #15 801137e: 3302 adds r3, #2 8011380: 61fb str r3, [r7, #28] pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); 8011382: 69fb ldr r3, [r7, #28] 8011384: 2200 movs r2, #0 8011386: 469a mov sl, r3 8011388: 4693 mov fp, r2 801138a: 6a7b ldr r3, [r7, #36] @ 0x24 801138c: 2200 movs r2, #0 801138e: 613b str r3, [r7, #16] 8011390: 617a str r2, [r7, #20] 8011392: 693b ldr r3, [r7, #16] 8011394: fb03 f20b mul.w r2, r3, fp 8011398: 697b ldr r3, [r7, #20] 801139a: fb0a f303 mul.w r3, sl, r3 801139e: 4413 add r3, r2 80113a0: 693a ldr r2, [r7, #16] 80113a2: fbaa 0102 umull r0, r1, sl, r2 80113a6: 440b add r3, r1 80113a8: 4619 mov r1, r3 80113aa: 4b2b ldr r3, [pc, #172] @ (8011458 ) 80113ac: fb03 f201 mul.w r2, r3, r1 80113b0: 2300 movs r3, #0 80113b2: fb00 f303 mul.w r3, r0, r3 80113b6: 4413 add r3, r2 80113b8: 4a27 ldr r2, [pc, #156] @ (8011458 ) 80113ba: fba0 4502 umull r4, r5, r0, r2 80113be: 442b add r3, r5 80113c0: 461d mov r5, r3 80113c2: 6a3b ldr r3, [r7, #32] 80113c4: 2200 movs r2, #0 80113c6: 60bb str r3, [r7, #8] 80113c8: 60fa str r2, [r7, #12] 80113ca: 6abb ldr r3, [r7, #40] @ 0x28 80113cc: 2200 movs r2, #0 80113ce: 603b str r3, [r7, #0] 80113d0: 607a str r2, [r7, #4] 80113d2: e9d7 0102 ldrd r0, r1, [r7, #8] 80113d6: 460b mov r3, r1 80113d8: e9d7 ab00 ldrd sl, fp, [r7] 80113dc: 4652 mov r2, sl 80113de: fb02 f203 mul.w r2, r2, r3 80113e2: 465b mov r3, fp 80113e4: 4684 mov ip, r0 80113e6: fb0c f303 mul.w r3, ip, r3 80113ea: 4413 add r3, r2 80113ec: 4602 mov r2, r0 80113ee: 4651 mov r1, sl 80113f0: fba2 8901 umull r8, r9, r2, r1 80113f4: 444b add r3, r9 80113f6: 4699 mov r9, r3 80113f8: 4642 mov r2, r8 80113fa: 464b mov r3, r9 80113fc: 4620 mov r0, r4 80113fe: 4629 mov r1, r5 8011400: f7f7 fef8 bl 80091f4 <__aeabi_uldivmod> 8011404: 4602 mov r2, r0 8011406: 460b mov r3, r1 8011408: 4613 mov r3, r2 801140a: 637b str r3, [r7, #52] @ 0x34 801140c: e007 b.n 801141e } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 801140e: 6a7b ldr r3, [r7, #36] @ 0x24 8011410: 4a11 ldr r2, [pc, #68] @ (8011458 ) 8011412: fb03 f202 mul.w r2, r3, r2 8011416: 6abb ldr r3, [r7, #40] @ 0x28 8011418: fbb2 f3f3 udiv r3, r2, r3 801141c: 637b str r3, [r7, #52] @ 0x34 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 801141e: 4b0f ldr r3, [pc, #60] @ (801145c ) 8011420: 7b5b ldrb r3, [r3, #13] 8011422: 461a mov r2, r3 8011424: 6a7b ldr r3, [r7, #36] @ 0x24 8011426: 4293 cmp r3, r2 8011428: d108 bne.n 801143c { pllclk = pllclk / 2; 801142a: 6b7b ldr r3, [r7, #52] @ 0x34 801142c: 085b lsrs r3, r3, #1 801142e: 637b str r3, [r7, #52] @ 0x34 8011430: e004 b.n 801143c #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8011432: 6a7b ldr r3, [r7, #36] @ 0x24 8011434: 4a0b ldr r2, [pc, #44] @ (8011464 ) 8011436: fb02 f303 mul.w r3, r2, r3 801143a: 637b str r3, [r7, #52] @ 0x34 } sysclockfreq = pllclk; 801143c: 6b7b ldr r3, [r7, #52] @ 0x34 801143e: 633b str r3, [r7, #48] @ 0x30 break; 8011440: e002 b.n 8011448 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 8011442: 4b09 ldr r3, [pc, #36] @ (8011468 ) 8011444: 633b str r3, [r7, #48] @ 0x30 break; 8011446: bf00 nop } } return sysclockfreq; 8011448: 6b3b ldr r3, [r7, #48] @ 0x30 } 801144a: 4618 mov r0, r3 801144c: 3738 adds r7, #56 @ 0x38 801144e: 46bd mov sp, r7 8011450: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8011454: 40021000 .word 0x40021000 8011458: 017d7840 .word 0x017d7840 801145c: 0801723c .word 0x0801723c 8011460: 0801724c .word 0x0801724c 8011464: 003d0900 .word 0x003d0900 8011468: 007a1200 .word 0x007a1200 0801146c : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 801146c: b480 push {r7} 801146e: af00 add r7, sp, #0 return SystemCoreClock; 8011470: 4b02 ldr r3, [pc, #8] @ (801147c ) 8011472: 681b ldr r3, [r3, #0] } 8011474: 4618 mov r0, r3 8011476: 46bd mov sp, r7 8011478: bc80 pop {r7} 801147a: 4770 bx lr 801147c: 20000084 .word 0x20000084 08011480 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8011480: b580 push {r7, lr} 8011482: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8011484: f7ff fff2 bl 801146c 8011488: 4602 mov r2, r0 801148a: 4b05 ldr r3, [pc, #20] @ (80114a0 ) 801148c: 685b ldr r3, [r3, #4] 801148e: 0a1b lsrs r3, r3, #8 8011490: f003 0307 and.w r3, r3, #7 8011494: 4903 ldr r1, [pc, #12] @ (80114a4 ) 8011496: 5ccb ldrb r3, [r1, r3] 8011498: fa22 f303 lsr.w r3, r2, r3 } 801149c: 4618 mov r0, r3 801149e: bd80 pop {r7, pc} 80114a0: 40021000 .word 0x40021000 80114a4: 08017234 .word 0x08017234 080114a8 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 80114a8: b580 push {r7, lr} 80114aa: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 80114ac: f7ff ffde bl 801146c 80114b0: 4602 mov r2, r0 80114b2: 4b05 ldr r3, [pc, #20] @ (80114c8 ) 80114b4: 685b ldr r3, [r3, #4] 80114b6: 0adb lsrs r3, r3, #11 80114b8: f003 0307 and.w r3, r3, #7 80114bc: 4903 ldr r1, [pc, #12] @ (80114cc ) 80114be: 5ccb ldrb r3, [r1, r3] 80114c0: fa22 f303 lsr.w r3, r2, r3 } 80114c4: 4618 mov r0, r3 80114c6: bd80 pop {r7, pc} 80114c8: 40021000 .word 0x40021000 80114cc: 08017234 .word 0x08017234 080114d0 : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 80114d0: b480 push {r7} 80114d2: b085 sub sp, #20 80114d4: af00 add r7, sp, #0 80114d6: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 80114d8: 4b0a ldr r3, [pc, #40] @ (8011504 ) 80114da: 681b ldr r3, [r3, #0] 80114dc: 4a0a ldr r2, [pc, #40] @ (8011508 ) 80114de: fba2 2303 umull r2, r3, r2, r3 80114e2: 0a5b lsrs r3, r3, #9 80114e4: 687a ldr r2, [r7, #4] 80114e6: fb02 f303 mul.w r3, r2, r3 80114ea: 60fb str r3, [r7, #12] do { __NOP(); 80114ec: bf00 nop } while (Delay --); 80114ee: 68fb ldr r3, [r7, #12] 80114f0: 1e5a subs r2, r3, #1 80114f2: 60fa str r2, [r7, #12] 80114f4: 2b00 cmp r3, #0 80114f6: d1f9 bne.n 80114ec } 80114f8: bf00 nop 80114fa: bf00 nop 80114fc: 3714 adds r7, #20 80114fe: 46bd mov sp, r7 8011500: bc80 pop {r7} 8011502: 4770 bx lr 8011504: 20000084 .word 0x20000084 8011508: 10624dd3 .word 0x10624dd3 0801150c : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 801150c: b580 push {r7, lr} 801150e: b088 sub sp, #32 8011510: af00 add r7, sp, #0 8011512: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 8011514: 2300 movs r3, #0 8011516: 617b str r3, [r7, #20] 8011518: 2300 movs r3, #0 801151a: 613b str r3, [r7, #16] #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t pllactive = 0U; 801151c: 2300 movs r3, #0 801151e: 61fb str r3, [r7, #28] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 8011520: 687b ldr r3, [r7, #4] 8011522: 681b ldr r3, [r3, #0] 8011524: f003 0301 and.w r3, r3, #1 8011528: 2b00 cmp r3, #0 801152a: d07d beq.n 8011628 { FlagStatus pwrclkchanged = RESET; 801152c: 2300 movs r3, #0 801152e: 76fb strb r3, [r7, #27] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8011530: 4b8b ldr r3, [pc, #556] @ (8011760 ) 8011532: 69db ldr r3, [r3, #28] 8011534: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011538: 2b00 cmp r3, #0 801153a: d10d bne.n 8011558 { __HAL_RCC_PWR_CLK_ENABLE(); 801153c: 4b88 ldr r3, [pc, #544] @ (8011760 ) 801153e: 69db ldr r3, [r3, #28] 8011540: 4a87 ldr r2, [pc, #540] @ (8011760 ) 8011542: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8011546: 61d3 str r3, [r2, #28] 8011548: 4b85 ldr r3, [pc, #532] @ (8011760 ) 801154a: 69db ldr r3, [r3, #28] 801154c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011550: 60fb str r3, [r7, #12] 8011552: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 8011554: 2301 movs r3, #1 8011556: 76fb strb r3, [r7, #27] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8011558: 4b82 ldr r3, [pc, #520] @ (8011764 ) 801155a: 681b ldr r3, [r3, #0] 801155c: f403 7380 and.w r3, r3, #256 @ 0x100 8011560: 2b00 cmp r3, #0 8011562: d118 bne.n 8011596 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8011564: 4b7f ldr r3, [pc, #508] @ (8011764 ) 8011566: 681b ldr r3, [r3, #0] 8011568: 4a7e ldr r2, [pc, #504] @ (8011764 ) 801156a: f443 7380 orr.w r3, r3, #256 @ 0x100 801156e: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8011570: f7fc fd50 bl 800e014 8011574: 6178 str r0, [r7, #20] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8011576: e008 b.n 801158a { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8011578: f7fc fd4c bl 800e014 801157c: 4602 mov r2, r0 801157e: 697b ldr r3, [r7, #20] 8011580: 1ad3 subs r3, r2, r3 8011582: 2b64 cmp r3, #100 @ 0x64 8011584: d901 bls.n 801158a { return HAL_TIMEOUT; 8011586: 2303 movs r3, #3 8011588: e0e5 b.n 8011756 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 801158a: 4b76 ldr r3, [pc, #472] @ (8011764 ) 801158c: 681b ldr r3, [r3, #0] 801158e: f403 7380 and.w r3, r3, #256 @ 0x100 8011592: 2b00 cmp r3, #0 8011594: d0f0 beq.n 8011578 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 8011596: 4b72 ldr r3, [pc, #456] @ (8011760 ) 8011598: 6a1b ldr r3, [r3, #32] 801159a: f403 7340 and.w r3, r3, #768 @ 0x300 801159e: 613b str r3, [r7, #16] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 80115a0: 693b ldr r3, [r7, #16] 80115a2: 2b00 cmp r3, #0 80115a4: d02e beq.n 8011604 80115a6: 687b ldr r3, [r7, #4] 80115a8: 685b ldr r3, [r3, #4] 80115aa: f403 7340 and.w r3, r3, #768 @ 0x300 80115ae: 693a ldr r2, [r7, #16] 80115b0: 429a cmp r2, r3 80115b2: d027 beq.n 8011604 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 80115b4: 4b6a ldr r3, [pc, #424] @ (8011760 ) 80115b6: 6a1b ldr r3, [r3, #32] 80115b8: f423 7340 bic.w r3, r3, #768 @ 0x300 80115bc: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80115be: 4b6a ldr r3, [pc, #424] @ (8011768 ) 80115c0: 2201 movs r2, #1 80115c2: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 80115c4: 4b68 ldr r3, [pc, #416] @ (8011768 ) 80115c6: 2200 movs r2, #0 80115c8: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 80115ca: 4a65 ldr r2, [pc, #404] @ (8011760 ) 80115cc: 693b ldr r3, [r7, #16] 80115ce: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 80115d0: 693b ldr r3, [r7, #16] 80115d2: f003 0301 and.w r3, r3, #1 80115d6: 2b00 cmp r3, #0 80115d8: d014 beq.n 8011604 { /* Get Start Tick */ tickstart = HAL_GetTick(); 80115da: f7fc fd1b bl 800e014 80115de: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80115e0: e00a b.n 80115f8 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80115e2: f7fc fd17 bl 800e014 80115e6: 4602 mov r2, r0 80115e8: 697b ldr r3, [r7, #20] 80115ea: 1ad3 subs r3, r2, r3 80115ec: f241 3288 movw r2, #5000 @ 0x1388 80115f0: 4293 cmp r3, r2 80115f2: d901 bls.n 80115f8 { return HAL_TIMEOUT; 80115f4: 2303 movs r3, #3 80115f6: e0ae b.n 8011756 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80115f8: 4b59 ldr r3, [pc, #356] @ (8011760 ) 80115fa: 6a1b ldr r3, [r3, #32] 80115fc: f003 0302 and.w r3, r3, #2 8011600: 2b00 cmp r3, #0 8011602: d0ee beq.n 80115e2 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8011604: 4b56 ldr r3, [pc, #344] @ (8011760 ) 8011606: 6a1b ldr r3, [r3, #32] 8011608: f423 7240 bic.w r2, r3, #768 @ 0x300 801160c: 687b ldr r3, [r7, #4] 801160e: 685b ldr r3, [r3, #4] 8011610: 4953 ldr r1, [pc, #332] @ (8011760 ) 8011612: 4313 orrs r3, r2 8011614: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8011616: 7efb ldrb r3, [r7, #27] 8011618: 2b01 cmp r3, #1 801161a: d105 bne.n 8011628 { __HAL_RCC_PWR_CLK_DISABLE(); 801161c: 4b50 ldr r3, [pc, #320] @ (8011760 ) 801161e: 69db ldr r3, [r3, #28] 8011620: 4a4f ldr r2, [pc, #316] @ (8011760 ) 8011622: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8011626: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8011628: 687b ldr r3, [r7, #4] 801162a: 681b ldr r3, [r3, #0] 801162c: f003 0302 and.w r3, r3, #2 8011630: 2b00 cmp r3, #0 8011632: d008 beq.n 8011646 { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8011634: 4b4a ldr r3, [pc, #296] @ (8011760 ) 8011636: 685b ldr r3, [r3, #4] 8011638: f423 4240 bic.w r2, r3, #49152 @ 0xc000 801163c: 687b ldr r3, [r7, #4] 801163e: 689b ldr r3, [r3, #8] 8011640: 4947 ldr r1, [pc, #284] @ (8011760 ) 8011642: 4313 orrs r3, r2 8011644: 604b str r3, [r1, #4] } #if defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ I2S2 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) 8011646: 687b ldr r3, [r7, #4] 8011648: 681b ldr r3, [r3, #0] 801164a: f003 0304 and.w r3, r3, #4 801164e: 2b00 cmp r3, #0 8011650: d008 beq.n 8011664 { /* Check the parameters */ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); /* Configure the I2S2 clock source */ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); 8011652: 4b43 ldr r3, [pc, #268] @ (8011760 ) 8011654: 6adb ldr r3, [r3, #44] @ 0x2c 8011656: f423 3200 bic.w r2, r3, #131072 @ 0x20000 801165a: 687b ldr r3, [r7, #4] 801165c: 68db ldr r3, [r3, #12] 801165e: 4940 ldr r1, [pc, #256] @ (8011760 ) 8011660: 4313 orrs r3, r2 8011662: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ I2S3 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) 8011664: 687b ldr r3, [r7, #4] 8011666: 681b ldr r3, [r3, #0] 8011668: f003 0308 and.w r3, r3, #8 801166c: 2b00 cmp r3, #0 801166e: d008 beq.n 8011682 { /* Check the parameters */ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); /* Configure the I2S3 clock source */ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); 8011670: 4b3b ldr r3, [pc, #236] @ (8011760 ) 8011672: 6adb ldr r3, [r3, #44] @ 0x2c 8011674: f423 2280 bic.w r2, r3, #262144 @ 0x40000 8011678: 687b ldr r3, [r7, #4] 801167a: 691b ldr r3, [r3, #16] 801167c: 4938 ldr r1, [pc, #224] @ (8011760 ) 801167e: 4313 orrs r3, r2 8011680: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ PLL I2S Configuration ----------------------*/ /* Check that PLLI2S need to be enabled */ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) 8011682: 4b37 ldr r3, [pc, #220] @ (8011760 ) 8011684: 6adb ldr r3, [r3, #44] @ 0x2c 8011686: f403 3300 and.w r3, r3, #131072 @ 0x20000 801168a: 2b00 cmp r3, #0 801168c: d105 bne.n 801169a 801168e: 4b34 ldr r3, [pc, #208] @ (8011760 ) 8011690: 6adb ldr r3, [r3, #44] @ 0x2c 8011692: f403 2380 and.w r3, r3, #262144 @ 0x40000 8011696: 2b00 cmp r3, #0 8011698: d001 beq.n 801169e { /* Update flag to indicate that PLL I2S should be active */ pllactive = 1; 801169a: 2301 movs r3, #1 801169c: 61fb str r3, [r7, #28] } /* Check if PLL I2S need to be enabled */ if (pllactive == 1) 801169e: 69fb ldr r3, [r7, #28] 80116a0: 2b01 cmp r3, #1 80116a2: d148 bne.n 8011736 { /* Enable PLL I2S only if not active */ if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) 80116a4: 4b2e ldr r3, [pc, #184] @ (8011760 ) 80116a6: 681b ldr r3, [r3, #0] 80116a8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80116ac: 2b00 cmp r3, #0 80116ae: d138 bne.n 8011722 assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); /* Prediv2 can be written only when the PLL2 is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 80116b0: 4b2b ldr r3, [pc, #172] @ (8011760 ) 80116b2: 681b ldr r3, [r3, #0] 80116b4: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 80116b8: 2b00 cmp r3, #0 80116ba: d009 beq.n 80116d0 (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) 80116bc: 4b28 ldr r3, [pc, #160] @ (8011760 ) 80116be: 6adb ldr r3, [r3, #44] @ 0x2c 80116c0: f003 02f0 and.w r2, r3, #240 @ 0xf0 80116c4: 687b ldr r3, [r7, #4] 80116c6: 699b ldr r3, [r3, #24] if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 80116c8: 429a cmp r2, r3 80116ca: d001 beq.n 80116d0 { return HAL_ERROR; 80116cc: 2301 movs r3, #1 80116ce: e042 b.n 8011756 } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); 80116d0: 4b23 ldr r3, [pc, #140] @ (8011760 ) 80116d2: 6adb ldr r3, [r3, #44] @ 0x2c 80116d4: f023 02f0 bic.w r2, r3, #240 @ 0xf0 80116d8: 687b ldr r3, [r7, #4] 80116da: 699b ldr r3, [r3, #24] 80116dc: 4920 ldr r1, [pc, #128] @ (8011760 ) 80116de: 4313 orrs r3, r2 80116e0: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); 80116e2: 4b1f ldr r3, [pc, #124] @ (8011760 ) 80116e4: 6adb ldr r3, [r3, #44] @ 0x2c 80116e6: f423 4270 bic.w r2, r3, #61440 @ 0xf000 80116ea: 687b ldr r3, [r7, #4] 80116ec: 695b ldr r3, [r3, #20] 80116ee: 491c ldr r1, [pc, #112] @ (8011760 ) 80116f0: 4313 orrs r3, r2 80116f2: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); 80116f4: 4b1d ldr r3, [pc, #116] @ (801176c ) 80116f6: 2201 movs r2, #1 80116f8: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80116fa: f7fc fc8b bl 800e014 80116fe: 6178 str r0, [r7, #20] /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8011700: e008 b.n 8011714 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8011702: f7fc fc87 bl 800e014 8011706: 4602 mov r2, r0 8011708: 697b ldr r3, [r7, #20] 801170a: 1ad3 subs r3, r2, r3 801170c: 2b64 cmp r3, #100 @ 0x64 801170e: d901 bls.n 8011714 { return HAL_TIMEOUT; 8011710: 2303 movs r3, #3 8011712: e020 b.n 8011756 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8011714: 4b12 ldr r3, [pc, #72] @ (8011760 ) 8011716: 681b ldr r3, [r3, #0] 8011718: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 801171c: 2b00 cmp r3, #0 801171e: d0f0 beq.n 8011702 8011720: e009 b.n 8011736 } } else { /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) 8011722: 4b0f ldr r3, [pc, #60] @ (8011760 ) 8011724: 6adb ldr r3, [r3, #44] @ 0x2c 8011726: f403 4270 and.w r2, r3, #61440 @ 0xf000 801172a: 687b ldr r3, [r7, #4] 801172c: 695b ldr r3, [r3, #20] 801172e: 429a cmp r2, r3 8011730: d001 beq.n 8011736 { return HAL_ERROR; 8011732: 2301 movs r3, #1 8011734: e00f b.n 8011756 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8011736: 687b ldr r3, [r7, #4] 8011738: 681b ldr r3, [r3, #0] 801173a: f003 0310 and.w r3, r3, #16 801173e: 2b00 cmp r3, #0 8011740: d008 beq.n 8011754 { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8011742: 4b07 ldr r3, [pc, #28] @ (8011760 ) 8011744: 685b ldr r3, [r3, #4] 8011746: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 801174a: 687b ldr r3, [r7, #4] 801174c: 69db ldr r3, [r3, #28] 801174e: 4904 ldr r1, [pc, #16] @ (8011760 ) 8011750: 4313 orrs r3, r2 8011752: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 8011754: 2300 movs r3, #0 } 8011756: 4618 mov r0, r3 8011758: 3720 adds r7, #32 801175a: 46bd mov sp, r7 801175c: bd80 pop {r7, pc} 801175e: bf00 nop 8011760: 40021000 .word 0x40021000 8011764: 40007000 .word 0x40007000 8011768: 42420440 .word 0x42420440 801176c: 42420070 .word 0x42420070 08011770 : * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 8011770: b580 push {r7, lr} 8011772: b08a sub sp, #40 @ 0x28 8011774: af00 add r7, sp, #0 8011776: 6078 str r0, [r7, #4] #if defined(STM32F105xC) || defined(STM32F107xC) static const uint8_t aPLLMULFactorTable[14U] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; 8011778: 2300 movs r3, #0 801177a: 61fb str r3, [r7, #28] 801177c: 2300 movs r3, #0 801177e: 627b str r3, [r7, #36] @ 0x24 8011780: 2300 movs r3, #0 8011782: 61bb str r3, [r7, #24] uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; 8011784: 2300 movs r3, #0 8011786: 617b str r3, [r7, #20] 8011788: 2300 movs r3, #0 801178a: 613b str r3, [r7, #16] 801178c: 2300 movs r3, #0 801178e: 60fb str r3, [r7, #12] static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; static const uint8_t aPredivFactorTable[2U] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 8011790: 2300 movs r3, #0 8011792: 60bb str r3, [r7, #8] 8011794: 2300 movs r3, #0 8011796: 623b str r3, [r7, #32] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 8011798: 687b ldr r3, [r7, #4] 801179a: 3b01 subs r3, #1 801179c: 2b0f cmp r3, #15 801179e: f200 811d bhi.w 80119dc 80117a2: a201 add r2, pc, #4 @ (adr r2, 80117a8 ) 80117a4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80117a8: 0801195d .word 0x0801195d 80117ac: 080119c1 .word 0x080119c1 80117b0: 080119dd .word 0x080119dd 80117b4: 080118bb .word 0x080118bb 80117b8: 080119dd .word 0x080119dd 80117bc: 080119dd .word 0x080119dd 80117c0: 080119dd .word 0x080119dd 80117c4: 0801190d .word 0x0801190d 80117c8: 080119dd .word 0x080119dd 80117cc: 080119dd .word 0x080119dd 80117d0: 080119dd .word 0x080119dd 80117d4: 080119dd .word 0x080119dd 80117d8: 080119dd .word 0x080119dd 80117dc: 080119dd .word 0x080119dd 80117e0: 080119dd .word 0x080119dd 80117e4: 080117e9 .word 0x080117e9 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) case RCC_PERIPHCLK_USB: { /* Get RCC configuration ------------------------------------------------------*/ temp_reg = RCC->CFGR; 80117e8: 4b83 ldr r3, [pc, #524] @ (80119f8 ) 80117ea: 685b ldr r3, [r3, #4] 80117ec: 60bb str r3, [r7, #8] /* Check if PLL is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) 80117ee: 4b82 ldr r3, [pc, #520] @ (80119f8 ) 80117f0: 681b ldr r3, [r3, #0] 80117f2: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80117f6: 2b00 cmp r3, #0 80117f8: f000 80f2 beq.w 80119e0 { pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 80117fc: 68bb ldr r3, [r7, #8] 80117fe: 0c9b lsrs r3, r3, #18 8011800: f003 030f and.w r3, r3, #15 8011804: 4a7d ldr r2, [pc, #500] @ (80119fc ) 8011806: 5cd3 ldrb r3, [r2, r3] 8011808: 61bb str r3, [r7, #24] if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 801180a: 68bb ldr r3, [r7, #8] 801180c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8011810: 2b00 cmp r3, #0 8011812: d03b beq.n 801188c { #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ || defined(STM32F100xE) prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 8011814: 4b78 ldr r3, [pc, #480] @ (80119f8 ) 8011816: 6adb ldr r3, [r3, #44] @ 0x2c 8011818: f003 030f and.w r3, r3, #15 801181c: 4a78 ldr r2, [pc, #480] @ (8011a00 ) 801181e: 5cd3 ldrb r3, [r2, r3] 8011820: 61fb str r3, [r7, #28] #else prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 8011822: 4b75 ldr r3, [pc, #468] @ (80119f8 ) 8011824: 6adb ldr r3, [r3, #44] @ 0x2c 8011826: f403 3380 and.w r3, r3, #65536 @ 0x10000 801182a: 2b00 cmp r3, #0 801182c: d01c beq.n 8011868 { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 801182e: 4b72 ldr r3, [pc, #456] @ (80119f8 ) 8011830: 6adb ldr r3, [r3, #44] @ 0x2c 8011832: 091b lsrs r3, r3, #4 8011834: f003 030f and.w r3, r3, #15 8011838: 3301 adds r3, #1 801183a: 60fb str r3, [r7, #12] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 801183c: 4b6e ldr r3, [pc, #440] @ (80119f8 ) 801183e: 6adb ldr r3, [r3, #44] @ 0x2c 8011840: 0a1b lsrs r3, r3, #8 8011842: f003 030f and.w r3, r3, #15 8011846: 3302 adds r3, #2 8011848: 617b str r3, [r7, #20] pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); 801184a: 4a6e ldr r2, [pc, #440] @ (8011a04 ) 801184c: 68fb ldr r3, [r7, #12] 801184e: fbb2 f3f3 udiv r3, r2, r3 8011852: 697a ldr r2, [r7, #20] 8011854: fb03 f202 mul.w r2, r3, r2 8011858: 69fb ldr r3, [r7, #28] 801185a: fbb2 f2f3 udiv r2, r2, r3 801185e: 69bb ldr r3, [r7, #24] 8011860: fb02 f303 mul.w r3, r2, r3 8011864: 627b str r3, [r7, #36] @ 0x24 8011866: e007 b.n 8011878 } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); 8011868: 4a66 ldr r2, [pc, #408] @ (8011a04 ) 801186a: 69fb ldr r3, [r7, #28] 801186c: fbb2 f2f3 udiv r2, r2, r3 8011870: 69bb ldr r3, [r7, #24] 8011872: fb02 f303 mul.w r3, r2, r3 8011876: 627b str r3, [r7, #36] @ 0x24 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 8011878: 4b60 ldr r3, [pc, #384] @ (80119fc ) 801187a: 7b5b ldrb r3, [r3, #13] 801187c: 461a mov r2, r3 801187e: 69bb ldr r3, [r7, #24] 8011880: 4293 cmp r3, r2 8011882: d108 bne.n 8011896 { pllclk = pllclk / 2; 8011884: 6a7b ldr r3, [r7, #36] @ 0x24 8011886: 085b lsrs r3, r3, #1 8011888: 627b str r3, [r7, #36] @ 0x24 801188a: e004 b.n 8011896 #endif /* STM32F105xC || STM32F107xC */ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 801188c: 69bb ldr r3, [r7, #24] 801188e: 4a5e ldr r2, [pc, #376] @ (8011a08 ) 8011890: fb02 f303 mul.w r3, r2, r3 8011894: 627b str r3, [r7, #36] @ 0x24 } /* Calcul of the USB frequency*/ #if defined(STM32F105xC) || defined(STM32F107xC) /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) 8011896: 4b58 ldr r3, [pc, #352] @ (80119f8 ) 8011898: 685b ldr r3, [r3, #4] 801189a: f403 0380 and.w r3, r3, #4194304 @ 0x400000 801189e: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 80118a2: d102 bne.n 80118aa { /* Prescaler of 2 selected for USB */ frequency = pllclk; 80118a4: 6a7b ldr r3, [r7, #36] @ 0x24 80118a6: 623b str r3, [r7, #32] /* Prescaler of 1.5 selected for USB */ frequency = (pllclk * 2) / 3; } #endif } break; 80118a8: e09a b.n 80119e0 frequency = (2 * pllclk) / 3; 80118aa: 6a7b ldr r3, [r7, #36] @ 0x24 80118ac: 005b lsls r3, r3, #1 80118ae: 4a57 ldr r2, [pc, #348] @ (8011a0c ) 80118b0: fba2 2303 umull r2, r3, r2, r3 80118b4: 085b lsrs r3, r3, #1 80118b6: 623b str r3, [r7, #32] break; 80118b8: e092 b.n 80119e0 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) 80118ba: 4b4f ldr r3, [pc, #316] @ (80119f8 ) 80118bc: 6adb ldr r3, [r3, #44] @ 0x2c 80118be: f403 3300 and.w r3, r3, #131072 @ 0x20000 80118c2: 2b00 cmp r3, #0 80118c4: d103 bne.n 80118ce { /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); 80118c6: f7ff fd15 bl 80112f4 80118ca: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 80118cc: e08a b.n 80119e4 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 80118ce: 4b4a ldr r3, [pc, #296] @ (80119f8 ) 80118d0: 681b ldr r3, [r3, #0] 80118d2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80118d6: 2b00 cmp r3, #0 80118d8: f000 8084 beq.w 80119e4 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 80118dc: 4b46 ldr r3, [pc, #280] @ (80119f8 ) 80118de: 6adb ldr r3, [r3, #44] @ 0x2c 80118e0: 091b lsrs r3, r3, #4 80118e2: f003 030f and.w r3, r3, #15 80118e6: 3301 adds r3, #1 80118e8: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 80118ea: 4b43 ldr r3, [pc, #268] @ (80119f8 ) 80118ec: 6adb ldr r3, [r3, #44] @ 0x2c 80118ee: 0b1b lsrs r3, r3, #12 80118f0: f003 030f and.w r3, r3, #15 80118f4: 3302 adds r3, #2 80118f6: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 80118f8: 4a42 ldr r2, [pc, #264] @ (8011a04 ) 80118fa: 68fb ldr r3, [r7, #12] 80118fc: fbb2 f3f3 udiv r3, r2, r3 8011900: 693a ldr r2, [r7, #16] 8011902: fb02 f303 mul.w r3, r2, r3 8011906: 005b lsls r3, r3, #1 8011908: 623b str r3, [r7, #32] break; 801190a: e06b b.n 80119e4 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) 801190c: 4b3a ldr r3, [pc, #232] @ (80119f8 ) 801190e: 6adb ldr r3, [r3, #44] @ 0x2c 8011910: f403 2380 and.w r3, r3, #262144 @ 0x40000 8011914: 2b00 cmp r3, #0 8011916: d103 bne.n 8011920 { /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); 8011918: f7ff fcec bl 80112f4 801191c: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 801191e: e063 b.n 80119e8 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8011920: 4b35 ldr r3, [pc, #212] @ (80119f8 ) 8011922: 681b ldr r3, [r3, #0] 8011924: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011928: 2b00 cmp r3, #0 801192a: d05d beq.n 80119e8 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 801192c: 4b32 ldr r3, [pc, #200] @ (80119f8 ) 801192e: 6adb ldr r3, [r3, #44] @ 0x2c 8011930: 091b lsrs r3, r3, #4 8011932: f003 030f and.w r3, r3, #15 8011936: 3301 adds r3, #1 8011938: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 801193a: 4b2f ldr r3, [pc, #188] @ (80119f8 ) 801193c: 6adb ldr r3, [r3, #44] @ 0x2c 801193e: 0b1b lsrs r3, r3, #12 8011940: f003 030f and.w r3, r3, #15 8011944: 3302 adds r3, #2 8011946: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 8011948: 4a2e ldr r2, [pc, #184] @ (8011a04 ) 801194a: 68fb ldr r3, [r7, #12] 801194c: fbb2 f3f3 udiv r3, r2, r3 8011950: 693a ldr r2, [r7, #16] 8011952: fb02 f303 mul.w r3, r2, r3 8011956: 005b lsls r3, r3, #1 8011958: 623b str r3, [r7, #32] break; 801195a: e045 b.n 80119e8 } #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ case RCC_PERIPHCLK_RTC: { /* Get RCC BDCR configuration ------------------------------------------------------*/ temp_reg = RCC->BDCR; 801195c: 4b26 ldr r3, [pc, #152] @ (80119f8 ) 801195e: 6a1b ldr r3, [r3, #32] 8011960: 60bb str r3, [r7, #8] /* Check if LSE is ready if RTC clock selection is LSE */ if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 8011962: 68bb ldr r3, [r7, #8] 8011964: f403 7340 and.w r3, r3, #768 @ 0x300 8011968: f5b3 7f80 cmp.w r3, #256 @ 0x100 801196c: d108 bne.n 8011980 801196e: 68bb ldr r3, [r7, #8] 8011970: f003 0302 and.w r3, r3, #2 8011974: 2b00 cmp r3, #0 8011976: d003 beq.n 8011980 { frequency = LSE_VALUE; 8011978: f44f 4300 mov.w r3, #32768 @ 0x8000 801197c: 623b str r3, [r7, #32] 801197e: e01e b.n 80119be } /* Check if LSI is ready if RTC clock selection is LSI */ else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 8011980: 68bb ldr r3, [r7, #8] 8011982: f403 7340 and.w r3, r3, #768 @ 0x300 8011986: f5b3 7f00 cmp.w r3, #512 @ 0x200 801198a: d109 bne.n 80119a0 801198c: 4b1a ldr r3, [pc, #104] @ (80119f8 ) 801198e: 6a5b ldr r3, [r3, #36] @ 0x24 8011990: f003 0302 and.w r3, r3, #2 8011994: 2b00 cmp r3, #0 8011996: d003 beq.n 80119a0 { frequency = LSI_VALUE; 8011998: f649 4340 movw r3, #40000 @ 0x9c40 801199c: 623b str r3, [r7, #32] 801199e: e00e b.n 80119be } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 80119a0: 68bb ldr r3, [r7, #8] 80119a2: f403 7340 and.w r3, r3, #768 @ 0x300 80119a6: f5b3 7f40 cmp.w r3, #768 @ 0x300 80119aa: d11f bne.n 80119ec 80119ac: 4b12 ldr r3, [pc, #72] @ (80119f8 ) 80119ae: 681b ldr r3, [r3, #0] 80119b0: f403 3300 and.w r3, r3, #131072 @ 0x20000 80119b4: 2b00 cmp r3, #0 80119b6: d019 beq.n 80119ec { frequency = HSE_VALUE / 128U; 80119b8: 4b15 ldr r3, [pc, #84] @ (8011a10 ) 80119ba: 623b str r3, [r7, #32] /* Clock not enabled for RTC*/ else { /* nothing to do: frequency already initialized to 0U */ } break; 80119bc: e016 b.n 80119ec 80119be: e015 b.n 80119ec } case RCC_PERIPHCLK_ADC: { frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 80119c0: f7ff fd72 bl 80114a8 80119c4: 4602 mov r2, r0 80119c6: 4b0c ldr r3, [pc, #48] @ (80119f8 ) 80119c8: 685b ldr r3, [r3, #4] 80119ca: 0b9b lsrs r3, r3, #14 80119cc: f003 0303 and.w r3, r3, #3 80119d0: 3301 adds r3, #1 80119d2: 005b lsls r3, r3, #1 80119d4: fbb2 f3f3 udiv r3, r2, r3 80119d8: 623b str r3, [r7, #32] break; 80119da: e008 b.n 80119ee } default: { break; 80119dc: bf00 nop 80119de: e006 b.n 80119ee break; 80119e0: bf00 nop 80119e2: e004 b.n 80119ee break; 80119e4: bf00 nop 80119e6: e002 b.n 80119ee break; 80119e8: bf00 nop 80119ea: e000 b.n 80119ee break; 80119ec: bf00 nop } } return (frequency); 80119ee: 6a3b ldr r3, [r7, #32] } 80119f0: 4618 mov r0, r3 80119f2: 3728 adds r7, #40 @ 0x28 80119f4: 46bd mov sp, r7 80119f6: bd80 pop {r7, pc} 80119f8: 40021000 .word 0x40021000 80119fc: 0801725c .word 0x0801725c 8011a00: 0801726c .word 0x0801726c 8011a04: 017d7840 .word 0x017d7840 8011a08: 003d0900 .word 0x003d0900 8011a0c: aaaaaaab .word 0xaaaaaaab 8011a10: 0002faf0 .word 0x0002faf0 08011a14 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { 8011a14: b580 push {r7, lr} 8011a16: b084 sub sp, #16 8011a18: af00 add r7, sp, #0 8011a1a: 6078 str r0, [r7, #4] uint32_t prescaler = 0U; 8011a1c: 2300 movs r3, #0 8011a1e: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8011a20: 687b ldr r3, [r7, #4] 8011a22: 2b00 cmp r3, #0 8011a24: d101 bne.n 8011a2a { return HAL_ERROR; 8011a26: 2301 movs r3, #1 8011a28: e07a b.n 8011b20 { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } #else if (hrtc->State == HAL_RTC_STATE_RESET) 8011a2a: 687b ldr r3, [r7, #4] 8011a2c: 7c5b ldrb r3, [r3, #17] 8011a2e: b2db uxtb r3, r3 8011a30: 2b00 cmp r3, #0 8011a32: d105 bne.n 8011a40 { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; 8011a34: 687b ldr r3, [r7, #4] 8011a36: 2200 movs r2, #0 8011a38: 741a strb r2, [r3, #16] /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); 8011a3a: 6878 ldr r0, [r7, #4] 8011a3c: f7fa f818 bl 800ba70 } #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; 8011a40: 687b ldr r3, [r7, #4] 8011a42: 2202 movs r2, #2 8011a44: 745a strb r2, [r3, #17] /* Waiting for synchro */ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 8011a46: 6878 ldr r0, [r7, #4] 8011a48: f000 f870 bl 8011b2c 8011a4c: 4603 mov r3, r0 8011a4e: 2b00 cmp r3, #0 8011a50: d004 beq.n 8011a5c { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8011a52: 687b ldr r3, [r7, #4] 8011a54: 2204 movs r2, #4 8011a56: 745a strb r2, [r3, #17] return HAL_ERROR; 8011a58: 2301 movs r3, #1 8011a5a: e061 b.n 8011b20 } /* Set Initialization mode */ if (RTC_EnterInitMode(hrtc) != HAL_OK) 8011a5c: 6878 ldr r0, [r7, #4] 8011a5e: f000 f892 bl 8011b86 8011a62: 4603 mov r3, r0 8011a64: 2b00 cmp r3, #0 8011a66: d004 beq.n 8011a72 { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8011a68: 687b ldr r3, [r7, #4] 8011a6a: 2204 movs r2, #4 8011a6c: 745a strb r2, [r3, #17] return HAL_ERROR; 8011a6e: 2301 movs r3, #1 8011a70: e056 b.n 8011b20 } else { /* Clear Flags Bits */ CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC)); 8011a72: 687b ldr r3, [r7, #4] 8011a74: 681b ldr r3, [r3, #0] 8011a76: 685a ldr r2, [r3, #4] 8011a78: 687b ldr r3, [r7, #4] 8011a7a: 681b ldr r3, [r3, #0] 8011a7c: f022 0207 bic.w r2, r2, #7 8011a80: 605a str r2, [r3, #4] if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE) 8011a82: 687b ldr r3, [r7, #4] 8011a84: 689b ldr r3, [r3, #8] 8011a86: 2b00 cmp r3, #0 8011a88: d005 beq.n 8011a96 { /* Disable the selected Tamper pin */ CLEAR_BIT(BKP->CR, BKP_CR_TPE); 8011a8a: 4b27 ldr r3, [pc, #156] @ (8011b28 ) 8011a8c: 6b1b ldr r3, [r3, #48] @ 0x30 8011a8e: 4a26 ldr r2, [pc, #152] @ (8011b28 ) 8011a90: f023 0301 bic.w r3, r3, #1 8011a94: 6313 str r3, [r2, #48] @ 0x30 } /* Set the signal which will be routed to RTC Tamper pin*/ MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut); 8011a96: 4b24 ldr r3, [pc, #144] @ (8011b28 ) 8011a98: 6adb ldr r3, [r3, #44] @ 0x2c 8011a9a: f423 7260 bic.w r2, r3, #896 @ 0x380 8011a9e: 687b ldr r3, [r7, #4] 8011aa0: 689b ldr r3, [r3, #8] 8011aa2: 4921 ldr r1, [pc, #132] @ (8011b28 ) 8011aa4: 4313 orrs r3, r2 8011aa6: 62cb str r3, [r1, #44] @ 0x2c if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND) 8011aa8: 687b ldr r3, [r7, #4] 8011aaa: 685b ldr r3, [r3, #4] 8011aac: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8011ab0: d003 beq.n 8011aba { /* RTC Prescaler provided directly by end-user*/ prescaler = hrtc->Init.AsynchPrediv; 8011ab2: 687b ldr r3, [r7, #4] 8011ab4: 685b ldr r3, [r3, #4] 8011ab6: 60fb str r3, [r7, #12] 8011ab8: e00e b.n 8011ad8 } else { /* RTC Prescaler will be automatically calculated to get 1 second timebase */ /* Get the RTCCLK frequency */ prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); 8011aba: 2001 movs r0, #1 8011abc: f7ff fe58 bl 8011770 8011ac0: 60f8 str r0, [r7, #12] /* Check that RTC clock is enabled*/ if (prescaler == 0U) 8011ac2: 68fb ldr r3, [r7, #12] 8011ac4: 2b00 cmp r3, #0 8011ac6: d104 bne.n 8011ad2 { /* Should not happen. Frequency is not available*/ hrtc->State = HAL_RTC_STATE_ERROR; 8011ac8: 687b ldr r3, [r7, #4] 8011aca: 2204 movs r2, #4 8011acc: 745a strb r2, [r3, #17] return HAL_ERROR; 8011ace: 2301 movs r3, #1 8011ad0: e026 b.n 8011b20 } else { /* RTC period = RTCCLK/(RTC_PR + 1) */ prescaler = prescaler - 1U; 8011ad2: 68fb ldr r3, [r7, #12] 8011ad4: 3b01 subs r3, #1 8011ad6: 60fb str r3, [r7, #12] } } /* Configure the RTC_PRLH / RTC_PRLL */ WRITE_REG(hrtc->Instance->PRLH, ((prescaler >> 16U) & RTC_PRLH_PRL)); 8011ad8: 68fb ldr r3, [r7, #12] 8011ada: 0c1a lsrs r2, r3, #16 8011adc: 687b ldr r3, [r7, #4] 8011ade: 681b ldr r3, [r3, #0] 8011ae0: f002 020f and.w r2, r2, #15 8011ae4: 609a str r2, [r3, #8] WRITE_REG(hrtc->Instance->PRLL, (prescaler & RTC_PRLL_PRL)); 8011ae6: 687b ldr r3, [r7, #4] 8011ae8: 681b ldr r3, [r3, #0] 8011aea: 68fa ldr r2, [r7, #12] 8011aec: b292 uxth r2, r2 8011aee: 60da str r2, [r3, #12] /* Wait for synchro */ if (RTC_ExitInitMode(hrtc) != HAL_OK) 8011af0: 6878 ldr r0, [r7, #4] 8011af2: f000 f870 bl 8011bd6 8011af6: 4603 mov r3, r0 8011af8: 2b00 cmp r3, #0 8011afa: d004 beq.n 8011b06 { hrtc->State = HAL_RTC_STATE_ERROR; 8011afc: 687b ldr r3, [r7, #4] 8011afe: 2204 movs r2, #4 8011b00: 745a strb r2, [r3, #17] return HAL_ERROR; 8011b02: 2301 movs r3, #1 8011b04: e00c b.n 8011b20 } /* Initialize date to 1st of January 2000 */ hrtc->DateToUpdate.Year = 0x00U; 8011b06: 687b ldr r3, [r7, #4] 8011b08: 2200 movs r2, #0 8011b0a: 73da strb r2, [r3, #15] hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; 8011b0c: 687b ldr r3, [r7, #4] 8011b0e: 2201 movs r2, #1 8011b10: 735a strb r2, [r3, #13] hrtc->DateToUpdate.Date = 0x01U; 8011b12: 687b ldr r3, [r7, #4] 8011b14: 2201 movs r2, #1 8011b16: 739a strb r2, [r3, #14] /* Set RTC state */ hrtc->State = HAL_RTC_STATE_READY; 8011b18: 687b ldr r3, [r7, #4] 8011b1a: 2201 movs r2, #1 8011b1c: 745a strb r2, [r3, #17] return HAL_OK; 8011b1e: 2300 movs r3, #0 } } 8011b20: 4618 mov r0, r3 8011b22: 3710 adds r7, #16 8011b24: 46bd mov sp, r7 8011b26: bd80 pop {r7, pc} 8011b28: 40006c00 .word 0x40006c00 08011b2c : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { 8011b2c: b580 push {r7, lr} 8011b2e: b084 sub sp, #16 8011b30: af00 add r7, sp, #0 8011b32: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8011b34: 2300 movs r3, #0 8011b36: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8011b38: 687b ldr r3, [r7, #4] 8011b3a: 2b00 cmp r3, #0 8011b3c: d101 bne.n 8011b42 { return HAL_ERROR; 8011b3e: 2301 movs r3, #1 8011b40: e01d b.n 8011b7e } /* Clear RSF flag */ CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); 8011b42: 687b ldr r3, [r7, #4] 8011b44: 681b ldr r3, [r3, #0] 8011b46: 685a ldr r2, [r3, #4] 8011b48: 687b ldr r3, [r7, #4] 8011b4a: 681b ldr r3, [r3, #0] 8011b4c: f022 0208 bic.w r2, r2, #8 8011b50: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8011b52: f7fc fa5f bl 800e014 8011b56: 60f8 str r0, [r7, #12] /* Wait the registers to be synchronised */ while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8011b58: e009 b.n 8011b6e { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8011b5a: f7fc fa5b bl 800e014 8011b5e: 4602 mov r2, r0 8011b60: 68fb ldr r3, [r7, #12] 8011b62: 1ad3 subs r3, r2, r3 8011b64: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8011b68: d901 bls.n 8011b6e { return HAL_TIMEOUT; 8011b6a: 2303 movs r3, #3 8011b6c: e007 b.n 8011b7e while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8011b6e: 687b ldr r3, [r7, #4] 8011b70: 681b ldr r3, [r3, #0] 8011b72: 685b ldr r3, [r3, #4] 8011b74: f003 0308 and.w r3, r3, #8 8011b78: 2b00 cmp r3, #0 8011b7a: d0ee beq.n 8011b5a } } return HAL_OK; 8011b7c: 2300 movs r3, #0 } 8011b7e: 4618 mov r0, r3 8011b80: 3710 adds r7, #16 8011b82: 46bd mov sp, r7 8011b84: bd80 pop {r7, pc} 08011b86 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { 8011b86: b580 push {r7, lr} 8011b88: b084 sub sp, #16 8011b8a: af00 add r7, sp, #0 8011b8c: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8011b8e: 2300 movs r3, #0 8011b90: 60fb str r3, [r7, #12] tickstart = HAL_GetTick(); 8011b92: f7fc fa3f bl 800e014 8011b96: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8011b98: e009 b.n 8011bae { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8011b9a: f7fc fa3b bl 800e014 8011b9e: 4602 mov r2, r0 8011ba0: 68fb ldr r3, [r7, #12] 8011ba2: 1ad3 subs r3, r2, r3 8011ba4: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8011ba8: d901 bls.n 8011bae { return HAL_TIMEOUT; 8011baa: 2303 movs r3, #3 8011bac: e00f b.n 8011bce while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8011bae: 687b ldr r3, [r7, #4] 8011bb0: 681b ldr r3, [r3, #0] 8011bb2: 685b ldr r3, [r3, #4] 8011bb4: f003 0320 and.w r3, r3, #32 8011bb8: 2b00 cmp r3, #0 8011bba: d0ee beq.n 8011b9a } } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 8011bbc: 687b ldr r3, [r7, #4] 8011bbe: 681b ldr r3, [r3, #0] 8011bc0: 685a ldr r2, [r3, #4] 8011bc2: 687b ldr r3, [r7, #4] 8011bc4: 681b ldr r3, [r3, #0] 8011bc6: f042 0210 orr.w r2, r2, #16 8011bca: 605a str r2, [r3, #4] return HAL_OK; 8011bcc: 2300 movs r3, #0 } 8011bce: 4618 mov r0, r3 8011bd0: 3710 adds r7, #16 8011bd2: 46bd mov sp, r7 8011bd4: bd80 pop {r7, pc} 08011bd6 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) { 8011bd6: b580 push {r7, lr} 8011bd8: b084 sub sp, #16 8011bda: af00 add r7, sp, #0 8011bdc: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8011bde: 2300 movs r3, #0 8011be0: 60fb str r3, [r7, #12] /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 8011be2: 687b ldr r3, [r7, #4] 8011be4: 681b ldr r3, [r3, #0] 8011be6: 685a ldr r2, [r3, #4] 8011be8: 687b ldr r3, [r7, #4] 8011bea: 681b ldr r3, [r3, #0] 8011bec: f022 0210 bic.w r2, r2, #16 8011bf0: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8011bf2: f7fc fa0f bl 800e014 8011bf6: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8011bf8: e009 b.n 8011c0e { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8011bfa: f7fc fa0b bl 800e014 8011bfe: 4602 mov r2, r0 8011c00: 68fb ldr r3, [r7, #12] 8011c02: 1ad3 subs r3, r2, r3 8011c04: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8011c08: d901 bls.n 8011c0e { return HAL_TIMEOUT; 8011c0a: 2303 movs r3, #3 8011c0c: e007 b.n 8011c1e while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8011c0e: 687b ldr r3, [r7, #4] 8011c10: 681b ldr r3, [r3, #0] 8011c12: 685b ldr r3, [r3, #4] 8011c14: f003 0320 and.w r3, r3, #32 8011c18: 2b00 cmp r3, #0 8011c1a: d0ee beq.n 8011bfa } } return HAL_OK; 8011c1c: 2300 movs r3, #0 } 8011c1e: 4618 mov r0, r3 8011c20: 3710 adds r7, #16 8011c22: 46bd mov sp, r7 8011c24: bd80 pop {r7, pc} 08011c26 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8011c26: b580 push {r7, lr} 8011c28: b082 sub sp, #8 8011c2a: af00 add r7, sp, #0 8011c2c: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8011c2e: 687b ldr r3, [r7, #4] 8011c30: 2b00 cmp r3, #0 8011c32: d101 bne.n 8011c38 { return HAL_ERROR; 8011c34: 2301 movs r3, #1 8011c36: e041 b.n 8011cbc assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8011c38: 687b ldr r3, [r7, #4] 8011c3a: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8011c3e: b2db uxtb r3, r3 8011c40: 2b00 cmp r3, #0 8011c42: d106 bne.n 8011c52 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8011c44: 687b ldr r3, [r7, #4] 8011c46: 2200 movs r2, #0 8011c48: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8011c4c: 6878 ldr r0, [r7, #4] 8011c4e: f7fb fe67 bl 800d920 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8011c52: 687b ldr r3, [r7, #4] 8011c54: 2202 movs r2, #2 8011c56: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8011c5a: 687b ldr r3, [r7, #4] 8011c5c: 681a ldr r2, [r3, #0] 8011c5e: 687b ldr r3, [r7, #4] 8011c60: 3304 adds r3, #4 8011c62: 4619 mov r1, r3 8011c64: 4610 mov r0, r2 8011c66: f000 fd33 bl 80126d0 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8011c6a: 687b ldr r3, [r7, #4] 8011c6c: 2201 movs r2, #1 8011c6e: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011c72: 687b ldr r3, [r7, #4] 8011c74: 2201 movs r2, #1 8011c76: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011c7a: 687b ldr r3, [r7, #4] 8011c7c: 2201 movs r2, #1 8011c7e: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011c82: 687b ldr r3, [r7, #4] 8011c84: 2201 movs r2, #1 8011c86: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011c8a: 687b ldr r3, [r7, #4] 8011c8c: 2201 movs r2, #1 8011c8e: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011c92: 687b ldr r3, [r7, #4] 8011c94: 2201 movs r2, #1 8011c96: f883 2042 strb.w r2, [r3, #66] @ 0x42 8011c9a: 687b ldr r3, [r7, #4] 8011c9c: 2201 movs r2, #1 8011c9e: f883 2043 strb.w r2, [r3, #67] @ 0x43 8011ca2: 687b ldr r3, [r7, #4] 8011ca4: 2201 movs r2, #1 8011ca6: f883 2044 strb.w r2, [r3, #68] @ 0x44 8011caa: 687b ldr r3, [r7, #4] 8011cac: 2201 movs r2, #1 8011cae: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8011cb2: 687b ldr r3, [r7, #4] 8011cb4: 2201 movs r2, #1 8011cb6: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8011cba: 2300 movs r3, #0 } 8011cbc: 4618 mov r0, r3 8011cbe: 3708 adds r7, #8 8011cc0: 46bd mov sp, r7 8011cc2: bd80 pop {r7, pc} 08011cc4 : * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { 8011cc4: b580 push {r7, lr} 8011cc6: b082 sub sp, #8 8011cc8: af00 add r7, sp, #0 8011cca: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8011ccc: 687b ldr r3, [r7, #4] 8011cce: 2b00 cmp r3, #0 8011cd0: d101 bne.n 8011cd6 { return HAL_ERROR; 8011cd2: 2301 movs r3, #1 8011cd4: e041 b.n 8011d5a assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8011cd6: 687b ldr r3, [r7, #4] 8011cd8: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8011cdc: b2db uxtb r3, r3 8011cde: 2b00 cmp r3, #0 8011ce0: d106 bne.n 8011cf0 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8011ce2: 687b ldr r3, [r7, #4] 8011ce4: 2200 movs r2, #0 8011ce6: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); 8011cea: 6878 ldr r0, [r7, #4] 8011cec: f000 f839 bl 8011d62 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8011cf0: 687b ldr r3, [r7, #4] 8011cf2: 2202 movs r2, #2 8011cf4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8011cf8: 687b ldr r3, [r7, #4] 8011cfa: 681a ldr r2, [r3, #0] 8011cfc: 687b ldr r3, [r7, #4] 8011cfe: 3304 adds r3, #4 8011d00: 4619 mov r1, r3 8011d02: 4610 mov r0, r2 8011d04: f000 fce4 bl 80126d0 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8011d08: 687b ldr r3, [r7, #4] 8011d0a: 2201 movs r2, #1 8011d0c: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011d10: 687b ldr r3, [r7, #4] 8011d12: 2201 movs r2, #1 8011d14: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011d18: 687b ldr r3, [r7, #4] 8011d1a: 2201 movs r2, #1 8011d1c: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011d20: 687b ldr r3, [r7, #4] 8011d22: 2201 movs r2, #1 8011d24: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011d28: 687b ldr r3, [r7, #4] 8011d2a: 2201 movs r2, #1 8011d2c: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011d30: 687b ldr r3, [r7, #4] 8011d32: 2201 movs r2, #1 8011d34: f883 2042 strb.w r2, [r3, #66] @ 0x42 8011d38: 687b ldr r3, [r7, #4] 8011d3a: 2201 movs r2, #1 8011d3c: f883 2043 strb.w r2, [r3, #67] @ 0x43 8011d40: 687b ldr r3, [r7, #4] 8011d42: 2201 movs r2, #1 8011d44: f883 2044 strb.w r2, [r3, #68] @ 0x44 8011d48: 687b ldr r3, [r7, #4] 8011d4a: 2201 movs r2, #1 8011d4c: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8011d50: 687b ldr r3, [r7, #4] 8011d52: 2201 movs r2, #1 8011d54: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8011d58: 2300 movs r3, #0 } 8011d5a: 4618 mov r0, r3 8011d5c: 3708 adds r7, #8 8011d5e: 46bd mov sp, r7 8011d60: bd80 pop {r7, pc} 08011d62 : * @brief Initializes the TIM Output Compare MSP. * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) { 8011d62: b480 push {r7} 8011d64: b083 sub sp, #12 8011d66: af00 add r7, sp, #0 8011d68: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_MspInit could be implemented in the user file */ } 8011d6a: bf00 nop 8011d6c: 370c adds r7, #12 8011d6e: 46bd mov sp, r7 8011d70: bc80 pop {r7} 8011d72: 4770 bx lr 08011d74 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 8011d74: b580 push {r7, lr} 8011d76: b084 sub sp, #16 8011d78: af00 add r7, sp, #0 8011d7a: 6078 str r0, [r7, #4] 8011d7c: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 8011d7e: 683b ldr r3, [r7, #0] 8011d80: 2b00 cmp r3, #0 8011d82: d109 bne.n 8011d98 8011d84: 687b ldr r3, [r7, #4] 8011d86: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8011d8a: b2db uxtb r3, r3 8011d8c: 2b01 cmp r3, #1 8011d8e: bf14 ite ne 8011d90: 2301 movne r3, #1 8011d92: 2300 moveq r3, #0 8011d94: b2db uxtb r3, r3 8011d96: e022 b.n 8011dde 8011d98: 683b ldr r3, [r7, #0] 8011d9a: 2b04 cmp r3, #4 8011d9c: d109 bne.n 8011db2 8011d9e: 687b ldr r3, [r7, #4] 8011da0: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8011da4: b2db uxtb r3, r3 8011da6: 2b01 cmp r3, #1 8011da8: bf14 ite ne 8011daa: 2301 movne r3, #1 8011dac: 2300 moveq r3, #0 8011dae: b2db uxtb r3, r3 8011db0: e015 b.n 8011dde 8011db2: 683b ldr r3, [r7, #0] 8011db4: 2b08 cmp r3, #8 8011db6: d109 bne.n 8011dcc 8011db8: 687b ldr r3, [r7, #4] 8011dba: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8011dbe: b2db uxtb r3, r3 8011dc0: 2b01 cmp r3, #1 8011dc2: bf14 ite ne 8011dc4: 2301 movne r3, #1 8011dc6: 2300 moveq r3, #0 8011dc8: b2db uxtb r3, r3 8011dca: e008 b.n 8011dde 8011dcc: 687b ldr r3, [r7, #4] 8011dce: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8011dd2: b2db uxtb r3, r3 8011dd4: 2b01 cmp r3, #1 8011dd6: bf14 ite ne 8011dd8: 2301 movne r3, #1 8011dda: 2300 moveq r3, #0 8011ddc: b2db uxtb r3, r3 8011dde: 2b00 cmp r3, #0 8011de0: d001 beq.n 8011de6 { return HAL_ERROR; 8011de2: 2301 movs r3, #1 8011de4: e063 b.n 8011eae } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8011de6: 683b ldr r3, [r7, #0] 8011de8: 2b00 cmp r3, #0 8011dea: d104 bne.n 8011df6 8011dec: 687b ldr r3, [r7, #4] 8011dee: 2202 movs r2, #2 8011df0: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011df4: e013 b.n 8011e1e 8011df6: 683b ldr r3, [r7, #0] 8011df8: 2b04 cmp r3, #4 8011dfa: d104 bne.n 8011e06 8011dfc: 687b ldr r3, [r7, #4] 8011dfe: 2202 movs r2, #2 8011e00: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011e04: e00b b.n 8011e1e 8011e06: 683b ldr r3, [r7, #0] 8011e08: 2b08 cmp r3, #8 8011e0a: d104 bne.n 8011e16 8011e0c: 687b ldr r3, [r7, #4] 8011e0e: 2202 movs r2, #2 8011e10: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011e14: e003 b.n 8011e1e 8011e16: 687b ldr r3, [r7, #4] 8011e18: 2202 movs r2, #2 8011e1a: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 8011e1e: 687b ldr r3, [r7, #4] 8011e20: 681b ldr r3, [r3, #0] 8011e22: 2201 movs r2, #1 8011e24: 6839 ldr r1, [r7, #0] 8011e26: 4618 mov r0, r3 8011e28: f000 fee8 bl 8012bfc if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8011e2c: 687b ldr r3, [r7, #4] 8011e2e: 681b ldr r3, [r3, #0] 8011e30: 4a21 ldr r2, [pc, #132] @ (8011eb8 ) 8011e32: 4293 cmp r3, r2 8011e34: d107 bne.n 8011e46 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8011e36: 687b ldr r3, [r7, #4] 8011e38: 681b ldr r3, [r3, #0] 8011e3a: 6c5a ldr r2, [r3, #68] @ 0x44 8011e3c: 687b ldr r3, [r7, #4] 8011e3e: 681b ldr r3, [r3, #0] 8011e40: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8011e44: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8011e46: 687b ldr r3, [r7, #4] 8011e48: 681b ldr r3, [r3, #0] 8011e4a: 4a1b ldr r2, [pc, #108] @ (8011eb8 ) 8011e4c: 4293 cmp r3, r2 8011e4e: d013 beq.n 8011e78 8011e50: 687b ldr r3, [r7, #4] 8011e52: 681b ldr r3, [r3, #0] 8011e54: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8011e58: d00e beq.n 8011e78 8011e5a: 687b ldr r3, [r7, #4] 8011e5c: 681b ldr r3, [r3, #0] 8011e5e: 4a17 ldr r2, [pc, #92] @ (8011ebc ) 8011e60: 4293 cmp r3, r2 8011e62: d009 beq.n 8011e78 8011e64: 687b ldr r3, [r7, #4] 8011e66: 681b ldr r3, [r3, #0] 8011e68: 4a15 ldr r2, [pc, #84] @ (8011ec0 ) 8011e6a: 4293 cmp r3, r2 8011e6c: d004 beq.n 8011e78 8011e6e: 687b ldr r3, [r7, #4] 8011e70: 681b ldr r3, [r3, #0] 8011e72: 4a14 ldr r2, [pc, #80] @ (8011ec4 ) 8011e74: 4293 cmp r3, r2 8011e76: d111 bne.n 8011e9c { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8011e78: 687b ldr r3, [r7, #4] 8011e7a: 681b ldr r3, [r3, #0] 8011e7c: 689b ldr r3, [r3, #8] 8011e7e: f003 0307 and.w r3, r3, #7 8011e82: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8011e84: 68fb ldr r3, [r7, #12] 8011e86: 2b06 cmp r3, #6 8011e88: d010 beq.n 8011eac { __HAL_TIM_ENABLE(htim); 8011e8a: 687b ldr r3, [r7, #4] 8011e8c: 681b ldr r3, [r3, #0] 8011e8e: 681a ldr r2, [r3, #0] 8011e90: 687b ldr r3, [r7, #4] 8011e92: 681b ldr r3, [r3, #0] 8011e94: f042 0201 orr.w r2, r2, #1 8011e98: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8011e9a: e007 b.n 8011eac } } else { __HAL_TIM_ENABLE(htim); 8011e9c: 687b ldr r3, [r7, #4] 8011e9e: 681b ldr r3, [r3, #0] 8011ea0: 681a ldr r2, [r3, #0] 8011ea2: 687b ldr r3, [r7, #4] 8011ea4: 681b ldr r3, [r3, #0] 8011ea6: f042 0201 orr.w r2, r2, #1 8011eaa: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8011eac: 2300 movs r3, #0 } 8011eae: 4618 mov r0, r3 8011eb0: 3710 adds r7, #16 8011eb2: 46bd mov sp, r7 8011eb4: bd80 pop {r7, pc} 8011eb6: bf00 nop 8011eb8: 40012c00 .word 0x40012c00 8011ebc: 40000400 .word 0x40000400 8011ec0: 40000800 .word 0x40000800 8011ec4: 40000c00 .word 0x40000c00 08011ec8 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 8011ec8: b580 push {r7, lr} 8011eca: b082 sub sp, #8 8011ecc: af00 add r7, sp, #0 8011ece: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8011ed0: 687b ldr r3, [r7, #4] 8011ed2: 2b00 cmp r3, #0 8011ed4: d101 bne.n 8011eda { return HAL_ERROR; 8011ed6: 2301 movs r3, #1 8011ed8: e041 b.n 8011f5e assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8011eda: 687b ldr r3, [r7, #4] 8011edc: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8011ee0: b2db uxtb r3, r3 8011ee2: 2b00 cmp r3, #0 8011ee4: d106 bne.n 8011ef4 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8011ee6: 687b ldr r3, [r7, #4] 8011ee8: 2200 movs r2, #0 8011eea: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 8011eee: 6878 ldr r0, [r7, #4] 8011ef0: f000 f839 bl 8011f66 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8011ef4: 687b ldr r3, [r7, #4] 8011ef6: 2202 movs r2, #2 8011ef8: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8011efc: 687b ldr r3, [r7, #4] 8011efe: 681a ldr r2, [r3, #0] 8011f00: 687b ldr r3, [r7, #4] 8011f02: 3304 adds r3, #4 8011f04: 4619 mov r1, r3 8011f06: 4610 mov r0, r2 8011f08: f000 fbe2 bl 80126d0 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8011f0c: 687b ldr r3, [r7, #4] 8011f0e: 2201 movs r2, #1 8011f10: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011f14: 687b ldr r3, [r7, #4] 8011f16: 2201 movs r2, #1 8011f18: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011f1c: 687b ldr r3, [r7, #4] 8011f1e: 2201 movs r2, #1 8011f20: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011f24: 687b ldr r3, [r7, #4] 8011f26: 2201 movs r2, #1 8011f28: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011f2c: 687b ldr r3, [r7, #4] 8011f2e: 2201 movs r2, #1 8011f30: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011f34: 687b ldr r3, [r7, #4] 8011f36: 2201 movs r2, #1 8011f38: f883 2042 strb.w r2, [r3, #66] @ 0x42 8011f3c: 687b ldr r3, [r7, #4] 8011f3e: 2201 movs r2, #1 8011f40: f883 2043 strb.w r2, [r3, #67] @ 0x43 8011f44: 687b ldr r3, [r7, #4] 8011f46: 2201 movs r2, #1 8011f48: f883 2044 strb.w r2, [r3, #68] @ 0x44 8011f4c: 687b ldr r3, [r7, #4] 8011f4e: 2201 movs r2, #1 8011f50: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8011f54: 687b ldr r3, [r7, #4] 8011f56: 2201 movs r2, #1 8011f58: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8011f5c: 2300 movs r3, #0 } 8011f5e: 4618 mov r0, r3 8011f60: 3708 adds r7, #8 8011f62: 46bd mov sp, r7 8011f64: bd80 pop {r7, pc} 08011f66 : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 8011f66: b480 push {r7} 8011f68: b083 sub sp, #12 8011f6a: af00 add r7, sp, #0 8011f6c: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 8011f6e: bf00 nop 8011f70: 370c adds r7, #12 8011f72: 46bd mov sp, r7 8011f74: bc80 pop {r7} 8011f76: 4770 bx lr 08011f78 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 8011f78: b580 push {r7, lr} 8011f7a: b084 sub sp, #16 8011f7c: af00 add r7, sp, #0 8011f7e: 6078 str r0, [r7, #4] 8011f80: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 8011f82: 683b ldr r3, [r7, #0] 8011f84: 2b00 cmp r3, #0 8011f86: d109 bne.n 8011f9c 8011f88: 687b ldr r3, [r7, #4] 8011f8a: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8011f8e: b2db uxtb r3, r3 8011f90: 2b01 cmp r3, #1 8011f92: bf14 ite ne 8011f94: 2301 movne r3, #1 8011f96: 2300 moveq r3, #0 8011f98: b2db uxtb r3, r3 8011f9a: e022 b.n 8011fe2 8011f9c: 683b ldr r3, [r7, #0] 8011f9e: 2b04 cmp r3, #4 8011fa0: d109 bne.n 8011fb6 8011fa2: 687b ldr r3, [r7, #4] 8011fa4: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8011fa8: b2db uxtb r3, r3 8011faa: 2b01 cmp r3, #1 8011fac: bf14 ite ne 8011fae: 2301 movne r3, #1 8011fb0: 2300 moveq r3, #0 8011fb2: b2db uxtb r3, r3 8011fb4: e015 b.n 8011fe2 8011fb6: 683b ldr r3, [r7, #0] 8011fb8: 2b08 cmp r3, #8 8011fba: d109 bne.n 8011fd0 8011fbc: 687b ldr r3, [r7, #4] 8011fbe: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8011fc2: b2db uxtb r3, r3 8011fc4: 2b01 cmp r3, #1 8011fc6: bf14 ite ne 8011fc8: 2301 movne r3, #1 8011fca: 2300 moveq r3, #0 8011fcc: b2db uxtb r3, r3 8011fce: e008 b.n 8011fe2 8011fd0: 687b ldr r3, [r7, #4] 8011fd2: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8011fd6: b2db uxtb r3, r3 8011fd8: 2b01 cmp r3, #1 8011fda: bf14 ite ne 8011fdc: 2301 movne r3, #1 8011fde: 2300 moveq r3, #0 8011fe0: b2db uxtb r3, r3 8011fe2: 2b00 cmp r3, #0 8011fe4: d001 beq.n 8011fea { return HAL_ERROR; 8011fe6: 2301 movs r3, #1 8011fe8: e063 b.n 80120b2 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8011fea: 683b ldr r3, [r7, #0] 8011fec: 2b00 cmp r3, #0 8011fee: d104 bne.n 8011ffa 8011ff0: 687b ldr r3, [r7, #4] 8011ff2: 2202 movs r2, #2 8011ff4: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011ff8: e013 b.n 8012022 8011ffa: 683b ldr r3, [r7, #0] 8011ffc: 2b04 cmp r3, #4 8011ffe: d104 bne.n 801200a 8012000: 687b ldr r3, [r7, #4] 8012002: 2202 movs r2, #2 8012004: f883 203f strb.w r2, [r3, #63] @ 0x3f 8012008: e00b b.n 8012022 801200a: 683b ldr r3, [r7, #0] 801200c: 2b08 cmp r3, #8 801200e: d104 bne.n 801201a 8012010: 687b ldr r3, [r7, #4] 8012012: 2202 movs r2, #2 8012014: f883 2040 strb.w r2, [r3, #64] @ 0x40 8012018: e003 b.n 8012022 801201a: 687b ldr r3, [r7, #4] 801201c: 2202 movs r2, #2 801201e: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 8012022: 687b ldr r3, [r7, #4] 8012024: 681b ldr r3, [r3, #0] 8012026: 2201 movs r2, #1 8012028: 6839 ldr r1, [r7, #0] 801202a: 4618 mov r0, r3 801202c: f000 fde6 bl 8012bfc if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8012030: 687b ldr r3, [r7, #4] 8012032: 681b ldr r3, [r3, #0] 8012034: 4a21 ldr r2, [pc, #132] @ (80120bc ) 8012036: 4293 cmp r3, r2 8012038: d107 bne.n 801204a { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 801203a: 687b ldr r3, [r7, #4] 801203c: 681b ldr r3, [r3, #0] 801203e: 6c5a ldr r2, [r3, #68] @ 0x44 8012040: 687b ldr r3, [r7, #4] 8012042: 681b ldr r3, [r3, #0] 8012044: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8012048: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 801204a: 687b ldr r3, [r7, #4] 801204c: 681b ldr r3, [r3, #0] 801204e: 4a1b ldr r2, [pc, #108] @ (80120bc ) 8012050: 4293 cmp r3, r2 8012052: d013 beq.n 801207c 8012054: 687b ldr r3, [r7, #4] 8012056: 681b ldr r3, [r3, #0] 8012058: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 801205c: d00e beq.n 801207c 801205e: 687b ldr r3, [r7, #4] 8012060: 681b ldr r3, [r3, #0] 8012062: 4a17 ldr r2, [pc, #92] @ (80120c0 ) 8012064: 4293 cmp r3, r2 8012066: d009 beq.n 801207c 8012068: 687b ldr r3, [r7, #4] 801206a: 681b ldr r3, [r3, #0] 801206c: 4a15 ldr r2, [pc, #84] @ (80120c4 ) 801206e: 4293 cmp r3, r2 8012070: d004 beq.n 801207c 8012072: 687b ldr r3, [r7, #4] 8012074: 681b ldr r3, [r3, #0] 8012076: 4a14 ldr r2, [pc, #80] @ (80120c8 ) 8012078: 4293 cmp r3, r2 801207a: d111 bne.n 80120a0 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 801207c: 687b ldr r3, [r7, #4] 801207e: 681b ldr r3, [r3, #0] 8012080: 689b ldr r3, [r3, #8] 8012082: f003 0307 and.w r3, r3, #7 8012086: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8012088: 68fb ldr r3, [r7, #12] 801208a: 2b06 cmp r3, #6 801208c: d010 beq.n 80120b0 { __HAL_TIM_ENABLE(htim); 801208e: 687b ldr r3, [r7, #4] 8012090: 681b ldr r3, [r3, #0] 8012092: 681a ldr r2, [r3, #0] 8012094: 687b ldr r3, [r7, #4] 8012096: 681b ldr r3, [r3, #0] 8012098: f042 0201 orr.w r2, r2, #1 801209c: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 801209e: e007 b.n 80120b0 } } else { __HAL_TIM_ENABLE(htim); 80120a0: 687b ldr r3, [r7, #4] 80120a2: 681b ldr r3, [r3, #0] 80120a4: 681a ldr r2, [r3, #0] 80120a6: 687b ldr r3, [r7, #4] 80120a8: 681b ldr r3, [r3, #0] 80120aa: f042 0201 orr.w r2, r2, #1 80120ae: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 80120b0: 2300 movs r3, #0 } 80120b2: 4618 mov r0, r3 80120b4: 3710 adds r7, #16 80120b6: 46bd mov sp, r7 80120b8: bd80 pop {r7, pc} 80120ba: bf00 nop 80120bc: 40012c00 .word 0x40012c00 80120c0: 40000400 .word 0x40000400 80120c4: 40000800 .word 0x40000800 80120c8: 40000c00 .word 0x40000c00 080120cc : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 80120cc: b580 push {r7, lr} 80120ce: b084 sub sp, #16 80120d0: af00 add r7, sp, #0 80120d2: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 80120d4: 687b ldr r3, [r7, #4] 80120d6: 681b ldr r3, [r3, #0] 80120d8: 68db ldr r3, [r3, #12] 80120da: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 80120dc: 687b ldr r3, [r7, #4] 80120de: 681b ldr r3, [r3, #0] 80120e0: 691b ldr r3, [r3, #16] 80120e2: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 80120e4: 68bb ldr r3, [r7, #8] 80120e6: f003 0302 and.w r3, r3, #2 80120ea: 2b00 cmp r3, #0 80120ec: d020 beq.n 8012130 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 80120ee: 68fb ldr r3, [r7, #12] 80120f0: f003 0302 and.w r3, r3, #2 80120f4: 2b00 cmp r3, #0 80120f6: d01b beq.n 8012130 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 80120f8: 687b ldr r3, [r7, #4] 80120fa: 681b ldr r3, [r3, #0] 80120fc: f06f 0202 mvn.w r2, #2 8012100: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 8012102: 687b ldr r3, [r7, #4] 8012104: 2201 movs r2, #1 8012106: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8012108: 687b ldr r3, [r7, #4] 801210a: 681b ldr r3, [r3, #0] 801210c: 699b ldr r3, [r3, #24] 801210e: f003 0303 and.w r3, r3, #3 8012112: 2b00 cmp r3, #0 8012114: d003 beq.n 801211e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8012116: 6878 ldr r0, [r7, #4] 8012118: f000 fabf bl 801269a 801211c: e005 b.n 801212a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 801211e: 6878 ldr r0, [r7, #4] 8012120: f000 fab2 bl 8012688 HAL_TIM_PWM_PulseFinishedCallback(htim); 8012124: 6878 ldr r0, [r7, #4] 8012126: f000 fac1 bl 80126ac #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 801212a: 687b ldr r3, [r7, #4] 801212c: 2200 movs r2, #0 801212e: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 8012130: 68bb ldr r3, [r7, #8] 8012132: f003 0304 and.w r3, r3, #4 8012136: 2b00 cmp r3, #0 8012138: d020 beq.n 801217c { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 801213a: 68fb ldr r3, [r7, #12] 801213c: f003 0304 and.w r3, r3, #4 8012140: 2b00 cmp r3, #0 8012142: d01b beq.n 801217c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 8012144: 687b ldr r3, [r7, #4] 8012146: 681b ldr r3, [r3, #0] 8012148: f06f 0204 mvn.w r2, #4 801214c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 801214e: 687b ldr r3, [r7, #4] 8012150: 2202 movs r2, #2 8012152: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8012154: 687b ldr r3, [r7, #4] 8012156: 681b ldr r3, [r3, #0] 8012158: 699b ldr r3, [r3, #24] 801215a: f403 7340 and.w r3, r3, #768 @ 0x300 801215e: 2b00 cmp r3, #0 8012160: d003 beq.n 801216a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8012162: 6878 ldr r0, [r7, #4] 8012164: f000 fa99 bl 801269a 8012168: e005 b.n 8012176 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 801216a: 6878 ldr r0, [r7, #4] 801216c: f000 fa8c bl 8012688 HAL_TIM_PWM_PulseFinishedCallback(htim); 8012170: 6878 ldr r0, [r7, #4] 8012172: f000 fa9b bl 80126ac #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8012176: 687b ldr r3, [r7, #4] 8012178: 2200 movs r2, #0 801217a: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 801217c: 68bb ldr r3, [r7, #8] 801217e: f003 0308 and.w r3, r3, #8 8012182: 2b00 cmp r3, #0 8012184: d020 beq.n 80121c8 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 8012186: 68fb ldr r3, [r7, #12] 8012188: f003 0308 and.w r3, r3, #8 801218c: 2b00 cmp r3, #0 801218e: d01b beq.n 80121c8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 8012190: 687b ldr r3, [r7, #4] 8012192: 681b ldr r3, [r3, #0] 8012194: f06f 0208 mvn.w r2, #8 8012198: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 801219a: 687b ldr r3, [r7, #4] 801219c: 2204 movs r2, #4 801219e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 80121a0: 687b ldr r3, [r7, #4] 80121a2: 681b ldr r3, [r3, #0] 80121a4: 69db ldr r3, [r3, #28] 80121a6: f003 0303 and.w r3, r3, #3 80121aa: 2b00 cmp r3, #0 80121ac: d003 beq.n 80121b6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80121ae: 6878 ldr r0, [r7, #4] 80121b0: f000 fa73 bl 801269a 80121b4: e005 b.n 80121c2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80121b6: 6878 ldr r0, [r7, #4] 80121b8: f000 fa66 bl 8012688 HAL_TIM_PWM_PulseFinishedCallback(htim); 80121bc: 6878 ldr r0, [r7, #4] 80121be: f000 fa75 bl 80126ac #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80121c2: 687b ldr r3, [r7, #4] 80121c4: 2200 movs r2, #0 80121c6: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 80121c8: 68bb ldr r3, [r7, #8] 80121ca: f003 0310 and.w r3, r3, #16 80121ce: 2b00 cmp r3, #0 80121d0: d020 beq.n 8012214 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 80121d2: 68fb ldr r3, [r7, #12] 80121d4: f003 0310 and.w r3, r3, #16 80121d8: 2b00 cmp r3, #0 80121da: d01b beq.n 8012214 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 80121dc: 687b ldr r3, [r7, #4] 80121de: 681b ldr r3, [r3, #0] 80121e0: f06f 0210 mvn.w r2, #16 80121e4: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 80121e6: 687b ldr r3, [r7, #4] 80121e8: 2208 movs r2, #8 80121ea: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 80121ec: 687b ldr r3, [r7, #4] 80121ee: 681b ldr r3, [r3, #0] 80121f0: 69db ldr r3, [r3, #28] 80121f2: f403 7340 and.w r3, r3, #768 @ 0x300 80121f6: 2b00 cmp r3, #0 80121f8: d003 beq.n 8012202 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80121fa: 6878 ldr r0, [r7, #4] 80121fc: f000 fa4d bl 801269a 8012200: e005 b.n 801220e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8012202: 6878 ldr r0, [r7, #4] 8012204: f000 fa40 bl 8012688 HAL_TIM_PWM_PulseFinishedCallback(htim); 8012208: 6878 ldr r0, [r7, #4] 801220a: f000 fa4f bl 80126ac #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 801220e: 687b ldr r3, [r7, #4] 8012210: 2200 movs r2, #0 8012212: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 8012214: 68bb ldr r3, [r7, #8] 8012216: f003 0301 and.w r3, r3, #1 801221a: 2b00 cmp r3, #0 801221c: d00c beq.n 8012238 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 801221e: 68fb ldr r3, [r7, #12] 8012220: f003 0301 and.w r3, r3, #1 8012224: 2b00 cmp r3, #0 8012226: d007 beq.n 8012238 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 8012228: 687b ldr r3, [r7, #4] 801222a: 681b ldr r3, [r3, #0] 801222c: f06f 0201 mvn.w r2, #1 8012230: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 8012232: 6878 ldr r0, [r7, #4] 8012234: f000 fa1f bl 8012676 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) 8012238: 68bb ldr r3, [r7, #8] 801223a: f003 0380 and.w r3, r3, #128 @ 0x80 801223e: 2b00 cmp r3, #0 8012240: d00c beq.n 801225c { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 8012242: 68fb ldr r3, [r7, #12] 8012244: f003 0380 and.w r3, r3, #128 @ 0x80 8012248: 2b00 cmp r3, #0 801224a: d007 beq.n 801225c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); 801224c: 687b ldr r3, [r7, #4] 801224e: 681b ldr r3, [r3, #0] 8012250: f06f 0280 mvn.w r2, #128 @ 0x80 8012254: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8012256: 6878 ldr r0, [r7, #4] 8012258: f000 fd63 bl 8012d22 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 801225c: 68bb ldr r3, [r7, #8] 801225e: f003 0340 and.w r3, r3, #64 @ 0x40 8012262: 2b00 cmp r3, #0 8012264: d00c beq.n 8012280 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 8012266: 68fb ldr r3, [r7, #12] 8012268: f003 0340 and.w r3, r3, #64 @ 0x40 801226c: 2b00 cmp r3, #0 801226e: d007 beq.n 8012280 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 8012270: 687b ldr r3, [r7, #4] 8012272: 681b ldr r3, [r3, #0] 8012274: f06f 0240 mvn.w r2, #64 @ 0x40 8012278: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 801227a: 6878 ldr r0, [r7, #4] 801227c: f000 fa1f bl 80126be #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 8012280: 68bb ldr r3, [r7, #8] 8012282: f003 0320 and.w r3, r3, #32 8012286: 2b00 cmp r3, #0 8012288: d00c beq.n 80122a4 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 801228a: 68fb ldr r3, [r7, #12] 801228c: f003 0320 and.w r3, r3, #32 8012290: 2b00 cmp r3, #0 8012292: d007 beq.n 80122a4 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 8012294: 687b ldr r3, [r7, #4] 8012296: 681b ldr r3, [r3, #0] 8012298: f06f 0220 mvn.w r2, #32 801229c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 801229e: 6878 ldr r0, [r7, #4] 80122a0: f000 fd36 bl 8012d10 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 80122a4: bf00 nop 80122a6: 3710 adds r7, #16 80122a8: 46bd mov sp, r7 80122aa: bd80 pop {r7, pc} 080122ac : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 80122ac: b580 push {r7, lr} 80122ae: b086 sub sp, #24 80122b0: af00 add r7, sp, #0 80122b2: 60f8 str r0, [r7, #12] 80122b4: 60b9 str r1, [r7, #8] 80122b6: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80122b8: 2300 movs r3, #0 80122ba: 75fb strb r3, [r7, #23] assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); 80122bc: 68fb ldr r3, [r7, #12] 80122be: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80122c2: 2b01 cmp r3, #1 80122c4: d101 bne.n 80122ca 80122c6: 2302 movs r3, #2 80122c8: e048 b.n 801235c 80122ca: 68fb ldr r3, [r7, #12] 80122cc: 2201 movs r2, #1 80122ce: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 80122d2: 687b ldr r3, [r7, #4] 80122d4: 2b0c cmp r3, #12 80122d6: d839 bhi.n 801234c 80122d8: a201 add r2, pc, #4 @ (adr r2, 80122e0 ) 80122da: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80122de: bf00 nop 80122e0: 08012315 .word 0x08012315 80122e4: 0801234d .word 0x0801234d 80122e8: 0801234d .word 0x0801234d 80122ec: 0801234d .word 0x0801234d 80122f0: 08012323 .word 0x08012323 80122f4: 0801234d .word 0x0801234d 80122f8: 0801234d .word 0x0801234d 80122fc: 0801234d .word 0x0801234d 8012300: 08012331 .word 0x08012331 8012304: 0801234d .word 0x0801234d 8012308: 0801234d .word 0x0801234d 801230c: 0801234d .word 0x0801234d 8012310: 0801233f .word 0x0801233f { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8012314: 68fb ldr r3, [r7, #12] 8012316: 681b ldr r3, [r3, #0] 8012318: 68b9 ldr r1, [r7, #8] 801231a: 4618 mov r0, r3 801231c: f000 fa50 bl 80127c0 break; 8012320: e017 b.n 8012352 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8012322: 68fb ldr r3, [r7, #12] 8012324: 681b ldr r3, [r3, #0] 8012326: 68b9 ldr r1, [r7, #8] 8012328: 4618 mov r0, r3 801232a: f000 faaf bl 801288c break; 801232e: e010 b.n 8012352 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8012330: 68fb ldr r3, [r7, #12] 8012332: 681b ldr r3, [r3, #0] 8012334: 68b9 ldr r1, [r7, #8] 8012336: 4618 mov r0, r3 8012338: f000 fb12 bl 8012960 break; 801233c: e009 b.n 8012352 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); 801233e: 68fb ldr r3, [r7, #12] 8012340: 681b ldr r3, [r3, #0] 8012342: 68b9 ldr r1, [r7, #8] 8012344: 4618 mov r0, r3 8012346: f000 fb75 bl 8012a34 break; 801234a: e002 b.n 8012352 } default: status = HAL_ERROR; 801234c: 2301 movs r3, #1 801234e: 75fb strb r3, [r7, #23] break; 8012350: bf00 nop } __HAL_UNLOCK(htim); 8012352: 68fb ldr r3, [r7, #12] 8012354: 2200 movs r2, #0 8012356: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 801235a: 7dfb ldrb r3, [r7, #23] } 801235c: 4618 mov r0, r3 801235e: 3718 adds r7, #24 8012360: 46bd mov sp, r7 8012362: bd80 pop {r7, pc} 08012364 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8012364: b580 push {r7, lr} 8012366: b086 sub sp, #24 8012368: af00 add r7, sp, #0 801236a: 60f8 str r0, [r7, #12] 801236c: 60b9 str r1, [r7, #8] 801236e: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8012370: 2300 movs r3, #0 8012372: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 8012374: 68fb ldr r3, [r7, #12] 8012376: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 801237a: 2b01 cmp r3, #1 801237c: d101 bne.n 8012382 801237e: 2302 movs r3, #2 8012380: e0ae b.n 80124e0 8012382: 68fb ldr r3, [r7, #12] 8012384: 2201 movs r2, #1 8012386: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 801238a: 687b ldr r3, [r7, #4] 801238c: 2b0c cmp r3, #12 801238e: f200 809f bhi.w 80124d0 8012392: a201 add r2, pc, #4 @ (adr r2, 8012398 ) 8012394: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012398: 080123cd .word 0x080123cd 801239c: 080124d1 .word 0x080124d1 80123a0: 080124d1 .word 0x080124d1 80123a4: 080124d1 .word 0x080124d1 80123a8: 0801240d .word 0x0801240d 80123ac: 080124d1 .word 0x080124d1 80123b0: 080124d1 .word 0x080124d1 80123b4: 080124d1 .word 0x080124d1 80123b8: 0801244f .word 0x0801244f 80123bc: 080124d1 .word 0x080124d1 80123c0: 080124d1 .word 0x080124d1 80123c4: 080124d1 .word 0x080124d1 80123c8: 0801248f .word 0x0801248f { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 80123cc: 68fb ldr r3, [r7, #12] 80123ce: 681b ldr r3, [r3, #0] 80123d0: 68b9 ldr r1, [r7, #8] 80123d2: 4618 mov r0, r3 80123d4: f000 f9f4 bl 80127c0 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 80123d8: 68fb ldr r3, [r7, #12] 80123da: 681b ldr r3, [r3, #0] 80123dc: 699a ldr r2, [r3, #24] 80123de: 68fb ldr r3, [r7, #12] 80123e0: 681b ldr r3, [r3, #0] 80123e2: f042 0208 orr.w r2, r2, #8 80123e6: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 80123e8: 68fb ldr r3, [r7, #12] 80123ea: 681b ldr r3, [r3, #0] 80123ec: 699a ldr r2, [r3, #24] 80123ee: 68fb ldr r3, [r7, #12] 80123f0: 681b ldr r3, [r3, #0] 80123f2: f022 0204 bic.w r2, r2, #4 80123f6: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 80123f8: 68fb ldr r3, [r7, #12] 80123fa: 681b ldr r3, [r3, #0] 80123fc: 6999 ldr r1, [r3, #24] 80123fe: 68bb ldr r3, [r7, #8] 8012400: 691a ldr r2, [r3, #16] 8012402: 68fb ldr r3, [r7, #12] 8012404: 681b ldr r3, [r3, #0] 8012406: 430a orrs r2, r1 8012408: 619a str r2, [r3, #24] break; 801240a: e064 b.n 80124d6 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 801240c: 68fb ldr r3, [r7, #12] 801240e: 681b ldr r3, [r3, #0] 8012410: 68b9 ldr r1, [r7, #8] 8012412: 4618 mov r0, r3 8012414: f000 fa3a bl 801288c /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8012418: 68fb ldr r3, [r7, #12] 801241a: 681b ldr r3, [r3, #0] 801241c: 699a ldr r2, [r3, #24] 801241e: 68fb ldr r3, [r7, #12] 8012420: 681b ldr r3, [r3, #0] 8012422: f442 6200 orr.w r2, r2, #2048 @ 0x800 8012426: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 8012428: 68fb ldr r3, [r7, #12] 801242a: 681b ldr r3, [r3, #0] 801242c: 699a ldr r2, [r3, #24] 801242e: 68fb ldr r3, [r7, #12] 8012430: 681b ldr r3, [r3, #0] 8012432: f422 6280 bic.w r2, r2, #1024 @ 0x400 8012436: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8012438: 68fb ldr r3, [r7, #12] 801243a: 681b ldr r3, [r3, #0] 801243c: 6999 ldr r1, [r3, #24] 801243e: 68bb ldr r3, [r7, #8] 8012440: 691b ldr r3, [r3, #16] 8012442: 021a lsls r2, r3, #8 8012444: 68fb ldr r3, [r7, #12] 8012446: 681b ldr r3, [r3, #0] 8012448: 430a orrs r2, r1 801244a: 619a str r2, [r3, #24] break; 801244c: e043 b.n 80124d6 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 801244e: 68fb ldr r3, [r7, #12] 8012450: 681b ldr r3, [r3, #0] 8012452: 68b9 ldr r1, [r7, #8] 8012454: 4618 mov r0, r3 8012456: f000 fa83 bl 8012960 /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 801245a: 68fb ldr r3, [r7, #12] 801245c: 681b ldr r3, [r3, #0] 801245e: 69da ldr r2, [r3, #28] 8012460: 68fb ldr r3, [r7, #12] 8012462: 681b ldr r3, [r3, #0] 8012464: f042 0208 orr.w r2, r2, #8 8012468: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 801246a: 68fb ldr r3, [r7, #12] 801246c: 681b ldr r3, [r3, #0] 801246e: 69da ldr r2, [r3, #28] 8012470: 68fb ldr r3, [r7, #12] 8012472: 681b ldr r3, [r3, #0] 8012474: f022 0204 bic.w r2, r2, #4 8012478: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 801247a: 68fb ldr r3, [r7, #12] 801247c: 681b ldr r3, [r3, #0] 801247e: 69d9 ldr r1, [r3, #28] 8012480: 68bb ldr r3, [r7, #8] 8012482: 691a ldr r2, [r3, #16] 8012484: 68fb ldr r3, [r7, #12] 8012486: 681b ldr r3, [r3, #0] 8012488: 430a orrs r2, r1 801248a: 61da str r2, [r3, #28] break; 801248c: e023 b.n 80124d6 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 801248e: 68fb ldr r3, [r7, #12] 8012490: 681b ldr r3, [r3, #0] 8012492: 68b9 ldr r1, [r7, #8] 8012494: 4618 mov r0, r3 8012496: f000 facd bl 8012a34 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 801249a: 68fb ldr r3, [r7, #12] 801249c: 681b ldr r3, [r3, #0] 801249e: 69da ldr r2, [r3, #28] 80124a0: 68fb ldr r3, [r7, #12] 80124a2: 681b ldr r3, [r3, #0] 80124a4: f442 6200 orr.w r2, r2, #2048 @ 0x800 80124a8: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 80124aa: 68fb ldr r3, [r7, #12] 80124ac: 681b ldr r3, [r3, #0] 80124ae: 69da ldr r2, [r3, #28] 80124b0: 68fb ldr r3, [r7, #12] 80124b2: 681b ldr r3, [r3, #0] 80124b4: f422 6280 bic.w r2, r2, #1024 @ 0x400 80124b8: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 80124ba: 68fb ldr r3, [r7, #12] 80124bc: 681b ldr r3, [r3, #0] 80124be: 69d9 ldr r1, [r3, #28] 80124c0: 68bb ldr r3, [r7, #8] 80124c2: 691b ldr r3, [r3, #16] 80124c4: 021a lsls r2, r3, #8 80124c6: 68fb ldr r3, [r7, #12] 80124c8: 681b ldr r3, [r3, #0] 80124ca: 430a orrs r2, r1 80124cc: 61da str r2, [r3, #28] break; 80124ce: e002 b.n 80124d6 } default: status = HAL_ERROR; 80124d0: 2301 movs r3, #1 80124d2: 75fb strb r3, [r7, #23] break; 80124d4: bf00 nop } __HAL_UNLOCK(htim); 80124d6: 68fb ldr r3, [r7, #12] 80124d8: 2200 movs r2, #0 80124da: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 80124de: 7dfb ldrb r3, [r7, #23] } 80124e0: 4618 mov r0, r3 80124e2: 3718 adds r7, #24 80124e4: 46bd mov sp, r7 80124e6: bd80 pop {r7, pc} 080124e8 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 80124e8: b580 push {r7, lr} 80124ea: b084 sub sp, #16 80124ec: af00 add r7, sp, #0 80124ee: 6078 str r0, [r7, #4] 80124f0: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 80124f2: 2300 movs r3, #0 80124f4: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 80124f6: 687b ldr r3, [r7, #4] 80124f8: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80124fc: 2b01 cmp r3, #1 80124fe: d101 bne.n 8012504 8012500: 2302 movs r3, #2 8012502: e0b4 b.n 801266e 8012504: 687b ldr r3, [r7, #4] 8012506: 2201 movs r2, #1 8012508: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 801250c: 687b ldr r3, [r7, #4] 801250e: 2202 movs r2, #2 8012510: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 8012514: 687b ldr r3, [r7, #4] 8012516: 681b ldr r3, [r3, #0] 8012518: 689b ldr r3, [r3, #8] 801251a: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 801251c: 68bb ldr r3, [r7, #8] 801251e: f023 0377 bic.w r3, r3, #119 @ 0x77 8012522: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8012524: 68bb ldr r3, [r7, #8] 8012526: f423 437f bic.w r3, r3, #65280 @ 0xff00 801252a: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 801252c: 687b ldr r3, [r7, #4] 801252e: 681b ldr r3, [r3, #0] 8012530: 68ba ldr r2, [r7, #8] 8012532: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 8012534: 683b ldr r3, [r7, #0] 8012536: 681b ldr r3, [r3, #0] 8012538: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 801253c: d03e beq.n 80125bc 801253e: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8012542: f200 8087 bhi.w 8012654 8012546: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 801254a: f000 8086 beq.w 801265a 801254e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012552: d87f bhi.n 8012654 8012554: 2b70 cmp r3, #112 @ 0x70 8012556: d01a beq.n 801258e 8012558: 2b70 cmp r3, #112 @ 0x70 801255a: d87b bhi.n 8012654 801255c: 2b60 cmp r3, #96 @ 0x60 801255e: d050 beq.n 8012602 8012560: 2b60 cmp r3, #96 @ 0x60 8012562: d877 bhi.n 8012654 8012564: 2b50 cmp r3, #80 @ 0x50 8012566: d03c beq.n 80125e2 8012568: 2b50 cmp r3, #80 @ 0x50 801256a: d873 bhi.n 8012654 801256c: 2b40 cmp r3, #64 @ 0x40 801256e: d058 beq.n 8012622 8012570: 2b40 cmp r3, #64 @ 0x40 8012572: d86f bhi.n 8012654 8012574: 2b30 cmp r3, #48 @ 0x30 8012576: d064 beq.n 8012642 8012578: 2b30 cmp r3, #48 @ 0x30 801257a: d86b bhi.n 8012654 801257c: 2b20 cmp r3, #32 801257e: d060 beq.n 8012642 8012580: 2b20 cmp r3, #32 8012582: d867 bhi.n 8012654 8012584: 2b00 cmp r3, #0 8012586: d05c beq.n 8012642 8012588: 2b10 cmp r3, #16 801258a: d05a beq.n 8012642 801258c: e062 b.n 8012654 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 801258e: 687b ldr r3, [r7, #4] 8012590: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8012592: 683b ldr r3, [r7, #0] 8012594: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 8012596: 683b ldr r3, [r7, #0] 8012598: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 801259a: 683b ldr r3, [r7, #0] 801259c: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 801259e: f000 fb0e bl 8012bbe /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 80125a2: 687b ldr r3, [r7, #4] 80125a4: 681b ldr r3, [r3, #0] 80125a6: 689b ldr r3, [r3, #8] 80125a8: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 80125aa: 68bb ldr r3, [r7, #8] 80125ac: f043 0377 orr.w r3, r3, #119 @ 0x77 80125b0: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80125b2: 687b ldr r3, [r7, #4] 80125b4: 681b ldr r3, [r3, #0] 80125b6: 68ba ldr r2, [r7, #8] 80125b8: 609a str r2, [r3, #8] break; 80125ba: e04f b.n 801265c assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 80125bc: 687b ldr r3, [r7, #4] 80125be: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 80125c0: 683b ldr r3, [r7, #0] 80125c2: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 80125c4: 683b ldr r3, [r7, #0] 80125c6: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 80125c8: 683b ldr r3, [r7, #0] 80125ca: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 80125cc: f000 faf7 bl 8012bbe /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 80125d0: 687b ldr r3, [r7, #4] 80125d2: 681b ldr r3, [r3, #0] 80125d4: 689a ldr r2, [r3, #8] 80125d6: 687b ldr r3, [r7, #4] 80125d8: 681b ldr r3, [r3, #0] 80125da: f442 4280 orr.w r2, r2, #16384 @ 0x4000 80125de: 609a str r2, [r3, #8] break; 80125e0: e03c b.n 801265c /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 80125e2: 687b ldr r3, [r7, #4] 80125e4: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80125e6: 683b ldr r3, [r7, #0] 80125e8: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80125ea: 683b ldr r3, [r7, #0] 80125ec: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 80125ee: 461a mov r2, r3 80125f0: f000 fa6e bl 8012ad0 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 80125f4: 687b ldr r3, [r7, #4] 80125f6: 681b ldr r3, [r3, #0] 80125f8: 2150 movs r1, #80 @ 0x50 80125fa: 4618 mov r0, r3 80125fc: f000 fac5 bl 8012b8a break; 8012600: e02c b.n 801265c /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 8012602: 687b ldr r3, [r7, #4] 8012604: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8012606: 683b ldr r3, [r7, #0] 8012608: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 801260a: 683b ldr r3, [r7, #0] 801260c: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 801260e: 461a mov r2, r3 8012610: f000 fa8c bl 8012b2c TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 8012614: 687b ldr r3, [r7, #4] 8012616: 681b ldr r3, [r3, #0] 8012618: 2160 movs r1, #96 @ 0x60 801261a: 4618 mov r0, r3 801261c: f000 fab5 bl 8012b8a break; 8012620: e01c b.n 801265c /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8012622: 687b ldr r3, [r7, #4] 8012624: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8012626: 683b ldr r3, [r7, #0] 8012628: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 801262a: 683b ldr r3, [r7, #0] 801262c: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 801262e: 461a mov r2, r3 8012630: f000 fa4e bl 8012ad0 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 8012634: 687b ldr r3, [r7, #4] 8012636: 681b ldr r3, [r3, #0] 8012638: 2140 movs r1, #64 @ 0x40 801263a: 4618 mov r0, r3 801263c: f000 faa5 bl 8012b8a break; 8012640: e00c b.n 801265c case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 8012642: 687b ldr r3, [r7, #4] 8012644: 681a ldr r2, [r3, #0] 8012646: 683b ldr r3, [r7, #0] 8012648: 681b ldr r3, [r3, #0] 801264a: 4619 mov r1, r3 801264c: 4610 mov r0, r2 801264e: f000 fa9c bl 8012b8a break; 8012652: e003 b.n 801265c } default: status = HAL_ERROR; 8012654: 2301 movs r3, #1 8012656: 73fb strb r3, [r7, #15] break; 8012658: e000 b.n 801265c break; 801265a: bf00 nop } htim->State = HAL_TIM_STATE_READY; 801265c: 687b ldr r3, [r7, #4] 801265e: 2201 movs r2, #1 8012660: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8012664: 687b ldr r3, [r7, #4] 8012666: 2200 movs r2, #0 8012668: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 801266c: 7bfb ldrb r3, [r7, #15] } 801266e: 4618 mov r0, r3 8012670: 3710 adds r7, #16 8012672: 46bd mov sp, r7 8012674: bd80 pop {r7, pc} 08012676 : * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8012676: b480 push {r7} 8012678: b083 sub sp, #12 801267a: af00 add r7, sp, #0 801267c: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } 801267e: bf00 nop 8012680: 370c adds r7, #12 8012682: 46bd mov sp, r7 8012684: bc80 pop {r7} 8012686: 4770 bx lr 08012688 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 8012688: b480 push {r7} 801268a: b083 sub sp, #12 801268c: af00 add r7, sp, #0 801268e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 8012690: bf00 nop 8012692: 370c adds r7, #12 8012694: 46bd mov sp, r7 8012696: bc80 pop {r7} 8012698: 4770 bx lr 0801269a : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 801269a: b480 push {r7} 801269c: b083 sub sp, #12 801269e: af00 add r7, sp, #0 80126a0: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 80126a2: bf00 nop 80126a4: 370c adds r7, #12 80126a6: 46bd mov sp, r7 80126a8: bc80 pop {r7} 80126aa: 4770 bx lr 080126ac : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 80126ac: b480 push {r7} 80126ae: b083 sub sp, #12 80126b0: af00 add r7, sp, #0 80126b2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 80126b4: bf00 nop 80126b6: 370c adds r7, #12 80126b8: 46bd mov sp, r7 80126ba: bc80 pop {r7} 80126bc: 4770 bx lr 080126be : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 80126be: b480 push {r7} 80126c0: b083 sub sp, #12 80126c2: af00 add r7, sp, #0 80126c4: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 80126c6: bf00 nop 80126c8: 370c adds r7, #12 80126ca: 46bd mov sp, r7 80126cc: bc80 pop {r7} 80126ce: 4770 bx lr 080126d0 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 80126d0: b480 push {r7} 80126d2: b085 sub sp, #20 80126d4: af00 add r7, sp, #0 80126d6: 6078 str r0, [r7, #4] 80126d8: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 80126da: 687b ldr r3, [r7, #4] 80126dc: 681b ldr r3, [r3, #0] 80126de: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80126e0: 687b ldr r3, [r7, #4] 80126e2: 4a33 ldr r2, [pc, #204] @ (80127b0 ) 80126e4: 4293 cmp r3, r2 80126e6: d00f beq.n 8012708 80126e8: 687b ldr r3, [r7, #4] 80126ea: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80126ee: d00b beq.n 8012708 80126f0: 687b ldr r3, [r7, #4] 80126f2: 4a30 ldr r2, [pc, #192] @ (80127b4 ) 80126f4: 4293 cmp r3, r2 80126f6: d007 beq.n 8012708 80126f8: 687b ldr r3, [r7, #4] 80126fa: 4a2f ldr r2, [pc, #188] @ (80127b8 ) 80126fc: 4293 cmp r3, r2 80126fe: d003 beq.n 8012708 8012700: 687b ldr r3, [r7, #4] 8012702: 4a2e ldr r2, [pc, #184] @ (80127bc ) 8012704: 4293 cmp r3, r2 8012706: d108 bne.n 801271a { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8012708: 68fb ldr r3, [r7, #12] 801270a: f023 0370 bic.w r3, r3, #112 @ 0x70 801270e: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8012710: 683b ldr r3, [r7, #0] 8012712: 685b ldr r3, [r3, #4] 8012714: 68fa ldr r2, [r7, #12] 8012716: 4313 orrs r3, r2 8012718: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 801271a: 687b ldr r3, [r7, #4] 801271c: 4a24 ldr r2, [pc, #144] @ (80127b0 ) 801271e: 4293 cmp r3, r2 8012720: d00f beq.n 8012742 8012722: 687b ldr r3, [r7, #4] 8012724: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8012728: d00b beq.n 8012742 801272a: 687b ldr r3, [r7, #4] 801272c: 4a21 ldr r2, [pc, #132] @ (80127b4 ) 801272e: 4293 cmp r3, r2 8012730: d007 beq.n 8012742 8012732: 687b ldr r3, [r7, #4] 8012734: 4a20 ldr r2, [pc, #128] @ (80127b8 ) 8012736: 4293 cmp r3, r2 8012738: d003 beq.n 8012742 801273a: 687b ldr r3, [r7, #4] 801273c: 4a1f ldr r2, [pc, #124] @ (80127bc ) 801273e: 4293 cmp r3, r2 8012740: d108 bne.n 8012754 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8012742: 68fb ldr r3, [r7, #12] 8012744: f423 7340 bic.w r3, r3, #768 @ 0x300 8012748: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 801274a: 683b ldr r3, [r7, #0] 801274c: 68db ldr r3, [r3, #12] 801274e: 68fa ldr r2, [r7, #12] 8012750: 4313 orrs r3, r2 8012752: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8012754: 68fb ldr r3, [r7, #12] 8012756: f023 0280 bic.w r2, r3, #128 @ 0x80 801275a: 683b ldr r3, [r7, #0] 801275c: 695b ldr r3, [r3, #20] 801275e: 4313 orrs r3, r2 8012760: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 8012762: 687b ldr r3, [r7, #4] 8012764: 68fa ldr r2, [r7, #12] 8012766: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8012768: 683b ldr r3, [r7, #0] 801276a: 689a ldr r2, [r3, #8] 801276c: 687b ldr r3, [r7, #4] 801276e: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8012770: 683b ldr r3, [r7, #0] 8012772: 681a ldr r2, [r3, #0] 8012774: 687b ldr r3, [r7, #4] 8012776: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8012778: 687b ldr r3, [r7, #4] 801277a: 4a0d ldr r2, [pc, #52] @ (80127b0 ) 801277c: 4293 cmp r3, r2 801277e: d103 bne.n 8012788 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8012780: 683b ldr r3, [r7, #0] 8012782: 691a ldr r2, [r3, #16] 8012784: 687b ldr r3, [r7, #4] 8012786: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8012788: 687b ldr r3, [r7, #4] 801278a: 2201 movs r2, #1 801278c: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 801278e: 687b ldr r3, [r7, #4] 8012790: 691b ldr r3, [r3, #16] 8012792: f003 0301 and.w r3, r3, #1 8012796: 2b00 cmp r3, #0 8012798: d005 beq.n 80127a6 { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 801279a: 687b ldr r3, [r7, #4] 801279c: 691b ldr r3, [r3, #16] 801279e: f023 0201 bic.w r2, r3, #1 80127a2: 687b ldr r3, [r7, #4] 80127a4: 611a str r2, [r3, #16] } } 80127a6: bf00 nop 80127a8: 3714 adds r7, #20 80127aa: 46bd mov sp, r7 80127ac: bc80 pop {r7} 80127ae: 4770 bx lr 80127b0: 40012c00 .word 0x40012c00 80127b4: 40000400 .word 0x40000400 80127b8: 40000800 .word 0x40000800 80127bc: 40000c00 .word 0x40000c00 080127c0 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80127c0: b480 push {r7} 80127c2: b087 sub sp, #28 80127c4: af00 add r7, sp, #0 80127c6: 6078 str r0, [r7, #4] 80127c8: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80127ca: 687b ldr r3, [r7, #4] 80127cc: 6a1b ldr r3, [r3, #32] 80127ce: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 80127d0: 687b ldr r3, [r7, #4] 80127d2: 6a1b ldr r3, [r3, #32] 80127d4: f023 0201 bic.w r2, r3, #1 80127d8: 687b ldr r3, [r7, #4] 80127da: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80127dc: 687b ldr r3, [r7, #4] 80127de: 685b ldr r3, [r3, #4] 80127e0: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80127e2: 687b ldr r3, [r7, #4] 80127e4: 699b ldr r3, [r3, #24] 80127e6: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 80127e8: 68fb ldr r3, [r7, #12] 80127ea: f023 0370 bic.w r3, r3, #112 @ 0x70 80127ee: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 80127f0: 68fb ldr r3, [r7, #12] 80127f2: f023 0303 bic.w r3, r3, #3 80127f6: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80127f8: 683b ldr r3, [r7, #0] 80127fa: 681b ldr r3, [r3, #0] 80127fc: 68fa ldr r2, [r7, #12] 80127fe: 4313 orrs r3, r2 8012800: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 8012802: 697b ldr r3, [r7, #20] 8012804: f023 0302 bic.w r3, r3, #2 8012808: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 801280a: 683b ldr r3, [r7, #0] 801280c: 689b ldr r3, [r3, #8] 801280e: 697a ldr r2, [r7, #20] 8012810: 4313 orrs r3, r2 8012812: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8012814: 687b ldr r3, [r7, #4] 8012816: 4a1c ldr r2, [pc, #112] @ (8012888 ) 8012818: 4293 cmp r3, r2 801281a: d10c bne.n 8012836 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 801281c: 697b ldr r3, [r7, #20] 801281e: f023 0308 bic.w r3, r3, #8 8012822: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8012824: 683b ldr r3, [r7, #0] 8012826: 68db ldr r3, [r3, #12] 8012828: 697a ldr r2, [r7, #20] 801282a: 4313 orrs r3, r2 801282c: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 801282e: 697b ldr r3, [r7, #20] 8012830: f023 0304 bic.w r3, r3, #4 8012834: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8012836: 687b ldr r3, [r7, #4] 8012838: 4a13 ldr r2, [pc, #76] @ (8012888 ) 801283a: 4293 cmp r3, r2 801283c: d111 bne.n 8012862 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 801283e: 693b ldr r3, [r7, #16] 8012840: f423 7380 bic.w r3, r3, #256 @ 0x100 8012844: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 8012846: 693b ldr r3, [r7, #16] 8012848: f423 7300 bic.w r3, r3, #512 @ 0x200 801284c: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 801284e: 683b ldr r3, [r7, #0] 8012850: 695b ldr r3, [r3, #20] 8012852: 693a ldr r2, [r7, #16] 8012854: 4313 orrs r3, r2 8012856: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 8012858: 683b ldr r3, [r7, #0] 801285a: 699b ldr r3, [r3, #24] 801285c: 693a ldr r2, [r7, #16] 801285e: 4313 orrs r3, r2 8012860: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8012862: 687b ldr r3, [r7, #4] 8012864: 693a ldr r2, [r7, #16] 8012866: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8012868: 687b ldr r3, [r7, #4] 801286a: 68fa ldr r2, [r7, #12] 801286c: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 801286e: 683b ldr r3, [r7, #0] 8012870: 685a ldr r2, [r3, #4] 8012872: 687b ldr r3, [r7, #4] 8012874: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8012876: 687b ldr r3, [r7, #4] 8012878: 697a ldr r2, [r7, #20] 801287a: 621a str r2, [r3, #32] } 801287c: bf00 nop 801287e: 371c adds r7, #28 8012880: 46bd mov sp, r7 8012882: bc80 pop {r7} 8012884: 4770 bx lr 8012886: bf00 nop 8012888: 40012c00 .word 0x40012c00 0801288c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 801288c: b480 push {r7} 801288e: b087 sub sp, #28 8012890: af00 add r7, sp, #0 8012892: 6078 str r0, [r7, #4] 8012894: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8012896: 687b ldr r3, [r7, #4] 8012898: 6a1b ldr r3, [r3, #32] 801289a: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 801289c: 687b ldr r3, [r7, #4] 801289e: 6a1b ldr r3, [r3, #32] 80128a0: f023 0210 bic.w r2, r3, #16 80128a4: 687b ldr r3, [r7, #4] 80128a6: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80128a8: 687b ldr r3, [r7, #4] 80128aa: 685b ldr r3, [r3, #4] 80128ac: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80128ae: 687b ldr r3, [r7, #4] 80128b0: 699b ldr r3, [r3, #24] 80128b2: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 80128b4: 68fb ldr r3, [r7, #12] 80128b6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80128ba: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 80128bc: 68fb ldr r3, [r7, #12] 80128be: f423 7340 bic.w r3, r3, #768 @ 0x300 80128c2: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80128c4: 683b ldr r3, [r7, #0] 80128c6: 681b ldr r3, [r3, #0] 80128c8: 021b lsls r3, r3, #8 80128ca: 68fa ldr r2, [r7, #12] 80128cc: 4313 orrs r3, r2 80128ce: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 80128d0: 697b ldr r3, [r7, #20] 80128d2: f023 0320 bic.w r3, r3, #32 80128d6: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 80128d8: 683b ldr r3, [r7, #0] 80128da: 689b ldr r3, [r3, #8] 80128dc: 011b lsls r3, r3, #4 80128de: 697a ldr r2, [r7, #20] 80128e0: 4313 orrs r3, r2 80128e2: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 80128e4: 687b ldr r3, [r7, #4] 80128e6: 4a1d ldr r2, [pc, #116] @ (801295c ) 80128e8: 4293 cmp r3, r2 80128ea: d10d bne.n 8012908 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 80128ec: 697b ldr r3, [r7, #20] 80128ee: f023 0380 bic.w r3, r3, #128 @ 0x80 80128f2: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 80128f4: 683b ldr r3, [r7, #0] 80128f6: 68db ldr r3, [r3, #12] 80128f8: 011b lsls r3, r3, #4 80128fa: 697a ldr r2, [r7, #20] 80128fc: 4313 orrs r3, r2 80128fe: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8012900: 697b ldr r3, [r7, #20] 8012902: f023 0340 bic.w r3, r3, #64 @ 0x40 8012906: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8012908: 687b ldr r3, [r7, #4] 801290a: 4a14 ldr r2, [pc, #80] @ (801295c ) 801290c: 4293 cmp r3, r2 801290e: d113 bne.n 8012938 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8012910: 693b ldr r3, [r7, #16] 8012912: f423 6380 bic.w r3, r3, #1024 @ 0x400 8012916: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8012918: 693b ldr r3, [r7, #16] 801291a: f423 6300 bic.w r3, r3, #2048 @ 0x800 801291e: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8012920: 683b ldr r3, [r7, #0] 8012922: 695b ldr r3, [r3, #20] 8012924: 009b lsls r3, r3, #2 8012926: 693a ldr r2, [r7, #16] 8012928: 4313 orrs r3, r2 801292a: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 801292c: 683b ldr r3, [r7, #0] 801292e: 699b ldr r3, [r3, #24] 8012930: 009b lsls r3, r3, #2 8012932: 693a ldr r2, [r7, #16] 8012934: 4313 orrs r3, r2 8012936: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8012938: 687b ldr r3, [r7, #4] 801293a: 693a ldr r2, [r7, #16] 801293c: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 801293e: 687b ldr r3, [r7, #4] 8012940: 68fa ldr r2, [r7, #12] 8012942: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8012944: 683b ldr r3, [r7, #0] 8012946: 685a ldr r2, [r3, #4] 8012948: 687b ldr r3, [r7, #4] 801294a: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 801294c: 687b ldr r3, [r7, #4] 801294e: 697a ldr r2, [r7, #20] 8012950: 621a str r2, [r3, #32] } 8012952: bf00 nop 8012954: 371c adds r7, #28 8012956: 46bd mov sp, r7 8012958: bc80 pop {r7} 801295a: 4770 bx lr 801295c: 40012c00 .word 0x40012c00 08012960 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8012960: b480 push {r7} 8012962: b087 sub sp, #28 8012964: af00 add r7, sp, #0 8012966: 6078 str r0, [r7, #4] 8012968: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 801296a: 687b ldr r3, [r7, #4] 801296c: 6a1b ldr r3, [r3, #32] 801296e: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8012970: 687b ldr r3, [r7, #4] 8012972: 6a1b ldr r3, [r3, #32] 8012974: f423 7280 bic.w r2, r3, #256 @ 0x100 8012978: 687b ldr r3, [r7, #4] 801297a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 801297c: 687b ldr r3, [r7, #4] 801297e: 685b ldr r3, [r3, #4] 8012980: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8012982: 687b ldr r3, [r7, #4] 8012984: 69db ldr r3, [r3, #28] 8012986: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8012988: 68fb ldr r3, [r7, #12] 801298a: f023 0370 bic.w r3, r3, #112 @ 0x70 801298e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8012990: 68fb ldr r3, [r7, #12] 8012992: f023 0303 bic.w r3, r3, #3 8012996: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8012998: 683b ldr r3, [r7, #0] 801299a: 681b ldr r3, [r3, #0] 801299c: 68fa ldr r2, [r7, #12] 801299e: 4313 orrs r3, r2 80129a0: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 80129a2: 697b ldr r3, [r7, #20] 80129a4: f423 7300 bic.w r3, r3, #512 @ 0x200 80129a8: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 80129aa: 683b ldr r3, [r7, #0] 80129ac: 689b ldr r3, [r3, #8] 80129ae: 021b lsls r3, r3, #8 80129b0: 697a ldr r2, [r7, #20] 80129b2: 4313 orrs r3, r2 80129b4: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 80129b6: 687b ldr r3, [r7, #4] 80129b8: 4a1d ldr r2, [pc, #116] @ (8012a30 ) 80129ba: 4293 cmp r3, r2 80129bc: d10d bne.n 80129da { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 80129be: 697b ldr r3, [r7, #20] 80129c0: f423 6300 bic.w r3, r3, #2048 @ 0x800 80129c4: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 80129c6: 683b ldr r3, [r7, #0] 80129c8: 68db ldr r3, [r3, #12] 80129ca: 021b lsls r3, r3, #8 80129cc: 697a ldr r2, [r7, #20] 80129ce: 4313 orrs r3, r2 80129d0: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 80129d2: 697b ldr r3, [r7, #20] 80129d4: f423 6380 bic.w r3, r3, #1024 @ 0x400 80129d8: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80129da: 687b ldr r3, [r7, #4] 80129dc: 4a14 ldr r2, [pc, #80] @ (8012a30 ) 80129de: 4293 cmp r3, r2 80129e0: d113 bne.n 8012a0a /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 80129e2: 693b ldr r3, [r7, #16] 80129e4: f423 5380 bic.w r3, r3, #4096 @ 0x1000 80129e8: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 80129ea: 693b ldr r3, [r7, #16] 80129ec: f423 5300 bic.w r3, r3, #8192 @ 0x2000 80129f0: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 80129f2: 683b ldr r3, [r7, #0] 80129f4: 695b ldr r3, [r3, #20] 80129f6: 011b lsls r3, r3, #4 80129f8: 693a ldr r2, [r7, #16] 80129fa: 4313 orrs r3, r2 80129fc: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 80129fe: 683b ldr r3, [r7, #0] 8012a00: 699b ldr r3, [r3, #24] 8012a02: 011b lsls r3, r3, #4 8012a04: 693a ldr r2, [r7, #16] 8012a06: 4313 orrs r3, r2 8012a08: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8012a0a: 687b ldr r3, [r7, #4] 8012a0c: 693a ldr r2, [r7, #16] 8012a0e: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8012a10: 687b ldr r3, [r7, #4] 8012a12: 68fa ldr r2, [r7, #12] 8012a14: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8012a16: 683b ldr r3, [r7, #0] 8012a18: 685a ldr r2, [r3, #4] 8012a1a: 687b ldr r3, [r7, #4] 8012a1c: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8012a1e: 687b ldr r3, [r7, #4] 8012a20: 697a ldr r2, [r7, #20] 8012a22: 621a str r2, [r3, #32] } 8012a24: bf00 nop 8012a26: 371c adds r7, #28 8012a28: 46bd mov sp, r7 8012a2a: bc80 pop {r7} 8012a2c: 4770 bx lr 8012a2e: bf00 nop 8012a30: 40012c00 .word 0x40012c00 08012a34 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8012a34: b480 push {r7} 8012a36: b087 sub sp, #28 8012a38: af00 add r7, sp, #0 8012a3a: 6078 str r0, [r7, #4] 8012a3c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8012a3e: 687b ldr r3, [r7, #4] 8012a40: 6a1b ldr r3, [r3, #32] 8012a42: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8012a44: 687b ldr r3, [r7, #4] 8012a46: 6a1b ldr r3, [r3, #32] 8012a48: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8012a4c: 687b ldr r3, [r7, #4] 8012a4e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8012a50: 687b ldr r3, [r7, #4] 8012a52: 685b ldr r3, [r3, #4] 8012a54: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8012a56: 687b ldr r3, [r7, #4] 8012a58: 69db ldr r3, [r3, #28] 8012a5a: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8012a5c: 68fb ldr r3, [r7, #12] 8012a5e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8012a62: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8012a64: 68fb ldr r3, [r7, #12] 8012a66: f423 7340 bic.w r3, r3, #768 @ 0x300 8012a6a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8012a6c: 683b ldr r3, [r7, #0] 8012a6e: 681b ldr r3, [r3, #0] 8012a70: 021b lsls r3, r3, #8 8012a72: 68fa ldr r2, [r7, #12] 8012a74: 4313 orrs r3, r2 8012a76: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8012a78: 693b ldr r3, [r7, #16] 8012a7a: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8012a7e: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8012a80: 683b ldr r3, [r7, #0] 8012a82: 689b ldr r3, [r3, #8] 8012a84: 031b lsls r3, r3, #12 8012a86: 693a ldr r2, [r7, #16] 8012a88: 4313 orrs r3, r2 8012a8a: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8012a8c: 687b ldr r3, [r7, #4] 8012a8e: 4a0f ldr r2, [pc, #60] @ (8012acc ) 8012a90: 4293 cmp r3, r2 8012a92: d109 bne.n 8012aa8 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8012a94: 697b ldr r3, [r7, #20] 8012a96: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8012a9a: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8012a9c: 683b ldr r3, [r7, #0] 8012a9e: 695b ldr r3, [r3, #20] 8012aa0: 019b lsls r3, r3, #6 8012aa2: 697a ldr r2, [r7, #20] 8012aa4: 4313 orrs r3, r2 8012aa6: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8012aa8: 687b ldr r3, [r7, #4] 8012aaa: 697a ldr r2, [r7, #20] 8012aac: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8012aae: 687b ldr r3, [r7, #4] 8012ab0: 68fa ldr r2, [r7, #12] 8012ab2: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8012ab4: 683b ldr r3, [r7, #0] 8012ab6: 685a ldr r2, [r3, #4] 8012ab8: 687b ldr r3, [r7, #4] 8012aba: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8012abc: 687b ldr r3, [r7, #4] 8012abe: 693a ldr r2, [r7, #16] 8012ac0: 621a str r2, [r3, #32] } 8012ac2: bf00 nop 8012ac4: 371c adds r7, #28 8012ac6: 46bd mov sp, r7 8012ac8: bc80 pop {r7} 8012aca: 4770 bx lr 8012acc: 40012c00 .word 0x40012c00 08012ad0 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8012ad0: b480 push {r7} 8012ad2: b087 sub sp, #28 8012ad4: af00 add r7, sp, #0 8012ad6: 60f8 str r0, [r7, #12] 8012ad8: 60b9 str r1, [r7, #8] 8012ada: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8012adc: 68fb ldr r3, [r7, #12] 8012ade: 6a1b ldr r3, [r3, #32] 8012ae0: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8012ae2: 68fb ldr r3, [r7, #12] 8012ae4: 6a1b ldr r3, [r3, #32] 8012ae6: f023 0201 bic.w r2, r3, #1 8012aea: 68fb ldr r3, [r7, #12] 8012aec: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8012aee: 68fb ldr r3, [r7, #12] 8012af0: 699b ldr r3, [r3, #24] 8012af2: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8012af4: 693b ldr r3, [r7, #16] 8012af6: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8012afa: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8012afc: 687b ldr r3, [r7, #4] 8012afe: 011b lsls r3, r3, #4 8012b00: 693a ldr r2, [r7, #16] 8012b02: 4313 orrs r3, r2 8012b04: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8012b06: 697b ldr r3, [r7, #20] 8012b08: f023 030a bic.w r3, r3, #10 8012b0c: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8012b0e: 697a ldr r2, [r7, #20] 8012b10: 68bb ldr r3, [r7, #8] 8012b12: 4313 orrs r3, r2 8012b14: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8012b16: 68fb ldr r3, [r7, #12] 8012b18: 693a ldr r2, [r7, #16] 8012b1a: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8012b1c: 68fb ldr r3, [r7, #12] 8012b1e: 697a ldr r2, [r7, #20] 8012b20: 621a str r2, [r3, #32] } 8012b22: bf00 nop 8012b24: 371c adds r7, #28 8012b26: 46bd mov sp, r7 8012b28: bc80 pop {r7} 8012b2a: 4770 bx lr 08012b2c : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8012b2c: b480 push {r7} 8012b2e: b087 sub sp, #28 8012b30: af00 add r7, sp, #0 8012b32: 60f8 str r0, [r7, #12] 8012b34: 60b9 str r1, [r7, #8] 8012b36: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8012b38: 68fb ldr r3, [r7, #12] 8012b3a: 6a1b ldr r3, [r3, #32] 8012b3c: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8012b3e: 68fb ldr r3, [r7, #12] 8012b40: 6a1b ldr r3, [r3, #32] 8012b42: f023 0210 bic.w r2, r3, #16 8012b46: 68fb ldr r3, [r7, #12] 8012b48: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8012b4a: 68fb ldr r3, [r7, #12] 8012b4c: 699b ldr r3, [r3, #24] 8012b4e: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8012b50: 693b ldr r3, [r7, #16] 8012b52: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8012b56: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8012b58: 687b ldr r3, [r7, #4] 8012b5a: 031b lsls r3, r3, #12 8012b5c: 693a ldr r2, [r7, #16] 8012b5e: 4313 orrs r3, r2 8012b60: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8012b62: 697b ldr r3, [r7, #20] 8012b64: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8012b68: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8012b6a: 68bb ldr r3, [r7, #8] 8012b6c: 011b lsls r3, r3, #4 8012b6e: 697a ldr r2, [r7, #20] 8012b70: 4313 orrs r3, r2 8012b72: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8012b74: 68fb ldr r3, [r7, #12] 8012b76: 693a ldr r2, [r7, #16] 8012b78: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8012b7a: 68fb ldr r3, [r7, #12] 8012b7c: 697a ldr r2, [r7, #20] 8012b7e: 621a str r2, [r3, #32] } 8012b80: bf00 nop 8012b82: 371c adds r7, #28 8012b84: 46bd mov sp, r7 8012b86: bc80 pop {r7} 8012b88: 4770 bx lr 08012b8a : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8012b8a: b480 push {r7} 8012b8c: b085 sub sp, #20 8012b8e: af00 add r7, sp, #0 8012b90: 6078 str r0, [r7, #4] 8012b92: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8012b94: 687b ldr r3, [r7, #4] 8012b96: 689b ldr r3, [r3, #8] 8012b98: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8012b9a: 68fb ldr r3, [r7, #12] 8012b9c: f023 0370 bic.w r3, r3, #112 @ 0x70 8012ba0: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8012ba2: 683a ldr r2, [r7, #0] 8012ba4: 68fb ldr r3, [r7, #12] 8012ba6: 4313 orrs r3, r2 8012ba8: f043 0307 orr.w r3, r3, #7 8012bac: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8012bae: 687b ldr r3, [r7, #4] 8012bb0: 68fa ldr r2, [r7, #12] 8012bb2: 609a str r2, [r3, #8] } 8012bb4: bf00 nop 8012bb6: 3714 adds r7, #20 8012bb8: 46bd mov sp, r7 8012bba: bc80 pop {r7} 8012bbc: 4770 bx lr 08012bbe : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8012bbe: b480 push {r7} 8012bc0: b087 sub sp, #28 8012bc2: af00 add r7, sp, #0 8012bc4: 60f8 str r0, [r7, #12] 8012bc6: 60b9 str r1, [r7, #8] 8012bc8: 607a str r2, [r7, #4] 8012bca: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8012bcc: 68fb ldr r3, [r7, #12] 8012bce: 689b ldr r3, [r3, #8] 8012bd0: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8012bd2: 697b ldr r3, [r7, #20] 8012bd4: f423 437f bic.w r3, r3, #65280 @ 0xff00 8012bd8: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8012bda: 683b ldr r3, [r7, #0] 8012bdc: 021a lsls r2, r3, #8 8012bde: 687b ldr r3, [r7, #4] 8012be0: 431a orrs r2, r3 8012be2: 68bb ldr r3, [r7, #8] 8012be4: 4313 orrs r3, r2 8012be6: 697a ldr r2, [r7, #20] 8012be8: 4313 orrs r3, r2 8012bea: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8012bec: 68fb ldr r3, [r7, #12] 8012bee: 697a ldr r2, [r7, #20] 8012bf0: 609a str r2, [r3, #8] } 8012bf2: bf00 nop 8012bf4: 371c adds r7, #28 8012bf6: 46bd mov sp, r7 8012bf8: bc80 pop {r7} 8012bfa: 4770 bx lr 08012bfc : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8012bfc: b480 push {r7} 8012bfe: b087 sub sp, #28 8012c00: af00 add r7, sp, #0 8012c02: 60f8 str r0, [r7, #12] 8012c04: 60b9 str r1, [r7, #8] 8012c06: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8012c08: 68bb ldr r3, [r7, #8] 8012c0a: f003 031f and.w r3, r3, #31 8012c0e: 2201 movs r2, #1 8012c10: fa02 f303 lsl.w r3, r2, r3 8012c14: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 8012c16: 68fb ldr r3, [r7, #12] 8012c18: 6a1a ldr r2, [r3, #32] 8012c1a: 697b ldr r3, [r7, #20] 8012c1c: 43db mvns r3, r3 8012c1e: 401a ands r2, r3 8012c20: 68fb ldr r3, [r7, #12] 8012c22: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8012c24: 68fb ldr r3, [r7, #12] 8012c26: 6a1a ldr r2, [r3, #32] 8012c28: 68bb ldr r3, [r7, #8] 8012c2a: f003 031f and.w r3, r3, #31 8012c2e: 6879 ldr r1, [r7, #4] 8012c30: fa01 f303 lsl.w r3, r1, r3 8012c34: 431a orrs r2, r3 8012c36: 68fb ldr r3, [r7, #12] 8012c38: 621a str r2, [r3, #32] } 8012c3a: bf00 nop 8012c3c: 371c adds r7, #28 8012c3e: 46bd mov sp, r7 8012c40: bc80 pop {r7} 8012c42: 4770 bx lr 08012c44 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8012c44: b480 push {r7} 8012c46: b085 sub sp, #20 8012c48: af00 add r7, sp, #0 8012c4a: 6078 str r0, [r7, #4] 8012c4c: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8012c4e: 687b ldr r3, [r7, #4] 8012c50: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8012c54: 2b01 cmp r3, #1 8012c56: d101 bne.n 8012c5c 8012c58: 2302 movs r3, #2 8012c5a: e04b b.n 8012cf4 8012c5c: 687b ldr r3, [r7, #4] 8012c5e: 2201 movs r2, #1 8012c60: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8012c64: 687b ldr r3, [r7, #4] 8012c66: 2202 movs r2, #2 8012c68: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8012c6c: 687b ldr r3, [r7, #4] 8012c6e: 681b ldr r3, [r3, #0] 8012c70: 685b ldr r3, [r3, #4] 8012c72: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8012c74: 687b ldr r3, [r7, #4] 8012c76: 681b ldr r3, [r3, #0] 8012c78: 689b ldr r3, [r3, #8] 8012c7a: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8012c7c: 68fb ldr r3, [r7, #12] 8012c7e: f023 0370 bic.w r3, r3, #112 @ 0x70 8012c82: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8012c84: 683b ldr r3, [r7, #0] 8012c86: 681b ldr r3, [r3, #0] 8012c88: 68fa ldr r2, [r7, #12] 8012c8a: 4313 orrs r3, r2 8012c8c: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8012c8e: 687b ldr r3, [r7, #4] 8012c90: 681b ldr r3, [r3, #0] 8012c92: 68fa ldr r2, [r7, #12] 8012c94: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8012c96: 687b ldr r3, [r7, #4] 8012c98: 681b ldr r3, [r3, #0] 8012c9a: 4a19 ldr r2, [pc, #100] @ (8012d00 ) 8012c9c: 4293 cmp r3, r2 8012c9e: d013 beq.n 8012cc8 8012ca0: 687b ldr r3, [r7, #4] 8012ca2: 681b ldr r3, [r3, #0] 8012ca4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8012ca8: d00e beq.n 8012cc8 8012caa: 687b ldr r3, [r7, #4] 8012cac: 681b ldr r3, [r3, #0] 8012cae: 4a15 ldr r2, [pc, #84] @ (8012d04 ) 8012cb0: 4293 cmp r3, r2 8012cb2: d009 beq.n 8012cc8 8012cb4: 687b ldr r3, [r7, #4] 8012cb6: 681b ldr r3, [r3, #0] 8012cb8: 4a13 ldr r2, [pc, #76] @ (8012d08 ) 8012cba: 4293 cmp r3, r2 8012cbc: d004 beq.n 8012cc8 8012cbe: 687b ldr r3, [r7, #4] 8012cc0: 681b ldr r3, [r3, #0] 8012cc2: 4a12 ldr r2, [pc, #72] @ (8012d0c ) 8012cc4: 4293 cmp r3, r2 8012cc6: d10c bne.n 8012ce2 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8012cc8: 68bb ldr r3, [r7, #8] 8012cca: f023 0380 bic.w r3, r3, #128 @ 0x80 8012cce: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8012cd0: 683b ldr r3, [r7, #0] 8012cd2: 685b ldr r3, [r3, #4] 8012cd4: 68ba ldr r2, [r7, #8] 8012cd6: 4313 orrs r3, r2 8012cd8: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8012cda: 687b ldr r3, [r7, #4] 8012cdc: 681b ldr r3, [r3, #0] 8012cde: 68ba ldr r2, [r7, #8] 8012ce0: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8012ce2: 687b ldr r3, [r7, #4] 8012ce4: 2201 movs r2, #1 8012ce6: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8012cea: 687b ldr r3, [r7, #4] 8012cec: 2200 movs r2, #0 8012cee: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8012cf2: 2300 movs r3, #0 } 8012cf4: 4618 mov r0, r3 8012cf6: 3714 adds r7, #20 8012cf8: 46bd mov sp, r7 8012cfa: bc80 pop {r7} 8012cfc: 4770 bx lr 8012cfe: bf00 nop 8012d00: 40012c00 .word 0x40012c00 8012d04: 40000400 .word 0x40000400 8012d08: 40000800 .word 0x40000800 8012d0c: 40000c00 .word 0x40000c00 08012d10 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8012d10: b480 push {r7} 8012d12: b083 sub sp, #12 8012d14: af00 add r7, sp, #0 8012d16: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8012d18: bf00 nop 8012d1a: 370c adds r7, #12 8012d1c: 46bd mov sp, r7 8012d1e: bc80 pop {r7} 8012d20: 4770 bx lr 08012d22 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8012d22: b480 push {r7} 8012d24: b083 sub sp, #12 8012d26: af00 add r7, sp, #0 8012d28: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8012d2a: bf00 nop 8012d2c: 370c adds r7, #12 8012d2e: 46bd mov sp, r7 8012d30: bc80 pop {r7} 8012d32: 4770 bx lr 08012d34 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8012d34: b580 push {r7, lr} 8012d36: b082 sub sp, #8 8012d38: af00 add r7, sp, #0 8012d3a: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8012d3c: 687b ldr r3, [r7, #4] 8012d3e: 2b00 cmp r3, #0 8012d40: d101 bne.n 8012d46 { return HAL_ERROR; 8012d42: 2301 movs r3, #1 8012d44: e042 b.n 8012dcc assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 8012d46: 687b ldr r3, [r7, #4] 8012d48: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8012d4c: b2db uxtb r3, r3 8012d4e: 2b00 cmp r3, #0 8012d50: d106 bne.n 8012d60 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8012d52: 687b ldr r3, [r7, #4] 8012d54: 2200 movs r2, #0 8012d56: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8012d5a: 6878 ldr r0, [r7, #4] 8012d5c: f7fa ff28 bl 800dbb0 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8012d60: 687b ldr r3, [r7, #4] 8012d62: 2224 movs r2, #36 @ 0x24 8012d64: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8012d68: 687b ldr r3, [r7, #4] 8012d6a: 681b ldr r3, [r3, #0] 8012d6c: 68da ldr r2, [r3, #12] 8012d6e: 687b ldr r3, [r7, #4] 8012d70: 681b ldr r3, [r3, #0] 8012d72: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8012d76: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8012d78: 6878 ldr r0, [r7, #4] 8012d7a: f000 fee7 bl 8013b4c /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8012d7e: 687b ldr r3, [r7, #4] 8012d80: 681b ldr r3, [r3, #0] 8012d82: 691a ldr r2, [r3, #16] 8012d84: 687b ldr r3, [r7, #4] 8012d86: 681b ldr r3, [r3, #0] 8012d88: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8012d8c: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8012d8e: 687b ldr r3, [r7, #4] 8012d90: 681b ldr r3, [r3, #0] 8012d92: 695a ldr r2, [r3, #20] 8012d94: 687b ldr r3, [r7, #4] 8012d96: 681b ldr r3, [r3, #0] 8012d98: f022 022a bic.w r2, r2, #42 @ 0x2a 8012d9c: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8012d9e: 687b ldr r3, [r7, #4] 8012da0: 681b ldr r3, [r3, #0] 8012da2: 68da ldr r2, [r3, #12] 8012da4: 687b ldr r3, [r7, #4] 8012da6: 681b ldr r3, [r3, #0] 8012da8: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8012dac: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012dae: 687b ldr r3, [r7, #4] 8012db0: 2200 movs r2, #0 8012db2: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8012db4: 687b ldr r3, [r7, #4] 8012db6: 2220 movs r2, #32 8012db8: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8012dbc: 687b ldr r3, [r7, #4] 8012dbe: 2220 movs r2, #32 8012dc0: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8012dc4: 687b ldr r3, [r7, #4] 8012dc6: 2200 movs r2, #0 8012dc8: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 8012dca: 2300 movs r3, #0 } 8012dcc: 4618 mov r0, r3 8012dce: 3708 adds r7, #8 8012dd0: 46bd mov sp, r7 8012dd2: bd80 pop {r7, pc} 08012dd4 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) { 8012dd4: b580 push {r7, lr} 8012dd6: b082 sub sp, #8 8012dd8: af00 add r7, sp, #0 8012dda: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8012ddc: 687b ldr r3, [r7, #4] 8012dde: 2b00 cmp r3, #0 8012de0: d101 bne.n 8012de6 { return HAL_ERROR; 8012de2: 2301 movs r3, #1 8012de4: e024 b.n 8012e30 } /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); huart->gState = HAL_UART_STATE_BUSY; 8012de6: 687b ldr r3, [r7, #4] 8012de8: 2224 movs r2, #36 @ 0x24 8012dea: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); 8012dee: 687b ldr r3, [r7, #4] 8012df0: 681b ldr r3, [r3, #0] 8012df2: 68da ldr r2, [r3, #12] 8012df4: 687b ldr r3, [r7, #4] 8012df6: 681b ldr r3, [r3, #0] 8012df8: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8012dfc: 60da str r2, [r3, #12] } /* DeInit the low level hardware */ huart->MspDeInitCallback(huart); #else /* DeInit the low level hardware */ HAL_UART_MspDeInit(huart); 8012dfe: 6878 ldr r0, [r7, #4] 8012e00: f7fb f820 bl 800de44 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012e04: 687b ldr r3, [r7, #4] 8012e06: 2200 movs r2, #0 8012e08: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_RESET; 8012e0a: 687b ldr r3, [r7, #4] 8012e0c: 2200 movs r2, #0 8012e0e: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_RESET; 8012e12: 687b ldr r3, [r7, #4] 8012e14: 2200 movs r2, #0 8012e16: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012e1a: 687b ldr r3, [r7, #4] 8012e1c: 2200 movs r2, #0 8012e1e: 631a str r2, [r3, #48] @ 0x30 huart->RxEventType = HAL_UART_RXEVENT_TC; 8012e20: 687b ldr r3, [r7, #4] 8012e22: 2200 movs r2, #0 8012e24: 635a str r2, [r3, #52] @ 0x34 /* Process Unlock */ __HAL_UNLOCK(huart); 8012e26: 687b ldr r3, [r7, #4] 8012e28: 2200 movs r2, #0 8012e2a: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_OK; 8012e2e: 2300 movs r3, #0 } 8012e30: 4618 mov r0, r3 8012e32: 3708 adds r7, #8 8012e34: 46bd mov sp, r7 8012e36: bd80 pop {r7, pc} 08012e38 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8012e38: b480 push {r7} 8012e3a: b085 sub sp, #20 8012e3c: af00 add r7, sp, #0 8012e3e: 60f8 str r0, [r7, #12] 8012e40: 60b9 str r1, [r7, #8] 8012e42: 4613 mov r3, r2 8012e44: 80fb strh r3, [r7, #6] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8012e46: 68fb ldr r3, [r7, #12] 8012e48: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8012e4c: b2db uxtb r3, r3 8012e4e: 2b20 cmp r3, #32 8012e50: d121 bne.n 8012e96 { if ((pData == NULL) || (Size == 0U)) 8012e52: 68bb ldr r3, [r7, #8] 8012e54: 2b00 cmp r3, #0 8012e56: d002 beq.n 8012e5e 8012e58: 88fb ldrh r3, [r7, #6] 8012e5a: 2b00 cmp r3, #0 8012e5c: d101 bne.n 8012e62 { return HAL_ERROR; 8012e5e: 2301 movs r3, #1 8012e60: e01a b.n 8012e98 } huart->pTxBuffPtr = pData; 8012e62: 68fb ldr r3, [r7, #12] 8012e64: 68ba ldr r2, [r7, #8] 8012e66: 621a str r2, [r3, #32] huart->TxXferSize = Size; 8012e68: 68fb ldr r3, [r7, #12] 8012e6a: 88fa ldrh r2, [r7, #6] 8012e6c: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8012e6e: 68fb ldr r3, [r7, #12] 8012e70: 88fa ldrh r2, [r7, #6] 8012e72: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 8012e74: 68fb ldr r3, [r7, #12] 8012e76: 2200 movs r2, #0 8012e78: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8012e7a: 68fb ldr r3, [r7, #12] 8012e7c: 2221 movs r2, #33 @ 0x21 8012e7e: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the UART Transmit data register empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); 8012e82: 68fb ldr r3, [r7, #12] 8012e84: 681b ldr r3, [r3, #0] 8012e86: 68da ldr r2, [r3, #12] 8012e88: 68fb ldr r3, [r7, #12] 8012e8a: 681b ldr r3, [r3, #0] 8012e8c: f042 0280 orr.w r2, r2, #128 @ 0x80 8012e90: 60da str r2, [r3, #12] return HAL_OK; 8012e92: 2300 movs r3, #0 8012e94: e000 b.n 8012e98 } else { return HAL_BUSY; 8012e96: 2302 movs r3, #2 } } 8012e98: 4618 mov r0, r3 8012e9a: 3714 adds r7, #20 8012e9c: 46bd mov sp, r7 8012e9e: bc80 pop {r7} 8012ea0: 4770 bx lr 08012ea2 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8012ea2: b580 push {r7, lr} 8012ea4: b08c sub sp, #48 @ 0x30 8012ea6: af00 add r7, sp, #0 8012ea8: 60f8 str r0, [r7, #12] 8012eaa: 60b9 str r1, [r7, #8] 8012eac: 4613 mov r3, r2 8012eae: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8012eb0: 68fb ldr r3, [r7, #12] 8012eb2: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8012eb6: b2db uxtb r3, r3 8012eb8: 2b20 cmp r3, #32 8012eba: d14a bne.n 8012f52 { if ((pData == NULL) || (Size == 0U)) 8012ebc: 68bb ldr r3, [r7, #8] 8012ebe: 2b00 cmp r3, #0 8012ec0: d002 beq.n 8012ec8 8012ec2: 88fb ldrh r3, [r7, #6] 8012ec4: 2b00 cmp r3, #0 8012ec6: d101 bne.n 8012ecc { return HAL_ERROR; 8012ec8: 2301 movs r3, #1 8012eca: e043 b.n 8012f54 } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8012ecc: 68fb ldr r3, [r7, #12] 8012ece: 2201 movs r2, #1 8012ed0: 631a str r2, [r3, #48] @ 0x30 huart->RxEventType = HAL_UART_RXEVENT_TC; 8012ed2: 68fb ldr r3, [r7, #12] 8012ed4: 2200 movs r2, #0 8012ed6: 635a str r2, [r3, #52] @ 0x34 status = UART_Start_Receive_IT(huart, pData, Size); 8012ed8: 88fb ldrh r3, [r7, #6] 8012eda: 461a mov r2, r3 8012edc: 68b9 ldr r1, [r7, #8] 8012ede: 68f8 ldr r0, [r7, #12] 8012ee0: f000 fbff bl 80136e2 8012ee4: 4603 mov r3, r0 8012ee6: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check Rx process has been successfully started */ if (status == HAL_OK) 8012eea: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8012eee: 2b00 cmp r3, #0 8012ef0: d12c bne.n 8012f4c { if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012ef2: 68fb ldr r3, [r7, #12] 8012ef4: 6b1b ldr r3, [r3, #48] @ 0x30 8012ef6: 2b01 cmp r3, #1 8012ef8: d125 bne.n 8012f46 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8012efa: 2300 movs r3, #0 8012efc: 613b str r3, [r7, #16] 8012efe: 68fb ldr r3, [r7, #12] 8012f00: 681b ldr r3, [r3, #0] 8012f02: 681b ldr r3, [r3, #0] 8012f04: 613b str r3, [r7, #16] 8012f06: 68fb ldr r3, [r7, #12] 8012f08: 681b ldr r3, [r3, #0] 8012f0a: 685b ldr r3, [r3, #4] 8012f0c: 613b str r3, [r7, #16] 8012f0e: 693b ldr r3, [r7, #16] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012f10: 68fb ldr r3, [r7, #12] 8012f12: 681b ldr r3, [r3, #0] 8012f14: 330c adds r3, #12 8012f16: 61bb str r3, [r7, #24] */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012f18: 69bb ldr r3, [r7, #24] 8012f1a: e853 3f00 ldrex r3, [r3] 8012f1e: 617b str r3, [r7, #20] return(result); 8012f20: 697b ldr r3, [r7, #20] 8012f22: f043 0310 orr.w r3, r3, #16 8012f26: 62bb str r3, [r7, #40] @ 0x28 8012f28: 68fb ldr r3, [r7, #12] 8012f2a: 681b ldr r3, [r3, #0] 8012f2c: 330c adds r3, #12 8012f2e: 6aba ldr r2, [r7, #40] @ 0x28 8012f30: 627a str r2, [r7, #36] @ 0x24 8012f32: 623b str r3, [r7, #32] */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012f34: 6a39 ldr r1, [r7, #32] 8012f36: 6a7a ldr r2, [r7, #36] @ 0x24 8012f38: e841 2300 strex r3, r2, [r1] 8012f3c: 61fb str r3, [r7, #28] return(result); 8012f3e: 69fb ldr r3, [r7, #28] 8012f40: 2b00 cmp r3, #0 8012f42: d1e5 bne.n 8012f10 8012f44: e002 b.n 8012f4c { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8012f46: 2301 movs r3, #1 8012f48: f887 302f strb.w r3, [r7, #47] @ 0x2f } } return status; 8012f4c: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8012f50: e000 b.n 8012f54 } else { return HAL_BUSY; 8012f52: 2302 movs r3, #2 } } 8012f54: 4618 mov r0, r3 8012f56: 3730 adds r7, #48 @ 0x30 8012f58: 46bd mov sp, r7 8012f5a: bd80 pop {r7, pc} 08012f5c : * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { 8012f5c: b580 push {r7, lr} 8012f5e: b0a2 sub sp, #136 @ 0x88 8012f60: af00 add r7, sp, #0 8012f62: 6078 str r0, [r7, #4] uint32_t AbortCplt = 0x01U; 8012f64: 2301 movs r3, #1 8012f66: f8c7 3084 str.w r3, [r7, #132] @ 0x84 /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); 8012f6a: 687b ldr r3, [r7, #4] 8012f6c: 681b ldr r3, [r3, #0] 8012f6e: 330c adds r3, #12 8012f70: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012f72: 6e3b ldr r3, [r7, #96] @ 0x60 8012f74: e853 3f00 ldrex r3, [r3] 8012f78: 65fb str r3, [r7, #92] @ 0x5c return(result); 8012f7a: 6dfb ldr r3, [r7, #92] @ 0x5c 8012f7c: f423 73f0 bic.w r3, r3, #480 @ 0x1e0 8012f80: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8012f84: 687b ldr r3, [r7, #4] 8012f86: 681b ldr r3, [r3, #0] 8012f88: 330c adds r3, #12 8012f8a: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8012f8e: 66fa str r2, [r7, #108] @ 0x6c 8012f90: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012f92: 6eb9 ldr r1, [r7, #104] @ 0x68 8012f94: 6efa ldr r2, [r7, #108] @ 0x6c 8012f96: e841 2300 strex r3, r2, [r1] 8012f9a: 667b str r3, [r7, #100] @ 0x64 return(result); 8012f9c: 6e7b ldr r3, [r7, #100] @ 0x64 8012f9e: 2b00 cmp r3, #0 8012fa0: d1e3 bne.n 8012f6a ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012fa2: 687b ldr r3, [r7, #4] 8012fa4: 681b ldr r3, [r3, #0] 8012fa6: 3314 adds r3, #20 8012fa8: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012faa: 6cfb ldr r3, [r7, #76] @ 0x4c 8012fac: e853 3f00 ldrex r3, [r3] 8012fb0: 64bb str r3, [r7, #72] @ 0x48 return(result); 8012fb2: 6cbb ldr r3, [r7, #72] @ 0x48 8012fb4: f023 0301 bic.w r3, r3, #1 8012fb8: 67fb str r3, [r7, #124] @ 0x7c 8012fba: 687b ldr r3, [r7, #4] 8012fbc: 681b ldr r3, [r3, #0] 8012fbe: 3314 adds r3, #20 8012fc0: 6ffa ldr r2, [r7, #124] @ 0x7c 8012fc2: 65ba str r2, [r7, #88] @ 0x58 8012fc4: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012fc6: 6d79 ldr r1, [r7, #84] @ 0x54 8012fc8: 6dba ldr r2, [r7, #88] @ 0x58 8012fca: e841 2300 strex r3, r2, [r1] 8012fce: 653b str r3, [r7, #80] @ 0x50 return(result); 8012fd0: 6d3b ldr r3, [r7, #80] @ 0x50 8012fd2: 2b00 cmp r3, #0 8012fd4: d1e5 bne.n 8012fa2 /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012fd6: 687b ldr r3, [r7, #4] 8012fd8: 6b1b ldr r3, [r3, #48] @ 0x30 8012fda: 2b01 cmp r3, #1 8012fdc: d119 bne.n 8013012 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); 8012fde: 687b ldr r3, [r7, #4] 8012fe0: 681b ldr r3, [r3, #0] 8012fe2: 330c adds r3, #12 8012fe4: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012fe6: 6bbb ldr r3, [r7, #56] @ 0x38 8012fe8: e853 3f00 ldrex r3, [r3] 8012fec: 637b str r3, [r7, #52] @ 0x34 return(result); 8012fee: 6b7b ldr r3, [r7, #52] @ 0x34 8012ff0: f023 0310 bic.w r3, r3, #16 8012ff4: 67bb str r3, [r7, #120] @ 0x78 8012ff6: 687b ldr r3, [r7, #4] 8012ff8: 681b ldr r3, [r3, #0] 8012ffa: 330c adds r3, #12 8012ffc: 6fba ldr r2, [r7, #120] @ 0x78 8012ffe: 647a str r2, [r7, #68] @ 0x44 8013000: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013002: 6c39 ldr r1, [r7, #64] @ 0x40 8013004: 6c7a ldr r2, [r7, #68] @ 0x44 8013006: e841 2300 strex r3, r2, [r1] 801300a: 63fb str r3, [r7, #60] @ 0x3c return(result); 801300c: 6bfb ldr r3, [r7, #60] @ 0x3c 801300e: 2b00 cmp r3, #0 8013010: d1e5 bne.n 8012fde } /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ if (huart->hdmatx != NULL) 8013012: 687b ldr r3, [r7, #4] 8013014: 6b9b ldr r3, [r3, #56] @ 0x38 8013016: 2b00 cmp r3, #0 8013018: d00f beq.n 801303a { /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. Otherwise, set it to NULL */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) 801301a: 687b ldr r3, [r7, #4] 801301c: 681b ldr r3, [r3, #0] 801301e: 695b ldr r3, [r3, #20] 8013020: f003 0380 and.w r3, r3, #128 @ 0x80 8013024: 2b00 cmp r3, #0 8013026: d004 beq.n 8013032 { huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; 8013028: 687b ldr r3, [r7, #4] 801302a: 6b9b ldr r3, [r3, #56] @ 0x38 801302c: 4a53 ldr r2, [pc, #332] @ (801317c ) 801302e: 635a str r2, [r3, #52] @ 0x34 8013030: e003 b.n 801303a } else { huart->hdmatx->XferAbortCallback = NULL; 8013032: 687b ldr r3, [r7, #4] 8013034: 6b9b ldr r3, [r3, #56] @ 0x38 8013036: 2200 movs r2, #0 8013038: 635a str r2, [r3, #52] @ 0x34 } } /* DMA Rx Handle is valid */ if (huart->hdmarx != NULL) 801303a: 687b ldr r3, [r7, #4] 801303c: 6bdb ldr r3, [r3, #60] @ 0x3c 801303e: 2b00 cmp r3, #0 8013040: d00f beq.n 8013062 { /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. Otherwise, set it to NULL */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013042: 687b ldr r3, [r7, #4] 8013044: 681b ldr r3, [r3, #0] 8013046: 695b ldr r3, [r3, #20] 8013048: f003 0340 and.w r3, r3, #64 @ 0x40 801304c: 2b00 cmp r3, #0 801304e: d004 beq.n 801305a { huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; 8013050: 687b ldr r3, [r7, #4] 8013052: 6bdb ldr r3, [r3, #60] @ 0x3c 8013054: 4a4a ldr r2, [pc, #296] @ (8013180 ) 8013056: 635a str r2, [r3, #52] @ 0x34 8013058: e003 b.n 8013062 } else { huart->hdmarx->XferAbortCallback = NULL; 801305a: 687b ldr r3, [r7, #4] 801305c: 6bdb ldr r3, [r3, #60] @ 0x3c 801305e: 2200 movs r2, #0 8013060: 635a str r2, [r3, #52] @ 0x34 } } /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) 8013062: 687b ldr r3, [r7, #4] 8013064: 681b ldr r3, [r3, #0] 8013066: 695b ldr r3, [r3, #20] 8013068: f003 0380 and.w r3, r3, #128 @ 0x80 801306c: 2b00 cmp r3, #0 801306e: d02d beq.n 80130cc { /* Disable DMA Tx at UART level */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8013070: 687b ldr r3, [r7, #4] 8013072: 681b ldr r3, [r3, #0] 8013074: 3314 adds r3, #20 8013076: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013078: 6a7b ldr r3, [r7, #36] @ 0x24 801307a: e853 3f00 ldrex r3, [r3] 801307e: 623b str r3, [r7, #32] return(result); 8013080: 6a3b ldr r3, [r7, #32] 8013082: f023 0380 bic.w r3, r3, #128 @ 0x80 8013086: 677b str r3, [r7, #116] @ 0x74 8013088: 687b ldr r3, [r7, #4] 801308a: 681b ldr r3, [r3, #0] 801308c: 3314 adds r3, #20 801308e: 6f7a ldr r2, [r7, #116] @ 0x74 8013090: 633a str r2, [r7, #48] @ 0x30 8013092: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013094: 6af9 ldr r1, [r7, #44] @ 0x2c 8013096: 6b3a ldr r2, [r7, #48] @ 0x30 8013098: e841 2300 strex r3, r2, [r1] 801309c: 62bb str r3, [r7, #40] @ 0x28 return(result); 801309e: 6abb ldr r3, [r7, #40] @ 0x28 80130a0: 2b00 cmp r3, #0 80130a2: d1e5 bne.n 8013070 /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) 80130a4: 687b ldr r3, [r7, #4] 80130a6: 6b9b ldr r3, [r3, #56] @ 0x38 80130a8: 2b00 cmp r3, #0 80130aa: d00f beq.n 80130cc { /* UART Tx DMA Abort callback has already been initialised : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA TX */ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) 80130ac: 687b ldr r3, [r7, #4] 80130ae: 6b9b ldr r3, [r3, #56] @ 0x38 80130b0: 4618 mov r0, r3 80130b2: f7fc fe61 bl 800fd78 80130b6: 4603 mov r3, r0 80130b8: 2b00 cmp r3, #0 80130ba: d004 beq.n 80130c6 { huart->hdmatx->XferAbortCallback = NULL; 80130bc: 687b ldr r3, [r7, #4] 80130be: 6b9b ldr r3, [r3, #56] @ 0x38 80130c0: 2200 movs r2, #0 80130c2: 635a str r2, [r3, #52] @ 0x34 80130c4: e002 b.n 80130cc } else { AbortCplt = 0x00U; 80130c6: 2300 movs r3, #0 80130c8: f8c7 3084 str.w r3, [r7, #132] @ 0x84 } } } /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80130cc: 687b ldr r3, [r7, #4] 80130ce: 681b ldr r3, [r3, #0] 80130d0: 695b ldr r3, [r3, #20] 80130d2: f003 0340 and.w r3, r3, #64 @ 0x40 80130d6: 2b00 cmp r3, #0 80130d8: d030 beq.n 801313c { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80130da: 687b ldr r3, [r7, #4] 80130dc: 681b ldr r3, [r3, #0] 80130de: 3314 adds r3, #20 80130e0: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80130e2: 693b ldr r3, [r7, #16] 80130e4: e853 3f00 ldrex r3, [r3] 80130e8: 60fb str r3, [r7, #12] return(result); 80130ea: 68fb ldr r3, [r7, #12] 80130ec: f023 0340 bic.w r3, r3, #64 @ 0x40 80130f0: 673b str r3, [r7, #112] @ 0x70 80130f2: 687b ldr r3, [r7, #4] 80130f4: 681b ldr r3, [r3, #0] 80130f6: 3314 adds r3, #20 80130f8: 6f3a ldr r2, [r7, #112] @ 0x70 80130fa: 61fa str r2, [r7, #28] 80130fc: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80130fe: 69b9 ldr r1, [r7, #24] 8013100: 69fa ldr r2, [r7, #28] 8013102: e841 2300 strex r3, r2, [r1] 8013106: 617b str r3, [r7, #20] return(result); 8013108: 697b ldr r3, [r7, #20] 801310a: 2b00 cmp r3, #0 801310c: d1e5 bne.n 80130da /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) 801310e: 687b ldr r3, [r7, #4] 8013110: 6bdb ldr r3, [r3, #60] @ 0x3c 8013112: 2b00 cmp r3, #0 8013114: d012 beq.n 801313c { /* UART Rx DMA Abort callback has already been initialised : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8013116: 687b ldr r3, [r7, #4] 8013118: 6bdb ldr r3, [r3, #60] @ 0x3c 801311a: 4618 mov r0, r3 801311c: f7fc fe2c bl 800fd78 8013120: 4603 mov r3, r0 8013122: 2b00 cmp r3, #0 8013124: d007 beq.n 8013136 { huart->hdmarx->XferAbortCallback = NULL; 8013126: 687b ldr r3, [r7, #4] 8013128: 6bdb ldr r3, [r3, #60] @ 0x3c 801312a: 2200 movs r2, #0 801312c: 635a str r2, [r3, #52] @ 0x34 AbortCplt = 0x01U; 801312e: 2301 movs r3, #1 8013130: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8013134: e002 b.n 801313c } else { AbortCplt = 0x00U; 8013136: 2300 movs r3, #0 8013138: f8c7 3084 str.w r3, [r7, #132] @ 0x84 } } } /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (AbortCplt == 0x01U) 801313c: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8013140: 2b01 cmp r3, #1 8013142: d116 bne.n 8013172 { /* Reset Tx and Rx transfer counters */ huart->TxXferCount = 0x00U; 8013144: 687b ldr r3, [r7, #4] 8013146: 2200 movs r2, #0 8013148: 84da strh r2, [r3, #38] @ 0x26 huart->RxXferCount = 0x00U; 801314a: 687b ldr r3, [r7, #4] 801314c: 2200 movs r2, #0 801314e: 85da strh r2, [r3, #46] @ 0x2e /* Reset ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8013150: 687b ldr r3, [r7, #4] 8013152: 2200 movs r2, #0 8013154: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; 8013156: 687b ldr r3, [r7, #4] 8013158: 2220 movs r2, #32 801315a: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 801315e: 687b ldr r3, [r7, #4] 8013160: 2220 movs r2, #32 8013162: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013166: 687b ldr r3, [r7, #4] 8013168: 2200 movs r2, #0 801316a: 631a str r2, [r3, #48] @ 0x30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Abort complete callback */ huart->AbortCpltCallback(huart); #else /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); 801316c: 6878 ldr r0, [r7, #4] 801316e: f000 faa4 bl 80136ba #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8013172: 2300 movs r3, #0 } 8013174: 4618 mov r0, r3 8013176: 3788 adds r7, #136 @ 0x88 8013178: 46bd mov sp, r7 801317a: bd80 pop {r7, pc} 801317c: 08013841 .word 0x08013841 8013180: 080138a1 .word 0x080138a1 08013184 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8013184: b580 push {r7, lr} 8013186: b0ba sub sp, #232 @ 0xe8 8013188: af00 add r7, sp, #0 801318a: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 801318c: 687b ldr r3, [r7, #4] 801318e: 681b ldr r3, [r3, #0] 8013190: 681b ldr r3, [r3, #0] 8013192: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8013196: 687b ldr r3, [r7, #4] 8013198: 681b ldr r3, [r3, #0] 801319a: 68db ldr r3, [r3, #12] 801319c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 80131a0: 687b ldr r3, [r7, #4] 80131a2: 681b ldr r3, [r3, #0] 80131a4: 695b ldr r3, [r3, #20] 80131a6: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 80131aa: 2300 movs r3, #0 80131ac: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 80131b0: 2300 movs r3, #0 80131b2: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 80131b6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80131ba: f003 030f and.w r3, r3, #15 80131be: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 80131c2: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 80131c6: 2b00 cmp r3, #0 80131c8: d10f bne.n 80131ea { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 80131ca: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80131ce: f003 0320 and.w r3, r3, #32 80131d2: 2b00 cmp r3, #0 80131d4: d009 beq.n 80131ea 80131d6: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80131da: f003 0320 and.w r3, r3, #32 80131de: 2b00 cmp r3, #0 80131e0: d003 beq.n 80131ea { UART_Receive_IT(huart); 80131e2: 6878 ldr r0, [r7, #4] 80131e4: f000 fbf3 bl 80139ce return; 80131e8: e25b b.n 80136a2 } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 80131ea: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 80131ee: 2b00 cmp r3, #0 80131f0: f000 80de beq.w 80133b0 80131f4: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80131f8: f003 0301 and.w r3, r3, #1 80131fc: 2b00 cmp r3, #0 80131fe: d106 bne.n 801320e || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 8013200: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013204: f403 7390 and.w r3, r3, #288 @ 0x120 8013208: 2b00 cmp r3, #0 801320a: f000 80d1 beq.w 80133b0 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 801320e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013212: f003 0301 and.w r3, r3, #1 8013216: 2b00 cmp r3, #0 8013218: d00b beq.n 8013232 801321a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801321e: f403 7380 and.w r3, r3, #256 @ 0x100 8013222: 2b00 cmp r3, #0 8013224: d005 beq.n 8013232 { huart->ErrorCode |= HAL_UART_ERROR_PE; 8013226: 687b ldr r3, [r7, #4] 8013228: 6c5b ldr r3, [r3, #68] @ 0x44 801322a: f043 0201 orr.w r2, r3, #1 801322e: 687b ldr r3, [r7, #4] 8013230: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8013232: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013236: f003 0304 and.w r3, r3, #4 801323a: 2b00 cmp r3, #0 801323c: d00b beq.n 8013256 801323e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8013242: f003 0301 and.w r3, r3, #1 8013246: 2b00 cmp r3, #0 8013248: d005 beq.n 8013256 { huart->ErrorCode |= HAL_UART_ERROR_NE; 801324a: 687b ldr r3, [r7, #4] 801324c: 6c5b ldr r3, [r3, #68] @ 0x44 801324e: f043 0202 orr.w r2, r3, #2 8013252: 687b ldr r3, [r7, #4] 8013254: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8013256: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801325a: f003 0302 and.w r3, r3, #2 801325e: 2b00 cmp r3, #0 8013260: d00b beq.n 801327a 8013262: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8013266: f003 0301 and.w r3, r3, #1 801326a: 2b00 cmp r3, #0 801326c: d005 beq.n 801327a { huart->ErrorCode |= HAL_UART_ERROR_FE; 801326e: 687b ldr r3, [r7, #4] 8013270: 6c5b ldr r3, [r3, #68] @ 0x44 8013272: f043 0204 orr.w r2, r3, #4 8013276: 687b ldr r3, [r7, #4] 8013278: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 801327a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801327e: f003 0308 and.w r3, r3, #8 8013282: 2b00 cmp r3, #0 8013284: d011 beq.n 80132aa 8013286: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801328a: f003 0320 and.w r3, r3, #32 801328e: 2b00 cmp r3, #0 8013290: d105 bne.n 801329e || ((cr3its & USART_CR3_EIE) != RESET))) 8013292: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8013296: f003 0301 and.w r3, r3, #1 801329a: 2b00 cmp r3, #0 801329c: d005 beq.n 80132aa { huart->ErrorCode |= HAL_UART_ERROR_ORE; 801329e: 687b ldr r3, [r7, #4] 80132a0: 6c5b ldr r3, [r3, #68] @ 0x44 80132a2: f043 0208 orr.w r2, r3, #8 80132a6: 687b ldr r3, [r7, #4] 80132a8: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 80132aa: 687b ldr r3, [r7, #4] 80132ac: 6c5b ldr r3, [r3, #68] @ 0x44 80132ae: 2b00 cmp r3, #0 80132b0: f000 81f2 beq.w 8013698 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 80132b4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80132b8: f003 0320 and.w r3, r3, #32 80132bc: 2b00 cmp r3, #0 80132be: d008 beq.n 80132d2 80132c0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80132c4: f003 0320 and.w r3, r3, #32 80132c8: 2b00 cmp r3, #0 80132ca: d002 beq.n 80132d2 { UART_Receive_IT(huart); 80132cc: 6878 ldr r0, [r7, #4] 80132ce: f000 fb7e bl 80139ce } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 80132d2: 687b ldr r3, [r7, #4] 80132d4: 681b ldr r3, [r3, #0] 80132d6: 695b ldr r3, [r3, #20] 80132d8: f003 0340 and.w r3, r3, #64 @ 0x40 80132dc: 2b00 cmp r3, #0 80132de: bf14 ite ne 80132e0: 2301 movne r3, #1 80132e2: 2300 moveq r3, #0 80132e4: b2db uxtb r3, r3 80132e6: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 80132ea: 687b ldr r3, [r7, #4] 80132ec: 6c5b ldr r3, [r3, #68] @ 0x44 80132ee: f003 0308 and.w r3, r3, #8 80132f2: 2b00 cmp r3, #0 80132f4: d103 bne.n 80132fe 80132f6: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 80132fa: 2b00 cmp r3, #0 80132fc: d04f beq.n 801339e { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 80132fe: 6878 ldr r0, [r7, #4] 8013300: f000 fa28 bl 8013754 /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013304: 687b ldr r3, [r7, #4] 8013306: 681b ldr r3, [r3, #0] 8013308: 695b ldr r3, [r3, #20] 801330a: f003 0340 and.w r3, r3, #64 @ 0x40 801330e: 2b00 cmp r3, #0 8013310: d041 beq.n 8013396 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8013312: 687b ldr r3, [r7, #4] 8013314: 681b ldr r3, [r3, #0] 8013316: 3314 adds r3, #20 8013318: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801331c: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8013320: e853 3f00 ldrex r3, [r3] 8013324: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8013328: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 801332c: f023 0340 bic.w r3, r3, #64 @ 0x40 8013330: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8013334: 687b ldr r3, [r7, #4] 8013336: 681b ldr r3, [r3, #0] 8013338: 3314 adds r3, #20 801333a: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 801333e: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 8013342: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013346: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 801334a: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 801334e: e841 2300 strex r3, r2, [r1] 8013352: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8013356: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 801335a: 2b00 cmp r3, #0 801335c: d1d9 bne.n 8013312 /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 801335e: 687b ldr r3, [r7, #4] 8013360: 6bdb ldr r3, [r3, #60] @ 0x3c 8013362: 2b00 cmp r3, #0 8013364: d013 beq.n 801338e { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8013366: 687b ldr r3, [r7, #4] 8013368: 6bdb ldr r3, [r3, #60] @ 0x3c 801336a: 4a7e ldr r2, [pc, #504] @ (8013564 ) 801336c: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 801336e: 687b ldr r3, [r7, #4] 8013370: 6bdb ldr r3, [r3, #60] @ 0x3c 8013372: 4618 mov r0, r3 8013374: f7fc fd00 bl 800fd78 8013378: 4603 mov r3, r0 801337a: 2b00 cmp r3, #0 801337c: d016 beq.n 80133ac { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 801337e: 687b ldr r3, [r7, #4] 8013380: 6bdb ldr r3, [r3, #60] @ 0x3c 8013382: 6b5b ldr r3, [r3, #52] @ 0x34 8013384: 687a ldr r2, [r7, #4] 8013386: 6bd2 ldr r2, [r2, #60] @ 0x3c 8013388: 4610 mov r0, r2 801338a: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801338c: e00e b.n 80133ac #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 801338e: 6878 ldr r0, [r7, #4] 8013390: f7f8 fc46 bl 800bc20 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013394: e00a b.n 80133ac #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013396: 6878 ldr r0, [r7, #4] 8013398: f7f8 fc42 bl 800bc20 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801339c: e006 b.n 80133ac #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 801339e: 6878 ldr r0, [r7, #4] 80133a0: f7f8 fc3e bl 800bc20 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80133a4: 687b ldr r3, [r7, #4] 80133a6: 2200 movs r2, #0 80133a8: 645a str r2, [r3, #68] @ 0x44 } } return; 80133aa: e175 b.n 8013698 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80133ac: bf00 nop return; 80133ae: e173 b.n 8013698 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80133b0: 687b ldr r3, [r7, #4] 80133b2: 6b1b ldr r3, [r3, #48] @ 0x30 80133b4: 2b01 cmp r3, #1 80133b6: f040 814f bne.w 8013658 && ((isrflags & USART_SR_IDLE) != 0U) 80133ba: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80133be: f003 0310 and.w r3, r3, #16 80133c2: 2b00 cmp r3, #0 80133c4: f000 8148 beq.w 8013658 && ((cr1its & USART_SR_IDLE) != 0U)) 80133c8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80133cc: f003 0310 and.w r3, r3, #16 80133d0: 2b00 cmp r3, #0 80133d2: f000 8141 beq.w 8013658 { __HAL_UART_CLEAR_IDLEFLAG(huart); 80133d6: 2300 movs r3, #0 80133d8: 60bb str r3, [r7, #8] 80133da: 687b ldr r3, [r7, #4] 80133dc: 681b ldr r3, [r3, #0] 80133de: 681b ldr r3, [r3, #0] 80133e0: 60bb str r3, [r7, #8] 80133e2: 687b ldr r3, [r7, #4] 80133e4: 681b ldr r3, [r3, #0] 80133e6: 685b ldr r3, [r3, #4] 80133e8: 60bb str r3, [r7, #8] 80133ea: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80133ec: 687b ldr r3, [r7, #4] 80133ee: 681b ldr r3, [r3, #0] 80133f0: 695b ldr r3, [r3, #20] 80133f2: f003 0340 and.w r3, r3, #64 @ 0x40 80133f6: 2b00 cmp r3, #0 80133f8: f000 80b6 beq.w 8013568 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 80133fc: 687b ldr r3, [r7, #4] 80133fe: 6bdb ldr r3, [r3, #60] @ 0x3c 8013400: 681b ldr r3, [r3, #0] 8013402: 685b ldr r3, [r3, #4] 8013404: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8013408: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 801340c: 2b00 cmp r3, #0 801340e: f000 8145 beq.w 801369c && (nb_remaining_rx_data < huart->RxXferSize)) 8013412: 687b ldr r3, [r7, #4] 8013414: 8d9b ldrh r3, [r3, #44] @ 0x2c 8013416: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 801341a: 429a cmp r2, r3 801341c: f080 813e bcs.w 801369c { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8013420: 687b ldr r3, [r7, #4] 8013422: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8013426: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8013428: 687b ldr r3, [r7, #4] 801342a: 6bdb ldr r3, [r3, #60] @ 0x3c 801342c: 699b ldr r3, [r3, #24] 801342e: 2b20 cmp r3, #32 8013430: f000 8088 beq.w 8013544 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8013434: 687b ldr r3, [r7, #4] 8013436: 681b ldr r3, [r3, #0] 8013438: 330c adds r3, #12 801343a: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801343e: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8013442: e853 3f00 ldrex r3, [r3] 8013446: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 801344a: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 801344e: f423 7380 bic.w r3, r3, #256 @ 0x100 8013452: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8013456: 687b ldr r3, [r7, #4] 8013458: 681b ldr r3, [r3, #0] 801345a: 330c adds r3, #12 801345c: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 8013460: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8013464: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013468: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 801346c: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8013470: e841 2300 strex r3, r2, [r1] 8013474: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8013478: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 801347c: 2b00 cmp r3, #0 801347e: d1d9 bne.n 8013434 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013480: 687b ldr r3, [r7, #4] 8013482: 681b ldr r3, [r3, #0] 8013484: 3314 adds r3, #20 8013486: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013488: 6f7b ldr r3, [r7, #116] @ 0x74 801348a: e853 3f00 ldrex r3, [r3] 801348e: 673b str r3, [r7, #112] @ 0x70 return(result); 8013490: 6f3b ldr r3, [r7, #112] @ 0x70 8013492: f023 0301 bic.w r3, r3, #1 8013496: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 801349a: 687b ldr r3, [r7, #4] 801349c: 681b ldr r3, [r3, #0] 801349e: 3314 adds r3, #20 80134a0: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 80134a4: f8c7 2080 str.w r2, [r7, #128] @ 0x80 80134a8: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80134aa: 6ff9 ldr r1, [r7, #124] @ 0x7c 80134ac: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 80134b0: e841 2300 strex r3, r2, [r1] 80134b4: 67bb str r3, [r7, #120] @ 0x78 return(result); 80134b6: 6fbb ldr r3, [r7, #120] @ 0x78 80134b8: 2b00 cmp r3, #0 80134ba: d1e1 bne.n 8013480 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80134bc: 687b ldr r3, [r7, #4] 80134be: 681b ldr r3, [r3, #0] 80134c0: 3314 adds r3, #20 80134c2: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80134c4: 6e3b ldr r3, [r7, #96] @ 0x60 80134c6: e853 3f00 ldrex r3, [r3] 80134ca: 65fb str r3, [r7, #92] @ 0x5c return(result); 80134cc: 6dfb ldr r3, [r7, #92] @ 0x5c 80134ce: f023 0340 bic.w r3, r3, #64 @ 0x40 80134d2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 80134d6: 687b ldr r3, [r7, #4] 80134d8: 681b ldr r3, [r3, #0] 80134da: 3314 adds r3, #20 80134dc: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 80134e0: 66fa str r2, [r7, #108] @ 0x6c 80134e2: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80134e4: 6eb9 ldr r1, [r7, #104] @ 0x68 80134e6: 6efa ldr r2, [r7, #108] @ 0x6c 80134e8: e841 2300 strex r3, r2, [r1] 80134ec: 667b str r3, [r7, #100] @ 0x64 return(result); 80134ee: 6e7b ldr r3, [r7, #100] @ 0x64 80134f0: 2b00 cmp r3, #0 80134f2: d1e3 bne.n 80134bc /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80134f4: 687b ldr r3, [r7, #4] 80134f6: 2220 movs r2, #32 80134f8: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80134fc: 687b ldr r3, [r7, #4] 80134fe: 2200 movs r2, #0 8013500: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013502: 687b ldr r3, [r7, #4] 8013504: 681b ldr r3, [r3, #0] 8013506: 330c adds r3, #12 8013508: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801350a: 6cfb ldr r3, [r7, #76] @ 0x4c 801350c: e853 3f00 ldrex r3, [r3] 8013510: 64bb str r3, [r7, #72] @ 0x48 return(result); 8013512: 6cbb ldr r3, [r7, #72] @ 0x48 8013514: f023 0310 bic.w r3, r3, #16 8013518: f8c7 30ac str.w r3, [r7, #172] @ 0xac 801351c: 687b ldr r3, [r7, #4] 801351e: 681b ldr r3, [r3, #0] 8013520: 330c adds r3, #12 8013522: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 8013526: 65ba str r2, [r7, #88] @ 0x58 8013528: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801352a: 6d79 ldr r1, [r7, #84] @ 0x54 801352c: 6dba ldr r2, [r7, #88] @ 0x58 801352e: e841 2300 strex r3, r2, [r1] 8013532: 653b str r3, [r7, #80] @ 0x50 return(result); 8013534: 6d3b ldr r3, [r7, #80] @ 0x50 8013536: 2b00 cmp r3, #0 8013538: d1e3 bne.n 8013502 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 801353a: 687b ldr r3, [r7, #4] 801353c: 6bdb ldr r3, [r3, #60] @ 0x3c 801353e: 4618 mov r0, r3 8013540: f7fc fbde bl 800fd00 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8013544: 687b ldr r3, [r7, #4] 8013546: 2202 movs r2, #2 8013548: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 801354a: 687b ldr r3, [r7, #4] 801354c: 8d9a ldrh r2, [r3, #44] @ 0x2c 801354e: 687b ldr r3, [r7, #4] 8013550: 8ddb ldrh r3, [r3, #46] @ 0x2e 8013552: b29b uxth r3, r3 8013554: 1ad3 subs r3, r2, r3 8013556: b29b uxth r3, r3 8013558: 4619 mov r1, r3 801355a: 6878 ldr r0, [r7, #4] 801355c: f7f9 fa44 bl 800c9e8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8013560: e09c b.n 801369c 8013562: bf00 nop 8013564: 08013819 .word 0x08013819 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8013568: 687b ldr r3, [r7, #4] 801356a: 8d9a ldrh r2, [r3, #44] @ 0x2c 801356c: 687b ldr r3, [r7, #4] 801356e: 8ddb ldrh r3, [r3, #46] @ 0x2e 8013570: b29b uxth r3, r3 8013572: 1ad3 subs r3, r2, r3 8013574: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8013578: 687b ldr r3, [r7, #4] 801357a: 8ddb ldrh r3, [r3, #46] @ 0x2e 801357c: b29b uxth r3, r3 801357e: 2b00 cmp r3, #0 8013580: f000 808e beq.w 80136a0 && (nb_rx_data > 0U)) 8013584: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8013588: 2b00 cmp r3, #0 801358a: f000 8089 beq.w 80136a0 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 801358e: 687b ldr r3, [r7, #4] 8013590: 681b ldr r3, [r3, #0] 8013592: 330c adds r3, #12 8013594: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013596: 6bbb ldr r3, [r7, #56] @ 0x38 8013598: e853 3f00 ldrex r3, [r3] 801359c: 637b str r3, [r7, #52] @ 0x34 return(result); 801359e: 6b7b ldr r3, [r7, #52] @ 0x34 80135a0: f423 7390 bic.w r3, r3, #288 @ 0x120 80135a4: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 80135a8: 687b ldr r3, [r7, #4] 80135aa: 681b ldr r3, [r3, #0] 80135ac: 330c adds r3, #12 80135ae: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 80135b2: 647a str r2, [r7, #68] @ 0x44 80135b4: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80135b6: 6c39 ldr r1, [r7, #64] @ 0x40 80135b8: 6c7a ldr r2, [r7, #68] @ 0x44 80135ba: e841 2300 strex r3, r2, [r1] 80135be: 63fb str r3, [r7, #60] @ 0x3c return(result); 80135c0: 6bfb ldr r3, [r7, #60] @ 0x3c 80135c2: 2b00 cmp r3, #0 80135c4: d1e3 bne.n 801358e /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80135c6: 687b ldr r3, [r7, #4] 80135c8: 681b ldr r3, [r3, #0] 80135ca: 3314 adds r3, #20 80135cc: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80135ce: 6a7b ldr r3, [r7, #36] @ 0x24 80135d0: e853 3f00 ldrex r3, [r3] 80135d4: 623b str r3, [r7, #32] return(result); 80135d6: 6a3b ldr r3, [r7, #32] 80135d8: f023 0301 bic.w r3, r3, #1 80135dc: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 80135e0: 687b ldr r3, [r7, #4] 80135e2: 681b ldr r3, [r3, #0] 80135e4: 3314 adds r3, #20 80135e6: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 80135ea: 633a str r2, [r7, #48] @ 0x30 80135ec: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80135ee: 6af9 ldr r1, [r7, #44] @ 0x2c 80135f0: 6b3a ldr r2, [r7, #48] @ 0x30 80135f2: e841 2300 strex r3, r2, [r1] 80135f6: 62bb str r3, [r7, #40] @ 0x28 return(result); 80135f8: 6abb ldr r3, [r7, #40] @ 0x28 80135fa: 2b00 cmp r3, #0 80135fc: d1e3 bne.n 80135c6 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80135fe: 687b ldr r3, [r7, #4] 8013600: 2220 movs r2, #32 8013602: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013606: 687b ldr r3, [r7, #4] 8013608: 2200 movs r2, #0 801360a: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801360c: 687b ldr r3, [r7, #4] 801360e: 681b ldr r3, [r3, #0] 8013610: 330c adds r3, #12 8013612: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013614: 693b ldr r3, [r7, #16] 8013616: e853 3f00 ldrex r3, [r3] 801361a: 60fb str r3, [r7, #12] return(result); 801361c: 68fb ldr r3, [r7, #12] 801361e: f023 0310 bic.w r3, r3, #16 8013622: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8013626: 687b ldr r3, [r7, #4] 8013628: 681b ldr r3, [r3, #0] 801362a: 330c adds r3, #12 801362c: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 8013630: 61fa str r2, [r7, #28] 8013632: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013634: 69b9 ldr r1, [r7, #24] 8013636: 69fa ldr r2, [r7, #28] 8013638: e841 2300 strex r3, r2, [r1] 801363c: 617b str r3, [r7, #20] return(result); 801363e: 697b ldr r3, [r7, #20] 8013640: 2b00 cmp r3, #0 8013642: d1e3 bne.n 801360c /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8013644: 687b ldr r3, [r7, #4] 8013646: 2202 movs r2, #2 8013648: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 801364a: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 801364e: 4619 mov r1, r3 8013650: 6878 ldr r0, [r7, #4] 8013652: f7f9 f9c9 bl 800c9e8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8013656: e023 b.n 80136a0 } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8013658: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801365c: f003 0380 and.w r3, r3, #128 @ 0x80 8013660: 2b00 cmp r3, #0 8013662: d009 beq.n 8013678 8013664: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013668: f003 0380 and.w r3, r3, #128 @ 0x80 801366c: 2b00 cmp r3, #0 801366e: d003 beq.n 8013678 { UART_Transmit_IT(huart); 8013670: 6878 ldr r0, [r7, #4] 8013672: f000 f945 bl 8013900 return; 8013676: e014 b.n 80136a2 } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8013678: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801367c: f003 0340 and.w r3, r3, #64 @ 0x40 8013680: 2b00 cmp r3, #0 8013682: d00e beq.n 80136a2 8013684: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013688: f003 0340 and.w r3, r3, #64 @ 0x40 801368c: 2b00 cmp r3, #0 801368e: d008 beq.n 80136a2 { UART_EndTransmit_IT(huart); 8013690: 6878 ldr r0, [r7, #4] 8013692: f000 f984 bl 801399e return; 8013696: e004 b.n 80136a2 return; 8013698: bf00 nop 801369a: e002 b.n 80136a2 return; 801369c: bf00 nop 801369e: e000 b.n 80136a2 return; 80136a0: bf00 nop } } 80136a2: 37e8 adds r7, #232 @ 0xe8 80136a4: 46bd mov sp, r7 80136a6: bd80 pop {r7, pc} 080136a8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 80136a8: b480 push {r7} 80136aa: b083 sub sp, #12 80136ac: af00 add r7, sp, #0 80136ae: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback could be implemented in the user file */ } 80136b0: bf00 nop 80136b2: 370c adds r7, #12 80136b4: 46bd mov sp, r7 80136b6: bc80 pop {r7} 80136b8: 4770 bx lr 080136ba : * @brief UART Abort Complete callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) { 80136ba: b480 push {r7} 80136bc: b083 sub sp, #12 80136be: af00 add r7, sp, #0 80136c0: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_AbortCpltCallback can be implemented in the user file. */ } 80136c2: bf00 nop 80136c4: 370c adds r7, #12 80136c6: 46bd mov sp, r7 80136c8: bc80 pop {r7} 80136ca: 4770 bx lr 080136cc : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART. * @retval UART Error Code */ uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) { 80136cc: b480 push {r7} 80136ce: b083 sub sp, #12 80136d0: af00 add r7, sp, #0 80136d2: 6078 str r0, [r7, #4] return huart->ErrorCode; 80136d4: 687b ldr r3, [r7, #4] 80136d6: 6c5b ldr r3, [r3, #68] @ 0x44 } 80136d8: 4618 mov r0, r3 80136da: 370c adds r7, #12 80136dc: 46bd mov sp, r7 80136de: bc80 pop {r7} 80136e0: 4770 bx lr 080136e2 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80136e2: b480 push {r7} 80136e4: b085 sub sp, #20 80136e6: af00 add r7, sp, #0 80136e8: 60f8 str r0, [r7, #12] 80136ea: 60b9 str r1, [r7, #8] 80136ec: 4613 mov r3, r2 80136ee: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 80136f0: 68fb ldr r3, [r7, #12] 80136f2: 68ba ldr r2, [r7, #8] 80136f4: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 80136f6: 68fb ldr r3, [r7, #12] 80136f8: 88fa ldrh r2, [r7, #6] 80136fa: 859a strh r2, [r3, #44] @ 0x2c huart->RxXferCount = Size; 80136fc: 68fb ldr r3, [r7, #12] 80136fe: 88fa ldrh r2, [r7, #6] 8013700: 85da strh r2, [r3, #46] @ 0x2e huart->ErrorCode = HAL_UART_ERROR_NONE; 8013702: 68fb ldr r3, [r7, #12] 8013704: 2200 movs r2, #0 8013706: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 8013708: 68fb ldr r3, [r7, #12] 801370a: 2222 movs r2, #34 @ 0x22 801370c: f883 2042 strb.w r2, [r3, #66] @ 0x42 if (huart->Init.Parity != UART_PARITY_NONE) 8013710: 68fb ldr r3, [r7, #12] 8013712: 691b ldr r3, [r3, #16] 8013714: 2b00 cmp r3, #0 8013716: d007 beq.n 8013728 { /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); 8013718: 68fb ldr r3, [r7, #12] 801371a: 681b ldr r3, [r3, #0] 801371c: 68da ldr r2, [r3, #12] 801371e: 68fb ldr r3, [r7, #12] 8013720: 681b ldr r3, [r3, #0] 8013722: f442 7280 orr.w r2, r2, #256 @ 0x100 8013726: 60da str r2, [r3, #12] } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); 8013728: 68fb ldr r3, [r7, #12] 801372a: 681b ldr r3, [r3, #0] 801372c: 695a ldr r2, [r3, #20] 801372e: 68fb ldr r3, [r7, #12] 8013730: 681b ldr r3, [r3, #0] 8013732: f042 0201 orr.w r2, r2, #1 8013736: 615a str r2, [r3, #20] /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); 8013738: 68fb ldr r3, [r7, #12] 801373a: 681b ldr r3, [r3, #0] 801373c: 68da ldr r2, [r3, #12] 801373e: 68fb ldr r3, [r7, #12] 8013740: 681b ldr r3, [r3, #0] 8013742: f042 0220 orr.w r2, r2, #32 8013746: 60da str r2, [r3, #12] return HAL_OK; 8013748: 2300 movs r3, #0 } 801374a: 4618 mov r0, r3 801374c: 3714 adds r7, #20 801374e: 46bd mov sp, r7 8013750: bc80 pop {r7} 8013752: 4770 bx lr 08013754 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8013754: b480 push {r7} 8013756: b095 sub sp, #84 @ 0x54 8013758: af00 add r7, sp, #0 801375a: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 801375c: 687b ldr r3, [r7, #4] 801375e: 681b ldr r3, [r3, #0] 8013760: 330c adds r3, #12 8013762: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013764: 6b7b ldr r3, [r7, #52] @ 0x34 8013766: e853 3f00 ldrex r3, [r3] 801376a: 633b str r3, [r7, #48] @ 0x30 return(result); 801376c: 6b3b ldr r3, [r7, #48] @ 0x30 801376e: f423 7390 bic.w r3, r3, #288 @ 0x120 8013772: 64fb str r3, [r7, #76] @ 0x4c 8013774: 687b ldr r3, [r7, #4] 8013776: 681b ldr r3, [r3, #0] 8013778: 330c adds r3, #12 801377a: 6cfa ldr r2, [r7, #76] @ 0x4c 801377c: 643a str r2, [r7, #64] @ 0x40 801377e: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013780: 6bf9 ldr r1, [r7, #60] @ 0x3c 8013782: 6c3a ldr r2, [r7, #64] @ 0x40 8013784: e841 2300 strex r3, r2, [r1] 8013788: 63bb str r3, [r7, #56] @ 0x38 return(result); 801378a: 6bbb ldr r3, [r7, #56] @ 0x38 801378c: 2b00 cmp r3, #0 801378e: d1e5 bne.n 801375c ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013790: 687b ldr r3, [r7, #4] 8013792: 681b ldr r3, [r3, #0] 8013794: 3314 adds r3, #20 8013796: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013798: 6a3b ldr r3, [r7, #32] 801379a: e853 3f00 ldrex r3, [r3] 801379e: 61fb str r3, [r7, #28] return(result); 80137a0: 69fb ldr r3, [r7, #28] 80137a2: f023 0301 bic.w r3, r3, #1 80137a6: 64bb str r3, [r7, #72] @ 0x48 80137a8: 687b ldr r3, [r7, #4] 80137aa: 681b ldr r3, [r3, #0] 80137ac: 3314 adds r3, #20 80137ae: 6cba ldr r2, [r7, #72] @ 0x48 80137b0: 62fa str r2, [r7, #44] @ 0x2c 80137b2: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80137b4: 6ab9 ldr r1, [r7, #40] @ 0x28 80137b6: 6afa ldr r2, [r7, #44] @ 0x2c 80137b8: e841 2300 strex r3, r2, [r1] 80137bc: 627b str r3, [r7, #36] @ 0x24 return(result); 80137be: 6a7b ldr r3, [r7, #36] @ 0x24 80137c0: 2b00 cmp r3, #0 80137c2: d1e5 bne.n 8013790 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80137c4: 687b ldr r3, [r7, #4] 80137c6: 6b1b ldr r3, [r3, #48] @ 0x30 80137c8: 2b01 cmp r3, #1 80137ca: d119 bne.n 8013800 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80137cc: 687b ldr r3, [r7, #4] 80137ce: 681b ldr r3, [r3, #0] 80137d0: 330c adds r3, #12 80137d2: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80137d4: 68fb ldr r3, [r7, #12] 80137d6: e853 3f00 ldrex r3, [r3] 80137da: 60bb str r3, [r7, #8] return(result); 80137dc: 68bb ldr r3, [r7, #8] 80137de: f023 0310 bic.w r3, r3, #16 80137e2: 647b str r3, [r7, #68] @ 0x44 80137e4: 687b ldr r3, [r7, #4] 80137e6: 681b ldr r3, [r3, #0] 80137e8: 330c adds r3, #12 80137ea: 6c7a ldr r2, [r7, #68] @ 0x44 80137ec: 61ba str r2, [r7, #24] 80137ee: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80137f0: 6979 ldr r1, [r7, #20] 80137f2: 69ba ldr r2, [r7, #24] 80137f4: e841 2300 strex r3, r2, [r1] 80137f8: 613b str r3, [r7, #16] return(result); 80137fa: 693b ldr r3, [r7, #16] 80137fc: 2b00 cmp r3, #0 80137fe: d1e5 bne.n 80137cc } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013800: 687b ldr r3, [r7, #4] 8013802: 2220 movs r2, #32 8013804: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013808: 687b ldr r3, [r7, #4] 801380a: 2200 movs r2, #0 801380c: 631a str r2, [r3, #48] @ 0x30 } 801380e: bf00 nop 8013810: 3754 adds r7, #84 @ 0x54 8013812: 46bd mov sp, r7 8013814: bc80 pop {r7} 8013816: 4770 bx lr 08013818 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8013818: b580 push {r7, lr} 801381a: b084 sub sp, #16 801381c: af00 add r7, sp, #0 801381e: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013820: 687b ldr r3, [r7, #4] 8013822: 6a5b ldr r3, [r3, #36] @ 0x24 8013824: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 8013826: 68fb ldr r3, [r7, #12] 8013828: 2200 movs r2, #0 801382a: 85da strh r2, [r3, #46] @ 0x2e huart->TxXferCount = 0x00U; 801382c: 68fb ldr r3, [r7, #12] 801382e: 2200 movs r2, #0 8013830: 84da strh r2, [r3, #38] @ 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013832: 68f8 ldr r0, [r7, #12] 8013834: f7f8 f9f4 bl 800bc20 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8013838: bf00 nop 801383a: 3710 adds r7, #16 801383c: 46bd mov sp, r7 801383e: bd80 pop {r7, pc} 08013840 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { 8013840: b580 push {r7, lr} 8013842: b084 sub sp, #16 8013844: af00 add r7, sp, #0 8013846: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013848: 687b ldr r3, [r7, #4] 801384a: 6a5b ldr r3, [r3, #36] @ 0x24 801384c: 60fb str r3, [r7, #12] huart->hdmatx->XferAbortCallback = NULL; 801384e: 68fb ldr r3, [r7, #12] 8013850: 6b9b ldr r3, [r3, #56] @ 0x38 8013852: 2200 movs r2, #0 8013854: 635a str r2, [r3, #52] @ 0x34 /* Check if an Abort process is still ongoing */ if (huart->hdmarx != NULL) 8013856: 68fb ldr r3, [r7, #12] 8013858: 6bdb ldr r3, [r3, #60] @ 0x3c 801385a: 2b00 cmp r3, #0 801385c: d004 beq.n 8013868 { if (huart->hdmarx->XferAbortCallback != NULL) 801385e: 68fb ldr r3, [r7, #12] 8013860: 6bdb ldr r3, [r3, #60] @ 0x3c 8013862: 6b5b ldr r3, [r3, #52] @ 0x34 8013864: 2b00 cmp r3, #0 8013866: d117 bne.n 8013898 return; } } /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ huart->TxXferCount = 0x00U; 8013868: 68fb ldr r3, [r7, #12] 801386a: 2200 movs r2, #0 801386c: 84da strh r2, [r3, #38] @ 0x26 huart->RxXferCount = 0x00U; 801386e: 68fb ldr r3, [r7, #12] 8013870: 2200 movs r2, #0 8013872: 85da strh r2, [r3, #46] @ 0x2e /* Reset ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8013874: 68fb ldr r3, [r7, #12] 8013876: 2200 movs r2, #0 8013878: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; 801387a: 68fb ldr r3, [r7, #12] 801387c: 2220 movs r2, #32 801387e: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8013882: 68fb ldr r3, [r7, #12] 8013884: 2220 movs r2, #32 8013886: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 801388a: 68fb ldr r3, [r7, #12] 801388c: 2200 movs r2, #0 801388e: 631a str r2, [r3, #48] @ 0x30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Abort complete callback */ huart->AbortCpltCallback(huart); #else /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); 8013890: 68f8 ldr r0, [r7, #12] 8013892: f7ff ff12 bl 80136ba 8013896: e000 b.n 801389a return; 8013898: bf00 nop #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 801389a: 3710 adds r7, #16 801389c: 46bd mov sp, r7 801389e: bd80 pop {r7, pc} 080138a0 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { 80138a0: b580 push {r7, lr} 80138a2: b084 sub sp, #16 80138a4: af00 add r7, sp, #0 80138a6: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80138a8: 687b ldr r3, [r7, #4] 80138aa: 6a5b ldr r3, [r3, #36] @ 0x24 80138ac: 60fb str r3, [r7, #12] huart->hdmarx->XferAbortCallback = NULL; 80138ae: 68fb ldr r3, [r7, #12] 80138b0: 6bdb ldr r3, [r3, #60] @ 0x3c 80138b2: 2200 movs r2, #0 80138b4: 635a str r2, [r3, #52] @ 0x34 /* Check if an Abort process is still ongoing */ if (huart->hdmatx != NULL) 80138b6: 68fb ldr r3, [r7, #12] 80138b8: 6b9b ldr r3, [r3, #56] @ 0x38 80138ba: 2b00 cmp r3, #0 80138bc: d004 beq.n 80138c8 { if (huart->hdmatx->XferAbortCallback != NULL) 80138be: 68fb ldr r3, [r7, #12] 80138c0: 6b9b ldr r3, [r3, #56] @ 0x38 80138c2: 6b5b ldr r3, [r3, #52] @ 0x34 80138c4: 2b00 cmp r3, #0 80138c6: d117 bne.n 80138f8 return; } } /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ huart->TxXferCount = 0x00U; 80138c8: 68fb ldr r3, [r7, #12] 80138ca: 2200 movs r2, #0 80138cc: 84da strh r2, [r3, #38] @ 0x26 huart->RxXferCount = 0x00U; 80138ce: 68fb ldr r3, [r7, #12] 80138d0: 2200 movs r2, #0 80138d2: 85da strh r2, [r3, #46] @ 0x2e /* Reset ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80138d4: 68fb ldr r3, [r7, #12] 80138d6: 2200 movs r2, #0 80138d8: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; 80138da: 68fb ldr r3, [r7, #12] 80138dc: 2220 movs r2, #32 80138de: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 80138e2: 68fb ldr r3, [r7, #12] 80138e4: 2220 movs r2, #32 80138e6: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80138ea: 68fb ldr r3, [r7, #12] 80138ec: 2200 movs r2, #0 80138ee: 631a str r2, [r3, #48] @ 0x30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Abort complete callback */ huart->AbortCpltCallback(huart); #else /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); 80138f0: 68f8 ldr r0, [r7, #12] 80138f2: f7ff fee2 bl 80136ba 80138f6: e000 b.n 80138fa return; 80138f8: bf00 nop #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80138fa: 3710 adds r7, #16 80138fc: 46bd mov sp, r7 80138fe: bd80 pop {r7, pc} 08013900 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 8013900: b480 push {r7} 8013902: b085 sub sp, #20 8013904: af00 add r7, sp, #0 8013906: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8013908: 687b ldr r3, [r7, #4] 801390a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 801390e: b2db uxtb r3, r3 8013910: 2b21 cmp r3, #33 @ 0x21 8013912: d13e bne.n 8013992 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8013914: 687b ldr r3, [r7, #4] 8013916: 689b ldr r3, [r3, #8] 8013918: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 801391c: d114 bne.n 8013948 801391e: 687b ldr r3, [r7, #4] 8013920: 691b ldr r3, [r3, #16] 8013922: 2b00 cmp r3, #0 8013924: d110 bne.n 8013948 { tmp = (const uint16_t *) huart->pTxBuffPtr; 8013926: 687b ldr r3, [r7, #4] 8013928: 6a1b ldr r3, [r3, #32] 801392a: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 801392c: 68fb ldr r3, [r7, #12] 801392e: 881b ldrh r3, [r3, #0] 8013930: 461a mov r2, r3 8013932: 687b ldr r3, [r7, #4] 8013934: 681b ldr r3, [r3, #0] 8013936: f3c2 0208 ubfx r2, r2, #0, #9 801393a: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 801393c: 687b ldr r3, [r7, #4] 801393e: 6a1b ldr r3, [r3, #32] 8013940: 1c9a adds r2, r3, #2 8013942: 687b ldr r3, [r7, #4] 8013944: 621a str r2, [r3, #32] 8013946: e008 b.n 801395a } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 8013948: 687b ldr r3, [r7, #4] 801394a: 6a1b ldr r3, [r3, #32] 801394c: 1c59 adds r1, r3, #1 801394e: 687a ldr r2, [r7, #4] 8013950: 6211 str r1, [r2, #32] 8013952: 781a ldrb r2, [r3, #0] 8013954: 687b ldr r3, [r7, #4] 8013956: 681b ldr r3, [r3, #0] 8013958: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 801395a: 687b ldr r3, [r7, #4] 801395c: 8cdb ldrh r3, [r3, #38] @ 0x26 801395e: b29b uxth r3, r3 8013960: 3b01 subs r3, #1 8013962: b29b uxth r3, r3 8013964: 687a ldr r2, [r7, #4] 8013966: 4619 mov r1, r3 8013968: 84d1 strh r1, [r2, #38] @ 0x26 801396a: 2b00 cmp r3, #0 801396c: d10f bne.n 801398e { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 801396e: 687b ldr r3, [r7, #4] 8013970: 681b ldr r3, [r3, #0] 8013972: 68da ldr r2, [r3, #12] 8013974: 687b ldr r3, [r7, #4] 8013976: 681b ldr r3, [r3, #0] 8013978: f022 0280 bic.w r2, r2, #128 @ 0x80 801397c: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 801397e: 687b ldr r3, [r7, #4] 8013980: 681b ldr r3, [r3, #0] 8013982: 68da ldr r2, [r3, #12] 8013984: 687b ldr r3, [r7, #4] 8013986: 681b ldr r3, [r3, #0] 8013988: f042 0240 orr.w r2, r2, #64 @ 0x40 801398c: 60da str r2, [r3, #12] } return HAL_OK; 801398e: 2300 movs r3, #0 8013990: e000 b.n 8013994 } else { return HAL_BUSY; 8013992: 2302 movs r3, #2 } } 8013994: 4618 mov r0, r3 8013996: 3714 adds r7, #20 8013998: 46bd mov sp, r7 801399a: bc80 pop {r7} 801399c: 4770 bx lr 0801399e : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 801399e: b580 push {r7, lr} 80139a0: b082 sub sp, #8 80139a2: af00 add r7, sp, #0 80139a4: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 80139a6: 687b ldr r3, [r7, #4] 80139a8: 681b ldr r3, [r3, #0] 80139aa: 68da ldr r2, [r3, #12] 80139ac: 687b ldr r3, [r7, #4] 80139ae: 681b ldr r3, [r3, #0] 80139b0: f022 0240 bic.w r2, r2, #64 @ 0x40 80139b4: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80139b6: 687b ldr r3, [r7, #4] 80139b8: 2220 movs r2, #32 80139ba: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 80139be: 6878 ldr r0, [r7, #4] 80139c0: f7f9 f87a bl 800cab8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 80139c4: 2300 movs r3, #0 } 80139c6: 4618 mov r0, r3 80139c8: 3708 adds r7, #8 80139ca: 46bd mov sp, r7 80139cc: bd80 pop {r7, pc} 080139ce : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 80139ce: b580 push {r7, lr} 80139d0: b08c sub sp, #48 @ 0x30 80139d2: af00 add r7, sp, #0 80139d4: 6078 str r0, [r7, #4] uint8_t *pdata8bits; uint16_t *pdata16bits; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80139d6: 687b ldr r3, [r7, #4] 80139d8: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 80139dc: b2db uxtb r3, r3 80139de: 2b22 cmp r3, #34 @ 0x22 80139e0: f040 80ae bne.w 8013b40 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80139e4: 687b ldr r3, [r7, #4] 80139e6: 689b ldr r3, [r3, #8] 80139e8: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80139ec: d117 bne.n 8013a1e 80139ee: 687b ldr r3, [r7, #4] 80139f0: 691b ldr r3, [r3, #16] 80139f2: 2b00 cmp r3, #0 80139f4: d113 bne.n 8013a1e { pdata8bits = NULL; 80139f6: 2300 movs r3, #0 80139f8: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = (uint16_t *) huart->pRxBuffPtr; 80139fa: 687b ldr r3, [r7, #4] 80139fc: 6a9b ldr r3, [r3, #40] @ 0x28 80139fe: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8013a00: 687b ldr r3, [r7, #4] 8013a02: 681b ldr r3, [r3, #0] 8013a04: 685b ldr r3, [r3, #4] 8013a06: b29b uxth r3, r3 8013a08: f3c3 0308 ubfx r3, r3, #0, #9 8013a0c: b29a uxth r2, r3 8013a0e: 6abb ldr r3, [r7, #40] @ 0x28 8013a10: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8013a12: 687b ldr r3, [r7, #4] 8013a14: 6a9b ldr r3, [r3, #40] @ 0x28 8013a16: 1c9a adds r2, r3, #2 8013a18: 687b ldr r3, [r7, #4] 8013a1a: 629a str r2, [r3, #40] @ 0x28 8013a1c: e026 b.n 8013a6c } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8013a1e: 687b ldr r3, [r7, #4] 8013a20: 6a9b ldr r3, [r3, #40] @ 0x28 8013a22: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = NULL; 8013a24: 2300 movs r3, #0 8013a26: 62bb str r3, [r7, #40] @ 0x28 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 8013a28: 687b ldr r3, [r7, #4] 8013a2a: 689b ldr r3, [r3, #8] 8013a2c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8013a30: d007 beq.n 8013a42 8013a32: 687b ldr r3, [r7, #4] 8013a34: 689b ldr r3, [r3, #8] 8013a36: 2b00 cmp r3, #0 8013a38: d10a bne.n 8013a50 8013a3a: 687b ldr r3, [r7, #4] 8013a3c: 691b ldr r3, [r3, #16] 8013a3e: 2b00 cmp r3, #0 8013a40: d106 bne.n 8013a50 { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8013a42: 687b ldr r3, [r7, #4] 8013a44: 681b ldr r3, [r3, #0] 8013a46: 685b ldr r3, [r3, #4] 8013a48: b2da uxtb r2, r3 8013a4a: 6afb ldr r3, [r7, #44] @ 0x2c 8013a4c: 701a strb r2, [r3, #0] 8013a4e: e008 b.n 8013a62 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8013a50: 687b ldr r3, [r7, #4] 8013a52: 681b ldr r3, [r3, #0] 8013a54: 685b ldr r3, [r3, #4] 8013a56: b2db uxtb r3, r3 8013a58: f003 037f and.w r3, r3, #127 @ 0x7f 8013a5c: b2da uxtb r2, r3 8013a5e: 6afb ldr r3, [r7, #44] @ 0x2c 8013a60: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 8013a62: 687b ldr r3, [r7, #4] 8013a64: 6a9b ldr r3, [r3, #40] @ 0x28 8013a66: 1c5a adds r2, r3, #1 8013a68: 687b ldr r3, [r7, #4] 8013a6a: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 8013a6c: 687b ldr r3, [r7, #4] 8013a6e: 8ddb ldrh r3, [r3, #46] @ 0x2e 8013a70: b29b uxth r3, r3 8013a72: 3b01 subs r3, #1 8013a74: b29b uxth r3, r3 8013a76: 687a ldr r2, [r7, #4] 8013a78: 4619 mov r1, r3 8013a7a: 85d1 strh r1, [r2, #46] @ 0x2e 8013a7c: 2b00 cmp r3, #0 8013a7e: d15d bne.n 8013b3c { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8013a80: 687b ldr r3, [r7, #4] 8013a82: 681b ldr r3, [r3, #0] 8013a84: 68da ldr r2, [r3, #12] 8013a86: 687b ldr r3, [r7, #4] 8013a88: 681b ldr r3, [r3, #0] 8013a8a: f022 0220 bic.w r2, r2, #32 8013a8e: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8013a90: 687b ldr r3, [r7, #4] 8013a92: 681b ldr r3, [r3, #0] 8013a94: 68da ldr r2, [r3, #12] 8013a96: 687b ldr r3, [r7, #4] 8013a98: 681b ldr r3, [r3, #0] 8013a9a: f422 7280 bic.w r2, r2, #256 @ 0x100 8013a9e: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8013aa0: 687b ldr r3, [r7, #4] 8013aa2: 681b ldr r3, [r3, #0] 8013aa4: 695a ldr r2, [r3, #20] 8013aa6: 687b ldr r3, [r7, #4] 8013aa8: 681b ldr r3, [r3, #0] 8013aaa: f022 0201 bic.w r2, r2, #1 8013aae: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013ab0: 687b ldr r3, [r7, #4] 8013ab2: 2220 movs r2, #32 8013ab4: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8013ab8: 687b ldr r3, [r7, #4] 8013aba: 2200 movs r2, #0 8013abc: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013abe: 687b ldr r3, [r7, #4] 8013ac0: 6b1b ldr r3, [r3, #48] @ 0x30 8013ac2: 2b01 cmp r3, #1 8013ac4: d135 bne.n 8013b32 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013ac6: 687b ldr r3, [r7, #4] 8013ac8: 2200 movs r2, #0 8013aca: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013acc: 687b ldr r3, [r7, #4] 8013ace: 681b ldr r3, [r3, #0] 8013ad0: 330c adds r3, #12 8013ad2: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013ad4: 697b ldr r3, [r7, #20] 8013ad6: e853 3f00 ldrex r3, [r3] 8013ada: 613b str r3, [r7, #16] return(result); 8013adc: 693b ldr r3, [r7, #16] 8013ade: f023 0310 bic.w r3, r3, #16 8013ae2: 627b str r3, [r7, #36] @ 0x24 8013ae4: 687b ldr r3, [r7, #4] 8013ae6: 681b ldr r3, [r3, #0] 8013ae8: 330c adds r3, #12 8013aea: 6a7a ldr r2, [r7, #36] @ 0x24 8013aec: 623a str r2, [r7, #32] 8013aee: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013af0: 69f9 ldr r1, [r7, #28] 8013af2: 6a3a ldr r2, [r7, #32] 8013af4: e841 2300 strex r3, r2, [r1] 8013af8: 61bb str r3, [r7, #24] return(result); 8013afa: 69bb ldr r3, [r7, #24] 8013afc: 2b00 cmp r3, #0 8013afe: d1e5 bne.n 8013acc /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 8013b00: 687b ldr r3, [r7, #4] 8013b02: 681b ldr r3, [r3, #0] 8013b04: 681b ldr r3, [r3, #0] 8013b06: f003 0310 and.w r3, r3, #16 8013b0a: 2b10 cmp r3, #16 8013b0c: d10a bne.n 8013b24 { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 8013b0e: 2300 movs r3, #0 8013b10: 60fb str r3, [r7, #12] 8013b12: 687b ldr r3, [r7, #4] 8013b14: 681b ldr r3, [r3, #0] 8013b16: 681b ldr r3, [r3, #0] 8013b18: 60fb str r3, [r7, #12] 8013b1a: 687b ldr r3, [r7, #4] 8013b1c: 681b ldr r3, [r3, #0] 8013b1e: 685b ldr r3, [r3, #4] 8013b20: 60fb str r3, [r7, #12] 8013b22: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8013b24: 687b ldr r3, [r7, #4] 8013b26: 8d9b ldrh r3, [r3, #44] @ 0x2c 8013b28: 4619 mov r1, r3 8013b2a: 6878 ldr r0, [r7, #4] 8013b2c: f7f8 ff5c bl 800c9e8 8013b30: e002 b.n 8013b38 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8013b32: 6878 ldr r0, [r7, #4] 8013b34: f7ff fdb8 bl 80136a8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8013b38: 2300 movs r3, #0 8013b3a: e002 b.n 8013b42 } return HAL_OK; 8013b3c: 2300 movs r3, #0 8013b3e: e000 b.n 8013b42 } else { return HAL_BUSY; 8013b40: 2302 movs r3, #2 } } 8013b42: 4618 mov r0, r3 8013b44: 3730 adds r7, #48 @ 0x30 8013b46: 46bd mov sp, r7 8013b48: bd80 pop {r7, pc} ... 08013b4c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8013b4c: b580 push {r7, lr} 8013b4e: b084 sub sp, #16 8013b50: af00 add r7, sp, #0 8013b52: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8013b54: 687b ldr r3, [r7, #4] 8013b56: 681b ldr r3, [r3, #0] 8013b58: 691b ldr r3, [r3, #16] 8013b5a: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8013b5e: 687b ldr r3, [r7, #4] 8013b60: 68da ldr r2, [r3, #12] 8013b62: 687b ldr r3, [r7, #4] 8013b64: 681b ldr r3, [r3, #0] 8013b66: 430a orrs r2, r1 8013b68: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 8013b6a: 687b ldr r3, [r7, #4] 8013b6c: 689a ldr r2, [r3, #8] 8013b6e: 687b ldr r3, [r7, #4] 8013b70: 691b ldr r3, [r3, #16] 8013b72: 431a orrs r2, r3 8013b74: 687b ldr r3, [r7, #4] 8013b76: 695b ldr r3, [r3, #20] 8013b78: 4313 orrs r3, r2 8013b7a: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 8013b7c: 687b ldr r3, [r7, #4] 8013b7e: 681b ldr r3, [r3, #0] 8013b80: 68db ldr r3, [r3, #12] 8013b82: f423 53b0 bic.w r3, r3, #5632 @ 0x1600 8013b86: f023 030c bic.w r3, r3, #12 8013b8a: 687a ldr r2, [r7, #4] 8013b8c: 6812 ldr r2, [r2, #0] 8013b8e: 68b9 ldr r1, [r7, #8] 8013b90: 430b orrs r3, r1 8013b92: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8013b94: 687b ldr r3, [r7, #4] 8013b96: 681b ldr r3, [r3, #0] 8013b98: 695b ldr r3, [r3, #20] 8013b9a: f423 7140 bic.w r1, r3, #768 @ 0x300 8013b9e: 687b ldr r3, [r7, #4] 8013ba0: 699a ldr r2, [r3, #24] 8013ba2: 687b ldr r3, [r7, #4] 8013ba4: 681b ldr r3, [r3, #0] 8013ba6: 430a orrs r2, r1 8013ba8: 615a str r2, [r3, #20] if(huart->Instance == USART1) 8013baa: 687b ldr r3, [r7, #4] 8013bac: 681b ldr r3, [r3, #0] 8013bae: 4a2c ldr r2, [pc, #176] @ (8013c60 ) 8013bb0: 4293 cmp r3, r2 8013bb2: d103 bne.n 8013bbc { pclk = HAL_RCC_GetPCLK2Freq(); 8013bb4: f7fd fc78 bl 80114a8 8013bb8: 60f8 str r0, [r7, #12] 8013bba: e002 b.n 8013bc2 } else { pclk = HAL_RCC_GetPCLK1Freq(); 8013bbc: f7fd fc60 bl 8011480 8013bc0: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8013bc2: 68fa ldr r2, [r7, #12] 8013bc4: 4613 mov r3, r2 8013bc6: 009b lsls r3, r3, #2 8013bc8: 4413 add r3, r2 8013bca: 009a lsls r2, r3, #2 8013bcc: 441a add r2, r3 8013bce: 687b ldr r3, [r7, #4] 8013bd0: 685b ldr r3, [r3, #4] 8013bd2: 009b lsls r3, r3, #2 8013bd4: fbb2 f3f3 udiv r3, r2, r3 8013bd8: 4a22 ldr r2, [pc, #136] @ (8013c64 ) 8013bda: fba2 2303 umull r2, r3, r2, r3 8013bde: 095b lsrs r3, r3, #5 8013be0: 0119 lsls r1, r3, #4 8013be2: 68fa ldr r2, [r7, #12] 8013be4: 4613 mov r3, r2 8013be6: 009b lsls r3, r3, #2 8013be8: 4413 add r3, r2 8013bea: 009a lsls r2, r3, #2 8013bec: 441a add r2, r3 8013bee: 687b ldr r3, [r7, #4] 8013bf0: 685b ldr r3, [r3, #4] 8013bf2: 009b lsls r3, r3, #2 8013bf4: fbb2 f2f3 udiv r2, r2, r3 8013bf8: 4b1a ldr r3, [pc, #104] @ (8013c64 ) 8013bfa: fba3 0302 umull r0, r3, r3, r2 8013bfe: 095b lsrs r3, r3, #5 8013c00: 2064 movs r0, #100 @ 0x64 8013c02: fb00 f303 mul.w r3, r0, r3 8013c06: 1ad3 subs r3, r2, r3 8013c08: 011b lsls r3, r3, #4 8013c0a: 3332 adds r3, #50 @ 0x32 8013c0c: 4a15 ldr r2, [pc, #84] @ (8013c64 ) 8013c0e: fba2 2303 umull r2, r3, r2, r3 8013c12: 095b lsrs r3, r3, #5 8013c14: f003 03f0 and.w r3, r3, #240 @ 0xf0 8013c18: 4419 add r1, r3 8013c1a: 68fa ldr r2, [r7, #12] 8013c1c: 4613 mov r3, r2 8013c1e: 009b lsls r3, r3, #2 8013c20: 4413 add r3, r2 8013c22: 009a lsls r2, r3, #2 8013c24: 441a add r2, r3 8013c26: 687b ldr r3, [r7, #4] 8013c28: 685b ldr r3, [r3, #4] 8013c2a: 009b lsls r3, r3, #2 8013c2c: fbb2 f2f3 udiv r2, r2, r3 8013c30: 4b0c ldr r3, [pc, #48] @ (8013c64 ) 8013c32: fba3 0302 umull r0, r3, r3, r2 8013c36: 095b lsrs r3, r3, #5 8013c38: 2064 movs r0, #100 @ 0x64 8013c3a: fb00 f303 mul.w r3, r0, r3 8013c3e: 1ad3 subs r3, r2, r3 8013c40: 011b lsls r3, r3, #4 8013c42: 3332 adds r3, #50 @ 0x32 8013c44: 4a07 ldr r2, [pc, #28] @ (8013c64 ) 8013c46: fba2 2303 umull r2, r3, r2, r3 8013c4a: 095b lsrs r3, r3, #5 8013c4c: f003 020f and.w r2, r3, #15 8013c50: 687b ldr r3, [r7, #4] 8013c52: 681b ldr r3, [r3, #0] 8013c54: 440a add r2, r1 8013c56: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 8013c58: bf00 nop 8013c5a: 3710 adds r7, #16 8013c5c: 46bd mov sp, r7 8013c5e: bd80 pop {r7, pc} 8013c60: 40013800 .word 0x40013800 8013c64: 51eb851f .word 0x51eb851f 08013c68 <__cvt>: 8013c68: 2b00 cmp r3, #0 8013c6a: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8013c6e: 461d mov r5, r3 8013c70: bfbb ittet lt 8013c72: f103 4300 addlt.w r3, r3, #2147483648 @ 0x80000000 8013c76: 461d movlt r5, r3 8013c78: 2300 movge r3, #0 8013c7a: 232d movlt r3, #45 @ 0x2d 8013c7c: b088 sub sp, #32 8013c7e: 4614 mov r4, r2 8013c80: bfb8 it lt 8013c82: 4614 movlt r4, r2 8013c84: 9a12 ldr r2, [sp, #72] @ 0x48 8013c86: 9e10 ldr r6, [sp, #64] @ 0x40 8013c88: 7013 strb r3, [r2, #0] 8013c8a: 9b14 ldr r3, [sp, #80] @ 0x50 8013c8c: f8dd a04c ldr.w sl, [sp, #76] @ 0x4c 8013c90: f023 0820 bic.w r8, r3, #32 8013c94: f1b8 0f46 cmp.w r8, #70 @ 0x46 8013c98: d005 beq.n 8013ca6 <__cvt+0x3e> 8013c9a: f1b8 0f45 cmp.w r8, #69 @ 0x45 8013c9e: d100 bne.n 8013ca2 <__cvt+0x3a> 8013ca0: 3601 adds r6, #1 8013ca2: 2302 movs r3, #2 8013ca4: e000 b.n 8013ca8 <__cvt+0x40> 8013ca6: 2303 movs r3, #3 8013ca8: aa07 add r2, sp, #28 8013caa: 9204 str r2, [sp, #16] 8013cac: aa06 add r2, sp, #24 8013cae: e9cd a202 strd sl, r2, [sp, #8] 8013cb2: e9cd 3600 strd r3, r6, [sp] 8013cb6: 4622 mov r2, r4 8013cb8: 462b mov r3, r5 8013cba: f000 fe3d bl 8014938 <_dtoa_r> 8013cbe: f1b8 0f47 cmp.w r8, #71 @ 0x47 8013cc2: 4607 mov r7, r0 8013cc4: d119 bne.n 8013cfa <__cvt+0x92> 8013cc6: 9b11 ldr r3, [sp, #68] @ 0x44 8013cc8: 07db lsls r3, r3, #31 8013cca: d50e bpl.n 8013cea <__cvt+0x82> 8013ccc: eb00 0906 add.w r9, r0, r6 8013cd0: 2200 movs r2, #0 8013cd2: 2300 movs r3, #0 8013cd4: 4620 mov r0, r4 8013cd6: 4629 mov r1, r5 8013cd8: f7f4 fed2 bl 8008a80 <__aeabi_dcmpeq> 8013cdc: b108 cbz r0, 8013ce2 <__cvt+0x7a> 8013cde: f8cd 901c str.w r9, [sp, #28] 8013ce2: 2230 movs r2, #48 @ 0x30 8013ce4: 9b07 ldr r3, [sp, #28] 8013ce6: 454b cmp r3, r9 8013ce8: d31e bcc.n 8013d28 <__cvt+0xc0> 8013cea: 4638 mov r0, r7 8013cec: 9b07 ldr r3, [sp, #28] 8013cee: 9a15 ldr r2, [sp, #84] @ 0x54 8013cf0: 1bdb subs r3, r3, r7 8013cf2: 6013 str r3, [r2, #0] 8013cf4: b008 add sp, #32 8013cf6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8013cfa: f1b8 0f46 cmp.w r8, #70 @ 0x46 8013cfe: eb00 0906 add.w r9, r0, r6 8013d02: d1e5 bne.n 8013cd0 <__cvt+0x68> 8013d04: 7803 ldrb r3, [r0, #0] 8013d06: 2b30 cmp r3, #48 @ 0x30 8013d08: d10a bne.n 8013d20 <__cvt+0xb8> 8013d0a: 2200 movs r2, #0 8013d0c: 2300 movs r3, #0 8013d0e: 4620 mov r0, r4 8013d10: 4629 mov r1, r5 8013d12: f7f4 feb5 bl 8008a80 <__aeabi_dcmpeq> 8013d16: b918 cbnz r0, 8013d20 <__cvt+0xb8> 8013d18: f1c6 0601 rsb r6, r6, #1 8013d1c: f8ca 6000 str.w r6, [sl] 8013d20: f8da 3000 ldr.w r3, [sl] 8013d24: 4499 add r9, r3 8013d26: e7d3 b.n 8013cd0 <__cvt+0x68> 8013d28: 1c59 adds r1, r3, #1 8013d2a: 9107 str r1, [sp, #28] 8013d2c: 701a strb r2, [r3, #0] 8013d2e: e7d9 b.n 8013ce4 <__cvt+0x7c> 08013d30 <__exponent>: 8013d30: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8013d32: 2900 cmp r1, #0 8013d34: bfb6 itet lt 8013d36: 232d movlt r3, #45 @ 0x2d 8013d38: 232b movge r3, #43 @ 0x2b 8013d3a: 4249 neglt r1, r1 8013d3c: 2909 cmp r1, #9 8013d3e: 7002 strb r2, [r0, #0] 8013d40: 7043 strb r3, [r0, #1] 8013d42: dd29 ble.n 8013d98 <__exponent+0x68> 8013d44: f10d 0307 add.w r3, sp, #7 8013d48: 461d mov r5, r3 8013d4a: 270a movs r7, #10 8013d4c: fbb1 f6f7 udiv r6, r1, r7 8013d50: 461a mov r2, r3 8013d52: fb07 1416 mls r4, r7, r6, r1 8013d56: 3430 adds r4, #48 @ 0x30 8013d58: f802 4c01 strb.w r4, [r2, #-1] 8013d5c: 460c mov r4, r1 8013d5e: 2c63 cmp r4, #99 @ 0x63 8013d60: 4631 mov r1, r6 8013d62: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff 8013d66: dcf1 bgt.n 8013d4c <__exponent+0x1c> 8013d68: 3130 adds r1, #48 @ 0x30 8013d6a: 1e94 subs r4, r2, #2 8013d6c: f803 1c01 strb.w r1, [r3, #-1] 8013d70: 4623 mov r3, r4 8013d72: 1c41 adds r1, r0, #1 8013d74: 42ab cmp r3, r5 8013d76: d30a bcc.n 8013d8e <__exponent+0x5e> 8013d78: f10d 0309 add.w r3, sp, #9 8013d7c: 1a9b subs r3, r3, r2 8013d7e: 42ac cmp r4, r5 8013d80: bf88 it hi 8013d82: 2300 movhi r3, #0 8013d84: 3302 adds r3, #2 8013d86: 4403 add r3, r0 8013d88: 1a18 subs r0, r3, r0 8013d8a: b003 add sp, #12 8013d8c: bdf0 pop {r4, r5, r6, r7, pc} 8013d8e: f813 6b01 ldrb.w r6, [r3], #1 8013d92: f801 6f01 strb.w r6, [r1, #1]! 8013d96: e7ed b.n 8013d74 <__exponent+0x44> 8013d98: 2330 movs r3, #48 @ 0x30 8013d9a: 3130 adds r1, #48 @ 0x30 8013d9c: 7083 strb r3, [r0, #2] 8013d9e: 70c1 strb r1, [r0, #3] 8013da0: 1d03 adds r3, r0, #4 8013da2: e7f1 b.n 8013d88 <__exponent+0x58> 08013da4 <_printf_float>: 8013da4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8013da8: b091 sub sp, #68 @ 0x44 8013daa: 460c mov r4, r1 8013dac: f8dd 8068 ldr.w r8, [sp, #104] @ 0x68 8013db0: 4616 mov r6, r2 8013db2: 461f mov r7, r3 8013db4: 4605 mov r5, r0 8013db6: f000 fcf7 bl 80147a8 <_localeconv_r> 8013dba: 6803 ldr r3, [r0, #0] 8013dbc: 4618 mov r0, r3 8013dbe: 9308 str r3, [sp, #32] 8013dc0: f7f4 fa32 bl 8008228 8013dc4: 2300 movs r3, #0 8013dc6: 930e str r3, [sp, #56] @ 0x38 8013dc8: f8d8 3000 ldr.w r3, [r8] 8013dcc: 9009 str r0, [sp, #36] @ 0x24 8013dce: 3307 adds r3, #7 8013dd0: f023 0307 bic.w r3, r3, #7 8013dd4: f103 0208 add.w r2, r3, #8 8013dd8: f894 a018 ldrb.w sl, [r4, #24] 8013ddc: f8d4 b000 ldr.w fp, [r4] 8013de0: f8c8 2000 str.w r2, [r8] 8013de4: e9d3 8900 ldrd r8, r9, [r3] 8013de8: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000 8013dec: 930b str r3, [sp, #44] @ 0x2c 8013dee: f8cd 8028 str.w r8, [sp, #40] @ 0x28 8013df2: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8013df6: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 8013dfa: e9c4 8912 strd r8, r9, [r4, #72] @ 0x48 8013dfe: 4b9c ldr r3, [pc, #624] @ (8014070 <_printf_float+0x2cc>) 8013e00: f7f4 fe70 bl 8008ae4 <__aeabi_dcmpun> 8013e04: bb70 cbnz r0, 8013e64 <_printf_float+0xc0> 8013e06: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 8013e0a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8013e0e: 4b98 ldr r3, [pc, #608] @ (8014070 <_printf_float+0x2cc>) 8013e10: f7f4 fe4a bl 8008aa8 <__aeabi_dcmple> 8013e14: bb30 cbnz r0, 8013e64 <_printf_float+0xc0> 8013e16: 2200 movs r2, #0 8013e18: 2300 movs r3, #0 8013e1a: 4640 mov r0, r8 8013e1c: 4649 mov r1, r9 8013e1e: f7f4 fe39 bl 8008a94 <__aeabi_dcmplt> 8013e22: b110 cbz r0, 8013e2a <_printf_float+0x86> 8013e24: 232d movs r3, #45 @ 0x2d 8013e26: f884 3043 strb.w r3, [r4, #67] @ 0x43 8013e2a: 4a92 ldr r2, [pc, #584] @ (8014074 <_printf_float+0x2d0>) 8013e2c: 4b92 ldr r3, [pc, #584] @ (8014078 <_printf_float+0x2d4>) 8013e2e: f1ba 0f47 cmp.w sl, #71 @ 0x47 8013e32: bf8c ite hi 8013e34: 4690 movhi r8, r2 8013e36: 4698 movls r8, r3 8013e38: 2303 movs r3, #3 8013e3a: f04f 0900 mov.w r9, #0 8013e3e: 6123 str r3, [r4, #16] 8013e40: f02b 0304 bic.w r3, fp, #4 8013e44: 6023 str r3, [r4, #0] 8013e46: 4633 mov r3, r6 8013e48: 4621 mov r1, r4 8013e4a: 4628 mov r0, r5 8013e4c: 9700 str r7, [sp, #0] 8013e4e: aa0f add r2, sp, #60 @ 0x3c 8013e50: f000 f9d4 bl 80141fc <_printf_common> 8013e54: 3001 adds r0, #1 8013e56: f040 8090 bne.w 8013f7a <_printf_float+0x1d6> 8013e5a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8013e5e: b011 add sp, #68 @ 0x44 8013e60: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8013e64: 4642 mov r2, r8 8013e66: 464b mov r3, r9 8013e68: 4640 mov r0, r8 8013e6a: 4649 mov r1, r9 8013e6c: f7f4 fe3a bl 8008ae4 <__aeabi_dcmpun> 8013e70: b148 cbz r0, 8013e86 <_printf_float+0xe2> 8013e72: 464b mov r3, r9 8013e74: 2b00 cmp r3, #0 8013e76: bfb8 it lt 8013e78: 232d movlt r3, #45 @ 0x2d 8013e7a: 4a80 ldr r2, [pc, #512] @ (801407c <_printf_float+0x2d8>) 8013e7c: bfb8 it lt 8013e7e: f884 3043 strblt.w r3, [r4, #67] @ 0x43 8013e82: 4b7f ldr r3, [pc, #508] @ (8014080 <_printf_float+0x2dc>) 8013e84: e7d3 b.n 8013e2e <_printf_float+0x8a> 8013e86: 6863 ldr r3, [r4, #4] 8013e88: f00a 01df and.w r1, sl, #223 @ 0xdf 8013e8c: 1c5a adds r2, r3, #1 8013e8e: d13f bne.n 8013f10 <_printf_float+0x16c> 8013e90: 2306 movs r3, #6 8013e92: 6063 str r3, [r4, #4] 8013e94: 2200 movs r2, #0 8013e96: f44b 6380 orr.w r3, fp, #1024 @ 0x400 8013e9a: 6023 str r3, [r4, #0] 8013e9c: 9206 str r2, [sp, #24] 8013e9e: aa0e add r2, sp, #56 @ 0x38 8013ea0: e9cd a204 strd sl, r2, [sp, #16] 8013ea4: aa0d add r2, sp, #52 @ 0x34 8013ea6: 9203 str r2, [sp, #12] 8013ea8: f10d 0233 add.w r2, sp, #51 @ 0x33 8013eac: e9cd 3201 strd r3, r2, [sp, #4] 8013eb0: 6863 ldr r3, [r4, #4] 8013eb2: 4642 mov r2, r8 8013eb4: 9300 str r3, [sp, #0] 8013eb6: 4628 mov r0, r5 8013eb8: 464b mov r3, r9 8013eba: 910a str r1, [sp, #40] @ 0x28 8013ebc: f7ff fed4 bl 8013c68 <__cvt> 8013ec0: 990a ldr r1, [sp, #40] @ 0x28 8013ec2: 4680 mov r8, r0 8013ec4: 2947 cmp r1, #71 @ 0x47 8013ec6: 990d ldr r1, [sp, #52] @ 0x34 8013ec8: d128 bne.n 8013f1c <_printf_float+0x178> 8013eca: 1cc8 adds r0, r1, #3 8013ecc: db02 blt.n 8013ed4 <_printf_float+0x130> 8013ece: 6863 ldr r3, [r4, #4] 8013ed0: 4299 cmp r1, r3 8013ed2: dd40 ble.n 8013f56 <_printf_float+0x1b2> 8013ed4: f1aa 0a02 sub.w sl, sl, #2 8013ed8: fa5f fa8a uxtb.w sl, sl 8013edc: 4652 mov r2, sl 8013ede: 3901 subs r1, #1 8013ee0: f104 0050 add.w r0, r4, #80 @ 0x50 8013ee4: 910d str r1, [sp, #52] @ 0x34 8013ee6: f7ff ff23 bl 8013d30 <__exponent> 8013eea: 9a0e ldr r2, [sp, #56] @ 0x38 8013eec: 4681 mov r9, r0 8013eee: 1813 adds r3, r2, r0 8013ef0: 2a01 cmp r2, #1 8013ef2: 6123 str r3, [r4, #16] 8013ef4: dc02 bgt.n 8013efc <_printf_float+0x158> 8013ef6: 6822 ldr r2, [r4, #0] 8013ef8: 07d2 lsls r2, r2, #31 8013efa: d501 bpl.n 8013f00 <_printf_float+0x15c> 8013efc: 3301 adds r3, #1 8013efe: 6123 str r3, [r4, #16] 8013f00: f89d 3033 ldrb.w r3, [sp, #51] @ 0x33 8013f04: 2b00 cmp r3, #0 8013f06: d09e beq.n 8013e46 <_printf_float+0xa2> 8013f08: 232d movs r3, #45 @ 0x2d 8013f0a: f884 3043 strb.w r3, [r4, #67] @ 0x43 8013f0e: e79a b.n 8013e46 <_printf_float+0xa2> 8013f10: 2947 cmp r1, #71 @ 0x47 8013f12: d1bf bne.n 8013e94 <_printf_float+0xf0> 8013f14: 2b00 cmp r3, #0 8013f16: d1bd bne.n 8013e94 <_printf_float+0xf0> 8013f18: 2301 movs r3, #1 8013f1a: e7ba b.n 8013e92 <_printf_float+0xee> 8013f1c: f1ba 0f65 cmp.w sl, #101 @ 0x65 8013f20: d9dc bls.n 8013edc <_printf_float+0x138> 8013f22: f1ba 0f66 cmp.w sl, #102 @ 0x66 8013f26: d118 bne.n 8013f5a <_printf_float+0x1b6> 8013f28: 2900 cmp r1, #0 8013f2a: 6863 ldr r3, [r4, #4] 8013f2c: dd0b ble.n 8013f46 <_printf_float+0x1a2> 8013f2e: 6121 str r1, [r4, #16] 8013f30: b913 cbnz r3, 8013f38 <_printf_float+0x194> 8013f32: 6822 ldr r2, [r4, #0] 8013f34: 07d0 lsls r0, r2, #31 8013f36: d502 bpl.n 8013f3e <_printf_float+0x19a> 8013f38: 3301 adds r3, #1 8013f3a: 440b add r3, r1 8013f3c: 6123 str r3, [r4, #16] 8013f3e: f04f 0900 mov.w r9, #0 8013f42: 65a1 str r1, [r4, #88] @ 0x58 8013f44: e7dc b.n 8013f00 <_printf_float+0x15c> 8013f46: b913 cbnz r3, 8013f4e <_printf_float+0x1aa> 8013f48: 6822 ldr r2, [r4, #0] 8013f4a: 07d2 lsls r2, r2, #31 8013f4c: d501 bpl.n 8013f52 <_printf_float+0x1ae> 8013f4e: 3302 adds r3, #2 8013f50: e7f4 b.n 8013f3c <_printf_float+0x198> 8013f52: 2301 movs r3, #1 8013f54: e7f2 b.n 8013f3c <_printf_float+0x198> 8013f56: f04f 0a67 mov.w sl, #103 @ 0x67 8013f5a: 9b0e ldr r3, [sp, #56] @ 0x38 8013f5c: 4299 cmp r1, r3 8013f5e: db05 blt.n 8013f6c <_printf_float+0x1c8> 8013f60: 6823 ldr r3, [r4, #0] 8013f62: 6121 str r1, [r4, #16] 8013f64: 07d8 lsls r0, r3, #31 8013f66: d5ea bpl.n 8013f3e <_printf_float+0x19a> 8013f68: 1c4b adds r3, r1, #1 8013f6a: e7e7 b.n 8013f3c <_printf_float+0x198> 8013f6c: 2900 cmp r1, #0 8013f6e: bfcc ite gt 8013f70: 2201 movgt r2, #1 8013f72: f1c1 0202 rsble r2, r1, #2 8013f76: 4413 add r3, r2 8013f78: e7e0 b.n 8013f3c <_printf_float+0x198> 8013f7a: 6823 ldr r3, [r4, #0] 8013f7c: 055a lsls r2, r3, #21 8013f7e: d407 bmi.n 8013f90 <_printf_float+0x1ec> 8013f80: 6923 ldr r3, [r4, #16] 8013f82: 4642 mov r2, r8 8013f84: 4631 mov r1, r6 8013f86: 4628 mov r0, r5 8013f88: 47b8 blx r7 8013f8a: 3001 adds r0, #1 8013f8c: d12b bne.n 8013fe6 <_printf_float+0x242> 8013f8e: e764 b.n 8013e5a <_printf_float+0xb6> 8013f90: f1ba 0f65 cmp.w sl, #101 @ 0x65 8013f94: f240 80dc bls.w 8014150 <_printf_float+0x3ac> 8013f98: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 8013f9c: 2200 movs r2, #0 8013f9e: 2300 movs r3, #0 8013fa0: f7f4 fd6e bl 8008a80 <__aeabi_dcmpeq> 8013fa4: 2800 cmp r0, #0 8013fa6: d033 beq.n 8014010 <_printf_float+0x26c> 8013fa8: 2301 movs r3, #1 8013faa: 4631 mov r1, r6 8013fac: 4628 mov r0, r5 8013fae: 4a35 ldr r2, [pc, #212] @ (8014084 <_printf_float+0x2e0>) 8013fb0: 47b8 blx r7 8013fb2: 3001 adds r0, #1 8013fb4: f43f af51 beq.w 8013e5a <_printf_float+0xb6> 8013fb8: e9dd 380d ldrd r3, r8, [sp, #52] @ 0x34 8013fbc: 4543 cmp r3, r8 8013fbe: db02 blt.n 8013fc6 <_printf_float+0x222> 8013fc0: 6823 ldr r3, [r4, #0] 8013fc2: 07d8 lsls r0, r3, #31 8013fc4: d50f bpl.n 8013fe6 <_printf_float+0x242> 8013fc6: e9dd 2308 ldrd r2, r3, [sp, #32] 8013fca: 4631 mov r1, r6 8013fcc: 4628 mov r0, r5 8013fce: 47b8 blx r7 8013fd0: 3001 adds r0, #1 8013fd2: f43f af42 beq.w 8013e5a <_printf_float+0xb6> 8013fd6: f04f 0900 mov.w r9, #0 8013fda: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 8013fde: f104 0a1a add.w sl, r4, #26 8013fe2: 45c8 cmp r8, r9 8013fe4: dc09 bgt.n 8013ffa <_printf_float+0x256> 8013fe6: 6823 ldr r3, [r4, #0] 8013fe8: 079b lsls r3, r3, #30 8013fea: f100 8102 bmi.w 80141f2 <_printf_float+0x44e> 8013fee: 68e0 ldr r0, [r4, #12] 8013ff0: 9b0f ldr r3, [sp, #60] @ 0x3c 8013ff2: 4298 cmp r0, r3 8013ff4: bfb8 it lt 8013ff6: 4618 movlt r0, r3 8013ff8: e731 b.n 8013e5e <_printf_float+0xba> 8013ffa: 2301 movs r3, #1 8013ffc: 4652 mov r2, sl 8013ffe: 4631 mov r1, r6 8014000: 4628 mov r0, r5 8014002: 47b8 blx r7 8014004: 3001 adds r0, #1 8014006: f43f af28 beq.w 8013e5a <_printf_float+0xb6> 801400a: f109 0901 add.w r9, r9, #1 801400e: e7e8 b.n 8013fe2 <_printf_float+0x23e> 8014010: 9b0d ldr r3, [sp, #52] @ 0x34 8014012: 2b00 cmp r3, #0 8014014: dc38 bgt.n 8014088 <_printf_float+0x2e4> 8014016: 2301 movs r3, #1 8014018: 4631 mov r1, r6 801401a: 4628 mov r0, r5 801401c: 4a19 ldr r2, [pc, #100] @ (8014084 <_printf_float+0x2e0>) 801401e: 47b8 blx r7 8014020: 3001 adds r0, #1 8014022: f43f af1a beq.w 8013e5a <_printf_float+0xb6> 8014026: e9dd 390d ldrd r3, r9, [sp, #52] @ 0x34 801402a: ea59 0303 orrs.w r3, r9, r3 801402e: d102 bne.n 8014036 <_printf_float+0x292> 8014030: 6823 ldr r3, [r4, #0] 8014032: 07d9 lsls r1, r3, #31 8014034: d5d7 bpl.n 8013fe6 <_printf_float+0x242> 8014036: e9dd 2308 ldrd r2, r3, [sp, #32] 801403a: 4631 mov r1, r6 801403c: 4628 mov r0, r5 801403e: 47b8 blx r7 8014040: 3001 adds r0, #1 8014042: f43f af0a beq.w 8013e5a <_printf_float+0xb6> 8014046: f04f 0a00 mov.w sl, #0 801404a: f104 0b1a add.w fp, r4, #26 801404e: 9b0d ldr r3, [sp, #52] @ 0x34 8014050: 425b negs r3, r3 8014052: 4553 cmp r3, sl 8014054: dc01 bgt.n 801405a <_printf_float+0x2b6> 8014056: 464b mov r3, r9 8014058: e793 b.n 8013f82 <_printf_float+0x1de> 801405a: 2301 movs r3, #1 801405c: 465a mov r2, fp 801405e: 4631 mov r1, r6 8014060: 4628 mov r0, r5 8014062: 47b8 blx r7 8014064: 3001 adds r0, #1 8014066: f43f aef8 beq.w 8013e5a <_printf_float+0xb6> 801406a: f10a 0a01 add.w sl, sl, #1 801406e: e7ee b.n 801404e <_printf_float+0x2aa> 8014070: 7fefffff .word 0x7fefffff 8014074: 08017280 .word 0x08017280 8014078: 0801727c .word 0x0801727c 801407c: 08017288 .word 0x08017288 8014080: 08017284 .word 0x08017284 8014084: 0801728c .word 0x0801728c 8014088: 6da3 ldr r3, [r4, #88] @ 0x58 801408a: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 801408e: 4553 cmp r3, sl 8014090: bfa8 it ge 8014092: 4653 movge r3, sl 8014094: 2b00 cmp r3, #0 8014096: 4699 mov r9, r3 8014098: dc36 bgt.n 8014108 <_printf_float+0x364> 801409a: f04f 0b00 mov.w fp, #0 801409e: ea29 79e9 bic.w r9, r9, r9, asr #31 80140a2: f104 021a add.w r2, r4, #26 80140a6: 6da3 ldr r3, [r4, #88] @ 0x58 80140a8: 930a str r3, [sp, #40] @ 0x28 80140aa: eba3 0309 sub.w r3, r3, r9 80140ae: 455b cmp r3, fp 80140b0: dc31 bgt.n 8014116 <_printf_float+0x372> 80140b2: 9b0d ldr r3, [sp, #52] @ 0x34 80140b4: 459a cmp sl, r3 80140b6: dc3a bgt.n 801412e <_printf_float+0x38a> 80140b8: 6823 ldr r3, [r4, #0] 80140ba: 07da lsls r2, r3, #31 80140bc: d437 bmi.n 801412e <_printf_float+0x38a> 80140be: 9b0d ldr r3, [sp, #52] @ 0x34 80140c0: ebaa 0903 sub.w r9, sl, r3 80140c4: 9b0a ldr r3, [sp, #40] @ 0x28 80140c6: ebaa 0303 sub.w r3, sl, r3 80140ca: 4599 cmp r9, r3 80140cc: bfa8 it ge 80140ce: 4699 movge r9, r3 80140d0: f1b9 0f00 cmp.w r9, #0 80140d4: dc33 bgt.n 801413e <_printf_float+0x39a> 80140d6: f04f 0800 mov.w r8, #0 80140da: ea29 79e9 bic.w r9, r9, r9, asr #31 80140de: f104 0b1a add.w fp, r4, #26 80140e2: 9b0d ldr r3, [sp, #52] @ 0x34 80140e4: ebaa 0303 sub.w r3, sl, r3 80140e8: eba3 0309 sub.w r3, r3, r9 80140ec: 4543 cmp r3, r8 80140ee: f77f af7a ble.w 8013fe6 <_printf_float+0x242> 80140f2: 2301 movs r3, #1 80140f4: 465a mov r2, fp 80140f6: 4631 mov r1, r6 80140f8: 4628 mov r0, r5 80140fa: 47b8 blx r7 80140fc: 3001 adds r0, #1 80140fe: f43f aeac beq.w 8013e5a <_printf_float+0xb6> 8014102: f108 0801 add.w r8, r8, #1 8014106: e7ec b.n 80140e2 <_printf_float+0x33e> 8014108: 4642 mov r2, r8 801410a: 4631 mov r1, r6 801410c: 4628 mov r0, r5 801410e: 47b8 blx r7 8014110: 3001 adds r0, #1 8014112: d1c2 bne.n 801409a <_printf_float+0x2f6> 8014114: e6a1 b.n 8013e5a <_printf_float+0xb6> 8014116: 2301 movs r3, #1 8014118: 4631 mov r1, r6 801411a: 4628 mov r0, r5 801411c: 920a str r2, [sp, #40] @ 0x28 801411e: 47b8 blx r7 8014120: 3001 adds r0, #1 8014122: f43f ae9a beq.w 8013e5a <_printf_float+0xb6> 8014126: 9a0a ldr r2, [sp, #40] @ 0x28 8014128: f10b 0b01 add.w fp, fp, #1 801412c: e7bb b.n 80140a6 <_printf_float+0x302> 801412e: 4631 mov r1, r6 8014130: e9dd 2308 ldrd r2, r3, [sp, #32] 8014134: 4628 mov r0, r5 8014136: 47b8 blx r7 8014138: 3001 adds r0, #1 801413a: d1c0 bne.n 80140be <_printf_float+0x31a> 801413c: e68d b.n 8013e5a <_printf_float+0xb6> 801413e: 9a0a ldr r2, [sp, #40] @ 0x28 8014140: 464b mov r3, r9 8014142: 4631 mov r1, r6 8014144: 4628 mov r0, r5 8014146: 4442 add r2, r8 8014148: 47b8 blx r7 801414a: 3001 adds r0, #1 801414c: d1c3 bne.n 80140d6 <_printf_float+0x332> 801414e: e684 b.n 8013e5a <_printf_float+0xb6> 8014150: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 8014154: f1ba 0f01 cmp.w sl, #1 8014158: dc01 bgt.n 801415e <_printf_float+0x3ba> 801415a: 07db lsls r3, r3, #31 801415c: d536 bpl.n 80141cc <_printf_float+0x428> 801415e: 2301 movs r3, #1 8014160: 4642 mov r2, r8 8014162: 4631 mov r1, r6 8014164: 4628 mov r0, r5 8014166: 47b8 blx r7 8014168: 3001 adds r0, #1 801416a: f43f ae76 beq.w 8013e5a <_printf_float+0xb6> 801416e: e9dd 2308 ldrd r2, r3, [sp, #32] 8014172: 4631 mov r1, r6 8014174: 4628 mov r0, r5 8014176: 47b8 blx r7 8014178: 3001 adds r0, #1 801417a: f43f ae6e beq.w 8013e5a <_printf_float+0xb6> 801417e: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 8014182: 2200 movs r2, #0 8014184: 2300 movs r3, #0 8014186: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff 801418a: f7f4 fc79 bl 8008a80 <__aeabi_dcmpeq> 801418e: b9c0 cbnz r0, 80141c2 <_printf_float+0x41e> 8014190: 4653 mov r3, sl 8014192: f108 0201 add.w r2, r8, #1 8014196: 4631 mov r1, r6 8014198: 4628 mov r0, r5 801419a: 47b8 blx r7 801419c: 3001 adds r0, #1 801419e: d10c bne.n 80141ba <_printf_float+0x416> 80141a0: e65b b.n 8013e5a <_printf_float+0xb6> 80141a2: 2301 movs r3, #1 80141a4: 465a mov r2, fp 80141a6: 4631 mov r1, r6 80141a8: 4628 mov r0, r5 80141aa: 47b8 blx r7 80141ac: 3001 adds r0, #1 80141ae: f43f ae54 beq.w 8013e5a <_printf_float+0xb6> 80141b2: f108 0801 add.w r8, r8, #1 80141b6: 45d0 cmp r8, sl 80141b8: dbf3 blt.n 80141a2 <_printf_float+0x3fe> 80141ba: 464b mov r3, r9 80141bc: f104 0250 add.w r2, r4, #80 @ 0x50 80141c0: e6e0 b.n 8013f84 <_printf_float+0x1e0> 80141c2: f04f 0800 mov.w r8, #0 80141c6: f104 0b1a add.w fp, r4, #26 80141ca: e7f4 b.n 80141b6 <_printf_float+0x412> 80141cc: 2301 movs r3, #1 80141ce: 4642 mov r2, r8 80141d0: e7e1 b.n 8014196 <_printf_float+0x3f2> 80141d2: 2301 movs r3, #1 80141d4: 464a mov r2, r9 80141d6: 4631 mov r1, r6 80141d8: 4628 mov r0, r5 80141da: 47b8 blx r7 80141dc: 3001 adds r0, #1 80141de: f43f ae3c beq.w 8013e5a <_printf_float+0xb6> 80141e2: f108 0801 add.w r8, r8, #1 80141e6: 68e3 ldr r3, [r4, #12] 80141e8: 990f ldr r1, [sp, #60] @ 0x3c 80141ea: 1a5b subs r3, r3, r1 80141ec: 4543 cmp r3, r8 80141ee: dcf0 bgt.n 80141d2 <_printf_float+0x42e> 80141f0: e6fd b.n 8013fee <_printf_float+0x24a> 80141f2: f04f 0800 mov.w r8, #0 80141f6: f104 0919 add.w r9, r4, #25 80141fa: e7f4 b.n 80141e6 <_printf_float+0x442> 080141fc <_printf_common>: 80141fc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8014200: 4616 mov r6, r2 8014202: 4698 mov r8, r3 8014204: 688a ldr r2, [r1, #8] 8014206: 690b ldr r3, [r1, #16] 8014208: 4607 mov r7, r0 801420a: 4293 cmp r3, r2 801420c: bfb8 it lt 801420e: 4613 movlt r3, r2 8014210: 6033 str r3, [r6, #0] 8014212: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 8014216: 460c mov r4, r1 8014218: f8dd 9020 ldr.w r9, [sp, #32] 801421c: b10a cbz r2, 8014222 <_printf_common+0x26> 801421e: 3301 adds r3, #1 8014220: 6033 str r3, [r6, #0] 8014222: 6823 ldr r3, [r4, #0] 8014224: 0699 lsls r1, r3, #26 8014226: bf42 ittt mi 8014228: 6833 ldrmi r3, [r6, #0] 801422a: 3302 addmi r3, #2 801422c: 6033 strmi r3, [r6, #0] 801422e: 6825 ldr r5, [r4, #0] 8014230: f015 0506 ands.w r5, r5, #6 8014234: d106 bne.n 8014244 <_printf_common+0x48> 8014236: f104 0a19 add.w sl, r4, #25 801423a: 68e3 ldr r3, [r4, #12] 801423c: 6832 ldr r2, [r6, #0] 801423e: 1a9b subs r3, r3, r2 8014240: 42ab cmp r3, r5 8014242: dc2b bgt.n 801429c <_printf_common+0xa0> 8014244: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 8014248: 6822 ldr r2, [r4, #0] 801424a: 3b00 subs r3, #0 801424c: bf18 it ne 801424e: 2301 movne r3, #1 8014250: 0692 lsls r2, r2, #26 8014252: d430 bmi.n 80142b6 <_printf_common+0xba> 8014254: 4641 mov r1, r8 8014256: 4638 mov r0, r7 8014258: f104 0243 add.w r2, r4, #67 @ 0x43 801425c: 47c8 blx r9 801425e: 3001 adds r0, #1 8014260: d023 beq.n 80142aa <_printf_common+0xae> 8014262: 6823 ldr r3, [r4, #0] 8014264: 6922 ldr r2, [r4, #16] 8014266: f003 0306 and.w r3, r3, #6 801426a: 2b04 cmp r3, #4 801426c: bf14 ite ne 801426e: 2500 movne r5, #0 8014270: 6833 ldreq r3, [r6, #0] 8014272: f04f 0600 mov.w r6, #0 8014276: bf08 it eq 8014278: 68e5 ldreq r5, [r4, #12] 801427a: f104 041a add.w r4, r4, #26 801427e: bf08 it eq 8014280: 1aed subeq r5, r5, r3 8014282: f854 3c12 ldr.w r3, [r4, #-18] 8014286: bf08 it eq 8014288: ea25 75e5 biceq.w r5, r5, r5, asr #31 801428c: 4293 cmp r3, r2 801428e: bfc4 itt gt 8014290: 1a9b subgt r3, r3, r2 8014292: 18ed addgt r5, r5, r3 8014294: 42b5 cmp r5, r6 8014296: d11a bne.n 80142ce <_printf_common+0xd2> 8014298: 2000 movs r0, #0 801429a: e008 b.n 80142ae <_printf_common+0xb2> 801429c: 2301 movs r3, #1 801429e: 4652 mov r2, sl 80142a0: 4641 mov r1, r8 80142a2: 4638 mov r0, r7 80142a4: 47c8 blx r9 80142a6: 3001 adds r0, #1 80142a8: d103 bne.n 80142b2 <_printf_common+0xb6> 80142aa: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80142ae: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80142b2: 3501 adds r5, #1 80142b4: e7c1 b.n 801423a <_printf_common+0x3e> 80142b6: 2030 movs r0, #48 @ 0x30 80142b8: 18e1 adds r1, r4, r3 80142ba: f881 0043 strb.w r0, [r1, #67] @ 0x43 80142be: 1c5a adds r2, r3, #1 80142c0: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 80142c4: 4422 add r2, r4 80142c6: 3302 adds r3, #2 80142c8: f882 1043 strb.w r1, [r2, #67] @ 0x43 80142cc: e7c2 b.n 8014254 <_printf_common+0x58> 80142ce: 2301 movs r3, #1 80142d0: 4622 mov r2, r4 80142d2: 4641 mov r1, r8 80142d4: 4638 mov r0, r7 80142d6: 47c8 blx r9 80142d8: 3001 adds r0, #1 80142da: d0e6 beq.n 80142aa <_printf_common+0xae> 80142dc: 3601 adds r6, #1 80142de: e7d9 b.n 8014294 <_printf_common+0x98> 080142e0 <_printf_i>: 80142e0: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 80142e4: 7e0f ldrb r7, [r1, #24] 80142e6: 4691 mov r9, r2 80142e8: 2f78 cmp r7, #120 @ 0x78 80142ea: 4680 mov r8, r0 80142ec: 460c mov r4, r1 80142ee: 469a mov sl, r3 80142f0: 9e0c ldr r6, [sp, #48] @ 0x30 80142f2: f101 0243 add.w r2, r1, #67 @ 0x43 80142f6: d807 bhi.n 8014308 <_printf_i+0x28> 80142f8: 2f62 cmp r7, #98 @ 0x62 80142fa: d80a bhi.n 8014312 <_printf_i+0x32> 80142fc: 2f00 cmp r7, #0 80142fe: f000 80d1 beq.w 80144a4 <_printf_i+0x1c4> 8014302: 2f58 cmp r7, #88 @ 0x58 8014304: f000 80b8 beq.w 8014478 <_printf_i+0x198> 8014308: f104 0642 add.w r6, r4, #66 @ 0x42 801430c: f884 7042 strb.w r7, [r4, #66] @ 0x42 8014310: e03a b.n 8014388 <_printf_i+0xa8> 8014312: f1a7 0363 sub.w r3, r7, #99 @ 0x63 8014316: 2b15 cmp r3, #21 8014318: d8f6 bhi.n 8014308 <_printf_i+0x28> 801431a: a101 add r1, pc, #4 @ (adr r1, 8014320 <_printf_i+0x40>) 801431c: f851 f023 ldr.w pc, [r1, r3, lsl #2] 8014320: 08014379 .word 0x08014379 8014324: 0801438d .word 0x0801438d 8014328: 08014309 .word 0x08014309 801432c: 08014309 .word 0x08014309 8014330: 08014309 .word 0x08014309 8014334: 08014309 .word 0x08014309 8014338: 0801438d .word 0x0801438d 801433c: 08014309 .word 0x08014309 8014340: 08014309 .word 0x08014309 8014344: 08014309 .word 0x08014309 8014348: 08014309 .word 0x08014309 801434c: 0801448b .word 0x0801448b 8014350: 080143b7 .word 0x080143b7 8014354: 08014445 .word 0x08014445 8014358: 08014309 .word 0x08014309 801435c: 08014309 .word 0x08014309 8014360: 080144ad .word 0x080144ad 8014364: 08014309 .word 0x08014309 8014368: 080143b7 .word 0x080143b7 801436c: 08014309 .word 0x08014309 8014370: 08014309 .word 0x08014309 8014374: 0801444d .word 0x0801444d 8014378: 6833 ldr r3, [r6, #0] 801437a: 1d1a adds r2, r3, #4 801437c: 681b ldr r3, [r3, #0] 801437e: 6032 str r2, [r6, #0] 8014380: f104 0642 add.w r6, r4, #66 @ 0x42 8014384: f884 3042 strb.w r3, [r4, #66] @ 0x42 8014388: 2301 movs r3, #1 801438a: e09c b.n 80144c6 <_printf_i+0x1e6> 801438c: 6833 ldr r3, [r6, #0] 801438e: 6820 ldr r0, [r4, #0] 8014390: 1d19 adds r1, r3, #4 8014392: 6031 str r1, [r6, #0] 8014394: 0606 lsls r6, r0, #24 8014396: d501 bpl.n 801439c <_printf_i+0xbc> 8014398: 681d ldr r5, [r3, #0] 801439a: e003 b.n 80143a4 <_printf_i+0xc4> 801439c: 0645 lsls r5, r0, #25 801439e: d5fb bpl.n 8014398 <_printf_i+0xb8> 80143a0: f9b3 5000 ldrsh.w r5, [r3] 80143a4: 2d00 cmp r5, #0 80143a6: da03 bge.n 80143b0 <_printf_i+0xd0> 80143a8: 232d movs r3, #45 @ 0x2d 80143aa: 426d negs r5, r5 80143ac: f884 3043 strb.w r3, [r4, #67] @ 0x43 80143b0: 230a movs r3, #10 80143b2: 4858 ldr r0, [pc, #352] @ (8014514 <_printf_i+0x234>) 80143b4: e011 b.n 80143da <_printf_i+0xfa> 80143b6: 6821 ldr r1, [r4, #0] 80143b8: 6833 ldr r3, [r6, #0] 80143ba: 0608 lsls r0, r1, #24 80143bc: f853 5b04 ldr.w r5, [r3], #4 80143c0: d402 bmi.n 80143c8 <_printf_i+0xe8> 80143c2: 0649 lsls r1, r1, #25 80143c4: bf48 it mi 80143c6: b2ad uxthmi r5, r5 80143c8: 2f6f cmp r7, #111 @ 0x6f 80143ca: 6033 str r3, [r6, #0] 80143cc: bf14 ite ne 80143ce: 230a movne r3, #10 80143d0: 2308 moveq r3, #8 80143d2: 4850 ldr r0, [pc, #320] @ (8014514 <_printf_i+0x234>) 80143d4: 2100 movs r1, #0 80143d6: f884 1043 strb.w r1, [r4, #67] @ 0x43 80143da: 6866 ldr r6, [r4, #4] 80143dc: 2e00 cmp r6, #0 80143de: 60a6 str r6, [r4, #8] 80143e0: db05 blt.n 80143ee <_printf_i+0x10e> 80143e2: 6821 ldr r1, [r4, #0] 80143e4: 432e orrs r6, r5 80143e6: f021 0104 bic.w r1, r1, #4 80143ea: 6021 str r1, [r4, #0] 80143ec: d04b beq.n 8014486 <_printf_i+0x1a6> 80143ee: 4616 mov r6, r2 80143f0: fbb5 f1f3 udiv r1, r5, r3 80143f4: fb03 5711 mls r7, r3, r1, r5 80143f8: 5dc7 ldrb r7, [r0, r7] 80143fa: f806 7d01 strb.w r7, [r6, #-1]! 80143fe: 462f mov r7, r5 8014400: 42bb cmp r3, r7 8014402: 460d mov r5, r1 8014404: d9f4 bls.n 80143f0 <_printf_i+0x110> 8014406: 2b08 cmp r3, #8 8014408: d10b bne.n 8014422 <_printf_i+0x142> 801440a: 6823 ldr r3, [r4, #0] 801440c: 07df lsls r7, r3, #31 801440e: d508 bpl.n 8014422 <_printf_i+0x142> 8014410: 6923 ldr r3, [r4, #16] 8014412: 6861 ldr r1, [r4, #4] 8014414: 4299 cmp r1, r3 8014416: bfde ittt le 8014418: 2330 movle r3, #48 @ 0x30 801441a: f806 3c01 strble.w r3, [r6, #-1] 801441e: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff 8014422: 1b92 subs r2, r2, r6 8014424: 6122 str r2, [r4, #16] 8014426: 464b mov r3, r9 8014428: 4621 mov r1, r4 801442a: 4640 mov r0, r8 801442c: f8cd a000 str.w sl, [sp] 8014430: aa03 add r2, sp, #12 8014432: f7ff fee3 bl 80141fc <_printf_common> 8014436: 3001 adds r0, #1 8014438: d14a bne.n 80144d0 <_printf_i+0x1f0> 801443a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801443e: b004 add sp, #16 8014440: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8014444: 6823 ldr r3, [r4, #0] 8014446: f043 0320 orr.w r3, r3, #32 801444a: 6023 str r3, [r4, #0] 801444c: 2778 movs r7, #120 @ 0x78 801444e: 4832 ldr r0, [pc, #200] @ (8014518 <_printf_i+0x238>) 8014450: f884 7045 strb.w r7, [r4, #69] @ 0x45 8014454: 6823 ldr r3, [r4, #0] 8014456: 6831 ldr r1, [r6, #0] 8014458: 061f lsls r7, r3, #24 801445a: f851 5b04 ldr.w r5, [r1], #4 801445e: d402 bmi.n 8014466 <_printf_i+0x186> 8014460: 065f lsls r7, r3, #25 8014462: bf48 it mi 8014464: b2ad uxthmi r5, r5 8014466: 6031 str r1, [r6, #0] 8014468: 07d9 lsls r1, r3, #31 801446a: bf44 itt mi 801446c: f043 0320 orrmi.w r3, r3, #32 8014470: 6023 strmi r3, [r4, #0] 8014472: b11d cbz r5, 801447c <_printf_i+0x19c> 8014474: 2310 movs r3, #16 8014476: e7ad b.n 80143d4 <_printf_i+0xf4> 8014478: 4826 ldr r0, [pc, #152] @ (8014514 <_printf_i+0x234>) 801447a: e7e9 b.n 8014450 <_printf_i+0x170> 801447c: 6823 ldr r3, [r4, #0] 801447e: f023 0320 bic.w r3, r3, #32 8014482: 6023 str r3, [r4, #0] 8014484: e7f6 b.n 8014474 <_printf_i+0x194> 8014486: 4616 mov r6, r2 8014488: e7bd b.n 8014406 <_printf_i+0x126> 801448a: 6833 ldr r3, [r6, #0] 801448c: 6825 ldr r5, [r4, #0] 801448e: 1d18 adds r0, r3, #4 8014490: 6961 ldr r1, [r4, #20] 8014492: 6030 str r0, [r6, #0] 8014494: 062e lsls r6, r5, #24 8014496: 681b ldr r3, [r3, #0] 8014498: d501 bpl.n 801449e <_printf_i+0x1be> 801449a: 6019 str r1, [r3, #0] 801449c: e002 b.n 80144a4 <_printf_i+0x1c4> 801449e: 0668 lsls r0, r5, #25 80144a0: d5fb bpl.n 801449a <_printf_i+0x1ba> 80144a2: 8019 strh r1, [r3, #0] 80144a4: 2300 movs r3, #0 80144a6: 4616 mov r6, r2 80144a8: 6123 str r3, [r4, #16] 80144aa: e7bc b.n 8014426 <_printf_i+0x146> 80144ac: 6833 ldr r3, [r6, #0] 80144ae: 2100 movs r1, #0 80144b0: 1d1a adds r2, r3, #4 80144b2: 6032 str r2, [r6, #0] 80144b4: 681e ldr r6, [r3, #0] 80144b6: 6862 ldr r2, [r4, #4] 80144b8: 4630 mov r0, r6 80144ba: f000 f979 bl 80147b0 80144be: b108 cbz r0, 80144c4 <_printf_i+0x1e4> 80144c0: 1b80 subs r0, r0, r6 80144c2: 6060 str r0, [r4, #4] 80144c4: 6863 ldr r3, [r4, #4] 80144c6: 6123 str r3, [r4, #16] 80144c8: 2300 movs r3, #0 80144ca: f884 3043 strb.w r3, [r4, #67] @ 0x43 80144ce: e7aa b.n 8014426 <_printf_i+0x146> 80144d0: 4632 mov r2, r6 80144d2: 4649 mov r1, r9 80144d4: 4640 mov r0, r8 80144d6: 6923 ldr r3, [r4, #16] 80144d8: 47d0 blx sl 80144da: 3001 adds r0, #1 80144dc: d0ad beq.n 801443a <_printf_i+0x15a> 80144de: 6823 ldr r3, [r4, #0] 80144e0: 079b lsls r3, r3, #30 80144e2: d413 bmi.n 801450c <_printf_i+0x22c> 80144e4: 68e0 ldr r0, [r4, #12] 80144e6: 9b03 ldr r3, [sp, #12] 80144e8: 4298 cmp r0, r3 80144ea: bfb8 it lt 80144ec: 4618 movlt r0, r3 80144ee: e7a6 b.n 801443e <_printf_i+0x15e> 80144f0: 2301 movs r3, #1 80144f2: 4632 mov r2, r6 80144f4: 4649 mov r1, r9 80144f6: 4640 mov r0, r8 80144f8: 47d0 blx sl 80144fa: 3001 adds r0, #1 80144fc: d09d beq.n 801443a <_printf_i+0x15a> 80144fe: 3501 adds r5, #1 8014500: 68e3 ldr r3, [r4, #12] 8014502: 9903 ldr r1, [sp, #12] 8014504: 1a5b subs r3, r3, r1 8014506: 42ab cmp r3, r5 8014508: dcf2 bgt.n 80144f0 <_printf_i+0x210> 801450a: e7eb b.n 80144e4 <_printf_i+0x204> 801450c: 2500 movs r5, #0 801450e: f104 0619 add.w r6, r4, #25 8014512: e7f5 b.n 8014500 <_printf_i+0x220> 8014514: 0801728e .word 0x0801728e 8014518: 0801729f .word 0x0801729f 0801451c : 801451c: 2300 movs r3, #0 801451e: b510 push {r4, lr} 8014520: 4604 mov r4, r0 8014522: e9c0 3300 strd r3, r3, [r0] 8014526: e9c0 3304 strd r3, r3, [r0, #16] 801452a: 6083 str r3, [r0, #8] 801452c: 8181 strh r1, [r0, #12] 801452e: 6643 str r3, [r0, #100] @ 0x64 8014530: 81c2 strh r2, [r0, #14] 8014532: 6183 str r3, [r0, #24] 8014534: 4619 mov r1, r3 8014536: 2208 movs r2, #8 8014538: 305c adds r0, #92 @ 0x5c 801453a: f000 f8ff bl 801473c 801453e: 4b0d ldr r3, [pc, #52] @ (8014574 ) 8014540: 6224 str r4, [r4, #32] 8014542: 6263 str r3, [r4, #36] @ 0x24 8014544: 4b0c ldr r3, [pc, #48] @ (8014578 ) 8014546: 62a3 str r3, [r4, #40] @ 0x28 8014548: 4b0c ldr r3, [pc, #48] @ (801457c ) 801454a: 62e3 str r3, [r4, #44] @ 0x2c 801454c: 4b0c ldr r3, [pc, #48] @ (8014580 ) 801454e: 6323 str r3, [r4, #48] @ 0x30 8014550: 4b0c ldr r3, [pc, #48] @ (8014584 ) 8014552: 429c cmp r4, r3 8014554: d006 beq.n 8014564 8014556: f103 0268 add.w r2, r3, #104 @ 0x68 801455a: 4294 cmp r4, r2 801455c: d002 beq.n 8014564 801455e: 33d0 adds r3, #208 @ 0xd0 8014560: 429c cmp r4, r3 8014562: d105 bne.n 8014570 8014564: f104 0058 add.w r0, r4, #88 @ 0x58 8014568: e8bd 4010 ldmia.w sp!, {r4, lr} 801456c: f000 b918 b.w 80147a0 <__retarget_lock_init_recursive> 8014570: bd10 pop {r4, pc} 8014572: bf00 nop 8014574: 080163c1 .word 0x080163c1 8014578: 080163e3 .word 0x080163e3 801457c: 0801641b .word 0x0801641b 8014580: 0801643f .word 0x0801643f 8014584: 20001274 .word 0x20001274 08014588 : 8014588: 4a02 ldr r2, [pc, #8] @ (8014594 ) 801458a: 4903 ldr r1, [pc, #12] @ (8014598 ) 801458c: 4803 ldr r0, [pc, #12] @ (801459c ) 801458e: f000 b8a5 b.w 80146dc <_fwalk_sglue> 8014592: bf00 nop 8014594: 20000090 .word 0x20000090 8014598: 08015c65 .word 0x08015c65 801459c: 200000a0 .word 0x200000a0 080145a0 : 80145a0: 6841 ldr r1, [r0, #4] 80145a2: 4b0c ldr r3, [pc, #48] @ (80145d4 ) 80145a4: b510 push {r4, lr} 80145a6: 4299 cmp r1, r3 80145a8: 4604 mov r4, r0 80145aa: d001 beq.n 80145b0 80145ac: f001 fb5a bl 8015c64 <_fflush_r> 80145b0: 68a1 ldr r1, [r4, #8] 80145b2: 4b09 ldr r3, [pc, #36] @ (80145d8 ) 80145b4: 4299 cmp r1, r3 80145b6: d002 beq.n 80145be 80145b8: 4620 mov r0, r4 80145ba: f001 fb53 bl 8015c64 <_fflush_r> 80145be: 68e1 ldr r1, [r4, #12] 80145c0: 4b06 ldr r3, [pc, #24] @ (80145dc ) 80145c2: 4299 cmp r1, r3 80145c4: d004 beq.n 80145d0 80145c6: 4620 mov r0, r4 80145c8: e8bd 4010 ldmia.w sp!, {r4, lr} 80145cc: f001 bb4a b.w 8015c64 <_fflush_r> 80145d0: bd10 pop {r4, pc} 80145d2: bf00 nop 80145d4: 20001274 .word 0x20001274 80145d8: 200012dc .word 0x200012dc 80145dc: 20001344 .word 0x20001344 080145e0 : 80145e0: b510 push {r4, lr} 80145e2: 4b0b ldr r3, [pc, #44] @ (8014610 ) 80145e4: 4c0b ldr r4, [pc, #44] @ (8014614 ) 80145e6: 4a0c ldr r2, [pc, #48] @ (8014618 ) 80145e8: 4620 mov r0, r4 80145ea: 601a str r2, [r3, #0] 80145ec: 2104 movs r1, #4 80145ee: 2200 movs r2, #0 80145f0: f7ff ff94 bl 801451c 80145f4: f104 0068 add.w r0, r4, #104 @ 0x68 80145f8: 2201 movs r2, #1 80145fa: 2109 movs r1, #9 80145fc: f7ff ff8e bl 801451c 8014600: f104 00d0 add.w r0, r4, #208 @ 0xd0 8014604: 2202 movs r2, #2 8014606: e8bd 4010 ldmia.w sp!, {r4, lr} 801460a: 2112 movs r1, #18 801460c: f7ff bf86 b.w 801451c 8014610: 200013ac .word 0x200013ac 8014614: 20001274 .word 0x20001274 8014618: 08014589 .word 0x08014589 0801461c <__sfp_lock_acquire>: 801461c: 4801 ldr r0, [pc, #4] @ (8014624 <__sfp_lock_acquire+0x8>) 801461e: f000 b8c0 b.w 80147a2 <__retarget_lock_acquire_recursive> 8014622: bf00 nop 8014624: 200013b1 .word 0x200013b1 08014628 <__sfp_lock_release>: 8014628: 4801 ldr r0, [pc, #4] @ (8014630 <__sfp_lock_release+0x8>) 801462a: f000 b8bb b.w 80147a4 <__retarget_lock_release_recursive> 801462e: bf00 nop 8014630: 200013b1 .word 0x200013b1 08014634 <__sinit>: 8014634: b510 push {r4, lr} 8014636: 4604 mov r4, r0 8014638: f7ff fff0 bl 801461c <__sfp_lock_acquire> 801463c: 6a23 ldr r3, [r4, #32] 801463e: b11b cbz r3, 8014648 <__sinit+0x14> 8014640: e8bd 4010 ldmia.w sp!, {r4, lr} 8014644: f7ff bff0 b.w 8014628 <__sfp_lock_release> 8014648: 4b04 ldr r3, [pc, #16] @ (801465c <__sinit+0x28>) 801464a: 6223 str r3, [r4, #32] 801464c: 4b04 ldr r3, [pc, #16] @ (8014660 <__sinit+0x2c>) 801464e: 681b ldr r3, [r3, #0] 8014650: 2b00 cmp r3, #0 8014652: d1f5 bne.n 8014640 <__sinit+0xc> 8014654: f7ff ffc4 bl 80145e0 8014658: e7f2 b.n 8014640 <__sinit+0xc> 801465a: bf00 nop 801465c: 080145a1 .word 0x080145a1 8014660: 200013ac .word 0x200013ac 08014664 <_vsniprintf_r>: 8014664: b530 push {r4, r5, lr} 8014666: 4614 mov r4, r2 8014668: 2c00 cmp r4, #0 801466a: 4605 mov r5, r0 801466c: 461a mov r2, r3 801466e: b09b sub sp, #108 @ 0x6c 8014670: da05 bge.n 801467e <_vsniprintf_r+0x1a> 8014672: 238b movs r3, #139 @ 0x8b 8014674: 6003 str r3, [r0, #0] 8014676: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801467a: b01b add sp, #108 @ 0x6c 801467c: bd30 pop {r4, r5, pc} 801467e: f44f 7302 mov.w r3, #520 @ 0x208 8014682: f8ad 300c strh.w r3, [sp, #12] 8014686: f04f 0300 mov.w r3, #0 801468a: 9319 str r3, [sp, #100] @ 0x64 801468c: bf0c ite eq 801468e: 4623 moveq r3, r4 8014690: f104 33ff addne.w r3, r4, #4294967295 @ 0xffffffff 8014694: 9302 str r3, [sp, #8] 8014696: 9305 str r3, [sp, #20] 8014698: f64f 73ff movw r3, #65535 @ 0xffff 801469c: 9100 str r1, [sp, #0] 801469e: 9104 str r1, [sp, #16] 80146a0: f8ad 300e strh.w r3, [sp, #14] 80146a4: 4669 mov r1, sp 80146a6: 9b1e ldr r3, [sp, #120] @ 0x78 80146a8: f000 ff76 bl 8015598 <_svfiprintf_r> 80146ac: 1c43 adds r3, r0, #1 80146ae: bfbc itt lt 80146b0: 238b movlt r3, #139 @ 0x8b 80146b2: 602b strlt r3, [r5, #0] 80146b4: 2c00 cmp r4, #0 80146b6: d0e0 beq.n 801467a <_vsniprintf_r+0x16> 80146b8: 2200 movs r2, #0 80146ba: 9b00 ldr r3, [sp, #0] 80146bc: 701a strb r2, [r3, #0] 80146be: e7dc b.n 801467a <_vsniprintf_r+0x16> 080146c0 : 80146c0: b507 push {r0, r1, r2, lr} 80146c2: 9300 str r3, [sp, #0] 80146c4: 4613 mov r3, r2 80146c6: 460a mov r2, r1 80146c8: 4601 mov r1, r0 80146ca: 4803 ldr r0, [pc, #12] @ (80146d8 ) 80146cc: 6800 ldr r0, [r0, #0] 80146ce: f7ff ffc9 bl 8014664 <_vsniprintf_r> 80146d2: b003 add sp, #12 80146d4: f85d fb04 ldr.w pc, [sp], #4 80146d8: 2000009c .word 0x2000009c 080146dc <_fwalk_sglue>: 80146dc: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 80146e0: 4607 mov r7, r0 80146e2: 4688 mov r8, r1 80146e4: 4614 mov r4, r2 80146e6: 2600 movs r6, #0 80146e8: e9d4 9501 ldrd r9, r5, [r4, #4] 80146ec: f1b9 0901 subs.w r9, r9, #1 80146f0: d505 bpl.n 80146fe <_fwalk_sglue+0x22> 80146f2: 6824 ldr r4, [r4, #0] 80146f4: 2c00 cmp r4, #0 80146f6: d1f7 bne.n 80146e8 <_fwalk_sglue+0xc> 80146f8: 4630 mov r0, r6 80146fa: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 80146fe: 89ab ldrh r3, [r5, #12] 8014700: 2b01 cmp r3, #1 8014702: d907 bls.n 8014714 <_fwalk_sglue+0x38> 8014704: f9b5 300e ldrsh.w r3, [r5, #14] 8014708: 3301 adds r3, #1 801470a: d003 beq.n 8014714 <_fwalk_sglue+0x38> 801470c: 4629 mov r1, r5 801470e: 4638 mov r0, r7 8014710: 47c0 blx r8 8014712: 4306 orrs r6, r0 8014714: 3568 adds r5, #104 @ 0x68 8014716: e7e9 b.n 80146ec <_fwalk_sglue+0x10> 08014718 : 8014718: b40f push {r0, r1, r2, r3} 801471a: b507 push {r0, r1, r2, lr} 801471c: 4906 ldr r1, [pc, #24] @ (8014738 ) 801471e: ab04 add r3, sp, #16 8014720: 6808 ldr r0, [r1, #0] 8014722: f853 2b04 ldr.w r2, [r3], #4 8014726: 6881 ldr r1, [r0, #8] 8014728: 9301 str r3, [sp, #4] 801472a: f001 f859 bl 80157e0 <_vfiprintf_r> 801472e: b003 add sp, #12 8014730: f85d eb04 ldr.w lr, [sp], #4 8014734: b004 add sp, #16 8014736: 4770 bx lr 8014738: 2000009c .word 0x2000009c 0801473c : 801473c: 4603 mov r3, r0 801473e: 4402 add r2, r0 8014740: 4293 cmp r3, r2 8014742: d100 bne.n 8014746 8014744: 4770 bx lr 8014746: f803 1b01 strb.w r1, [r3], #1 801474a: e7f9 b.n 8014740 0801474c <__errno>: 801474c: 4b01 ldr r3, [pc, #4] @ (8014754 <__errno+0x8>) 801474e: 6818 ldr r0, [r3, #0] 8014750: 4770 bx lr 8014752: bf00 nop 8014754: 2000009c .word 0x2000009c 08014758 <__libc_init_array>: 8014758: b570 push {r4, r5, r6, lr} 801475a: 2600 movs r6, #0 801475c: 4d0c ldr r5, [pc, #48] @ (8014790 <__libc_init_array+0x38>) 801475e: 4c0d ldr r4, [pc, #52] @ (8014794 <__libc_init_array+0x3c>) 8014760: 1b64 subs r4, r4, r5 8014762: 10a4 asrs r4, r4, #2 8014764: 42a6 cmp r6, r4 8014766: d109 bne.n 801477c <__libc_init_array+0x24> 8014768: f002 f906 bl 8016978 <_init> 801476c: 2600 movs r6, #0 801476e: 4d0a ldr r5, [pc, #40] @ (8014798 <__libc_init_array+0x40>) 8014770: 4c0a ldr r4, [pc, #40] @ (801479c <__libc_init_array+0x44>) 8014772: 1b64 subs r4, r4, r5 8014774: 10a4 asrs r4, r4, #2 8014776: 42a6 cmp r6, r4 8014778: d105 bne.n 8014786 <__libc_init_array+0x2e> 801477a: bd70 pop {r4, r5, r6, pc} 801477c: f855 3b04 ldr.w r3, [r5], #4 8014780: 4798 blx r3 8014782: 3601 adds r6, #1 8014784: e7ee b.n 8014764 <__libc_init_array+0xc> 8014786: f855 3b04 ldr.w r3, [r5], #4 801478a: 4798 blx r3 801478c: 3601 adds r6, #1 801478e: e7f2 b.n 8014776 <__libc_init_array+0x1e> 8014790: 080175fc .word 0x080175fc 8014794: 080175fc .word 0x080175fc 8014798: 080175fc .word 0x080175fc 801479c: 08017600 .word 0x08017600 080147a0 <__retarget_lock_init_recursive>: 80147a0: 4770 bx lr 080147a2 <__retarget_lock_acquire_recursive>: 80147a2: 4770 bx lr 080147a4 <__retarget_lock_release_recursive>: 80147a4: 4770 bx lr ... 080147a8 <_localeconv_r>: 80147a8: 4800 ldr r0, [pc, #0] @ (80147ac <_localeconv_r+0x4>) 80147aa: 4770 bx lr 80147ac: 200001dc .word 0x200001dc 080147b0 : 80147b0: 4603 mov r3, r0 80147b2: b510 push {r4, lr} 80147b4: b2c9 uxtb r1, r1 80147b6: 4402 add r2, r0 80147b8: 4293 cmp r3, r2 80147ba: 4618 mov r0, r3 80147bc: d101 bne.n 80147c2 80147be: 2000 movs r0, #0 80147c0: e003 b.n 80147ca 80147c2: 7804 ldrb r4, [r0, #0] 80147c4: 3301 adds r3, #1 80147c6: 428c cmp r4, r1 80147c8: d1f6 bne.n 80147b8 80147ca: bd10 pop {r4, pc} 080147cc : 80147cc: 440a add r2, r1 80147ce: 4291 cmp r1, r2 80147d0: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 80147d4: d100 bne.n 80147d8 80147d6: 4770 bx lr 80147d8: b510 push {r4, lr} 80147da: f811 4b01 ldrb.w r4, [r1], #1 80147de: 4291 cmp r1, r2 80147e0: f803 4f01 strb.w r4, [r3, #1]! 80147e4: d1f9 bne.n 80147da 80147e6: bd10 pop {r4, pc} 080147e8 <__assert_func>: 80147e8: b51f push {r0, r1, r2, r3, r4, lr} 80147ea: 4614 mov r4, r2 80147ec: 461a mov r2, r3 80147ee: 4b09 ldr r3, [pc, #36] @ (8014814 <__assert_func+0x2c>) 80147f0: 4605 mov r5, r0 80147f2: 681b ldr r3, [r3, #0] 80147f4: 68d8 ldr r0, [r3, #12] 80147f6: b14c cbz r4, 801480c <__assert_func+0x24> 80147f8: 4b07 ldr r3, [pc, #28] @ (8014818 <__assert_func+0x30>) 80147fa: e9cd 3401 strd r3, r4, [sp, #4] 80147fe: 9100 str r1, [sp, #0] 8014800: 462b mov r3, r5 8014802: 4906 ldr r1, [pc, #24] @ (801481c <__assert_func+0x34>) 8014804: f001 fe20 bl 8016448 8014808: f001 ffe6 bl 80167d8 801480c: 4b04 ldr r3, [pc, #16] @ (8014820 <__assert_func+0x38>) 801480e: 461c mov r4, r3 8014810: e7f3 b.n 80147fa <__assert_func+0x12> 8014812: bf00 nop 8014814: 2000009c .word 0x2000009c 8014818: 080172b0 .word 0x080172b0 801481c: 080172bd .word 0x080172bd 8014820: 080172eb .word 0x080172eb 08014824 : 8014824: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8014828: 6903 ldr r3, [r0, #16] 801482a: 690c ldr r4, [r1, #16] 801482c: 4607 mov r7, r0 801482e: 42a3 cmp r3, r4 8014830: db7e blt.n 8014930 8014832: 3c01 subs r4, #1 8014834: 00a3 lsls r3, r4, #2 8014836: f100 0514 add.w r5, r0, #20 801483a: f101 0814 add.w r8, r1, #20 801483e: 9300 str r3, [sp, #0] 8014840: eb05 0384 add.w r3, r5, r4, lsl #2 8014844: 9301 str r3, [sp, #4] 8014846: f858 3024 ldr.w r3, [r8, r4, lsl #2] 801484a: f855 2024 ldr.w r2, [r5, r4, lsl #2] 801484e: 3301 adds r3, #1 8014850: 429a cmp r2, r3 8014852: fbb2 f6f3 udiv r6, r2, r3 8014856: eb08 0984 add.w r9, r8, r4, lsl #2 801485a: d32e bcc.n 80148ba 801485c: f04f 0a00 mov.w sl, #0 8014860: 46c4 mov ip, r8 8014862: 46ae mov lr, r5 8014864: 46d3 mov fp, sl 8014866: f85c 3b04 ldr.w r3, [ip], #4 801486a: b298 uxth r0, r3 801486c: fb06 a000 mla r0, r6, r0, sl 8014870: 0c1b lsrs r3, r3, #16 8014872: 0c02 lsrs r2, r0, #16 8014874: fb06 2303 mla r3, r6, r3, r2 8014878: f8de 2000 ldr.w r2, [lr] 801487c: b280 uxth r0, r0 801487e: b292 uxth r2, r2 8014880: 1a12 subs r2, r2, r0 8014882: 445a add r2, fp 8014884: f8de 0000 ldr.w r0, [lr] 8014888: ea4f 4a13 mov.w sl, r3, lsr #16 801488c: b29b uxth r3, r3 801488e: ebc3 4322 rsb r3, r3, r2, asr #16 8014892: eb03 4310 add.w r3, r3, r0, lsr #16 8014896: b292 uxth r2, r2 8014898: ea42 4203 orr.w r2, r2, r3, lsl #16 801489c: 45e1 cmp r9, ip 801489e: ea4f 4b23 mov.w fp, r3, asr #16 80148a2: f84e 2b04 str.w r2, [lr], #4 80148a6: d2de bcs.n 8014866 80148a8: 9b00 ldr r3, [sp, #0] 80148aa: 58eb ldr r3, [r5, r3] 80148ac: b92b cbnz r3, 80148ba 80148ae: 9b01 ldr r3, [sp, #4] 80148b0: 3b04 subs r3, #4 80148b2: 429d cmp r5, r3 80148b4: 461a mov r2, r3 80148b6: d32f bcc.n 8014918 80148b8: 613c str r4, [r7, #16] 80148ba: 4638 mov r0, r7 80148bc: f001 fc78 bl 80161b0 <__mcmp> 80148c0: 2800 cmp r0, #0 80148c2: db25 blt.n 8014910 80148c4: 4629 mov r1, r5 80148c6: 2000 movs r0, #0 80148c8: f858 2b04 ldr.w r2, [r8], #4 80148cc: f8d1 c000 ldr.w ip, [r1] 80148d0: fa1f fe82 uxth.w lr, r2 80148d4: fa1f f38c uxth.w r3, ip 80148d8: eba3 030e sub.w r3, r3, lr 80148dc: 4403 add r3, r0 80148de: 0c12 lsrs r2, r2, #16 80148e0: ebc2 4223 rsb r2, r2, r3, asr #16 80148e4: eb02 421c add.w r2, r2, ip, lsr #16 80148e8: b29b uxth r3, r3 80148ea: ea43 4302 orr.w r3, r3, r2, lsl #16 80148ee: 45c1 cmp r9, r8 80148f0: ea4f 4022 mov.w r0, r2, asr #16 80148f4: f841 3b04 str.w r3, [r1], #4 80148f8: d2e6 bcs.n 80148c8 80148fa: f855 2024 ldr.w r2, [r5, r4, lsl #2] 80148fe: eb05 0384 add.w r3, r5, r4, lsl #2 8014902: b922 cbnz r2, 801490e 8014904: 3b04 subs r3, #4 8014906: 429d cmp r5, r3 8014908: 461a mov r2, r3 801490a: d30b bcc.n 8014924 801490c: 613c str r4, [r7, #16] 801490e: 3601 adds r6, #1 8014910: 4630 mov r0, r6 8014912: b003 add sp, #12 8014914: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8014918: 6812 ldr r2, [r2, #0] 801491a: 3b04 subs r3, #4 801491c: 2a00 cmp r2, #0 801491e: d1cb bne.n 80148b8 8014920: 3c01 subs r4, #1 8014922: e7c6 b.n 80148b2 8014924: 6812 ldr r2, [r2, #0] 8014926: 3b04 subs r3, #4 8014928: 2a00 cmp r2, #0 801492a: d1ef bne.n 801490c 801492c: 3c01 subs r4, #1 801492e: e7ea b.n 8014906 8014930: 2000 movs r0, #0 8014932: e7ee b.n 8014912 8014934: 0000 movs r0, r0 ... 08014938 <_dtoa_r>: 8014938: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801493c: 4614 mov r4, r2 801493e: 461d mov r5, r3 8014940: 69c7 ldr r7, [r0, #28] 8014942: b097 sub sp, #92 @ 0x5c 8014944: 4681 mov r9, r0 8014946: e9cd 4506 strd r4, r5, [sp, #24] 801494a: 9e23 ldr r6, [sp, #140] @ 0x8c 801494c: b97f cbnz r7, 801496e <_dtoa_r+0x36> 801494e: 2010 movs r0, #16 8014950: f001 f85e bl 8015a10 8014954: 4602 mov r2, r0 8014956: f8c9 001c str.w r0, [r9, #28] 801495a: b920 cbnz r0, 8014966 <_dtoa_r+0x2e> 801495c: 21ef movs r1, #239 @ 0xef 801495e: 4bac ldr r3, [pc, #688] @ (8014c10 <_dtoa_r+0x2d8>) 8014960: 48ac ldr r0, [pc, #688] @ (8014c14 <_dtoa_r+0x2dc>) 8014962: f7ff ff41 bl 80147e8 <__assert_func> 8014966: e9c0 7701 strd r7, r7, [r0, #4] 801496a: 6007 str r7, [r0, #0] 801496c: 60c7 str r7, [r0, #12] 801496e: f8d9 301c ldr.w r3, [r9, #28] 8014972: 6819 ldr r1, [r3, #0] 8014974: b159 cbz r1, 801498e <_dtoa_r+0x56> 8014976: 685a ldr r2, [r3, #4] 8014978: 2301 movs r3, #1 801497a: 4093 lsls r3, r2 801497c: 604a str r2, [r1, #4] 801497e: 608b str r3, [r1, #8] 8014980: 4648 mov r0, r9 8014982: f001 f9e3 bl 8015d4c <_Bfree> 8014986: 2200 movs r2, #0 8014988: f8d9 301c ldr.w r3, [r9, #28] 801498c: 601a str r2, [r3, #0] 801498e: 1e2b subs r3, r5, #0 8014990: bfaf iteee ge 8014992: 2300 movge r3, #0 8014994: 2201 movlt r2, #1 8014996: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000 801499a: 9307 strlt r3, [sp, #28] 801499c: bfa8 it ge 801499e: 6033 strge r3, [r6, #0] 80149a0: f8dd 801c ldr.w r8, [sp, #28] 80149a4: 4b9c ldr r3, [pc, #624] @ (8014c18 <_dtoa_r+0x2e0>) 80149a6: bfb8 it lt 80149a8: 6032 strlt r2, [r6, #0] 80149aa: ea33 0308 bics.w r3, r3, r8 80149ae: d112 bne.n 80149d6 <_dtoa_r+0x9e> 80149b0: f242 730f movw r3, #9999 @ 0x270f 80149b4: 9a22 ldr r2, [sp, #136] @ 0x88 80149b6: 6013 str r3, [r2, #0] 80149b8: f3c8 0313 ubfx r3, r8, #0, #20 80149bc: 4323 orrs r3, r4 80149be: f000 855e beq.w 801547e <_dtoa_r+0xb46> 80149c2: 9b24 ldr r3, [sp, #144] @ 0x90 80149c4: f8df a254 ldr.w sl, [pc, #596] @ 8014c1c <_dtoa_r+0x2e4> 80149c8: 2b00 cmp r3, #0 80149ca: f000 8560 beq.w 801548e <_dtoa_r+0xb56> 80149ce: f10a 0303 add.w r3, sl, #3 80149d2: f000 bd5a b.w 801548a <_dtoa_r+0xb52> 80149d6: e9dd 2306 ldrd r2, r3, [sp, #24] 80149da: e9cd 230c strd r2, r3, [sp, #48] @ 0x30 80149de: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 80149e2: 2200 movs r2, #0 80149e4: 2300 movs r3, #0 80149e6: f7f4 f84b bl 8008a80 <__aeabi_dcmpeq> 80149ea: 4607 mov r7, r0 80149ec: b158 cbz r0, 8014a06 <_dtoa_r+0xce> 80149ee: 2301 movs r3, #1 80149f0: 9a22 ldr r2, [sp, #136] @ 0x88 80149f2: 6013 str r3, [r2, #0] 80149f4: 9b24 ldr r3, [sp, #144] @ 0x90 80149f6: b113 cbz r3, 80149fe <_dtoa_r+0xc6> 80149f8: 4b89 ldr r3, [pc, #548] @ (8014c20 <_dtoa_r+0x2e8>) 80149fa: 9a24 ldr r2, [sp, #144] @ 0x90 80149fc: 6013 str r3, [r2, #0] 80149fe: f8df a224 ldr.w sl, [pc, #548] @ 8014c24 <_dtoa_r+0x2ec> 8014a02: f000 bd44 b.w 801548e <_dtoa_r+0xb56> 8014a06: ab14 add r3, sp, #80 @ 0x50 8014a08: 9301 str r3, [sp, #4] 8014a0a: ab15 add r3, sp, #84 @ 0x54 8014a0c: 9300 str r3, [sp, #0] 8014a0e: 4648 mov r0, r9 8014a10: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30 8014a14: f001 fc7c bl 8016310 <__d2b> 8014a18: f3c8 560a ubfx r6, r8, #20, #11 8014a1c: 9003 str r0, [sp, #12] 8014a1e: 2e00 cmp r6, #0 8014a20: d078 beq.n 8014b14 <_dtoa_r+0x1dc> 8014a22: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8014a26: 9b0d ldr r3, [sp, #52] @ 0x34 8014a28: f2a6 36ff subw r6, r6, #1023 @ 0x3ff 8014a2c: f3c3 0313 ubfx r3, r3, #0, #20 8014a30: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000 8014a34: f443 1340 orr.w r3, r3, #3145728 @ 0x300000 8014a38: 9712 str r7, [sp, #72] @ 0x48 8014a3a: 4619 mov r1, r3 8014a3c: 2200 movs r2, #0 8014a3e: 4b7a ldr r3, [pc, #488] @ (8014c28 <_dtoa_r+0x2f0>) 8014a40: f7f3 fbfe bl 8008240 <__aeabi_dsub> 8014a44: a36c add r3, pc, #432 @ (adr r3, 8014bf8 <_dtoa_r+0x2c0>) 8014a46: e9d3 2300 ldrd r2, r3, [r3] 8014a4a: f7f3 fdb1 bl 80085b0 <__aeabi_dmul> 8014a4e: a36c add r3, pc, #432 @ (adr r3, 8014c00 <_dtoa_r+0x2c8>) 8014a50: e9d3 2300 ldrd r2, r3, [r3] 8014a54: f7f3 fbf6 bl 8008244 <__adddf3> 8014a58: 4604 mov r4, r0 8014a5a: 4630 mov r0, r6 8014a5c: 460d mov r5, r1 8014a5e: f7f3 fd3d bl 80084dc <__aeabi_i2d> 8014a62: a369 add r3, pc, #420 @ (adr r3, 8014c08 <_dtoa_r+0x2d0>) 8014a64: e9d3 2300 ldrd r2, r3, [r3] 8014a68: f7f3 fda2 bl 80085b0 <__aeabi_dmul> 8014a6c: 4602 mov r2, r0 8014a6e: 460b mov r3, r1 8014a70: 4620 mov r0, r4 8014a72: 4629 mov r1, r5 8014a74: f7f3 fbe6 bl 8008244 <__adddf3> 8014a78: 4604 mov r4, r0 8014a7a: 460d mov r5, r1 8014a7c: f7f4 f848 bl 8008b10 <__aeabi_d2iz> 8014a80: 2200 movs r2, #0 8014a82: 4607 mov r7, r0 8014a84: 2300 movs r3, #0 8014a86: 4620 mov r0, r4 8014a88: 4629 mov r1, r5 8014a8a: f7f4 f803 bl 8008a94 <__aeabi_dcmplt> 8014a8e: b140 cbz r0, 8014aa2 <_dtoa_r+0x16a> 8014a90: 4638 mov r0, r7 8014a92: f7f3 fd23 bl 80084dc <__aeabi_i2d> 8014a96: 4622 mov r2, r4 8014a98: 462b mov r3, r5 8014a9a: f7f3 fff1 bl 8008a80 <__aeabi_dcmpeq> 8014a9e: b900 cbnz r0, 8014aa2 <_dtoa_r+0x16a> 8014aa0: 3f01 subs r7, #1 8014aa2: 2f16 cmp r7, #22 8014aa4: d854 bhi.n 8014b50 <_dtoa_r+0x218> 8014aa6: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8014aaa: 4b60 ldr r3, [pc, #384] @ (8014c2c <_dtoa_r+0x2f4>) 8014aac: eb03 03c7 add.w r3, r3, r7, lsl #3 8014ab0: e9d3 2300 ldrd r2, r3, [r3] 8014ab4: f7f3 ffee bl 8008a94 <__aeabi_dcmplt> 8014ab8: 2800 cmp r0, #0 8014aba: d04b beq.n 8014b54 <_dtoa_r+0x21c> 8014abc: 2300 movs r3, #0 8014abe: 3f01 subs r7, #1 8014ac0: 930f str r3, [sp, #60] @ 0x3c 8014ac2: 9b14 ldr r3, [sp, #80] @ 0x50 8014ac4: 1b9b subs r3, r3, r6 8014ac6: 1e5a subs r2, r3, #1 8014ac8: bf49 itett mi 8014aca: f1c3 0301 rsbmi r3, r3, #1 8014ace: 2300 movpl r3, #0 8014ad0: 9304 strmi r3, [sp, #16] 8014ad2: 2300 movmi r3, #0 8014ad4: 9209 str r2, [sp, #36] @ 0x24 8014ad6: bf54 ite pl 8014ad8: 9304 strpl r3, [sp, #16] 8014ada: 9309 strmi r3, [sp, #36] @ 0x24 8014adc: 2f00 cmp r7, #0 8014ade: db3b blt.n 8014b58 <_dtoa_r+0x220> 8014ae0: 9b09 ldr r3, [sp, #36] @ 0x24 8014ae2: 970e str r7, [sp, #56] @ 0x38 8014ae4: 443b add r3, r7 8014ae6: 9309 str r3, [sp, #36] @ 0x24 8014ae8: 2300 movs r3, #0 8014aea: 930a str r3, [sp, #40] @ 0x28 8014aec: 9b20 ldr r3, [sp, #128] @ 0x80 8014aee: 2b09 cmp r3, #9 8014af0: d865 bhi.n 8014bbe <_dtoa_r+0x286> 8014af2: 2b05 cmp r3, #5 8014af4: bfc4 itt gt 8014af6: 3b04 subgt r3, #4 8014af8: 9320 strgt r3, [sp, #128] @ 0x80 8014afa: 9b20 ldr r3, [sp, #128] @ 0x80 8014afc: bfc8 it gt 8014afe: 2400 movgt r4, #0 8014b00: f1a3 0302 sub.w r3, r3, #2 8014b04: bfd8 it le 8014b06: 2401 movle r4, #1 8014b08: 2b03 cmp r3, #3 8014b0a: d864 bhi.n 8014bd6 <_dtoa_r+0x29e> 8014b0c: e8df f003 tbb [pc, r3] 8014b10: 2c385553 .word 0x2c385553 8014b14: e9dd 6314 ldrd r6, r3, [sp, #80] @ 0x50 8014b18: 441e add r6, r3 8014b1a: f206 4332 addw r3, r6, #1074 @ 0x432 8014b1e: 2b20 cmp r3, #32 8014b20: bfc1 itttt gt 8014b22: f1c3 0340 rsbgt r3, r3, #64 @ 0x40 8014b26: fa08 f803 lslgt.w r8, r8, r3 8014b2a: f206 4312 addwgt r3, r6, #1042 @ 0x412 8014b2e: fa24 f303 lsrgt.w r3, r4, r3 8014b32: bfd6 itet le 8014b34: f1c3 0320 rsble r3, r3, #32 8014b38: ea48 0003 orrgt.w r0, r8, r3 8014b3c: fa04 f003 lslle.w r0, r4, r3 8014b40: f7f3 fcbc bl 80084bc <__aeabi_ui2d> 8014b44: 2201 movs r2, #1 8014b46: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000 8014b4a: 3e01 subs r6, #1 8014b4c: 9212 str r2, [sp, #72] @ 0x48 8014b4e: e774 b.n 8014a3a <_dtoa_r+0x102> 8014b50: 2301 movs r3, #1 8014b52: e7b5 b.n 8014ac0 <_dtoa_r+0x188> 8014b54: 900f str r0, [sp, #60] @ 0x3c 8014b56: e7b4 b.n 8014ac2 <_dtoa_r+0x18a> 8014b58: 9b04 ldr r3, [sp, #16] 8014b5a: 1bdb subs r3, r3, r7 8014b5c: 9304 str r3, [sp, #16] 8014b5e: 427b negs r3, r7 8014b60: 930a str r3, [sp, #40] @ 0x28 8014b62: 2300 movs r3, #0 8014b64: 930e str r3, [sp, #56] @ 0x38 8014b66: e7c1 b.n 8014aec <_dtoa_r+0x1b4> 8014b68: 2301 movs r3, #1 8014b6a: 930b str r3, [sp, #44] @ 0x2c 8014b6c: 9b21 ldr r3, [sp, #132] @ 0x84 8014b6e: eb07 0b03 add.w fp, r7, r3 8014b72: f10b 0301 add.w r3, fp, #1 8014b76: 2b01 cmp r3, #1 8014b78: 9308 str r3, [sp, #32] 8014b7a: bfb8 it lt 8014b7c: 2301 movlt r3, #1 8014b7e: e006 b.n 8014b8e <_dtoa_r+0x256> 8014b80: 2301 movs r3, #1 8014b82: 930b str r3, [sp, #44] @ 0x2c 8014b84: 9b21 ldr r3, [sp, #132] @ 0x84 8014b86: 2b00 cmp r3, #0 8014b88: dd28 ble.n 8014bdc <_dtoa_r+0x2a4> 8014b8a: 469b mov fp, r3 8014b8c: 9308 str r3, [sp, #32] 8014b8e: 2100 movs r1, #0 8014b90: 2204 movs r2, #4 8014b92: f8d9 001c ldr.w r0, [r9, #28] 8014b96: f102 0514 add.w r5, r2, #20 8014b9a: 429d cmp r5, r3 8014b9c: d926 bls.n 8014bec <_dtoa_r+0x2b4> 8014b9e: 6041 str r1, [r0, #4] 8014ba0: 4648 mov r0, r9 8014ba2: f001 f893 bl 8015ccc <_Balloc> 8014ba6: 4682 mov sl, r0 8014ba8: 2800 cmp r0, #0 8014baa: d143 bne.n 8014c34 <_dtoa_r+0x2fc> 8014bac: 4602 mov r2, r0 8014bae: f240 11af movw r1, #431 @ 0x1af 8014bb2: 4b1f ldr r3, [pc, #124] @ (8014c30 <_dtoa_r+0x2f8>) 8014bb4: e6d4 b.n 8014960 <_dtoa_r+0x28> 8014bb6: 2300 movs r3, #0 8014bb8: e7e3 b.n 8014b82 <_dtoa_r+0x24a> 8014bba: 2300 movs r3, #0 8014bbc: e7d5 b.n 8014b6a <_dtoa_r+0x232> 8014bbe: 2401 movs r4, #1 8014bc0: 2300 movs r3, #0 8014bc2: 940b str r4, [sp, #44] @ 0x2c 8014bc4: 9320 str r3, [sp, #128] @ 0x80 8014bc6: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff 8014bca: 2200 movs r2, #0 8014bcc: 2312 movs r3, #18 8014bce: f8cd b020 str.w fp, [sp, #32] 8014bd2: 9221 str r2, [sp, #132] @ 0x84 8014bd4: e7db b.n 8014b8e <_dtoa_r+0x256> 8014bd6: 2301 movs r3, #1 8014bd8: 930b str r3, [sp, #44] @ 0x2c 8014bda: e7f4 b.n 8014bc6 <_dtoa_r+0x28e> 8014bdc: f04f 0b01 mov.w fp, #1 8014be0: 465b mov r3, fp 8014be2: f8cd b020 str.w fp, [sp, #32] 8014be6: f8cd b084 str.w fp, [sp, #132] @ 0x84 8014bea: e7d0 b.n 8014b8e <_dtoa_r+0x256> 8014bec: 3101 adds r1, #1 8014bee: 0052 lsls r2, r2, #1 8014bf0: e7d1 b.n 8014b96 <_dtoa_r+0x25e> 8014bf2: bf00 nop 8014bf4: f3af 8000 nop.w 8014bf8: 636f4361 .word 0x636f4361 8014bfc: 3fd287a7 .word 0x3fd287a7 8014c00: 8b60c8b3 .word 0x8b60c8b3 8014c04: 3fc68a28 .word 0x3fc68a28 8014c08: 509f79fb .word 0x509f79fb 8014c0c: 3fd34413 .word 0x3fd34413 8014c10: 080172f9 .word 0x080172f9 8014c14: 08017310 .word 0x08017310 8014c18: 7ff00000 .word 0x7ff00000 8014c1c: 080172f5 .word 0x080172f5 8014c20: 0801728d .word 0x0801728d 8014c24: 0801728c .word 0x0801728c 8014c28: 3ff80000 .word 0x3ff80000 8014c2c: 08017428 .word 0x08017428 8014c30: 08017368 .word 0x08017368 8014c34: f8d9 301c ldr.w r3, [r9, #28] 8014c38: 6018 str r0, [r3, #0] 8014c3a: 9b08 ldr r3, [sp, #32] 8014c3c: 2b0e cmp r3, #14 8014c3e: f200 80a1 bhi.w 8014d84 <_dtoa_r+0x44c> 8014c42: 2c00 cmp r4, #0 8014c44: f000 809e beq.w 8014d84 <_dtoa_r+0x44c> 8014c48: 2f00 cmp r7, #0 8014c4a: dd33 ble.n 8014cb4 <_dtoa_r+0x37c> 8014c4c: 4b9c ldr r3, [pc, #624] @ (8014ec0 <_dtoa_r+0x588>) 8014c4e: f007 020f and.w r2, r7, #15 8014c52: eb03 03c2 add.w r3, r3, r2, lsl #3 8014c56: 05f8 lsls r0, r7, #23 8014c58: e9d3 3400 ldrd r3, r4, [r3] 8014c5c: e9cd 3410 strd r3, r4, [sp, #64] @ 0x40 8014c60: ea4f 1427 mov.w r4, r7, asr #4 8014c64: d516 bpl.n 8014c94 <_dtoa_r+0x35c> 8014c66: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8014c6a: 4b96 ldr r3, [pc, #600] @ (8014ec4 <_dtoa_r+0x58c>) 8014c6c: 2603 movs r6, #3 8014c6e: e9d3 2308 ldrd r2, r3, [r3, #32] 8014c72: f7f3 fdc7 bl 8008804 <__aeabi_ddiv> 8014c76: e9cd 0106 strd r0, r1, [sp, #24] 8014c7a: f004 040f and.w r4, r4, #15 8014c7e: 4d91 ldr r5, [pc, #580] @ (8014ec4 <_dtoa_r+0x58c>) 8014c80: b954 cbnz r4, 8014c98 <_dtoa_r+0x360> 8014c82: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 8014c86: e9dd 0106 ldrd r0, r1, [sp, #24] 8014c8a: f7f3 fdbb bl 8008804 <__aeabi_ddiv> 8014c8e: e9cd 0106 strd r0, r1, [sp, #24] 8014c92: e028 b.n 8014ce6 <_dtoa_r+0x3ae> 8014c94: 2602 movs r6, #2 8014c96: e7f2 b.n 8014c7e <_dtoa_r+0x346> 8014c98: 07e1 lsls r1, r4, #31 8014c9a: d508 bpl.n 8014cae <_dtoa_r+0x376> 8014c9c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 8014ca0: e9d5 2300 ldrd r2, r3, [r5] 8014ca4: f7f3 fc84 bl 80085b0 <__aeabi_dmul> 8014ca8: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 8014cac: 3601 adds r6, #1 8014cae: 1064 asrs r4, r4, #1 8014cb0: 3508 adds r5, #8 8014cb2: e7e5 b.n 8014c80 <_dtoa_r+0x348> 8014cb4: f000 80af beq.w 8014e16 <_dtoa_r+0x4de> 8014cb8: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8014cbc: 427c negs r4, r7 8014cbe: 4b80 ldr r3, [pc, #512] @ (8014ec0 <_dtoa_r+0x588>) 8014cc0: f004 020f and.w r2, r4, #15 8014cc4: eb03 03c2 add.w r3, r3, r2, lsl #3 8014cc8: e9d3 2300 ldrd r2, r3, [r3] 8014ccc: f7f3 fc70 bl 80085b0 <__aeabi_dmul> 8014cd0: 2602 movs r6, #2 8014cd2: 2300 movs r3, #0 8014cd4: e9cd 0106 strd r0, r1, [sp, #24] 8014cd8: 4d7a ldr r5, [pc, #488] @ (8014ec4 <_dtoa_r+0x58c>) 8014cda: 1124 asrs r4, r4, #4 8014cdc: 2c00 cmp r4, #0 8014cde: f040 808f bne.w 8014e00 <_dtoa_r+0x4c8> 8014ce2: 2b00 cmp r3, #0 8014ce4: d1d3 bne.n 8014c8e <_dtoa_r+0x356> 8014ce6: e9dd 4506 ldrd r4, r5, [sp, #24] 8014cea: 9b0f ldr r3, [sp, #60] @ 0x3c 8014cec: 2b00 cmp r3, #0 8014cee: f000 8094 beq.w 8014e1a <_dtoa_r+0x4e2> 8014cf2: 2200 movs r2, #0 8014cf4: 4620 mov r0, r4 8014cf6: 4629 mov r1, r5 8014cf8: 4b73 ldr r3, [pc, #460] @ (8014ec8 <_dtoa_r+0x590>) 8014cfa: f7f3 fecb bl 8008a94 <__aeabi_dcmplt> 8014cfe: 2800 cmp r0, #0 8014d00: f000 808b beq.w 8014e1a <_dtoa_r+0x4e2> 8014d04: 9b08 ldr r3, [sp, #32] 8014d06: 2b00 cmp r3, #0 8014d08: f000 8087 beq.w 8014e1a <_dtoa_r+0x4e2> 8014d0c: f1bb 0f00 cmp.w fp, #0 8014d10: dd34 ble.n 8014d7c <_dtoa_r+0x444> 8014d12: 4620 mov r0, r4 8014d14: 2200 movs r2, #0 8014d16: 4629 mov r1, r5 8014d18: 4b6c ldr r3, [pc, #432] @ (8014ecc <_dtoa_r+0x594>) 8014d1a: f7f3 fc49 bl 80085b0 <__aeabi_dmul> 8014d1e: 465c mov r4, fp 8014d20: e9cd 0106 strd r0, r1, [sp, #24] 8014d24: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff 8014d28: 3601 adds r6, #1 8014d2a: 4630 mov r0, r6 8014d2c: f7f3 fbd6 bl 80084dc <__aeabi_i2d> 8014d30: e9dd 2306 ldrd r2, r3, [sp, #24] 8014d34: f7f3 fc3c bl 80085b0 <__aeabi_dmul> 8014d38: 2200 movs r2, #0 8014d3a: 4b65 ldr r3, [pc, #404] @ (8014ed0 <_dtoa_r+0x598>) 8014d3c: f7f3 fa82 bl 8008244 <__adddf3> 8014d40: 4605 mov r5, r0 8014d42: f1a1 7650 sub.w r6, r1, #54525952 @ 0x3400000 8014d46: 2c00 cmp r4, #0 8014d48: d16a bne.n 8014e20 <_dtoa_r+0x4e8> 8014d4a: e9dd 0106 ldrd r0, r1, [sp, #24] 8014d4e: 2200 movs r2, #0 8014d50: 4b60 ldr r3, [pc, #384] @ (8014ed4 <_dtoa_r+0x59c>) 8014d52: f7f3 fa75 bl 8008240 <__aeabi_dsub> 8014d56: 4602 mov r2, r0 8014d58: 460b mov r3, r1 8014d5a: e9cd 2306 strd r2, r3, [sp, #24] 8014d5e: 462a mov r2, r5 8014d60: 4633 mov r3, r6 8014d62: f7f3 feb5 bl 8008ad0 <__aeabi_dcmpgt> 8014d66: 2800 cmp r0, #0 8014d68: f040 8298 bne.w 801529c <_dtoa_r+0x964> 8014d6c: e9dd 0106 ldrd r0, r1, [sp, #24] 8014d70: 462a mov r2, r5 8014d72: f106 4300 add.w r3, r6, #2147483648 @ 0x80000000 8014d76: f7f3 fe8d bl 8008a94 <__aeabi_dcmplt> 8014d7a: bb38 cbnz r0, 8014dcc <_dtoa_r+0x494> 8014d7c: e9dd 340c ldrd r3, r4, [sp, #48] @ 0x30 8014d80: e9cd 3406 strd r3, r4, [sp, #24] 8014d84: 9b15 ldr r3, [sp, #84] @ 0x54 8014d86: 2b00 cmp r3, #0 8014d88: f2c0 8157 blt.w 801503a <_dtoa_r+0x702> 8014d8c: 2f0e cmp r7, #14 8014d8e: f300 8154 bgt.w 801503a <_dtoa_r+0x702> 8014d92: 4b4b ldr r3, [pc, #300] @ (8014ec0 <_dtoa_r+0x588>) 8014d94: eb03 03c7 add.w r3, r3, r7, lsl #3 8014d98: e9d3 3400 ldrd r3, r4, [r3] 8014d9c: e9cd 3404 strd r3, r4, [sp, #16] 8014da0: 9b21 ldr r3, [sp, #132] @ 0x84 8014da2: 2b00 cmp r3, #0 8014da4: f280 80e5 bge.w 8014f72 <_dtoa_r+0x63a> 8014da8: 9b08 ldr r3, [sp, #32] 8014daa: 2b00 cmp r3, #0 8014dac: f300 80e1 bgt.w 8014f72 <_dtoa_r+0x63a> 8014db0: d10c bne.n 8014dcc <_dtoa_r+0x494> 8014db2: e9dd 0104 ldrd r0, r1, [sp, #16] 8014db6: 2200 movs r2, #0 8014db8: 4b46 ldr r3, [pc, #280] @ (8014ed4 <_dtoa_r+0x59c>) 8014dba: f7f3 fbf9 bl 80085b0 <__aeabi_dmul> 8014dbe: e9dd 2306 ldrd r2, r3, [sp, #24] 8014dc2: f7f3 fe7b bl 8008abc <__aeabi_dcmpge> 8014dc6: 2800 cmp r0, #0 8014dc8: f000 8266 beq.w 8015298 <_dtoa_r+0x960> 8014dcc: 2400 movs r4, #0 8014dce: 4625 mov r5, r4 8014dd0: 9b21 ldr r3, [sp, #132] @ 0x84 8014dd2: 4656 mov r6, sl 8014dd4: ea6f 0803 mvn.w r8, r3 8014dd8: 2700 movs r7, #0 8014dda: 4621 mov r1, r4 8014ddc: 4648 mov r0, r9 8014dde: f000 ffb5 bl 8015d4c <_Bfree> 8014de2: 2d00 cmp r5, #0 8014de4: f000 80bd beq.w 8014f62 <_dtoa_r+0x62a> 8014de8: b12f cbz r7, 8014df6 <_dtoa_r+0x4be> 8014dea: 42af cmp r7, r5 8014dec: d003 beq.n 8014df6 <_dtoa_r+0x4be> 8014dee: 4639 mov r1, r7 8014df0: 4648 mov r0, r9 8014df2: f000 ffab bl 8015d4c <_Bfree> 8014df6: 4629 mov r1, r5 8014df8: 4648 mov r0, r9 8014dfa: f000 ffa7 bl 8015d4c <_Bfree> 8014dfe: e0b0 b.n 8014f62 <_dtoa_r+0x62a> 8014e00: 07e2 lsls r2, r4, #31 8014e02: d505 bpl.n 8014e10 <_dtoa_r+0x4d8> 8014e04: e9d5 2300 ldrd r2, r3, [r5] 8014e08: f7f3 fbd2 bl 80085b0 <__aeabi_dmul> 8014e0c: 2301 movs r3, #1 8014e0e: 3601 adds r6, #1 8014e10: 1064 asrs r4, r4, #1 8014e12: 3508 adds r5, #8 8014e14: e762 b.n 8014cdc <_dtoa_r+0x3a4> 8014e16: 2602 movs r6, #2 8014e18: e765 b.n 8014ce6 <_dtoa_r+0x3ae> 8014e1a: 46b8 mov r8, r7 8014e1c: 9c08 ldr r4, [sp, #32] 8014e1e: e784 b.n 8014d2a <_dtoa_r+0x3f2> 8014e20: 4b27 ldr r3, [pc, #156] @ (8014ec0 <_dtoa_r+0x588>) 8014e22: 990b ldr r1, [sp, #44] @ 0x2c 8014e24: eb03 03c4 add.w r3, r3, r4, lsl #3 8014e28: e953 2302 ldrd r2, r3, [r3, #-8] 8014e2c: 4454 add r4, sl 8014e2e: 2900 cmp r1, #0 8014e30: d054 beq.n 8014edc <_dtoa_r+0x5a4> 8014e32: 2000 movs r0, #0 8014e34: 4928 ldr r1, [pc, #160] @ (8014ed8 <_dtoa_r+0x5a0>) 8014e36: f7f3 fce5 bl 8008804 <__aeabi_ddiv> 8014e3a: 4633 mov r3, r6 8014e3c: 462a mov r2, r5 8014e3e: f7f3 f9ff bl 8008240 <__aeabi_dsub> 8014e42: 4656 mov r6, sl 8014e44: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 8014e48: e9dd 0106 ldrd r0, r1, [sp, #24] 8014e4c: f7f3 fe60 bl 8008b10 <__aeabi_d2iz> 8014e50: 4605 mov r5, r0 8014e52: f7f3 fb43 bl 80084dc <__aeabi_i2d> 8014e56: 4602 mov r2, r0 8014e58: 460b mov r3, r1 8014e5a: e9dd 0106 ldrd r0, r1, [sp, #24] 8014e5e: f7f3 f9ef bl 8008240 <__aeabi_dsub> 8014e62: 4602 mov r2, r0 8014e64: 460b mov r3, r1 8014e66: 3530 adds r5, #48 @ 0x30 8014e68: e9cd 2306 strd r2, r3, [sp, #24] 8014e6c: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 8014e70: f806 5b01 strb.w r5, [r6], #1 8014e74: f7f3 fe0e bl 8008a94 <__aeabi_dcmplt> 8014e78: 2800 cmp r0, #0 8014e7a: d172 bne.n 8014f62 <_dtoa_r+0x62a> 8014e7c: e9dd 2306 ldrd r2, r3, [sp, #24] 8014e80: 2000 movs r0, #0 8014e82: 4911 ldr r1, [pc, #68] @ (8014ec8 <_dtoa_r+0x590>) 8014e84: f7f3 f9dc bl 8008240 <__aeabi_dsub> 8014e88: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 8014e8c: f7f3 fe02 bl 8008a94 <__aeabi_dcmplt> 8014e90: 2800 cmp r0, #0 8014e92: f040 80b4 bne.w 8014ffe <_dtoa_r+0x6c6> 8014e96: 42a6 cmp r6, r4 8014e98: f43f af70 beq.w 8014d7c <_dtoa_r+0x444> 8014e9c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 8014ea0: 2200 movs r2, #0 8014ea2: 4b0a ldr r3, [pc, #40] @ (8014ecc <_dtoa_r+0x594>) 8014ea4: f7f3 fb84 bl 80085b0 <__aeabi_dmul> 8014ea8: 2200 movs r2, #0 8014eaa: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 8014eae: e9dd 0106 ldrd r0, r1, [sp, #24] 8014eb2: 4b06 ldr r3, [pc, #24] @ (8014ecc <_dtoa_r+0x594>) 8014eb4: f7f3 fb7c bl 80085b0 <__aeabi_dmul> 8014eb8: e9cd 0106 strd r0, r1, [sp, #24] 8014ebc: e7c4 b.n 8014e48 <_dtoa_r+0x510> 8014ebe: bf00 nop 8014ec0: 08017428 .word 0x08017428 8014ec4: 08017400 .word 0x08017400 8014ec8: 3ff00000 .word 0x3ff00000 8014ecc: 40240000 .word 0x40240000 8014ed0: 401c0000 .word 0x401c0000 8014ed4: 40140000 .word 0x40140000 8014ed8: 3fe00000 .word 0x3fe00000 8014edc: 4631 mov r1, r6 8014ede: 4628 mov r0, r5 8014ee0: f7f3 fb66 bl 80085b0 <__aeabi_dmul> 8014ee4: 4656 mov r6, sl 8014ee6: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 8014eea: 9413 str r4, [sp, #76] @ 0x4c 8014eec: e9dd 0106 ldrd r0, r1, [sp, #24] 8014ef0: f7f3 fe0e bl 8008b10 <__aeabi_d2iz> 8014ef4: 4605 mov r5, r0 8014ef6: f7f3 faf1 bl 80084dc <__aeabi_i2d> 8014efa: 4602 mov r2, r0 8014efc: 460b mov r3, r1 8014efe: e9dd 0106 ldrd r0, r1, [sp, #24] 8014f02: f7f3 f99d bl 8008240 <__aeabi_dsub> 8014f06: 4602 mov r2, r0 8014f08: 460b mov r3, r1 8014f0a: 3530 adds r5, #48 @ 0x30 8014f0c: f806 5b01 strb.w r5, [r6], #1 8014f10: 42a6 cmp r6, r4 8014f12: e9cd 2306 strd r2, r3, [sp, #24] 8014f16: f04f 0200 mov.w r2, #0 8014f1a: d124 bne.n 8014f66 <_dtoa_r+0x62e> 8014f1c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 8014f20: 4bae ldr r3, [pc, #696] @ (80151dc <_dtoa_r+0x8a4>) 8014f22: f7f3 f98f bl 8008244 <__adddf3> 8014f26: 4602 mov r2, r0 8014f28: 460b mov r3, r1 8014f2a: e9dd 0106 ldrd r0, r1, [sp, #24] 8014f2e: f7f3 fdcf bl 8008ad0 <__aeabi_dcmpgt> 8014f32: 2800 cmp r0, #0 8014f34: d163 bne.n 8014ffe <_dtoa_r+0x6c6> 8014f36: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 8014f3a: 2000 movs r0, #0 8014f3c: 49a7 ldr r1, [pc, #668] @ (80151dc <_dtoa_r+0x8a4>) 8014f3e: f7f3 f97f bl 8008240 <__aeabi_dsub> 8014f42: 4602 mov r2, r0 8014f44: 460b mov r3, r1 8014f46: e9dd 0106 ldrd r0, r1, [sp, #24] 8014f4a: f7f3 fda3 bl 8008a94 <__aeabi_dcmplt> 8014f4e: 2800 cmp r0, #0 8014f50: f43f af14 beq.w 8014d7c <_dtoa_r+0x444> 8014f54: 9e13 ldr r6, [sp, #76] @ 0x4c 8014f56: 1e73 subs r3, r6, #1 8014f58: 9313 str r3, [sp, #76] @ 0x4c 8014f5a: f816 3c01 ldrb.w r3, [r6, #-1] 8014f5e: 2b30 cmp r3, #48 @ 0x30 8014f60: d0f8 beq.n 8014f54 <_dtoa_r+0x61c> 8014f62: 4647 mov r7, r8 8014f64: e03b b.n 8014fde <_dtoa_r+0x6a6> 8014f66: 4b9e ldr r3, [pc, #632] @ (80151e0 <_dtoa_r+0x8a8>) 8014f68: f7f3 fb22 bl 80085b0 <__aeabi_dmul> 8014f6c: e9cd 0106 strd r0, r1, [sp, #24] 8014f70: e7bc b.n 8014eec <_dtoa_r+0x5b4> 8014f72: 4656 mov r6, sl 8014f74: e9dd 4506 ldrd r4, r5, [sp, #24] 8014f78: e9dd 2304 ldrd r2, r3, [sp, #16] 8014f7c: 4620 mov r0, r4 8014f7e: 4629 mov r1, r5 8014f80: f7f3 fc40 bl 8008804 <__aeabi_ddiv> 8014f84: f7f3 fdc4 bl 8008b10 <__aeabi_d2iz> 8014f88: 4680 mov r8, r0 8014f8a: f7f3 faa7 bl 80084dc <__aeabi_i2d> 8014f8e: e9dd 2304 ldrd r2, r3, [sp, #16] 8014f92: f7f3 fb0d bl 80085b0 <__aeabi_dmul> 8014f96: 4602 mov r2, r0 8014f98: 460b mov r3, r1 8014f9a: 4620 mov r0, r4 8014f9c: 4629 mov r1, r5 8014f9e: f7f3 f94f bl 8008240 <__aeabi_dsub> 8014fa2: f108 0430 add.w r4, r8, #48 @ 0x30 8014fa6: 9d08 ldr r5, [sp, #32] 8014fa8: f806 4b01 strb.w r4, [r6], #1 8014fac: eba6 040a sub.w r4, r6, sl 8014fb0: 42a5 cmp r5, r4 8014fb2: 4602 mov r2, r0 8014fb4: 460b mov r3, r1 8014fb6: d133 bne.n 8015020 <_dtoa_r+0x6e8> 8014fb8: f7f3 f944 bl 8008244 <__adddf3> 8014fbc: e9dd 2304 ldrd r2, r3, [sp, #16] 8014fc0: 4604 mov r4, r0 8014fc2: 460d mov r5, r1 8014fc4: f7f3 fd84 bl 8008ad0 <__aeabi_dcmpgt> 8014fc8: b9c0 cbnz r0, 8014ffc <_dtoa_r+0x6c4> 8014fca: e9dd 2304 ldrd r2, r3, [sp, #16] 8014fce: 4620 mov r0, r4 8014fd0: 4629 mov r1, r5 8014fd2: f7f3 fd55 bl 8008a80 <__aeabi_dcmpeq> 8014fd6: b110 cbz r0, 8014fde <_dtoa_r+0x6a6> 8014fd8: f018 0f01 tst.w r8, #1 8014fdc: d10e bne.n 8014ffc <_dtoa_r+0x6c4> 8014fde: 4648 mov r0, r9 8014fe0: 9903 ldr r1, [sp, #12] 8014fe2: f000 feb3 bl 8015d4c <_Bfree> 8014fe6: 2300 movs r3, #0 8014fe8: 7033 strb r3, [r6, #0] 8014fea: 9b22 ldr r3, [sp, #136] @ 0x88 8014fec: 3701 adds r7, #1 8014fee: 601f str r7, [r3, #0] 8014ff0: 9b24 ldr r3, [sp, #144] @ 0x90 8014ff2: 2b00 cmp r3, #0 8014ff4: f000 824b beq.w 801548e <_dtoa_r+0xb56> 8014ff8: 601e str r6, [r3, #0] 8014ffa: e248 b.n 801548e <_dtoa_r+0xb56> 8014ffc: 46b8 mov r8, r7 8014ffe: 4633 mov r3, r6 8015000: 461e mov r6, r3 8015002: f813 2d01 ldrb.w r2, [r3, #-1]! 8015006: 2a39 cmp r2, #57 @ 0x39 8015008: d106 bne.n 8015018 <_dtoa_r+0x6e0> 801500a: 459a cmp sl, r3 801500c: d1f8 bne.n 8015000 <_dtoa_r+0x6c8> 801500e: 2230 movs r2, #48 @ 0x30 8015010: f108 0801 add.w r8, r8, #1 8015014: f88a 2000 strb.w r2, [sl] 8015018: 781a ldrb r2, [r3, #0] 801501a: 3201 adds r2, #1 801501c: 701a strb r2, [r3, #0] 801501e: e7a0 b.n 8014f62 <_dtoa_r+0x62a> 8015020: 2200 movs r2, #0 8015022: 4b6f ldr r3, [pc, #444] @ (80151e0 <_dtoa_r+0x8a8>) 8015024: f7f3 fac4 bl 80085b0 <__aeabi_dmul> 8015028: 2200 movs r2, #0 801502a: 2300 movs r3, #0 801502c: 4604 mov r4, r0 801502e: 460d mov r5, r1 8015030: f7f3 fd26 bl 8008a80 <__aeabi_dcmpeq> 8015034: 2800 cmp r0, #0 8015036: d09f beq.n 8014f78 <_dtoa_r+0x640> 8015038: e7d1 b.n 8014fde <_dtoa_r+0x6a6> 801503a: 9a0b ldr r2, [sp, #44] @ 0x2c 801503c: 2a00 cmp r2, #0 801503e: f000 80ea beq.w 8015216 <_dtoa_r+0x8de> 8015042: 9a20 ldr r2, [sp, #128] @ 0x80 8015044: 2a01 cmp r2, #1 8015046: f300 80cd bgt.w 80151e4 <_dtoa_r+0x8ac> 801504a: 9a12 ldr r2, [sp, #72] @ 0x48 801504c: 2a00 cmp r2, #0 801504e: f000 80c1 beq.w 80151d4 <_dtoa_r+0x89c> 8015052: f203 4333 addw r3, r3, #1075 @ 0x433 8015056: 9c0a ldr r4, [sp, #40] @ 0x28 8015058: 9e04 ldr r6, [sp, #16] 801505a: 9a04 ldr r2, [sp, #16] 801505c: 2101 movs r1, #1 801505e: 441a add r2, r3 8015060: 9204 str r2, [sp, #16] 8015062: 9a09 ldr r2, [sp, #36] @ 0x24 8015064: 4648 mov r0, r9 8015066: 441a add r2, r3 8015068: 9209 str r2, [sp, #36] @ 0x24 801506a: f000 ff23 bl 8015eb4 <__i2b> 801506e: 4605 mov r5, r0 8015070: b166 cbz r6, 801508c <_dtoa_r+0x754> 8015072: 9b09 ldr r3, [sp, #36] @ 0x24 8015074: 2b00 cmp r3, #0 8015076: dd09 ble.n 801508c <_dtoa_r+0x754> 8015078: 42b3 cmp r3, r6 801507a: bfa8 it ge 801507c: 4633 movge r3, r6 801507e: 9a04 ldr r2, [sp, #16] 8015080: 1af6 subs r6, r6, r3 8015082: 1ad2 subs r2, r2, r3 8015084: 9204 str r2, [sp, #16] 8015086: 9a09 ldr r2, [sp, #36] @ 0x24 8015088: 1ad3 subs r3, r2, r3 801508a: 9309 str r3, [sp, #36] @ 0x24 801508c: 9b0a ldr r3, [sp, #40] @ 0x28 801508e: b30b cbz r3, 80150d4 <_dtoa_r+0x79c> 8015090: 9b0b ldr r3, [sp, #44] @ 0x2c 8015092: 2b00 cmp r3, #0 8015094: f000 80c6 beq.w 8015224 <_dtoa_r+0x8ec> 8015098: 2c00 cmp r4, #0 801509a: f000 80c0 beq.w 801521e <_dtoa_r+0x8e6> 801509e: 4629 mov r1, r5 80150a0: 4622 mov r2, r4 80150a2: 4648 mov r0, r9 80150a4: f000 ffbe bl 8016024 <__pow5mult> 80150a8: 9a03 ldr r2, [sp, #12] 80150aa: 4601 mov r1, r0 80150ac: 4605 mov r5, r0 80150ae: 4648 mov r0, r9 80150b0: f000 ff16 bl 8015ee0 <__multiply> 80150b4: 9903 ldr r1, [sp, #12] 80150b6: 4680 mov r8, r0 80150b8: 4648 mov r0, r9 80150ba: f000 fe47 bl 8015d4c <_Bfree> 80150be: 9b0a ldr r3, [sp, #40] @ 0x28 80150c0: 1b1b subs r3, r3, r4 80150c2: 930a str r3, [sp, #40] @ 0x28 80150c4: f000 80b1 beq.w 801522a <_dtoa_r+0x8f2> 80150c8: 4641 mov r1, r8 80150ca: 9a0a ldr r2, [sp, #40] @ 0x28 80150cc: 4648 mov r0, r9 80150ce: f000 ffa9 bl 8016024 <__pow5mult> 80150d2: 9003 str r0, [sp, #12] 80150d4: 2101 movs r1, #1 80150d6: 4648 mov r0, r9 80150d8: f000 feec bl 8015eb4 <__i2b> 80150dc: 9b0e ldr r3, [sp, #56] @ 0x38 80150de: 4604 mov r4, r0 80150e0: 2b00 cmp r3, #0 80150e2: f000 81d8 beq.w 8015496 <_dtoa_r+0xb5e> 80150e6: 461a mov r2, r3 80150e8: 4601 mov r1, r0 80150ea: 4648 mov r0, r9 80150ec: f000 ff9a bl 8016024 <__pow5mult> 80150f0: 9b20 ldr r3, [sp, #128] @ 0x80 80150f2: 4604 mov r4, r0 80150f4: 2b01 cmp r3, #1 80150f6: f300 809f bgt.w 8015238 <_dtoa_r+0x900> 80150fa: 9b06 ldr r3, [sp, #24] 80150fc: 2b00 cmp r3, #0 80150fe: f040 8097 bne.w 8015230 <_dtoa_r+0x8f8> 8015102: 9b07 ldr r3, [sp, #28] 8015104: f3c3 0313 ubfx r3, r3, #0, #20 8015108: 2b00 cmp r3, #0 801510a: f040 8093 bne.w 8015234 <_dtoa_r+0x8fc> 801510e: 9b07 ldr r3, [sp, #28] 8015110: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8015114: 0d1b lsrs r3, r3, #20 8015116: 051b lsls r3, r3, #20 8015118: b133 cbz r3, 8015128 <_dtoa_r+0x7f0> 801511a: 9b04 ldr r3, [sp, #16] 801511c: 3301 adds r3, #1 801511e: 9304 str r3, [sp, #16] 8015120: 9b09 ldr r3, [sp, #36] @ 0x24 8015122: 3301 adds r3, #1 8015124: 9309 str r3, [sp, #36] @ 0x24 8015126: 2301 movs r3, #1 8015128: 930a str r3, [sp, #40] @ 0x28 801512a: 9b0e ldr r3, [sp, #56] @ 0x38 801512c: 2b00 cmp r3, #0 801512e: f000 81b8 beq.w 80154a2 <_dtoa_r+0xb6a> 8015132: 6923 ldr r3, [r4, #16] 8015134: eb04 0383 add.w r3, r4, r3, lsl #2 8015138: 6918 ldr r0, [r3, #16] 801513a: f000 fe6f bl 8015e1c <__hi0bits> 801513e: f1c0 0020 rsb r0, r0, #32 8015142: 9b09 ldr r3, [sp, #36] @ 0x24 8015144: 4418 add r0, r3 8015146: f010 001f ands.w r0, r0, #31 801514a: f000 8082 beq.w 8015252 <_dtoa_r+0x91a> 801514e: f1c0 0320 rsb r3, r0, #32 8015152: 2b04 cmp r3, #4 8015154: dd73 ble.n 801523e <_dtoa_r+0x906> 8015156: 9b04 ldr r3, [sp, #16] 8015158: f1c0 001c rsb r0, r0, #28 801515c: 4403 add r3, r0 801515e: 9304 str r3, [sp, #16] 8015160: 9b09 ldr r3, [sp, #36] @ 0x24 8015162: 4406 add r6, r0 8015164: 4403 add r3, r0 8015166: 9309 str r3, [sp, #36] @ 0x24 8015168: 9b04 ldr r3, [sp, #16] 801516a: 2b00 cmp r3, #0 801516c: dd05 ble.n 801517a <_dtoa_r+0x842> 801516e: 461a mov r2, r3 8015170: 4648 mov r0, r9 8015172: 9903 ldr r1, [sp, #12] 8015174: f000 ffb0 bl 80160d8 <__lshift> 8015178: 9003 str r0, [sp, #12] 801517a: 9b09 ldr r3, [sp, #36] @ 0x24 801517c: 2b00 cmp r3, #0 801517e: dd05 ble.n 801518c <_dtoa_r+0x854> 8015180: 4621 mov r1, r4 8015182: 461a mov r2, r3 8015184: 4648 mov r0, r9 8015186: f000 ffa7 bl 80160d8 <__lshift> 801518a: 4604 mov r4, r0 801518c: 9b0f ldr r3, [sp, #60] @ 0x3c 801518e: 2b00 cmp r3, #0 8015190: d061 beq.n 8015256 <_dtoa_r+0x91e> 8015192: 4621 mov r1, r4 8015194: 9803 ldr r0, [sp, #12] 8015196: f001 f80b bl 80161b0 <__mcmp> 801519a: 2800 cmp r0, #0 801519c: da5b bge.n 8015256 <_dtoa_r+0x91e> 801519e: 2300 movs r3, #0 80151a0: 220a movs r2, #10 80151a2: 4648 mov r0, r9 80151a4: 9903 ldr r1, [sp, #12] 80151a6: f000 fdf3 bl 8015d90 <__multadd> 80151aa: 9b0b ldr r3, [sp, #44] @ 0x2c 80151ac: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff 80151b0: 9003 str r0, [sp, #12] 80151b2: 2b00 cmp r3, #0 80151b4: f000 8177 beq.w 80154a6 <_dtoa_r+0xb6e> 80151b8: 4629 mov r1, r5 80151ba: 2300 movs r3, #0 80151bc: 220a movs r2, #10 80151be: 4648 mov r0, r9 80151c0: f000 fde6 bl 8015d90 <__multadd> 80151c4: f1bb 0f00 cmp.w fp, #0 80151c8: 4605 mov r5, r0 80151ca: dc6f bgt.n 80152ac <_dtoa_r+0x974> 80151cc: 9b20 ldr r3, [sp, #128] @ 0x80 80151ce: 2b02 cmp r3, #2 80151d0: dc49 bgt.n 8015266 <_dtoa_r+0x92e> 80151d2: e06b b.n 80152ac <_dtoa_r+0x974> 80151d4: 9b14 ldr r3, [sp, #80] @ 0x50 80151d6: f1c3 0336 rsb r3, r3, #54 @ 0x36 80151da: e73c b.n 8015056 <_dtoa_r+0x71e> 80151dc: 3fe00000 .word 0x3fe00000 80151e0: 40240000 .word 0x40240000 80151e4: 9b08 ldr r3, [sp, #32] 80151e6: 1e5c subs r4, r3, #1 80151e8: 9b0a ldr r3, [sp, #40] @ 0x28 80151ea: 42a3 cmp r3, r4 80151ec: db09 blt.n 8015202 <_dtoa_r+0x8ca> 80151ee: 1b1c subs r4, r3, r4 80151f0: 9b08 ldr r3, [sp, #32] 80151f2: 2b00 cmp r3, #0 80151f4: f6bf af30 bge.w 8015058 <_dtoa_r+0x720> 80151f8: 9b04 ldr r3, [sp, #16] 80151fa: 9a08 ldr r2, [sp, #32] 80151fc: 1a9e subs r6, r3, r2 80151fe: 2300 movs r3, #0 8015200: e72b b.n 801505a <_dtoa_r+0x722> 8015202: 9b0a ldr r3, [sp, #40] @ 0x28 8015204: 9a0e ldr r2, [sp, #56] @ 0x38 8015206: 1ae3 subs r3, r4, r3 8015208: 441a add r2, r3 801520a: 940a str r4, [sp, #40] @ 0x28 801520c: 9e04 ldr r6, [sp, #16] 801520e: 2400 movs r4, #0 8015210: 9b08 ldr r3, [sp, #32] 8015212: 920e str r2, [sp, #56] @ 0x38 8015214: e721 b.n 801505a <_dtoa_r+0x722> 8015216: 9c0a ldr r4, [sp, #40] @ 0x28 8015218: 9e04 ldr r6, [sp, #16] 801521a: 9d0b ldr r5, [sp, #44] @ 0x2c 801521c: e728 b.n 8015070 <_dtoa_r+0x738> 801521e: f8dd 800c ldr.w r8, [sp, #12] 8015222: e751 b.n 80150c8 <_dtoa_r+0x790> 8015224: 9a0a ldr r2, [sp, #40] @ 0x28 8015226: 9903 ldr r1, [sp, #12] 8015228: e750 b.n 80150cc <_dtoa_r+0x794> 801522a: f8cd 800c str.w r8, [sp, #12] 801522e: e751 b.n 80150d4 <_dtoa_r+0x79c> 8015230: 2300 movs r3, #0 8015232: e779 b.n 8015128 <_dtoa_r+0x7f0> 8015234: 9b06 ldr r3, [sp, #24] 8015236: e777 b.n 8015128 <_dtoa_r+0x7f0> 8015238: 2300 movs r3, #0 801523a: 930a str r3, [sp, #40] @ 0x28 801523c: e779 b.n 8015132 <_dtoa_r+0x7fa> 801523e: d093 beq.n 8015168 <_dtoa_r+0x830> 8015240: 9a04 ldr r2, [sp, #16] 8015242: 331c adds r3, #28 8015244: 441a add r2, r3 8015246: 9204 str r2, [sp, #16] 8015248: 9a09 ldr r2, [sp, #36] @ 0x24 801524a: 441e add r6, r3 801524c: 441a add r2, r3 801524e: 9209 str r2, [sp, #36] @ 0x24 8015250: e78a b.n 8015168 <_dtoa_r+0x830> 8015252: 4603 mov r3, r0 8015254: e7f4 b.n 8015240 <_dtoa_r+0x908> 8015256: 9b08 ldr r3, [sp, #32] 8015258: 46b8 mov r8, r7 801525a: 2b00 cmp r3, #0 801525c: dc20 bgt.n 80152a0 <_dtoa_r+0x968> 801525e: 469b mov fp, r3 8015260: 9b20 ldr r3, [sp, #128] @ 0x80 8015262: 2b02 cmp r3, #2 8015264: dd1e ble.n 80152a4 <_dtoa_r+0x96c> 8015266: f1bb 0f00 cmp.w fp, #0 801526a: f47f adb1 bne.w 8014dd0 <_dtoa_r+0x498> 801526e: 4621 mov r1, r4 8015270: 465b mov r3, fp 8015272: 2205 movs r2, #5 8015274: 4648 mov r0, r9 8015276: f000 fd8b bl 8015d90 <__multadd> 801527a: 4601 mov r1, r0 801527c: 4604 mov r4, r0 801527e: 9803 ldr r0, [sp, #12] 8015280: f000 ff96 bl 80161b0 <__mcmp> 8015284: 2800 cmp r0, #0 8015286: f77f ada3 ble.w 8014dd0 <_dtoa_r+0x498> 801528a: 4656 mov r6, sl 801528c: 2331 movs r3, #49 @ 0x31 801528e: f108 0801 add.w r8, r8, #1 8015292: f806 3b01 strb.w r3, [r6], #1 8015296: e59f b.n 8014dd8 <_dtoa_r+0x4a0> 8015298: 46b8 mov r8, r7 801529a: 9c08 ldr r4, [sp, #32] 801529c: 4625 mov r5, r4 801529e: e7f4 b.n 801528a <_dtoa_r+0x952> 80152a0: f8dd b020 ldr.w fp, [sp, #32] 80152a4: 9b0b ldr r3, [sp, #44] @ 0x2c 80152a6: 2b00 cmp r3, #0 80152a8: f000 8101 beq.w 80154ae <_dtoa_r+0xb76> 80152ac: 2e00 cmp r6, #0 80152ae: dd05 ble.n 80152bc <_dtoa_r+0x984> 80152b0: 4629 mov r1, r5 80152b2: 4632 mov r2, r6 80152b4: 4648 mov r0, r9 80152b6: f000 ff0f bl 80160d8 <__lshift> 80152ba: 4605 mov r5, r0 80152bc: 9b0a ldr r3, [sp, #40] @ 0x28 80152be: 2b00 cmp r3, #0 80152c0: d05c beq.n 801537c <_dtoa_r+0xa44> 80152c2: 4648 mov r0, r9 80152c4: 6869 ldr r1, [r5, #4] 80152c6: f000 fd01 bl 8015ccc <_Balloc> 80152ca: 4606 mov r6, r0 80152cc: b928 cbnz r0, 80152da <_dtoa_r+0x9a2> 80152ce: 4602 mov r2, r0 80152d0: f240 21ef movw r1, #751 @ 0x2ef 80152d4: 4b80 ldr r3, [pc, #512] @ (80154d8 <_dtoa_r+0xba0>) 80152d6: f7ff bb43 b.w 8014960 <_dtoa_r+0x28> 80152da: 692a ldr r2, [r5, #16] 80152dc: f105 010c add.w r1, r5, #12 80152e0: 3202 adds r2, #2 80152e2: 0092 lsls r2, r2, #2 80152e4: 300c adds r0, #12 80152e6: f7ff fa71 bl 80147cc 80152ea: 2201 movs r2, #1 80152ec: 4631 mov r1, r6 80152ee: 4648 mov r0, r9 80152f0: f000 fef2 bl 80160d8 <__lshift> 80152f4: 462f mov r7, r5 80152f6: 4605 mov r5, r0 80152f8: f10a 0301 add.w r3, sl, #1 80152fc: 9304 str r3, [sp, #16] 80152fe: eb0a 030b add.w r3, sl, fp 8015302: 930a str r3, [sp, #40] @ 0x28 8015304: 9b06 ldr r3, [sp, #24] 8015306: f003 0301 and.w r3, r3, #1 801530a: 9309 str r3, [sp, #36] @ 0x24 801530c: 9b04 ldr r3, [sp, #16] 801530e: 4621 mov r1, r4 8015310: 9803 ldr r0, [sp, #12] 8015312: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff 8015316: f7ff fa85 bl 8014824 801531a: 4603 mov r3, r0 801531c: 4639 mov r1, r7 801531e: 3330 adds r3, #48 @ 0x30 8015320: 9006 str r0, [sp, #24] 8015322: 9803 ldr r0, [sp, #12] 8015324: 930b str r3, [sp, #44] @ 0x2c 8015326: f000 ff43 bl 80161b0 <__mcmp> 801532a: 462a mov r2, r5 801532c: 9008 str r0, [sp, #32] 801532e: 4621 mov r1, r4 8015330: 4648 mov r0, r9 8015332: f000 ff59 bl 80161e8 <__mdiff> 8015336: 68c2 ldr r2, [r0, #12] 8015338: 4606 mov r6, r0 801533a: 9b0b ldr r3, [sp, #44] @ 0x2c 801533c: bb02 cbnz r2, 8015380 <_dtoa_r+0xa48> 801533e: 4601 mov r1, r0 8015340: 9803 ldr r0, [sp, #12] 8015342: f000 ff35 bl 80161b0 <__mcmp> 8015346: 4602 mov r2, r0 8015348: 9b0b ldr r3, [sp, #44] @ 0x2c 801534a: 4631 mov r1, r6 801534c: 4648 mov r0, r9 801534e: e9cd 320b strd r3, r2, [sp, #44] @ 0x2c 8015352: f000 fcfb bl 8015d4c <_Bfree> 8015356: 9b20 ldr r3, [sp, #128] @ 0x80 8015358: 9a0c ldr r2, [sp, #48] @ 0x30 801535a: 9e04 ldr r6, [sp, #16] 801535c: ea42 0103 orr.w r1, r2, r3 8015360: 9b09 ldr r3, [sp, #36] @ 0x24 8015362: 4319 orrs r1, r3 8015364: 9b0b ldr r3, [sp, #44] @ 0x2c 8015366: d10d bne.n 8015384 <_dtoa_r+0xa4c> 8015368: 2b39 cmp r3, #57 @ 0x39 801536a: d027 beq.n 80153bc <_dtoa_r+0xa84> 801536c: 9a08 ldr r2, [sp, #32] 801536e: 2a00 cmp r2, #0 8015370: dd01 ble.n 8015376 <_dtoa_r+0xa3e> 8015372: 9b06 ldr r3, [sp, #24] 8015374: 3331 adds r3, #49 @ 0x31 8015376: f88b 3000 strb.w r3, [fp] 801537a: e52e b.n 8014dda <_dtoa_r+0x4a2> 801537c: 4628 mov r0, r5 801537e: e7b9 b.n 80152f4 <_dtoa_r+0x9bc> 8015380: 2201 movs r2, #1 8015382: e7e2 b.n 801534a <_dtoa_r+0xa12> 8015384: 9908 ldr r1, [sp, #32] 8015386: 2900 cmp r1, #0 8015388: db04 blt.n 8015394 <_dtoa_r+0xa5c> 801538a: 9820 ldr r0, [sp, #128] @ 0x80 801538c: 4301 orrs r1, r0 801538e: 9809 ldr r0, [sp, #36] @ 0x24 8015390: 4301 orrs r1, r0 8015392: d120 bne.n 80153d6 <_dtoa_r+0xa9e> 8015394: 2a00 cmp r2, #0 8015396: ddee ble.n 8015376 <_dtoa_r+0xa3e> 8015398: 2201 movs r2, #1 801539a: 9903 ldr r1, [sp, #12] 801539c: 4648 mov r0, r9 801539e: 9304 str r3, [sp, #16] 80153a0: f000 fe9a bl 80160d8 <__lshift> 80153a4: 4621 mov r1, r4 80153a6: 9003 str r0, [sp, #12] 80153a8: f000 ff02 bl 80161b0 <__mcmp> 80153ac: 2800 cmp r0, #0 80153ae: 9b04 ldr r3, [sp, #16] 80153b0: dc02 bgt.n 80153b8 <_dtoa_r+0xa80> 80153b2: d1e0 bne.n 8015376 <_dtoa_r+0xa3e> 80153b4: 07da lsls r2, r3, #31 80153b6: d5de bpl.n 8015376 <_dtoa_r+0xa3e> 80153b8: 2b39 cmp r3, #57 @ 0x39 80153ba: d1da bne.n 8015372 <_dtoa_r+0xa3a> 80153bc: 2339 movs r3, #57 @ 0x39 80153be: f88b 3000 strb.w r3, [fp] 80153c2: 4633 mov r3, r6 80153c4: 461e mov r6, r3 80153c6: f816 2c01 ldrb.w r2, [r6, #-1] 80153ca: 3b01 subs r3, #1 80153cc: 2a39 cmp r2, #57 @ 0x39 80153ce: d04e beq.n 801546e <_dtoa_r+0xb36> 80153d0: 3201 adds r2, #1 80153d2: 701a strb r2, [r3, #0] 80153d4: e501 b.n 8014dda <_dtoa_r+0x4a2> 80153d6: 2a00 cmp r2, #0 80153d8: dd03 ble.n 80153e2 <_dtoa_r+0xaaa> 80153da: 2b39 cmp r3, #57 @ 0x39 80153dc: d0ee beq.n 80153bc <_dtoa_r+0xa84> 80153de: 3301 adds r3, #1 80153e0: e7c9 b.n 8015376 <_dtoa_r+0xa3e> 80153e2: 9a04 ldr r2, [sp, #16] 80153e4: 990a ldr r1, [sp, #40] @ 0x28 80153e6: f802 3c01 strb.w r3, [r2, #-1] 80153ea: 428a cmp r2, r1 80153ec: d028 beq.n 8015440 <_dtoa_r+0xb08> 80153ee: 2300 movs r3, #0 80153f0: 220a movs r2, #10 80153f2: 9903 ldr r1, [sp, #12] 80153f4: 4648 mov r0, r9 80153f6: f000 fccb bl 8015d90 <__multadd> 80153fa: 42af cmp r7, r5 80153fc: 9003 str r0, [sp, #12] 80153fe: f04f 0300 mov.w r3, #0 8015402: f04f 020a mov.w r2, #10 8015406: 4639 mov r1, r7 8015408: 4648 mov r0, r9 801540a: d107 bne.n 801541c <_dtoa_r+0xae4> 801540c: f000 fcc0 bl 8015d90 <__multadd> 8015410: 4607 mov r7, r0 8015412: 4605 mov r5, r0 8015414: 9b04 ldr r3, [sp, #16] 8015416: 3301 adds r3, #1 8015418: 9304 str r3, [sp, #16] 801541a: e777 b.n 801530c <_dtoa_r+0x9d4> 801541c: f000 fcb8 bl 8015d90 <__multadd> 8015420: 4629 mov r1, r5 8015422: 4607 mov r7, r0 8015424: 2300 movs r3, #0 8015426: 220a movs r2, #10 8015428: 4648 mov r0, r9 801542a: f000 fcb1 bl 8015d90 <__multadd> 801542e: 4605 mov r5, r0 8015430: e7f0 b.n 8015414 <_dtoa_r+0xadc> 8015432: f1bb 0f00 cmp.w fp, #0 8015436: bfcc ite gt 8015438: 465e movgt r6, fp 801543a: 2601 movle r6, #1 801543c: 2700 movs r7, #0 801543e: 4456 add r6, sl 8015440: 2201 movs r2, #1 8015442: 9903 ldr r1, [sp, #12] 8015444: 4648 mov r0, r9 8015446: 9304 str r3, [sp, #16] 8015448: f000 fe46 bl 80160d8 <__lshift> 801544c: 4621 mov r1, r4 801544e: 9003 str r0, [sp, #12] 8015450: f000 feae bl 80161b0 <__mcmp> 8015454: 2800 cmp r0, #0 8015456: dcb4 bgt.n 80153c2 <_dtoa_r+0xa8a> 8015458: d102 bne.n 8015460 <_dtoa_r+0xb28> 801545a: 9b04 ldr r3, [sp, #16] 801545c: 07db lsls r3, r3, #31 801545e: d4b0 bmi.n 80153c2 <_dtoa_r+0xa8a> 8015460: 4633 mov r3, r6 8015462: 461e mov r6, r3 8015464: f813 2d01 ldrb.w r2, [r3, #-1]! 8015468: 2a30 cmp r2, #48 @ 0x30 801546a: d0fa beq.n 8015462 <_dtoa_r+0xb2a> 801546c: e4b5 b.n 8014dda <_dtoa_r+0x4a2> 801546e: 459a cmp sl, r3 8015470: d1a8 bne.n 80153c4 <_dtoa_r+0xa8c> 8015472: 2331 movs r3, #49 @ 0x31 8015474: f108 0801 add.w r8, r8, #1 8015478: f88a 3000 strb.w r3, [sl] 801547c: e4ad b.n 8014dda <_dtoa_r+0x4a2> 801547e: 9b24 ldr r3, [sp, #144] @ 0x90 8015480: f8df a058 ldr.w sl, [pc, #88] @ 80154dc <_dtoa_r+0xba4> 8015484: b11b cbz r3, 801548e <_dtoa_r+0xb56> 8015486: f10a 0308 add.w r3, sl, #8 801548a: 9a24 ldr r2, [sp, #144] @ 0x90 801548c: 6013 str r3, [r2, #0] 801548e: 4650 mov r0, sl 8015490: b017 add sp, #92 @ 0x5c 8015492: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8015496: 9b20 ldr r3, [sp, #128] @ 0x80 8015498: 2b01 cmp r3, #1 801549a: f77f ae2e ble.w 80150fa <_dtoa_r+0x7c2> 801549e: 9b0e ldr r3, [sp, #56] @ 0x38 80154a0: 930a str r3, [sp, #40] @ 0x28 80154a2: 2001 movs r0, #1 80154a4: e64d b.n 8015142 <_dtoa_r+0x80a> 80154a6: f1bb 0f00 cmp.w fp, #0 80154aa: f77f aed9 ble.w 8015260 <_dtoa_r+0x928> 80154ae: 4656 mov r6, sl 80154b0: 4621 mov r1, r4 80154b2: 9803 ldr r0, [sp, #12] 80154b4: f7ff f9b6 bl 8014824 80154b8: f100 0330 add.w r3, r0, #48 @ 0x30 80154bc: f806 3b01 strb.w r3, [r6], #1 80154c0: eba6 020a sub.w r2, r6, sl 80154c4: 4593 cmp fp, r2 80154c6: ddb4 ble.n 8015432 <_dtoa_r+0xafa> 80154c8: 2300 movs r3, #0 80154ca: 220a movs r2, #10 80154cc: 4648 mov r0, r9 80154ce: 9903 ldr r1, [sp, #12] 80154d0: f000 fc5e bl 8015d90 <__multadd> 80154d4: 9003 str r0, [sp, #12] 80154d6: e7eb b.n 80154b0 <_dtoa_r+0xb78> 80154d8: 08017368 .word 0x08017368 80154dc: 080172ec .word 0x080172ec 080154e0 <__ssputs_r>: 80154e0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80154e4: 461f mov r7, r3 80154e6: 688e ldr r6, [r1, #8] 80154e8: 4682 mov sl, r0 80154ea: 42be cmp r6, r7 80154ec: 460c mov r4, r1 80154ee: 4690 mov r8, r2 80154f0: 680b ldr r3, [r1, #0] 80154f2: d82d bhi.n 8015550 <__ssputs_r+0x70> 80154f4: f9b1 200c ldrsh.w r2, [r1, #12] 80154f8: f412 6f90 tst.w r2, #1152 @ 0x480 80154fc: d026 beq.n 801554c <__ssputs_r+0x6c> 80154fe: 6965 ldr r5, [r4, #20] 8015500: 6909 ldr r1, [r1, #16] 8015502: eb05 0545 add.w r5, r5, r5, lsl #1 8015506: eba3 0901 sub.w r9, r3, r1 801550a: eb05 75d5 add.w r5, r5, r5, lsr #31 801550e: 1c7b adds r3, r7, #1 8015510: 444b add r3, r9 8015512: 106d asrs r5, r5, #1 8015514: 429d cmp r5, r3 8015516: bf38 it cc 8015518: 461d movcc r5, r3 801551a: 0553 lsls r3, r2, #21 801551c: d527 bpl.n 801556e <__ssputs_r+0x8e> 801551e: 4629 mov r1, r5 8015520: f000 faa0 bl 8015a64 <_malloc_r> 8015524: 4606 mov r6, r0 8015526: b360 cbz r0, 8015582 <__ssputs_r+0xa2> 8015528: 464a mov r2, r9 801552a: 6921 ldr r1, [r4, #16] 801552c: f7ff f94e bl 80147cc 8015530: 89a3 ldrh r3, [r4, #12] 8015532: f423 6390 bic.w r3, r3, #1152 @ 0x480 8015536: f043 0380 orr.w r3, r3, #128 @ 0x80 801553a: 81a3 strh r3, [r4, #12] 801553c: 6126 str r6, [r4, #16] 801553e: 444e add r6, r9 8015540: 6026 str r6, [r4, #0] 8015542: 463e mov r6, r7 8015544: 6165 str r5, [r4, #20] 8015546: eba5 0509 sub.w r5, r5, r9 801554a: 60a5 str r5, [r4, #8] 801554c: 42be cmp r6, r7 801554e: d900 bls.n 8015552 <__ssputs_r+0x72> 8015550: 463e mov r6, r7 8015552: 4632 mov r2, r6 8015554: 4641 mov r1, r8 8015556: 6820 ldr r0, [r4, #0] 8015558: f001 f8ab bl 80166b2 801555c: 2000 movs r0, #0 801555e: 68a3 ldr r3, [r4, #8] 8015560: 1b9b subs r3, r3, r6 8015562: 60a3 str r3, [r4, #8] 8015564: 6823 ldr r3, [r4, #0] 8015566: 4433 add r3, r6 8015568: 6023 str r3, [r4, #0] 801556a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801556e: 462a mov r2, r5 8015570: f000 ff7c bl 801646c <_realloc_r> 8015574: 4606 mov r6, r0 8015576: 2800 cmp r0, #0 8015578: d1e0 bne.n 801553c <__ssputs_r+0x5c> 801557a: 4650 mov r0, sl 801557c: 6921 ldr r1, [r4, #16] 801557e: f001 f947 bl 8016810 <_free_r> 8015582: 230c movs r3, #12 8015584: f8ca 3000 str.w r3, [sl] 8015588: 89a3 ldrh r3, [r4, #12] 801558a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801558e: f043 0340 orr.w r3, r3, #64 @ 0x40 8015592: 81a3 strh r3, [r4, #12] 8015594: e7e9 b.n 801556a <__ssputs_r+0x8a> ... 08015598 <_svfiprintf_r>: 8015598: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801559c: 4698 mov r8, r3 801559e: 898b ldrh r3, [r1, #12] 80155a0: 4607 mov r7, r0 80155a2: 061b lsls r3, r3, #24 80155a4: 460d mov r5, r1 80155a6: 4614 mov r4, r2 80155a8: b09d sub sp, #116 @ 0x74 80155aa: d510 bpl.n 80155ce <_svfiprintf_r+0x36> 80155ac: 690b ldr r3, [r1, #16] 80155ae: b973 cbnz r3, 80155ce <_svfiprintf_r+0x36> 80155b0: 2140 movs r1, #64 @ 0x40 80155b2: f000 fa57 bl 8015a64 <_malloc_r> 80155b6: 6028 str r0, [r5, #0] 80155b8: 6128 str r0, [r5, #16] 80155ba: b930 cbnz r0, 80155ca <_svfiprintf_r+0x32> 80155bc: 230c movs r3, #12 80155be: 603b str r3, [r7, #0] 80155c0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80155c4: b01d add sp, #116 @ 0x74 80155c6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80155ca: 2340 movs r3, #64 @ 0x40 80155cc: 616b str r3, [r5, #20] 80155ce: 2300 movs r3, #0 80155d0: 9309 str r3, [sp, #36] @ 0x24 80155d2: 2320 movs r3, #32 80155d4: f88d 3029 strb.w r3, [sp, #41] @ 0x29 80155d8: 2330 movs r3, #48 @ 0x30 80155da: f04f 0901 mov.w r9, #1 80155de: f8cd 800c str.w r8, [sp, #12] 80155e2: f8df 8198 ldr.w r8, [pc, #408] @ 801577c <_svfiprintf_r+0x1e4> 80155e6: f88d 302a strb.w r3, [sp, #42] @ 0x2a 80155ea: 4623 mov r3, r4 80155ec: 469a mov sl, r3 80155ee: f813 2b01 ldrb.w r2, [r3], #1 80155f2: b10a cbz r2, 80155f8 <_svfiprintf_r+0x60> 80155f4: 2a25 cmp r2, #37 @ 0x25 80155f6: d1f9 bne.n 80155ec <_svfiprintf_r+0x54> 80155f8: ebba 0b04 subs.w fp, sl, r4 80155fc: d00b beq.n 8015616 <_svfiprintf_r+0x7e> 80155fe: 465b mov r3, fp 8015600: 4622 mov r2, r4 8015602: 4629 mov r1, r5 8015604: 4638 mov r0, r7 8015606: f7ff ff6b bl 80154e0 <__ssputs_r> 801560a: 3001 adds r0, #1 801560c: f000 80a7 beq.w 801575e <_svfiprintf_r+0x1c6> 8015610: 9a09 ldr r2, [sp, #36] @ 0x24 8015612: 445a add r2, fp 8015614: 9209 str r2, [sp, #36] @ 0x24 8015616: f89a 3000 ldrb.w r3, [sl] 801561a: 2b00 cmp r3, #0 801561c: f000 809f beq.w 801575e <_svfiprintf_r+0x1c6> 8015620: 2300 movs r3, #0 8015622: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8015626: e9cd 2305 strd r2, r3, [sp, #20] 801562a: f10a 0a01 add.w sl, sl, #1 801562e: 9304 str r3, [sp, #16] 8015630: 9307 str r3, [sp, #28] 8015632: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8015636: 931a str r3, [sp, #104] @ 0x68 8015638: 4654 mov r4, sl 801563a: 2205 movs r2, #5 801563c: f814 1b01 ldrb.w r1, [r4], #1 8015640: 484e ldr r0, [pc, #312] @ (801577c <_svfiprintf_r+0x1e4>) 8015642: f7ff f8b5 bl 80147b0 8015646: 9a04 ldr r2, [sp, #16] 8015648: b9d8 cbnz r0, 8015682 <_svfiprintf_r+0xea> 801564a: 06d0 lsls r0, r2, #27 801564c: bf44 itt mi 801564e: 2320 movmi r3, #32 8015650: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8015654: 0711 lsls r1, r2, #28 8015656: bf44 itt mi 8015658: 232b movmi r3, #43 @ 0x2b 801565a: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 801565e: f89a 3000 ldrb.w r3, [sl] 8015662: 2b2a cmp r3, #42 @ 0x2a 8015664: d015 beq.n 8015692 <_svfiprintf_r+0xfa> 8015666: 4654 mov r4, sl 8015668: 2000 movs r0, #0 801566a: f04f 0c0a mov.w ip, #10 801566e: 9a07 ldr r2, [sp, #28] 8015670: 4621 mov r1, r4 8015672: f811 3b01 ldrb.w r3, [r1], #1 8015676: 3b30 subs r3, #48 @ 0x30 8015678: 2b09 cmp r3, #9 801567a: d94b bls.n 8015714 <_svfiprintf_r+0x17c> 801567c: b1b0 cbz r0, 80156ac <_svfiprintf_r+0x114> 801567e: 9207 str r2, [sp, #28] 8015680: e014 b.n 80156ac <_svfiprintf_r+0x114> 8015682: eba0 0308 sub.w r3, r0, r8 8015686: fa09 f303 lsl.w r3, r9, r3 801568a: 4313 orrs r3, r2 801568c: 46a2 mov sl, r4 801568e: 9304 str r3, [sp, #16] 8015690: e7d2 b.n 8015638 <_svfiprintf_r+0xa0> 8015692: 9b03 ldr r3, [sp, #12] 8015694: 1d19 adds r1, r3, #4 8015696: 681b ldr r3, [r3, #0] 8015698: 9103 str r1, [sp, #12] 801569a: 2b00 cmp r3, #0 801569c: bfbb ittet lt 801569e: 425b neglt r3, r3 80156a0: f042 0202 orrlt.w r2, r2, #2 80156a4: 9307 strge r3, [sp, #28] 80156a6: 9307 strlt r3, [sp, #28] 80156a8: bfb8 it lt 80156aa: 9204 strlt r2, [sp, #16] 80156ac: 7823 ldrb r3, [r4, #0] 80156ae: 2b2e cmp r3, #46 @ 0x2e 80156b0: d10a bne.n 80156c8 <_svfiprintf_r+0x130> 80156b2: 7863 ldrb r3, [r4, #1] 80156b4: 2b2a cmp r3, #42 @ 0x2a 80156b6: d132 bne.n 801571e <_svfiprintf_r+0x186> 80156b8: 9b03 ldr r3, [sp, #12] 80156ba: 3402 adds r4, #2 80156bc: 1d1a adds r2, r3, #4 80156be: 681b ldr r3, [r3, #0] 80156c0: 9203 str r2, [sp, #12] 80156c2: ea43 73e3 orr.w r3, r3, r3, asr #31 80156c6: 9305 str r3, [sp, #20] 80156c8: f8df a0b4 ldr.w sl, [pc, #180] @ 8015780 <_svfiprintf_r+0x1e8> 80156cc: 2203 movs r2, #3 80156ce: 4650 mov r0, sl 80156d0: 7821 ldrb r1, [r4, #0] 80156d2: f7ff f86d bl 80147b0 80156d6: b138 cbz r0, 80156e8 <_svfiprintf_r+0x150> 80156d8: 2240 movs r2, #64 @ 0x40 80156da: 9b04 ldr r3, [sp, #16] 80156dc: eba0 000a sub.w r0, r0, sl 80156e0: 4082 lsls r2, r0 80156e2: 4313 orrs r3, r2 80156e4: 3401 adds r4, #1 80156e6: 9304 str r3, [sp, #16] 80156e8: f814 1b01 ldrb.w r1, [r4], #1 80156ec: 2206 movs r2, #6 80156ee: 4825 ldr r0, [pc, #148] @ (8015784 <_svfiprintf_r+0x1ec>) 80156f0: f88d 1028 strb.w r1, [sp, #40] @ 0x28 80156f4: f7ff f85c bl 80147b0 80156f8: 2800 cmp r0, #0 80156fa: d036 beq.n 801576a <_svfiprintf_r+0x1d2> 80156fc: 4b22 ldr r3, [pc, #136] @ (8015788 <_svfiprintf_r+0x1f0>) 80156fe: bb1b cbnz r3, 8015748 <_svfiprintf_r+0x1b0> 8015700: 9b03 ldr r3, [sp, #12] 8015702: 3307 adds r3, #7 8015704: f023 0307 bic.w r3, r3, #7 8015708: 3308 adds r3, #8 801570a: 9303 str r3, [sp, #12] 801570c: 9b09 ldr r3, [sp, #36] @ 0x24 801570e: 4433 add r3, r6 8015710: 9309 str r3, [sp, #36] @ 0x24 8015712: e76a b.n 80155ea <_svfiprintf_r+0x52> 8015714: 460c mov r4, r1 8015716: 2001 movs r0, #1 8015718: fb0c 3202 mla r2, ip, r2, r3 801571c: e7a8 b.n 8015670 <_svfiprintf_r+0xd8> 801571e: 2300 movs r3, #0 8015720: f04f 0c0a mov.w ip, #10 8015724: 4619 mov r1, r3 8015726: 3401 adds r4, #1 8015728: 9305 str r3, [sp, #20] 801572a: 4620 mov r0, r4 801572c: f810 2b01 ldrb.w r2, [r0], #1 8015730: 3a30 subs r2, #48 @ 0x30 8015732: 2a09 cmp r2, #9 8015734: d903 bls.n 801573e <_svfiprintf_r+0x1a6> 8015736: 2b00 cmp r3, #0 8015738: d0c6 beq.n 80156c8 <_svfiprintf_r+0x130> 801573a: 9105 str r1, [sp, #20] 801573c: e7c4 b.n 80156c8 <_svfiprintf_r+0x130> 801573e: 4604 mov r4, r0 8015740: 2301 movs r3, #1 8015742: fb0c 2101 mla r1, ip, r1, r2 8015746: e7f0 b.n 801572a <_svfiprintf_r+0x192> 8015748: ab03 add r3, sp, #12 801574a: 9300 str r3, [sp, #0] 801574c: 462a mov r2, r5 801574e: 4638 mov r0, r7 8015750: 4b0e ldr r3, [pc, #56] @ (801578c <_svfiprintf_r+0x1f4>) 8015752: a904 add r1, sp, #16 8015754: f7fe fb26 bl 8013da4 <_printf_float> 8015758: 1c42 adds r2, r0, #1 801575a: 4606 mov r6, r0 801575c: d1d6 bne.n 801570c <_svfiprintf_r+0x174> 801575e: 89ab ldrh r3, [r5, #12] 8015760: 065b lsls r3, r3, #25 8015762: f53f af2d bmi.w 80155c0 <_svfiprintf_r+0x28> 8015766: 9809 ldr r0, [sp, #36] @ 0x24 8015768: e72c b.n 80155c4 <_svfiprintf_r+0x2c> 801576a: ab03 add r3, sp, #12 801576c: 9300 str r3, [sp, #0] 801576e: 462a mov r2, r5 8015770: 4638 mov r0, r7 8015772: 4b06 ldr r3, [pc, #24] @ (801578c <_svfiprintf_r+0x1f4>) 8015774: a904 add r1, sp, #16 8015776: f7fe fdb3 bl 80142e0 <_printf_i> 801577a: e7ed b.n 8015758 <_svfiprintf_r+0x1c0> 801577c: 08017379 .word 0x08017379 8015780: 0801737f .word 0x0801737f 8015784: 08017383 .word 0x08017383 8015788: 08013da5 .word 0x08013da5 801578c: 080154e1 .word 0x080154e1 08015790 <__sfputc_r>: 8015790: 6893 ldr r3, [r2, #8] 8015792: b410 push {r4} 8015794: 3b01 subs r3, #1 8015796: 2b00 cmp r3, #0 8015798: 6093 str r3, [r2, #8] 801579a: da07 bge.n 80157ac <__sfputc_r+0x1c> 801579c: 6994 ldr r4, [r2, #24] 801579e: 42a3 cmp r3, r4 80157a0: db01 blt.n 80157a6 <__sfputc_r+0x16> 80157a2: 290a cmp r1, #10 80157a4: d102 bne.n 80157ac <__sfputc_r+0x1c> 80157a6: bc10 pop {r4} 80157a8: f000 be8e b.w 80164c8 <__swbuf_r> 80157ac: 6813 ldr r3, [r2, #0] 80157ae: 1c58 adds r0, r3, #1 80157b0: 6010 str r0, [r2, #0] 80157b2: 7019 strb r1, [r3, #0] 80157b4: 4608 mov r0, r1 80157b6: bc10 pop {r4} 80157b8: 4770 bx lr 080157ba <__sfputs_r>: 80157ba: b5f8 push {r3, r4, r5, r6, r7, lr} 80157bc: 4606 mov r6, r0 80157be: 460f mov r7, r1 80157c0: 4614 mov r4, r2 80157c2: 18d5 adds r5, r2, r3 80157c4: 42ac cmp r4, r5 80157c6: d101 bne.n 80157cc <__sfputs_r+0x12> 80157c8: 2000 movs r0, #0 80157ca: e007 b.n 80157dc <__sfputs_r+0x22> 80157cc: 463a mov r2, r7 80157ce: 4630 mov r0, r6 80157d0: f814 1b01 ldrb.w r1, [r4], #1 80157d4: f7ff ffdc bl 8015790 <__sfputc_r> 80157d8: 1c43 adds r3, r0, #1 80157da: d1f3 bne.n 80157c4 <__sfputs_r+0xa> 80157dc: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 080157e0 <_vfiprintf_r>: 80157e0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80157e4: 460d mov r5, r1 80157e6: 4614 mov r4, r2 80157e8: 4698 mov r8, r3 80157ea: 4606 mov r6, r0 80157ec: b09d sub sp, #116 @ 0x74 80157ee: b118 cbz r0, 80157f8 <_vfiprintf_r+0x18> 80157f0: 6a03 ldr r3, [r0, #32] 80157f2: b90b cbnz r3, 80157f8 <_vfiprintf_r+0x18> 80157f4: f7fe ff1e bl 8014634 <__sinit> 80157f8: 6e6b ldr r3, [r5, #100] @ 0x64 80157fa: 07d9 lsls r1, r3, #31 80157fc: d405 bmi.n 801580a <_vfiprintf_r+0x2a> 80157fe: 89ab ldrh r3, [r5, #12] 8015800: 059a lsls r2, r3, #22 8015802: d402 bmi.n 801580a <_vfiprintf_r+0x2a> 8015804: 6da8 ldr r0, [r5, #88] @ 0x58 8015806: f7fe ffcc bl 80147a2 <__retarget_lock_acquire_recursive> 801580a: 89ab ldrh r3, [r5, #12] 801580c: 071b lsls r3, r3, #28 801580e: d501 bpl.n 8015814 <_vfiprintf_r+0x34> 8015810: 692b ldr r3, [r5, #16] 8015812: b99b cbnz r3, 801583c <_vfiprintf_r+0x5c> 8015814: 4629 mov r1, r5 8015816: 4630 mov r0, r6 8015818: f000 fe94 bl 8016544 <__swsetup_r> 801581c: b170 cbz r0, 801583c <_vfiprintf_r+0x5c> 801581e: 6e6b ldr r3, [r5, #100] @ 0x64 8015820: 07dc lsls r4, r3, #31 8015822: d504 bpl.n 801582e <_vfiprintf_r+0x4e> 8015824: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015828: b01d add sp, #116 @ 0x74 801582a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801582e: 89ab ldrh r3, [r5, #12] 8015830: 0598 lsls r0, r3, #22 8015832: d4f7 bmi.n 8015824 <_vfiprintf_r+0x44> 8015834: 6da8 ldr r0, [r5, #88] @ 0x58 8015836: f7fe ffb5 bl 80147a4 <__retarget_lock_release_recursive> 801583a: e7f3 b.n 8015824 <_vfiprintf_r+0x44> 801583c: 2300 movs r3, #0 801583e: 9309 str r3, [sp, #36] @ 0x24 8015840: 2320 movs r3, #32 8015842: f88d 3029 strb.w r3, [sp, #41] @ 0x29 8015846: 2330 movs r3, #48 @ 0x30 8015848: f04f 0901 mov.w r9, #1 801584c: f8cd 800c str.w r8, [sp, #12] 8015850: f8df 81a8 ldr.w r8, [pc, #424] @ 80159fc <_vfiprintf_r+0x21c> 8015854: f88d 302a strb.w r3, [sp, #42] @ 0x2a 8015858: 4623 mov r3, r4 801585a: 469a mov sl, r3 801585c: f813 2b01 ldrb.w r2, [r3], #1 8015860: b10a cbz r2, 8015866 <_vfiprintf_r+0x86> 8015862: 2a25 cmp r2, #37 @ 0x25 8015864: d1f9 bne.n 801585a <_vfiprintf_r+0x7a> 8015866: ebba 0b04 subs.w fp, sl, r4 801586a: d00b beq.n 8015884 <_vfiprintf_r+0xa4> 801586c: 465b mov r3, fp 801586e: 4622 mov r2, r4 8015870: 4629 mov r1, r5 8015872: 4630 mov r0, r6 8015874: f7ff ffa1 bl 80157ba <__sfputs_r> 8015878: 3001 adds r0, #1 801587a: f000 80a7 beq.w 80159cc <_vfiprintf_r+0x1ec> 801587e: 9a09 ldr r2, [sp, #36] @ 0x24 8015880: 445a add r2, fp 8015882: 9209 str r2, [sp, #36] @ 0x24 8015884: f89a 3000 ldrb.w r3, [sl] 8015888: 2b00 cmp r3, #0 801588a: f000 809f beq.w 80159cc <_vfiprintf_r+0x1ec> 801588e: 2300 movs r3, #0 8015890: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8015894: e9cd 2305 strd r2, r3, [sp, #20] 8015898: f10a 0a01 add.w sl, sl, #1 801589c: 9304 str r3, [sp, #16] 801589e: 9307 str r3, [sp, #28] 80158a0: f88d 3053 strb.w r3, [sp, #83] @ 0x53 80158a4: 931a str r3, [sp, #104] @ 0x68 80158a6: 4654 mov r4, sl 80158a8: 2205 movs r2, #5 80158aa: f814 1b01 ldrb.w r1, [r4], #1 80158ae: 4853 ldr r0, [pc, #332] @ (80159fc <_vfiprintf_r+0x21c>) 80158b0: f7fe ff7e bl 80147b0 80158b4: 9a04 ldr r2, [sp, #16] 80158b6: b9d8 cbnz r0, 80158f0 <_vfiprintf_r+0x110> 80158b8: 06d1 lsls r1, r2, #27 80158ba: bf44 itt mi 80158bc: 2320 movmi r3, #32 80158be: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 80158c2: 0713 lsls r3, r2, #28 80158c4: bf44 itt mi 80158c6: 232b movmi r3, #43 @ 0x2b 80158c8: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 80158cc: f89a 3000 ldrb.w r3, [sl] 80158d0: 2b2a cmp r3, #42 @ 0x2a 80158d2: d015 beq.n 8015900 <_vfiprintf_r+0x120> 80158d4: 4654 mov r4, sl 80158d6: 2000 movs r0, #0 80158d8: f04f 0c0a mov.w ip, #10 80158dc: 9a07 ldr r2, [sp, #28] 80158de: 4621 mov r1, r4 80158e0: f811 3b01 ldrb.w r3, [r1], #1 80158e4: 3b30 subs r3, #48 @ 0x30 80158e6: 2b09 cmp r3, #9 80158e8: d94b bls.n 8015982 <_vfiprintf_r+0x1a2> 80158ea: b1b0 cbz r0, 801591a <_vfiprintf_r+0x13a> 80158ec: 9207 str r2, [sp, #28] 80158ee: e014 b.n 801591a <_vfiprintf_r+0x13a> 80158f0: eba0 0308 sub.w r3, r0, r8 80158f4: fa09 f303 lsl.w r3, r9, r3 80158f8: 4313 orrs r3, r2 80158fa: 46a2 mov sl, r4 80158fc: 9304 str r3, [sp, #16] 80158fe: e7d2 b.n 80158a6 <_vfiprintf_r+0xc6> 8015900: 9b03 ldr r3, [sp, #12] 8015902: 1d19 adds r1, r3, #4 8015904: 681b ldr r3, [r3, #0] 8015906: 9103 str r1, [sp, #12] 8015908: 2b00 cmp r3, #0 801590a: bfbb ittet lt 801590c: 425b neglt r3, r3 801590e: f042 0202 orrlt.w r2, r2, #2 8015912: 9307 strge r3, [sp, #28] 8015914: 9307 strlt r3, [sp, #28] 8015916: bfb8 it lt 8015918: 9204 strlt r2, [sp, #16] 801591a: 7823 ldrb r3, [r4, #0] 801591c: 2b2e cmp r3, #46 @ 0x2e 801591e: d10a bne.n 8015936 <_vfiprintf_r+0x156> 8015920: 7863 ldrb r3, [r4, #1] 8015922: 2b2a cmp r3, #42 @ 0x2a 8015924: d132 bne.n 801598c <_vfiprintf_r+0x1ac> 8015926: 9b03 ldr r3, [sp, #12] 8015928: 3402 adds r4, #2 801592a: 1d1a adds r2, r3, #4 801592c: 681b ldr r3, [r3, #0] 801592e: 9203 str r2, [sp, #12] 8015930: ea43 73e3 orr.w r3, r3, r3, asr #31 8015934: 9305 str r3, [sp, #20] 8015936: f8df a0c8 ldr.w sl, [pc, #200] @ 8015a00 <_vfiprintf_r+0x220> 801593a: 2203 movs r2, #3 801593c: 4650 mov r0, sl 801593e: 7821 ldrb r1, [r4, #0] 8015940: f7fe ff36 bl 80147b0 8015944: b138 cbz r0, 8015956 <_vfiprintf_r+0x176> 8015946: 2240 movs r2, #64 @ 0x40 8015948: 9b04 ldr r3, [sp, #16] 801594a: eba0 000a sub.w r0, r0, sl 801594e: 4082 lsls r2, r0 8015950: 4313 orrs r3, r2 8015952: 3401 adds r4, #1 8015954: 9304 str r3, [sp, #16] 8015956: f814 1b01 ldrb.w r1, [r4], #1 801595a: 2206 movs r2, #6 801595c: 4829 ldr r0, [pc, #164] @ (8015a04 <_vfiprintf_r+0x224>) 801595e: f88d 1028 strb.w r1, [sp, #40] @ 0x28 8015962: f7fe ff25 bl 80147b0 8015966: 2800 cmp r0, #0 8015968: d03f beq.n 80159ea <_vfiprintf_r+0x20a> 801596a: 4b27 ldr r3, [pc, #156] @ (8015a08 <_vfiprintf_r+0x228>) 801596c: bb1b cbnz r3, 80159b6 <_vfiprintf_r+0x1d6> 801596e: 9b03 ldr r3, [sp, #12] 8015970: 3307 adds r3, #7 8015972: f023 0307 bic.w r3, r3, #7 8015976: 3308 adds r3, #8 8015978: 9303 str r3, [sp, #12] 801597a: 9b09 ldr r3, [sp, #36] @ 0x24 801597c: 443b add r3, r7 801597e: 9309 str r3, [sp, #36] @ 0x24 8015980: e76a b.n 8015858 <_vfiprintf_r+0x78> 8015982: 460c mov r4, r1 8015984: 2001 movs r0, #1 8015986: fb0c 3202 mla r2, ip, r2, r3 801598a: e7a8 b.n 80158de <_vfiprintf_r+0xfe> 801598c: 2300 movs r3, #0 801598e: f04f 0c0a mov.w ip, #10 8015992: 4619 mov r1, r3 8015994: 3401 adds r4, #1 8015996: 9305 str r3, [sp, #20] 8015998: 4620 mov r0, r4 801599a: f810 2b01 ldrb.w r2, [r0], #1 801599e: 3a30 subs r2, #48 @ 0x30 80159a0: 2a09 cmp r2, #9 80159a2: d903 bls.n 80159ac <_vfiprintf_r+0x1cc> 80159a4: 2b00 cmp r3, #0 80159a6: d0c6 beq.n 8015936 <_vfiprintf_r+0x156> 80159a8: 9105 str r1, [sp, #20] 80159aa: e7c4 b.n 8015936 <_vfiprintf_r+0x156> 80159ac: 4604 mov r4, r0 80159ae: 2301 movs r3, #1 80159b0: fb0c 2101 mla r1, ip, r1, r2 80159b4: e7f0 b.n 8015998 <_vfiprintf_r+0x1b8> 80159b6: ab03 add r3, sp, #12 80159b8: 9300 str r3, [sp, #0] 80159ba: 462a mov r2, r5 80159bc: 4630 mov r0, r6 80159be: 4b13 ldr r3, [pc, #76] @ (8015a0c <_vfiprintf_r+0x22c>) 80159c0: a904 add r1, sp, #16 80159c2: f7fe f9ef bl 8013da4 <_printf_float> 80159c6: 4607 mov r7, r0 80159c8: 1c78 adds r0, r7, #1 80159ca: d1d6 bne.n 801597a <_vfiprintf_r+0x19a> 80159cc: 6e6b ldr r3, [r5, #100] @ 0x64 80159ce: 07d9 lsls r1, r3, #31 80159d0: d405 bmi.n 80159de <_vfiprintf_r+0x1fe> 80159d2: 89ab ldrh r3, [r5, #12] 80159d4: 059a lsls r2, r3, #22 80159d6: d402 bmi.n 80159de <_vfiprintf_r+0x1fe> 80159d8: 6da8 ldr r0, [r5, #88] @ 0x58 80159da: f7fe fee3 bl 80147a4 <__retarget_lock_release_recursive> 80159de: 89ab ldrh r3, [r5, #12] 80159e0: 065b lsls r3, r3, #25 80159e2: f53f af1f bmi.w 8015824 <_vfiprintf_r+0x44> 80159e6: 9809 ldr r0, [sp, #36] @ 0x24 80159e8: e71e b.n 8015828 <_vfiprintf_r+0x48> 80159ea: ab03 add r3, sp, #12 80159ec: 9300 str r3, [sp, #0] 80159ee: 462a mov r2, r5 80159f0: 4630 mov r0, r6 80159f2: 4b06 ldr r3, [pc, #24] @ (8015a0c <_vfiprintf_r+0x22c>) 80159f4: a904 add r1, sp, #16 80159f6: f7fe fc73 bl 80142e0 <_printf_i> 80159fa: e7e4 b.n 80159c6 <_vfiprintf_r+0x1e6> 80159fc: 08017379 .word 0x08017379 8015a00: 0801737f .word 0x0801737f 8015a04: 08017383 .word 0x08017383 8015a08: 08013da5 .word 0x08013da5 8015a0c: 080157bb .word 0x080157bb 08015a10 : 8015a10: 4b02 ldr r3, [pc, #8] @ (8015a1c ) 8015a12: 4601 mov r1, r0 8015a14: 6818 ldr r0, [r3, #0] 8015a16: f000 b825 b.w 8015a64 <_malloc_r> 8015a1a: bf00 nop 8015a1c: 2000009c .word 0x2000009c 08015a20 : 8015a20: b570 push {r4, r5, r6, lr} 8015a22: 4e0f ldr r6, [pc, #60] @ (8015a60 ) 8015a24: 460c mov r4, r1 8015a26: 6831 ldr r1, [r6, #0] 8015a28: 4605 mov r5, r0 8015a2a: b911 cbnz r1, 8015a32 8015a2c: f000 fe90 bl 8016750 <_sbrk_r> 8015a30: 6030 str r0, [r6, #0] 8015a32: 4621 mov r1, r4 8015a34: 4628 mov r0, r5 8015a36: f000 fe8b bl 8016750 <_sbrk_r> 8015a3a: 1c43 adds r3, r0, #1 8015a3c: d103 bne.n 8015a46 8015a3e: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff 8015a42: 4620 mov r0, r4 8015a44: bd70 pop {r4, r5, r6, pc} 8015a46: 1cc4 adds r4, r0, #3 8015a48: f024 0403 bic.w r4, r4, #3 8015a4c: 42a0 cmp r0, r4 8015a4e: d0f8 beq.n 8015a42 8015a50: 1a21 subs r1, r4, r0 8015a52: 4628 mov r0, r5 8015a54: f000 fe7c bl 8016750 <_sbrk_r> 8015a58: 3001 adds r0, #1 8015a5a: d1f2 bne.n 8015a42 8015a5c: e7ef b.n 8015a3e 8015a5e: bf00 nop 8015a60: 200013b4 .word 0x200013b4 08015a64 <_malloc_r>: 8015a64: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8015a68: 1ccd adds r5, r1, #3 8015a6a: f025 0503 bic.w r5, r5, #3 8015a6e: 3508 adds r5, #8 8015a70: 2d0c cmp r5, #12 8015a72: bf38 it cc 8015a74: 250c movcc r5, #12 8015a76: 2d00 cmp r5, #0 8015a78: 4606 mov r6, r0 8015a7a: db01 blt.n 8015a80 <_malloc_r+0x1c> 8015a7c: 42a9 cmp r1, r5 8015a7e: d904 bls.n 8015a8a <_malloc_r+0x26> 8015a80: 230c movs r3, #12 8015a82: 6033 str r3, [r6, #0] 8015a84: 2000 movs r0, #0 8015a86: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8015a8a: f8df 80d4 ldr.w r8, [pc, #212] @ 8015b60 <_malloc_r+0xfc> 8015a8e: f000 f911 bl 8015cb4 <__malloc_lock> 8015a92: f8d8 3000 ldr.w r3, [r8] 8015a96: 461c mov r4, r3 8015a98: bb44 cbnz r4, 8015aec <_malloc_r+0x88> 8015a9a: 4629 mov r1, r5 8015a9c: 4630 mov r0, r6 8015a9e: f7ff ffbf bl 8015a20 8015aa2: 1c43 adds r3, r0, #1 8015aa4: 4604 mov r4, r0 8015aa6: d158 bne.n 8015b5a <_malloc_r+0xf6> 8015aa8: f8d8 4000 ldr.w r4, [r8] 8015aac: 4627 mov r7, r4 8015aae: 2f00 cmp r7, #0 8015ab0: d143 bne.n 8015b3a <_malloc_r+0xd6> 8015ab2: 2c00 cmp r4, #0 8015ab4: d04b beq.n 8015b4e <_malloc_r+0xea> 8015ab6: 6823 ldr r3, [r4, #0] 8015ab8: 4639 mov r1, r7 8015aba: 4630 mov r0, r6 8015abc: eb04 0903 add.w r9, r4, r3 8015ac0: f000 fe46 bl 8016750 <_sbrk_r> 8015ac4: 4581 cmp r9, r0 8015ac6: d142 bne.n 8015b4e <_malloc_r+0xea> 8015ac8: 6821 ldr r1, [r4, #0] 8015aca: 4630 mov r0, r6 8015acc: 1a6d subs r5, r5, r1 8015ace: 4629 mov r1, r5 8015ad0: f7ff ffa6 bl 8015a20 8015ad4: 3001 adds r0, #1 8015ad6: d03a beq.n 8015b4e <_malloc_r+0xea> 8015ad8: 6823 ldr r3, [r4, #0] 8015ada: 442b add r3, r5 8015adc: 6023 str r3, [r4, #0] 8015ade: f8d8 3000 ldr.w r3, [r8] 8015ae2: 685a ldr r2, [r3, #4] 8015ae4: bb62 cbnz r2, 8015b40 <_malloc_r+0xdc> 8015ae6: f8c8 7000 str.w r7, [r8] 8015aea: e00f b.n 8015b0c <_malloc_r+0xa8> 8015aec: 6822 ldr r2, [r4, #0] 8015aee: 1b52 subs r2, r2, r5 8015af0: d420 bmi.n 8015b34 <_malloc_r+0xd0> 8015af2: 2a0b cmp r2, #11 8015af4: d917 bls.n 8015b26 <_malloc_r+0xc2> 8015af6: 1961 adds r1, r4, r5 8015af8: 42a3 cmp r3, r4 8015afa: 6025 str r5, [r4, #0] 8015afc: bf18 it ne 8015afe: 6059 strne r1, [r3, #4] 8015b00: 6863 ldr r3, [r4, #4] 8015b02: bf08 it eq 8015b04: f8c8 1000 streq.w r1, [r8] 8015b08: 5162 str r2, [r4, r5] 8015b0a: 604b str r3, [r1, #4] 8015b0c: 4630 mov r0, r6 8015b0e: f000 f8d7 bl 8015cc0 <__malloc_unlock> 8015b12: f104 000b add.w r0, r4, #11 8015b16: 1d23 adds r3, r4, #4 8015b18: f020 0007 bic.w r0, r0, #7 8015b1c: 1ac2 subs r2, r0, r3 8015b1e: bf1c itt ne 8015b20: 1a1b subne r3, r3, r0 8015b22: 50a3 strne r3, [r4, r2] 8015b24: e7af b.n 8015a86 <_malloc_r+0x22> 8015b26: 6862 ldr r2, [r4, #4] 8015b28: 42a3 cmp r3, r4 8015b2a: bf0c ite eq 8015b2c: f8c8 2000 streq.w r2, [r8] 8015b30: 605a strne r2, [r3, #4] 8015b32: e7eb b.n 8015b0c <_malloc_r+0xa8> 8015b34: 4623 mov r3, r4 8015b36: 6864 ldr r4, [r4, #4] 8015b38: e7ae b.n 8015a98 <_malloc_r+0x34> 8015b3a: 463c mov r4, r7 8015b3c: 687f ldr r7, [r7, #4] 8015b3e: e7b6 b.n 8015aae <_malloc_r+0x4a> 8015b40: 461a mov r2, r3 8015b42: 685b ldr r3, [r3, #4] 8015b44: 42a3 cmp r3, r4 8015b46: d1fb bne.n 8015b40 <_malloc_r+0xdc> 8015b48: 2300 movs r3, #0 8015b4a: 6053 str r3, [r2, #4] 8015b4c: e7de b.n 8015b0c <_malloc_r+0xa8> 8015b4e: 230c movs r3, #12 8015b50: 4630 mov r0, r6 8015b52: 6033 str r3, [r6, #0] 8015b54: f000 f8b4 bl 8015cc0 <__malloc_unlock> 8015b58: e794 b.n 8015a84 <_malloc_r+0x20> 8015b5a: 6005 str r5, [r0, #0] 8015b5c: e7d6 b.n 8015b0c <_malloc_r+0xa8> 8015b5e: bf00 nop 8015b60: 200013b8 .word 0x200013b8 08015b64 <__sflush_r>: 8015b64: f9b1 200c ldrsh.w r2, [r1, #12] 8015b68: b5f8 push {r3, r4, r5, r6, r7, lr} 8015b6a: 0716 lsls r6, r2, #28 8015b6c: 4605 mov r5, r0 8015b6e: 460c mov r4, r1 8015b70: d454 bmi.n 8015c1c <__sflush_r+0xb8> 8015b72: 684b ldr r3, [r1, #4] 8015b74: 2b00 cmp r3, #0 8015b76: dc02 bgt.n 8015b7e <__sflush_r+0x1a> 8015b78: 6c0b ldr r3, [r1, #64] @ 0x40 8015b7a: 2b00 cmp r3, #0 8015b7c: dd48 ble.n 8015c10 <__sflush_r+0xac> 8015b7e: 6ae6 ldr r6, [r4, #44] @ 0x2c 8015b80: 2e00 cmp r6, #0 8015b82: d045 beq.n 8015c10 <__sflush_r+0xac> 8015b84: 2300 movs r3, #0 8015b86: f412 5280 ands.w r2, r2, #4096 @ 0x1000 8015b8a: 682f ldr r7, [r5, #0] 8015b8c: 6a21 ldr r1, [r4, #32] 8015b8e: 602b str r3, [r5, #0] 8015b90: d030 beq.n 8015bf4 <__sflush_r+0x90> 8015b92: 6d62 ldr r2, [r4, #84] @ 0x54 8015b94: 89a3 ldrh r3, [r4, #12] 8015b96: 0759 lsls r1, r3, #29 8015b98: d505 bpl.n 8015ba6 <__sflush_r+0x42> 8015b9a: 6863 ldr r3, [r4, #4] 8015b9c: 1ad2 subs r2, r2, r3 8015b9e: 6b63 ldr r3, [r4, #52] @ 0x34 8015ba0: b10b cbz r3, 8015ba6 <__sflush_r+0x42> 8015ba2: 6c23 ldr r3, [r4, #64] @ 0x40 8015ba4: 1ad2 subs r2, r2, r3 8015ba6: 2300 movs r3, #0 8015ba8: 4628 mov r0, r5 8015baa: 6ae6 ldr r6, [r4, #44] @ 0x2c 8015bac: 6a21 ldr r1, [r4, #32] 8015bae: 47b0 blx r6 8015bb0: 1c43 adds r3, r0, #1 8015bb2: 89a3 ldrh r3, [r4, #12] 8015bb4: d106 bne.n 8015bc4 <__sflush_r+0x60> 8015bb6: 6829 ldr r1, [r5, #0] 8015bb8: 291d cmp r1, #29 8015bba: d82b bhi.n 8015c14 <__sflush_r+0xb0> 8015bbc: 4a28 ldr r2, [pc, #160] @ (8015c60 <__sflush_r+0xfc>) 8015bbe: 40ca lsrs r2, r1 8015bc0: 07d6 lsls r6, r2, #31 8015bc2: d527 bpl.n 8015c14 <__sflush_r+0xb0> 8015bc4: 2200 movs r2, #0 8015bc6: 6062 str r2, [r4, #4] 8015bc8: 6922 ldr r2, [r4, #16] 8015bca: 04d9 lsls r1, r3, #19 8015bcc: 6022 str r2, [r4, #0] 8015bce: d504 bpl.n 8015bda <__sflush_r+0x76> 8015bd0: 1c42 adds r2, r0, #1 8015bd2: d101 bne.n 8015bd8 <__sflush_r+0x74> 8015bd4: 682b ldr r3, [r5, #0] 8015bd6: b903 cbnz r3, 8015bda <__sflush_r+0x76> 8015bd8: 6560 str r0, [r4, #84] @ 0x54 8015bda: 6b61 ldr r1, [r4, #52] @ 0x34 8015bdc: 602f str r7, [r5, #0] 8015bde: b1b9 cbz r1, 8015c10 <__sflush_r+0xac> 8015be0: f104 0344 add.w r3, r4, #68 @ 0x44 8015be4: 4299 cmp r1, r3 8015be6: d002 beq.n 8015bee <__sflush_r+0x8a> 8015be8: 4628 mov r0, r5 8015bea: f000 fe11 bl 8016810 <_free_r> 8015bee: 2300 movs r3, #0 8015bf0: 6363 str r3, [r4, #52] @ 0x34 8015bf2: e00d b.n 8015c10 <__sflush_r+0xac> 8015bf4: 2301 movs r3, #1 8015bf6: 4628 mov r0, r5 8015bf8: 47b0 blx r6 8015bfa: 4602 mov r2, r0 8015bfc: 1c50 adds r0, r2, #1 8015bfe: d1c9 bne.n 8015b94 <__sflush_r+0x30> 8015c00: 682b ldr r3, [r5, #0] 8015c02: 2b00 cmp r3, #0 8015c04: d0c6 beq.n 8015b94 <__sflush_r+0x30> 8015c06: 2b1d cmp r3, #29 8015c08: d001 beq.n 8015c0e <__sflush_r+0xaa> 8015c0a: 2b16 cmp r3, #22 8015c0c: d11d bne.n 8015c4a <__sflush_r+0xe6> 8015c0e: 602f str r7, [r5, #0] 8015c10: 2000 movs r0, #0 8015c12: e021 b.n 8015c58 <__sflush_r+0xf4> 8015c14: f043 0340 orr.w r3, r3, #64 @ 0x40 8015c18: b21b sxth r3, r3 8015c1a: e01a b.n 8015c52 <__sflush_r+0xee> 8015c1c: 690f ldr r7, [r1, #16] 8015c1e: 2f00 cmp r7, #0 8015c20: d0f6 beq.n 8015c10 <__sflush_r+0xac> 8015c22: 0793 lsls r3, r2, #30 8015c24: bf18 it ne 8015c26: 2300 movne r3, #0 8015c28: 680e ldr r6, [r1, #0] 8015c2a: bf08 it eq 8015c2c: 694b ldreq r3, [r1, #20] 8015c2e: 1bf6 subs r6, r6, r7 8015c30: 600f str r7, [r1, #0] 8015c32: 608b str r3, [r1, #8] 8015c34: 2e00 cmp r6, #0 8015c36: ddeb ble.n 8015c10 <__sflush_r+0xac> 8015c38: 4633 mov r3, r6 8015c3a: 463a mov r2, r7 8015c3c: 4628 mov r0, r5 8015c3e: 6a21 ldr r1, [r4, #32] 8015c40: f8d4 c028 ldr.w ip, [r4, #40] @ 0x28 8015c44: 47e0 blx ip 8015c46: 2800 cmp r0, #0 8015c48: dc07 bgt.n 8015c5a <__sflush_r+0xf6> 8015c4a: f9b4 300c ldrsh.w r3, [r4, #12] 8015c4e: f043 0340 orr.w r3, r3, #64 @ 0x40 8015c52: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015c56: 81a3 strh r3, [r4, #12] 8015c58: bdf8 pop {r3, r4, r5, r6, r7, pc} 8015c5a: 4407 add r7, r0 8015c5c: 1a36 subs r6, r6, r0 8015c5e: e7e9 b.n 8015c34 <__sflush_r+0xd0> 8015c60: 20400001 .word 0x20400001 08015c64 <_fflush_r>: 8015c64: b538 push {r3, r4, r5, lr} 8015c66: 690b ldr r3, [r1, #16] 8015c68: 4605 mov r5, r0 8015c6a: 460c mov r4, r1 8015c6c: b913 cbnz r3, 8015c74 <_fflush_r+0x10> 8015c6e: 2500 movs r5, #0 8015c70: 4628 mov r0, r5 8015c72: bd38 pop {r3, r4, r5, pc} 8015c74: b118 cbz r0, 8015c7e <_fflush_r+0x1a> 8015c76: 6a03 ldr r3, [r0, #32] 8015c78: b90b cbnz r3, 8015c7e <_fflush_r+0x1a> 8015c7a: f7fe fcdb bl 8014634 <__sinit> 8015c7e: f9b4 300c ldrsh.w r3, [r4, #12] 8015c82: 2b00 cmp r3, #0 8015c84: d0f3 beq.n 8015c6e <_fflush_r+0xa> 8015c86: 6e62 ldr r2, [r4, #100] @ 0x64 8015c88: 07d0 lsls r0, r2, #31 8015c8a: d404 bmi.n 8015c96 <_fflush_r+0x32> 8015c8c: 0599 lsls r1, r3, #22 8015c8e: d402 bmi.n 8015c96 <_fflush_r+0x32> 8015c90: 6da0 ldr r0, [r4, #88] @ 0x58 8015c92: f7fe fd86 bl 80147a2 <__retarget_lock_acquire_recursive> 8015c96: 4628 mov r0, r5 8015c98: 4621 mov r1, r4 8015c9a: f7ff ff63 bl 8015b64 <__sflush_r> 8015c9e: 6e63 ldr r3, [r4, #100] @ 0x64 8015ca0: 4605 mov r5, r0 8015ca2: 07da lsls r2, r3, #31 8015ca4: d4e4 bmi.n 8015c70 <_fflush_r+0xc> 8015ca6: 89a3 ldrh r3, [r4, #12] 8015ca8: 059b lsls r3, r3, #22 8015caa: d4e1 bmi.n 8015c70 <_fflush_r+0xc> 8015cac: 6da0 ldr r0, [r4, #88] @ 0x58 8015cae: f7fe fd79 bl 80147a4 <__retarget_lock_release_recursive> 8015cb2: e7dd b.n 8015c70 <_fflush_r+0xc> 08015cb4 <__malloc_lock>: 8015cb4: 4801 ldr r0, [pc, #4] @ (8015cbc <__malloc_lock+0x8>) 8015cb6: f7fe bd74 b.w 80147a2 <__retarget_lock_acquire_recursive> 8015cba: bf00 nop 8015cbc: 200013b0 .word 0x200013b0 08015cc0 <__malloc_unlock>: 8015cc0: 4801 ldr r0, [pc, #4] @ (8015cc8 <__malloc_unlock+0x8>) 8015cc2: f7fe bd6f b.w 80147a4 <__retarget_lock_release_recursive> 8015cc6: bf00 nop 8015cc8: 200013b0 .word 0x200013b0 08015ccc <_Balloc>: 8015ccc: b570 push {r4, r5, r6, lr} 8015cce: 69c6 ldr r6, [r0, #28] 8015cd0: 4604 mov r4, r0 8015cd2: 460d mov r5, r1 8015cd4: b976 cbnz r6, 8015cf4 <_Balloc+0x28> 8015cd6: 2010 movs r0, #16 8015cd8: f7ff fe9a bl 8015a10 8015cdc: 4602 mov r2, r0 8015cde: 61e0 str r0, [r4, #28] 8015ce0: b920 cbnz r0, 8015cec <_Balloc+0x20> 8015ce2: 216b movs r1, #107 @ 0x6b 8015ce4: 4b17 ldr r3, [pc, #92] @ (8015d44 <_Balloc+0x78>) 8015ce6: 4818 ldr r0, [pc, #96] @ (8015d48 <_Balloc+0x7c>) 8015ce8: f7fe fd7e bl 80147e8 <__assert_func> 8015cec: e9c0 6601 strd r6, r6, [r0, #4] 8015cf0: 6006 str r6, [r0, #0] 8015cf2: 60c6 str r6, [r0, #12] 8015cf4: 69e6 ldr r6, [r4, #28] 8015cf6: 68f3 ldr r3, [r6, #12] 8015cf8: b183 cbz r3, 8015d1c <_Balloc+0x50> 8015cfa: 69e3 ldr r3, [r4, #28] 8015cfc: 68db ldr r3, [r3, #12] 8015cfe: f853 0025 ldr.w r0, [r3, r5, lsl #2] 8015d02: b9b8 cbnz r0, 8015d34 <_Balloc+0x68> 8015d04: 2101 movs r1, #1 8015d06: fa01 f605 lsl.w r6, r1, r5 8015d0a: 1d72 adds r2, r6, #5 8015d0c: 4620 mov r0, r4 8015d0e: 0092 lsls r2, r2, #2 8015d10: f000 fd69 bl 80167e6 <_calloc_r> 8015d14: b160 cbz r0, 8015d30 <_Balloc+0x64> 8015d16: e9c0 5601 strd r5, r6, [r0, #4] 8015d1a: e00e b.n 8015d3a <_Balloc+0x6e> 8015d1c: 2221 movs r2, #33 @ 0x21 8015d1e: 2104 movs r1, #4 8015d20: 4620 mov r0, r4 8015d22: f000 fd60 bl 80167e6 <_calloc_r> 8015d26: 69e3 ldr r3, [r4, #28] 8015d28: 60f0 str r0, [r6, #12] 8015d2a: 68db ldr r3, [r3, #12] 8015d2c: 2b00 cmp r3, #0 8015d2e: d1e4 bne.n 8015cfa <_Balloc+0x2e> 8015d30: 2000 movs r0, #0 8015d32: bd70 pop {r4, r5, r6, pc} 8015d34: 6802 ldr r2, [r0, #0] 8015d36: f843 2025 str.w r2, [r3, r5, lsl #2] 8015d3a: 2300 movs r3, #0 8015d3c: e9c0 3303 strd r3, r3, [r0, #12] 8015d40: e7f7 b.n 8015d32 <_Balloc+0x66> 8015d42: bf00 nop 8015d44: 080172f9 .word 0x080172f9 8015d48: 0801738a .word 0x0801738a 08015d4c <_Bfree>: 8015d4c: b570 push {r4, r5, r6, lr} 8015d4e: 69c6 ldr r6, [r0, #28] 8015d50: 4605 mov r5, r0 8015d52: 460c mov r4, r1 8015d54: b976 cbnz r6, 8015d74 <_Bfree+0x28> 8015d56: 2010 movs r0, #16 8015d58: f7ff fe5a bl 8015a10 8015d5c: 4602 mov r2, r0 8015d5e: 61e8 str r0, [r5, #28] 8015d60: b920 cbnz r0, 8015d6c <_Bfree+0x20> 8015d62: 218f movs r1, #143 @ 0x8f 8015d64: 4b08 ldr r3, [pc, #32] @ (8015d88 <_Bfree+0x3c>) 8015d66: 4809 ldr r0, [pc, #36] @ (8015d8c <_Bfree+0x40>) 8015d68: f7fe fd3e bl 80147e8 <__assert_func> 8015d6c: e9c0 6601 strd r6, r6, [r0, #4] 8015d70: 6006 str r6, [r0, #0] 8015d72: 60c6 str r6, [r0, #12] 8015d74: b13c cbz r4, 8015d86 <_Bfree+0x3a> 8015d76: 69eb ldr r3, [r5, #28] 8015d78: 6862 ldr r2, [r4, #4] 8015d7a: 68db ldr r3, [r3, #12] 8015d7c: f853 1022 ldr.w r1, [r3, r2, lsl #2] 8015d80: 6021 str r1, [r4, #0] 8015d82: f843 4022 str.w r4, [r3, r2, lsl #2] 8015d86: bd70 pop {r4, r5, r6, pc} 8015d88: 080172f9 .word 0x080172f9 8015d8c: 0801738a .word 0x0801738a 08015d90 <__multadd>: 8015d90: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8015d94: 4607 mov r7, r0 8015d96: 460c mov r4, r1 8015d98: 461e mov r6, r3 8015d9a: 2000 movs r0, #0 8015d9c: 690d ldr r5, [r1, #16] 8015d9e: f101 0c14 add.w ip, r1, #20 8015da2: f8dc 3000 ldr.w r3, [ip] 8015da6: 3001 adds r0, #1 8015da8: b299 uxth r1, r3 8015daa: fb02 6101 mla r1, r2, r1, r6 8015dae: 0c1e lsrs r6, r3, #16 8015db0: 0c0b lsrs r3, r1, #16 8015db2: fb02 3306 mla r3, r2, r6, r3 8015db6: b289 uxth r1, r1 8015db8: eb01 4103 add.w r1, r1, r3, lsl #16 8015dbc: 4285 cmp r5, r0 8015dbe: ea4f 4613 mov.w r6, r3, lsr #16 8015dc2: f84c 1b04 str.w r1, [ip], #4 8015dc6: dcec bgt.n 8015da2 <__multadd+0x12> 8015dc8: b30e cbz r6, 8015e0e <__multadd+0x7e> 8015dca: 68a3 ldr r3, [r4, #8] 8015dcc: 42ab cmp r3, r5 8015dce: dc19 bgt.n 8015e04 <__multadd+0x74> 8015dd0: 6861 ldr r1, [r4, #4] 8015dd2: 4638 mov r0, r7 8015dd4: 3101 adds r1, #1 8015dd6: f7ff ff79 bl 8015ccc <_Balloc> 8015dda: 4680 mov r8, r0 8015ddc: b928 cbnz r0, 8015dea <__multadd+0x5a> 8015dde: 4602 mov r2, r0 8015de0: 21ba movs r1, #186 @ 0xba 8015de2: 4b0c ldr r3, [pc, #48] @ (8015e14 <__multadd+0x84>) 8015de4: 480c ldr r0, [pc, #48] @ (8015e18 <__multadd+0x88>) 8015de6: f7fe fcff bl 80147e8 <__assert_func> 8015dea: 6922 ldr r2, [r4, #16] 8015dec: f104 010c add.w r1, r4, #12 8015df0: 3202 adds r2, #2 8015df2: 0092 lsls r2, r2, #2 8015df4: 300c adds r0, #12 8015df6: f7fe fce9 bl 80147cc 8015dfa: 4621 mov r1, r4 8015dfc: 4638 mov r0, r7 8015dfe: f7ff ffa5 bl 8015d4c <_Bfree> 8015e02: 4644 mov r4, r8 8015e04: eb04 0385 add.w r3, r4, r5, lsl #2 8015e08: 3501 adds r5, #1 8015e0a: 615e str r6, [r3, #20] 8015e0c: 6125 str r5, [r4, #16] 8015e0e: 4620 mov r0, r4 8015e10: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8015e14: 08017368 .word 0x08017368 8015e18: 0801738a .word 0x0801738a 08015e1c <__hi0bits>: 8015e1c: 4603 mov r3, r0 8015e1e: f5b0 3f80 cmp.w r0, #65536 @ 0x10000 8015e22: bf3a itte cc 8015e24: 0403 lslcc r3, r0, #16 8015e26: 2010 movcc r0, #16 8015e28: 2000 movcs r0, #0 8015e2a: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8015e2e: bf3c itt cc 8015e30: 021b lslcc r3, r3, #8 8015e32: 3008 addcc r0, #8 8015e34: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8015e38: bf3c itt cc 8015e3a: 011b lslcc r3, r3, #4 8015e3c: 3004 addcc r0, #4 8015e3e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8015e42: bf3c itt cc 8015e44: 009b lslcc r3, r3, #2 8015e46: 3002 addcc r0, #2 8015e48: 2b00 cmp r3, #0 8015e4a: db05 blt.n 8015e58 <__hi0bits+0x3c> 8015e4c: f013 4f80 tst.w r3, #1073741824 @ 0x40000000 8015e50: f100 0001 add.w r0, r0, #1 8015e54: bf08 it eq 8015e56: 2020 moveq r0, #32 8015e58: 4770 bx lr 08015e5a <__lo0bits>: 8015e5a: 6803 ldr r3, [r0, #0] 8015e5c: 4602 mov r2, r0 8015e5e: f013 0007 ands.w r0, r3, #7 8015e62: d00b beq.n 8015e7c <__lo0bits+0x22> 8015e64: 07d9 lsls r1, r3, #31 8015e66: d421 bmi.n 8015eac <__lo0bits+0x52> 8015e68: 0798 lsls r0, r3, #30 8015e6a: bf49 itett mi 8015e6c: 085b lsrmi r3, r3, #1 8015e6e: 089b lsrpl r3, r3, #2 8015e70: 2001 movmi r0, #1 8015e72: 6013 strmi r3, [r2, #0] 8015e74: bf5c itt pl 8015e76: 2002 movpl r0, #2 8015e78: 6013 strpl r3, [r2, #0] 8015e7a: 4770 bx lr 8015e7c: b299 uxth r1, r3 8015e7e: b909 cbnz r1, 8015e84 <__lo0bits+0x2a> 8015e80: 2010 movs r0, #16 8015e82: 0c1b lsrs r3, r3, #16 8015e84: b2d9 uxtb r1, r3 8015e86: b909 cbnz r1, 8015e8c <__lo0bits+0x32> 8015e88: 3008 adds r0, #8 8015e8a: 0a1b lsrs r3, r3, #8 8015e8c: 0719 lsls r1, r3, #28 8015e8e: bf04 itt eq 8015e90: 091b lsreq r3, r3, #4 8015e92: 3004 addeq r0, #4 8015e94: 0799 lsls r1, r3, #30 8015e96: bf04 itt eq 8015e98: 089b lsreq r3, r3, #2 8015e9a: 3002 addeq r0, #2 8015e9c: 07d9 lsls r1, r3, #31 8015e9e: d403 bmi.n 8015ea8 <__lo0bits+0x4e> 8015ea0: 085b lsrs r3, r3, #1 8015ea2: f100 0001 add.w r0, r0, #1 8015ea6: d003 beq.n 8015eb0 <__lo0bits+0x56> 8015ea8: 6013 str r3, [r2, #0] 8015eaa: 4770 bx lr 8015eac: 2000 movs r0, #0 8015eae: 4770 bx lr 8015eb0: 2020 movs r0, #32 8015eb2: 4770 bx lr 08015eb4 <__i2b>: 8015eb4: b510 push {r4, lr} 8015eb6: 460c mov r4, r1 8015eb8: 2101 movs r1, #1 8015eba: f7ff ff07 bl 8015ccc <_Balloc> 8015ebe: 4602 mov r2, r0 8015ec0: b928 cbnz r0, 8015ece <__i2b+0x1a> 8015ec2: f240 1145 movw r1, #325 @ 0x145 8015ec6: 4b04 ldr r3, [pc, #16] @ (8015ed8 <__i2b+0x24>) 8015ec8: 4804 ldr r0, [pc, #16] @ (8015edc <__i2b+0x28>) 8015eca: f7fe fc8d bl 80147e8 <__assert_func> 8015ece: 2301 movs r3, #1 8015ed0: 6144 str r4, [r0, #20] 8015ed2: 6103 str r3, [r0, #16] 8015ed4: bd10 pop {r4, pc} 8015ed6: bf00 nop 8015ed8: 08017368 .word 0x08017368 8015edc: 0801738a .word 0x0801738a 08015ee0 <__multiply>: 8015ee0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8015ee4: 4617 mov r7, r2 8015ee6: 690a ldr r2, [r1, #16] 8015ee8: 693b ldr r3, [r7, #16] 8015eea: 4689 mov r9, r1 8015eec: 429a cmp r2, r3 8015eee: bfa2 ittt ge 8015ef0: 463b movge r3, r7 8015ef2: 460f movge r7, r1 8015ef4: 4699 movge r9, r3 8015ef6: 693d ldr r5, [r7, #16] 8015ef8: f8d9 a010 ldr.w sl, [r9, #16] 8015efc: 68bb ldr r3, [r7, #8] 8015efe: 6879 ldr r1, [r7, #4] 8015f00: eb05 060a add.w r6, r5, sl 8015f04: 42b3 cmp r3, r6 8015f06: b085 sub sp, #20 8015f08: bfb8 it lt 8015f0a: 3101 addlt r1, #1 8015f0c: f7ff fede bl 8015ccc <_Balloc> 8015f10: b930 cbnz r0, 8015f20 <__multiply+0x40> 8015f12: 4602 mov r2, r0 8015f14: f44f 71b1 mov.w r1, #354 @ 0x162 8015f18: 4b40 ldr r3, [pc, #256] @ (801601c <__multiply+0x13c>) 8015f1a: 4841 ldr r0, [pc, #260] @ (8016020 <__multiply+0x140>) 8015f1c: f7fe fc64 bl 80147e8 <__assert_func> 8015f20: f100 0414 add.w r4, r0, #20 8015f24: 4623 mov r3, r4 8015f26: 2200 movs r2, #0 8015f28: eb04 0e86 add.w lr, r4, r6, lsl #2 8015f2c: 4573 cmp r3, lr 8015f2e: d320 bcc.n 8015f72 <__multiply+0x92> 8015f30: f107 0814 add.w r8, r7, #20 8015f34: f109 0114 add.w r1, r9, #20 8015f38: eb08 0585 add.w r5, r8, r5, lsl #2 8015f3c: eb01 038a add.w r3, r1, sl, lsl #2 8015f40: 9302 str r3, [sp, #8] 8015f42: 1beb subs r3, r5, r7 8015f44: 3b15 subs r3, #21 8015f46: f023 0303 bic.w r3, r3, #3 8015f4a: 3304 adds r3, #4 8015f4c: 3715 adds r7, #21 8015f4e: 42bd cmp r5, r7 8015f50: bf38 it cc 8015f52: 2304 movcc r3, #4 8015f54: 9301 str r3, [sp, #4] 8015f56: 9b02 ldr r3, [sp, #8] 8015f58: 9103 str r1, [sp, #12] 8015f5a: 428b cmp r3, r1 8015f5c: d80c bhi.n 8015f78 <__multiply+0x98> 8015f5e: 2e00 cmp r6, #0 8015f60: dd03 ble.n 8015f6a <__multiply+0x8a> 8015f62: f85e 3d04 ldr.w r3, [lr, #-4]! 8015f66: 2b00 cmp r3, #0 8015f68: d055 beq.n 8016016 <__multiply+0x136> 8015f6a: 6106 str r6, [r0, #16] 8015f6c: b005 add sp, #20 8015f6e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8015f72: f843 2b04 str.w r2, [r3], #4 8015f76: e7d9 b.n 8015f2c <__multiply+0x4c> 8015f78: f8b1 a000 ldrh.w sl, [r1] 8015f7c: f1ba 0f00 cmp.w sl, #0 8015f80: d01f beq.n 8015fc2 <__multiply+0xe2> 8015f82: 46c4 mov ip, r8 8015f84: 46a1 mov r9, r4 8015f86: 2700 movs r7, #0 8015f88: f85c 2b04 ldr.w r2, [ip], #4 8015f8c: f8d9 3000 ldr.w r3, [r9] 8015f90: fa1f fb82 uxth.w fp, r2 8015f94: b29b uxth r3, r3 8015f96: fb0a 330b mla r3, sl, fp, r3 8015f9a: 443b add r3, r7 8015f9c: f8d9 7000 ldr.w r7, [r9] 8015fa0: 0c12 lsrs r2, r2, #16 8015fa2: 0c3f lsrs r7, r7, #16 8015fa4: fb0a 7202 mla r2, sl, r2, r7 8015fa8: eb02 4213 add.w r2, r2, r3, lsr #16 8015fac: b29b uxth r3, r3 8015fae: ea43 4302 orr.w r3, r3, r2, lsl #16 8015fb2: 4565 cmp r5, ip 8015fb4: ea4f 4712 mov.w r7, r2, lsr #16 8015fb8: f849 3b04 str.w r3, [r9], #4 8015fbc: d8e4 bhi.n 8015f88 <__multiply+0xa8> 8015fbe: 9b01 ldr r3, [sp, #4] 8015fc0: 50e7 str r7, [r4, r3] 8015fc2: 9b03 ldr r3, [sp, #12] 8015fc4: 3104 adds r1, #4 8015fc6: f8b3 9002 ldrh.w r9, [r3, #2] 8015fca: f1b9 0f00 cmp.w r9, #0 8015fce: d020 beq.n 8016012 <__multiply+0x132> 8015fd0: 4647 mov r7, r8 8015fd2: 46a4 mov ip, r4 8015fd4: f04f 0a00 mov.w sl, #0 8015fd8: 6823 ldr r3, [r4, #0] 8015fda: f8b7 b000 ldrh.w fp, [r7] 8015fde: f8bc 2002 ldrh.w r2, [ip, #2] 8015fe2: b29b uxth r3, r3 8015fe4: fb09 220b mla r2, r9, fp, r2 8015fe8: 4452 add r2, sl 8015fea: ea43 4302 orr.w r3, r3, r2, lsl #16 8015fee: f84c 3b04 str.w r3, [ip], #4 8015ff2: f857 3b04 ldr.w r3, [r7], #4 8015ff6: ea4f 4a13 mov.w sl, r3, lsr #16 8015ffa: f8bc 3000 ldrh.w r3, [ip] 8015ffe: 42bd cmp r5, r7 8016000: fb09 330a mla r3, r9, sl, r3 8016004: eb03 4312 add.w r3, r3, r2, lsr #16 8016008: ea4f 4a13 mov.w sl, r3, lsr #16 801600c: d8e5 bhi.n 8015fda <__multiply+0xfa> 801600e: 9a01 ldr r2, [sp, #4] 8016010: 50a3 str r3, [r4, r2] 8016012: 3404 adds r4, #4 8016014: e79f b.n 8015f56 <__multiply+0x76> 8016016: 3e01 subs r6, #1 8016018: e7a1 b.n 8015f5e <__multiply+0x7e> 801601a: bf00 nop 801601c: 08017368 .word 0x08017368 8016020: 0801738a .word 0x0801738a 08016024 <__pow5mult>: 8016024: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8016028: 4615 mov r5, r2 801602a: f012 0203 ands.w r2, r2, #3 801602e: 4607 mov r7, r0 8016030: 460e mov r6, r1 8016032: d007 beq.n 8016044 <__pow5mult+0x20> 8016034: 4c25 ldr r4, [pc, #148] @ (80160cc <__pow5mult+0xa8>) 8016036: 3a01 subs r2, #1 8016038: 2300 movs r3, #0 801603a: f854 2022 ldr.w r2, [r4, r2, lsl #2] 801603e: f7ff fea7 bl 8015d90 <__multadd> 8016042: 4606 mov r6, r0 8016044: 10ad asrs r5, r5, #2 8016046: d03d beq.n 80160c4 <__pow5mult+0xa0> 8016048: 69fc ldr r4, [r7, #28] 801604a: b97c cbnz r4, 801606c <__pow5mult+0x48> 801604c: 2010 movs r0, #16 801604e: f7ff fcdf bl 8015a10 8016052: 4602 mov r2, r0 8016054: 61f8 str r0, [r7, #28] 8016056: b928 cbnz r0, 8016064 <__pow5mult+0x40> 8016058: f240 11b3 movw r1, #435 @ 0x1b3 801605c: 4b1c ldr r3, [pc, #112] @ (80160d0 <__pow5mult+0xac>) 801605e: 481d ldr r0, [pc, #116] @ (80160d4 <__pow5mult+0xb0>) 8016060: f7fe fbc2 bl 80147e8 <__assert_func> 8016064: e9c0 4401 strd r4, r4, [r0, #4] 8016068: 6004 str r4, [r0, #0] 801606a: 60c4 str r4, [r0, #12] 801606c: f8d7 801c ldr.w r8, [r7, #28] 8016070: f8d8 4008 ldr.w r4, [r8, #8] 8016074: b94c cbnz r4, 801608a <__pow5mult+0x66> 8016076: f240 2171 movw r1, #625 @ 0x271 801607a: 4638 mov r0, r7 801607c: f7ff ff1a bl 8015eb4 <__i2b> 8016080: 2300 movs r3, #0 8016082: 4604 mov r4, r0 8016084: f8c8 0008 str.w r0, [r8, #8] 8016088: 6003 str r3, [r0, #0] 801608a: f04f 0900 mov.w r9, #0 801608e: 07eb lsls r3, r5, #31 8016090: d50a bpl.n 80160a8 <__pow5mult+0x84> 8016092: 4631 mov r1, r6 8016094: 4622 mov r2, r4 8016096: 4638 mov r0, r7 8016098: f7ff ff22 bl 8015ee0 <__multiply> 801609c: 4680 mov r8, r0 801609e: 4631 mov r1, r6 80160a0: 4638 mov r0, r7 80160a2: f7ff fe53 bl 8015d4c <_Bfree> 80160a6: 4646 mov r6, r8 80160a8: 106d asrs r5, r5, #1 80160aa: d00b beq.n 80160c4 <__pow5mult+0xa0> 80160ac: 6820 ldr r0, [r4, #0] 80160ae: b938 cbnz r0, 80160c0 <__pow5mult+0x9c> 80160b0: 4622 mov r2, r4 80160b2: 4621 mov r1, r4 80160b4: 4638 mov r0, r7 80160b6: f7ff ff13 bl 8015ee0 <__multiply> 80160ba: 6020 str r0, [r4, #0] 80160bc: f8c0 9000 str.w r9, [r0] 80160c0: 4604 mov r4, r0 80160c2: e7e4 b.n 801608e <__pow5mult+0x6a> 80160c4: 4630 mov r0, r6 80160c6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 80160ca: bf00 nop 80160cc: 080173f0 .word 0x080173f0 80160d0: 080172f9 .word 0x080172f9 80160d4: 0801738a .word 0x0801738a 080160d8 <__lshift>: 80160d8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80160dc: 460c mov r4, r1 80160de: 4607 mov r7, r0 80160e0: 4691 mov r9, r2 80160e2: 6923 ldr r3, [r4, #16] 80160e4: 6849 ldr r1, [r1, #4] 80160e6: eb03 1862 add.w r8, r3, r2, asr #5 80160ea: 68a3 ldr r3, [r4, #8] 80160ec: ea4f 1a62 mov.w sl, r2, asr #5 80160f0: f108 0601 add.w r6, r8, #1 80160f4: 42b3 cmp r3, r6 80160f6: db0b blt.n 8016110 <__lshift+0x38> 80160f8: 4638 mov r0, r7 80160fa: f7ff fde7 bl 8015ccc <_Balloc> 80160fe: 4605 mov r5, r0 8016100: b948 cbnz r0, 8016116 <__lshift+0x3e> 8016102: 4602 mov r2, r0 8016104: f44f 71ef mov.w r1, #478 @ 0x1de 8016108: 4b27 ldr r3, [pc, #156] @ (80161a8 <__lshift+0xd0>) 801610a: 4828 ldr r0, [pc, #160] @ (80161ac <__lshift+0xd4>) 801610c: f7fe fb6c bl 80147e8 <__assert_func> 8016110: 3101 adds r1, #1 8016112: 005b lsls r3, r3, #1 8016114: e7ee b.n 80160f4 <__lshift+0x1c> 8016116: 2300 movs r3, #0 8016118: f100 0114 add.w r1, r0, #20 801611c: f100 0210 add.w r2, r0, #16 8016120: 4618 mov r0, r3 8016122: 4553 cmp r3, sl 8016124: db33 blt.n 801618e <__lshift+0xb6> 8016126: 6920 ldr r0, [r4, #16] 8016128: ea2a 7aea bic.w sl, sl, sl, asr #31 801612c: f104 0314 add.w r3, r4, #20 8016130: f019 091f ands.w r9, r9, #31 8016134: eb01 018a add.w r1, r1, sl, lsl #2 8016138: eb03 0c80 add.w ip, r3, r0, lsl #2 801613c: d02b beq.n 8016196 <__lshift+0xbe> 801613e: 468a mov sl, r1 8016140: 2200 movs r2, #0 8016142: f1c9 0e20 rsb lr, r9, #32 8016146: 6818 ldr r0, [r3, #0] 8016148: fa00 f009 lsl.w r0, r0, r9 801614c: 4310 orrs r0, r2 801614e: f84a 0b04 str.w r0, [sl], #4 8016152: f853 2b04 ldr.w r2, [r3], #4 8016156: 459c cmp ip, r3 8016158: fa22 f20e lsr.w r2, r2, lr 801615c: d8f3 bhi.n 8016146 <__lshift+0x6e> 801615e: ebac 0304 sub.w r3, ip, r4 8016162: 3b15 subs r3, #21 8016164: f023 0303 bic.w r3, r3, #3 8016168: 3304 adds r3, #4 801616a: f104 0015 add.w r0, r4, #21 801616e: 4560 cmp r0, ip 8016170: bf88 it hi 8016172: 2304 movhi r3, #4 8016174: 50ca str r2, [r1, r3] 8016176: b10a cbz r2, 801617c <__lshift+0xa4> 8016178: f108 0602 add.w r6, r8, #2 801617c: 3e01 subs r6, #1 801617e: 4638 mov r0, r7 8016180: 4621 mov r1, r4 8016182: 612e str r6, [r5, #16] 8016184: f7ff fde2 bl 8015d4c <_Bfree> 8016188: 4628 mov r0, r5 801618a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801618e: f842 0f04 str.w r0, [r2, #4]! 8016192: 3301 adds r3, #1 8016194: e7c5 b.n 8016122 <__lshift+0x4a> 8016196: 3904 subs r1, #4 8016198: f853 2b04 ldr.w r2, [r3], #4 801619c: 459c cmp ip, r3 801619e: f841 2f04 str.w r2, [r1, #4]! 80161a2: d8f9 bhi.n 8016198 <__lshift+0xc0> 80161a4: e7ea b.n 801617c <__lshift+0xa4> 80161a6: bf00 nop 80161a8: 08017368 .word 0x08017368 80161ac: 0801738a .word 0x0801738a 080161b0 <__mcmp>: 80161b0: 4603 mov r3, r0 80161b2: 690a ldr r2, [r1, #16] 80161b4: 6900 ldr r0, [r0, #16] 80161b6: b530 push {r4, r5, lr} 80161b8: 1a80 subs r0, r0, r2 80161ba: d10e bne.n 80161da <__mcmp+0x2a> 80161bc: 3314 adds r3, #20 80161be: 3114 adds r1, #20 80161c0: eb03 0482 add.w r4, r3, r2, lsl #2 80161c4: eb01 0182 add.w r1, r1, r2, lsl #2 80161c8: f854 5d04 ldr.w r5, [r4, #-4]! 80161cc: f851 2d04 ldr.w r2, [r1, #-4]! 80161d0: 4295 cmp r5, r2 80161d2: d003 beq.n 80161dc <__mcmp+0x2c> 80161d4: d205 bcs.n 80161e2 <__mcmp+0x32> 80161d6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80161da: bd30 pop {r4, r5, pc} 80161dc: 42a3 cmp r3, r4 80161de: d3f3 bcc.n 80161c8 <__mcmp+0x18> 80161e0: e7fb b.n 80161da <__mcmp+0x2a> 80161e2: 2001 movs r0, #1 80161e4: e7f9 b.n 80161da <__mcmp+0x2a> ... 080161e8 <__mdiff>: 80161e8: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 80161ec: 4689 mov r9, r1 80161ee: 4606 mov r6, r0 80161f0: 4611 mov r1, r2 80161f2: 4648 mov r0, r9 80161f4: 4614 mov r4, r2 80161f6: f7ff ffdb bl 80161b0 <__mcmp> 80161fa: 1e05 subs r5, r0, #0 80161fc: d112 bne.n 8016224 <__mdiff+0x3c> 80161fe: 4629 mov r1, r5 8016200: 4630 mov r0, r6 8016202: f7ff fd63 bl 8015ccc <_Balloc> 8016206: 4602 mov r2, r0 8016208: b928 cbnz r0, 8016216 <__mdiff+0x2e> 801620a: f240 2137 movw r1, #567 @ 0x237 801620e: 4b3e ldr r3, [pc, #248] @ (8016308 <__mdiff+0x120>) 8016210: 483e ldr r0, [pc, #248] @ (801630c <__mdiff+0x124>) 8016212: f7fe fae9 bl 80147e8 <__assert_func> 8016216: 2301 movs r3, #1 8016218: e9c0 3504 strd r3, r5, [r0, #16] 801621c: 4610 mov r0, r2 801621e: b003 add sp, #12 8016220: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8016224: bfbc itt lt 8016226: 464b movlt r3, r9 8016228: 46a1 movlt r9, r4 801622a: 4630 mov r0, r6 801622c: f8d9 1004 ldr.w r1, [r9, #4] 8016230: bfba itte lt 8016232: 461c movlt r4, r3 8016234: 2501 movlt r5, #1 8016236: 2500 movge r5, #0 8016238: f7ff fd48 bl 8015ccc <_Balloc> 801623c: 4602 mov r2, r0 801623e: b918 cbnz r0, 8016248 <__mdiff+0x60> 8016240: f240 2145 movw r1, #581 @ 0x245 8016244: 4b30 ldr r3, [pc, #192] @ (8016308 <__mdiff+0x120>) 8016246: e7e3 b.n 8016210 <__mdiff+0x28> 8016248: f100 0b14 add.w fp, r0, #20 801624c: f8d9 7010 ldr.w r7, [r9, #16] 8016250: f109 0310 add.w r3, r9, #16 8016254: 60c5 str r5, [r0, #12] 8016256: f04f 0c00 mov.w ip, #0 801625a: f109 0514 add.w r5, r9, #20 801625e: 46d9 mov r9, fp 8016260: 6926 ldr r6, [r4, #16] 8016262: f104 0e14 add.w lr, r4, #20 8016266: eb05 0887 add.w r8, r5, r7, lsl #2 801626a: eb0e 0686 add.w r6, lr, r6, lsl #2 801626e: 9301 str r3, [sp, #4] 8016270: 9b01 ldr r3, [sp, #4] 8016272: f85e 0b04 ldr.w r0, [lr], #4 8016276: f853 af04 ldr.w sl, [r3, #4]! 801627a: b281 uxth r1, r0 801627c: 9301 str r3, [sp, #4] 801627e: fa1f f38a uxth.w r3, sl 8016282: 1a5b subs r3, r3, r1 8016284: 0c00 lsrs r0, r0, #16 8016286: 4463 add r3, ip 8016288: ebc0 401a rsb r0, r0, sl, lsr #16 801628c: eb00 4023 add.w r0, r0, r3, asr #16 8016290: b29b uxth r3, r3 8016292: ea43 4300 orr.w r3, r3, r0, lsl #16 8016296: 4576 cmp r6, lr 8016298: ea4f 4c20 mov.w ip, r0, asr #16 801629c: f849 3b04 str.w r3, [r9], #4 80162a0: d8e6 bhi.n 8016270 <__mdiff+0x88> 80162a2: 1b33 subs r3, r6, r4 80162a4: 3b15 subs r3, #21 80162a6: f023 0303 bic.w r3, r3, #3 80162aa: 3415 adds r4, #21 80162ac: 3304 adds r3, #4 80162ae: 42a6 cmp r6, r4 80162b0: bf38 it cc 80162b2: 2304 movcc r3, #4 80162b4: 441d add r5, r3 80162b6: 445b add r3, fp 80162b8: 461e mov r6, r3 80162ba: 462c mov r4, r5 80162bc: 4544 cmp r4, r8 80162be: d30e bcc.n 80162de <__mdiff+0xf6> 80162c0: f108 0103 add.w r1, r8, #3 80162c4: 1b49 subs r1, r1, r5 80162c6: f021 0103 bic.w r1, r1, #3 80162ca: 3d03 subs r5, #3 80162cc: 45a8 cmp r8, r5 80162ce: bf38 it cc 80162d0: 2100 movcc r1, #0 80162d2: 440b add r3, r1 80162d4: f853 1d04 ldr.w r1, [r3, #-4]! 80162d8: b199 cbz r1, 8016302 <__mdiff+0x11a> 80162da: 6117 str r7, [r2, #16] 80162dc: e79e b.n 801621c <__mdiff+0x34> 80162de: 46e6 mov lr, ip 80162e0: f854 1b04 ldr.w r1, [r4], #4 80162e4: fa1f fc81 uxth.w ip, r1 80162e8: 44f4 add ip, lr 80162ea: 0c08 lsrs r0, r1, #16 80162ec: 4471 add r1, lr 80162ee: eb00 402c add.w r0, r0, ip, asr #16 80162f2: b289 uxth r1, r1 80162f4: ea41 4100 orr.w r1, r1, r0, lsl #16 80162f8: ea4f 4c20 mov.w ip, r0, asr #16 80162fc: f846 1b04 str.w r1, [r6], #4 8016300: e7dc b.n 80162bc <__mdiff+0xd4> 8016302: 3f01 subs r7, #1 8016304: e7e6 b.n 80162d4 <__mdiff+0xec> 8016306: bf00 nop 8016308: 08017368 .word 0x08017368 801630c: 0801738a .word 0x0801738a 08016310 <__d2b>: 8016310: e92d 4373 stmdb sp!, {r0, r1, r4, r5, r6, r8, r9, lr} 8016314: 2101 movs r1, #1 8016316: 4690 mov r8, r2 8016318: 4699 mov r9, r3 801631a: 9e08 ldr r6, [sp, #32] 801631c: f7ff fcd6 bl 8015ccc <_Balloc> 8016320: 4604 mov r4, r0 8016322: b930 cbnz r0, 8016332 <__d2b+0x22> 8016324: 4602 mov r2, r0 8016326: f240 310f movw r1, #783 @ 0x30f 801632a: 4b23 ldr r3, [pc, #140] @ (80163b8 <__d2b+0xa8>) 801632c: 4823 ldr r0, [pc, #140] @ (80163bc <__d2b+0xac>) 801632e: f7fe fa5b bl 80147e8 <__assert_func> 8016332: f3c9 550a ubfx r5, r9, #20, #11 8016336: f3c9 0313 ubfx r3, r9, #0, #20 801633a: b10d cbz r5, 8016340 <__d2b+0x30> 801633c: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8016340: 9301 str r3, [sp, #4] 8016342: f1b8 0300 subs.w r3, r8, #0 8016346: d024 beq.n 8016392 <__d2b+0x82> 8016348: 4668 mov r0, sp 801634a: 9300 str r3, [sp, #0] 801634c: f7ff fd85 bl 8015e5a <__lo0bits> 8016350: e9dd 1200 ldrd r1, r2, [sp] 8016354: b1d8 cbz r0, 801638e <__d2b+0x7e> 8016356: f1c0 0320 rsb r3, r0, #32 801635a: fa02 f303 lsl.w r3, r2, r3 801635e: 430b orrs r3, r1 8016360: 40c2 lsrs r2, r0 8016362: 6163 str r3, [r4, #20] 8016364: 9201 str r2, [sp, #4] 8016366: 9b01 ldr r3, [sp, #4] 8016368: 2b00 cmp r3, #0 801636a: bf0c ite eq 801636c: 2201 moveq r2, #1 801636e: 2202 movne r2, #2 8016370: 61a3 str r3, [r4, #24] 8016372: 6122 str r2, [r4, #16] 8016374: b1ad cbz r5, 80163a2 <__d2b+0x92> 8016376: f2a5 4533 subw r5, r5, #1075 @ 0x433 801637a: 4405 add r5, r0 801637c: 6035 str r5, [r6, #0] 801637e: f1c0 0035 rsb r0, r0, #53 @ 0x35 8016382: 9b09 ldr r3, [sp, #36] @ 0x24 8016384: 6018 str r0, [r3, #0] 8016386: 4620 mov r0, r4 8016388: b002 add sp, #8 801638a: e8bd 8370 ldmia.w sp!, {r4, r5, r6, r8, r9, pc} 801638e: 6161 str r1, [r4, #20] 8016390: e7e9 b.n 8016366 <__d2b+0x56> 8016392: a801 add r0, sp, #4 8016394: f7ff fd61 bl 8015e5a <__lo0bits> 8016398: 9b01 ldr r3, [sp, #4] 801639a: 2201 movs r2, #1 801639c: 6163 str r3, [r4, #20] 801639e: 3020 adds r0, #32 80163a0: e7e7 b.n 8016372 <__d2b+0x62> 80163a2: f2a0 4032 subw r0, r0, #1074 @ 0x432 80163a6: eb04 0382 add.w r3, r4, r2, lsl #2 80163aa: 6030 str r0, [r6, #0] 80163ac: 6918 ldr r0, [r3, #16] 80163ae: f7ff fd35 bl 8015e1c <__hi0bits> 80163b2: ebc0 1042 rsb r0, r0, r2, lsl #5 80163b6: e7e4 b.n 8016382 <__d2b+0x72> 80163b8: 08017368 .word 0x08017368 80163bc: 0801738a .word 0x0801738a 080163c0 <__sread>: 80163c0: b510 push {r4, lr} 80163c2: 460c mov r4, r1 80163c4: f9b1 100e ldrsh.w r1, [r1, #14] 80163c8: f000 f9b0 bl 801672c <_read_r> 80163cc: 2800 cmp r0, #0 80163ce: bfab itete ge 80163d0: 6d63 ldrge r3, [r4, #84] @ 0x54 80163d2: 89a3 ldrhlt r3, [r4, #12] 80163d4: 181b addge r3, r3, r0 80163d6: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 80163da: bfac ite ge 80163dc: 6563 strge r3, [r4, #84] @ 0x54 80163de: 81a3 strhlt r3, [r4, #12] 80163e0: bd10 pop {r4, pc} 080163e2 <__swrite>: 80163e2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80163e6: 461f mov r7, r3 80163e8: 898b ldrh r3, [r1, #12] 80163ea: 4605 mov r5, r0 80163ec: 05db lsls r3, r3, #23 80163ee: 460c mov r4, r1 80163f0: 4616 mov r6, r2 80163f2: d505 bpl.n 8016400 <__swrite+0x1e> 80163f4: 2302 movs r3, #2 80163f6: 2200 movs r2, #0 80163f8: f9b1 100e ldrsh.w r1, [r1, #14] 80163fc: f000 f984 bl 8016708 <_lseek_r> 8016400: 89a3 ldrh r3, [r4, #12] 8016402: 4632 mov r2, r6 8016404: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8016408: 81a3 strh r3, [r4, #12] 801640a: 4628 mov r0, r5 801640c: 463b mov r3, r7 801640e: f9b4 100e ldrsh.w r1, [r4, #14] 8016412: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8016416: f000 b9ab b.w 8016770 <_write_r> 0801641a <__sseek>: 801641a: b510 push {r4, lr} 801641c: 460c mov r4, r1 801641e: f9b1 100e ldrsh.w r1, [r1, #14] 8016422: f000 f971 bl 8016708 <_lseek_r> 8016426: 1c43 adds r3, r0, #1 8016428: 89a3 ldrh r3, [r4, #12] 801642a: bf15 itete ne 801642c: 6560 strne r0, [r4, #84] @ 0x54 801642e: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 8016432: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 8016436: 81a3 strheq r3, [r4, #12] 8016438: bf18 it ne 801643a: 81a3 strhne r3, [r4, #12] 801643c: bd10 pop {r4, pc} 0801643e <__sclose>: 801643e: f9b1 100e ldrsh.w r1, [r1, #14] 8016442: f000 b9a7 b.w 8016794 <_close_r> ... 08016448 : 8016448: b40e push {r1, r2, r3} 801644a: b503 push {r0, r1, lr} 801644c: 4601 mov r1, r0 801644e: ab03 add r3, sp, #12 8016450: 4805 ldr r0, [pc, #20] @ (8016468 ) 8016452: f853 2b04 ldr.w r2, [r3], #4 8016456: 6800 ldr r0, [r0, #0] 8016458: 9301 str r3, [sp, #4] 801645a: f7ff f9c1 bl 80157e0 <_vfiprintf_r> 801645e: b002 add sp, #8 8016460: f85d eb04 ldr.w lr, [sp], #4 8016464: b003 add sp, #12 8016466: 4770 bx lr 8016468: 2000009c .word 0x2000009c 0801646c <_realloc_r>: 801646c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8016470: 4607 mov r7, r0 8016472: 4614 mov r4, r2 8016474: 460d mov r5, r1 8016476: b921 cbnz r1, 8016482 <_realloc_r+0x16> 8016478: 4611 mov r1, r2 801647a: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 801647e: f7ff baf1 b.w 8015a64 <_malloc_r> 8016482: b92a cbnz r2, 8016490 <_realloc_r+0x24> 8016484: f000 f9c4 bl 8016810 <_free_r> 8016488: 4625 mov r5, r4 801648a: 4628 mov r0, r5 801648c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8016490: f000 fa18 bl 80168c4 <_malloc_usable_size_r> 8016494: 4284 cmp r4, r0 8016496: 4606 mov r6, r0 8016498: d802 bhi.n 80164a0 <_realloc_r+0x34> 801649a: ebb4 0f50 cmp.w r4, r0, lsr #1 801649e: d8f4 bhi.n 801648a <_realloc_r+0x1e> 80164a0: 4621 mov r1, r4 80164a2: 4638 mov r0, r7 80164a4: f7ff fade bl 8015a64 <_malloc_r> 80164a8: 4680 mov r8, r0 80164aa: b908 cbnz r0, 80164b0 <_realloc_r+0x44> 80164ac: 4645 mov r5, r8 80164ae: e7ec b.n 801648a <_realloc_r+0x1e> 80164b0: 42b4 cmp r4, r6 80164b2: 4622 mov r2, r4 80164b4: 4629 mov r1, r5 80164b6: bf28 it cs 80164b8: 4632 movcs r2, r6 80164ba: f7fe f987 bl 80147cc 80164be: 4629 mov r1, r5 80164c0: 4638 mov r0, r7 80164c2: f000 f9a5 bl 8016810 <_free_r> 80164c6: e7f1 b.n 80164ac <_realloc_r+0x40> 080164c8 <__swbuf_r>: 80164c8: b5f8 push {r3, r4, r5, r6, r7, lr} 80164ca: 460e mov r6, r1 80164cc: 4614 mov r4, r2 80164ce: 4605 mov r5, r0 80164d0: b118 cbz r0, 80164da <__swbuf_r+0x12> 80164d2: 6a03 ldr r3, [r0, #32] 80164d4: b90b cbnz r3, 80164da <__swbuf_r+0x12> 80164d6: f7fe f8ad bl 8014634 <__sinit> 80164da: 69a3 ldr r3, [r4, #24] 80164dc: 60a3 str r3, [r4, #8] 80164de: 89a3 ldrh r3, [r4, #12] 80164e0: 071a lsls r2, r3, #28 80164e2: d501 bpl.n 80164e8 <__swbuf_r+0x20> 80164e4: 6923 ldr r3, [r4, #16] 80164e6: b943 cbnz r3, 80164fa <__swbuf_r+0x32> 80164e8: 4621 mov r1, r4 80164ea: 4628 mov r0, r5 80164ec: f000 f82a bl 8016544 <__swsetup_r> 80164f0: b118 cbz r0, 80164fa <__swbuf_r+0x32> 80164f2: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff 80164f6: 4638 mov r0, r7 80164f8: bdf8 pop {r3, r4, r5, r6, r7, pc} 80164fa: 6823 ldr r3, [r4, #0] 80164fc: 6922 ldr r2, [r4, #16] 80164fe: b2f6 uxtb r6, r6 8016500: 1a98 subs r0, r3, r2 8016502: 6963 ldr r3, [r4, #20] 8016504: 4637 mov r7, r6 8016506: 4283 cmp r3, r0 8016508: dc05 bgt.n 8016516 <__swbuf_r+0x4e> 801650a: 4621 mov r1, r4 801650c: 4628 mov r0, r5 801650e: f7ff fba9 bl 8015c64 <_fflush_r> 8016512: 2800 cmp r0, #0 8016514: d1ed bne.n 80164f2 <__swbuf_r+0x2a> 8016516: 68a3 ldr r3, [r4, #8] 8016518: 3b01 subs r3, #1 801651a: 60a3 str r3, [r4, #8] 801651c: 6823 ldr r3, [r4, #0] 801651e: 1c5a adds r2, r3, #1 8016520: 6022 str r2, [r4, #0] 8016522: 701e strb r6, [r3, #0] 8016524: 6962 ldr r2, [r4, #20] 8016526: 1c43 adds r3, r0, #1 8016528: 429a cmp r2, r3 801652a: d004 beq.n 8016536 <__swbuf_r+0x6e> 801652c: 89a3 ldrh r3, [r4, #12] 801652e: 07db lsls r3, r3, #31 8016530: d5e1 bpl.n 80164f6 <__swbuf_r+0x2e> 8016532: 2e0a cmp r6, #10 8016534: d1df bne.n 80164f6 <__swbuf_r+0x2e> 8016536: 4621 mov r1, r4 8016538: 4628 mov r0, r5 801653a: f7ff fb93 bl 8015c64 <_fflush_r> 801653e: 2800 cmp r0, #0 8016540: d0d9 beq.n 80164f6 <__swbuf_r+0x2e> 8016542: e7d6 b.n 80164f2 <__swbuf_r+0x2a> 08016544 <__swsetup_r>: 8016544: b538 push {r3, r4, r5, lr} 8016546: 4b29 ldr r3, [pc, #164] @ (80165ec <__swsetup_r+0xa8>) 8016548: 4605 mov r5, r0 801654a: 6818 ldr r0, [r3, #0] 801654c: 460c mov r4, r1 801654e: b118 cbz r0, 8016558 <__swsetup_r+0x14> 8016550: 6a03 ldr r3, [r0, #32] 8016552: b90b cbnz r3, 8016558 <__swsetup_r+0x14> 8016554: f7fe f86e bl 8014634 <__sinit> 8016558: f9b4 300c ldrsh.w r3, [r4, #12] 801655c: 0719 lsls r1, r3, #28 801655e: d422 bmi.n 80165a6 <__swsetup_r+0x62> 8016560: 06da lsls r2, r3, #27 8016562: d407 bmi.n 8016574 <__swsetup_r+0x30> 8016564: 2209 movs r2, #9 8016566: 602a str r2, [r5, #0] 8016568: f043 0340 orr.w r3, r3, #64 @ 0x40 801656c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016570: 81a3 strh r3, [r4, #12] 8016572: e033 b.n 80165dc <__swsetup_r+0x98> 8016574: 0758 lsls r0, r3, #29 8016576: d512 bpl.n 801659e <__swsetup_r+0x5a> 8016578: 6b61 ldr r1, [r4, #52] @ 0x34 801657a: b141 cbz r1, 801658e <__swsetup_r+0x4a> 801657c: f104 0344 add.w r3, r4, #68 @ 0x44 8016580: 4299 cmp r1, r3 8016582: d002 beq.n 801658a <__swsetup_r+0x46> 8016584: 4628 mov r0, r5 8016586: f000 f943 bl 8016810 <_free_r> 801658a: 2300 movs r3, #0 801658c: 6363 str r3, [r4, #52] @ 0x34 801658e: 89a3 ldrh r3, [r4, #12] 8016590: f023 0324 bic.w r3, r3, #36 @ 0x24 8016594: 81a3 strh r3, [r4, #12] 8016596: 2300 movs r3, #0 8016598: 6063 str r3, [r4, #4] 801659a: 6923 ldr r3, [r4, #16] 801659c: 6023 str r3, [r4, #0] 801659e: 89a3 ldrh r3, [r4, #12] 80165a0: f043 0308 orr.w r3, r3, #8 80165a4: 81a3 strh r3, [r4, #12] 80165a6: 6923 ldr r3, [r4, #16] 80165a8: b94b cbnz r3, 80165be <__swsetup_r+0x7a> 80165aa: 89a3 ldrh r3, [r4, #12] 80165ac: f403 7320 and.w r3, r3, #640 @ 0x280 80165b0: f5b3 7f00 cmp.w r3, #512 @ 0x200 80165b4: d003 beq.n 80165be <__swsetup_r+0x7a> 80165b6: 4621 mov r1, r4 80165b8: 4628 mov r0, r5 80165ba: f000 f83e bl 801663a <__smakebuf_r> 80165be: f9b4 300c ldrsh.w r3, [r4, #12] 80165c2: f013 0201 ands.w r2, r3, #1 80165c6: d00a beq.n 80165de <__swsetup_r+0x9a> 80165c8: 2200 movs r2, #0 80165ca: 60a2 str r2, [r4, #8] 80165cc: 6962 ldr r2, [r4, #20] 80165ce: 4252 negs r2, r2 80165d0: 61a2 str r2, [r4, #24] 80165d2: 6922 ldr r2, [r4, #16] 80165d4: b942 cbnz r2, 80165e8 <__swsetup_r+0xa4> 80165d6: f013 0080 ands.w r0, r3, #128 @ 0x80 80165da: d1c5 bne.n 8016568 <__swsetup_r+0x24> 80165dc: bd38 pop {r3, r4, r5, pc} 80165de: 0799 lsls r1, r3, #30 80165e0: bf58 it pl 80165e2: 6962 ldrpl r2, [r4, #20] 80165e4: 60a2 str r2, [r4, #8] 80165e6: e7f4 b.n 80165d2 <__swsetup_r+0x8e> 80165e8: 2000 movs r0, #0 80165ea: e7f7 b.n 80165dc <__swsetup_r+0x98> 80165ec: 2000009c .word 0x2000009c 080165f0 <__swhatbuf_r>: 80165f0: b570 push {r4, r5, r6, lr} 80165f2: 460c mov r4, r1 80165f4: f9b1 100e ldrsh.w r1, [r1, #14] 80165f8: 4615 mov r5, r2 80165fa: 2900 cmp r1, #0 80165fc: 461e mov r6, r3 80165fe: b096 sub sp, #88 @ 0x58 8016600: da0c bge.n 801661c <__swhatbuf_r+0x2c> 8016602: 89a3 ldrh r3, [r4, #12] 8016604: 2100 movs r1, #0 8016606: f013 0f80 tst.w r3, #128 @ 0x80 801660a: bf14 ite ne 801660c: 2340 movne r3, #64 @ 0x40 801660e: f44f 6380 moveq.w r3, #1024 @ 0x400 8016612: 2000 movs r0, #0 8016614: 6031 str r1, [r6, #0] 8016616: 602b str r3, [r5, #0] 8016618: b016 add sp, #88 @ 0x58 801661a: bd70 pop {r4, r5, r6, pc} 801661c: 466a mov r2, sp 801661e: f000 f8c9 bl 80167b4 <_fstat_r> 8016622: 2800 cmp r0, #0 8016624: dbed blt.n 8016602 <__swhatbuf_r+0x12> 8016626: 9901 ldr r1, [sp, #4] 8016628: f401 4170 and.w r1, r1, #61440 @ 0xf000 801662c: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 8016630: 4259 negs r1, r3 8016632: 4159 adcs r1, r3 8016634: f44f 6380 mov.w r3, #1024 @ 0x400 8016638: e7eb b.n 8016612 <__swhatbuf_r+0x22> 0801663a <__smakebuf_r>: 801663a: 898b ldrh r3, [r1, #12] 801663c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 801663e: 079d lsls r5, r3, #30 8016640: 4606 mov r6, r0 8016642: 460c mov r4, r1 8016644: d507 bpl.n 8016656 <__smakebuf_r+0x1c> 8016646: f104 0347 add.w r3, r4, #71 @ 0x47 801664a: 6023 str r3, [r4, #0] 801664c: 6123 str r3, [r4, #16] 801664e: 2301 movs r3, #1 8016650: 6163 str r3, [r4, #20] 8016652: b003 add sp, #12 8016654: bdf0 pop {r4, r5, r6, r7, pc} 8016656: 466a mov r2, sp 8016658: ab01 add r3, sp, #4 801665a: f7ff ffc9 bl 80165f0 <__swhatbuf_r> 801665e: 9f00 ldr r7, [sp, #0] 8016660: 4605 mov r5, r0 8016662: 4639 mov r1, r7 8016664: 4630 mov r0, r6 8016666: f7ff f9fd bl 8015a64 <_malloc_r> 801666a: b948 cbnz r0, 8016680 <__smakebuf_r+0x46> 801666c: f9b4 300c ldrsh.w r3, [r4, #12] 8016670: 059a lsls r2, r3, #22 8016672: d4ee bmi.n 8016652 <__smakebuf_r+0x18> 8016674: f023 0303 bic.w r3, r3, #3 8016678: f043 0302 orr.w r3, r3, #2 801667c: 81a3 strh r3, [r4, #12] 801667e: e7e2 b.n 8016646 <__smakebuf_r+0xc> 8016680: 89a3 ldrh r3, [r4, #12] 8016682: e9c4 0704 strd r0, r7, [r4, #16] 8016686: f043 0380 orr.w r3, r3, #128 @ 0x80 801668a: 81a3 strh r3, [r4, #12] 801668c: 9b01 ldr r3, [sp, #4] 801668e: 6020 str r0, [r4, #0] 8016690: b15b cbz r3, 80166aa <__smakebuf_r+0x70> 8016692: 4630 mov r0, r6 8016694: f9b4 100e ldrsh.w r1, [r4, #14] 8016698: f000 f826 bl 80166e8 <_isatty_r> 801669c: b128 cbz r0, 80166aa <__smakebuf_r+0x70> 801669e: 89a3 ldrh r3, [r4, #12] 80166a0: f023 0303 bic.w r3, r3, #3 80166a4: f043 0301 orr.w r3, r3, #1 80166a8: 81a3 strh r3, [r4, #12] 80166aa: 89a3 ldrh r3, [r4, #12] 80166ac: 431d orrs r5, r3 80166ae: 81a5 strh r5, [r4, #12] 80166b0: e7cf b.n 8016652 <__smakebuf_r+0x18> 080166b2 : 80166b2: 4288 cmp r0, r1 80166b4: b510 push {r4, lr} 80166b6: eb01 0402 add.w r4, r1, r2 80166ba: d902 bls.n 80166c2 80166bc: 4284 cmp r4, r0 80166be: 4623 mov r3, r4 80166c0: d807 bhi.n 80166d2 80166c2: 1e43 subs r3, r0, #1 80166c4: 42a1 cmp r1, r4 80166c6: d008 beq.n 80166da 80166c8: f811 2b01 ldrb.w r2, [r1], #1 80166cc: f803 2f01 strb.w r2, [r3, #1]! 80166d0: e7f8 b.n 80166c4 80166d2: 4601 mov r1, r0 80166d4: 4402 add r2, r0 80166d6: 428a cmp r2, r1 80166d8: d100 bne.n 80166dc 80166da: bd10 pop {r4, pc} 80166dc: f813 4d01 ldrb.w r4, [r3, #-1]! 80166e0: f802 4d01 strb.w r4, [r2, #-1]! 80166e4: e7f7 b.n 80166d6 ... 080166e8 <_isatty_r>: 80166e8: b538 push {r3, r4, r5, lr} 80166ea: 2300 movs r3, #0 80166ec: 4d05 ldr r5, [pc, #20] @ (8016704 <_isatty_r+0x1c>) 80166ee: 4604 mov r4, r0 80166f0: 4608 mov r0, r1 80166f2: 602b str r3, [r5, #0] 80166f4: f7f6 ffa7 bl 800d646 <_isatty> 80166f8: 1c43 adds r3, r0, #1 80166fa: d102 bne.n 8016702 <_isatty_r+0x1a> 80166fc: 682b ldr r3, [r5, #0] 80166fe: b103 cbz r3, 8016702 <_isatty_r+0x1a> 8016700: 6023 str r3, [r4, #0] 8016702: bd38 pop {r3, r4, r5, pc} 8016704: 200013bc .word 0x200013bc 08016708 <_lseek_r>: 8016708: b538 push {r3, r4, r5, lr} 801670a: 4604 mov r4, r0 801670c: 4608 mov r0, r1 801670e: 4611 mov r1, r2 8016710: 2200 movs r2, #0 8016712: 4d05 ldr r5, [pc, #20] @ (8016728 <_lseek_r+0x20>) 8016714: 602a str r2, [r5, #0] 8016716: 461a mov r2, r3 8016718: f7f6 ff9f bl 800d65a <_lseek> 801671c: 1c43 adds r3, r0, #1 801671e: d102 bne.n 8016726 <_lseek_r+0x1e> 8016720: 682b ldr r3, [r5, #0] 8016722: b103 cbz r3, 8016726 <_lseek_r+0x1e> 8016724: 6023 str r3, [r4, #0] 8016726: bd38 pop {r3, r4, r5, pc} 8016728: 200013bc .word 0x200013bc 0801672c <_read_r>: 801672c: b538 push {r3, r4, r5, lr} 801672e: 4604 mov r4, r0 8016730: 4608 mov r0, r1 8016732: 4611 mov r1, r2 8016734: 2200 movs r2, #0 8016736: 4d05 ldr r5, [pc, #20] @ (801674c <_read_r+0x20>) 8016738: 602a str r2, [r5, #0] 801673a: 461a mov r2, r3 801673c: f7f6 ff4c bl 800d5d8 <_read> 8016740: 1c43 adds r3, r0, #1 8016742: d102 bne.n 801674a <_read_r+0x1e> 8016744: 682b ldr r3, [r5, #0] 8016746: b103 cbz r3, 801674a <_read_r+0x1e> 8016748: 6023 str r3, [r4, #0] 801674a: bd38 pop {r3, r4, r5, pc} 801674c: 200013bc .word 0x200013bc 08016750 <_sbrk_r>: 8016750: b538 push {r3, r4, r5, lr} 8016752: 2300 movs r3, #0 8016754: 4d05 ldr r5, [pc, #20] @ (801676c <_sbrk_r+0x1c>) 8016756: 4604 mov r4, r0 8016758: 4608 mov r0, r1 801675a: 602b str r3, [r5, #0] 801675c: f7f6 ff8a bl 800d674 <_sbrk> 8016760: 1c43 adds r3, r0, #1 8016762: d102 bne.n 801676a <_sbrk_r+0x1a> 8016764: 682b ldr r3, [r5, #0] 8016766: b103 cbz r3, 801676a <_sbrk_r+0x1a> 8016768: 6023 str r3, [r4, #0] 801676a: bd38 pop {r3, r4, r5, pc} 801676c: 200013bc .word 0x200013bc 08016770 <_write_r>: 8016770: b538 push {r3, r4, r5, lr} 8016772: 4604 mov r4, r0 8016774: 4608 mov r0, r1 8016776: 4611 mov r1, r2 8016778: 2200 movs r2, #0 801677a: 4d05 ldr r5, [pc, #20] @ (8016790 <_write_r+0x20>) 801677c: 602a str r2, [r5, #0] 801677e: 461a mov r2, r3 8016780: f7f3 fdc8 bl 800a314 <_write> 8016784: 1c43 adds r3, r0, #1 8016786: d102 bne.n 801678e <_write_r+0x1e> 8016788: 682b ldr r3, [r5, #0] 801678a: b103 cbz r3, 801678e <_write_r+0x1e> 801678c: 6023 str r3, [r4, #0] 801678e: bd38 pop {r3, r4, r5, pc} 8016790: 200013bc .word 0x200013bc 08016794 <_close_r>: 8016794: b538 push {r3, r4, r5, lr} 8016796: 2300 movs r3, #0 8016798: 4d05 ldr r5, [pc, #20] @ (80167b0 <_close_r+0x1c>) 801679a: 4604 mov r4, r0 801679c: 4608 mov r0, r1 801679e: 602b str r3, [r5, #0] 80167a0: f7f6 ff37 bl 800d612 <_close> 80167a4: 1c43 adds r3, r0, #1 80167a6: d102 bne.n 80167ae <_close_r+0x1a> 80167a8: 682b ldr r3, [r5, #0] 80167aa: b103 cbz r3, 80167ae <_close_r+0x1a> 80167ac: 6023 str r3, [r4, #0] 80167ae: bd38 pop {r3, r4, r5, pc} 80167b0: 200013bc .word 0x200013bc 080167b4 <_fstat_r>: 80167b4: b538 push {r3, r4, r5, lr} 80167b6: 2300 movs r3, #0 80167b8: 4d06 ldr r5, [pc, #24] @ (80167d4 <_fstat_r+0x20>) 80167ba: 4604 mov r4, r0 80167bc: 4608 mov r0, r1 80167be: 4611 mov r1, r2 80167c0: 602b str r3, [r5, #0] 80167c2: f7f6 ff31 bl 800d628 <_fstat> 80167c6: 1c43 adds r3, r0, #1 80167c8: d102 bne.n 80167d0 <_fstat_r+0x1c> 80167ca: 682b ldr r3, [r5, #0] 80167cc: b103 cbz r3, 80167d0 <_fstat_r+0x1c> 80167ce: 6023 str r3, [r4, #0] 80167d0: bd38 pop {r3, r4, r5, pc} 80167d2: bf00 nop 80167d4: 200013bc .word 0x200013bc 080167d8 : 80167d8: 2006 movs r0, #6 80167da: b508 push {r3, lr} 80167dc: f000 f8b0 bl 8016940 80167e0: 2001 movs r0, #1 80167e2: f7f6 feee bl 800d5c2 <_exit> 080167e6 <_calloc_r>: 80167e6: b570 push {r4, r5, r6, lr} 80167e8: fba1 5402 umull r5, r4, r1, r2 80167ec: b934 cbnz r4, 80167fc <_calloc_r+0x16> 80167ee: 4629 mov r1, r5 80167f0: f7ff f938 bl 8015a64 <_malloc_r> 80167f4: 4606 mov r6, r0 80167f6: b928 cbnz r0, 8016804 <_calloc_r+0x1e> 80167f8: 4630 mov r0, r6 80167fa: bd70 pop {r4, r5, r6, pc} 80167fc: 220c movs r2, #12 80167fe: 2600 movs r6, #0 8016800: 6002 str r2, [r0, #0] 8016802: e7f9 b.n 80167f8 <_calloc_r+0x12> 8016804: 462a mov r2, r5 8016806: 4621 mov r1, r4 8016808: f7fd ff98 bl 801473c 801680c: e7f4 b.n 80167f8 <_calloc_r+0x12> ... 08016810 <_free_r>: 8016810: b538 push {r3, r4, r5, lr} 8016812: 4605 mov r5, r0 8016814: 2900 cmp r1, #0 8016816: d040 beq.n 801689a <_free_r+0x8a> 8016818: f851 3c04 ldr.w r3, [r1, #-4] 801681c: 1f0c subs r4, r1, #4 801681e: 2b00 cmp r3, #0 8016820: bfb8 it lt 8016822: 18e4 addlt r4, r4, r3 8016824: f7ff fa46 bl 8015cb4 <__malloc_lock> 8016828: 4a1c ldr r2, [pc, #112] @ (801689c <_free_r+0x8c>) 801682a: 6813 ldr r3, [r2, #0] 801682c: b933 cbnz r3, 801683c <_free_r+0x2c> 801682e: 6063 str r3, [r4, #4] 8016830: 6014 str r4, [r2, #0] 8016832: 4628 mov r0, r5 8016834: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8016838: f7ff ba42 b.w 8015cc0 <__malloc_unlock> 801683c: 42a3 cmp r3, r4 801683e: d908 bls.n 8016852 <_free_r+0x42> 8016840: 6820 ldr r0, [r4, #0] 8016842: 1821 adds r1, r4, r0 8016844: 428b cmp r3, r1 8016846: bf01 itttt eq 8016848: 6819 ldreq r1, [r3, #0] 801684a: 685b ldreq r3, [r3, #4] 801684c: 1809 addeq r1, r1, r0 801684e: 6021 streq r1, [r4, #0] 8016850: e7ed b.n 801682e <_free_r+0x1e> 8016852: 461a mov r2, r3 8016854: 685b ldr r3, [r3, #4] 8016856: b10b cbz r3, 801685c <_free_r+0x4c> 8016858: 42a3 cmp r3, r4 801685a: d9fa bls.n 8016852 <_free_r+0x42> 801685c: 6811 ldr r1, [r2, #0] 801685e: 1850 adds r0, r2, r1 8016860: 42a0 cmp r0, r4 8016862: d10b bne.n 801687c <_free_r+0x6c> 8016864: 6820 ldr r0, [r4, #0] 8016866: 4401 add r1, r0 8016868: 1850 adds r0, r2, r1 801686a: 4283 cmp r3, r0 801686c: 6011 str r1, [r2, #0] 801686e: d1e0 bne.n 8016832 <_free_r+0x22> 8016870: 6818 ldr r0, [r3, #0] 8016872: 685b ldr r3, [r3, #4] 8016874: 4408 add r0, r1 8016876: 6010 str r0, [r2, #0] 8016878: 6053 str r3, [r2, #4] 801687a: e7da b.n 8016832 <_free_r+0x22> 801687c: d902 bls.n 8016884 <_free_r+0x74> 801687e: 230c movs r3, #12 8016880: 602b str r3, [r5, #0] 8016882: e7d6 b.n 8016832 <_free_r+0x22> 8016884: 6820 ldr r0, [r4, #0] 8016886: 1821 adds r1, r4, r0 8016888: 428b cmp r3, r1 801688a: bf01 itttt eq 801688c: 6819 ldreq r1, [r3, #0] 801688e: 685b ldreq r3, [r3, #4] 8016890: 1809 addeq r1, r1, r0 8016892: 6021 streq r1, [r4, #0] 8016894: 6063 str r3, [r4, #4] 8016896: 6054 str r4, [r2, #4] 8016898: e7cb b.n 8016832 <_free_r+0x22> 801689a: bd38 pop {r3, r4, r5, pc} 801689c: 200013b8 .word 0x200013b8 080168a0 <__ascii_mbtowc>: 80168a0: b082 sub sp, #8 80168a2: b901 cbnz r1, 80168a6 <__ascii_mbtowc+0x6> 80168a4: a901 add r1, sp, #4 80168a6: b142 cbz r2, 80168ba <__ascii_mbtowc+0x1a> 80168a8: b14b cbz r3, 80168be <__ascii_mbtowc+0x1e> 80168aa: 7813 ldrb r3, [r2, #0] 80168ac: 600b str r3, [r1, #0] 80168ae: 7812 ldrb r2, [r2, #0] 80168b0: 1e10 subs r0, r2, #0 80168b2: bf18 it ne 80168b4: 2001 movne r0, #1 80168b6: b002 add sp, #8 80168b8: 4770 bx lr 80168ba: 4610 mov r0, r2 80168bc: e7fb b.n 80168b6 <__ascii_mbtowc+0x16> 80168be: f06f 0001 mvn.w r0, #1 80168c2: e7f8 b.n 80168b6 <__ascii_mbtowc+0x16> 080168c4 <_malloc_usable_size_r>: 80168c4: f851 3c04 ldr.w r3, [r1, #-4] 80168c8: 1f18 subs r0, r3, #4 80168ca: 2b00 cmp r3, #0 80168cc: bfbc itt lt 80168ce: 580b ldrlt r3, [r1, r0] 80168d0: 18c0 addlt r0, r0, r3 80168d2: 4770 bx lr 080168d4 <__ascii_wctomb>: 80168d4: 4603 mov r3, r0 80168d6: 4608 mov r0, r1 80168d8: b141 cbz r1, 80168ec <__ascii_wctomb+0x18> 80168da: 2aff cmp r2, #255 @ 0xff 80168dc: d904 bls.n 80168e8 <__ascii_wctomb+0x14> 80168de: 228a movs r2, #138 @ 0x8a 80168e0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80168e4: 601a str r2, [r3, #0] 80168e6: 4770 bx lr 80168e8: 2001 movs r0, #1 80168ea: 700a strb r2, [r1, #0] 80168ec: 4770 bx lr 080168ee <_raise_r>: 80168ee: 291f cmp r1, #31 80168f0: b538 push {r3, r4, r5, lr} 80168f2: 4605 mov r5, r0 80168f4: 460c mov r4, r1 80168f6: d904 bls.n 8016902 <_raise_r+0x14> 80168f8: 2316 movs r3, #22 80168fa: 6003 str r3, [r0, #0] 80168fc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016900: bd38 pop {r3, r4, r5, pc} 8016902: 6bc2 ldr r2, [r0, #60] @ 0x3c 8016904: b112 cbz r2, 801690c <_raise_r+0x1e> 8016906: f852 3021 ldr.w r3, [r2, r1, lsl #2] 801690a: b94b cbnz r3, 8016920 <_raise_r+0x32> 801690c: 4628 mov r0, r5 801690e: f000 f831 bl 8016974 <_getpid_r> 8016912: 4622 mov r2, r4 8016914: 4601 mov r1, r0 8016916: 4628 mov r0, r5 8016918: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 801691c: f000 b818 b.w 8016950 <_kill_r> 8016920: 2b01 cmp r3, #1 8016922: d00a beq.n 801693a <_raise_r+0x4c> 8016924: 1c59 adds r1, r3, #1 8016926: d103 bne.n 8016930 <_raise_r+0x42> 8016928: 2316 movs r3, #22 801692a: 6003 str r3, [r0, #0] 801692c: 2001 movs r0, #1 801692e: e7e7 b.n 8016900 <_raise_r+0x12> 8016930: 2100 movs r1, #0 8016932: 4620 mov r0, r4 8016934: f842 1024 str.w r1, [r2, r4, lsl #2] 8016938: 4798 blx r3 801693a: 2000 movs r0, #0 801693c: e7e0 b.n 8016900 <_raise_r+0x12> ... 08016940 : 8016940: 4b02 ldr r3, [pc, #8] @ (801694c ) 8016942: 4601 mov r1, r0 8016944: 6818 ldr r0, [r3, #0] 8016946: f7ff bfd2 b.w 80168ee <_raise_r> 801694a: bf00 nop 801694c: 2000009c .word 0x2000009c 08016950 <_kill_r>: 8016950: b538 push {r3, r4, r5, lr} 8016952: 2300 movs r3, #0 8016954: 4d06 ldr r5, [pc, #24] @ (8016970 <_kill_r+0x20>) 8016956: 4604 mov r4, r0 8016958: 4608 mov r0, r1 801695a: 4611 mov r1, r2 801695c: 602b str r3, [r5, #0] 801695e: f7f6 fe20 bl 800d5a2 <_kill> 8016962: 1c43 adds r3, r0, #1 8016964: d102 bne.n 801696c <_kill_r+0x1c> 8016966: 682b ldr r3, [r5, #0] 8016968: b103 cbz r3, 801696c <_kill_r+0x1c> 801696a: 6023 str r3, [r4, #0] 801696c: bd38 pop {r3, r4, r5, pc} 801696e: bf00 nop 8016970: 200013bc .word 0x200013bc 08016974 <_getpid_r>: 8016974: f7f6 be0e b.w 800d594 <_getpid> 08016978 <_init>: 8016978: b5f8 push {r3, r4, r5, r6, r7, lr} 801697a: bf00 nop 801697c: bcf8 pop {r3, r4, r5, r6, r7} 801697e: bc08 pop {r3} 8016980: 469e mov lr, r3 8016982: 4770 bx lr 08016984 <_fini>: 8016984: b5f8 push {r3, r4, r5, r6, r7, lr} 8016986: bf00 nop 8016988: bcf8 pop {r3, r4, r5, r6, r7} 801698a: bc08 pop {r3} 801698c: 469e mov lr, r3 801698e: 4770 bx lr