CCSModuleSW30Web.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001e8 08008000 08008000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000dd28 080081e8 080081e8 000011e8 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000844 08015f10 08015f10 0000ef10 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08016754 08016754 00010254 2**0 CONTENTS 4 .ARM 00000008 08016754 08016754 0000f754 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 0801675c 0801675c 00010254 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0801675c 0801675c 0000f75c 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08016760 08016760 0000f760 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000254 20000000 08016764 00010000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000010fc 20000258 080169b8 00010258 2**3 ALLOC 10 ._user_heap_stack 00000604 20001354 080169b8 00010354 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 00010254 2**0 CONTENTS, READONLY 12 .debug_info 0001c2c3 00000000 00000000 0001027d 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 000054b3 00000000 00000000 0002c540 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 000016c8 00000000 00000000 000319f8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 0000118d 00000000 00000000 000330c0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00026186 00000000 00000000 0003424d 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0001e8df 00000000 00000000 0005a3d3 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000c9521 00000000 00000000 00078cb2 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 001421d3 2**0 CONTENTS, READONLY 20 .debug_frame 00006d30 00000000 00000000 00142218 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 0000006e 00000000 00000000 00148f48 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080081e8 <__do_global_dtors_aux>: 80081e8: b510 push {r4, lr} 80081ea: 4c05 ldr r4, [pc, #20] @ (8008200 <__do_global_dtors_aux+0x18>) 80081ec: 7823 ldrb r3, [r4, #0] 80081ee: b933 cbnz r3, 80081fe <__do_global_dtors_aux+0x16> 80081f0: 4b04 ldr r3, [pc, #16] @ (8008204 <__do_global_dtors_aux+0x1c>) 80081f2: b113 cbz r3, 80081fa <__do_global_dtors_aux+0x12> 80081f4: 4804 ldr r0, [pc, #16] @ (8008208 <__do_global_dtors_aux+0x20>) 80081f6: f3af 8000 nop.w 80081fa: 2301 movs r3, #1 80081fc: 7023 strb r3, [r4, #0] 80081fe: bd10 pop {r4, pc} 8008200: 20000258 .word 0x20000258 8008204: 00000000 .word 0x00000000 8008208: 08015ef8 .word 0x08015ef8 0800820c : 800820c: b508 push {r3, lr} 800820e: 4b03 ldr r3, [pc, #12] @ (800821c ) 8008210: b11b cbz r3, 800821a 8008212: 4903 ldr r1, [pc, #12] @ (8008220 ) 8008214: 4803 ldr r0, [pc, #12] @ (8008224 ) 8008216: f3af 8000 nop.w 800821a: bd08 pop {r3, pc} 800821c: 00000000 .word 0x00000000 8008220: 2000025c .word 0x2000025c 8008224: 08015ef8 .word 0x08015ef8 08008228 : 8008228: 4603 mov r3, r0 800822a: f813 2b01 ldrb.w r2, [r3], #1 800822e: 2a00 cmp r2, #0 8008230: d1fb bne.n 800822a 8008232: 1a18 subs r0, r3, r0 8008234: 3801 subs r0, #1 8008236: 4770 bx lr 08008238 <__aeabi_drsub>: 8008238: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 800823c: e002 b.n 8008244 <__adddf3> 800823e: bf00 nop 08008240 <__aeabi_dsub>: 8008240: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 08008244 <__adddf3>: 8008244: b530 push {r4, r5, lr} 8008246: ea4f 0441 mov.w r4, r1, lsl #1 800824a: ea4f 0543 mov.w r5, r3, lsl #1 800824e: ea94 0f05 teq r4, r5 8008252: bf08 it eq 8008254: ea90 0f02 teqeq r0, r2 8008258: bf1f itttt ne 800825a: ea54 0c00 orrsne.w ip, r4, r0 800825e: ea55 0c02 orrsne.w ip, r5, r2 8008262: ea7f 5c64 mvnsne.w ip, r4, asr #21 8008266: ea7f 5c65 mvnsne.w ip, r5, asr #21 800826a: f000 80e2 beq.w 8008432 <__adddf3+0x1ee> 800826e: ea4f 5454 mov.w r4, r4, lsr #21 8008272: ebd4 5555 rsbs r5, r4, r5, lsr #21 8008276: bfb8 it lt 8008278: 426d neglt r5, r5 800827a: dd0c ble.n 8008296 <__adddf3+0x52> 800827c: 442c add r4, r5 800827e: ea80 0202 eor.w r2, r0, r2 8008282: ea81 0303 eor.w r3, r1, r3 8008286: ea82 0000 eor.w r0, r2, r0 800828a: ea83 0101 eor.w r1, r3, r1 800828e: ea80 0202 eor.w r2, r0, r2 8008292: ea81 0303 eor.w r3, r1, r3 8008296: 2d36 cmp r5, #54 @ 0x36 8008298: bf88 it hi 800829a: bd30 pophi {r4, r5, pc} 800829c: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 80082a0: ea4f 3101 mov.w r1, r1, lsl #12 80082a4: f44f 1c80 mov.w ip, #1048576 @ 0x100000 80082a8: ea4c 3111 orr.w r1, ip, r1, lsr #12 80082ac: d002 beq.n 80082b4 <__adddf3+0x70> 80082ae: 4240 negs r0, r0 80082b0: eb61 0141 sbc.w r1, r1, r1, lsl #1 80082b4: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 80082b8: ea4f 3303 mov.w r3, r3, lsl #12 80082bc: ea4c 3313 orr.w r3, ip, r3, lsr #12 80082c0: d002 beq.n 80082c8 <__adddf3+0x84> 80082c2: 4252 negs r2, r2 80082c4: eb63 0343 sbc.w r3, r3, r3, lsl #1 80082c8: ea94 0f05 teq r4, r5 80082cc: f000 80a7 beq.w 800841e <__adddf3+0x1da> 80082d0: f1a4 0401 sub.w r4, r4, #1 80082d4: f1d5 0e20 rsbs lr, r5, #32 80082d8: db0d blt.n 80082f6 <__adddf3+0xb2> 80082da: fa02 fc0e lsl.w ip, r2, lr 80082de: fa22 f205 lsr.w r2, r2, r5 80082e2: 1880 adds r0, r0, r2 80082e4: f141 0100 adc.w r1, r1, #0 80082e8: fa03 f20e lsl.w r2, r3, lr 80082ec: 1880 adds r0, r0, r2 80082ee: fa43 f305 asr.w r3, r3, r5 80082f2: 4159 adcs r1, r3 80082f4: e00e b.n 8008314 <__adddf3+0xd0> 80082f6: f1a5 0520 sub.w r5, r5, #32 80082fa: f10e 0e20 add.w lr, lr, #32 80082fe: 2a01 cmp r2, #1 8008300: fa03 fc0e lsl.w ip, r3, lr 8008304: bf28 it cs 8008306: f04c 0c02 orrcs.w ip, ip, #2 800830a: fa43 f305 asr.w r3, r3, r5 800830e: 18c0 adds r0, r0, r3 8008310: eb51 71e3 adcs.w r1, r1, r3, asr #31 8008314: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008318: d507 bpl.n 800832a <__adddf3+0xe6> 800831a: f04f 0e00 mov.w lr, #0 800831e: f1dc 0c00 rsbs ip, ip, #0 8008322: eb7e 0000 sbcs.w r0, lr, r0 8008326: eb6e 0101 sbc.w r1, lr, r1 800832a: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 800832e: d31b bcc.n 8008368 <__adddf3+0x124> 8008330: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 8008334: d30c bcc.n 8008350 <__adddf3+0x10c> 8008336: 0849 lsrs r1, r1, #1 8008338: ea5f 0030 movs.w r0, r0, rrx 800833c: ea4f 0c3c mov.w ip, ip, rrx 8008340: f104 0401 add.w r4, r4, #1 8008344: ea4f 5244 mov.w r2, r4, lsl #21 8008348: f512 0f80 cmn.w r2, #4194304 @ 0x400000 800834c: f080 809a bcs.w 8008484 <__adddf3+0x240> 8008350: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008354: bf08 it eq 8008356: ea5f 0c50 movseq.w ip, r0, lsr #1 800835a: f150 0000 adcs.w r0, r0, #0 800835e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008362: ea41 0105 orr.w r1, r1, r5 8008366: bd30 pop {r4, r5, pc} 8008368: ea5f 0c4c movs.w ip, ip, lsl #1 800836c: 4140 adcs r0, r0 800836e: eb41 0101 adc.w r1, r1, r1 8008372: 3c01 subs r4, #1 8008374: bf28 it cs 8008376: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 800837a: d2e9 bcs.n 8008350 <__adddf3+0x10c> 800837c: f091 0f00 teq r1, #0 8008380: bf04 itt eq 8008382: 4601 moveq r1, r0 8008384: 2000 moveq r0, #0 8008386: fab1 f381 clz r3, r1 800838a: bf08 it eq 800838c: 3320 addeq r3, #32 800838e: f1a3 030b sub.w r3, r3, #11 8008392: f1b3 0220 subs.w r2, r3, #32 8008396: da0c bge.n 80083b2 <__adddf3+0x16e> 8008398: 320c adds r2, #12 800839a: dd08 ble.n 80083ae <__adddf3+0x16a> 800839c: f102 0c14 add.w ip, r2, #20 80083a0: f1c2 020c rsb r2, r2, #12 80083a4: fa01 f00c lsl.w r0, r1, ip 80083a8: fa21 f102 lsr.w r1, r1, r2 80083ac: e00c b.n 80083c8 <__adddf3+0x184> 80083ae: f102 0214 add.w r2, r2, #20 80083b2: bfd8 it le 80083b4: f1c2 0c20 rsble ip, r2, #32 80083b8: fa01 f102 lsl.w r1, r1, r2 80083bc: fa20 fc0c lsr.w ip, r0, ip 80083c0: bfdc itt le 80083c2: ea41 010c orrle.w r1, r1, ip 80083c6: 4090 lslle r0, r2 80083c8: 1ae4 subs r4, r4, r3 80083ca: bfa2 ittt ge 80083cc: eb01 5104 addge.w r1, r1, r4, lsl #20 80083d0: 4329 orrge r1, r5 80083d2: bd30 popge {r4, r5, pc} 80083d4: ea6f 0404 mvn.w r4, r4 80083d8: 3c1f subs r4, #31 80083da: da1c bge.n 8008416 <__adddf3+0x1d2> 80083dc: 340c adds r4, #12 80083de: dc0e bgt.n 80083fe <__adddf3+0x1ba> 80083e0: f104 0414 add.w r4, r4, #20 80083e4: f1c4 0220 rsb r2, r4, #32 80083e8: fa20 f004 lsr.w r0, r0, r4 80083ec: fa01 f302 lsl.w r3, r1, r2 80083f0: ea40 0003 orr.w r0, r0, r3 80083f4: fa21 f304 lsr.w r3, r1, r4 80083f8: ea45 0103 orr.w r1, r5, r3 80083fc: bd30 pop {r4, r5, pc} 80083fe: f1c4 040c rsb r4, r4, #12 8008402: f1c4 0220 rsb r2, r4, #32 8008406: fa20 f002 lsr.w r0, r0, r2 800840a: fa01 f304 lsl.w r3, r1, r4 800840e: ea40 0003 orr.w r0, r0, r3 8008412: 4629 mov r1, r5 8008414: bd30 pop {r4, r5, pc} 8008416: fa21 f004 lsr.w r0, r1, r4 800841a: 4629 mov r1, r5 800841c: bd30 pop {r4, r5, pc} 800841e: f094 0f00 teq r4, #0 8008422: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 8008426: bf06 itte eq 8008428: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 800842c: 3401 addeq r4, #1 800842e: 3d01 subne r5, #1 8008430: e74e b.n 80082d0 <__adddf3+0x8c> 8008432: ea7f 5c64 mvns.w ip, r4, asr #21 8008436: bf18 it ne 8008438: ea7f 5c65 mvnsne.w ip, r5, asr #21 800843c: d029 beq.n 8008492 <__adddf3+0x24e> 800843e: ea94 0f05 teq r4, r5 8008442: bf08 it eq 8008444: ea90 0f02 teqeq r0, r2 8008448: d005 beq.n 8008456 <__adddf3+0x212> 800844a: ea54 0c00 orrs.w ip, r4, r0 800844e: bf04 itt eq 8008450: 4619 moveq r1, r3 8008452: 4610 moveq r0, r2 8008454: bd30 pop {r4, r5, pc} 8008456: ea91 0f03 teq r1, r3 800845a: bf1e ittt ne 800845c: 2100 movne r1, #0 800845e: 2000 movne r0, #0 8008460: bd30 popne {r4, r5, pc} 8008462: ea5f 5c54 movs.w ip, r4, lsr #21 8008466: d105 bne.n 8008474 <__adddf3+0x230> 8008468: 0040 lsls r0, r0, #1 800846a: 4149 adcs r1, r1 800846c: bf28 it cs 800846e: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 8008472: bd30 pop {r4, r5, pc} 8008474: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 8008478: bf3c itt cc 800847a: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 800847e: bd30 popcc {r4, r5, pc} 8008480: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008484: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 8008488: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 800848c: f04f 0000 mov.w r0, #0 8008490: bd30 pop {r4, r5, pc} 8008492: ea7f 5c64 mvns.w ip, r4, asr #21 8008496: bf1a itte ne 8008498: 4619 movne r1, r3 800849a: 4610 movne r0, r2 800849c: ea7f 5c65 mvnseq.w ip, r5, asr #21 80084a0: bf1c itt ne 80084a2: 460b movne r3, r1 80084a4: 4602 movne r2, r0 80084a6: ea50 3401 orrs.w r4, r0, r1, lsl #12 80084aa: bf06 itte eq 80084ac: ea52 3503 orrseq.w r5, r2, r3, lsl #12 80084b0: ea91 0f03 teqeq r1, r3 80084b4: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 80084b8: bd30 pop {r4, r5, pc} 80084ba: bf00 nop 080084bc <__aeabi_ui2d>: 80084bc: f090 0f00 teq r0, #0 80084c0: bf04 itt eq 80084c2: 2100 moveq r1, #0 80084c4: 4770 bxeq lr 80084c6: b530 push {r4, r5, lr} 80084c8: f44f 6480 mov.w r4, #1024 @ 0x400 80084cc: f104 0432 add.w r4, r4, #50 @ 0x32 80084d0: f04f 0500 mov.w r5, #0 80084d4: f04f 0100 mov.w r1, #0 80084d8: e750 b.n 800837c <__adddf3+0x138> 80084da: bf00 nop 080084dc <__aeabi_i2d>: 80084dc: f090 0f00 teq r0, #0 80084e0: bf04 itt eq 80084e2: 2100 moveq r1, #0 80084e4: 4770 bxeq lr 80084e6: b530 push {r4, r5, lr} 80084e8: f44f 6480 mov.w r4, #1024 @ 0x400 80084ec: f104 0432 add.w r4, r4, #50 @ 0x32 80084f0: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 80084f4: bf48 it mi 80084f6: 4240 negmi r0, r0 80084f8: f04f 0100 mov.w r1, #0 80084fc: e73e b.n 800837c <__adddf3+0x138> 80084fe: bf00 nop 08008500 <__aeabi_f2d>: 8008500: 0042 lsls r2, r0, #1 8008502: ea4f 01e2 mov.w r1, r2, asr #3 8008506: ea4f 0131 mov.w r1, r1, rrx 800850a: ea4f 7002 mov.w r0, r2, lsl #28 800850e: bf1f itttt ne 8008510: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 8008514: f093 4f7f teqne r3, #4278190080 @ 0xff000000 8008518: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 800851c: 4770 bxne lr 800851e: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 8008522: bf08 it eq 8008524: 4770 bxeq lr 8008526: f093 4f7f teq r3, #4278190080 @ 0xff000000 800852a: bf04 itt eq 800852c: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 8008530: 4770 bxeq lr 8008532: b530 push {r4, r5, lr} 8008534: f44f 7460 mov.w r4, #896 @ 0x380 8008538: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 800853c: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 8008540: e71c b.n 800837c <__adddf3+0x138> 8008542: bf00 nop 08008544 <__aeabi_ul2d>: 8008544: ea50 0201 orrs.w r2, r0, r1 8008548: bf08 it eq 800854a: 4770 bxeq lr 800854c: b530 push {r4, r5, lr} 800854e: f04f 0500 mov.w r5, #0 8008552: e00a b.n 800856a <__aeabi_l2d+0x16> 08008554 <__aeabi_l2d>: 8008554: ea50 0201 orrs.w r2, r0, r1 8008558: bf08 it eq 800855a: 4770 bxeq lr 800855c: b530 push {r4, r5, lr} 800855e: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 8008562: d502 bpl.n 800856a <__aeabi_l2d+0x16> 8008564: 4240 negs r0, r0 8008566: eb61 0141 sbc.w r1, r1, r1, lsl #1 800856a: f44f 6480 mov.w r4, #1024 @ 0x400 800856e: f104 0432 add.w r4, r4, #50 @ 0x32 8008572: ea5f 5c91 movs.w ip, r1, lsr #22 8008576: f43f aed8 beq.w 800832a <__adddf3+0xe6> 800857a: f04f 0203 mov.w r2, #3 800857e: ea5f 0cdc movs.w ip, ip, lsr #3 8008582: bf18 it ne 8008584: 3203 addne r2, #3 8008586: ea5f 0cdc movs.w ip, ip, lsr #3 800858a: bf18 it ne 800858c: 3203 addne r2, #3 800858e: eb02 02dc add.w r2, r2, ip, lsr #3 8008592: f1c2 0320 rsb r3, r2, #32 8008596: fa00 fc03 lsl.w ip, r0, r3 800859a: fa20 f002 lsr.w r0, r0, r2 800859e: fa01 fe03 lsl.w lr, r1, r3 80085a2: ea40 000e orr.w r0, r0, lr 80085a6: fa21 f102 lsr.w r1, r1, r2 80085aa: 4414 add r4, r2 80085ac: e6bd b.n 800832a <__adddf3+0xe6> 80085ae: bf00 nop 080085b0 <__aeabi_dmul>: 80085b0: b570 push {r4, r5, r6, lr} 80085b2: f04f 0cff mov.w ip, #255 @ 0xff 80085b6: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 80085ba: ea1c 5411 ands.w r4, ip, r1, lsr #20 80085be: bf1d ittte ne 80085c0: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80085c4: ea94 0f0c teqne r4, ip 80085c8: ea95 0f0c teqne r5, ip 80085cc: f000 f8de bleq 800878c <__aeabi_dmul+0x1dc> 80085d0: 442c add r4, r5 80085d2: ea81 0603 eor.w r6, r1, r3 80085d6: ea21 514c bic.w r1, r1, ip, lsl #21 80085da: ea23 534c bic.w r3, r3, ip, lsl #21 80085de: ea50 3501 orrs.w r5, r0, r1, lsl #12 80085e2: bf18 it ne 80085e4: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80085e8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 80085ec: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80085f0: d038 beq.n 8008664 <__aeabi_dmul+0xb4> 80085f2: fba0 ce02 umull ip, lr, r0, r2 80085f6: f04f 0500 mov.w r5, #0 80085fa: fbe1 e502 umlal lr, r5, r1, r2 80085fe: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000 8008602: fbe0 e503 umlal lr, r5, r0, r3 8008606: f04f 0600 mov.w r6, #0 800860a: fbe1 5603 umlal r5, r6, r1, r3 800860e: f09c 0f00 teq ip, #0 8008612: bf18 it ne 8008614: f04e 0e01 orrne.w lr, lr, #1 8008618: f1a4 04ff sub.w r4, r4, #255 @ 0xff 800861c: f5b6 7f00 cmp.w r6, #512 @ 0x200 8008620: f564 7440 sbc.w r4, r4, #768 @ 0x300 8008624: d204 bcs.n 8008630 <__aeabi_dmul+0x80> 8008626: ea5f 0e4e movs.w lr, lr, lsl #1 800862a: 416d adcs r5, r5 800862c: eb46 0606 adc.w r6, r6, r6 8008630: ea42 21c6 orr.w r1, r2, r6, lsl #11 8008634: ea41 5155 orr.w r1, r1, r5, lsr #21 8008638: ea4f 20c5 mov.w r0, r5, lsl #11 800863c: ea40 505e orr.w r0, r0, lr, lsr #21 8008640: ea4f 2ece mov.w lr, lr, lsl #11 8008644: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008648: bf88 it hi 800864a: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800864e: d81e bhi.n 800868e <__aeabi_dmul+0xde> 8008650: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000 8008654: bf08 it eq 8008656: ea5f 0e50 movseq.w lr, r0, lsr #1 800865a: f150 0000 adcs.w r0, r0, #0 800865e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008662: bd70 pop {r4, r5, r6, pc} 8008664: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000 8008668: ea46 0101 orr.w r1, r6, r1 800866c: ea40 0002 orr.w r0, r0, r2 8008670: ea81 0103 eor.w r1, r1, r3 8008674: ebb4 045c subs.w r4, r4, ip, lsr #1 8008678: bfc2 ittt gt 800867a: ebd4 050c rsbsgt r5, r4, ip 800867e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8008682: bd70 popgt {r4, r5, r6, pc} 8008684: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008688: f04f 0e00 mov.w lr, #0 800868c: 3c01 subs r4, #1 800868e: f300 80ab bgt.w 80087e8 <__aeabi_dmul+0x238> 8008692: f114 0f36 cmn.w r4, #54 @ 0x36 8008696: bfde ittt le 8008698: 2000 movle r0, #0 800869a: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000 800869e: bd70 pople {r4, r5, r6, pc} 80086a0: f1c4 0400 rsb r4, r4, #0 80086a4: 3c20 subs r4, #32 80086a6: da35 bge.n 8008714 <__aeabi_dmul+0x164> 80086a8: 340c adds r4, #12 80086aa: dc1b bgt.n 80086e4 <__aeabi_dmul+0x134> 80086ac: f104 0414 add.w r4, r4, #20 80086b0: f1c4 0520 rsb r5, r4, #32 80086b4: fa00 f305 lsl.w r3, r0, r5 80086b8: fa20 f004 lsr.w r0, r0, r4 80086bc: fa01 f205 lsl.w r2, r1, r5 80086c0: ea40 0002 orr.w r0, r0, r2 80086c4: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000 80086c8: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 80086cc: eb10 70d3 adds.w r0, r0, r3, lsr #31 80086d0: fa21 f604 lsr.w r6, r1, r4 80086d4: eb42 0106 adc.w r1, r2, r6 80086d8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80086dc: bf08 it eq 80086de: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80086e2: bd70 pop {r4, r5, r6, pc} 80086e4: f1c4 040c rsb r4, r4, #12 80086e8: f1c4 0520 rsb r5, r4, #32 80086ec: fa00 f304 lsl.w r3, r0, r4 80086f0: fa20 f005 lsr.w r0, r0, r5 80086f4: fa01 f204 lsl.w r2, r1, r4 80086f8: ea40 0002 orr.w r0, r0, r2 80086fc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8008700: eb10 70d3 adds.w r0, r0, r3, lsr #31 8008704: f141 0100 adc.w r1, r1, #0 8008708: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 800870c: bf08 it eq 800870e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8008712: bd70 pop {r4, r5, r6, pc} 8008714: f1c4 0520 rsb r5, r4, #32 8008718: fa00 f205 lsl.w r2, r0, r5 800871c: ea4e 0e02 orr.w lr, lr, r2 8008720: fa20 f304 lsr.w r3, r0, r4 8008724: fa01 f205 lsl.w r2, r1, r5 8008728: ea43 0302 orr.w r3, r3, r2 800872c: fa21 f004 lsr.w r0, r1, r4 8008730: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8008734: fa21 f204 lsr.w r2, r1, r4 8008738: ea20 0002 bic.w r0, r0, r2 800873c: eb00 70d3 add.w r0, r0, r3, lsr #31 8008740: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8008744: bf08 it eq 8008746: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800874a: bd70 pop {r4, r5, r6, pc} 800874c: f094 0f00 teq r4, #0 8008750: d10f bne.n 8008772 <__aeabi_dmul+0x1c2> 8008752: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000 8008756: 0040 lsls r0, r0, #1 8008758: eb41 0101 adc.w r1, r1, r1 800875c: f411 1f80 tst.w r1, #1048576 @ 0x100000 8008760: bf08 it eq 8008762: 3c01 subeq r4, #1 8008764: d0f7 beq.n 8008756 <__aeabi_dmul+0x1a6> 8008766: ea41 0106 orr.w r1, r1, r6 800876a: f095 0f00 teq r5, #0 800876e: bf18 it ne 8008770: 4770 bxne lr 8008772: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000 8008776: 0052 lsls r2, r2, #1 8008778: eb43 0303 adc.w r3, r3, r3 800877c: f413 1f80 tst.w r3, #1048576 @ 0x100000 8008780: bf08 it eq 8008782: 3d01 subeq r5, #1 8008784: d0f7 beq.n 8008776 <__aeabi_dmul+0x1c6> 8008786: ea43 0306 orr.w r3, r3, r6 800878a: 4770 bx lr 800878c: ea94 0f0c teq r4, ip 8008790: ea0c 5513 and.w r5, ip, r3, lsr #20 8008794: bf18 it ne 8008796: ea95 0f0c teqne r5, ip 800879a: d00c beq.n 80087b6 <__aeabi_dmul+0x206> 800879c: ea50 0641 orrs.w r6, r0, r1, lsl #1 80087a0: bf18 it ne 80087a2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80087a6: d1d1 bne.n 800874c <__aeabi_dmul+0x19c> 80087a8: ea81 0103 eor.w r1, r1, r3 80087ac: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087b0: f04f 0000 mov.w r0, #0 80087b4: bd70 pop {r4, r5, r6, pc} 80087b6: ea50 0641 orrs.w r6, r0, r1, lsl #1 80087ba: bf06 itte eq 80087bc: 4610 moveq r0, r2 80087be: 4619 moveq r1, r3 80087c0: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80087c4: d019 beq.n 80087fa <__aeabi_dmul+0x24a> 80087c6: ea94 0f0c teq r4, ip 80087ca: d102 bne.n 80087d2 <__aeabi_dmul+0x222> 80087cc: ea50 3601 orrs.w r6, r0, r1, lsl #12 80087d0: d113 bne.n 80087fa <__aeabi_dmul+0x24a> 80087d2: ea95 0f0c teq r5, ip 80087d6: d105 bne.n 80087e4 <__aeabi_dmul+0x234> 80087d8: ea52 3603 orrs.w r6, r2, r3, lsl #12 80087dc: bf1c itt ne 80087de: 4610 movne r0, r2 80087e0: 4619 movne r1, r3 80087e2: d10a bne.n 80087fa <__aeabi_dmul+0x24a> 80087e4: ea81 0103 eor.w r1, r1, r3 80087e8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087ec: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087f0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 80087f4: f04f 0000 mov.w r0, #0 80087f8: bd70 pop {r4, r5, r6, pc} 80087fa: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087fe: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000 8008802: bd70 pop {r4, r5, r6, pc} 08008804 <__aeabi_ddiv>: 8008804: b570 push {r4, r5, r6, lr} 8008806: f04f 0cff mov.w ip, #255 @ 0xff 800880a: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 800880e: ea1c 5411 ands.w r4, ip, r1, lsr #20 8008812: bf1d ittte ne 8008814: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8008818: ea94 0f0c teqne r4, ip 800881c: ea95 0f0c teqne r5, ip 8008820: f000 f8a7 bleq 8008972 <__aeabi_ddiv+0x16e> 8008824: eba4 0405 sub.w r4, r4, r5 8008828: ea81 0e03 eor.w lr, r1, r3 800882c: ea52 3503 orrs.w r5, r2, r3, lsl #12 8008830: ea4f 3101 mov.w r1, r1, lsl #12 8008834: f000 8088 beq.w 8008948 <__aeabi_ddiv+0x144> 8008838: ea4f 3303 mov.w r3, r3, lsl #12 800883c: f04f 5580 mov.w r5, #268435456 @ 0x10000000 8008840: ea45 1313 orr.w r3, r5, r3, lsr #4 8008844: ea43 6312 orr.w r3, r3, r2, lsr #24 8008848: ea4f 2202 mov.w r2, r2, lsl #8 800884c: ea45 1511 orr.w r5, r5, r1, lsr #4 8008850: ea45 6510 orr.w r5, r5, r0, lsr #24 8008854: ea4f 2600 mov.w r6, r0, lsl #8 8008858: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000 800885c: 429d cmp r5, r3 800885e: bf08 it eq 8008860: 4296 cmpeq r6, r2 8008862: f144 04fd adc.w r4, r4, #253 @ 0xfd 8008866: f504 7440 add.w r4, r4, #768 @ 0x300 800886a: d202 bcs.n 8008872 <__aeabi_ddiv+0x6e> 800886c: 085b lsrs r3, r3, #1 800886e: ea4f 0232 mov.w r2, r2, rrx 8008872: 1ab6 subs r6, r6, r2 8008874: eb65 0503 sbc.w r5, r5, r3 8008878: 085b lsrs r3, r3, #1 800887a: ea4f 0232 mov.w r2, r2, rrx 800887e: f44f 1080 mov.w r0, #1048576 @ 0x100000 8008882: f44f 2c00 mov.w ip, #524288 @ 0x80000 8008886: ebb6 0e02 subs.w lr, r6, r2 800888a: eb75 0e03 sbcs.w lr, r5, r3 800888e: bf22 ittt cs 8008890: 1ab6 subcs r6, r6, r2 8008892: 4675 movcs r5, lr 8008894: ea40 000c orrcs.w r0, r0, ip 8008898: 085b lsrs r3, r3, #1 800889a: ea4f 0232 mov.w r2, r2, rrx 800889e: ebb6 0e02 subs.w lr, r6, r2 80088a2: eb75 0e03 sbcs.w lr, r5, r3 80088a6: bf22 ittt cs 80088a8: 1ab6 subcs r6, r6, r2 80088aa: 4675 movcs r5, lr 80088ac: ea40 005c orrcs.w r0, r0, ip, lsr #1 80088b0: 085b lsrs r3, r3, #1 80088b2: ea4f 0232 mov.w r2, r2, rrx 80088b6: ebb6 0e02 subs.w lr, r6, r2 80088ba: eb75 0e03 sbcs.w lr, r5, r3 80088be: bf22 ittt cs 80088c0: 1ab6 subcs r6, r6, r2 80088c2: 4675 movcs r5, lr 80088c4: ea40 009c orrcs.w r0, r0, ip, lsr #2 80088c8: 085b lsrs r3, r3, #1 80088ca: ea4f 0232 mov.w r2, r2, rrx 80088ce: ebb6 0e02 subs.w lr, r6, r2 80088d2: eb75 0e03 sbcs.w lr, r5, r3 80088d6: bf22 ittt cs 80088d8: 1ab6 subcs r6, r6, r2 80088da: 4675 movcs r5, lr 80088dc: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80088e0: ea55 0e06 orrs.w lr, r5, r6 80088e4: d018 beq.n 8008918 <__aeabi_ddiv+0x114> 80088e6: ea4f 1505 mov.w r5, r5, lsl #4 80088ea: ea45 7516 orr.w r5, r5, r6, lsr #28 80088ee: ea4f 1606 mov.w r6, r6, lsl #4 80088f2: ea4f 03c3 mov.w r3, r3, lsl #3 80088f6: ea43 7352 orr.w r3, r3, r2, lsr #29 80088fa: ea4f 02c2 mov.w r2, r2, lsl #3 80088fe: ea5f 1c1c movs.w ip, ip, lsr #4 8008902: d1c0 bne.n 8008886 <__aeabi_ddiv+0x82> 8008904: f411 1f80 tst.w r1, #1048576 @ 0x100000 8008908: d10b bne.n 8008922 <__aeabi_ddiv+0x11e> 800890a: ea41 0100 orr.w r1, r1, r0 800890e: f04f 0000 mov.w r0, #0 8008912: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000 8008916: e7b6 b.n 8008886 <__aeabi_ddiv+0x82> 8008918: f411 1f80 tst.w r1, #1048576 @ 0x100000 800891c: bf04 itt eq 800891e: 4301 orreq r1, r0 8008920: 2000 moveq r0, #0 8008922: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008926: bf88 it hi 8008928: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800892c: f63f aeaf bhi.w 800868e <__aeabi_dmul+0xde> 8008930: ebb5 0c03 subs.w ip, r5, r3 8008934: bf04 itt eq 8008936: ebb6 0c02 subseq.w ip, r6, r2 800893a: ea5f 0c50 movseq.w ip, r0, lsr #1 800893e: f150 0000 adcs.w r0, r0, #0 8008942: eb41 5104 adc.w r1, r1, r4, lsl #20 8008946: bd70 pop {r4, r5, r6, pc} 8008948: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000 800894c: ea4e 3111 orr.w r1, lr, r1, lsr #12 8008950: eb14 045c adds.w r4, r4, ip, lsr #1 8008954: bfc2 ittt gt 8008956: ebd4 050c rsbsgt r5, r4, ip 800895a: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800895e: bd70 popgt {r4, r5, r6, pc} 8008960: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008964: f04f 0e00 mov.w lr, #0 8008968: 3c01 subs r4, #1 800896a: e690 b.n 800868e <__aeabi_dmul+0xde> 800896c: ea45 0e06 orr.w lr, r5, r6 8008970: e68d b.n 800868e <__aeabi_dmul+0xde> 8008972: ea0c 5513 and.w r5, ip, r3, lsr #20 8008976: ea94 0f0c teq r4, ip 800897a: bf08 it eq 800897c: ea95 0f0c teqeq r5, ip 8008980: f43f af3b beq.w 80087fa <__aeabi_dmul+0x24a> 8008984: ea94 0f0c teq r4, ip 8008988: d10a bne.n 80089a0 <__aeabi_ddiv+0x19c> 800898a: ea50 3401 orrs.w r4, r0, r1, lsl #12 800898e: f47f af34 bne.w 80087fa <__aeabi_dmul+0x24a> 8008992: ea95 0f0c teq r5, ip 8008996: f47f af25 bne.w 80087e4 <__aeabi_dmul+0x234> 800899a: 4610 mov r0, r2 800899c: 4619 mov r1, r3 800899e: e72c b.n 80087fa <__aeabi_dmul+0x24a> 80089a0: ea95 0f0c teq r5, ip 80089a4: d106 bne.n 80089b4 <__aeabi_ddiv+0x1b0> 80089a6: ea52 3503 orrs.w r5, r2, r3, lsl #12 80089aa: f43f aefd beq.w 80087a8 <__aeabi_dmul+0x1f8> 80089ae: 4610 mov r0, r2 80089b0: 4619 mov r1, r3 80089b2: e722 b.n 80087fa <__aeabi_dmul+0x24a> 80089b4: ea50 0641 orrs.w r6, r0, r1, lsl #1 80089b8: bf18 it ne 80089ba: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80089be: f47f aec5 bne.w 800874c <__aeabi_dmul+0x19c> 80089c2: ea50 0441 orrs.w r4, r0, r1, lsl #1 80089c6: f47f af0d bne.w 80087e4 <__aeabi_dmul+0x234> 80089ca: ea52 0543 orrs.w r5, r2, r3, lsl #1 80089ce: f47f aeeb bne.w 80087a8 <__aeabi_dmul+0x1f8> 80089d2: e712 b.n 80087fa <__aeabi_dmul+0x24a> 080089d4 <__gedf2>: 80089d4: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80089d8: e006 b.n 80089e8 <__cmpdf2+0x4> 80089da: bf00 nop 080089dc <__ledf2>: 80089dc: f04f 0c01 mov.w ip, #1 80089e0: e002 b.n 80089e8 <__cmpdf2+0x4> 80089e2: bf00 nop 080089e4 <__cmpdf2>: 80089e4: f04f 0c01 mov.w ip, #1 80089e8: f84d cd04 str.w ip, [sp, #-4]! 80089ec: ea4f 0c41 mov.w ip, r1, lsl #1 80089f0: ea7f 5c6c mvns.w ip, ip, asr #21 80089f4: ea4f 0c43 mov.w ip, r3, lsl #1 80089f8: bf18 it ne 80089fa: ea7f 5c6c mvnsne.w ip, ip, asr #21 80089fe: d01b beq.n 8008a38 <__cmpdf2+0x54> 8008a00: b001 add sp, #4 8008a02: ea50 0c41 orrs.w ip, r0, r1, lsl #1 8008a06: bf0c ite eq 8008a08: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 8008a0c: ea91 0f03 teqne r1, r3 8008a10: bf02 ittt eq 8008a12: ea90 0f02 teqeq r0, r2 8008a16: 2000 moveq r0, #0 8008a18: 4770 bxeq lr 8008a1a: f110 0f00 cmn.w r0, #0 8008a1e: ea91 0f03 teq r1, r3 8008a22: bf58 it pl 8008a24: 4299 cmppl r1, r3 8008a26: bf08 it eq 8008a28: 4290 cmpeq r0, r2 8008a2a: bf2c ite cs 8008a2c: 17d8 asrcs r0, r3, #31 8008a2e: ea6f 70e3 mvncc.w r0, r3, asr #31 8008a32: f040 0001 orr.w r0, r0, #1 8008a36: 4770 bx lr 8008a38: ea4f 0c41 mov.w ip, r1, lsl #1 8008a3c: ea7f 5c6c mvns.w ip, ip, asr #21 8008a40: d102 bne.n 8008a48 <__cmpdf2+0x64> 8008a42: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8008a46: d107 bne.n 8008a58 <__cmpdf2+0x74> 8008a48: ea4f 0c43 mov.w ip, r3, lsl #1 8008a4c: ea7f 5c6c mvns.w ip, ip, asr #21 8008a50: d1d6 bne.n 8008a00 <__cmpdf2+0x1c> 8008a52: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8008a56: d0d3 beq.n 8008a00 <__cmpdf2+0x1c> 8008a58: f85d 0b04 ldr.w r0, [sp], #4 8008a5c: 4770 bx lr 8008a5e: bf00 nop 08008a60 <__aeabi_cdrcmple>: 8008a60: 4684 mov ip, r0 8008a62: 4610 mov r0, r2 8008a64: 4662 mov r2, ip 8008a66: 468c mov ip, r1 8008a68: 4619 mov r1, r3 8008a6a: 4663 mov r3, ip 8008a6c: e000 b.n 8008a70 <__aeabi_cdcmpeq> 8008a6e: bf00 nop 08008a70 <__aeabi_cdcmpeq>: 8008a70: b501 push {r0, lr} 8008a72: f7ff ffb7 bl 80089e4 <__cmpdf2> 8008a76: 2800 cmp r0, #0 8008a78: bf48 it mi 8008a7a: f110 0f00 cmnmi.w r0, #0 8008a7e: bd01 pop {r0, pc} 08008a80 <__aeabi_dcmpeq>: 8008a80: f84d ed08 str.w lr, [sp, #-8]! 8008a84: f7ff fff4 bl 8008a70 <__aeabi_cdcmpeq> 8008a88: bf0c ite eq 8008a8a: 2001 moveq r0, #1 8008a8c: 2000 movne r0, #0 8008a8e: f85d fb08 ldr.w pc, [sp], #8 8008a92: bf00 nop 08008a94 <__aeabi_dcmplt>: 8008a94: f84d ed08 str.w lr, [sp, #-8]! 8008a98: f7ff ffea bl 8008a70 <__aeabi_cdcmpeq> 8008a9c: bf34 ite cc 8008a9e: 2001 movcc r0, #1 8008aa0: 2000 movcs r0, #0 8008aa2: f85d fb08 ldr.w pc, [sp], #8 8008aa6: bf00 nop 08008aa8 <__aeabi_dcmple>: 8008aa8: f84d ed08 str.w lr, [sp, #-8]! 8008aac: f7ff ffe0 bl 8008a70 <__aeabi_cdcmpeq> 8008ab0: bf94 ite ls 8008ab2: 2001 movls r0, #1 8008ab4: 2000 movhi r0, #0 8008ab6: f85d fb08 ldr.w pc, [sp], #8 8008aba: bf00 nop 08008abc <__aeabi_dcmpge>: 8008abc: f84d ed08 str.w lr, [sp, #-8]! 8008ac0: f7ff ffce bl 8008a60 <__aeabi_cdrcmple> 8008ac4: bf94 ite ls 8008ac6: 2001 movls r0, #1 8008ac8: 2000 movhi r0, #0 8008aca: f85d fb08 ldr.w pc, [sp], #8 8008ace: bf00 nop 08008ad0 <__aeabi_dcmpgt>: 8008ad0: f84d ed08 str.w lr, [sp, #-8]! 8008ad4: f7ff ffc4 bl 8008a60 <__aeabi_cdrcmple> 8008ad8: bf34 ite cc 8008ada: 2001 movcc r0, #1 8008adc: 2000 movcs r0, #0 8008ade: f85d fb08 ldr.w pc, [sp], #8 8008ae2: bf00 nop 08008ae4 <__aeabi_dcmpun>: 8008ae4: ea4f 0c41 mov.w ip, r1, lsl #1 8008ae8: ea7f 5c6c mvns.w ip, ip, asr #21 8008aec: d102 bne.n 8008af4 <__aeabi_dcmpun+0x10> 8008aee: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8008af2: d10a bne.n 8008b0a <__aeabi_dcmpun+0x26> 8008af4: ea4f 0c43 mov.w ip, r3, lsl #1 8008af8: ea7f 5c6c mvns.w ip, ip, asr #21 8008afc: d102 bne.n 8008b04 <__aeabi_dcmpun+0x20> 8008afe: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8008b02: d102 bne.n 8008b0a <__aeabi_dcmpun+0x26> 8008b04: f04f 0000 mov.w r0, #0 8008b08: 4770 bx lr 8008b0a: f04f 0001 mov.w r0, #1 8008b0e: 4770 bx lr 08008b10 <__aeabi_d2iz>: 8008b10: ea4f 0241 mov.w r2, r1, lsl #1 8008b14: f512 1200 adds.w r2, r2, #2097152 @ 0x200000 8008b18: d215 bcs.n 8008b46 <__aeabi_d2iz+0x36> 8008b1a: d511 bpl.n 8008b40 <__aeabi_d2iz+0x30> 8008b1c: f46f 7378 mvn.w r3, #992 @ 0x3e0 8008b20: ebb3 5262 subs.w r2, r3, r2, asr #21 8008b24: d912 bls.n 8008b4c <__aeabi_d2iz+0x3c> 8008b26: ea4f 23c1 mov.w r3, r1, lsl #11 8008b2a: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8008b2e: ea43 5350 orr.w r3, r3, r0, lsr #21 8008b32: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008b36: fa23 f002 lsr.w r0, r3, r2 8008b3a: bf18 it ne 8008b3c: 4240 negne r0, r0 8008b3e: 4770 bx lr 8008b40: f04f 0000 mov.w r0, #0 8008b44: 4770 bx lr 8008b46: ea50 3001 orrs.w r0, r0, r1, lsl #12 8008b4a: d105 bne.n 8008b58 <__aeabi_d2iz+0x48> 8008b4c: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000 8008b50: bf08 it eq 8008b52: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 8008b56: 4770 bx lr 8008b58: f04f 0000 mov.w r0, #0 8008b5c: 4770 bx lr 8008b5e: bf00 nop 08008b60 <__aeabi_d2f>: 8008b60: ea4f 0241 mov.w r2, r1, lsl #1 8008b64: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000 8008b68: bf24 itt cs 8008b6a: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000 8008b6e: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000 8008b72: d90d bls.n 8008b90 <__aeabi_d2f+0x30> 8008b74: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008b78: ea4f 02c0 mov.w r2, r0, lsl #3 8008b7c: ea4c 7050 orr.w r0, ip, r0, lsr #29 8008b80: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000 8008b84: eb40 0083 adc.w r0, r0, r3, lsl #2 8008b88: bf08 it eq 8008b8a: f020 0001 biceq.w r0, r0, #1 8008b8e: 4770 bx lr 8008b90: f011 4f80 tst.w r1, #1073741824 @ 0x40000000 8008b94: d121 bne.n 8008bda <__aeabi_d2f+0x7a> 8008b96: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000 8008b9a: bfbc itt lt 8008b9c: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000 8008ba0: 4770 bxlt lr 8008ba2: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008ba6: ea4f 5252 mov.w r2, r2, lsr #21 8008baa: f1c2 0218 rsb r2, r2, #24 8008bae: f1c2 0c20 rsb ip, r2, #32 8008bb2: fa10 f30c lsls.w r3, r0, ip 8008bb6: fa20 f002 lsr.w r0, r0, r2 8008bba: bf18 it ne 8008bbc: f040 0001 orrne.w r0, r0, #1 8008bc0: ea4f 23c1 mov.w r3, r1, lsl #11 8008bc4: ea4f 23d3 mov.w r3, r3, lsr #11 8008bc8: fa03 fc0c lsl.w ip, r3, ip 8008bcc: ea40 000c orr.w r0, r0, ip 8008bd0: fa23 f302 lsr.w r3, r3, r2 8008bd4: ea4f 0343 mov.w r3, r3, lsl #1 8008bd8: e7cc b.n 8008b74 <__aeabi_d2f+0x14> 8008bda: ea7f 5362 mvns.w r3, r2, asr #21 8008bde: d107 bne.n 8008bf0 <__aeabi_d2f+0x90> 8008be0: ea50 3301 orrs.w r3, r0, r1, lsl #12 8008be4: bf1e ittt ne 8008be6: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000 8008bea: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000 8008bee: 4770 bxne lr 8008bf0: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000 8008bf4: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008bf8: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008bfc: 4770 bx lr 8008bfe: bf00 nop 08008c00 <__aeabi_frsub>: 8008c00: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000 8008c04: e002 b.n 8008c0c <__addsf3> 8008c06: bf00 nop 08008c08 <__aeabi_fsub>: 8008c08: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 08008c0c <__addsf3>: 8008c0c: 0042 lsls r2, r0, #1 8008c0e: bf1f itttt ne 8008c10: ea5f 0341 movsne.w r3, r1, lsl #1 8008c14: ea92 0f03 teqne r2, r3 8008c18: ea7f 6c22 mvnsne.w ip, r2, asr #24 8008c1c: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008c20: d06a beq.n 8008cf8 <__addsf3+0xec> 8008c22: ea4f 6212 mov.w r2, r2, lsr #24 8008c26: ebd2 6313 rsbs r3, r2, r3, lsr #24 8008c2a: bfc1 itttt gt 8008c2c: 18d2 addgt r2, r2, r3 8008c2e: 4041 eorgt r1, r0 8008c30: 4048 eorgt r0, r1 8008c32: 4041 eorgt r1, r0 8008c34: bfb8 it lt 8008c36: 425b neglt r3, r3 8008c38: 2b19 cmp r3, #25 8008c3a: bf88 it hi 8008c3c: 4770 bxhi lr 8008c3e: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 8008c42: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008c46: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000 8008c4a: bf18 it ne 8008c4c: 4240 negne r0, r0 8008c4e: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008c52: f441 0100 orr.w r1, r1, #8388608 @ 0x800000 8008c56: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000 8008c5a: bf18 it ne 8008c5c: 4249 negne r1, r1 8008c5e: ea92 0f03 teq r2, r3 8008c62: d03f beq.n 8008ce4 <__addsf3+0xd8> 8008c64: f1a2 0201 sub.w r2, r2, #1 8008c68: fa41 fc03 asr.w ip, r1, r3 8008c6c: eb10 000c adds.w r0, r0, ip 8008c70: f1c3 0320 rsb r3, r3, #32 8008c74: fa01 f103 lsl.w r1, r1, r3 8008c78: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008c7c: d502 bpl.n 8008c84 <__addsf3+0x78> 8008c7e: 4249 negs r1, r1 8008c80: eb60 0040 sbc.w r0, r0, r0, lsl #1 8008c84: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000 8008c88: d313 bcc.n 8008cb2 <__addsf3+0xa6> 8008c8a: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000 8008c8e: d306 bcc.n 8008c9e <__addsf3+0x92> 8008c90: 0840 lsrs r0, r0, #1 8008c92: ea4f 0131 mov.w r1, r1, rrx 8008c96: f102 0201 add.w r2, r2, #1 8008c9a: 2afe cmp r2, #254 @ 0xfe 8008c9c: d251 bcs.n 8008d42 <__addsf3+0x136> 8008c9e: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000 8008ca2: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008ca6: bf08 it eq 8008ca8: f020 0001 biceq.w r0, r0, #1 8008cac: ea40 0003 orr.w r0, r0, r3 8008cb0: 4770 bx lr 8008cb2: 0049 lsls r1, r1, #1 8008cb4: eb40 0000 adc.w r0, r0, r0 8008cb8: 3a01 subs r2, #1 8008cba: bf28 it cs 8008cbc: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000 8008cc0: d2ed bcs.n 8008c9e <__addsf3+0x92> 8008cc2: fab0 fc80 clz ip, r0 8008cc6: f1ac 0c08 sub.w ip, ip, #8 8008cca: ebb2 020c subs.w r2, r2, ip 8008cce: fa00 f00c lsl.w r0, r0, ip 8008cd2: bfaa itet ge 8008cd4: eb00 50c2 addge.w r0, r0, r2, lsl #23 8008cd8: 4252 neglt r2, r2 8008cda: 4318 orrge r0, r3 8008cdc: bfbc itt lt 8008cde: 40d0 lsrlt r0, r2 8008ce0: 4318 orrlt r0, r3 8008ce2: 4770 bx lr 8008ce4: f092 0f00 teq r2, #0 8008ce8: f481 0100 eor.w r1, r1, #8388608 @ 0x800000 8008cec: bf06 itte eq 8008cee: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000 8008cf2: 3201 addeq r2, #1 8008cf4: 3b01 subne r3, #1 8008cf6: e7b5 b.n 8008c64 <__addsf3+0x58> 8008cf8: ea4f 0341 mov.w r3, r1, lsl #1 8008cfc: ea7f 6c22 mvns.w ip, r2, asr #24 8008d00: bf18 it ne 8008d02: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008d06: d021 beq.n 8008d4c <__addsf3+0x140> 8008d08: ea92 0f03 teq r2, r3 8008d0c: d004 beq.n 8008d18 <__addsf3+0x10c> 8008d0e: f092 0f00 teq r2, #0 8008d12: bf08 it eq 8008d14: 4608 moveq r0, r1 8008d16: 4770 bx lr 8008d18: ea90 0f01 teq r0, r1 8008d1c: bf1c itt ne 8008d1e: 2000 movne r0, #0 8008d20: 4770 bxne lr 8008d22: f012 4f7f tst.w r2, #4278190080 @ 0xff000000 8008d26: d104 bne.n 8008d32 <__addsf3+0x126> 8008d28: 0040 lsls r0, r0, #1 8008d2a: bf28 it cs 8008d2c: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000 8008d30: 4770 bx lr 8008d32: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000 8008d36: bf3c itt cc 8008d38: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000 8008d3c: 4770 bxcc lr 8008d3e: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008d42: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000 8008d46: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008d4a: 4770 bx lr 8008d4c: ea7f 6222 mvns.w r2, r2, asr #24 8008d50: bf16 itet ne 8008d52: 4608 movne r0, r1 8008d54: ea7f 6323 mvnseq.w r3, r3, asr #24 8008d58: 4601 movne r1, r0 8008d5a: 0242 lsls r2, r0, #9 8008d5c: bf06 itte eq 8008d5e: ea5f 2341 movseq.w r3, r1, lsl #9 8008d62: ea90 0f01 teqeq r0, r1 8008d66: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000 8008d6a: 4770 bx lr 08008d6c <__aeabi_ui2f>: 8008d6c: f04f 0300 mov.w r3, #0 8008d70: e004 b.n 8008d7c <__aeabi_i2f+0x8> 8008d72: bf00 nop 08008d74 <__aeabi_i2f>: 8008d74: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000 8008d78: bf48 it mi 8008d7a: 4240 negmi r0, r0 8008d7c: ea5f 0c00 movs.w ip, r0 8008d80: bf08 it eq 8008d82: 4770 bxeq lr 8008d84: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000 8008d88: 4601 mov r1, r0 8008d8a: f04f 0000 mov.w r0, #0 8008d8e: e01c b.n 8008dca <__aeabi_l2f+0x2a> 08008d90 <__aeabi_ul2f>: 8008d90: ea50 0201 orrs.w r2, r0, r1 8008d94: bf08 it eq 8008d96: 4770 bxeq lr 8008d98: f04f 0300 mov.w r3, #0 8008d9c: e00a b.n 8008db4 <__aeabi_l2f+0x14> 8008d9e: bf00 nop 08008da0 <__aeabi_l2f>: 8008da0: ea50 0201 orrs.w r2, r0, r1 8008da4: bf08 it eq 8008da6: 4770 bxeq lr 8008da8: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000 8008dac: d502 bpl.n 8008db4 <__aeabi_l2f+0x14> 8008dae: 4240 negs r0, r0 8008db0: eb61 0141 sbc.w r1, r1, r1, lsl #1 8008db4: ea5f 0c01 movs.w ip, r1 8008db8: bf02 ittt eq 8008dba: 4684 moveq ip, r0 8008dbc: 4601 moveq r1, r0 8008dbe: 2000 moveq r0, #0 8008dc0: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000 8008dc4: bf08 it eq 8008dc6: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000 8008dca: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 8008dce: fabc f28c clz r2, ip 8008dd2: 3a08 subs r2, #8 8008dd4: eba3 53c2 sub.w r3, r3, r2, lsl #23 8008dd8: db10 blt.n 8008dfc <__aeabi_l2f+0x5c> 8008dda: fa01 fc02 lsl.w ip, r1, r2 8008dde: 4463 add r3, ip 8008de0: fa00 fc02 lsl.w ip, r0, r2 8008de4: f1c2 0220 rsb r2, r2, #32 8008de8: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008dec: fa20 f202 lsr.w r2, r0, r2 8008df0: eb43 0002 adc.w r0, r3, r2 8008df4: bf08 it eq 8008df6: f020 0001 biceq.w r0, r0, #1 8008dfa: 4770 bx lr 8008dfc: f102 0220 add.w r2, r2, #32 8008e00: fa01 fc02 lsl.w ip, r1, r2 8008e04: f1c2 0220 rsb r2, r2, #32 8008e08: ea50 004c orrs.w r0, r0, ip, lsl #1 8008e0c: fa21 f202 lsr.w r2, r1, r2 8008e10: eb43 0002 adc.w r0, r3, r2 8008e14: bf08 it eq 8008e16: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008e1a: 4770 bx lr 08008e1c <__aeabi_fmul>: 8008e1c: f04f 0cff mov.w ip, #255 @ 0xff 8008e20: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008e24: bf1e ittt ne 8008e26: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008e2a: ea92 0f0c teqne r2, ip 8008e2e: ea93 0f0c teqne r3, ip 8008e32: d06f beq.n 8008f14 <__aeabi_fmul+0xf8> 8008e34: 441a add r2, r3 8008e36: ea80 0c01 eor.w ip, r0, r1 8008e3a: 0240 lsls r0, r0, #9 8008e3c: bf18 it ne 8008e3e: ea5f 2141 movsne.w r1, r1, lsl #9 8008e42: d01e beq.n 8008e82 <__aeabi_fmul+0x66> 8008e44: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8008e48: ea43 1050 orr.w r0, r3, r0, lsr #5 8008e4c: ea43 1151 orr.w r1, r3, r1, lsr #5 8008e50: fba0 3101 umull r3, r1, r0, r1 8008e54: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008e58: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000 8008e5c: bf3e ittt cc 8008e5e: 0049 lslcc r1, r1, #1 8008e60: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 8008e64: 005b lslcc r3, r3, #1 8008e66: ea40 0001 orr.w r0, r0, r1 8008e6a: f162 027f sbc.w r2, r2, #127 @ 0x7f 8008e6e: 2afd cmp r2, #253 @ 0xfd 8008e70: d81d bhi.n 8008eae <__aeabi_fmul+0x92> 8008e72: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008e76: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008e7a: bf08 it eq 8008e7c: f020 0001 biceq.w r0, r0, #1 8008e80: 4770 bx lr 8008e82: f090 0f00 teq r0, #0 8008e86: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8008e8a: bf08 it eq 8008e8c: 0249 lsleq r1, r1, #9 8008e8e: ea4c 2050 orr.w r0, ip, r0, lsr #9 8008e92: ea40 2051 orr.w r0, r0, r1, lsr #9 8008e96: 3a7f subs r2, #127 @ 0x7f 8008e98: bfc2 ittt gt 8008e9a: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 8008e9e: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8008ea2: 4770 bxgt lr 8008ea4: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008ea8: f04f 0300 mov.w r3, #0 8008eac: 3a01 subs r2, #1 8008eae: dc5d bgt.n 8008f6c <__aeabi_fmul+0x150> 8008eb0: f112 0f19 cmn.w r2, #25 8008eb4: bfdc itt le 8008eb6: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000 8008eba: 4770 bxle lr 8008ebc: f1c2 0200 rsb r2, r2, #0 8008ec0: 0041 lsls r1, r0, #1 8008ec2: fa21 f102 lsr.w r1, r1, r2 8008ec6: f1c2 0220 rsb r2, r2, #32 8008eca: fa00 fc02 lsl.w ip, r0, r2 8008ece: ea5f 0031 movs.w r0, r1, rrx 8008ed2: f140 0000 adc.w r0, r0, #0 8008ed6: ea53 034c orrs.w r3, r3, ip, lsl #1 8008eda: bf08 it eq 8008edc: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008ee0: 4770 bx lr 8008ee2: f092 0f00 teq r2, #0 8008ee6: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8008eea: bf02 ittt eq 8008eec: 0040 lsleq r0, r0, #1 8008eee: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 8008ef2: 3a01 subeq r2, #1 8008ef4: d0f9 beq.n 8008eea <__aeabi_fmul+0xce> 8008ef6: ea40 000c orr.w r0, r0, ip 8008efa: f093 0f00 teq r3, #0 8008efe: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008f02: bf02 ittt eq 8008f04: 0049 lsleq r1, r1, #1 8008f06: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8008f0a: 3b01 subeq r3, #1 8008f0c: d0f9 beq.n 8008f02 <__aeabi_fmul+0xe6> 8008f0e: ea41 010c orr.w r1, r1, ip 8008f12: e78f b.n 8008e34 <__aeabi_fmul+0x18> 8008f14: ea0c 53d1 and.w r3, ip, r1, lsr #23 8008f18: ea92 0f0c teq r2, ip 8008f1c: bf18 it ne 8008f1e: ea93 0f0c teqne r3, ip 8008f22: d00a beq.n 8008f3a <__aeabi_fmul+0x11e> 8008f24: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 8008f28: bf18 it ne 8008f2a: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 8008f2e: d1d8 bne.n 8008ee2 <__aeabi_fmul+0xc6> 8008f30: ea80 0001 eor.w r0, r0, r1 8008f34: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008f38: 4770 bx lr 8008f3a: f090 0f00 teq r0, #0 8008f3e: bf17 itett ne 8008f40: f090 4f00 teqne r0, #2147483648 @ 0x80000000 8008f44: 4608 moveq r0, r1 8008f46: f091 0f00 teqne r1, #0 8008f4a: f091 4f00 teqne r1, #2147483648 @ 0x80000000 8008f4e: d014 beq.n 8008f7a <__aeabi_fmul+0x15e> 8008f50: ea92 0f0c teq r2, ip 8008f54: d101 bne.n 8008f5a <__aeabi_fmul+0x13e> 8008f56: 0242 lsls r2, r0, #9 8008f58: d10f bne.n 8008f7a <__aeabi_fmul+0x15e> 8008f5a: ea93 0f0c teq r3, ip 8008f5e: d103 bne.n 8008f68 <__aeabi_fmul+0x14c> 8008f60: 024b lsls r3, r1, #9 8008f62: bf18 it ne 8008f64: 4608 movne r0, r1 8008f66: d108 bne.n 8008f7a <__aeabi_fmul+0x15e> 8008f68: ea80 0001 eor.w r0, r0, r1 8008f6c: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008f70: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008f74: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008f78: 4770 bx lr 8008f7a: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008f7e: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000 8008f82: 4770 bx lr 08008f84 <__aeabi_fdiv>: 8008f84: f04f 0cff mov.w ip, #255 @ 0xff 8008f88: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008f8c: bf1e ittt ne 8008f8e: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008f92: ea92 0f0c teqne r2, ip 8008f96: ea93 0f0c teqne r3, ip 8008f9a: d069 beq.n 8009070 <__aeabi_fdiv+0xec> 8008f9c: eba2 0203 sub.w r2, r2, r3 8008fa0: ea80 0c01 eor.w ip, r0, r1 8008fa4: 0249 lsls r1, r1, #9 8008fa6: ea4f 2040 mov.w r0, r0, lsl #9 8008faa: d037 beq.n 800901c <__aeabi_fdiv+0x98> 8008fac: f04f 5380 mov.w r3, #268435456 @ 0x10000000 8008fb0: ea43 1111 orr.w r1, r3, r1, lsr #4 8008fb4: ea43 1310 orr.w r3, r3, r0, lsr #4 8008fb8: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008fbc: 428b cmp r3, r1 8008fbe: bf38 it cc 8008fc0: 005b lslcc r3, r3, #1 8008fc2: f142 027d adc.w r2, r2, #125 @ 0x7d 8008fc6: f44f 0c00 mov.w ip, #8388608 @ 0x800000 8008fca: 428b cmp r3, r1 8008fcc: bf24 itt cs 8008fce: 1a5b subcs r3, r3, r1 8008fd0: ea40 000c orrcs.w r0, r0, ip 8008fd4: ebb3 0f51 cmp.w r3, r1, lsr #1 8008fd8: bf24 itt cs 8008fda: eba3 0351 subcs.w r3, r3, r1, lsr #1 8008fde: ea40 005c orrcs.w r0, r0, ip, lsr #1 8008fe2: ebb3 0f91 cmp.w r3, r1, lsr #2 8008fe6: bf24 itt cs 8008fe8: eba3 0391 subcs.w r3, r3, r1, lsr #2 8008fec: ea40 009c orrcs.w r0, r0, ip, lsr #2 8008ff0: ebb3 0fd1 cmp.w r3, r1, lsr #3 8008ff4: bf24 itt cs 8008ff6: eba3 03d1 subcs.w r3, r3, r1, lsr #3 8008ffa: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8008ffe: 011b lsls r3, r3, #4 8009000: bf18 it ne 8009002: ea5f 1c1c movsne.w ip, ip, lsr #4 8009006: d1e0 bne.n 8008fca <__aeabi_fdiv+0x46> 8009008: 2afd cmp r2, #253 @ 0xfd 800900a: f63f af50 bhi.w 8008eae <__aeabi_fmul+0x92> 800900e: 428b cmp r3, r1 8009010: eb40 50c2 adc.w r0, r0, r2, lsl #23 8009014: bf08 it eq 8009016: f020 0001 biceq.w r0, r0, #1 800901a: 4770 bx lr 800901c: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8009020: ea4c 2050 orr.w r0, ip, r0, lsr #9 8009024: 327f adds r2, #127 @ 0x7f 8009026: bfc2 ittt gt 8009028: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 800902c: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8009030: 4770 bxgt lr 8009032: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8009036: f04f 0300 mov.w r3, #0 800903a: 3a01 subs r2, #1 800903c: e737 b.n 8008eae <__aeabi_fmul+0x92> 800903e: f092 0f00 teq r2, #0 8009042: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8009046: bf02 ittt eq 8009048: 0040 lsleq r0, r0, #1 800904a: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 800904e: 3a01 subeq r2, #1 8009050: d0f9 beq.n 8009046 <__aeabi_fdiv+0xc2> 8009052: ea40 000c orr.w r0, r0, ip 8009056: f093 0f00 teq r3, #0 800905a: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 800905e: bf02 ittt eq 8009060: 0049 lsleq r1, r1, #1 8009062: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8009066: 3b01 subeq r3, #1 8009068: d0f9 beq.n 800905e <__aeabi_fdiv+0xda> 800906a: ea41 010c orr.w r1, r1, ip 800906e: e795 b.n 8008f9c <__aeabi_fdiv+0x18> 8009070: ea0c 53d1 and.w r3, ip, r1, lsr #23 8009074: ea92 0f0c teq r2, ip 8009078: d108 bne.n 800908c <__aeabi_fdiv+0x108> 800907a: 0242 lsls r2, r0, #9 800907c: f47f af7d bne.w 8008f7a <__aeabi_fmul+0x15e> 8009080: ea93 0f0c teq r3, ip 8009084: f47f af70 bne.w 8008f68 <__aeabi_fmul+0x14c> 8009088: 4608 mov r0, r1 800908a: e776 b.n 8008f7a <__aeabi_fmul+0x15e> 800908c: ea93 0f0c teq r3, ip 8009090: d104 bne.n 800909c <__aeabi_fdiv+0x118> 8009092: 024b lsls r3, r1, #9 8009094: f43f af4c beq.w 8008f30 <__aeabi_fmul+0x114> 8009098: 4608 mov r0, r1 800909a: e76e b.n 8008f7a <__aeabi_fmul+0x15e> 800909c: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 80090a0: bf18 it ne 80090a2: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 80090a6: d1ca bne.n 800903e <__aeabi_fdiv+0xba> 80090a8: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000 80090ac: f47f af5c bne.w 8008f68 <__aeabi_fmul+0x14c> 80090b0: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000 80090b4: f47f af3c bne.w 8008f30 <__aeabi_fmul+0x114> 80090b8: e75f b.n 8008f7a <__aeabi_fmul+0x15e> 80090ba: bf00 nop 080090bc <__gesf2>: 80090bc: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80090c0: e006 b.n 80090d0 <__cmpsf2+0x4> 80090c2: bf00 nop 080090c4 <__lesf2>: 80090c4: f04f 0c01 mov.w ip, #1 80090c8: e002 b.n 80090d0 <__cmpsf2+0x4> 80090ca: bf00 nop 080090cc <__cmpsf2>: 80090cc: f04f 0c01 mov.w ip, #1 80090d0: f84d cd04 str.w ip, [sp, #-4]! 80090d4: ea4f 0240 mov.w r2, r0, lsl #1 80090d8: ea4f 0341 mov.w r3, r1, lsl #1 80090dc: ea7f 6c22 mvns.w ip, r2, asr #24 80090e0: bf18 it ne 80090e2: ea7f 6c23 mvnsne.w ip, r3, asr #24 80090e6: d011 beq.n 800910c <__cmpsf2+0x40> 80090e8: b001 add sp, #4 80090ea: ea52 0c53 orrs.w ip, r2, r3, lsr #1 80090ee: bf18 it ne 80090f0: ea90 0f01 teqne r0, r1 80090f4: bf58 it pl 80090f6: ebb2 0003 subspl.w r0, r2, r3 80090fa: bf88 it hi 80090fc: 17c8 asrhi r0, r1, #31 80090fe: bf38 it cc 8009100: ea6f 70e1 mvncc.w r0, r1, asr #31 8009104: bf18 it ne 8009106: f040 0001 orrne.w r0, r0, #1 800910a: 4770 bx lr 800910c: ea7f 6c22 mvns.w ip, r2, asr #24 8009110: d102 bne.n 8009118 <__cmpsf2+0x4c> 8009112: ea5f 2c40 movs.w ip, r0, lsl #9 8009116: d105 bne.n 8009124 <__cmpsf2+0x58> 8009118: ea7f 6c23 mvns.w ip, r3, asr #24 800911c: d1e4 bne.n 80090e8 <__cmpsf2+0x1c> 800911e: ea5f 2c41 movs.w ip, r1, lsl #9 8009122: d0e1 beq.n 80090e8 <__cmpsf2+0x1c> 8009124: f85d 0b04 ldr.w r0, [sp], #4 8009128: 4770 bx lr 800912a: bf00 nop 0800912c <__aeabi_cfrcmple>: 800912c: 4684 mov ip, r0 800912e: 4608 mov r0, r1 8009130: 4661 mov r1, ip 8009132: e7ff b.n 8009134 <__aeabi_cfcmpeq> 08009134 <__aeabi_cfcmpeq>: 8009134: b50f push {r0, r1, r2, r3, lr} 8009136: f7ff ffc9 bl 80090cc <__cmpsf2> 800913a: 2800 cmp r0, #0 800913c: bf48 it mi 800913e: f110 0f00 cmnmi.w r0, #0 8009142: bd0f pop {r0, r1, r2, r3, pc} 08009144 <__aeabi_fcmpeq>: 8009144: f84d ed08 str.w lr, [sp, #-8]! 8009148: f7ff fff4 bl 8009134 <__aeabi_cfcmpeq> 800914c: bf0c ite eq 800914e: 2001 moveq r0, #1 8009150: 2000 movne r0, #0 8009152: f85d fb08 ldr.w pc, [sp], #8 8009156: bf00 nop 08009158 <__aeabi_fcmplt>: 8009158: f84d ed08 str.w lr, [sp, #-8]! 800915c: f7ff ffea bl 8009134 <__aeabi_cfcmpeq> 8009160: bf34 ite cc 8009162: 2001 movcc r0, #1 8009164: 2000 movcs r0, #0 8009166: f85d fb08 ldr.w pc, [sp], #8 800916a: bf00 nop 0800916c <__aeabi_fcmple>: 800916c: f84d ed08 str.w lr, [sp, #-8]! 8009170: f7ff ffe0 bl 8009134 <__aeabi_cfcmpeq> 8009174: bf94 ite ls 8009176: 2001 movls r0, #1 8009178: 2000 movhi r0, #0 800917a: f85d fb08 ldr.w pc, [sp], #8 800917e: bf00 nop 08009180 <__aeabi_fcmpge>: 8009180: f84d ed08 str.w lr, [sp, #-8]! 8009184: f7ff ffd2 bl 800912c <__aeabi_cfrcmple> 8009188: bf94 ite ls 800918a: 2001 movls r0, #1 800918c: 2000 movhi r0, #0 800918e: f85d fb08 ldr.w pc, [sp], #8 8009192: bf00 nop 08009194 <__aeabi_fcmpgt>: 8009194: f84d ed08 str.w lr, [sp, #-8]! 8009198: f7ff ffc8 bl 800912c <__aeabi_cfrcmple> 800919c: bf34 ite cc 800919e: 2001 movcc r0, #1 80091a0: 2000 movcs r0, #0 80091a2: f85d fb08 ldr.w pc, [sp], #8 80091a6: bf00 nop 080091a8 <__aeabi_f2iz>: 80091a8: ea4f 0240 mov.w r2, r0, lsl #1 80091ac: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000 80091b0: d30f bcc.n 80091d2 <__aeabi_f2iz+0x2a> 80091b2: f04f 039e mov.w r3, #158 @ 0x9e 80091b6: ebb3 6212 subs.w r2, r3, r2, lsr #24 80091ba: d90d bls.n 80091d8 <__aeabi_f2iz+0x30> 80091bc: ea4f 2300 mov.w r3, r0, lsl #8 80091c0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80091c4: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 80091c8: fa23 f002 lsr.w r0, r3, r2 80091cc: bf18 it ne 80091ce: 4240 negne r0, r0 80091d0: 4770 bx lr 80091d2: f04f 0000 mov.w r0, #0 80091d6: 4770 bx lr 80091d8: f112 0f61 cmn.w r2, #97 @ 0x61 80091dc: d101 bne.n 80091e2 <__aeabi_f2iz+0x3a> 80091de: 0242 lsls r2, r0, #9 80091e0: d105 bne.n 80091ee <__aeabi_f2iz+0x46> 80091e2: f010 4000 ands.w r0, r0, #2147483648 @ 0x80000000 80091e6: bf08 it eq 80091e8: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 80091ec: 4770 bx lr 80091ee: f04f 0000 mov.w r0, #0 80091f2: 4770 bx lr 080091f4 <__aeabi_uldivmod>: 80091f4: b953 cbnz r3, 800920c <__aeabi_uldivmod+0x18> 80091f6: b94a cbnz r2, 800920c <__aeabi_uldivmod+0x18> 80091f8: 2900 cmp r1, #0 80091fa: bf08 it eq 80091fc: 2800 cmpeq r0, #0 80091fe: bf1c itt ne 8009200: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8009204: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8009208: f000 b98c b.w 8009524 <__aeabi_idiv0> 800920c: f1ad 0c08 sub.w ip, sp, #8 8009210: e96d ce04 strd ip, lr, [sp, #-16]! 8009214: f000 f806 bl 8009224 <__udivmoddi4> 8009218: f8dd e004 ldr.w lr, [sp, #4] 800921c: e9dd 2302 ldrd r2, r3, [sp, #8] 8009220: b004 add sp, #16 8009222: 4770 bx lr 08009224 <__udivmoddi4>: 8009224: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8009228: 9d08 ldr r5, [sp, #32] 800922a: 468e mov lr, r1 800922c: 4604 mov r4, r0 800922e: 4688 mov r8, r1 8009230: 2b00 cmp r3, #0 8009232: d14a bne.n 80092ca <__udivmoddi4+0xa6> 8009234: 428a cmp r2, r1 8009236: 4617 mov r7, r2 8009238: d962 bls.n 8009300 <__udivmoddi4+0xdc> 800923a: fab2 f682 clz r6, r2 800923e: b14e cbz r6, 8009254 <__udivmoddi4+0x30> 8009240: f1c6 0320 rsb r3, r6, #32 8009244: fa01 f806 lsl.w r8, r1, r6 8009248: fa20 f303 lsr.w r3, r0, r3 800924c: 40b7 lsls r7, r6 800924e: ea43 0808 orr.w r8, r3, r8 8009252: 40b4 lsls r4, r6 8009254: ea4f 4e17 mov.w lr, r7, lsr #16 8009258: fbb8 f1fe udiv r1, r8, lr 800925c: fa1f fc87 uxth.w ip, r7 8009260: fb0e 8811 mls r8, lr, r1, r8 8009264: fb01 f20c mul.w r2, r1, ip 8009268: 0c23 lsrs r3, r4, #16 800926a: ea43 4308 orr.w r3, r3, r8, lsl #16 800926e: 429a cmp r2, r3 8009270: d909 bls.n 8009286 <__udivmoddi4+0x62> 8009272: 18fb adds r3, r7, r3 8009274: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8009278: f080 80eb bcs.w 8009452 <__udivmoddi4+0x22e> 800927c: 429a cmp r2, r3 800927e: f240 80e8 bls.w 8009452 <__udivmoddi4+0x22e> 8009282: 3902 subs r1, #2 8009284: 443b add r3, r7 8009286: 1a9a subs r2, r3, r2 8009288: fbb2 f0fe udiv r0, r2, lr 800928c: fb0e 2210 mls r2, lr, r0, r2 8009290: fb00 fc0c mul.w ip, r0, ip 8009294: b2a3 uxth r3, r4 8009296: ea43 4302 orr.w r3, r3, r2, lsl #16 800929a: 459c cmp ip, r3 800929c: d909 bls.n 80092b2 <__udivmoddi4+0x8e> 800929e: 18fb adds r3, r7, r3 80092a0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80092a4: f080 80d7 bcs.w 8009456 <__udivmoddi4+0x232> 80092a8: 459c cmp ip, r3 80092aa: f240 80d4 bls.w 8009456 <__udivmoddi4+0x232> 80092ae: 443b add r3, r7 80092b0: 3802 subs r0, #2 80092b2: ea40 4001 orr.w r0, r0, r1, lsl #16 80092b6: 2100 movs r1, #0 80092b8: eba3 030c sub.w r3, r3, ip 80092bc: b11d cbz r5, 80092c6 <__udivmoddi4+0xa2> 80092be: 2200 movs r2, #0 80092c0: 40f3 lsrs r3, r6 80092c2: e9c5 3200 strd r3, r2, [r5] 80092c6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80092ca: 428b cmp r3, r1 80092cc: d905 bls.n 80092da <__udivmoddi4+0xb6> 80092ce: b10d cbz r5, 80092d4 <__udivmoddi4+0xb0> 80092d0: e9c5 0100 strd r0, r1, [r5] 80092d4: 2100 movs r1, #0 80092d6: 4608 mov r0, r1 80092d8: e7f5 b.n 80092c6 <__udivmoddi4+0xa2> 80092da: fab3 f183 clz r1, r3 80092de: 2900 cmp r1, #0 80092e0: d146 bne.n 8009370 <__udivmoddi4+0x14c> 80092e2: 4573 cmp r3, lr 80092e4: d302 bcc.n 80092ec <__udivmoddi4+0xc8> 80092e6: 4282 cmp r2, r0 80092e8: f200 8108 bhi.w 80094fc <__udivmoddi4+0x2d8> 80092ec: 1a84 subs r4, r0, r2 80092ee: eb6e 0203 sbc.w r2, lr, r3 80092f2: 2001 movs r0, #1 80092f4: 4690 mov r8, r2 80092f6: 2d00 cmp r5, #0 80092f8: d0e5 beq.n 80092c6 <__udivmoddi4+0xa2> 80092fa: e9c5 4800 strd r4, r8, [r5] 80092fe: e7e2 b.n 80092c6 <__udivmoddi4+0xa2> 8009300: 2a00 cmp r2, #0 8009302: f000 8091 beq.w 8009428 <__udivmoddi4+0x204> 8009306: fab2 f682 clz r6, r2 800930a: 2e00 cmp r6, #0 800930c: f040 80a5 bne.w 800945a <__udivmoddi4+0x236> 8009310: 1a8a subs r2, r1, r2 8009312: 2101 movs r1, #1 8009314: 0c03 lsrs r3, r0, #16 8009316: ea4f 4e17 mov.w lr, r7, lsr #16 800931a: b280 uxth r0, r0 800931c: b2bc uxth r4, r7 800931e: fbb2 fcfe udiv ip, r2, lr 8009322: fb0e 221c mls r2, lr, ip, r2 8009326: ea43 4302 orr.w r3, r3, r2, lsl #16 800932a: fb04 f20c mul.w r2, r4, ip 800932e: 429a cmp r2, r3 8009330: d907 bls.n 8009342 <__udivmoddi4+0x11e> 8009332: 18fb adds r3, r7, r3 8009334: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8009338: d202 bcs.n 8009340 <__udivmoddi4+0x11c> 800933a: 429a cmp r2, r3 800933c: f200 80e3 bhi.w 8009506 <__udivmoddi4+0x2e2> 8009340: 46c4 mov ip, r8 8009342: 1a9b subs r3, r3, r2 8009344: fbb3 f2fe udiv r2, r3, lr 8009348: fb0e 3312 mls r3, lr, r2, r3 800934c: fb02 f404 mul.w r4, r2, r4 8009350: ea40 4303 orr.w r3, r0, r3, lsl #16 8009354: 429c cmp r4, r3 8009356: d907 bls.n 8009368 <__udivmoddi4+0x144> 8009358: 18fb adds r3, r7, r3 800935a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800935e: d202 bcs.n 8009366 <__udivmoddi4+0x142> 8009360: 429c cmp r4, r3 8009362: f200 80cd bhi.w 8009500 <__udivmoddi4+0x2dc> 8009366: 4602 mov r2, r0 8009368: 1b1b subs r3, r3, r4 800936a: ea42 400c orr.w r0, r2, ip, lsl #16 800936e: e7a5 b.n 80092bc <__udivmoddi4+0x98> 8009370: f1c1 0620 rsb r6, r1, #32 8009374: 408b lsls r3, r1 8009376: fa22 f706 lsr.w r7, r2, r6 800937a: 431f orrs r7, r3 800937c: fa2e fa06 lsr.w sl, lr, r6 8009380: ea4f 4917 mov.w r9, r7, lsr #16 8009384: fbba f8f9 udiv r8, sl, r9 8009388: fa0e fe01 lsl.w lr, lr, r1 800938c: fa20 f306 lsr.w r3, r0, r6 8009390: fb09 aa18 mls sl, r9, r8, sl 8009394: fa1f fc87 uxth.w ip, r7 8009398: ea43 030e orr.w r3, r3, lr 800939c: fa00 fe01 lsl.w lr, r0, r1 80093a0: fb08 f00c mul.w r0, r8, ip 80093a4: 0c1c lsrs r4, r3, #16 80093a6: ea44 440a orr.w r4, r4, sl, lsl #16 80093aa: 42a0 cmp r0, r4 80093ac: fa02 f201 lsl.w r2, r2, r1 80093b0: d90a bls.n 80093c8 <__udivmoddi4+0x1a4> 80093b2: 193c adds r4, r7, r4 80093b4: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff 80093b8: f080 809e bcs.w 80094f8 <__udivmoddi4+0x2d4> 80093bc: 42a0 cmp r0, r4 80093be: f240 809b bls.w 80094f8 <__udivmoddi4+0x2d4> 80093c2: f1a8 0802 sub.w r8, r8, #2 80093c6: 443c add r4, r7 80093c8: 1a24 subs r4, r4, r0 80093ca: b298 uxth r0, r3 80093cc: fbb4 f3f9 udiv r3, r4, r9 80093d0: fb09 4413 mls r4, r9, r3, r4 80093d4: fb03 fc0c mul.w ip, r3, ip 80093d8: ea40 4404 orr.w r4, r0, r4, lsl #16 80093dc: 45a4 cmp ip, r4 80093de: d909 bls.n 80093f4 <__udivmoddi4+0x1d0> 80093e0: 193c adds r4, r7, r4 80093e2: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 80093e6: f080 8085 bcs.w 80094f4 <__udivmoddi4+0x2d0> 80093ea: 45a4 cmp ip, r4 80093ec: f240 8082 bls.w 80094f4 <__udivmoddi4+0x2d0> 80093f0: 3b02 subs r3, #2 80093f2: 443c add r4, r7 80093f4: ea43 4008 orr.w r0, r3, r8, lsl #16 80093f8: eba4 040c sub.w r4, r4, ip 80093fc: fba0 8c02 umull r8, ip, r0, r2 8009400: 4564 cmp r4, ip 8009402: 4643 mov r3, r8 8009404: 46e1 mov r9, ip 8009406: d364 bcc.n 80094d2 <__udivmoddi4+0x2ae> 8009408: d061 beq.n 80094ce <__udivmoddi4+0x2aa> 800940a: b15d cbz r5, 8009424 <__udivmoddi4+0x200> 800940c: ebbe 0203 subs.w r2, lr, r3 8009410: eb64 0409 sbc.w r4, r4, r9 8009414: fa04 f606 lsl.w r6, r4, r6 8009418: fa22 f301 lsr.w r3, r2, r1 800941c: 431e orrs r6, r3 800941e: 40cc lsrs r4, r1 8009420: e9c5 6400 strd r6, r4, [r5] 8009424: 2100 movs r1, #0 8009426: e74e b.n 80092c6 <__udivmoddi4+0xa2> 8009428: fbb1 fcf2 udiv ip, r1, r2 800942c: 0c01 lsrs r1, r0, #16 800942e: ea41 410e orr.w r1, r1, lr, lsl #16 8009432: b280 uxth r0, r0 8009434: ea40 4201 orr.w r2, r0, r1, lsl #16 8009438: 463b mov r3, r7 800943a: fbb1 f1f7 udiv r1, r1, r7 800943e: 4638 mov r0, r7 8009440: 463c mov r4, r7 8009442: 46b8 mov r8, r7 8009444: 46be mov lr, r7 8009446: 2620 movs r6, #32 8009448: eba2 0208 sub.w r2, r2, r8 800944c: ea41 410c orr.w r1, r1, ip, lsl #16 8009450: e765 b.n 800931e <__udivmoddi4+0xfa> 8009452: 4601 mov r1, r0 8009454: e717 b.n 8009286 <__udivmoddi4+0x62> 8009456: 4610 mov r0, r2 8009458: e72b b.n 80092b2 <__udivmoddi4+0x8e> 800945a: f1c6 0120 rsb r1, r6, #32 800945e: fa2e fc01 lsr.w ip, lr, r1 8009462: 40b7 lsls r7, r6 8009464: fa0e fe06 lsl.w lr, lr, r6 8009468: fa20 f101 lsr.w r1, r0, r1 800946c: ea41 010e orr.w r1, r1, lr 8009470: ea4f 4e17 mov.w lr, r7, lsr #16 8009474: fbbc f8fe udiv r8, ip, lr 8009478: b2bc uxth r4, r7 800947a: fb0e cc18 mls ip, lr, r8, ip 800947e: fb08 f904 mul.w r9, r8, r4 8009482: 0c0a lsrs r2, r1, #16 8009484: ea42 420c orr.w r2, r2, ip, lsl #16 8009488: 40b0 lsls r0, r6 800948a: 4591 cmp r9, r2 800948c: ea4f 4310 mov.w r3, r0, lsr #16 8009490: b280 uxth r0, r0 8009492: d93e bls.n 8009512 <__udivmoddi4+0x2ee> 8009494: 18ba adds r2, r7, r2 8009496: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 800949a: d201 bcs.n 80094a0 <__udivmoddi4+0x27c> 800949c: 4591 cmp r9, r2 800949e: d81f bhi.n 80094e0 <__udivmoddi4+0x2bc> 80094a0: eba2 0209 sub.w r2, r2, r9 80094a4: fbb2 f9fe udiv r9, r2, lr 80094a8: fb09 f804 mul.w r8, r9, r4 80094ac: fb0e 2a19 mls sl, lr, r9, r2 80094b0: b28a uxth r2, r1 80094b2: ea42 420a orr.w r2, r2, sl, lsl #16 80094b6: 4542 cmp r2, r8 80094b8: d229 bcs.n 800950e <__udivmoddi4+0x2ea> 80094ba: 18ba adds r2, r7, r2 80094bc: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80094c0: d2c2 bcs.n 8009448 <__udivmoddi4+0x224> 80094c2: 4542 cmp r2, r8 80094c4: d2c0 bcs.n 8009448 <__udivmoddi4+0x224> 80094c6: f1a9 0102 sub.w r1, r9, #2 80094ca: 443a add r2, r7 80094cc: e7bc b.n 8009448 <__udivmoddi4+0x224> 80094ce: 45c6 cmp lr, r8 80094d0: d29b bcs.n 800940a <__udivmoddi4+0x1e6> 80094d2: ebb8 0302 subs.w r3, r8, r2 80094d6: eb6c 0c07 sbc.w ip, ip, r7 80094da: 3801 subs r0, #1 80094dc: 46e1 mov r9, ip 80094de: e794 b.n 800940a <__udivmoddi4+0x1e6> 80094e0: eba7 0909 sub.w r9, r7, r9 80094e4: 444a add r2, r9 80094e6: fbb2 f9fe udiv r9, r2, lr 80094ea: f1a8 0c02 sub.w ip, r8, #2 80094ee: fb09 f804 mul.w r8, r9, r4 80094f2: e7db b.n 80094ac <__udivmoddi4+0x288> 80094f4: 4603 mov r3, r0 80094f6: e77d b.n 80093f4 <__udivmoddi4+0x1d0> 80094f8: 46d0 mov r8, sl 80094fa: e765 b.n 80093c8 <__udivmoddi4+0x1a4> 80094fc: 4608 mov r0, r1 80094fe: e6fa b.n 80092f6 <__udivmoddi4+0xd2> 8009500: 443b add r3, r7 8009502: 3a02 subs r2, #2 8009504: e730 b.n 8009368 <__udivmoddi4+0x144> 8009506: f1ac 0c02 sub.w ip, ip, #2 800950a: 443b add r3, r7 800950c: e719 b.n 8009342 <__udivmoddi4+0x11e> 800950e: 4649 mov r1, r9 8009510: e79a b.n 8009448 <__udivmoddi4+0x224> 8009512: eba2 0209 sub.w r2, r2, r9 8009516: fbb2 f9fe udiv r9, r2, lr 800951a: 46c4 mov ip, r8 800951c: fb09 f804 mul.w r8, r9, r4 8009520: e7c4 b.n 80094ac <__udivmoddi4+0x288> 8009522: bf00 nop 08009524 <__aeabi_idiv0>: 8009524: 4770 bx lr 8009526: bf00 nop 08009528 : ADC_HandleTypeDef hadc1; /* ADC1 init function */ void MX_ADC1_Init(void) { 8009528: b580 push {r7, lr} 800952a: b084 sub sp, #16 800952c: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 800952e: 1d3b adds r3, r7, #4 8009530: 2200 movs r2, #0 8009532: 601a str r2, [r3, #0] 8009534: 605a str r2, [r3, #4] 8009536: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 8009538: 4b18 ldr r3, [pc, #96] @ (800959c ) 800953a: 4a19 ldr r2, [pc, #100] @ (80095a0 ) 800953c: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 800953e: 4b17 ldr r3, [pc, #92] @ (800959c ) 8009540: 2200 movs r2, #0 8009542: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = DISABLE; 8009544: 4b15 ldr r3, [pc, #84] @ (800959c ) 8009546: 2200 movs r2, #0 8009548: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 800954a: 4b14 ldr r3, [pc, #80] @ (800959c ) 800954c: 2200 movs r2, #0 800954e: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 8009550: 4b12 ldr r3, [pc, #72] @ (800959c ) 8009552: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009556: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 8009558: 4b10 ldr r3, [pc, #64] @ (800959c ) 800955a: 2200 movs r2, #0 800955c: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 1; 800955e: 4b0f ldr r3, [pc, #60] @ (800959c ) 8009560: 2201 movs r2, #1 8009562: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 8009564: 480d ldr r0, [pc, #52] @ (800959c ) 8009566: f004 fbb7 bl 800dcd8 800956a: 4603 mov r3, r0 800956c: 2b00 cmp r3, #0 800956e: d001 beq.n 8009574 { Error_Handler(); 8009570: f001 fa50 bl 800aa14 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 8009574: 2308 movs r3, #8 8009576: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8009578: 2301 movs r3, #1 800957a: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 800957c: 2300 movs r3, #0 800957e: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8009580: 1d3b adds r3, r7, #4 8009582: 4619 mov r1, r3 8009584: 4805 ldr r0, [pc, #20] @ (800959c ) 8009586: f004 fe6b bl 800e260 800958a: 4603 mov r3, r0 800958c: 2b00 cmp r3, #0 800958e: d001 beq.n 8009594 { Error_Handler(); 8009590: f001 fa40 bl 800aa14 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 8009594: bf00 nop 8009596: 3710 adds r7, #16 8009598: 46bd mov sp, r7 800959a: bd80 pop {r7, pc} 800959c: 20000274 .word 0x20000274 80095a0: 40012400 .word 0x40012400 080095a4 : void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 80095a4: b580 push {r7, lr} 80095a6: b08a sub sp, #40 @ 0x28 80095a8: af00 add r7, sp, #0 80095aa: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80095ac: f107 0318 add.w r3, r7, #24 80095b0: 2200 movs r2, #0 80095b2: 601a str r2, [r3, #0] 80095b4: 605a str r2, [r3, #4] 80095b6: 609a str r2, [r3, #8] 80095b8: 60da str r2, [r3, #12] if(adcHandle->Instance==ADC1) 80095ba: 687b ldr r3, [r7, #4] 80095bc: 681b ldr r3, [r3, #0] 80095be: 4a1f ldr r2, [pc, #124] @ (800963c ) 80095c0: 4293 cmp r3, r2 80095c2: d137 bne.n 8009634 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* ADC1 clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 80095c4: 4b1e ldr r3, [pc, #120] @ (8009640 ) 80095c6: 699b ldr r3, [r3, #24] 80095c8: 4a1d ldr r2, [pc, #116] @ (8009640 ) 80095ca: f443 7300 orr.w r3, r3, #512 @ 0x200 80095ce: 6193 str r3, [r2, #24] 80095d0: 4b1b ldr r3, [pc, #108] @ (8009640 ) 80095d2: 699b ldr r3, [r3, #24] 80095d4: f403 7300 and.w r3, r3, #512 @ 0x200 80095d8: 617b str r3, [r7, #20] 80095da: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 80095dc: 4b18 ldr r3, [pc, #96] @ (8009640 ) 80095de: 699b ldr r3, [r3, #24] 80095e0: 4a17 ldr r2, [pc, #92] @ (8009640 ) 80095e2: f043 0304 orr.w r3, r3, #4 80095e6: 6193 str r3, [r2, #24] 80095e8: 4b15 ldr r3, [pc, #84] @ (8009640 ) 80095ea: 699b ldr r3, [r3, #24] 80095ec: f003 0304 and.w r3, r3, #4 80095f0: 613b str r3, [r7, #16] 80095f2: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 80095f4: 4b12 ldr r3, [pc, #72] @ (8009640 ) 80095f6: 699b ldr r3, [r3, #24] 80095f8: 4a11 ldr r2, [pc, #68] @ (8009640 ) 80095fa: f043 0308 orr.w r3, r3, #8 80095fe: 6193 str r3, [r2, #24] 8009600: 4b0f ldr r3, [pc, #60] @ (8009640 ) 8009602: 699b ldr r3, [r3, #24] 8009604: f003 0308 and.w r3, r3, #8 8009608: 60fb str r3, [r7, #12] 800960a: 68fb ldr r3, [r7, #12] PA3 ------> ADC1_IN3 PA4 ------> ADC1_IN4 PB0 ------> ADC1_IN8 PB1 ------> ADC1_IN9 */ GPIO_InitStruct.Pin = GPIO_PIN_3|CP_ADC_Pin; 800960c: 2318 movs r3, #24 800960e: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009610: 2303 movs r3, #3 8009612: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8009614: f107 0318 add.w r3, r7, #24 8009618: 4619 mov r1, r3 800961a: 480a ldr r0, [pc, #40] @ (8009644 ) 800961c: f006 f9a4 bl 800f968 GPIO_InitStruct.Pin = ADC_NTC1_Pin|ADC_NTC2_Pin; 8009620: 2303 movs r3, #3 8009622: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009624: 2303 movs r3, #3 8009626: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009628: f107 0318 add.w r3, r7, #24 800962c: 4619 mov r1, r3 800962e: 4806 ldr r0, [pc, #24] @ (8009648 ) 8009630: f006 f99a bl 800f968 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 8009634: bf00 nop 8009636: 3728 adds r7, #40 @ 0x28 8009638: 46bd mov sp, r7 800963a: bd80 pop {r7, pc} 800963c: 40012400 .word 0x40012400 8009640: 40021000 .word 0x40021000 8009644: 40010800 .word 0x40010800 8009648: 40010c00 .word 0x40010c00 0800964c : uint8_t RELAY_State[RELAY_COUNT]; static volatile uint8_t adc_lock = 0; static SMAFilter_t conn_temp_adc_filter[2]; void RELAY_Write(relay_t num, uint8_t state){ 800964c: b580 push {r7, lr} 800964e: b082 sub sp, #8 8009650: af00 add r7, sp, #0 8009652: 4603 mov r3, r0 8009654: 460a mov r2, r1 8009656: 71fb strb r3, [r7, #7] 8009658: 4613 mov r3, r2 800965a: 71bb strb r3, [r7, #6] switch (num) { 800965c: 79fb ldrb r3, [r7, #7] 800965e: 2b07 cmp r3, #7 8009660: d850 bhi.n 8009704 8009662: a201 add r2, pc, #4 @ (adr r2, 8009668 ) 8009664: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009668: 08009689 .word 0x08009689 800966c: 08009699 .word 0x08009699 8009670: 080096a9 .word 0x080096a9 8009674: 080096b9 .word 0x080096b9 8009678: 080096c9 .word 0x080096c9 800967c: 080096d9 .word 0x080096d9 8009680: 080096e7 .word 0x080096e7 8009684: 080096f7 .word 0x080096f7 case RELAY_AUX0: HAL_GPIO_WritePin(RELAY1_GPIO_Port, RELAY1_Pin, state); 8009688: 79bb ldrb r3, [r7, #6] 800968a: 461a mov r2, r3 800968c: f44f 7180 mov.w r1, #256 @ 0x100 8009690: 4821 ldr r0, [pc, #132] @ (8009718 ) 8009692: f006 fb04 bl 800fc9e break; 8009696: e036 b.n 8009706 case RELAY_AUX1: HAL_GPIO_WritePin(RELAY2_GPIO_Port, RELAY2_Pin, state); 8009698: 79bb ldrb r3, [r7, #6] 800969a: 461a mov r2, r3 800969c: f44f 7100 mov.w r1, #512 @ 0x200 80096a0: 481d ldr r0, [pc, #116] @ (8009718 ) 80096a2: f006 fafc bl 800fc9e break; 80096a6: e02e b.n 8009706 case RELAY3: HAL_GPIO_WritePin(RELAY3_GPIO_Port, RELAY3_Pin, state); 80096a8: 79bb ldrb r3, [r7, #6] 80096aa: 461a mov r2, r3 80096ac: f44f 6180 mov.w r1, #1024 @ 0x400 80096b0: 4819 ldr r0, [pc, #100] @ (8009718 ) 80096b2: f006 faf4 bl 800fc9e break; 80096b6: e026 b.n 8009706 case RELAY_DC: HAL_GPIO_WritePin(RELAY4_GPIO_Port, RELAY4_Pin, state); 80096b8: 79bb ldrb r3, [r7, #6] 80096ba: 461a mov r2, r3 80096bc: f44f 6100 mov.w r1, #2048 @ 0x800 80096c0: 4815 ldr r0, [pc, #84] @ (8009718 ) 80096c2: f006 faec bl 800fc9e break; 80096c6: e01e b.n 8009706 case RELAY_AC: HAL_GPIO_WritePin(RELAY5_GPIO_Port, RELAY5_Pin, state); 80096c8: 79bb ldrb r3, [r7, #6] 80096ca: 461a mov r2, r3 80096cc: f44f 5180 mov.w r1, #4096 @ 0x1000 80096d0: 4811 ldr r0, [pc, #68] @ (8009718 ) 80096d2: f006 fae4 bl 800fc9e break; 80096d6: e016 b.n 8009706 case RELAY_CP: HAL_GPIO_WritePin(RELAY_CP_GPIO_Port, RELAY_CP_Pin, state); 80096d8: 79bb ldrb r3, [r7, #6] 80096da: 461a mov r2, r3 80096dc: 2108 movs r1, #8 80096de: 480f ldr r0, [pc, #60] @ (800971c ) 80096e0: f006 fadd bl 800fc9e break; 80096e4: e00f b.n 8009706 case RELAY_CC: HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, state); 80096e6: 79bb ldrb r3, [r7, #6] 80096e8: 461a mov r2, r3 80096ea: f44f 4100 mov.w r1, #32768 @ 0x8000 80096ee: 480c ldr r0, [pc, #48] @ (8009720 ) 80096f0: f006 fad5 bl 800fc9e break; 80096f4: e007 b.n 8009706 case RELAY_DC1: HAL_GPIO_WritePin(RELAY_DC_GPIO_Port, RELAY_DC_Pin, state); 80096f6: 79bb ldrb r3, [r7, #6] 80096f8: 461a mov r2, r3 80096fa: 2108 movs r1, #8 80096fc: 4809 ldr r0, [pc, #36] @ (8009724 ) 80096fe: f006 face bl 800fc9e break; 8009702: e000 b.n 8009706 default: break; 8009704: bf00 nop } RELAY_State[num] = state; 8009706: 79fb ldrb r3, [r7, #7] 8009708: 4907 ldr r1, [pc, #28] @ (8009728 ) 800970a: 79ba ldrb r2, [r7, #6] 800970c: 54ca strb r2, [r1, r3] } 800970e: bf00 nop 8009710: 3708 adds r7, #8 8009712: 46bd mov sp, r7 8009714: bd80 pop {r7, pc} 8009716: bf00 nop 8009718: 40011800 .word 0x40011800 800971c: 40011000 .word 0x40011000 8009720: 40010800 .word 0x40010800 8009724: 40011400 .word 0x40011400 8009728: 200002a4 .word 0x200002a4 0800972c : uint8_t RELAY_Read(relay_t num){ 800972c: b480 push {r7} 800972e: b083 sub sp, #12 8009730: af00 add r7, sp, #0 8009732: 4603 mov r3, r0 8009734: 71fb strb r3, [r7, #7] return RELAY_State[num]; 8009736: 79fb ldrb r3, [r7, #7] 8009738: 4a03 ldr r2, [pc, #12] @ (8009748 ) 800973a: 5cd3 ldrb r3, [r2, r3] } 800973c: 4618 mov r0, r3 800973e: 370c adds r7, #12 8009740: 46bd mov sp, r7 8009742: bc80 pop {r7} 8009744: 4770 bx lr 8009746: bf00 nop 8009748: 200002a4 .word 0x200002a4 0800974c : uint8_t IN_ReadInput(inputNum_t input_n){ 800974c: b580 push {r7, lr} 800974e: b082 sub sp, #8 8009750: af00 add r7, sp, #0 8009752: 4603 mov r3, r0 8009754: 71fb strb r3, [r7, #7] switch(input_n){ 8009756: 79fb ldrb r3, [r7, #7] 8009758: 2b06 cmp r3, #6 800975a: d83b bhi.n 80097d4 800975c: a201 add r2, pc, #4 @ (adr r2, 8009764 ) 800975e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009762: bf00 nop 8009764: 08009781 .word 0x08009781 8009768: 0800978d .word 0x0800978d 800976c: 08009799 .word 0x08009799 8009770: 080097a5 .word 0x080097a5 8009774: 080097b1 .word 0x080097b1 8009778: 080097bd .word 0x080097bd 800977c: 080097c9 .word 0x080097c9 case IN_SW0: return HAL_GPIO_ReadPin(IN_SW0_GPIO_Port, IN_SW0_Pin); 8009780: 2102 movs r1, #2 8009782: 4817 ldr r0, [pc, #92] @ (80097e0 ) 8009784: f006 fa74 bl 800fc70 8009788: 4603 mov r3, r0 800978a: e024 b.n 80097d6 case IN_SW1: return HAL_GPIO_ReadPin(IN_SW1_GPIO_Port, IN_SW1_Pin); 800978c: 2104 movs r1, #4 800978e: 4814 ldr r0, [pc, #80] @ (80097e0 ) 8009790: f006 fa6e bl 800fc70 8009794: 4603 mov r3, r0 8009796: e01e b.n 80097d6 case IN0: return HAL_GPIO_ReadPin(IN0_GPIO_Port, IN0_Pin); 8009798: 2180 movs r1, #128 @ 0x80 800979a: 4812 ldr r0, [pc, #72] @ (80097e4 ) 800979c: f006 fa68 bl 800fc70 80097a0: 4603 mov r3, r0 80097a2: e018 b.n 80097d6 case IN_ESTOP: return HAL_GPIO_ReadPin(IN_ESTOP_GPIO_Port, IN_ESTOP_Pin); 80097a4: 2180 movs r1, #128 @ 0x80 80097a6: 4810 ldr r0, [pc, #64] @ (80097e8 ) 80097a8: f006 fa62 bl 800fc70 80097ac: 4603 mov r3, r0 80097ae: e012 b.n 80097d6 case IN_FB1: return HAL_GPIO_ReadPin(IN_FB1_GPIO_Port, IN_FB1_Pin); 80097b0: 2110 movs r1, #16 80097b2: 480e ldr r0, [pc, #56] @ (80097ec ) 80097b4: f006 fa5c bl 800fc70 80097b8: 4603 mov r3, r0 80097ba: e00c b.n 80097d6 case IN_CONT_FB_DC: return HAL_GPIO_ReadPin(IN_FB2_GPIO_Port, IN_FB2_Pin); 80097bc: 2108 movs r1, #8 80097be: 480b ldr r0, [pc, #44] @ (80097ec ) 80097c0: f006 fa56 bl 800fc70 80097c4: 4603 mov r3, r0 80097c6: e006 b.n 80097d6 case ISO_IN: return HAL_GPIO_ReadPin(ISO_IN_GPIO_Port, ISO_IN_Pin); 80097c8: 2102 movs r1, #2 80097ca: 4806 ldr r0, [pc, #24] @ (80097e4 ) 80097cc: f006 fa50 bl 800fc70 80097d0: 4603 mov r3, r0 80097d2: e000 b.n 80097d6 default: return 0; 80097d4: 2300 movs r3, #0 } } 80097d6: 4618 mov r0, r3 80097d8: 3708 adds r7, #8 80097da: 46bd mov sp, r7 80097dc: bd80 pop {r7, pc} 80097de: bf00 nop 80097e0: 40010800 .word 0x40010800 80097e4: 40011800 .word 0x40011800 80097e8: 40011400 .word 0x40011400 80097ec: 40010c00 .word 0x40010c00 080097f0 : // // HAL_ADC_Stop(&hadc1); // stop adc return 0; } void Init_Peripheral(){ 80097f0: b580 push {r7, lr} 80097f2: af00 add r7, sp, #0 HAL_ADCEx_Calibration_Start(&hadc1); 80097f4: 4815 ldr r0, [pc, #84] @ (800984c ) 80097f6: f004 fec7 bl 800e588 RELAY_Write(RELAY_AUX0, 0); 80097fa: 2100 movs r1, #0 80097fc: 2000 movs r0, #0 80097fe: f7ff ff25 bl 800964c RELAY_Write(RELAY_AUX1, 0); 8009802: 2100 movs r1, #0 8009804: 2001 movs r0, #1 8009806: f7ff ff21 bl 800964c RELAY_Write(RELAY3, 0); 800980a: 2100 movs r1, #0 800980c: 2002 movs r0, #2 800980e: f7ff ff1d bl 800964c RELAY_Write(RELAY_DC, 0); 8009812: 2100 movs r1, #0 8009814: 2003 movs r0, #3 8009816: f7ff ff19 bl 800964c RELAY_Write(RELAY_AC, 0); 800981a: 2100 movs r1, #0 800981c: 2004 movs r0, #4 800981e: f7ff ff15 bl 800964c RELAY_Write(RELAY_CP, 0); 8009822: 2100 movs r1, #0 8009824: 2005 movs r0, #5 8009826: f7ff ff11 bl 800964c RELAY_Write(RELAY_CC, 0); 800982a: 2100 movs r1, #0 800982c: 2006 movs r0, #6 800982e: f7ff ff0d bl 800964c RELAY_Write(RELAY_DC1, 0); 8009832: 2100 movs r1, #0 8009834: 2007 movs r0, #7 8009836: f7ff ff09 bl 800964c SMAFilter_Init(&conn_temp_adc_filter[0]); 800983a: 4805 ldr r0, [pc, #20] @ (8009850 ) 800983c: f003 fc0a bl 800d054 SMAFilter_Init(&conn_temp_adc_filter[1]); 8009840: 4804 ldr r0, [pc, #16] @ (8009854 ) 8009842: f003 fc07 bl 800d054 } 8009846: bf00 nop 8009848: bd80 pop {r7, pc} 800984a: bf00 nop 800984c: 20000274 .word 0x20000274 8009850: 200002b0 .word 0x200002b0 8009854: 200002d8 .word 0x200002d8 08009858 : float pt1000_to_temperature(float resistance) { 8009858: b590 push {r4, r7, lr} 800985a: b087 sub sp, #28 800985c: af00 add r7, sp, #0 800985e: 6078 str r0, [r7, #4] // Константы для PT1000 const float R0 = 1000.0; // Сопротивление при 0 °C 8009860: 4b0c ldr r3, [pc, #48] @ (8009894 ) 8009862: 617b str r3, [r7, #20] const float C_A = 3.9083E-3f; 8009864: 4b0c ldr r3, [pc, #48] @ (8009898 ) 8009866: 613b str r3, [r7, #16] float temperature = (resistance-R0) / ( R0 * C_A); 8009868: 6979 ldr r1, [r7, #20] 800986a: 6878 ldr r0, [r7, #4] 800986c: f7ff f9cc bl 8008c08 <__aeabi_fsub> 8009870: 4603 mov r3, r0 8009872: 461c mov r4, r3 8009874: 6939 ldr r1, [r7, #16] 8009876: 6978 ldr r0, [r7, #20] 8009878: f7ff fad0 bl 8008e1c <__aeabi_fmul> 800987c: 4603 mov r3, r0 800987e: 4619 mov r1, r3 8009880: 4620 mov r0, r4 8009882: f7ff fb7f bl 8008f84 <__aeabi_fdiv> 8009886: 4603 mov r3, r0 8009888: 60fb str r3, [r7, #12] return temperature; 800988a: 68fb ldr r3, [r7, #12] } 800988c: 4618 mov r0, r3 800988e: 371c adds r7, #28 8009890: 46bd mov sp, r7 8009892: bd90 pop {r4, r7, pc} 8009894: 447a0000 .word 0x447a0000 8009898: 3b801132 .word 0x3b801132 800989c: 00000000 .word 0x00000000 080098a0 : float calculate_NTC_resistance(int adc_value, float Vref, float Vin, float R) { 80098a0: b5b0 push {r4, r5, r7, lr} 80098a2: b086 sub sp, #24 80098a4: af00 add r7, sp, #0 80098a6: 60f8 str r0, [r7, #12] 80098a8: 60b9 str r1, [r7, #8] 80098aa: 607a str r2, [r7, #4] 80098ac: 603b str r3, [r7, #0] // Преобразуем значение АЦП в выходное напряжение float Vout = (adc_value / 4095.0) * Vref; 80098ae: 68f8 ldr r0, [r7, #12] 80098b0: f7fe fe14 bl 80084dc <__aeabi_i2d> 80098b4: a31c add r3, pc, #112 @ (adr r3, 8009928 ) 80098b6: e9d3 2300 ldrd r2, r3, [r3] 80098ba: f7fe ffa3 bl 8008804 <__aeabi_ddiv> 80098be: 4602 mov r2, r0 80098c0: 460b mov r3, r1 80098c2: 4614 mov r4, r2 80098c4: 461d mov r5, r3 80098c6: 68b8 ldr r0, [r7, #8] 80098c8: f7fe fe1a bl 8008500 <__aeabi_f2d> 80098cc: 4602 mov r2, r0 80098ce: 460b mov r3, r1 80098d0: 4620 mov r0, r4 80098d2: 4629 mov r1, r5 80098d4: f7fe fe6c bl 80085b0 <__aeabi_dmul> 80098d8: 4602 mov r2, r0 80098da: 460b mov r3, r1 80098dc: 4610 mov r0, r2 80098de: 4619 mov r1, r3 80098e0: f7ff f93e bl 8008b60 <__aeabi_d2f> 80098e4: 4603 mov r3, r0 80098e6: 617b str r3, [r7, #20] // Проверяем, чтобы Vout не было равно Vin if (Vout >= Vin) { 80098e8: 6879 ldr r1, [r7, #4] 80098ea: 6978 ldr r0, [r7, #20] 80098ec: f7ff fc48 bl 8009180 <__aeabi_fcmpge> 80098f0: 4603 mov r3, r0 80098f2: 2b00 cmp r3, #0 80098f4: d001 beq.n 80098fa return -1; // Ошибка: Vout не может быть больше или равно Vin 80098f6: 4b0e ldr r3, [pc, #56] @ (8009930 ) 80098f8: e010 b.n 800991c } // Вычисляем сопротивление термистора float R_NTC = R * (Vout / (Vin - Vout)); 80098fa: 6979 ldr r1, [r7, #20] 80098fc: 6878 ldr r0, [r7, #4] 80098fe: f7ff f983 bl 8008c08 <__aeabi_fsub> 8009902: 4603 mov r3, r0 8009904: 4619 mov r1, r3 8009906: 6978 ldr r0, [r7, #20] 8009908: f7ff fb3c bl 8008f84 <__aeabi_fdiv> 800990c: 4603 mov r3, r0 800990e: 4619 mov r1, r3 8009910: 6838 ldr r0, [r7, #0] 8009912: f7ff fa83 bl 8008e1c <__aeabi_fmul> 8009916: 4603 mov r3, r0 8009918: 613b str r3, [r7, #16] return R_NTC; 800991a: 693b ldr r3, [r7, #16] } 800991c: 4618 mov r0, r3 800991e: 3718 adds r7, #24 8009920: 46bd mov sp, r7 8009922: bdb0 pop {r4, r5, r7, pc} 8009924: f3af 8000 nop.w 8009928: 00000000 .word 0x00000000 800992c: 40affe00 .word 0x40affe00 8009930: bf800000 .word 0xbf800000 08009934 : int16_t CONN_ReadTemp(uint8_t ch){ 8009934: b580 push {r7, lr} 8009936: b088 sub sp, #32 8009938: af00 add r7, sp, #0 800993a: 4603 mov r3, r0 800993c: 71fb strb r3, [r7, #7] ADC_LockBlocking(); 800993e: f000 f89b bl 8009a78 //TODO if(ch)ADC_Select_Channel(ADC_CHANNEL_8); 8009942: 79fb ldrb r3, [r7, #7] 8009944: 2b00 cmp r3, #0 8009946: d003 beq.n 8009950 8009948: 2008 movs r0, #8 800994a: f000 f853 bl 80099f4 800994e: e002 b.n 8009956 else ADC_Select_Channel(ADC_CHANNEL_9); 8009950: 2009 movs r0, #9 8009952: f000 f84f bl 80099f4 // Начало конверсии HAL_ADC_Start(&hadc1); 8009956: 4822 ldr r0, [pc, #136] @ (80099e0 ) 8009958: f004 fa96 bl 800de88 // Ожидание окончания конверсии HAL_ADC_PollForConversion(&hadc1, HAL_MAX_DELAY); 800995c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8009960: 481f ldr r0, [pc, #124] @ (80099e0 ) 8009962: f004 fb6b bl 800e03c // Получение значения uint32_t adcValue = HAL_ADC_GetValue(&hadc1); 8009966: 481e ldr r0, [pc, #120] @ (80099e0 ) 8009968: f004 fc6e bl 800e248 800996c: 61f8 str r0, [r7, #28] // Остановка АЦП (по желанию) HAL_ADC_Stop(&hadc1); 800996e: 481c ldr r0, [pc, #112] @ (80099e0 ) 8009970: f004 fb38 bl 800dfe4 int32_t adc_filtered = SMAFilter_Update(&conn_temp_adc_filter[ch ? 1u : 0u], (int32_t)adcValue); 8009974: 79fb ldrb r3, [r7, #7] 8009976: 2b00 cmp r3, #0 8009978: d001 beq.n 800997e 800997a: 2201 movs r2, #1 800997c: e000 b.n 8009980 800997e: 2200 movs r2, #0 8009980: 4613 mov r3, r2 8009982: 009b lsls r3, r3, #2 8009984: 4413 add r3, r2 8009986: 00db lsls r3, r3, #3 8009988: 4a16 ldr r2, [pc, #88] @ (80099e4 ) 800998a: 4413 add r3, r2 800998c: 69fa ldr r2, [r7, #28] 800998e: 4611 mov r1, r2 8009990: 4618 mov r0, r3 8009992: f003 fb84 bl 800d09e 8009996: 61b8 str r0, [r7, #24] if((uint32_t)adc_filtered > 4000u) { 8009998: 69bb ldr r3, [r7, #24] 800999a: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800999e: d903 bls.n 80099a8 ADC_Unlock(); 80099a0: f000 f876 bl 8009a90 return 20; //Термодатчик не подключен 80099a4: 2314 movs r3, #20 80099a6: e017 b.n 80099d8 } // int adc_value = 2048; // Пример значения АЦП float Vref = 3.3; // Напряжение опорное 80099a8: 4b0f ldr r3, [pc, #60] @ (80099e8 ) 80099aa: 617b str r3, [r7, #20] float Vin = 5.0; // Входное напряжение 80099ac: 4b0f ldr r3, [pc, #60] @ (80099ec ) 80099ae: 613b str r3, [r7, #16] float R = 1000; // Сопротивление резистора в Омах 80099b0: 4b0f ldr r3, [pc, #60] @ (80099f0 ) 80099b2: 60fb str r3, [r7, #12] float temp = pt1000_to_temperature(calculate_NTC_resistance((int)adc_filtered, Vref, Vin, R)); 80099b4: 68fb ldr r3, [r7, #12] 80099b6: 693a ldr r2, [r7, #16] 80099b8: 6979 ldr r1, [r7, #20] 80099ba: 69b8 ldr r0, [r7, #24] 80099bc: f7ff ff70 bl 80098a0 80099c0: 4603 mov r3, r0 80099c2: 4618 mov r0, r3 80099c4: f7ff ff48 bl 8009858 80099c8: 60b8 str r0, [r7, #8] ADC_Unlock(); 80099ca: f000 f861 bl 8009a90 return (int16_t)temp; 80099ce: 68b8 ldr r0, [r7, #8] 80099d0: f7ff fbea bl 80091a8 <__aeabi_f2iz> 80099d4: 4603 mov r3, r0 80099d6: b21b sxth r3, r3 } 80099d8: 4618 mov r0, r3 80099da: 3720 adds r7, #32 80099dc: 46bd mov sp, r7 80099de: bd80 pop {r7, pc} 80099e0: 20000274 .word 0x20000274 80099e4: 200002b0 .word 0x200002b0 80099e8: 40533333 .word 0x40533333 80099ec: 40a00000 .word 0x40a00000 80099f0: 447a0000 .word 0x447a0000 080099f4 : int16_t GBT_ReadTemp(uint8_t ch){ return CONN_ReadTemp(ch); } void ADC_Select_Channel(uint32_t ch) { 80099f4: b580 push {r7, lr} 80099f6: b086 sub sp, #24 80099f8: af00 add r7, sp, #0 80099fa: 6078 str r0, [r7, #4] ADC_ChannelConfTypeDef conf = { 80099fc: 687b ldr r3, [r7, #4] 80099fe: 60fb str r3, [r7, #12] 8009a00: 2301 movs r3, #1 8009a02: 613b str r3, [r7, #16] 8009a04: 2303 movs r3, #3 8009a06: 617b str r3, [r7, #20] .Channel = ch, .Rank = 1, .SamplingTime = ADC_SAMPLETIME_28CYCLES_5, }; if (HAL_ADC_ConfigChannel(&hadc1, &conf) != HAL_OK) { 8009a08: f107 030c add.w r3, r7, #12 8009a0c: 4619 mov r1, r3 8009a0e: 4806 ldr r0, [pc, #24] @ (8009a28 ) 8009a10: f004 fc26 bl 800e260 8009a14: 4603 mov r3, r0 8009a16: 2b00 cmp r3, #0 8009a18: d001 beq.n 8009a1e Error_Handler(); 8009a1a: f000 fffb bl 800aa14 } } 8009a1e: bf00 nop 8009a20: 3718 adds r7, #24 8009a22: 46bd mov sp, r7 8009a24: bd80 pop {r7, pc} 8009a26: bf00 nop 8009a28: 20000274 .word 0x20000274 08009a2c : uint8_t ADC_TryLock(void) { 8009a2c: b480 push {r7} 8009a2e: b083 sub sp, #12 8009a30: af00 add r7, sp, #0 */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8009a32: f3ef 8310 mrs r3, PRIMASK 8009a36: 603b str r3, [r7, #0] return(result); 8009a38: 683b ldr r3, [r7, #0] uint32_t primask = __get_PRIMASK(); 8009a3a: 607b str r3, [r7, #4] __ASM volatile ("cpsid i" : : : "memory"); 8009a3c: b672 cpsid i } 8009a3e: bf00 nop __disable_irq(); if (adc_lock != 0u) { 8009a40: 4b0c ldr r3, [pc, #48] @ (8009a74 ) 8009a42: 781b ldrb r3, [r3, #0] 8009a44: b2db uxtb r3, r3 8009a46: 2b00 cmp r3, #0 8009a48: d006 beq.n 8009a58 if (primask == 0u) { 8009a4a: 687b ldr r3, [r7, #4] 8009a4c: 2b00 cmp r3, #0 8009a4e: d101 bne.n 8009a54 __ASM volatile ("cpsie i" : : : "memory"); 8009a50: b662 cpsie i } 8009a52: bf00 nop __enable_irq(); } return 0u; 8009a54: 2300 movs r3, #0 8009a56: e008 b.n 8009a6a } adc_lock = 1u; 8009a58: 4b06 ldr r3, [pc, #24] @ (8009a74 ) 8009a5a: 2201 movs r2, #1 8009a5c: 701a strb r2, [r3, #0] if (primask == 0u) { 8009a5e: 687b ldr r3, [r7, #4] 8009a60: 2b00 cmp r3, #0 8009a62: d101 bne.n 8009a68 __ASM volatile ("cpsie i" : : : "memory"); 8009a64: b662 cpsie i } 8009a66: bf00 nop __enable_irq(); } return 1u; 8009a68: 2301 movs r3, #1 } 8009a6a: 4618 mov r0, r3 8009a6c: 370c adds r7, #12 8009a6e: 46bd mov sp, r7 8009a70: bc80 pop {r7} 8009a72: 4770 bx lr 8009a74: 200002ac .word 0x200002ac 08009a78 : void ADC_LockBlocking(void) { 8009a78: b580 push {r7, lr} 8009a7a: af00 add r7, sp, #0 while (ADC_TryLock() == 0u) { 8009a7c: bf00 nop 8009a7e: f7ff ffd5 bl 8009a2c 8009a82: 4603 mov r3, r0 8009a84: 2b00 cmp r3, #0 8009a86: d0fa beq.n 8009a7e /* wait in main context until ADC is free */ } } 8009a88: bf00 nop 8009a8a: bf00 nop 8009a8c: bd80 pop {r7, pc} ... 08009a90 : void ADC_Unlock(void) { 8009a90: b480 push {r7} 8009a92: b083 sub sp, #12 8009a94: af00 add r7, sp, #0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8009a96: f3ef 8310 mrs r3, PRIMASK 8009a9a: 603b str r3, [r7, #0] return(result); 8009a9c: 683b ldr r3, [r7, #0] uint32_t primask = __get_PRIMASK(); 8009a9e: 607b str r3, [r7, #4] __ASM volatile ("cpsid i" : : : "memory"); 8009aa0: b672 cpsid i } 8009aa2: bf00 nop __disable_irq(); adc_lock = 0u; 8009aa4: 4b06 ldr r3, [pc, #24] @ (8009ac0 ) 8009aa6: 2200 movs r2, #0 8009aa8: 701a strb r2, [r3, #0] if (primask == 0u) { 8009aaa: 687b ldr r3, [r7, #4] 8009aac: 2b00 cmp r3, #0 8009aae: d101 bne.n 8009ab4 __ASM volatile ("cpsie i" : : : "memory"); 8009ab0: b662 cpsie i } 8009ab2: bf00 nop __enable_irq(); } } 8009ab4: bf00 nop 8009ab6: 370c adds r7, #12 8009ab8: 46bd mov sp, r7 8009aba: bc80 pop {r7} 8009abc: 4770 bx lr 8009abe: bf00 nop 8009ac0: 200002ac .word 0x200002ac 08009ac4 : CAN_HandleTypeDef hcan1; CAN_HandleTypeDef hcan2; /* CAN1 init function */ void MX_CAN1_Init(void) { 8009ac4: b580 push {r7, lr} 8009ac6: af00 add r7, sp, #0 /* USER CODE END CAN1_Init 0 */ /* USER CODE BEGIN CAN1_Init 1 */ /* USER CODE END CAN1_Init 1 */ hcan1.Instance = CAN1; 8009ac8: 4b17 ldr r3, [pc, #92] @ (8009b28 ) 8009aca: 4a18 ldr r2, [pc, #96] @ (8009b2c ) 8009acc: 601a str r2, [r3, #0] hcan1.Init.Prescaler = 8; 8009ace: 4b16 ldr r3, [pc, #88] @ (8009b28 ) 8009ad0: 2208 movs r2, #8 8009ad2: 605a str r2, [r3, #4] hcan1.Init.Mode = CAN_MODE_NORMAL; 8009ad4: 4b14 ldr r3, [pc, #80] @ (8009b28 ) 8009ad6: 2200 movs r2, #0 8009ad8: 609a str r2, [r3, #8] hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; 8009ada: 4b13 ldr r3, [pc, #76] @ (8009b28 ) 8009adc: 2200 movs r2, #0 8009ade: 60da str r2, [r3, #12] hcan1.Init.TimeSeg1 = CAN_BS1_15TQ; 8009ae0: 4b11 ldr r3, [pc, #68] @ (8009b28 ) 8009ae2: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009ae6: 611a str r2, [r3, #16] hcan1.Init.TimeSeg2 = CAN_BS2_2TQ; 8009ae8: 4b0f ldr r3, [pc, #60] @ (8009b28 ) 8009aea: f44f 1280 mov.w r2, #1048576 @ 0x100000 8009aee: 615a str r2, [r3, #20] hcan1.Init.TimeTriggeredMode = DISABLE; 8009af0: 4b0d ldr r3, [pc, #52] @ (8009b28 ) 8009af2: 2200 movs r2, #0 8009af4: 761a strb r2, [r3, #24] hcan1.Init.AutoBusOff = ENABLE; 8009af6: 4b0c ldr r3, [pc, #48] @ (8009b28 ) 8009af8: 2201 movs r2, #1 8009afa: 765a strb r2, [r3, #25] hcan1.Init.AutoWakeUp = ENABLE; 8009afc: 4b0a ldr r3, [pc, #40] @ (8009b28 ) 8009afe: 2201 movs r2, #1 8009b00: 769a strb r2, [r3, #26] hcan1.Init.AutoRetransmission = ENABLE; 8009b02: 4b09 ldr r3, [pc, #36] @ (8009b28 ) 8009b04: 2201 movs r2, #1 8009b06: 76da strb r2, [r3, #27] hcan1.Init.ReceiveFifoLocked = DISABLE; 8009b08: 4b07 ldr r3, [pc, #28] @ (8009b28 ) 8009b0a: 2200 movs r2, #0 8009b0c: 771a strb r2, [r3, #28] hcan1.Init.TransmitFifoPriority = ENABLE; 8009b0e: 4b06 ldr r3, [pc, #24] @ (8009b28 ) 8009b10: 2201 movs r2, #1 8009b12: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan1) != HAL_OK) 8009b14: 4804 ldr r0, [pc, #16] @ (8009b28 ) 8009b16: f004 fde5 bl 800e6e4 8009b1a: 4603 mov r3, r0 8009b1c: 2b00 cmp r3, #0 8009b1e: d001 beq.n 8009b24 { Error_Handler(); 8009b20: f000 ff78 bl 800aa14 } /* USER CODE BEGIN CAN1_Init 2 */ /* USER CODE END CAN1_Init 2 */ } 8009b24: bf00 nop 8009b26: bd80 pop {r7, pc} 8009b28: 20000300 .word 0x20000300 8009b2c: 40006400 .word 0x40006400 08009b30 : /* CAN2 init function */ void MX_CAN2_Init(void) { 8009b30: b580 push {r7, lr} 8009b32: af00 add r7, sp, #0 /* USER CODE END CAN2_Init 0 */ /* USER CODE BEGIN CAN2_Init 1 */ /* USER CODE END CAN2_Init 1 */ hcan2.Instance = CAN2; 8009b34: 4b17 ldr r3, [pc, #92] @ (8009b94 ) 8009b36: 4a18 ldr r2, [pc, #96] @ (8009b98 ) 8009b38: 601a str r2, [r3, #0] hcan2.Init.Prescaler = 16; 8009b3a: 4b16 ldr r3, [pc, #88] @ (8009b94 ) 8009b3c: 2210 movs r2, #16 8009b3e: 605a str r2, [r3, #4] hcan2.Init.Mode = CAN_MODE_NORMAL; 8009b40: 4b14 ldr r3, [pc, #80] @ (8009b94 ) 8009b42: 2200 movs r2, #0 8009b44: 609a str r2, [r3, #8] hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; 8009b46: 4b13 ldr r3, [pc, #76] @ (8009b94 ) 8009b48: 2200 movs r2, #0 8009b4a: 60da str r2, [r3, #12] hcan2.Init.TimeSeg1 = CAN_BS1_15TQ; 8009b4c: 4b11 ldr r3, [pc, #68] @ (8009b94 ) 8009b4e: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009b52: 611a str r2, [r3, #16] hcan2.Init.TimeSeg2 = CAN_BS2_2TQ; 8009b54: 4b0f ldr r3, [pc, #60] @ (8009b94 ) 8009b56: f44f 1280 mov.w r2, #1048576 @ 0x100000 8009b5a: 615a str r2, [r3, #20] hcan2.Init.TimeTriggeredMode = DISABLE; 8009b5c: 4b0d ldr r3, [pc, #52] @ (8009b94 ) 8009b5e: 2200 movs r2, #0 8009b60: 761a strb r2, [r3, #24] hcan2.Init.AutoBusOff = ENABLE; 8009b62: 4b0c ldr r3, [pc, #48] @ (8009b94 ) 8009b64: 2201 movs r2, #1 8009b66: 765a strb r2, [r3, #25] hcan2.Init.AutoWakeUp = ENABLE; 8009b68: 4b0a ldr r3, [pc, #40] @ (8009b94 ) 8009b6a: 2201 movs r2, #1 8009b6c: 769a strb r2, [r3, #26] hcan2.Init.AutoRetransmission = ENABLE; 8009b6e: 4b09 ldr r3, [pc, #36] @ (8009b94 ) 8009b70: 2201 movs r2, #1 8009b72: 76da strb r2, [r3, #27] hcan2.Init.ReceiveFifoLocked = DISABLE; 8009b74: 4b07 ldr r3, [pc, #28] @ (8009b94 ) 8009b76: 2200 movs r2, #0 8009b78: 771a strb r2, [r3, #28] hcan2.Init.TransmitFifoPriority = ENABLE; 8009b7a: 4b06 ldr r3, [pc, #24] @ (8009b94 ) 8009b7c: 2201 movs r2, #1 8009b7e: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan2) != HAL_OK) 8009b80: 4804 ldr r0, [pc, #16] @ (8009b94 ) 8009b82: f004 fdaf bl 800e6e4 8009b86: 4603 mov r3, r0 8009b88: 2b00 cmp r3, #0 8009b8a: d001 beq.n 8009b90 { Error_Handler(); 8009b8c: f000 ff42 bl 800aa14 } /* USER CODE BEGIN CAN2_Init 2 */ /* USER CODE END CAN2_Init 2 */ } 8009b90: bf00 nop 8009b92: bd80 pop {r7, pc} 8009b94: 20000328 .word 0x20000328 8009b98: 40006800 .word 0x40006800 08009b9c : static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0; void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) { 8009b9c: b580 push {r7, lr} 8009b9e: b08e sub sp, #56 @ 0x38 8009ba0: af00 add r7, sp, #0 8009ba2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8009ba4: f107 0320 add.w r3, r7, #32 8009ba8: 2200 movs r2, #0 8009baa: 601a str r2, [r3, #0] 8009bac: 605a str r2, [r3, #4] 8009bae: 609a str r2, [r3, #8] 8009bb0: 60da str r2, [r3, #12] if(canHandle->Instance==CAN1) 8009bb2: 687b ldr r3, [r7, #4] 8009bb4: 681b ldr r3, [r3, #0] 8009bb6: 4a61 ldr r2, [pc, #388] @ (8009d3c ) 8009bb8: 4293 cmp r3, r2 8009bba: d153 bne.n 8009c64 { /* USER CODE BEGIN CAN1_MspInit 0 */ /* USER CODE END CAN1_MspInit 0 */ /* CAN1 clock enable */ HAL_RCC_CAN1_CLK_ENABLED++; 8009bbc: 4b60 ldr r3, [pc, #384] @ (8009d40 ) 8009bbe: 681b ldr r3, [r3, #0] 8009bc0: 3301 adds r3, #1 8009bc2: 4a5f ldr r2, [pc, #380] @ (8009d40 ) 8009bc4: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009bc6: 4b5e ldr r3, [pc, #376] @ (8009d40 ) 8009bc8: 681b ldr r3, [r3, #0] 8009bca: 2b01 cmp r3, #1 8009bcc: d10b bne.n 8009be6 __HAL_RCC_CAN1_CLK_ENABLE(); 8009bce: 4b5d ldr r3, [pc, #372] @ (8009d44 ) 8009bd0: 69db ldr r3, [r3, #28] 8009bd2: 4a5c ldr r2, [pc, #368] @ (8009d44 ) 8009bd4: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009bd8: 61d3 str r3, [r2, #28] 8009bda: 4b5a ldr r3, [pc, #360] @ (8009d44 ) 8009bdc: 69db ldr r3, [r3, #28] 8009bde: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009be2: 61fb str r3, [r7, #28] 8009be4: 69fb ldr r3, [r7, #28] } __HAL_RCC_GPIOD_CLK_ENABLE(); 8009be6: 4b57 ldr r3, [pc, #348] @ (8009d44 ) 8009be8: 699b ldr r3, [r3, #24] 8009bea: 4a56 ldr r2, [pc, #344] @ (8009d44 ) 8009bec: f043 0320 orr.w r3, r3, #32 8009bf0: 6193 str r3, [r2, #24] 8009bf2: 4b54 ldr r3, [pc, #336] @ (8009d44 ) 8009bf4: 699b ldr r3, [r3, #24] 8009bf6: f003 0320 and.w r3, r3, #32 8009bfa: 61bb str r3, [r7, #24] 8009bfc: 69bb ldr r3, [r7, #24] /**CAN1 GPIO Configuration PD0 ------> CAN1_RX PD1 ------> CAN1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0; 8009bfe: 2301 movs r3, #1 8009c00: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009c02: 2300 movs r3, #0 8009c04: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009c06: 2300 movs r3, #0 8009c08: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009c0a: f107 0320 add.w r3, r7, #32 8009c0e: 4619 mov r1, r3 8009c10: 484d ldr r0, [pc, #308] @ (8009d48 ) 8009c12: f005 fea9 bl 800f968 GPIO_InitStruct.Pin = GPIO_PIN_1; 8009c16: 2302 movs r3, #2 8009c18: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009c1a: 2302 movs r3, #2 8009c1c: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009c1e: 2303 movs r3, #3 8009c20: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009c22: f107 0320 add.w r3, r7, #32 8009c26: 4619 mov r1, r3 8009c28: 4847 ldr r0, [pc, #284] @ (8009d48 ) 8009c2a: f005 fe9d bl 800f968 __HAL_AFIO_REMAP_CAN1_3(); 8009c2e: 4b47 ldr r3, [pc, #284] @ (8009d4c ) 8009c30: 685b ldr r3, [r3, #4] 8009c32: 633b str r3, [r7, #48] @ 0x30 8009c34: 6b3b ldr r3, [r7, #48] @ 0x30 8009c36: f423 43c0 bic.w r3, r3, #24576 @ 0x6000 8009c3a: 633b str r3, [r7, #48] @ 0x30 8009c3c: 6b3b ldr r3, [r7, #48] @ 0x30 8009c3e: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009c42: 633b str r3, [r7, #48] @ 0x30 8009c44: 6b3b ldr r3, [r7, #48] @ 0x30 8009c46: f443 43c0 orr.w r3, r3, #24576 @ 0x6000 8009c4a: 633b str r3, [r7, #48] @ 0x30 8009c4c: 4a3f ldr r2, [pc, #252] @ (8009d4c ) 8009c4e: 6b3b ldr r3, [r7, #48] @ 0x30 8009c50: 6053 str r3, [r2, #4] /* CAN1 interrupt Init */ HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 0, 0); 8009c52: 2200 movs r2, #0 8009c54: 2100 movs r1, #0 8009c56: 2014 movs r0, #20 8009c58: f005 fcf1 bl 800f63e HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn); 8009c5c: 2014 movs r0, #20 8009c5e: f005 fd0a bl 800f676 HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); /* USER CODE BEGIN CAN2_MspInit 1 */ /* USER CODE END CAN2_MspInit 1 */ } } 8009c62: e067 b.n 8009d34 else if(canHandle->Instance==CAN2) 8009c64: 687b ldr r3, [r7, #4] 8009c66: 681b ldr r3, [r3, #0] 8009c68: 4a39 ldr r2, [pc, #228] @ (8009d50 ) 8009c6a: 4293 cmp r3, r2 8009c6c: d162 bne.n 8009d34 __HAL_RCC_CAN2_CLK_ENABLE(); 8009c6e: 4b35 ldr r3, [pc, #212] @ (8009d44 ) 8009c70: 69db ldr r3, [r3, #28] 8009c72: 4a34 ldr r2, [pc, #208] @ (8009d44 ) 8009c74: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 8009c78: 61d3 str r3, [r2, #28] 8009c7a: 4b32 ldr r3, [pc, #200] @ (8009d44 ) 8009c7c: 69db ldr r3, [r3, #28] 8009c7e: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8009c82: 617b str r3, [r7, #20] 8009c84: 697b ldr r3, [r7, #20] HAL_RCC_CAN1_CLK_ENABLED++; 8009c86: 4b2e ldr r3, [pc, #184] @ (8009d40 ) 8009c88: 681b ldr r3, [r3, #0] 8009c8a: 3301 adds r3, #1 8009c8c: 4a2c ldr r2, [pc, #176] @ (8009d40 ) 8009c8e: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009c90: 4b2b ldr r3, [pc, #172] @ (8009d40 ) 8009c92: 681b ldr r3, [r3, #0] 8009c94: 2b01 cmp r3, #1 8009c96: d10b bne.n 8009cb0 __HAL_RCC_CAN1_CLK_ENABLE(); 8009c98: 4b2a ldr r3, [pc, #168] @ (8009d44 ) 8009c9a: 69db ldr r3, [r3, #28] 8009c9c: 4a29 ldr r2, [pc, #164] @ (8009d44 ) 8009c9e: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009ca2: 61d3 str r3, [r2, #28] 8009ca4: 4b27 ldr r3, [pc, #156] @ (8009d44 ) 8009ca6: 69db ldr r3, [r3, #28] 8009ca8: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009cac: 613b str r3, [r7, #16] 8009cae: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8009cb0: 4b24 ldr r3, [pc, #144] @ (8009d44 ) 8009cb2: 699b ldr r3, [r3, #24] 8009cb4: 4a23 ldr r2, [pc, #140] @ (8009d44 ) 8009cb6: f043 0308 orr.w r3, r3, #8 8009cba: 6193 str r3, [r2, #24] 8009cbc: 4b21 ldr r3, [pc, #132] @ (8009d44 ) 8009cbe: 699b ldr r3, [r3, #24] 8009cc0: f003 0308 and.w r3, r3, #8 8009cc4: 60fb str r3, [r7, #12] 8009cc6: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_5; 8009cc8: 2320 movs r3, #32 8009cca: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009ccc: 2300 movs r3, #0 8009cce: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009cd0: 2300 movs r3, #0 8009cd2: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009cd4: f107 0320 add.w r3, r7, #32 8009cd8: 4619 mov r1, r3 8009cda: 481e ldr r0, [pc, #120] @ (8009d54 ) 8009cdc: f005 fe44 bl 800f968 GPIO_InitStruct.Pin = GPIO_PIN_6; 8009ce0: 2340 movs r3, #64 @ 0x40 8009ce2: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009ce4: 2302 movs r3, #2 8009ce6: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009ce8: 2303 movs r3, #3 8009cea: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009cec: f107 0320 add.w r3, r7, #32 8009cf0: 4619 mov r1, r3 8009cf2: 4818 ldr r0, [pc, #96] @ (8009d54 ) 8009cf4: f005 fe38 bl 800f968 __HAL_AFIO_REMAP_CAN2_ENABLE(); 8009cf8: 4b14 ldr r3, [pc, #80] @ (8009d4c ) 8009cfa: 685b ldr r3, [r3, #4] 8009cfc: 637b str r3, [r7, #52] @ 0x34 8009cfe: 6b7b ldr r3, [r7, #52] @ 0x34 8009d00: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009d04: 637b str r3, [r7, #52] @ 0x34 8009d06: 6b7b ldr r3, [r7, #52] @ 0x34 8009d08: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8009d0c: 637b str r3, [r7, #52] @ 0x34 8009d0e: 4a0f ldr r2, [pc, #60] @ (8009d4c ) 8009d10: 6b7b ldr r3, [r7, #52] @ 0x34 8009d12: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(CAN2_TX_IRQn, 0, 0); 8009d14: 2200 movs r2, #0 8009d16: 2100 movs r1, #0 8009d18: 203f movs r0, #63 @ 0x3f 8009d1a: f005 fc90 bl 800f63e HAL_NVIC_EnableIRQ(CAN2_TX_IRQn); 8009d1e: 203f movs r0, #63 @ 0x3f 8009d20: f005 fca9 bl 800f676 HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 0, 0); 8009d24: 2200 movs r2, #0 8009d26: 2100 movs r1, #0 8009d28: 2041 movs r0, #65 @ 0x41 8009d2a: f005 fc88 bl 800f63e HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); 8009d2e: 2041 movs r0, #65 @ 0x41 8009d30: f005 fca1 bl 800f676 } 8009d34: bf00 nop 8009d36: 3738 adds r7, #56 @ 0x38 8009d38: 46bd mov sp, r7 8009d3a: bd80 pop {r7, pc} 8009d3c: 40006400 .word 0x40006400 8009d40: 20000350 .word 0x20000350 8009d44: 40021000 .word 0x40021000 8009d48: 40011400 .word 0x40011400 8009d4c: 40010000 .word 0x40010000 8009d50: 40006800 .word 0x40006800 8009d54: 40010c00 .word 0x40010c00 08009d58 : #include "debug.h" ChargingConnector_t CONN; CONN_State_t connectorState; void CONN_Init(){ 8009d58: b480 push {r7} 8009d5a: af00 add r7, sp, #0 CONN.connControl = CMD_NONE; 8009d5c: 4b08 ldr r3, [pc, #32] @ (8009d80 ) 8009d5e: 2200 movs r2, #0 8009d60: 701a strb r2, [r3, #0] CONN.connState = Unknown; 8009d62: 4b07 ldr r3, [pc, #28] @ (8009d80 ) 8009d64: 2200 movs r2, #0 8009d66: 705a strb r2, [r3, #1] CONN.RequestedVoltage = PSU_MIN_VOLTAGE; 8009d68: 4b05 ldr r3, [pc, #20] @ (8009d80 ) 8009d6a: 2200 movs r2, #0 8009d6c: f062 0269 orn r2, r2, #105 @ 0x69 8009d70: 73da strb r2, [r3, #15] 8009d72: 2200 movs r2, #0 8009d74: 741a strb r2, [r3, #16] } 8009d76: bf00 nop 8009d78: 46bd mov sp, r7 8009d7a: bc80 pop {r7} 8009d7c: 4770 bx lr 8009d7e: bf00 nop 8009d80: 20000354 .word 0x20000354 08009d84 : void CONN_Loop(){ 8009d84: b580 push {r7, lr} 8009d86: af00 add r7, sp, #0 static CONN_State_t last_connState = Unknown; if(last_connState != CONN.connState){ 8009d88: 4b1a ldr r3, [pc, #104] @ (8009df4 ) 8009d8a: 785a ldrb r2, [r3, #1] 8009d8c: 4b1a ldr r3, [pc, #104] @ (8009df8 ) 8009d8e: 781b ldrb r3, [r3, #0] 8009d90: 429a cmp r2, r3 8009d92: d006 beq.n 8009da2 last_connState = CONN.connState; 8009d94: 4b17 ldr r3, [pc, #92] @ (8009df4 ) 8009d96: 785a ldrb r2, [r3, #1] 8009d98: 4b17 ldr r3, [pc, #92] @ (8009df8 ) 8009d9a: 701a strb r2, [r3, #0] CONN.connControl = CMD_NONE; 8009d9c: 4b15 ldr r3, [pc, #84] @ (8009df4 ) 8009d9e: 2200 movs r2, #0 8009da0: 701a strb r2, [r3, #0] } if(PSU0.cont_fault){ 8009da2: 4b16 ldr r3, [pc, #88] @ (8009dfc ) 8009da4: 7b1b ldrb r3, [r3, #12] 8009da6: 2b00 cmp r3, #0 8009da8: d003 beq.n 8009db2 CONN.chargingError = CONN_ERR_CONTACTOR; 8009daa: 4b12 ldr r3, [pc, #72] @ (8009df4 ) 8009dac: 2207 movs r2, #7 8009dae: 775a strb r2, [r3, #29] 8009db0: e00e b.n 8009dd0 } else if(PSU0.psu_fault){ 8009db2: 4b12 ldr r3, [pc, #72] @ (8009dfc ) 8009db4: 7b5b ldrb r3, [r3, #13] 8009db6: 2b00 cmp r3, #0 8009db8: d003 beq.n 8009dc2 CONN.chargingError = CONN_ERR_PSU_FAULT; 8009dba: 4b0e ldr r3, [pc, #56] @ (8009df4 ) 8009dbc: 220a movs r2, #10 8009dbe: 775a strb r2, [r3, #29] 8009dc0: e006 b.n 8009dd0 // } else if(!CTRL.ac_ok) { // CONN.chargingError = CONN_ERR_AC_FAULT; // } else }else if (CONN.EvConnected == 0){ 8009dc2: 4b0c ldr r3, [pc, #48] @ (8009df4 ) 8009dc4: 7f9b ldrb r3, [r3, #30] 8009dc6: 2b00 cmp r3, #0 8009dc8: d102 bne.n 8009dd0 CONN.chargingError = CONN_NO_ERROR; 8009dca: 4b0a ldr r3, [pc, #40] @ (8009df4 ) 8009dcc: 2200 movs r2, #0 8009dce: 775a strb r2, [r3, #29] } if(ED_TraceWarning(CONN.chargingError, 0)) printf("CONN%d Error: %d\n", 0, CONN.chargingError); 8009dd0: 4b08 ldr r3, [pc, #32] @ (8009df4 ) 8009dd2: 7f5b ldrb r3, [r3, #29] 8009dd4: 2100 movs r1, #0 8009dd6: 4618 mov r0, r3 8009dd8: f000 fc60 bl 800a69c 8009ddc: 4603 mov r3, r0 8009dde: 2b00 cmp r3, #0 8009de0: d006 beq.n 8009df0 8009de2: 4b04 ldr r3, [pc, #16] @ (8009df4 ) 8009de4: 7f5b ldrb r3, [r3, #29] 8009de6: 461a mov r2, r3 8009de8: 2100 movs r1, #0 8009dea: 4805 ldr r0, [pc, #20] @ (8009e00 ) 8009dec: f009 ff54 bl 8013c98 } 8009df0: bf00 nop 8009df2: bd80 pop {r7, pc} 8009df4: 20000354 .word 0x20000354 8009df8: 20000374 .word 0x20000374 8009dfc: 200008a4 .word 0x200008a4 8009e00: 08015f10 .word 0x08015f10 08009e04 : void CONN_Task(){ 8009e04: b480 push {r7} 8009e06: af00 add r7, sp, #0 /* CCS state machine is handled in serial.c. * Keep this task lightweight for scheduler compatibility. */ return; 8009e08: bf00 nop } 8009e0a: 46bd mov sp, r7 8009e0c: bc80 pop {r7} 8009e0e: 4770 bx lr 08009e10 : void CONN_SetState(CONN_State_t state){ 8009e10: b580 push {r7, lr} 8009e12: b082 sub sp, #8 8009e14: af00 add r7, sp, #0 8009e16: 4603 mov r3, r0 8009e18: 71fb strb r3, [r7, #7] if (connectorState == state) { 8009e1a: 4b41 ldr r3, [pc, #260] @ (8009f20 ) 8009e1c: 781b ldrb r3, [r3, #0] 8009e1e: 79fa ldrb r2, [r7, #7] 8009e20: 429a cmp r2, r3 8009e22: d103 bne.n 8009e2c CONN.connState = state; 8009e24: 4a3f ldr r2, [pc, #252] @ (8009f24 ) 8009e26: 79fb ldrb r3, [r7, #7] 8009e28: 7053 strb r3, [r2, #1] return; 8009e2a: e075 b.n 8009f18 } connectorState = state; 8009e2c: 4a3c ldr r2, [pc, #240] @ (8009f20 ) 8009e2e: 79fb ldrb r3, [r7, #7] 8009e30: 7013 strb r3, [r2, #0] if(connectorState == Unknown) log_printf(LOG_INFO, "Connector: Unknown\n"); 8009e32: 4b3b ldr r3, [pc, #236] @ (8009f20 ) 8009e34: 781b ldrb r3, [r3, #0] 8009e36: 2b00 cmp r3, #0 8009e38: d103 bne.n 8009e42 8009e3a: 493b ldr r1, [pc, #236] @ (8009f28 ) 8009e3c: 2007 movs r0, #7 8009e3e: f000 fabf bl 800a3c0 if(connectorState == Unplugged) log_printf(LOG_INFO, "Connector: Unplugged\n"); 8009e42: 4b37 ldr r3, [pc, #220] @ (8009f20 ) 8009e44: 781b ldrb r3, [r3, #0] 8009e46: 2b01 cmp r3, #1 8009e48: d103 bne.n 8009e52 8009e4a: 4938 ldr r1, [pc, #224] @ (8009f2c ) 8009e4c: 2007 movs r0, #7 8009e4e: f000 fab7 bl 800a3c0 if(connectorState == Disabled) log_printf(LOG_INFO, "Connector: Disabled\n"); 8009e52: 4b33 ldr r3, [pc, #204] @ (8009f20 ) 8009e54: 781b ldrb r3, [r3, #0] 8009e56: 2b02 cmp r3, #2 8009e58: d103 bne.n 8009e62 8009e5a: 4935 ldr r1, [pc, #212] @ (8009f30 ) 8009e5c: 2007 movs r0, #7 8009e5e: f000 faaf bl 800a3c0 if(connectorState == Preparing) log_printf(LOG_INFO, "Connector: Preparing\n"); 8009e62: 4b2f ldr r3, [pc, #188] @ (8009f20 ) 8009e64: 781b ldrb r3, [r3, #0] 8009e66: 2b03 cmp r3, #3 8009e68: d103 bne.n 8009e72 8009e6a: 4932 ldr r1, [pc, #200] @ (8009f34 ) 8009e6c: 2007 movs r0, #7 8009e6e: f000 faa7 bl 800a3c0 if(connectorState == AuthRequired) log_printf(LOG_INFO, "Connector: AuthRequired\n"); 8009e72: 4b2b ldr r3, [pc, #172] @ (8009f20 ) 8009e74: 781b ldrb r3, [r3, #0] 8009e76: 2b04 cmp r3, #4 8009e78: d103 bne.n 8009e82 8009e7a: 492f ldr r1, [pc, #188] @ (8009f38 ) 8009e7c: 2007 movs r0, #7 8009e7e: f000 fa9f bl 800a3c0 if(connectorState == WaitingForEnergy) log_printf(LOG_INFO, "Connector: WaitingForEnergy\n"); 8009e82: 4b27 ldr r3, [pc, #156] @ (8009f20 ) 8009e84: 781b ldrb r3, [r3, #0] 8009e86: 2b05 cmp r3, #5 8009e88: d103 bne.n 8009e92 8009e8a: 492c ldr r1, [pc, #176] @ (8009f3c ) 8009e8c: 2007 movs r0, #7 8009e8e: f000 fa97 bl 800a3c0 if(connectorState == ChargingPausedEV) log_printf(LOG_INFO, "Connector: ChargingPausedEV\n"); 8009e92: 4b23 ldr r3, [pc, #140] @ (8009f20 ) 8009e94: 781b ldrb r3, [r3, #0] 8009e96: 2b06 cmp r3, #6 8009e98: d103 bne.n 8009ea2 8009e9a: 4929 ldr r1, [pc, #164] @ (8009f40 ) 8009e9c: 2007 movs r0, #7 8009e9e: f000 fa8f bl 800a3c0 if(connectorState == ChargingPausedEVSE) log_printf(LOG_INFO, "Connector: ChargingPausedEVSE\n"); 8009ea2: 4b1f ldr r3, [pc, #124] @ (8009f20 ) 8009ea4: 781b ldrb r3, [r3, #0] 8009ea6: 2b07 cmp r3, #7 8009ea8: d103 bne.n 8009eb2 8009eaa: 4926 ldr r1, [pc, #152] @ (8009f44 ) 8009eac: 2007 movs r0, #7 8009eae: f000 fa87 bl 800a3c0 if(connectorState == Charging) log_printf(LOG_INFO, "Connector: Charging\n"); 8009eb2: 4b1b ldr r3, [pc, #108] @ (8009f20 ) 8009eb4: 781b ldrb r3, [r3, #0] 8009eb6: 2b08 cmp r3, #8 8009eb8: d103 bne.n 8009ec2 8009eba: 4923 ldr r1, [pc, #140] @ (8009f48 ) 8009ebc: 2007 movs r0, #7 8009ebe: f000 fa7f bl 800a3c0 if(connectorState == AuthTimeout) log_printf(LOG_INFO, "Connector: AuthTimeout\n"); 8009ec2: 4b17 ldr r3, [pc, #92] @ (8009f20 ) 8009ec4: 781b ldrb r3, [r3, #0] 8009ec6: 2b09 cmp r3, #9 8009ec8: d103 bne.n 8009ed2 8009eca: 4920 ldr r1, [pc, #128] @ (8009f4c ) 8009ecc: 2007 movs r0, #7 8009ece: f000 fa77 bl 800a3c0 if(connectorState == Finished) log_printf(LOG_INFO, "Connector: Finished\n"); 8009ed2: 4b13 ldr r3, [pc, #76] @ (8009f20 ) 8009ed4: 781b ldrb r3, [r3, #0] 8009ed6: 2b0a cmp r3, #10 8009ed8: d103 bne.n 8009ee2 8009eda: 491d ldr r1, [pc, #116] @ (8009f50 ) 8009edc: 2007 movs r0, #7 8009ede: f000 fa6f bl 800a3c0 if(connectorState == FinishedEVSE) log_printf(LOG_INFO, "Connector: FinishedEVSE\n"); 8009ee2: 4b0f ldr r3, [pc, #60] @ (8009f20 ) 8009ee4: 781b ldrb r3, [r3, #0] 8009ee6: 2b0b cmp r3, #11 8009ee8: d103 bne.n 8009ef2 8009eea: 491a ldr r1, [pc, #104] @ (8009f54 ) 8009eec: 2007 movs r0, #7 8009eee: f000 fa67 bl 800a3c0 if(connectorState == FinishedEV) log_printf(LOG_INFO, "Connector: FinishedEV\n"); 8009ef2: 4b0b ldr r3, [pc, #44] @ (8009f20 ) 8009ef4: 781b ldrb r3, [r3, #0] 8009ef6: 2b0c cmp r3, #12 8009ef8: d103 bne.n 8009f02 8009efa: 4917 ldr r1, [pc, #92] @ (8009f58 ) 8009efc: 2007 movs r0, #7 8009efe: f000 fa5f bl 800a3c0 if(connectorState == Replugging) log_printf(LOG_INFO, "Connector: Replugging\n"); 8009f02: 4b07 ldr r3, [pc, #28] @ (8009f20 ) 8009f04: 781b ldrb r3, [r3, #0] 8009f06: 2b0d cmp r3, #13 8009f08: d103 bne.n 8009f12 8009f0a: 4914 ldr r1, [pc, #80] @ (8009f5c ) 8009f0c: 2007 movs r0, #7 8009f0e: f000 fa57 bl 800a3c0 CONN.connState = state; 8009f12: 4a04 ldr r2, [pc, #16] @ (8009f24 ) 8009f14: 79fb ldrb r3, [r7, #7] 8009f16: 7053 strb r3, [r2, #1] } 8009f18: 3708 adds r7, #8 8009f1a: 46bd mov sp, r7 8009f1c: bd80 pop {r7, pc} 8009f1e: bf00 nop 8009f20: 20000373 .word 0x20000373 8009f24: 20000354 .word 0x20000354 8009f28: 08015f24 .word 0x08015f24 8009f2c: 08015f38 .word 0x08015f38 8009f30: 08015f50 .word 0x08015f50 8009f34: 08015f68 .word 0x08015f68 8009f38: 08015f80 .word 0x08015f80 8009f3c: 08015f9c .word 0x08015f9c 8009f40: 08015fbc .word 0x08015fbc 8009f44: 08015fdc .word 0x08015fdc 8009f48: 08015ffc .word 0x08015ffc 8009f4c: 08016014 .word 0x08016014 8009f50: 0801602c .word 0x0801602c 8009f54: 08016044 .word 0x08016044 8009f58: 08016060 .word 0x08016060 8009f5c: 08016078 .word 0x08016078 08009f60 : static int32_t cp_voltage_mv = 0; static uint8_t cp_duty = 0; CP_State_t fake_cp_state = EV_STATE_ACQUIRING; static uint32_t CP_ReadAdcChannel(uint32_t ch) { 8009f60: b580 push {r7, lr} 8009f62: b084 sub sp, #16 8009f64: af00 add r7, sp, #0 8009f66: 6078 str r0, [r7, #4] uint32_t adc = 0; 8009f68: 2300 movs r3, #0 8009f6a: 60fb str r3, [r7, #12] ADC_Select_Channel(ch); 8009f6c: 6878 ldr r0, [r7, #4] 8009f6e: f7ff fd41 bl 80099f4 HAL_ADC_Start(&hadc1); 8009f72: 4809 ldr r0, [pc, #36] @ (8009f98 ) 8009f74: f003 ff88 bl 800de88 HAL_ADC_PollForConversion(&hadc1, 10); 8009f78: 210a movs r1, #10 8009f7a: 4807 ldr r0, [pc, #28] @ (8009f98 ) 8009f7c: f004 f85e bl 800e03c adc = HAL_ADC_GetValue(&hadc1); 8009f80: 4805 ldr r0, [pc, #20] @ (8009f98 ) 8009f82: f004 f961 bl 800e248 8009f86: 60f8 str r0, [r7, #12] HAL_ADC_Stop(&hadc1); 8009f88: 4803 ldr r0, [pc, #12] @ (8009f98 ) 8009f8a: f004 f82b bl 800dfe4 return adc; 8009f8e: 68fb ldr r3, [r7, #12] } 8009f90: 4618 mov r0, r3 8009f92: 3710 adds r7, #16 8009f94: 46bd mov sp, r7 8009f96: bd80 pop {r7, pc} 8009f98: 20000274 .word 0x20000274 08009f9c : #define VREFINT_CAL_ADDR ((uint16_t*)0x1FFFF7BA) // для STM32F1! static int32_t CP_ReadVoltageMv(void) { 8009f9c: b580 push {r7, lr} 8009f9e: b084 sub sp, #16 8009fa0: af00 add r7, sp, #0 uint32_t adc = 0; 8009fa2: 2300 movs r3, #0 8009fa4: 60fb str r3, [r7, #12] int32_t v_adc_mv = 0; 8009fa6: 2300 movs r3, #0 8009fa8: 60bb str r3, [r7, #8] int32_t v_out_mv = 0; 8009faa: 2300 movs r3, #0 8009fac: 607b str r3, [r7, #4] adc = CP_ReadAdcChannel((uint32_t)4u); 8009fae: 2004 movs r0, #4 8009fb0: f7ff ffd6 bl 8009f60 8009fb4: 60f8 str r0, [r7, #12] v_adc_mv = (int32_t)((adc * 3300u) / 4095u); 8009fb6: 68fb ldr r3, [r7, #12] 8009fb8: f640 42e4 movw r2, #3300 @ 0xce4 8009fbc: fb03 f202 mul.w r2, r3, r2 8009fc0: 4b0d ldr r3, [pc, #52] @ (8009ff8 ) 8009fc2: fba3 1302 umull r1, r3, r3, r2 8009fc6: 1ad2 subs r2, r2, r3 8009fc8: 0852 lsrs r2, r2, #1 8009fca: 4413 add r3, r2 8009fcc: 0adb lsrs r3, r3, #11 8009fce: 60bb str r3, [r7, #8] v_out_mv = ((v_adc_mv - 1723) * 1000) / 130; 8009fd0: 68bb ldr r3, [r7, #8] 8009fd2: f2a3 63bb subw r3, r3, #1723 @ 0x6bb 8009fd6: f44f 727a mov.w r2, #1000 @ 0x3e8 8009fda: fb02 f303 mul.w r3, r2, r3 8009fde: 4a07 ldr r2, [pc, #28] @ (8009ffc ) 8009fe0: fb82 1203 smull r1, r2, r2, r3 8009fe4: 1192 asrs r2, r2, #6 8009fe6: 17db asrs r3, r3, #31 8009fe8: 1ad3 subs r3, r2, r3 8009fea: 607b str r3, [r7, #4] return v_out_mv; 8009fec: 687b ldr r3, [r7, #4] } 8009fee: 4618 mov r0, r3 8009ff0: 3710 adds r7, #16 8009ff2: 46bd mov sp, r7 8009ff4: bd80 pop {r7, pc} 8009ff6: bf00 nop 8009ff8: 00100101 .word 0x00100101 8009ffc: 7e07e07f .word 0x7e07e07f 0800a000 : void CP_Init(void) { 800a000: b580 push {r7, lr} 800a002: af00 add r7, sp, #0 /* TIM3_CH2 (PA7): set 1kHz PWM like original CCS logic. */ htim3.Instance->PSC = 160 - 1; 800a004: 4b0e ldr r3, [pc, #56] @ (800a040 ) 800a006: 681b ldr r3, [r3, #0] 800a008: 229f movs r2, #159 @ 0x9f 800a00a: 629a str r2, [r3, #40] @ 0x28 htim3.Instance->ARR = MAX_DUTY - 1; 800a00c: 4b0c ldr r3, [pc, #48] @ (800a040 ) 800a00e: 681b ldr r3, [r3, #0] 800a010: f240 12c1 movw r2, #449 @ 0x1c1 800a014: 62da str r2, [r3, #44] @ 0x2c #if DUTY_INVERT == 0 htim3.Instance->CCR2 = MAX_DUTY; 800a016: 4b0a ldr r3, [pc, #40] @ (800a040 ) 800a018: 681b ldr r3, [r3, #0] 800a01a: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a01e: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = MAX_DUTY + 5; 800a020: 4b07 ldr r3, [pc, #28] @ (800a040 ) 800a022: 681b ldr r3, [r3, #0] 800a024: f240 12c7 movw r2, #455 @ 0x1c7 800a028: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = 0; htim3.Instance->CCR1 = 0; #endif HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_2); 800a02a: 2104 movs r1, #4 800a02c: 4804 ldr r0, [pc, #16] @ (800a040 ) 800a02e: f007 f9b9 bl 80113a4 HAL_TIM_OC_Start_IT(&htim3, TIM_CHANNEL_1); 800a032: 2100 movs r1, #0 800a034: 4802 ldr r0, [pc, #8] @ (800a040 ) 800a036: f007 f867 bl 8011108 } 800a03a: bf00 nop 800a03c: bd80 pop {r7, pc} 800a03e: bf00 nop 800a040: 20001054 .word 0x20001054 0800a044 : void CP_SetDuty(uint8_t percentage) { 800a044: b480 push {r7} 800a046: b085 sub sp, #20 800a048: af00 add r7, sp, #0 800a04a: 4603 mov r3, r0 800a04c: 71fb strb r3, [r7, #7] uint32_t pwmduty = MAX_DUTY * percentage / 100; 800a04e: 79fb ldrb r3, [r7, #7] 800a050: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a054: fb02 f303 mul.w r3, r2, r3 800a058: 4a0b ldr r2, [pc, #44] @ (800a088 ) 800a05a: fb82 1203 smull r1, r2, r2, r3 800a05e: 1152 asrs r2, r2, #5 800a060: 17db asrs r3, r3, #31 800a062: 1ad3 subs r3, r2, r3 800a064: 60fb str r3, [r7, #12] cp_duty = percentage; 800a066: 4a09 ldr r2, [pc, #36] @ (800a08c ) 800a068: 79fb ldrb r3, [r7, #7] 800a06a: 7013 strb r3, [r2, #0] #if DUTY_INVERT == 0 htim3.Instance->CCR2 = pwmduty; 800a06c: 4b08 ldr r3, [pc, #32] @ (800a090 ) 800a06e: 681b ldr r3, [r3, #0] 800a070: 68fa ldr r2, [r7, #12] 800a072: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = 0 + 1; 800a074: 4b06 ldr r3, [pc, #24] @ (800a090 ) 800a076: 681b ldr r3, [r3, #0] 800a078: 2201 movs r2, #1 800a07a: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = MAX_DUTY - pwmduty; htim3.Instance->CCR1 = MAX_DUTY - pwmduty + 5; #endif } 800a07c: bf00 nop 800a07e: 3714 adds r7, #20 800a080: 46bd mov sp, r7 800a082: bc80 pop {r7} 800a084: 4770 bx lr 800a086: bf00 nop 800a088: 51eb851f .word 0x51eb851f 800a08c: 2000037c .word 0x2000037c 800a090: 20001054 .word 0x20001054 0800a094 : uint8_t CP_GetDuty(void) { 800a094: b480 push {r7} 800a096: af00 add r7, sp, #0 return cp_duty; 800a098: 4b02 ldr r3, [pc, #8] @ (800a0a4 ) 800a09a: 781b ldrb r3, [r3, #0] } 800a09c: 4618 mov r0, r3 800a09e: 46bd mov sp, r7 800a0a0: bc80 pop {r7} 800a0a2: 4770 bx lr 800a0a4: 2000037c .word 0x2000037c 0800a0a8 : int32_t CP_GetVoltage(void) { return cp_voltage_mv; } CP_State_t CP_GetState(void) { 800a0a8: b480 push {r7} 800a0aa: b083 sub sp, #12 800a0ac: af00 add r7, sp, #0 int32_t voltage_real = cp_voltage_mv; 800a0ae: 4b24 ldr r3, [pc, #144] @ (800a140 ) 800a0b0: 681b ldr r3, [r3, #0] 800a0b2: 607b str r3, [r7, #4] if(fake_cp_state != EV_STATE_ACQUIRING) { 800a0b4: 4b23 ldr r3, [pc, #140] @ (800a144 ) 800a0b6: 781b ldrb r3, [r3, #0] 800a0b8: 2b06 cmp r3, #6 800a0ba: d002 beq.n 800a0c2 return fake_cp_state; 800a0bc: 4b21 ldr r3, [pc, #132] @ (800a144 ) 800a0be: 781b ldrb r3, [r3, #0] 800a0c0: e038 b.n 800a134 } if (voltage_real >= (12000-1000)) { 800a0c2: 687b ldr r3, [r7, #4] 800a0c4: f642 22f7 movw r2, #10999 @ 0x2af7 800a0c8: 4293 cmp r3, r2 800a0ca: dd01 ble.n 800a0d0 return EV_STATE_A_IDLE; 800a0cc: 2300 movs r3, #0 800a0ce: e031 b.n 800a134 } else if (voltage_real >= (9000-1000) && voltage_real <= (9000+1000)) { 800a0d0: 687b ldr r3, [r7, #4] 800a0d2: f5b3 5ffa cmp.w r3, #8000 @ 0x1f40 800a0d6: db06 blt.n 800a0e6 800a0d8: 687b ldr r3, [r7, #4] 800a0da: f242 7210 movw r2, #10000 @ 0x2710 800a0de: 4293 cmp r3, r2 800a0e0: dc01 bgt.n 800a0e6 return EV_STATE_B_CONN_PREP; 800a0e2: 2301 movs r3, #1 800a0e4: e026 b.n 800a134 } else if (voltage_real >= (6000-1000) && voltage_real <= (6000+1000)) { 800a0e6: 687b ldr r3, [r7, #4] 800a0e8: f241 3287 movw r2, #4999 @ 0x1387 800a0ec: 4293 cmp r3, r2 800a0ee: dd06 ble.n 800a0fe 800a0f0: 687b ldr r3, [r7, #4] 800a0f2: f641 3258 movw r2, #7000 @ 0x1b58 800a0f6: 4293 cmp r3, r2 800a0f8: dc01 bgt.n 800a0fe return EV_STATE_C_CONN_ACTIVE; 800a0fa: 2302 movs r3, #2 800a0fc: e01a b.n 800a134 } else if (voltage_real >= (3000-1000) && voltage_real <= (3000 + 1000)) { 800a0fe: 687b ldr r3, [r7, #4] 800a100: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800a104: db05 blt.n 800a112 800a106: 687b ldr r3, [r7, #4] 800a108: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800a10c: dc01 bgt.n 800a112 return EV_STATE_D_CONN_ACT_VENT; 800a10e: 2303 movs r3, #3 800a110: e010 b.n 800a134 } else if (voltage_real >= (0-1000) && voltage_real <= (0+2000)){ 800a112: 687b ldr r3, [r7, #4] 800a114: f513 7f7a cmn.w r3, #1000 @ 0x3e8 800a118: db05 blt.n 800a126 800a11a: 687b ldr r3, [r7, #4] 800a11c: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800a120: dc01 bgt.n 800a126 return EV_STATE_E_NO_POWER; 800a122: 2304 movs r3, #4 800a124: e006 b.n 800a134 } else if (voltage_real <= (-12000+1000)) { 800a126: 687b ldr r3, [r7, #4] 800a128: 4a07 ldr r2, [pc, #28] @ (800a148 ) 800a12a: 4293 cmp r3, r2 800a12c: da01 bge.n 800a132 return EV_STATE_F_ERROR; 800a12e: 2305 movs r3, #5 800a130: e000 b.n 800a134 } else { return EV_STATE_ACQUIRING; 800a132: 2306 movs r3, #6 } } 800a134: 4618 mov r0, r3 800a136: 370c adds r7, #12 800a138: 46bd mov sp, r7 800a13a: bc80 pop {r7} 800a13c: 4770 bx lr 800a13e: bf00 nop 800a140: 20000378 .word 0x20000378 800a144: 20000004 .word 0x20000004 800a148: ffffd509 .word 0xffffd509 0800a14c : void CP_Loop(void) { (void)CP_GetState(); } void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 800a14c: b580 push {r7, lr} 800a14e: b082 sub sp, #8 800a150: af00 add r7, sp, #0 800a152: 6078 str r0, [r7, #4] if (htim->Instance == TIM3 && htim->Channel == HAL_TIM_ACTIVE_CHANNEL_1) { 800a154: 687b ldr r3, [r7, #4] 800a156: 681b ldr r3, [r3, #0] 800a158: 4a0b ldr r2, [pc, #44] @ (800a188 ) 800a15a: 4293 cmp r3, r2 800a15c: d111 bne.n 800a182 800a15e: 687b ldr r3, [r7, #4] 800a160: 7f1b ldrb r3, [r3, #28] 800a162: 2b01 cmp r3, #1 800a164: d10d bne.n 800a182 if (ADC_TryLock() == 0u) { 800a166: f7ff fc61 bl 8009a2c 800a16a: 4603 mov r3, r0 800a16c: 2b00 cmp r3, #0 800a16e: d007 beq.n 800a180 return; } cp_voltage_mv = CP_ReadVoltageMv(); 800a170: f7ff ff14 bl 8009f9c 800a174: 4603 mov r3, r0 800a176: 4a05 ldr r2, [pc, #20] @ (800a18c ) 800a178: 6013 str r3, [r2, #0] ADC_Unlock(); 800a17a: f7ff fc89 bl 8009a90 800a17e: e000 b.n 800a182 return; 800a180: bf00 nop } } 800a182: 3708 adds r7, #8 800a184: 46bd mov sp, r7 800a186: bd80 pop {r7, pc} 800a188: 40000400 .word 0x40000400 800a18c: 20000378 .word 0x20000378 0800a190 : CRC_HandleTypeDef hcrc; /* CRC init function */ void MX_CRC_Init(void) { 800a190: b580 push {r7, lr} 800a192: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 800a194: 4b06 ldr r3, [pc, #24] @ (800a1b0 ) 800a196: 4a07 ldr r2, [pc, #28] @ (800a1b4 ) 800a198: 601a str r2, [r3, #0] if (HAL_CRC_Init(&hcrc) != HAL_OK) 800a19a: 4805 ldr r0, [pc, #20] @ (800a1b0 ) 800a19c: f005 fa85 bl 800f6aa 800a1a0: 4603 mov r3, r0 800a1a2: 2b00 cmp r3, #0 800a1a4: d001 beq.n 800a1aa { Error_Handler(); 800a1a6: f000 fc35 bl 800aa14 } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 800a1aa: bf00 nop 800a1ac: bd80 pop {r7, pc} 800a1ae: bf00 nop 800a1b0: 20000380 .word 0x20000380 800a1b4: 40023000 .word 0x40023000 0800a1b8 : void HAL_CRC_MspInit(CRC_HandleTypeDef* crcHandle) { 800a1b8: b480 push {r7} 800a1ba: b085 sub sp, #20 800a1bc: af00 add r7, sp, #0 800a1be: 6078 str r0, [r7, #4] if(crcHandle->Instance==CRC) 800a1c0: 687b ldr r3, [r7, #4] 800a1c2: 681b ldr r3, [r3, #0] 800a1c4: 4a09 ldr r2, [pc, #36] @ (800a1ec ) 800a1c6: 4293 cmp r3, r2 800a1c8: d10b bne.n 800a1e2 { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* CRC clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 800a1ca: 4b09 ldr r3, [pc, #36] @ (800a1f0 ) 800a1cc: 695b ldr r3, [r3, #20] 800a1ce: 4a08 ldr r2, [pc, #32] @ (800a1f0 ) 800a1d0: f043 0340 orr.w r3, r3, #64 @ 0x40 800a1d4: 6153 str r3, [r2, #20] 800a1d6: 4b06 ldr r3, [pc, #24] @ (800a1f0 ) 800a1d8: 695b ldr r3, [r3, #20] 800a1da: f003 0340 and.w r3, r3, #64 @ 0x40 800a1de: 60fb str r3, [r7, #12] 800a1e0: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 800a1e2: bf00 nop 800a1e4: 3714 adds r7, #20 800a1e6: 46bd mov sp, r7 800a1e8: bc80 pop {r7} 800a1ea: 4770 bx lr 800a1ec: 40023000 .word 0x40023000 800a1f0: 40021000 .word 0x40021000 0800a1f4 <_write>: #if defined(__GNUC__) int _write(int fd, char * ptr, int len) { 800a1f4: b580 push {r7, lr} 800a1f6: b084 sub sp, #16 800a1f8: af00 add r7, sp, #0 800a1fa: 60f8 str r0, [r7, #12] 800a1fc: 60b9 str r1, [r7, #8] 800a1fe: 607a str r2, [r7, #4] debug_buffer_add((const uint8_t*)ptr, len); 800a200: 687b ldr r3, [r7, #4] 800a202: b29b uxth r3, r3 800a204: 4619 mov r1, r3 800a206: 68b8 ldr r0, [r7, #8] 800a208: f000 f806 bl 800a218 return len; 800a20c: 687b ldr r3, [r7, #4] } 800a20e: 4618 mov r0, r3 800a210: 3710 adds r7, #16 800a212: 46bd mov sp, r7 800a214: bd80 pop {r7, pc} ... 0800a218 : #endif // Добавляет данные в кольцевой буфер void debug_buffer_add(const uint8_t* data, uint16_t len) { 800a218: b480 push {r7} 800a21a: b085 sub sp, #20 800a21c: af00 add r7, sp, #0 800a21e: 6078 str r0, [r7, #4] 800a220: 460b mov r3, r1 800a222: 807b strh r3, [r7, #2] __ASM volatile ("cpsid i" : : : "memory"); 800a224: b672 cpsid i } 800a226: bf00 nop __disable_irq(); for (uint16_t i = 0; i < len; i++) { 800a228: 2300 movs r3, #0 800a22a: 81fb strh r3, [r7, #14] 800a22c: e045 b.n 800a2ba // Если буфер полон, перезаписываем старые данные if (debug_buffer.count >= DEBUG_BUFFER_SIZE) { 800a22e: 4b28 ldr r3, [pc, #160] @ (800a2d0 ) 800a230: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a234: b29b uxth r3, r3 800a236: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800a23a: d318 bcc.n 800a26e debug_buffer.read_index = (debug_buffer.read_index + 1) % DEBUG_BUFFER_SIZE; 800a23c: 4b24 ldr r3, [pc, #144] @ (800a2d0 ) 800a23e: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a242: b29b uxth r3, r3 800a244: 3301 adds r3, #1 800a246: 425a negs r2, r3 800a248: f3c3 0309 ubfx r3, r3, #0, #10 800a24c: f3c2 0209 ubfx r2, r2, #0, #10 800a250: bf58 it pl 800a252: 4253 negpl r3, r2 800a254: b29a uxth r2, r3 800a256: 4b1e ldr r3, [pc, #120] @ (800a2d0 ) 800a258: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count--; 800a25c: 4b1c ldr r3, [pc, #112] @ (800a2d0 ) 800a25e: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a262: b29b uxth r3, r3 800a264: 3b01 subs r3, #1 800a266: b29a uxth r2, r3 800a268: 4b19 ldr r3, [pc, #100] @ (800a2d0 ) 800a26a: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 } debug_buffer.buffer[debug_buffer.write_index] = data[i]; 800a26e: 89fb ldrh r3, [r7, #14] 800a270: 687a ldr r2, [r7, #4] 800a272: 4413 add r3, r2 800a274: 4a16 ldr r2, [pc, #88] @ (800a2d0 ) 800a276: f8b2 2400 ldrh.w r2, [r2, #1024] @ 0x400 800a27a: b292 uxth r2, r2 800a27c: 7819 ldrb r1, [r3, #0] 800a27e: 4b14 ldr r3, [pc, #80] @ (800a2d0 ) 800a280: 5499 strb r1, [r3, r2] debug_buffer.write_index = (debug_buffer.write_index + 1) % DEBUG_BUFFER_SIZE; 800a282: 4b13 ldr r3, [pc, #76] @ (800a2d0 ) 800a284: f8b3 3400 ldrh.w r3, [r3, #1024] @ 0x400 800a288: b29b uxth r3, r3 800a28a: 3301 adds r3, #1 800a28c: 425a negs r2, r3 800a28e: f3c3 0309 ubfx r3, r3, #0, #10 800a292: f3c2 0209 ubfx r2, r2, #0, #10 800a296: bf58 it pl 800a298: 4253 negpl r3, r2 800a29a: b29a uxth r2, r3 800a29c: 4b0c ldr r3, [pc, #48] @ (800a2d0 ) 800a29e: f8a3 2400 strh.w r2, [r3, #1024] @ 0x400 debug_buffer.count++; 800a2a2: 4b0b ldr r3, [pc, #44] @ (800a2d0 ) 800a2a4: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a2a8: b29b uxth r3, r3 800a2aa: 3301 adds r3, #1 800a2ac: b29a uxth r2, r3 800a2ae: 4b08 ldr r3, [pc, #32] @ (800a2d0 ) 800a2b0: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 for (uint16_t i = 0; i < len; i++) { 800a2b4: 89fb ldrh r3, [r7, #14] 800a2b6: 3301 adds r3, #1 800a2b8: 81fb strh r3, [r7, #14] 800a2ba: 89fa ldrh r2, [r7, #14] 800a2bc: 887b ldrh r3, [r7, #2] 800a2be: 429a cmp r2, r3 800a2c0: d3b5 bcc.n 800a22e __ASM volatile ("cpsie i" : : : "memory"); 800a2c2: b662 cpsie i } 800a2c4: bf00 nop } __enable_irq(); } 800a2c6: bf00 nop 800a2c8: 3714 adds r7, #20 800a2ca: 46bd mov sp, r7 800a2cc: bc80 pop {r7} 800a2ce: 4770 bx lr 800a2d0: 20000388 .word 0x20000388 0800a2d4 : // Возвращает количество доступных данных в буфере uint16_t debug_buffer_available(void) { 800a2d4: b480 push {r7} 800a2d6: b083 sub sp, #12 800a2d8: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a2da: b672 cpsid i } 800a2dc: bf00 nop __disable_irq(); uint16_t count = debug_buffer.count; 800a2de: 4b06 ldr r3, [pc, #24] @ (800a2f8 ) 800a2e0: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a2e4: 80fb strh r3, [r7, #6] __ASM volatile ("cpsie i" : : : "memory"); 800a2e6: b662 cpsie i } 800a2e8: bf00 nop __enable_irq(); return count; 800a2ea: 88fb ldrh r3, [r7, #6] } 800a2ec: 4618 mov r0, r3 800a2ee: 370c adds r7, #12 800a2f0: 46bd mov sp, r7 800a2f2: bc80 pop {r7} 800a2f4: 4770 bx lr 800a2f6: bf00 nop 800a2f8: 20000388 .word 0x20000388 0800a2fc : // Отправляет один пакет данных из буфера через SC_SendPacket (не более 250 байт) void debug_buffer_send(void) { 800a2fc: b580 push {r7, lr} 800a2fe: b082 sub sp, #8 800a300: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a302: b672 cpsid i } 800a304: bf00 nop __disable_irq(); // Если буфер пуст, ничего не делаем if (debug_buffer.count == 0) { 800a306: 4b2d ldr r3, [pc, #180] @ (800a3bc ) 800a308: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a30c: b29b uxth r3, r3 800a30e: 2b00 cmp r3, #0 800a310: d102 bne.n 800a318 __ASM volatile ("cpsie i" : : : "memory"); 800a312: b662 cpsie i } 800a314: bf00 nop __enable_irq(); return; 800a316: e04e b.n 800a3b6 } // Определяем сколько байт можно отправить (не более 250) uint16_t bytes_to_send = debug_buffer.count; 800a318: 4b28 ldr r3, [pc, #160] @ (800a3bc ) 800a31a: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a31e: 80fb strh r3, [r7, #6] if (bytes_to_send > DEBUG_BUFFER_MAX_COUNT) { 800a320: 88fb ldrh r3, [r7, #6] 800a322: 2b80 cmp r3, #128 @ 0x80 800a324: d901 bls.n 800a32a bytes_to_send = DEBUG_BUFFER_MAX_COUNT; 800a326: 2380 movs r3, #128 @ 0x80 800a328: 80fb strh r3, [r7, #6] } // Вычисляем сколько байт до конца буфера uint16_t bytes_to_end = DEBUG_BUFFER_SIZE - debug_buffer.read_index; 800a32a: 4b24 ldr r3, [pc, #144] @ (800a3bc ) 800a32c: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a330: b29b uxth r3, r3 800a332: f5c3 6380 rsb r3, r3, #1024 @ 0x400 800a336: 80bb strh r3, [r7, #4] // Отправляем только непрерывный блок (до конца буфера или до bytes_to_send) if (bytes_to_send > bytes_to_end) { 800a338: 88fa ldrh r2, [r7, #6] 800a33a: 88bb ldrh r3, [r7, #4] 800a33c: 429a cmp r2, r3 800a33e: d901 bls.n 800a344 bytes_to_send = bytes_to_end; 800a340: 88bb ldrh r3, [r7, #4] 800a342: 80fb strh r3, [r7, #6] } // Отправляем данные напрямую из буфера if(bytes_to_send == debug_buffer.count){ 800a344: 4b1d ldr r3, [pc, #116] @ (800a3bc ) 800a346: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a34a: b29b uxth r3, r3 800a34c: 88fa ldrh r2, [r7, #6] 800a34e: 429a cmp r2, r3 800a350: d10c bne.n 800a36c SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG); 800a352: 4b1a ldr r3, [pc, #104] @ (800a3bc ) 800a354: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a358: b29b uxth r3, r3 800a35a: 461a mov r2, r3 800a35c: 4b17 ldr r3, [pc, #92] @ (800a3bc ) 800a35e: 4413 add r3, r2 800a360: 88f9 ldrh r1, [r7, #6] 800a362: 2250 movs r2, #80 @ 0x50 800a364: 4618 mov r0, r3 800a366: f002 fb87 bl 800ca78 800a36a: e00b b.n 800a384 }else{ SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG_CONTINUE); 800a36c: 4b13 ldr r3, [pc, #76] @ (800a3bc ) 800a36e: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a372: b29b uxth r3, r3 800a374: 461a mov r2, r3 800a376: 4b11 ldr r3, [pc, #68] @ (800a3bc ) 800a378: 4413 add r3, r2 800a37a: 88f9 ldrh r1, [r7, #6] 800a37c: 2251 movs r2, #81 @ 0x51 800a37e: 4618 mov r0, r3 800a380: f002 fb7a bl 800ca78 } debug_buffer.read_index = (debug_buffer.read_index + bytes_to_send) % DEBUG_BUFFER_SIZE; 800a384: 4b0d ldr r3, [pc, #52] @ (800a3bc ) 800a386: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a38a: b29a uxth r2, r3 800a38c: 88fb ldrh r3, [r7, #6] 800a38e: 4413 add r3, r2 800a390: b29b uxth r3, r3 800a392: f3c3 0309 ubfx r3, r3, #0, #10 800a396: b29a uxth r2, r3 800a398: 4b08 ldr r3, [pc, #32] @ (800a3bc ) 800a39a: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count -= bytes_to_send; 800a39e: 4b07 ldr r3, [pc, #28] @ (800a3bc ) 800a3a0: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a3a4: b29a uxth r2, r3 800a3a6: 88fb ldrh r3, [r7, #6] 800a3a8: 1ad3 subs r3, r2, r3 800a3aa: b29a uxth r2, r3 800a3ac: 4b03 ldr r3, [pc, #12] @ (800a3bc ) 800a3ae: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 __ASM volatile ("cpsie i" : : : "memory"); 800a3b2: b662 cpsie i } 800a3b4: bf00 nop __enable_irq(); } 800a3b6: 3708 adds r7, #8 800a3b8: 46bd mov sp, r7 800a3ba: bd80 pop {r7, pc} 800a3bc: 20000388 .word 0x20000388 0800a3c0 : #define LOG_BUFFER_SIZE 128 uint8_t log_buffer[LOG_BUFFER_SIZE]; // Кастомный printf с приоритетом лога int log_printf(LogLevel_t level, const char *format, ...) { 800a3c0: b40e push {r1, r2, r3} 800a3c2: b580 push {r7, lr} 800a3c4: b085 sub sp, #20 800a3c6: af00 add r7, sp, #0 800a3c8: 4603 mov r3, r0 800a3ca: 71fb strb r3, [r7, #7] va_list args; int result; // Добавляем приоритет первым байтом log_buffer[0] = (uint8_t)level; 800a3cc: 4a15 ldr r2, [pc, #84] @ (800a424 ) 800a3ce: 79fb ldrb r3, [r7, #7] 800a3d0: 7013 strb r3, [r2, #0] // Форматируем строку начиная со второго байта va_start(args, format); 800a3d2: f107 0320 add.w r3, r7, #32 800a3d6: 60bb str r3, [r7, #8] result = vsnprintf((char*)&log_buffer[1], LOG_BUFFER_SIZE - 2, format, args); 800a3d8: 68bb ldr r3, [r7, #8] 800a3da: 69fa ldr r2, [r7, #28] 800a3dc: 217e movs r1, #126 @ 0x7e 800a3de: 4812 ldr r0, [pc, #72] @ (800a428 ) 800a3e0: f009 fc2e bl 8013c40 800a3e4: 60f8 str r0, [r7, #12] va_end(args); // Проверяем, не переполнился ли буфер if (result < 0) { 800a3e6: 68fb ldr r3, [r7, #12] 800a3e8: 2b00 cmp r3, #0 800a3ea: da01 bge.n 800a3f0 return result; 800a3ec: 68fb ldr r3, [r7, #12] 800a3ee: e012 b.n 800a416 } // Ограничиваем размер, чтобы оставить место для нуль-терминатора if (result >= (LOG_BUFFER_SIZE - 2)) { 800a3f0: 68fb ldr r3, [r7, #12] 800a3f2: 2b7d cmp r3, #125 @ 0x7d 800a3f4: dd01 ble.n 800a3fa result = LOG_BUFFER_SIZE - 2; 800a3f6: 237e movs r3, #126 @ 0x7e 800a3f8: 60fb str r3, [r7, #12] } // Добавляем нуль-терминатор в конец log_buffer[result + 1] = '\0'; 800a3fa: 68fb ldr r3, [r7, #12] 800a3fc: 3301 adds r3, #1 800a3fe: 4a09 ldr r2, [pc, #36] @ (800a424 ) 800a400: 2100 movs r1, #0 800a402: 54d1 strb r1, [r2, r3] // Отправляем в буфер (приоритет + строка + нуль-терминатор) debug_buffer_add(log_buffer, result + 2); 800a404: 68fb ldr r3, [r7, #12] 800a406: b29b uxth r3, r3 800a408: 3302 adds r3, #2 800a40a: b29b uxth r3, r3 800a40c: 4619 mov r1, r3 800a40e: 4805 ldr r0, [pc, #20] @ (800a424 ) 800a410: f7ff ff02 bl 800a218 return result; 800a414: 68fb ldr r3, [r7, #12] } 800a416: 4618 mov r0, r3 800a418: 3714 adds r7, #20 800a41a: 46bd mov sp, r7 800a41c: e8bd 4080 ldmia.w sp!, {r7, lr} 800a420: b003 add sp, #12 800a422: 4770 bx lr 800a424: 20000790 .word 0x20000790 800a428: 20000791 .word 0x20000791 0800a42c : * EXTI PB8 ------> I2C1_SCL PB9 ------> I2C1_SDA */ void MX_GPIO_Init(void) { 800a42c: b580 push {r7, lr} 800a42e: b08a sub sp, #40 @ 0x28 800a430: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800a432: f107 0314 add.w r3, r7, #20 800a436: 2200 movs r2, #0 800a438: 601a str r2, [r3, #0] 800a43a: 605a str r2, [r3, #4] 800a43c: 609a str r2, [r3, #8] 800a43e: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 800a440: 4b7d ldr r3, [pc, #500] @ (800a638 ) 800a442: 699b ldr r3, [r3, #24] 800a444: 4a7c ldr r2, [pc, #496] @ (800a638 ) 800a446: f043 0310 orr.w r3, r3, #16 800a44a: 6193 str r3, [r2, #24] 800a44c: 4b7a ldr r3, [pc, #488] @ (800a638 ) 800a44e: 699b ldr r3, [r3, #24] 800a450: f003 0310 and.w r3, r3, #16 800a454: 613b str r3, [r7, #16] 800a456: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800a458: 4b77 ldr r3, [pc, #476] @ (800a638 ) 800a45a: 699b ldr r3, [r3, #24] 800a45c: 4a76 ldr r2, [pc, #472] @ (800a638 ) 800a45e: f043 0304 orr.w r3, r3, #4 800a462: 6193 str r3, [r2, #24] 800a464: 4b74 ldr r3, [pc, #464] @ (800a638 ) 800a466: 699b ldr r3, [r3, #24] 800a468: f003 0304 and.w r3, r3, #4 800a46c: 60fb str r3, [r7, #12] 800a46e: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 800a470: 4b71 ldr r3, [pc, #452] @ (800a638 ) 800a472: 699b ldr r3, [r3, #24] 800a474: 4a70 ldr r2, [pc, #448] @ (800a638 ) 800a476: f043 0308 orr.w r3, r3, #8 800a47a: 6193 str r3, [r2, #24] 800a47c: 4b6e ldr r3, [pc, #440] @ (800a638 ) 800a47e: 699b ldr r3, [r3, #24] 800a480: f003 0308 and.w r3, r3, #8 800a484: 60bb str r3, [r7, #8] 800a486: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOE_CLK_ENABLE(); 800a488: 4b6b ldr r3, [pc, #428] @ (800a638 ) 800a48a: 699b ldr r3, [r3, #24] 800a48c: 4a6a ldr r2, [pc, #424] @ (800a638 ) 800a48e: f043 0340 orr.w r3, r3, #64 @ 0x40 800a492: 6193 str r3, [r2, #24] 800a494: 4b68 ldr r3, [pc, #416] @ (800a638 ) 800a496: 699b ldr r3, [r3, #24] 800a498: f003 0340 and.w r3, r3, #64 @ 0x40 800a49c: 607b str r3, [r7, #4] 800a49e: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 800a4a0: 4b65 ldr r3, [pc, #404] @ (800a638 ) 800a4a2: 699b ldr r3, [r3, #24] 800a4a4: 4a64 ldr r2, [pc, #400] @ (800a638 ) 800a4a6: f043 0320 orr.w r3, r3, #32 800a4aa: 6193 str r3, [r2, #24] 800a4ac: 4b62 ldr r3, [pc, #392] @ (800a638 ) 800a4ae: 699b ldr r3, [r3, #24] 800a4b0: f003 0320 and.w r3, r3, #32 800a4b4: 603b str r3, [r7, #0] 800a4b6: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin, GPIO_PIN_RESET); 800a4b8: 2200 movs r2, #0 800a4ba: 2138 movs r1, #56 @ 0x38 800a4bc: 485f ldr r0, [pc, #380] @ (800a63c ) 800a4be: f005 fbee bl 800fc9e /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a4c2: 2200 movs r2, #0 800a4c4: f44f 51f8 mov.w r1, #7936 @ 0x1f00 800a4c8: 485d ldr r0, [pc, #372] @ (800a640 ) 800a4ca: f005 fbe8 bl 800fc9e |RELAY5_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, GPIO_PIN_RESET); 800a4ce: 2200 movs r2, #0 800a4d0: f44f 4100 mov.w r1, #32768 @ 0x8000 800a4d4: 485b ldr r0, [pc, #364] @ (800a644 ) 800a4d6: f005 fbe2 bl 800fc9e /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, RELAY_DC_Pin|USART2_DIR_Pin, GPIO_PIN_RESET); 800a4da: 2200 movs r2, #0 800a4dc: 2118 movs r1, #24 800a4de: 485a ldr r0, [pc, #360] @ (800a648 ) 800a4e0: f005 fbdd bl 800fc9e /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(EE_WP_GPIO_Port, EE_WP_Pin, GPIO_PIN_RESET); 800a4e4: 2200 movs r2, #0 800a4e6: 2180 movs r1, #128 @ 0x80 800a4e8: 4858 ldr r0, [pc, #352] @ (800a64c ) 800a4ea: f005 fbd8 bl 800fc9e /*Configure GPIO pins : RELAY_CP_Pin LOCK_A_Pin LOCK_B_Pin */ GPIO_InitStruct.Pin = RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin; 800a4ee: 2338 movs r3, #56 @ 0x38 800a4f0: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a4f2: 2301 movs r3, #1 800a4f4: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a4f6: 2300 movs r3, #0 800a4f8: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a4fa: 2302 movs r3, #2 800a4fc: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800a4fe: f107 0314 add.w r3, r7, #20 800a502: 4619 mov r1, r3 800a504: 484d ldr r0, [pc, #308] @ (800a63c ) 800a506: f005 fa2f bl 800f968 /*Configure GPIO pin : IN_SW0_Pin */ GPIO_InitStruct.Pin = IN_SW0_Pin; 800a50a: 2302 movs r3, #2 800a50c: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a50e: 2300 movs r3, #0 800a510: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a512: 2300 movs r3, #0 800a514: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW0_GPIO_Port, &GPIO_InitStruct); 800a516: f107 0314 add.w r3, r7, #20 800a51a: 4619 mov r1, r3 800a51c: 4849 ldr r0, [pc, #292] @ (800a644 ) 800a51e: f005 fa23 bl 800f968 /*Configure GPIO pin : IN_SW1_Pin */ GPIO_InitStruct.Pin = IN_SW1_Pin; 800a522: 2304 movs r3, #4 800a524: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a526: 2300 movs r3, #0 800a528: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 800a52a: 2302 movs r3, #2 800a52c: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW1_GPIO_Port, &GPIO_InitStruct); 800a52e: f107 0314 add.w r3, r7, #20 800a532: 4619 mov r1, r3 800a534: 4843 ldr r0, [pc, #268] @ (800a644 ) 800a536: f005 fa17 bl 800f968 /*Configure GPIO pins : IN0_Pin AC_OK_Pin ISO_IN_Pin */ GPIO_InitStruct.Pin = IN0_Pin|AC_OK_Pin|ISO_IN_Pin; 800a53a: f244 0382 movw r3, #16514 @ 0x4082 800a53e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a540: 2300 movs r3, #0 800a542: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a544: 2300 movs r3, #0 800a546: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a548: f107 0314 add.w r3, r7, #20 800a54c: 4619 mov r1, r3 800a54e: 483c ldr r0, [pc, #240] @ (800a640 ) 800a550: f005 fa0a bl 800f968 /*Configure GPIO pins : RELAY1_Pin RELAY2_Pin RELAY3_Pin RELAY4_Pin RELAY5_Pin */ GPIO_InitStruct.Pin = RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a554: f44f 53f8 mov.w r3, #7936 @ 0x1f00 800a558: 617b str r3, [r7, #20] |RELAY5_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a55a: 2301 movs r3, #1 800a55c: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a55e: 2300 movs r3, #0 800a560: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a562: 2302 movs r3, #2 800a564: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a566: f107 0314 add.w r3, r7, #20 800a56a: 4619 mov r1, r3 800a56c: 4834 ldr r0, [pc, #208] @ (800a640 ) 800a56e: f005 f9fb bl 800f968 /*Configure GPIO pin : RELAY_CC_Pin */ GPIO_InitStruct.Pin = RELAY_CC_Pin; 800a572: f44f 4300 mov.w r3, #32768 @ 0x8000 800a576: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a578: 2301 movs r3, #1 800a57a: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a57c: 2300 movs r3, #0 800a57e: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a580: 2302 movs r3, #2 800a582: 623b str r3, [r7, #32] HAL_GPIO_Init(RELAY_CC_GPIO_Port, &GPIO_InitStruct); 800a584: f107 0314 add.w r3, r7, #20 800a588: 4619 mov r1, r3 800a58a: 482e ldr r0, [pc, #184] @ (800a644 ) 800a58c: f005 f9ec bl 800f968 /*Configure GPIO pins : RELAY_DC_Pin USART2_DIR_Pin */ GPIO_InitStruct.Pin = RELAY_DC_Pin|USART2_DIR_Pin; 800a590: 2318 movs r3, #24 800a592: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a594: 2301 movs r3, #1 800a596: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a598: 2300 movs r3, #0 800a59a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a59c: 2302 movs r3, #2 800a59e: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800a5a0: f107 0314 add.w r3, r7, #20 800a5a4: 4619 mov r1, r3 800a5a6: 4828 ldr r0, [pc, #160] @ (800a648 ) 800a5a8: f005 f9de bl 800f968 /*Configure GPIO pin : IN_ESTOP_Pin */ GPIO_InitStruct.Pin = IN_ESTOP_Pin; 800a5ac: 2380 movs r3, #128 @ 0x80 800a5ae: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a5b0: 2300 movs r3, #0 800a5b2: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a5b4: 2300 movs r3, #0 800a5b6: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_ESTOP_GPIO_Port, &GPIO_InitStruct); 800a5b8: f107 0314 add.w r3, r7, #20 800a5bc: 4619 mov r1, r3 800a5be: 4822 ldr r0, [pc, #136] @ (800a648 ) 800a5c0: f005 f9d2 bl 800f968 /*Configure GPIO pins : IN_FB2_Pin IN_FB1_Pin */ GPIO_InitStruct.Pin = IN_FB2_Pin|IN_FB1_Pin; 800a5c4: 2318 movs r3, #24 800a5c6: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a5c8: 2300 movs r3, #0 800a5ca: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a5cc: 2300 movs r3, #0 800a5ce: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a5d0: f107 0314 add.w r3, r7, #20 800a5d4: 4619 mov r1, r3 800a5d6: 481d ldr r0, [pc, #116] @ (800a64c ) 800a5d8: f005 f9c6 bl 800f968 /*Configure GPIO pin : EE_WP_Pin */ GPIO_InitStruct.Pin = EE_WP_Pin; 800a5dc: 2380 movs r3, #128 @ 0x80 800a5de: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a5e0: 2301 movs r3, #1 800a5e2: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a5e4: 2300 movs r3, #0 800a5e6: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a5e8: 2302 movs r3, #2 800a5ea: 623b str r3, [r7, #32] HAL_GPIO_Init(EE_WP_GPIO_Port, &GPIO_InitStruct); 800a5ec: f107 0314 add.w r3, r7, #20 800a5f0: 4619 mov r1, r3 800a5f2: 4816 ldr r0, [pc, #88] @ (800a64c ) 800a5f4: f005 f9b8 bl 800f968 /*Configure GPIO pins : PB8 PB9 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 800a5f8: f44f 7340 mov.w r3, #768 @ 0x300 800a5fc: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 800a5fe: 2312 movs r3, #18 800a600: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a602: 2303 movs r3, #3 800a604: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a606: f107 0314 add.w r3, r7, #20 800a60a: 4619 mov r1, r3 800a60c: 480f ldr r0, [pc, #60] @ (800a64c ) 800a60e: f005 f9ab bl 800f968 /*Configure peripheral I/O remapping */ __HAL_AFIO_REMAP_I2C1_ENABLE(); 800a612: 4b0f ldr r3, [pc, #60] @ (800a650 ) 800a614: 685b ldr r3, [r3, #4] 800a616: 627b str r3, [r7, #36] @ 0x24 800a618: 6a7b ldr r3, [r7, #36] @ 0x24 800a61a: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800a61e: 627b str r3, [r7, #36] @ 0x24 800a620: 6a7b ldr r3, [r7, #36] @ 0x24 800a622: f043 0302 orr.w r3, r3, #2 800a626: 627b str r3, [r7, #36] @ 0x24 800a628: 4a09 ldr r2, [pc, #36] @ (800a650 ) 800a62a: 6a7b ldr r3, [r7, #36] @ 0x24 800a62c: 6053 str r3, [r2, #4] } 800a62e: bf00 nop 800a630: 3728 adds r7, #40 @ 0x28 800a632: 46bd mov sp, r7 800a634: bd80 pop {r7, pc} 800a636: bf00 nop 800a638: 40021000 .word 0x40021000 800a63c: 40011000 .word 0x40011000 800a640: 40011800 .word 0x40011800 800a644: 40010800 .word 0x40010800 800a648: 40011400 .word 0x40011400 800a64c: 40010c00 .word 0x40010c00 800a650: 40010000 .word 0x40010000 0800a654 <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 800a654: b480 push {r7} 800a656: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 800a658: f3bf 8f4f dsb sy } 800a65c: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800a65e: 4b06 ldr r3, [pc, #24] @ (800a678 <__NVIC_SystemReset+0x24>) 800a660: 68db ldr r3, [r3, #12] 800a662: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800a666: 4904 ldr r1, [pc, #16] @ (800a678 <__NVIC_SystemReset+0x24>) 800a668: 4b04 ldr r3, [pc, #16] @ (800a67c <__NVIC_SystemReset+0x28>) 800a66a: 4313 orrs r3, r2 800a66c: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800a66e: f3bf 8f4f dsb sy } 800a672: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 800a674: bf00 nop 800a676: e7fd b.n 800a674 <__NVIC_SystemReset+0x20> 800a678: e000ed00 .word 0xe000ed00 800a67c: 05fa0004 .word 0x05fa0004 0800a680 : * bootloader before starting this program. Unfortunately, function * SystemInit() overwrites this change again. * @return none. */ static void VectorBase_Config(void) { 800a680: b480 push {r7} 800a682: af00 add r7, sp, #0 * c-startup code. */ extern const unsigned long g_pfnVectors[]; /* Remap the vector table to where the vector table is located for this program. */ SCB->VTOR = (unsigned long)&g_pfnVectors[0]; 800a684: 4b03 ldr r3, [pc, #12] @ (800a694 ) 800a686: 4a04 ldr r2, [pc, #16] @ (800a698 ) 800a688: 609a str r2, [r3, #8] } 800a68a: bf00 nop 800a68c: 46bd mov sp, r7 800a68e: bc80 pop {r7} 800a690: 4770 bx lr 800a692: bf00 nop 800a694: e000ed00 .word 0xe000ed00 800a698: 08008000 .word 0x08008000 0800a69c : uint8_t ED_TraceWarning(uint8_t flag, uint8_t id){ 800a69c: b480 push {r7} 800a69e: b085 sub sp, #20 800a6a0: af00 add r7, sp, #0 800a6a2: 4603 mov r3, r0 800a6a4: 460a mov r2, r1 800a6a6: 71fb strb r3, [r7, #7] 800a6a8: 4613 mov r3, r2 800a6aa: 71bb strb r3, [r7, #6] static uint8_t memory[32]; if(id > 31) return 0; 800a6ac: 79bb ldrb r3, [r7, #6] 800a6ae: 2b1f cmp r3, #31 800a6b0: d901 bls.n 800a6b6 800a6b2: 2300 movs r3, #0 800a6b4: e00e b.n 800a6d4 uint8_t result = 0; 800a6b6: 2300 movs r3, #0 800a6b8: 73fb strb r3, [r7, #15] if(memory[id] != flag){ 800a6ba: 79bb ldrb r3, [r7, #6] 800a6bc: 4a08 ldr r2, [pc, #32] @ (800a6e0 ) 800a6be: 5cd3 ldrb r3, [r2, r3] 800a6c0: 79fa ldrb r2, [r7, #7] 800a6c2: 429a cmp r2, r3 800a6c4: d001 beq.n 800a6ca result = 1; 800a6c6: 2301 movs r3, #1 800a6c8: 73fb strb r3, [r7, #15] } memory[id] = flag; 800a6ca: 79bb ldrb r3, [r7, #6] 800a6cc: 4904 ldr r1, [pc, #16] @ (800a6e0 ) 800a6ce: 79fa ldrb r2, [r7, #7] 800a6d0: 54ca strb r2, [r1, r3] return result; 800a6d2: 7bfb ldrb r3, [r7, #15] } 800a6d4: 4618 mov r0, r3 800a6d6: 3714 adds r7, #20 800a6d8: 46bd mov sp, r7 800a6da: bc80 pop {r7} 800a6dc: 4770 bx lr 800a6de: bf00 nop 800a6e0: 20000810 .word 0x20000810 0800a6e4 : void ED_Delay(uint32_t Delay) { 800a6e4: b580 push {r7, lr} 800a6e6: b084 sub sp, #16 800a6e8: af00 add r7, sp, #0 800a6ea: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800a6ec: f003 fac6 bl 800dc7c 800a6f0: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800a6f2: 687b ldr r3, [r7, #4] 800a6f4: 60fb str r3, [r7, #12] if (wait < HAL_MAX_DELAY) 800a6f6: 68fb ldr r3, [r7, #12] 800a6f8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800a6fc: d010 beq.n 800a720 { wait += (uint32_t)(uwTickFreq); 800a6fe: 4b0f ldr r3, [pc, #60] @ (800a73c ) 800a700: 781b ldrb r3, [r3, #0] 800a702: 461a mov r2, r3 800a704: 68fb ldr r3, [r7, #12] 800a706: 4413 add r3, r2 800a708: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait){ 800a70a: e009 b.n 800a720 CCS_SerialLoop(); 800a70c: f001 f9c2 bl 800ba94 StopButtonControl(); 800a710: f000 f816 bl 800a740 // CP_Loop(); CONN_Task(); 800a714: f7ff fb76 bl 8009e04 LED_Task(); 800a718: f001 f894 bl 800b844 SC_Task(); 800a71c: f001 ffac bl 800c678 while ((HAL_GetTick() - tickstart) < wait){ 800a720: f003 faac bl 800dc7c 800a724: 4602 mov r2, r0 800a726: 68bb ldr r3, [r7, #8] 800a728: 1ad3 subs r3, r2, r3 800a72a: 68fa ldr r2, [r7, #12] 800a72c: 429a cmp r2, r3 800a72e: d8ed bhi.n 800a70c } } 800a730: bf00 nop 800a732: bf00 nop 800a734: 3710 adds r7, #16 800a736: 46bd mov sp, r7 800a738: bd80 pop {r7, pc} 800a73a: bf00 nop 800a73c: 20000088 .word 0x20000088 0800a740 : void StopButtonControl(){ 800a740: b580 push {r7, lr} 800a742: b082 sub sp, #8 800a744: af00 add r7, sp, #0 static uint32_t tick; static uint32_t hold_time; static uint8_t stop_btn_fault = 1; uint32_t now = HAL_GetTick(); 800a746: f003 fa99 bl 800dc7c 800a74a: 6078 str r0, [r7, #4] /* Run no faster than once per 10 ms. */ if((now - tick) < 10){ 800a74c: 4b2a ldr r3, [pc, #168] @ (800a7f8 ) 800a74e: 681b ldr r3, [r3, #0] 800a750: 687a ldr r2, [r7, #4] 800a752: 1ad3 subs r3, r2, r3 800a754: 2b09 cmp r3, #9 800a756: d949 bls.n 800a7ec return; } tick = now; 800a758: 4a27 ldr r2, [pc, #156] @ (800a7f8 ) 800a75a: 687b ldr r3, [r7, #4] 800a75c: 6013 str r3, [r2, #0] uint8_t pressed = !IN_ReadInput(IN_ESTOP); 800a75e: 2003 movs r0, #3 800a760: f7fe fff4 bl 800974c 800a764: 4603 mov r3, r0 800a766: 2b00 cmp r3, #0 800a768: bf0c ite eq 800a76a: 2301 moveq r3, #1 800a76c: 2300 movne r3, #0 800a76e: b2db uxtb r3, r3 800a770: 70fb strb r3, [r7, #3] if(!pressed){ 800a772: 78fb ldrb r3, [r7, #3] 800a774: 2b00 cmp r3, #0 800a776: d102 bne.n 800a77e stop_btn_fault = 0; 800a778: 4b20 ldr r3, [pc, #128] @ (800a7fc ) 800a77a: 2200 movs r2, #0 800a77c: 701a strb r2, [r3, #0] } if(stop_btn_fault){ 800a77e: 4b1f ldr r3, [pc, #124] @ (800a7fc ) 800a780: 781b ldrb r3, [r3, #0] 800a782: 2b00 cmp r3, #0 800a784: d134 bne.n 800a7f0 return; } if(pressed){ 800a786: 78fb ldrb r3, [r7, #3] 800a788: 2b00 cmp r3, #0 800a78a: d02b beq.n 800a7e4 if(hold_time == 0){ 800a78c: 4b1c ldr r3, [pc, #112] @ (800a800 ) 800a78e: 681b ldr r3, [r3, #0] 800a790: 2b00 cmp r3, #0 800a792: d102 bne.n 800a79a CONN.connControl = CMD_STOP; 800a794: 4b1b ldr r3, [pc, #108] @ (800a804 ) 800a796: 2201 movs r2, #1 800a798: 701a strb r2, [r3, #0] } hold_time += 10; 800a79a: 4b19 ldr r3, [pc, #100] @ (800a800 ) 800a79c: 681b ldr r3, [r3, #0] 800a79e: 330a adds r3, #10 800a7a0: 4a17 ldr r2, [pc, #92] @ (800a800 ) 800a7a2: 6013 str r3, [r2, #0] if(hold_time == 5000){ 800a7a4: 4b16 ldr r3, [pc, #88] @ (800a800 ) 800a7a6: 681b ldr r3, [r3, #0] 800a7a8: f241 3288 movw r2, #5000 @ 0x1388 800a7ac: 4293 cmp r3, r2 800a7ae: d102 bne.n 800a7b6 CONN.connControl = CMD_FORCE_UNLOCK; 800a7b0: 4b14 ldr r3, [pc, #80] @ (800a804 ) 800a7b2: 2203 movs r2, #3 800a7b4: 701a strb r2, [r3, #0] } if(hold_time > 40000){ 800a7b6: 4b12 ldr r3, [pc, #72] @ (800a800 ) 800a7b8: 681b ldr r3, [r3, #0] 800a7ba: f649 4240 movw r2, #40000 @ 0x9c40 800a7be: 4293 cmp r3, r2 800a7c0: d917 bls.n 800a7f2 SC_SendPacket(NULL, 0, RESP_SUCCESS); 800a7c2: 2212 movs r2, #18 800a7c4: 2100 movs r1, #0 800a7c6: 2000 movs r0, #0 800a7c8: f002 f956 bl 800ca78 while(huart2.gState == HAL_UART_STATE_BUSY_TX); 800a7cc: bf00 nop 800a7ce: 4b0e ldr r3, [pc, #56] @ (800a808 ) 800a7d0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800a7d4: b2db uxtb r3, r3 800a7d6: 2b21 cmp r3, #33 @ 0x21 800a7d8: d0f9 beq.n 800a7ce HAL_Delay(10); 800a7da: 200a movs r0, #10 800a7dc: f003 fa58 bl 800dc90 NVIC_SystemReset(); 800a7e0: f7ff ff38 bl 800a654 <__NVIC_SystemReset> } } else{ hold_time = 0; 800a7e4: 4b06 ldr r3, [pc, #24] @ (800a800 ) 800a7e6: 2200 movs r2, #0 800a7e8: 601a str r2, [r3, #0] 800a7ea: e002 b.n 800a7f2 return; 800a7ec: bf00 nop 800a7ee: e000 b.n 800a7f2 return; 800a7f0: bf00 nop } } 800a7f2: 3708 adds r7, #8 800a7f4: 46bd mov sp, r7 800a7f6: bd80 pop {r7, pc} 800a7f8: 20000830 .word 0x20000830 800a7fc: 20000005 .word 0x20000005 800a800: 20000834 .word 0x20000834 800a804: 20000354 .word 0x20000354 800a808: 20001174 .word 0x20001174 0800a80c : uint8_t temp0, temp1; static void CAN1_MinimalReInit(void) { 800a80c: b580 push {r7, lr} 800a80e: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan1); 800a810: 480b ldr r0, [pc, #44] @ (800a840 ) 800a812: f004 f987 bl 800eb24 MX_CAN1_Init(); 800a816: f7ff f955 bl 8009ac4 if (HAL_CAN_Start(&hcan1) != HAL_OK) { 800a81a: 4809 ldr r0, [pc, #36] @ (800a840 ) 800a81c: f004 f93e bl 800ea9c 800a820: 4603 mov r3, r0 800a822: 2b00 cmp r3, #0 800a824: d001 beq.n 800a82a Error_Handler(); 800a826: f000 f8f5 bl 800aa14 } if (HAL_CAN_ActivateNotification(&hcan1, CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) { 800a82a: 2102 movs r1, #2 800a82c: 4804 ldr r0, [pc, #16] @ (800a840 ) 800a82e: f004 fbe6 bl 800effe 800a832: 4603 mov r3, r0 800a834: 2b00 cmp r3, #0 800a836: d001 beq.n 800a83c Error_Handler(); 800a838: f000 f8ec bl 800aa14 } } 800a83c: bf00 nop 800a83e: bd80 pop {r7, pc} 800a840: 20000300 .word 0x20000300 0800a844
: /** * @brief The application entry point. * @retval int */ int main(void) { 800a844: b580 push {r7, lr} 800a846: b082 sub sp, #8 800a848: af02 add r7, sp, #8 /* USER CODE BEGIN 1 */ VectorBase_Config(); 800a84a: f7ff ff19 bl 800a680 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800a84e: f003 f9bd bl 800dbcc /* USER CODE BEGIN Init */ HAL_RCC_DeInit(); 800a852: f005 fa49 bl 800fce8 /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800a856: f000 f86d bl 800a934 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800a85a: f7ff fde7 bl 800a42c MX_ADC1_Init(); 800a85e: f7fe fe63 bl 8009528 MX_CAN1_Init(); 800a862: f7ff f92f bl 8009ac4 MX_CAN2_Init(); 800a866: f7ff f963 bl 8009b30 MX_RTC_Init(); 800a86a: f001 f889 bl 800b980 MX_TIM4_Init(); 800a86e: f002 fe65 bl 800d53c MX_USART2_UART_Init(); 800a872: f002 ffe3 bl 800d83c MX_CRC_Init(); 800a876: f7ff fc8b bl 800a190 MX_UART5_Init(); 800a87a: f002 ff8b bl 800d794 MX_USART1_UART_Init(); 800a87e: f002 ffb3 bl 800d7e8 MX_USART3_UART_Init(); 800a882: f003 f805 bl 800d890 MX_TIM3_Init(); 800a886: f002 fdcb bl 800d420 /* USER CODE BEGIN 2 */ Init_Peripheral(); 800a88a: f7fe ffb1 bl 80097f0 LED_Init(); 800a88e: f000 ffb9 bl 800b804 HAL_Delay(300); 800a892: f44f 7096 mov.w r0, #300 @ 0x12c 800a896: f003 f9fb bl 800dc90 CCS_Init(); 800a89a: f001 fb61 bl 800bf60 SC_Init(); 800a89e: f001 fed7 bl 800c650 log_printf(LOG_INFO, "CCS module start\n"); 800a8a2: 491f ldr r1, [pc, #124] @ (800a920 ) 800a8a4: 2007 movs r0, #7 800a8a6: f7ff fd8b bl 800a3c0 ReadVersion(); 800a8aa: f001 fead bl 800c608 log_printf(LOG_INFO, "Serial number: %d\n", infoPacket.serialNumber); 800a8ae: 4b1d ldr r3, [pc, #116] @ (800a924 ) 800a8b0: 881b ldrh r3, [r3, #0] 800a8b2: b29b uxth r3, r3 800a8b4: 461a mov r2, r3 800a8b6: 491c ldr r1, [pc, #112] @ (800a928 ) 800a8b8: 2007 movs r0, #7 800a8ba: f7ff fd81 bl 800a3c0 log_printf(LOG_INFO, "Board revision: %d\n", infoPacket.boardVersion); 800a8be: 4b19 ldr r3, [pc, #100] @ (800a924 ) 800a8c0: 789b ldrb r3, [r3, #2] 800a8c2: 461a mov r2, r3 800a8c4: 4919 ldr r1, [pc, #100] @ (800a92c ) 800a8c6: 2007 movs r0, #7 800a8c8: f7ff fd7a bl 800a3c0 log_printf(LOG_INFO, "FW version: %d.%d.%d\n", infoPacket.fw_version_major, infoPacket.fw_version_minor, infoPacket.fw_version_patch); 800a8cc: 4b15 ldr r3, [pc, #84] @ (800a924 ) 800a8ce: 889b ldrh r3, [r3, #4] 800a8d0: b29b uxth r3, r3 800a8d2: 461a mov r2, r3 800a8d4: 4b13 ldr r3, [pc, #76] @ (800a924 ) 800a8d6: 88db ldrh r3, [r3, #6] 800a8d8: b29b uxth r3, r3 800a8da: 4619 mov r1, r3 800a8dc: 4b11 ldr r3, [pc, #68] @ (800a924 ) 800a8de: 891b ldrh r3, [r3, #8] 800a8e0: b29b uxth r3, r3 800a8e2: 9300 str r3, [sp, #0] 800a8e4: 460b mov r3, r1 800a8e6: 4912 ldr r1, [pc, #72] @ (800a930 ) 800a8e8: 2007 movs r0, #7 800a8ea: f7ff fd69 bl 800a3c0 CAN1_MinimalReInit(); 800a8ee: f7ff ff8d bl 800a80c PSU_Init(); 800a8f2: f000 fa79 bl 800ade8 CONN_Init(); 800a8f6: f7ff fa2f bl 8009d58 /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ PSU_ReadWrite(); 800a8fa: f000 fb87 bl 800b00c PSU_Task(); 800a8fe: f000 fc3d bl 800b17c ED_Delay(10); 800a902: 200a movs r0, #10 800a904: f7ff feee bl 800a6e4 METER_CalculateEnergy(); 800a908: f000 f88a bl 800aa20 CONN_Loop(); 800a90c: f7ff fa3a bl 8009d84 LED_Write(); 800a910: f000 fe2a bl 800b568 ED_Delay(10); 800a914: 200a movs r0, #10 800a916: f7ff fee5 bl 800a6e4 { 800a91a: bf00 nop 800a91c: e7ed b.n 800a8fa 800a91e: bf00 nop 800a920: 080160c4 .word 0x080160c4 800a924: 20001044 .word 0x20001044 800a928: 080160d8 .word 0x080160d8 800a92c: 080160ec .word 0x080160ec 800a930: 08016100 .word 0x08016100 0800a934 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800a934: b580 push {r7, lr} 800a936: b09c sub sp, #112 @ 0x70 800a938: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800a93a: f107 0338 add.w r3, r7, #56 @ 0x38 800a93e: 2238 movs r2, #56 @ 0x38 800a940: 2100 movs r1, #0 800a942: 4618 mov r0, r3 800a944: f009 f9ba bl 8013cbc RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800a948: f107 0324 add.w r3, r7, #36 @ 0x24 800a94c: 2200 movs r2, #0 800a94e: 601a str r2, [r3, #0] 800a950: 605a str r2, [r3, #4] 800a952: 609a str r2, [r3, #8] 800a954: 60da str r2, [r3, #12] 800a956: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 800a958: 1d3b adds r3, r7, #4 800a95a: 2220 movs r2, #32 800a95c: 2100 movs r1, #0 800a95e: 4618 mov r0, r3 800a960: f009 f9ac bl 8013cbc /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; 800a964: 2305 movs r3, #5 800a966: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 800a968: f44f 3380 mov.w r3, #65536 @ 0x10000 800a96c: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV5; 800a96e: 2304 movs r3, #4 800a970: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 800a972: 2301 movs r3, #1 800a974: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800a976: 2301 movs r3, #1 800a978: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.Prediv1Source = RCC_PREDIV1_SOURCE_PLL2; 800a97a: f44f 3380 mov.w r3, #65536 @ 0x10000 800a97e: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800a980: 2302 movs r3, #2 800a982: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800a984: f44f 3380 mov.w r3, #65536 @ 0x10000 800a988: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 800a98a: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000 800a98e: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL2.PLL2State = RCC_PLL2_ON; 800a990: 2302 movs r3, #2 800a992: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL2.PLL2MUL = RCC_PLL2_MUL8; 800a994: f44f 63c0 mov.w r3, #1536 @ 0x600 800a998: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL2.HSEPrediv2Value = RCC_HSE_PREDIV2_DIV5; 800a99a: 2340 movs r3, #64 @ 0x40 800a99c: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800a99e: f107 0338 add.w r3, r7, #56 @ 0x38 800a9a2: 4618 mov r0, r3 800a9a4: f005 fa70 bl 800fe88 800a9a8: 4603 mov r3, r0 800a9aa: 2b00 cmp r3, #0 800a9ac: d001 beq.n 800a9b2 { Error_Handler(); 800a9ae: f000 f831 bl 800aa14 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800a9b2: 230f movs r3, #15 800a9b4: 627b str r3, [r7, #36] @ 0x24 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800a9b6: 2302 movs r3, #2 800a9b8: 62bb str r3, [r7, #40] @ 0x28 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800a9ba: 2300 movs r3, #0 800a9bc: 62fb str r3, [r7, #44] @ 0x2c RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 800a9be: f44f 6380 mov.w r3, #1024 @ 0x400 800a9c2: 633b str r3, [r7, #48] @ 0x30 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 800a9c4: 2300 movs r3, #0 800a9c6: 637b str r3, [r7, #52] @ 0x34 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800a9c8: f107 0324 add.w r3, r7, #36 @ 0x24 800a9cc: 2102 movs r1, #2 800a9ce: 4618 mov r0, r3 800a9d0: f005 fd70 bl 80104b4 800a9d4: 4603 mov r3, r0 800a9d6: 2b00 cmp r3, #0 800a9d8: d001 beq.n 800a9de { Error_Handler(); 800a9da: f000 f81b bl 800aa14 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC; 800a9de: 2303 movs r3, #3 800a9e0: 607b str r3, [r7, #4] PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 800a9e2: f44f 7380 mov.w r3, #256 @ 0x100 800a9e6: 60bb str r3, [r7, #8] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 800a9e8: f44f 4300 mov.w r3, #32768 @ 0x8000 800a9ec: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 800a9ee: 1d3b adds r3, r7, #4 800a9f0: 4618 mov r0, r3 800a9f2: f005 ff55 bl 80108a0 800a9f6: 4603 mov r3, r0 800a9f8: 2b00 cmp r3, #0 800a9fa: d001 beq.n 800aa00 { Error_Handler(); 800a9fc: f000 f80a bl 800aa14 } /** Configure the Systick interrupt time */ __HAL_RCC_PLLI2S_ENABLE(); 800aa00: 4b03 ldr r3, [pc, #12] @ (800aa10 ) 800aa02: 2201 movs r2, #1 800aa04: 601a str r2, [r3, #0] } 800aa06: bf00 nop 800aa08: 3770 adds r7, #112 @ 0x70 800aa0a: 46bd mov sp, r7 800aa0c: bd80 pop {r7, pc} 800aa0e: bf00 nop 800aa10: 42420070 .word 0x42420070 0800aa14 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 800aa14: b480 push {r7} 800aa16: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800aa18: b672 cpsid i } 800aa1a: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 800aa1c: bf00 nop 800aa1e: e7fd b.n 800aa1c 0800aa20 : METER_t METER; // Функция для расчета и накопления энергии c дробной частью без счетчиков void METER_CalculateEnergy() { 800aa20: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} 800aa24: b084 sub sp, #16 800aa26: af00 add r7, sp, #0 // Проверяем, что индекс находится в пределах массива METER.online = 0; 800aa28: 4b2e ldr r3, [pc, #184] @ (800aae4 ) 800aa2a: 2200 movs r2, #0 800aa2c: 711a strb r2, [r3, #4] if(CONN.connState == Charging){ 800aa2e: 4b2e ldr r3, [pc, #184] @ (800aae8 ) 800aa30: 785b ldrb r3, [r3, #1] 800aa32: 2b08 cmp r3, #8 800aa34: d104 bne.n 800aa40 METER.enable = 1; 800aa36: 4b2b ldr r3, [pc, #172] @ (800aae4 ) 800aa38: 2201 movs r2, #1 800aa3a: f883 2024 strb.w r2, [r3, #36] @ 0x24 800aa3e: e003 b.n 800aa48 }else{ METER.enable = 0; 800aa40: 4b28 ldr r3, [pc, #160] @ (800aae4 ) 800aa42: 2200 movs r2, #0 800aa44: f883 2024 strb.w r2, [r3, #36] @ 0x24 } uint32_t currentTick = HAL_GetTick(); // Получаем текущее время в миллисекундах 800aa48: f003 f918 bl 800dc7c 800aa4c: 60f8 str r0, [r7, #12] uint32_t elapsedTimeMs = currentTick - METER.lastTick; // Вычисляем время, прошедшее с последнего вызова в секундах 800aa4e: 4b25 ldr r3, [pc, #148] @ (800aae4 ) 800aa50: 689b ldr r3, [r3, #8] 800aa52: 68fa ldr r2, [r7, #12] 800aa54: 1ad3 subs r3, r2, r3 800aa56: 60bb str r3, [r7, #8] METER.lastTick = currentTick; // Обновляем время последнего вызова для текущего коннектора 800aa58: 4a22 ldr r2, [pc, #136] @ (800aae4 ) 800aa5a: 68fb ldr r3, [r7, #12] 800aa5c: 6093 str r3, [r2, #8] uint32_t energyWs = CONN.Power * elapsedTimeMs / 1000; // Рассчитываем энергию в ватт-секундах за прошедший промежуток времени 800aa5e: 4b22 ldr r3, [pc, #136] @ (800aae8 ) 800aa60: f8d3 3003 ldr.w r3, [r3, #3] 800aa64: 68ba ldr r2, [r7, #8] 800aa66: fb02 f303 mul.w r3, r2, r3 800aa6a: 4a20 ldr r2, [pc, #128] @ (800aaec ) 800aa6c: fba2 2303 umull r2, r3, r2, r3 800aa70: 099b lsrs r3, r3, #6 800aa72: 607b str r3, [r7, #4] //Расчет энергии теперь идет всегда, смещение берем суммарное METER.EnergyPSU_Ws += energyWs; 800aa74: 4b1b ldr r3, [pc, #108] @ (800aae4 ) 800aa76: e9d3 2304 ldrd r2, r3, [r3, #16] 800aa7a: 6879 ldr r1, [r7, #4] 800aa7c: 2000 movs r0, #0 800aa7e: 460c mov r4, r1 800aa80: 4605 mov r5, r0 800aa82: eb12 0804 adds.w r8, r2, r4 800aa86: eb43 0905 adc.w r9, r3, r5 800aa8a: 4b16 ldr r3, [pc, #88] @ (800aae4 ) 800aa8c: e9c3 8904 strd r8, r9, [r3, #16] // Абсолютное значение энергии разъема складывается из накопленной дробной части и значения со счетчиков METER.AbsoluteEnergy = (uint32_t)METER.EnergyPSU_Ws/3600; //переводим в Вт*час 800aa90: 4b14 ldr r3, [pc, #80] @ (800aae4 ) 800aa92: e9d3 2304 ldrd r2, r3, [r3, #16] 800aa96: 4b16 ldr r3, [pc, #88] @ (800aaf0 ) 800aa98: fba3 2302 umull r2, r3, r3, r2 800aa9c: 0adb lsrs r3, r3, #11 800aa9e: 4a11 ldr r2, [pc, #68] @ (800aae4 ) 800aaa0: 6193 str r3, [r2, #24] if(METER.enable) { 800aaa2: 4b10 ldr r3, [pc, #64] @ (800aae4 ) 800aaa4: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800aaa8: 2b00 cmp r3, #0 800aaaa: d008 beq.n 800aabe //enabled state CONN.Energy = METER.AbsoluteEnergy - METER.EnergyOffset;//переводим в Вт*час 800aaac: 4b0d ldr r3, [pc, #52] @ (800aae4 ) 800aaae: 699a ldr r2, [r3, #24] 800aab0: 4b0c ldr r3, [pc, #48] @ (800aae4 ) 800aab2: 69db ldr r3, [r3, #28] 800aab4: 1ad3 subs r3, r2, r3 800aab6: 4a0c ldr r2, [pc, #48] @ (800aae8 ) 800aab8: f8c2 3007 str.w r3, [r2, #7] METER.EnergyOffset = METER.AbsoluteEnergy; } } 800aabc: e00c b.n 800aad8 CONN.Energy = 0; 800aabe: 4b0a ldr r3, [pc, #40] @ (800aae8 ) 800aac0: 2200 movs r2, #0 800aac2: 71da strb r2, [r3, #7] 800aac4: 2200 movs r2, #0 800aac6: 721a strb r2, [r3, #8] 800aac8: 2200 movs r2, #0 800aaca: 725a strb r2, [r3, #9] 800aacc: 2200 movs r2, #0 800aace: 729a strb r2, [r3, #10] METER.EnergyOffset = METER.AbsoluteEnergy; 800aad0: 4b04 ldr r3, [pc, #16] @ (800aae4 ) 800aad2: 699b ldr r3, [r3, #24] 800aad4: 4a03 ldr r2, [pc, #12] @ (800aae4 ) 800aad6: 61d3 str r3, [r2, #28] } 800aad8: bf00 nop 800aada: 3710 adds r7, #16 800aadc: 46bd mov sp, r7 800aade: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} 800aae2: bf00 nop 800aae4: 20000838 .word 0x20000838 800aae8: 20000354 .word 0x20000354 800aaec: 10624dd3 .word 0x10624dd3 800aaf0: 91a2b3c5 .word 0x91a2b3c5 0800aaf4 : uint32_t can_lastpacket; extern CAN_HandleTypeDef hcan2; static void PSU_SwitchState(PSU_State_t state){ 800aaf4: b580 push {r7, lr} 800aaf6: b082 sub sp, #8 800aaf8: af00 add r7, sp, #0 800aafa: 4603 mov r3, r0 800aafc: 71fb strb r3, [r7, #7] PSU0.state = state; 800aafe: 4a06 ldr r2, [pc, #24] @ (800ab18 ) 800ab00: 79fb ldrb r3, [r7, #7] 800ab02: 71d3 strb r3, [r2, #7] PSU0.statetick = HAL_GetTick(); 800ab04: f003 f8ba bl 800dc7c 800ab08: 4603 mov r3, r0 800ab0a: 4a03 ldr r2, [pc, #12] @ (800ab18 ) 800ab0c: 6113 str r3, [r2, #16] } 800ab0e: bf00 nop 800ab10: 3708 adds r7, #8 800ab12: 46bd mov sp, r7 800ab14: bd80 pop {r7, pc} 800ab16: bf00 nop 800ab18: 200008a4 .word 0x200008a4 0800ab1c : static uint32_t PSU_StateTime(void){ 800ab1c: b580 push {r7, lr} 800ab1e: af00 add r7, sp, #0 return HAL_GetTick() - PSU0.statetick; 800ab20: f003 f8ac bl 800dc7c 800ab24: 4602 mov r2, r0 800ab26: 4b02 ldr r3, [pc, #8] @ (800ab30 ) 800ab28: 691b ldr r3, [r3, #16] 800ab2a: 1ad3 subs r3, r2, r3 } 800ab2c: 4618 mov r0, r3 800ab2e: bd80 pop {r7, pc} 800ab30: 200008a4 .word 0x200008a4 0800ab34 : void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan){ 800ab34: b580 push {r7, lr} 800ab36: b084 sub sp, #16 800ab38: af00 add r7, sp, #0 800ab3a: 6078 str r0, [r7, #4] static CAN_RxHeaderTypeDef RxHeader; static uint8_t RxData[8] = {0,}; CanId_t CanId; if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO1, &RxHeader, RxData) == HAL_OK) 800ab3c: 4b88 ldr r3, [pc, #544] @ (800ad60 ) 800ab3e: 4a89 ldr r2, [pc, #548] @ (800ad64 ) 800ab40: 2101 movs r1, #1 800ab42: 6878 ldr r0, [r7, #4] 800ab44: f004 f93a bl 800edbc 800ab48: 4603 mov r3, r0 800ab4a: 2b00 cmp r3, #0 800ab4c: f040 8104 bne.w 800ad58 { memcpy(&CanId, &RxHeader.ExtId, sizeof(CanId_t)); 800ab50: 4b84 ldr r3, [pc, #528] @ (800ad64 ) 800ab52: 685b ldr r3, [r3, #4] 800ab54: 60bb str r3, [r7, #8] /* Для DC30 поддерживается только один силовой модуль (source == 0) */ if(CanId.source != 0) return; 800ab56: 7a3b ldrb r3, [r7, #8] 800ab58: 2b00 cmp r3, #0 800ab5a: f040 80fc bne.w 800ad56 can_lastpacket = HAL_GetTick(); 800ab5e: f003 f88d bl 800dc7c 800ab62: 4603 mov r3, r0 800ab64: 4a80 ldr r2, [pc, #512] @ (800ad68 ) 800ab66: 6013 str r3, [r2, #0] if(CanId.command==0x02){ 800ab68: 7abb ldrb r3, [r7, #10] 800ab6a: f003 033f and.w r3, r3, #63 @ 0x3f 800ab6e: b2db uxtb r3, r3 800ab70: 2b02 cmp r3, #2 800ab72: d105 bne.n 800ab80 memcpy(&PSU_02, RxData, 8); 800ab74: 4b7d ldr r3, [pc, #500] @ (800ad6c ) 800ab76: 4a7a ldr r2, [pc, #488] @ (800ad60 ) 800ab78: e892 0003 ldmia.w r2, {r0, r1} 800ab7c: e883 0003 stmia.w r3, {r0, r1} } if(CanId.command==0x04){ 800ab80: 7abb ldrb r3, [r7, #10] 800ab82: f003 033f and.w r3, r3, #63 @ 0x3f 800ab86: b2db uxtb r3, r3 800ab88: 2b04 cmp r3, #4 800ab8a: d119 bne.n 800abc0 memcpy(&PSU_04, RxData, 8); 800ab8c: 4b78 ldr r3, [pc, #480] @ (800ad70 ) 800ab8e: 4a74 ldr r2, [pc, #464] @ (800ad60 ) 800ab90: e892 0003 ldmia.w r2, {r0, r1} 800ab94: e883 0003 stmia.w r3, {r0, r1} PSU0.tempAmbient = PSU_04.moduleTemperature; 800ab98: 4b75 ldr r3, [pc, #468] @ (800ad70 ) 800ab9a: 791b ldrb r3, [r3, #4] 800ab9c: 461a mov r2, r3 800ab9e: 4b75 ldr r3, [pc, #468] @ (800ad74 ) 800aba0: 621a str r2, [r3, #32] PSU0.status0.raw = PSU_04.modularForm0; 800aba2: 4b73 ldr r3, [pc, #460] @ (800ad70 ) 800aba4: 7a1a ldrb r2, [r3, #8] 800aba6: 4b73 ldr r3, [pc, #460] @ (800ad74 ) 800aba8: f883 2024 strb.w r2, [r3, #36] @ 0x24 PSU0.status1.raw = PSU_04.modularForm1; 800abac: 4b70 ldr r3, [pc, #448] @ (800ad70 ) 800abae: 79da ldrb r2, [r3, #7] 800abb0: 4b70 ldr r3, [pc, #448] @ (800ad74 ) 800abb2: f883 2025 strb.w r2, [r3, #37] @ 0x25 PSU0.status2.raw = PSU_04.modularForm2; 800abb6: 4b6e ldr r3, [pc, #440] @ (800ad70 ) 800abb8: 799a ldrb r2, [r3, #6] 800abba: 4b6e ldr r3, [pc, #440] @ (800ad74 ) 800abbc: f883 2026 strb.w r2, [r3, #38] @ 0x26 } if(CanId.command==0x06){ 800abc0: 7abb ldrb r3, [r7, #10] 800abc2: f003 033f and.w r3, r3, #63 @ 0x3f 800abc6: b2db uxtb r3, r3 800abc8: 2b06 cmp r3, #6 800abca: d123 bne.n 800ac14 memcpy(&PSU_06, RxData, 8); 800abcc: 4b6a ldr r3, [pc, #424] @ (800ad78 ) 800abce: 4a64 ldr r2, [pc, #400] @ (800ad60 ) 800abd0: e892 0003 ldmia.w r2, {r0, r1} 800abd4: e883 0003 stmia.w r3, {r0, r1} PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800abd8: 4b67 ldr r3, [pc, #412] @ (800ad78 ) 800abda: 785b ldrb r3, [r3, #1] 800abdc: 461a mov r2, r3 800abde: 4b66 ldr r3, [pc, #408] @ (800ad78 ) 800abe0: 781b ldrb r3, [r3, #0] 800abe2: 021b lsls r3, r3, #8 800abe4: 4413 add r3, r2 800abe6: 461a mov r2, r3 800abe8: 4b63 ldr r3, [pc, #396] @ (800ad78 ) 800abea: 609a str r2, [r3, #8] PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800abec: 4b62 ldr r3, [pc, #392] @ (800ad78 ) 800abee: 78db ldrb r3, [r3, #3] 800abf0: 461a mov r2, r3 800abf2: 4b61 ldr r3, [pc, #388] @ (800ad78 ) 800abf4: 789b ldrb r3, [r3, #2] 800abf6: 021b lsls r3, r3, #8 800abf8: 4413 add r3, r2 800abfa: 461a mov r2, r3 800abfc: 4b5e ldr r3, [pc, #376] @ (800ad78 ) 800abfe: 60da str r2, [r3, #12] PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ac00: 4b5d ldr r3, [pc, #372] @ (800ad78 ) 800ac02: 795b ldrb r3, [r3, #5] 800ac04: 461a mov r2, r3 800ac06: 4b5c ldr r3, [pc, #368] @ (800ad78 ) 800ac08: 791b ldrb r3, [r3, #4] 800ac0a: 021b lsls r3, r3, #8 800ac0c: 4413 add r3, r2 800ac0e: 461a mov r2, r3 800ac10: 4b59 ldr r3, [pc, #356] @ (800ad78 ) 800ac12: 611a str r2, [r3, #16] } if(CanId.command==0x08){ 800ac14: 7abb ldrb r3, [r7, #10] 800ac16: f003 033f and.w r3, r3, #63 @ 0x3f 800ac1a: b2db uxtb r3, r3 800ac1c: 2b08 cmp r3, #8 800ac1e: d105 bne.n 800ac2c memcpy(&PSU_08, RxData, 8); 800ac20: 4b56 ldr r3, [pc, #344] @ (800ad7c ) 800ac22: 4a4f ldr r2, [pc, #316] @ (800ad60 ) 800ac24: e892 0003 ldmia.w r2, {r0, r1} 800ac28: e883 0003 stmia.w r3, {r0, r1} } if(CanId.command==0x09){ 800ac2c: 7abb ldrb r3, [r7, #10] 800ac2e: f003 033f and.w r3, r3, #63 @ 0x3f 800ac32: b2db uxtb r3, r3 800ac34: 2b09 cmp r3, #9 800ac36: f040 808f bne.w 800ad58 memcpy(&PSU_09, RxData, 8); 800ac3a: 4b51 ldr r3, [pc, #324] @ (800ad80 ) 800ac3c: 4a48 ldr r2, [pc, #288] @ (800ad60 ) 800ac3e: e892 0003 ldmia.w r2, {r0, r1} 800ac42: e883 0003 stmia.w r3, {r0, r1} PSU_09.moduleNCurrent = PSU_09.moduleNCurrent_[3]; 800ac46: 4b4e ldr r3, [pc, #312] @ (800ad80 ) 800ac48: 79db ldrb r3, [r3, #7] 800ac4a: 461a mov r2, r3 800ac4c: 4b4c ldr r3, [pc, #304] @ (800ad80 ) 800ac4e: 60da str r2, [r3, #12] PSU_09.moduleNCurrent |= PSU_09.moduleNCurrent_[2]<<8; 800ac50: 4b4b ldr r3, [pc, #300] @ (800ad80 ) 800ac52: 68da ldr r2, [r3, #12] 800ac54: 4b4a ldr r3, [pc, #296] @ (800ad80 ) 800ac56: 799b ldrb r3, [r3, #6] 800ac58: 021b lsls r3, r3, #8 800ac5a: 4313 orrs r3, r2 800ac5c: 4a48 ldr r2, [pc, #288] @ (800ad80 ) 800ac5e: 60d3 str r3, [r2, #12] PSU_09.moduleNCurrent |= PSU_09.moduleNCurrent_[1]<<16; 800ac60: 4b47 ldr r3, [pc, #284] @ (800ad80 ) 800ac62: 68da ldr r2, [r3, #12] 800ac64: 4b46 ldr r3, [pc, #280] @ (800ad80 ) 800ac66: 795b ldrb r3, [r3, #5] 800ac68: 041b lsls r3, r3, #16 800ac6a: 4313 orrs r3, r2 800ac6c: 4a44 ldr r2, [pc, #272] @ (800ad80 ) 800ac6e: 60d3 str r3, [r2, #12] PSU_09.moduleNCurrent |= PSU_09.moduleNCurrent_[0]<<24; 800ac70: 4b43 ldr r3, [pc, #268] @ (800ad80 ) 800ac72: 68da ldr r2, [r3, #12] 800ac74: 4b42 ldr r3, [pc, #264] @ (800ad80 ) 800ac76: 791b ldrb r3, [r3, #4] 800ac78: 061b lsls r3, r3, #24 800ac7a: 4313 orrs r3, r2 800ac7c: 4a40 ldr r2, [pc, #256] @ (800ad80 ) 800ac7e: 60d3 str r3, [r2, #12] PSU_09.moduleNVoltage = PSU_09.moduleNVoltage_[3]; 800ac80: 4b3f ldr r3, [pc, #252] @ (800ad80 ) 800ac82: 78db ldrb r3, [r3, #3] 800ac84: 461a mov r2, r3 800ac86: 4b3e ldr r3, [pc, #248] @ (800ad80 ) 800ac88: 609a str r2, [r3, #8] PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[2]<<8; 800ac8a: 4b3d ldr r3, [pc, #244] @ (800ad80 ) 800ac8c: 689a ldr r2, [r3, #8] 800ac8e: 4b3c ldr r3, [pc, #240] @ (800ad80 ) 800ac90: 789b ldrb r3, [r3, #2] 800ac92: 021b lsls r3, r3, #8 800ac94: 4313 orrs r3, r2 800ac96: 4a3a ldr r2, [pc, #232] @ (800ad80 ) 800ac98: 6093 str r3, [r2, #8] PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[1]<<16; 800ac9a: 4b39 ldr r3, [pc, #228] @ (800ad80 ) 800ac9c: 689a ldr r2, [r3, #8] 800ac9e: 4b38 ldr r3, [pc, #224] @ (800ad80 ) 800aca0: 785b ldrb r3, [r3, #1] 800aca2: 041b lsls r3, r3, #16 800aca4: 4313 orrs r3, r2 800aca6: 4a36 ldr r2, [pc, #216] @ (800ad80 ) 800aca8: 6093 str r3, [r2, #8] PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[0]<<24; 800acaa: 4b35 ldr r3, [pc, #212] @ (800ad80 ) 800acac: 689a ldr r2, [r3, #8] 800acae: 4b34 ldr r3, [pc, #208] @ (800ad80 ) 800acb0: 781b ldrb r3, [r3, #0] 800acb2: 061b lsls r3, r3, #24 800acb4: 4313 orrs r3, r2 800acb6: 4a32 ldr r2, [pc, #200] @ (800ad80 ) 800acb8: 6093 str r3, [r2, #8] // PSU_09 -> PSU -> CONN (один модуль) { uint16_t v = PSU_09.moduleNVoltage / 1000; 800acba: 4b31 ldr r3, [pc, #196] @ (800ad80 ) 800acbc: 689b ldr r3, [r3, #8] 800acbe: 4a31 ldr r2, [pc, #196] @ (800ad84 ) 800acc0: fba2 2303 umull r2, r3, r2, r3 800acc4: 099b lsrs r3, r3, #6 800acc6: 81fb strh r3, [r7, #14] int16_t i = PSU_09.moduleNCurrent / 100; 800acc8: 4b2d ldr r3, [pc, #180] @ (800ad80 ) 800acca: 68db ldr r3, [r3, #12] 800accc: 4a2e ldr r2, [pc, #184] @ (800ad88 ) 800acce: fba2 2303 umull r2, r3, r2, r3 800acd2: 095b lsrs r3, r3, #5 800acd4: 81bb strh r3, [r7, #12] // Обновляем модель PSU0 по телеметрии PSU0.outputVoltage = v; 800acd6: 4a27 ldr r2, [pc, #156] @ (800ad74 ) 800acd8: 89fb ldrh r3, [r7, #14] 800acda: 8053 strh r3, [r2, #2] PSU0.outputCurrent = i; 800acdc: 4a25 ldr r2, [pc, #148] @ (800ad74 ) 800acde: 89bb ldrh r3, [r7, #12] 800ace0: 8093 strh r3, [r2, #4] PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800ace2: 89fb ldrh r3, [r7, #14] 800ace4: 2b13 cmp r3, #19 800ace6: bf8c ite hi 800ace8: 2301 movhi r3, #1 800acea: 2300 movls r3, #0 800acec: b2db uxtb r3, r3 800acee: 461a mov r2, r3 800acf0: 4b20 ldr r3, [pc, #128] @ (800ad74 ) 800acf2: 729a strb r2, [r3, #10] PSU0.online = 1; 800acf4: 4b1f ldr r3, [pc, #124] @ (800ad74 ) 800acf6: 2201 movs r2, #1 800acf8: 721a strb r2, [r3, #8] PSU0.temperature = PSU_04.moduleTemperature; 800acfa: 4b1d ldr r3, [pc, #116] @ (800ad70 ) 800acfc: 791a ldrb r2, [r3, #4] 800acfe: 4b1d ldr r3, [pc, #116] @ (800ad74 ) 800ad00: 719a strb r2, [r3, #6] // Экспортируем значения из PSU0 в CONN только, // когда модуль хотя бы в состоянии READY и выше if(PSU0.state >= PSU_READY){ 800ad02: 4b1c ldr r3, [pc, #112] @ (800ad74 ) 800ad04: 79db ldrb r3, [r3, #7] 800ad06: 2b01 cmp r3, #1 800ad08: d926 bls.n 800ad58 CONN.MeasuredVoltage = PSU0.outputVoltage; 800ad0a: 4b1a ldr r3, [pc, #104] @ (800ad74 ) 800ad0c: 885a ldrh r2, [r3, #2] 800ad0e: 4b1f ldr r3, [pc, #124] @ (800ad8c ) 800ad10: f8a3 2013 strh.w r2, [r3, #19] CONN.MeasuredCurrent = PSU0.outputCurrent; 800ad14: 4b17 ldr r3, [pc, #92] @ (800ad74 ) 800ad16: f9b3 3004 ldrsh.w r3, [r3, #4] 800ad1a: b29a uxth r2, r3 800ad1c: 4b1b ldr r3, [pc, #108] @ (800ad8c ) 800ad1e: f8a3 2015 strh.w r2, [r3, #21] CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800ad22: 4b1a ldr r3, [pc, #104] @ (800ad8c ) 800ad24: f8b3 3015 ldrh.w r3, [r3, #21] 800ad28: b29b uxth r3, r3 800ad2a: 461a mov r2, r3 800ad2c: 4b17 ldr r3, [pc, #92] @ (800ad8c ) 800ad2e: f8b3 3013 ldrh.w r3, [r3, #19] 800ad32: b29b uxth r3, r3 800ad34: fb02 f303 mul.w r3, r2, r3 800ad38: 4a15 ldr r2, [pc, #84] @ (800ad90 ) 800ad3a: fb82 1203 smull r1, r2, r2, r3 800ad3e: 1092 asrs r2, r2, #2 800ad40: 17db asrs r3, r3, #31 800ad42: 1ad3 subs r3, r2, r3 800ad44: 461a mov r2, r3 800ad46: 4b11 ldr r3, [pc, #68] @ (800ad8c ) 800ad48: f8c3 2003 str.w r2, [r3, #3] CONN.outputEnabled = PSU0.PSU_enabled; 800ad4c: 4b09 ldr r3, [pc, #36] @ (800ad74 ) 800ad4e: 7a9a ldrb r2, [r3, #10] 800ad50: 4b0e ldr r3, [pc, #56] @ (800ad8c ) 800ad52: 761a strb r2, [r3, #24] 800ad54: e000 b.n 800ad58 if(CanId.source != 0) return; 800ad56: bf00 nop } } } } } 800ad58: 3710 adds r7, #16 800ad5a: 46bd mov sp, r7 800ad5c: bd80 pop {r7, pc} 800ad5e: bf00 nop 800ad60: 200008ec .word 0x200008ec 800ad64: 200008d0 .word 0x200008d0 800ad68: 200008cc .word 0x200008cc 800ad6c: 20000860 .word 0x20000860 800ad70: 2000086c .word 0x2000086c 800ad74: 200008a4 .word 0x200008a4 800ad78: 20000878 .word 0x20000878 800ad7c: 2000088c .word 0x2000088c 800ad80: 20000894 .word 0x20000894 800ad84: 10624dd3 .word 0x10624dd3 800ad88: 51eb851f .word 0x51eb851f 800ad8c: 20000354 .word 0x20000354 800ad90: 66666667 .word 0x66666667 0800ad94 : void PSU_CAN_FilterInit(){ 800ad94: b580 push {r7, lr} 800ad96: b08a sub sp, #40 @ 0x28 800ad98: af00 add r7, sp, #0 CAN_FilterTypeDef sFilterConfig; sFilterConfig.FilterBank = 14; 800ad9a: 230e movs r3, #14 800ad9c: 617b str r3, [r7, #20] sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; 800ad9e: 2300 movs r3, #0 800ada0: 61bb str r3, [r7, #24] sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; 800ada2: 2301 movs r3, #1 800ada4: 61fb str r3, [r7, #28] sFilterConfig.FilterIdHigh = 0x0000; 800ada6: 2300 movs r3, #0 800ada8: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = 0x0000; 800adaa: 2300 movs r3, #0 800adac: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 800adae: 2300 movs r3, #0 800adb0: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = 0x0000; 800adb2: 2300 movs r3, #0 800adb4: 60fb str r3, [r7, #12] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; 800adb6: 2300 movs r3, #0 800adb8: 613b str r3, [r7, #16] sFilterConfig.FilterActivation = ENABLE; 800adba: 2301 movs r3, #1 800adbc: 623b str r3, [r7, #32] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; 800adbe: 2301 movs r3, #1 800adc0: 613b str r3, [r7, #16] sFilterConfig.SlaveStartFilterBank = 14; 800adc2: 230e movs r3, #14 800adc4: 627b str r3, [r7, #36] @ 0x24 if(HAL_CAN_ConfigFilter(&hcan2, &sFilterConfig) != HAL_OK) 800adc6: 463b mov r3, r7 800adc8: 4619 mov r1, r3 800adca: 4806 ldr r0, [pc, #24] @ (800ade4 ) 800adcc: f003 fd86 bl 800e8dc 800add0: 4603 mov r3, r0 800add2: 2b00 cmp r3, #0 800add4: d001 beq.n 800adda { Error_Handler(); 800add6: f7ff fe1d bl 800aa14 } } 800adda: bf00 nop 800addc: 3728 adds r7, #40 @ 0x28 800adde: 46bd mov sp, r7 800ade0: bd80 pop {r7, pc} 800ade2: bf00 nop 800ade4: 20000328 .word 0x20000328 0800ade8 : void PSU_Init(){ 800ade8: b580 push {r7, lr} 800adea: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan2); 800adec: 4815 ldr r0, [pc, #84] @ (800ae44 ) 800adee: f003 fe99 bl 800eb24 MX_CAN2_Init(); 800adf2: f7fe fe9d bl 8009b30 PSU_CAN_FilterInit(); 800adf6: f7ff ffcd bl 800ad94 HAL_CAN_Start(&hcan2); 800adfa: 4812 ldr r0, [pc, #72] @ (800ae44 ) 800adfc: f003 fe4e bl 800ea9c HAL_CAN_ActivateNotification(&hcan2, CAN_IT_RX_FIFO1_MSG_PENDING /* | CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | CAN_IT_TX_MAILBOX_EMPTY*/); 800ae00: 2110 movs r1, #16 800ae02: 4810 ldr r0, [pc, #64] @ (800ae44 ) 800ae04: f004 f8fb bl 800effe memset(&PSU0, 0, sizeof(PSU0)); 800ae08: 2228 movs r2, #40 @ 0x28 800ae0a: 2100 movs r1, #0 800ae0c: 480e ldr r0, [pc, #56] @ (800ae48 ) 800ae0e: f008 ff55 bl 8013cbc PSU0.state = PSU_UNREADY; 800ae12: 4b0d ldr r3, [pc, #52] @ (800ae48 ) 800ae14: 2200 movs r2, #0 800ae16: 71da strb r2, [r3, #7] PSU0.statetick = HAL_GetTick(); 800ae18: f002 ff30 bl 800dc7c 800ae1c: 4603 mov r3, r0 800ae1e: 4a0a ldr r2, [pc, #40] @ (800ae48 ) 800ae20: 6113 str r3, [r2, #16] PSU0.power_limit = PSU_MAX_POWER; // kW 800ae22: 4b09 ldr r3, [pc, #36] @ (800ae48 ) 800ae24: f247 5230 movw r2, #30000 @ 0x7530 800ae28: 615a str r2, [r3, #20] PSU0.hv_mode = 0; 800ae2a: 4b07 ldr r3, [pc, #28] @ (800ae48 ) 800ae2c: 2200 movs r2, #0 800ae2e: 761a strb r2, [r3, #24] PSU0.hv_tick = 0; 800ae30: 4b05 ldr r3, [pc, #20] @ (800ae48 ) 800ae32: 2200 movs r2, #0 800ae34: 61da str r2, [r3, #28] PSU_Enable(0, 0); 800ae36: 2100 movs r1, #0 800ae38: 2000 movs r0, #0 800ae3a: f000 f807 bl 800ae4c } 800ae3e: bf00 nop 800ae40: bd80 pop {r7, pc} 800ae42: bf00 nop 800ae44: 20000328 .word 0x20000328 800ae48: 200008a4 .word 0x200008a4 0800ae4c : void PSU_Enable(uint8_t addr, uint8_t enable){ 800ae4c: b580 push {r7, lr} 800ae4e: b084 sub sp, #16 800ae50: af00 add r7, sp, #0 800ae52: 4603 mov r3, r0 800ae54: 460a mov r2, r1 800ae56: 71fb strb r3, [r7, #7] 800ae58: 4613 mov r3, r2 800ae5a: 71bb strb r3, [r7, #6] PSU_1A_t data; memset(&data, 0, sizeof(data)); 800ae5c: f107 0308 add.w r3, r7, #8 800ae60: 2208 movs r2, #8 800ae62: 2100 movs r1, #0 800ae64: 4618 mov r0, r3 800ae66: f008 ff29 bl 8013cbc /* Для DC30 поддерживается только один модуль с адресом 0 */ if(addr != 0) return; 800ae6a: 79fb ldrb r3, [r7, #7] 800ae6c: 2b00 cmp r3, #0 800ae6e: d115 bne.n 800ae9c if(PSU0.online == 0) return; 800ae70: 4b0d ldr r3, [pc, #52] @ (800aea8 ) 800ae72: 7a1b ldrb r3, [r3, #8] 800ae74: 2b00 cmp r3, #0 800ae76: d013 beq.n 800aea0 data.enable = !enable; 800ae78: 79bb ldrb r3, [r7, #6] 800ae7a: 2b00 cmp r3, #0 800ae7c: bf0c ite eq 800ae7e: 2301 moveq r3, #1 800ae80: 2300 movne r3, #0 800ae82: b2db uxtb r3, r3 800ae84: 723b strb r3, [r7, #8] PSU_SendCmd(0xF0, addr, 0x1A, &data); 800ae86: 79f9 ldrb r1, [r7, #7] 800ae88: f107 0308 add.w r3, r7, #8 800ae8c: 221a movs r2, #26 800ae8e: 20f0 movs r0, #240 @ 0xf0 800ae90: f000 f866 bl 800af60 ED_Delay(CAN_DELAY); 800ae94: 2014 movs r0, #20 800ae96: f7ff fc25 bl 800a6e4 800ae9a: e002 b.n 800aea2 if(addr != 0) return; 800ae9c: bf00 nop 800ae9e: e000 b.n 800aea2 if(PSU0.online == 0) return; 800aea0: bf00 nop } 800aea2: 3710 adds r7, #16 800aea4: 46bd mov sp, r7 800aea6: bd80 pop {r7, pc} 800aea8: 200008a4 .word 0x200008a4 0800aeac : memset(&data, 0, sizeof(data)); data.enable = !enable; if(addr != 0) return; PSU_SendCmd(0xF0, addr, 0x1D, &data); } void PSU_SetVoltageCurrent(uint8_t addr, uint16_t voltage, uint16_t current){ 800aeac: b580 push {r7, lr} 800aeae: b086 sub sp, #24 800aeb0: af00 add r7, sp, #0 800aeb2: 4603 mov r3, r0 800aeb4: 71fb strb r3, [r7, #7] 800aeb6: 460b mov r3, r1 800aeb8: 80bb strh r3, [r7, #4] 800aeba: 4613 mov r3, r2 800aebc: 807b strh r3, [r7, #2] PSU_1C_t data; memset(&data, 0, sizeof(data)); 800aebe: f107 0308 add.w r3, r7, #8 800aec2: 2208 movs r2, #8 800aec4: 2100 movs r1, #0 800aec6: 4618 mov r0, r3 800aec8: f008 fef8 bl 8013cbc if(addr != 0) return; 800aecc: 79fb ldrb r3, [r7, #7] 800aece: 2b00 cmp r3, #0 800aed0: d140 bne.n 800af54 if(voltage 800aed8: 2396 movs r3, #150 @ 0x96 800aeda: 80bb strh r3, [r7, #4] if((PSU0.hv_mode==0) && voltage>499) voltage = 499; 800aedc: 4b1f ldr r3, [pc, #124] @ (800af5c ) 800aede: 7e1b ldrb r3, [r3, #24] 800aee0: 2b00 cmp r3, #0 800aee2: d106 bne.n 800aef2 800aee4: 88bb ldrh r3, [r7, #4] 800aee6: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800aeea: d302 bcc.n 800aef2 800aeec: f240 13f3 movw r3, #499 @ 0x1f3 800aef0: 80bb strh r3, [r7, #4] uint32_t current_ma = current * 100; 800aef2: 887b ldrh r3, [r7, #2] 800aef4: 2264 movs r2, #100 @ 0x64 800aef6: fb02 f303 mul.w r3, r2, r3 800aefa: 617b str r3, [r7, #20] uint32_t voltage_mv = voltage * 1000; 800aefc: 88bb ldrh r3, [r7, #4] 800aefe: f44f 727a mov.w r2, #1000 @ 0x3e8 800af02: fb02 f303 mul.w r3, r2, r3 800af06: 613b str r3, [r7, #16] data.moduleCurrentTotal[0] = (current_ma >> 24) & 0xFF; 800af08: 697b ldr r3, [r7, #20] 800af0a: 0e1b lsrs r3, r3, #24 800af0c: b2db uxtb r3, r3 800af0e: 733b strb r3, [r7, #12] data.moduleCurrentTotal[1] = (current_ma >> 16) & 0xFF; 800af10: 697b ldr r3, [r7, #20] 800af12: 0c1b lsrs r3, r3, #16 800af14: b2db uxtb r3, r3 800af16: 737b strb r3, [r7, #13] data.moduleCurrentTotal[2] = (current_ma >> 8) & 0xFF; 800af18: 697b ldr r3, [r7, #20] 800af1a: 0a1b lsrs r3, r3, #8 800af1c: b2db uxtb r3, r3 800af1e: 73bb strb r3, [r7, #14] data.moduleCurrentTotal[3] = (current_ma >> 0) & 0xFF; 800af20: 697b ldr r3, [r7, #20] 800af22: b2db uxtb r3, r3 800af24: 73fb strb r3, [r7, #15] data.moduleVoltage[0] = (voltage_mv >> 24) & 0xFF; 800af26: 693b ldr r3, [r7, #16] 800af28: 0e1b lsrs r3, r3, #24 800af2a: b2db uxtb r3, r3 800af2c: 723b strb r3, [r7, #8] data.moduleVoltage[1] = (voltage_mv >> 16) & 0xFF; 800af2e: 693b ldr r3, [r7, #16] 800af30: 0c1b lsrs r3, r3, #16 800af32: b2db uxtb r3, r3 800af34: 727b strb r3, [r7, #9] data.moduleVoltage[2] = (voltage_mv >> 8) & 0xFF; 800af36: 693b ldr r3, [r7, #16] 800af38: 0a1b lsrs r3, r3, #8 800af3a: b2db uxtb r3, r3 800af3c: 72bb strb r3, [r7, #10] data.moduleVoltage[3] = (voltage_mv >> 0) & 0xFF; 800af3e: 693b ldr r3, [r7, #16] 800af40: b2db uxtb r3, r3 800af42: 72fb strb r3, [r7, #11] PSU_SendCmd(0xF0, addr, 0x1C, &data); 800af44: 79f9 ldrb r1, [r7, #7] 800af46: f107 0308 add.w r3, r7, #8 800af4a: 221c movs r2, #28 800af4c: 20f0 movs r0, #240 @ 0xf0 800af4e: f000 f807 bl 800af60 800af52: e000 b.n 800af56 if(addr != 0) return; 800af54: bf00 nop } 800af56: 3718 adds r7, #24 800af58: 46bd mov sp, r7 800af5a: bd80 pop {r7, pc} 800af5c: 200008a4 .word 0x200008a4 0800af60 : void PSU_SendCmd(uint8_t source, uint8_t destination, uint8_t cmd, void *data){ 800af60: b580 push {r7, lr} 800af62: b08c sub sp, #48 @ 0x30 800af64: af00 add r7, sp, #0 800af66: 603b str r3, [r7, #0] 800af68: 4603 mov r3, r0 800af6a: 71fb strb r3, [r7, #7] 800af6c: 460b mov r3, r1 800af6e: 71bb strb r3, [r7, #6] 800af70: 4613 mov r3, r2 800af72: 717b strb r3, [r7, #5] CanId_t CanId; CanId.source = source; 800af74: 79fb ldrb r3, [r7, #7] 800af76: f887 3028 strb.w r3, [r7, #40] @ 0x28 CanId.destination = destination; 800af7a: 79bb ldrb r3, [r7, #6] 800af7c: f887 3029 strb.w r3, [r7, #41] @ 0x29 CanId.command = cmd; 800af80: 797b ldrb r3, [r7, #5] 800af82: f003 033f and.w r3, r3, #63 @ 0x3f 800af86: b2da uxtb r2, r3 800af88: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 800af8c: f362 0305 bfi r3, r2, #0, #6 800af90: f887 302a strb.w r3, [r7, #42] @ 0x2a CanId.device = 0x0A; 800af94: 8d7b ldrh r3, [r7, #42] @ 0x2a 800af96: 220a movs r2, #10 800af98: f362 1389 bfi r3, r2, #6, #4 800af9c: 857b strh r3, [r7, #42] @ 0x2a int8_t retry_counter = 10; 800af9e: 230a movs r3, #10 800afa0: f887 302f strb.w r3, [r7, #47] @ 0x2f CAN_TxHeaderTypeDef tx_header; uint32_t tx_mailbox; HAL_StatusTypeDef CAN_result; memcpy(&tx_header.ExtId, &CanId, sizeof(CanId_t)); 800afa4: 6abb ldr r3, [r7, #40] @ 0x28 800afa6: 617b str r3, [r7, #20] tx_header.RTR = CAN_RTR_DATA; 800afa8: 2300 movs r3, #0 800afaa: 61fb str r3, [r7, #28] tx_header.IDE = CAN_ID_EXT; 800afac: 2304 movs r3, #4 800afae: 61bb str r3, [r7, #24] tx_header.DLC = 8; 800afb0: 2308 movs r3, #8 800afb2: 623b str r3, [r7, #32] while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800afb4: e01e b.n 800aff4 if (HAL_CAN_GetTxMailboxesFreeLevel(&hcan2) > 0){ 800afb6: 4814 ldr r0, [pc, #80] @ (800b008 ) 800afb8: f003 fecc bl 800ed54 800afbc: 4603 mov r3, r0 800afbe: 2b00 cmp r3, #0 800afc0: d00e beq.n 800afe0 /* отправка сообщения */ CAN_result = HAL_CAN_AddTxMessage(&hcan2, &tx_header, (uint8_t*)data, &tx_mailbox); 800afc2: f107 030c add.w r3, r7, #12 800afc6: f107 0110 add.w r1, r7, #16 800afca: 683a ldr r2, [r7, #0] 800afcc: 480e ldr r0, [pc, #56] @ (800b008 ) 800afce: f003 fdf2 bl 800ebb6 800afd2: 4603 mov r3, r0 800afd4: f887 302e strb.w r3, [r7, #46] @ 0x2e /* если отправка удалась, выход */ if(CAN_result == HAL_OK) { 800afd8: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 800afdc: 2b00 cmp r3, #0 800afde: d00e beq.n 800affe return; retry_counter = 0; } } ED_Delay(1); 800afe0: 2001 movs r0, #1 800afe2: f7ff fb7f bl 800a6e4 retry_counter--; 800afe6: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800afea: b2db uxtb r3, r3 800afec: 3b01 subs r3, #1 800afee: b2db uxtb r3, r3 800aff0: f887 302f strb.w r3, [r7, #47] @ 0x2f while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800aff4: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800aff8: 2b00 cmp r3, #0 800affa: dcdc bgt.n 800afb6 800affc: e000 b.n 800b000 return; 800affe: bf00 nop } } 800b000: 3730 adds r7, #48 @ 0x30 800b002: 46bd mov sp, r7 800b004: bd80 pop {r7, pc} 800b006: bf00 nop 800b008: 20000328 .word 0x20000328 0800b00c : uint32_t max(uint32_t a, uint32_t b){ if(a>b) return a; else return b; } void PSU_ReadWrite(){ 800b00c: b580 push {r7, lr} 800b00e: b082 sub sp, #8 800b010: af00 add r7, sp, #0 uint8_t zero_data[8] = {0,0,0,0,0,0,0,0}; 800b012: 463b mov r3, r7 800b014: 2200 movs r2, #0 800b016: 601a str r2, [r3, #0] 800b018: 605a str r2, [r3, #4] PSU_SendCmd(0xF0, 0, 0x04, zero_data);ED_Delay(CAN_DELAY); 800b01a: 463b mov r3, r7 800b01c: 2204 movs r2, #4 800b01e: 2100 movs r1, #0 800b020: 20f0 movs r0, #240 @ 0xf0 800b022: f7ff ff9d bl 800af60 800b026: 2014 movs r0, #20 800b028: f7ff fb5c bl 800a6e4 PSU_SendCmd(0xF0, 0, 0x06, zero_data);ED_Delay(CAN_DELAY); 800b02c: 463b mov r3, r7 800b02e: 2206 movs r2, #6 800b030: 2100 movs r1, #0 800b032: 20f0 movs r0, #240 @ 0xf0 800b034: f7ff ff94 bl 800af60 800b038: 2014 movs r0, #20 800b03a: f7ff fb53 bl 800a6e4 // PSU_SendCmd(0xF0, 0, 0x08, zero_data);ED_Delay(CAN_DELAY); PSU_SendCmd(0xF0, 0, 0x09, zero_data);ED_Delay(CAN_DELAY); 800b03e: 463b mov r3, r7 800b040: 2209 movs r2, #9 800b042: 2100 movs r1, #0 800b044: 20f0 movs r0, #240 @ 0xf0 800b046: f7ff ff8b bl 800af60 800b04a: 2014 movs r0, #20 800b04c: f7ff fb4a bl 800a6e4 // Power Limit if ((CONN.WantedCurrent/10) * CONN.MeasuredVoltage > PSU0.power_limit){ 800b050: 4b46 ldr r3, [pc, #280] @ (800b16c ) 800b052: f8b3 301b ldrh.w r3, [r3, #27] 800b056: b29b uxth r3, r3 800b058: 4a45 ldr r2, [pc, #276] @ (800b170 ) 800b05a: fba2 2303 umull r2, r3, r2, r3 800b05e: 08db lsrs r3, r3, #3 800b060: b29b uxth r3, r3 800b062: 461a mov r2, r3 800b064: 4b41 ldr r3, [pc, #260] @ (800b16c ) 800b066: f8b3 3013 ldrh.w r3, [r3, #19] 800b06a: b29b uxth r3, r3 800b06c: fb02 f303 mul.w r3, r2, r3 800b070: 461a mov r2, r3 800b072: 4b40 ldr r3, [pc, #256] @ (800b174 ) 800b074: 695b ldr r3, [r3, #20] 800b076: 429a cmp r2, r3 800b078: d911 bls.n 800b09e CONN.RequestedCurrent = PSU0.power_limit * 10 / CONN.MeasuredVoltage; 800b07a: 4b3e ldr r3, [pc, #248] @ (800b174 ) 800b07c: 695a ldr r2, [r3, #20] 800b07e: 4613 mov r3, r2 800b080: 009b lsls r3, r3, #2 800b082: 4413 add r3, r2 800b084: 005b lsls r3, r3, #1 800b086: 461a mov r2, r3 800b088: 4b38 ldr r3, [pc, #224] @ (800b16c ) 800b08a: f8b3 3013 ldrh.w r3, [r3, #19] 800b08e: b29b uxth r3, r3 800b090: fbb2 f3f3 udiv r3, r2, r3 800b094: b29a uxth r2, r3 800b096: 4b35 ldr r3, [pc, #212] @ (800b16c ) 800b098: f8a3 2011 strh.w r2, [r3, #17] 800b09c: e006 b.n 800b0ac }else{ CONN.RequestedCurrent = CONN.WantedCurrent; 800b09e: 4b33 ldr r3, [pc, #204] @ (800b16c ) 800b0a0: f8b3 301b ldrh.w r3, [r3, #27] 800b0a4: b29a uxth r2, r3 800b0a6: 4b31 ldr r3, [pc, #196] @ (800b16c ) 800b0a8: f8a3 2011 strh.w r2, [r3, #17] } if(CONN.RequestedCurrent > (PSU_MAX_CURRENT*10)){ 800b0ac: 4b2f ldr r3, [pc, #188] @ (800b16c ) 800b0ae: f8b3 3011 ldrh.w r3, [r3, #17] 800b0b2: b29b uxth r3, r3 800b0b4: f240 5232 movw r2, #1330 @ 0x532 800b0b8: 4293 cmp r3, r2 800b0ba: d908 bls.n 800b0ce CONN.RequestedCurrent = PSU_MAX_CURRENT*10; 800b0bc: 4b2b ldr r3, [pc, #172] @ (800b16c ) 800b0be: 2200 movs r2, #0 800b0c0: f042 0232 orr.w r2, r2, #50 @ 0x32 800b0c4: 745a strb r2, [r3, #17] 800b0c6: 2200 movs r2, #0 800b0c8: f042 0205 orr.w r2, r2, #5 800b0cc: 749a strb r2, [r3, #18] } CONN.RequestedPower = CONN.RequestedCurrent * CONN.RequestedVoltage / 10; 800b0ce: 4b27 ldr r3, [pc, #156] @ (800b16c ) 800b0d0: f8b3 3011 ldrh.w r3, [r3, #17] 800b0d4: b29b uxth r3, r3 800b0d6: 461a mov r2, r3 800b0d8: 4b24 ldr r3, [pc, #144] @ (800b16c ) 800b0da: f8b3 300f ldrh.w r3, [r3, #15] 800b0de: b29b uxth r3, r3 800b0e0: fb02 f303 mul.w r3, r2, r3 800b0e4: 4a24 ldr r2, [pc, #144] @ (800b178 ) 800b0e6: fb82 1203 smull r1, r2, r2, r3 800b0ea: 1092 asrs r2, r2, #2 800b0ec: 17db asrs r3, r3, #31 800b0ee: 1ad3 subs r3, r2, r3 800b0f0: 461a mov r2, r3 800b0f2: 4b1e ldr r3, [pc, #120] @ (800b16c ) 800b0f4: f8c3 200b str.w r2, [r3, #11] if(PSU0.ready){ 800b0f8: 4b1e ldr r3, [pc, #120] @ (800b174 ) 800b0fa: 7a5b ldrb r3, [r3, #9] 800b0fc: 2b00 cmp r3, #0 800b0fe: d030 beq.n 800b162 PSU_SetVoltageCurrent(0, CONN.RequestedVoltage, CONN.RequestedCurrent); // Normal mode 800b100: 4b1a ldr r3, [pc, #104] @ (800b16c ) 800b102: f8b3 300f ldrh.w r3, [r3, #15] 800b106: b29b uxth r3, r3 800b108: 4a18 ldr r2, [pc, #96] @ (800b16c ) 800b10a: f8b2 2011 ldrh.w r2, [r2, #17] 800b10e: b292 uxth r2, r2 800b110: 4619 mov r1, r3 800b112: 2000 movs r0, #0 800b114: f7ff feca bl 800aeac ED_Delay(CAN_DELAY); 800b118: 2014 movs r0, #20 800b11a: f7ff fae3 bl 800a6e4 if(CONN.MeasuredVoltage > 490){ 800b11e: 4b13 ldr r3, [pc, #76] @ (800b16c ) 800b120: f8b3 3013 ldrh.w r3, [r3, #19] 800b124: b29b uxth r3, r3 800b126: f5b3 7ff5 cmp.w r3, #490 @ 0x1ea 800b12a: d917 bls.n 800b15c if(PSU0.hv_tick == 0){ 800b12c: 4b11 ldr r3, [pc, #68] @ (800b174 ) 800b12e: 69db ldr r3, [r3, #28] 800b130: 2b00 cmp r3, #0 800b132: d105 bne.n 800b140 PSU0.hv_tick = HAL_GetTick(); 800b134: f002 fda2 bl 800dc7c 800b138: 4603 mov r3, r0 800b13a: 4a0e ldr r2, [pc, #56] @ (800b174 ) 800b13c: 61d3 str r3, [r2, #28] } // PSU_SetHVMode(0, PSU0.hv_mode); // auto set, no need // ED_Delay(CAN_DELAY); } 800b13e: e010 b.n 800b162 }else if((HAL_GetTick() - PSU0.hv_tick) >= 10000){ 800b140: f002 fd9c bl 800dc7c 800b144: 4602 mov r2, r0 800b146: 4b0b ldr r3, [pc, #44] @ (800b174 ) 800b148: 69db ldr r3, [r3, #28] 800b14a: 1ad3 subs r3, r2, r3 800b14c: f242 720f movw r2, #9999 @ 0x270f 800b150: 4293 cmp r3, r2 800b152: d906 bls.n 800b162 PSU0.hv_mode = 1; 800b154: 4b07 ldr r3, [pc, #28] @ (800b174 ) 800b156: 2201 movs r2, #1 800b158: 761a strb r2, [r3, #24] } 800b15a: e002 b.n 800b162 PSU0.hv_tick = 0; 800b15c: 4b05 ldr r3, [pc, #20] @ (800b174 ) 800b15e: 2200 movs r2, #0 800b160: 61da str r2, [r3, #28] } 800b162: bf00 nop 800b164: 3708 adds r7, #8 800b166: 46bd mov sp, r7 800b168: bd80 pop {r7, pc} 800b16a: bf00 nop 800b16c: 20000354 .word 0x20000354 800b170: cccccccd .word 0xcccccccd 800b174: 200008a4 .word 0x200008a4 800b178: 66666667 .word 0x66666667 0800b17c : void PSU_Task(void){ 800b17c: b598 push {r3, r4, r7, lr} 800b17e: af00 add r7, sp, #0 static uint32_t psu_on_tick = 0; static uint32_t dc_on_tick = 0; static uint32_t cont_ok_tick = 0; // Обновляем ONLINE/READY по таймауту if((HAL_GetTick() - can_lastpacket) > PSU_ONLINE_TIMEOUT){ 800b180: f002 fd7c bl 800dc7c 800b184: 4602 mov r2, r0 800b186: 4bb5 ldr r3, [pc, #724] @ (800b45c ) 800b188: 681b ldr r3, [r3, #0] 800b18a: 1ad3 subs r3, r2, r3 800b18c: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b190: d920 bls.n 800b1d4 PSU0.online = 0; 800b192: 4bb3 ldr r3, [pc, #716] @ (800b460 ) 800b194: 2200 movs r2, #0 800b196: 721a strb r2, [r3, #8] PSU0.PSU_enabled = 0; 800b198: 4bb1 ldr r3, [pc, #708] @ (800b460 ) 800b19a: 2200 movs r2, #0 800b19c: 729a strb r2, [r3, #10] PSU_04.moduleTemperature = 0; 800b19e: 4bb1 ldr r3, [pc, #708] @ (800b464 ) 800b1a0: 2200 movs r2, #0 800b1a2: 711a strb r2, [r3, #4] PSU_04.modularForm0 = 0; 800b1a4: 4baf ldr r3, [pc, #700] @ (800b464 ) 800b1a6: 2200 movs r2, #0 800b1a8: 721a strb r2, [r3, #8] PSU_04.modularForm1 = 0; 800b1aa: 4bae ldr r3, [pc, #696] @ (800b464 ) 800b1ac: 2200 movs r2, #0 800b1ae: 71da strb r2, [r3, #7] PSU_04.modularForm2 = 0; 800b1b0: 4bac ldr r3, [pc, #688] @ (800b464 ) 800b1b2: 2200 movs r2, #0 800b1b4: 719a strb r2, [r3, #6] PSU_06.VAB = 0; 800b1b6: 4bac ldr r3, [pc, #688] @ (800b468 ) 800b1b8: 2200 movs r2, #0 800b1ba: 609a str r2, [r3, #8] PSU_06.VBC = 0; 800b1bc: 4baa ldr r3, [pc, #680] @ (800b468 ) 800b1be: 2200 movs r2, #0 800b1c0: 60da str r2, [r3, #12] PSU_06.VCA = 0; 800b1c2: 4ba9 ldr r3, [pc, #676] @ (800b468 ) 800b1c4: 2200 movs r2, #0 800b1c6: 611a str r2, [r3, #16] PSU_09.moduleNCurrent = 0; 800b1c8: 4ba8 ldr r3, [pc, #672] @ (800b46c ) 800b1ca: 2200 movs r2, #0 800b1cc: 60da str r2, [r3, #12] PSU_09.moduleNVoltage = 0; 800b1ce: 4ba7 ldr r3, [pc, #668] @ (800b46c ) 800b1d0: 2200 movs r2, #0 800b1d2: 609a str r2, [r3, #8] } if(!PSU0.online || !PSU0.enableAC){ 800b1d4: 4ba2 ldr r3, [pc, #648] @ (800b460 ) 800b1d6: 7a1b ldrb r3, [r3, #8] 800b1d8: 2b00 cmp r3, #0 800b1da: d003 beq.n 800b1e4 800b1dc: 4ba0 ldr r3, [pc, #640] @ (800b460 ) 800b1de: 781b ldrb r3, [r3, #0] 800b1e0: 2b00 cmp r3, #0 800b1e2: d10c bne.n 800b1fe CONN.MeasuredVoltage = 0; 800b1e4: 4ba2 ldr r3, [pc, #648] @ (800b470 ) 800b1e6: 2200 movs r2, #0 800b1e8: 74da strb r2, [r3, #19] 800b1ea: 2200 movs r2, #0 800b1ec: 751a strb r2, [r3, #20] CONN.MeasuredCurrent = 0; 800b1ee: 4ba0 ldr r3, [pc, #640] @ (800b470 ) 800b1f0: 2200 movs r2, #0 800b1f2: 755a strb r2, [r3, #21] 800b1f4: 2200 movs r2, #0 800b1f6: 759a strb r2, [r3, #22] CONN.outputEnabled = 0; 800b1f8: 4b9d ldr r3, [pc, #628] @ (800b470 ) 800b1fa: 2200 movs r2, #0 800b1fc: 761a strb r2, [r3, #24] } // Управление AC-контактором с задержкой отключения 1 минута if(CONN.EvConnected){ 800b1fe: 4b9c ldr r3, [pc, #624] @ (800b470 ) 800b200: 7f9b ldrb r3, [r3, #30] 800b202: 2b00 cmp r3, #0 800b204: d00c beq.n 800b220 RELAY_Write(RELAY_AC, 1); 800b206: 2101 movs r1, #1 800b208: 2004 movs r0, #4 800b20a: f7fe fa1f bl 800964c psu_on_tick = HAL_GetTick(); 800b20e: f002 fd35 bl 800dc7c 800b212: 4603 mov r3, r0 800b214: 4a97 ldr r2, [pc, #604] @ (800b474 ) 800b216: 6013 str r3, [r2, #0] PSU0.enableAC = 1; 800b218: 4b91 ldr r3, [pc, #580] @ (800b460 ) 800b21a: 2201 movs r2, #1 800b21c: 701a strb r2, [r3, #0] 800b21e: e010 b.n 800b242 }else{ if((HAL_GetTick() - psu_on_tick) > 1 * 60000){ 800b220: f002 fd2c bl 800dc7c 800b224: 4602 mov r2, r0 800b226: 4b93 ldr r3, [pc, #588] @ (800b474 ) 800b228: 681b ldr r3, [r3, #0] 800b22a: 1ad3 subs r3, r2, r3 800b22c: f64e 2260 movw r2, #60000 @ 0xea60 800b230: 4293 cmp r3, r2 800b232: d906 bls.n 800b242 RELAY_Write(RELAY_AC, 0); 800b234: 2100 movs r1, #0 800b236: 2004 movs r0, #4 800b238: f7fe fa08 bl 800964c PSU0.enableAC = 0; 800b23c: 4b88 ldr r3, [pc, #544] @ (800b460 ) 800b23e: 2200 movs r2, #0 800b240: 701a strb r2, [r3, #0] } } // Текущее состояние DC-контактора по обратной связи PSU0.CONT_enabled = IN_ReadInput(IN_CONT_FB_DC); 800b242: 2005 movs r0, #5 800b244: f7fe fa82 bl 800974c 800b248: 4603 mov r3, r0 800b24a: 461a mov r2, r3 800b24c: 4b84 ldr r3, [pc, #528] @ (800b460 ) 800b24e: 72da strb r2, [r3, #11] // Обновляем ready с учётом ошибок if(PSU0.online && !PSU0.cont_fault && PSU0.enableAC){ 800b250: 4b83 ldr r3, [pc, #524] @ (800b460 ) 800b252: 7a1b ldrb r3, [r3, #8] 800b254: 2b00 cmp r3, #0 800b256: d007 beq.n 800b268 800b258: 4b81 ldr r3, [pc, #516] @ (800b460 ) 800b25a: 7b1b ldrb r3, [r3, #12] 800b25c: 2b00 cmp r3, #0 800b25e: d103 bne.n 800b268 800b260: 4b7f ldr r3, [pc, #508] @ (800b460 ) 800b262: 781b ldrb r3, [r3, #0] 800b264: 2b00 cmp r3, #0 800b266: d102 bne.n 800b26e // PSU0.ready = 1; }else{ PSU0.ready = 0; 800b268: 4b7d ldr r3, [pc, #500] @ (800b460 ) 800b26a: 2200 movs r2, #0 800b26c: 725a strb r2, [r3, #9] } switch(PSU0.state){ 800b26e: 4b7c ldr r3, [pc, #496] @ (800b460 ) 800b270: 79db ldrb r3, [r3, #7] 800b272: 2b09 cmp r3, #9 800b274: f200 8157 bhi.w 800b526 800b278: a201 add r2, pc, #4 @ (adr r2, 800b280 ) 800b27a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b27e: bf00 nop 800b280: 0800b2a9 .word 0x0800b2a9 800b284: 0800b2dd .word 0x0800b2dd 800b288: 0800b2f9 .word 0x0800b2f9 800b28c: 0800b337 .word 0x0800b337 800b290: 0800b385 .word 0x0800b385 800b294: 0800b3c7 .word 0x0800b3c7 800b298: 0800b431 .word 0x0800b431 800b29c: 0800b4d9 .word 0x0800b4d9 800b2a0: 0800b489 .word 0x0800b489 800b2a4: 0800b513 .word 0x0800b513 case PSU_UNREADY: PSU0.enableOutput = 0; 800b2a8: 4b6d ldr r3, [pc, #436] @ (800b460 ) 800b2aa: 2200 movs r2, #0 800b2ac: 705a strb r2, [r3, #1] RELAY_Write(RELAY_DC, 0); 800b2ae: 2100 movs r1, #0 800b2b0: 2003 movs r0, #3 800b2b2: f7fe f9cb bl 800964c if(PSU0.online && PSU0.enableAC && !PSU0.cont_fault){ 800b2b6: 4b6a ldr r3, [pc, #424] @ (800b460 ) 800b2b8: 7a1b ldrb r3, [r3, #8] 800b2ba: 2b00 cmp r3, #0 800b2bc: f000 8137 beq.w 800b52e 800b2c0: 4b67 ldr r3, [pc, #412] @ (800b460 ) 800b2c2: 781b ldrb r3, [r3, #0] 800b2c4: 2b00 cmp r3, #0 800b2c6: f000 8132 beq.w 800b52e 800b2ca: 4b65 ldr r3, [pc, #404] @ (800b460 ) 800b2cc: 7b1b ldrb r3, [r3, #12] 800b2ce: 2b00 cmp r3, #0 800b2d0: f040 812d bne.w 800b52e PSU_SwitchState(PSU_INITIALIZING); 800b2d4: 2001 movs r0, #1 800b2d6: f7ff fc0d bl 800aaf4 } break; 800b2da: e128 b.n 800b52e case PSU_INITIALIZING: if(PSU_StateTime() > 4000){ // Wait 4s for PSU to initialize 800b2dc: f7ff fc1e bl 800ab1c 800b2e0: 4603 mov r3, r0 800b2e2: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b2e6: f240 8124 bls.w 800b532 PSU0.ready = 1; 800b2ea: 4b5d ldr r3, [pc, #372] @ (800b460 ) 800b2ec: 2201 movs r2, #1 800b2ee: 725a strb r2, [r3, #9] PSU_SwitchState(PSU_READY); 800b2f0: 2002 movs r0, #2 800b2f2: f7ff fbff bl 800aaf4 } break; 800b2f6: e11c b.n 800b532 case PSU_READY: // модуль готов, но выключен PSU0.hv_mode = 0; 800b2f8: 4b59 ldr r3, [pc, #356] @ (800b460 ) 800b2fa: 2200 movs r2, #0 800b2fc: 761a strb r2, [r3, #24] PSU0.hv_tick = 0; 800b2fe: 4b58 ldr r3, [pc, #352] @ (800b460 ) 800b300: 2200 movs r2, #0 800b302: 61da str r2, [r3, #28] RELAY_Write(RELAY_DC, 0); 800b304: 2100 movs r1, #0 800b306: 2003 movs r0, #3 800b308: f7fe f9a0 bl 800964c if(!PSU0.ready){ 800b30c: 4b54 ldr r3, [pc, #336] @ (800b460 ) 800b30e: 7a5b ldrb r3, [r3, #9] 800b310: 2b00 cmp r3, #0 800b312: d103 bne.n 800b31c PSU_SwitchState(PSU_UNREADY); 800b314: 2000 movs r0, #0 800b316: f7ff fbed bl 800aaf4 break; 800b31a: e11b b.n 800b554 } if(CONN.EnableOutput){ 800b31c: 4b54 ldr r3, [pc, #336] @ (800b470 ) 800b31e: 7ddb ldrb r3, [r3, #23] 800b320: 2b00 cmp r3, #0 800b322: f000 8108 beq.w 800b536 PSU_Enable(0, 1); 800b326: 2101 movs r1, #1 800b328: 2000 movs r0, #0 800b32a: f7ff fd8f bl 800ae4c PSU_SwitchState(PSU_WAIT_ACK_ON); 800b32e: 2003 movs r0, #3 800b330: f7ff fbe0 bl 800aaf4 } break; 800b334: e0ff b.n 800b536 case PSU_WAIT_ACK_ON: if(PSU0.PSU_enabled && PSU0.ready){ 800b336: 4b4a ldr r3, [pc, #296] @ (800b460 ) 800b338: 7a9b ldrb r3, [r3, #10] 800b33a: 2b00 cmp r3, #0 800b33c: d00c beq.n 800b358 800b33e: 4b48 ldr r3, [pc, #288] @ (800b460 ) 800b340: 7a5b ldrb r3, [r3, #9] 800b342: 2b00 cmp r3, #0 800b344: d008 beq.n 800b358 dc_on_tick = HAL_GetTick(); 800b346: f002 fc99 bl 800dc7c 800b34a: 4603 mov r3, r0 800b34c: 4a4a ldr r2, [pc, #296] @ (800b478 ) 800b34e: 6013 str r3, [r2, #0] PSU_SwitchState(PSU_CONT_WAIT_ACK_ON); 800b350: 2004 movs r0, #4 800b352: f7ff fbcf bl 800aaf4 PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU on timeout\n"); } break; 800b356: e0f0 b.n 800b53a }else if(PSU_StateTime() > 10000){ 800b358: f7ff fbe0 bl 800ab1c 800b35c: 4603 mov r3, r0 800b35e: f242 7210 movw r2, #10000 @ 0x2710 800b362: 4293 cmp r3, r2 800b364: f240 80e9 bls.w 800b53a PSU0.psu_fault = 1; 800b368: 4b3d ldr r3, [pc, #244] @ (800b460 ) 800b36a: 2201 movs r2, #1 800b36c: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b36e: 4b40 ldr r3, [pc, #256] @ (800b470 ) 800b370: 220a movs r2, #10 800b372: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b374: 2000 movs r0, #0 800b376: f7ff fbbd bl 800aaf4 log_printf(LOG_ERR, "PSU on timeout\n"); 800b37a: 4940 ldr r1, [pc, #256] @ (800b47c ) 800b37c: 2004 movs r0, #4 800b37e: f7ff f81f bl 800a3c0 break; 800b382: e0da b.n 800b53a case PSU_CONT_WAIT_ACK_ON: // замыкаем DC-контактор и ждём подтверждение RELAY_Write(RELAY_DC, 1); 800b384: 2101 movs r1, #1 800b386: 2003 movs r0, #3 800b388: f7fe f960 bl 800964c if(PSU0.CONT_enabled){ 800b38c: 4b34 ldr r3, [pc, #208] @ (800b460 ) 800b38e: 7adb ldrb r3, [r3, #11] 800b390: 2b00 cmp r3, #0 800b392: d003 beq.n 800b39c PSU_SwitchState(PSU_CONNECTED); 800b394: 2005 movs r0, #5 800b396: f7ff fbad bl 800aaf4 PSU0.cont_fault = 1; CONN.chargingError = CONN_ERR_CONTACTOR; PSU_SwitchState(PSU_CURRENT_DROP); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b39a: e0d0 b.n 800b53e }else if(PSU_StateTime() > 1000){ 800b39c: f7ff fbbe bl 800ab1c 800b3a0: 4603 mov r3, r0 800b3a2: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b3a6: f240 80ca bls.w 800b53e PSU0.cont_fault = 1; 800b3aa: 4b2d ldr r3, [pc, #180] @ (800b460 ) 800b3ac: 2201 movs r2, #1 800b3ae: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b3b0: 4b2f ldr r3, [pc, #188] @ (800b470 ) 800b3b2: 2207 movs r2, #7 800b3b4: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_CURRENT_DROP); 800b3b6: 2006 movs r0, #6 800b3b8: f7ff fb9c bl 800aaf4 log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b3bc: 4930 ldr r1, [pc, #192] @ (800b480 ) 800b3be: 2004 movs r0, #4 800b3c0: f7fe fffe bl 800a3c0 break; 800b3c4: e0bb b.n 800b53e case PSU_CONNECTED: // Основное рабочее состояние if(!CONN.EnableOutput || !PSU0.ready){ 800b3c6: 4b2a ldr r3, [pc, #168] @ (800b470 ) 800b3c8: 7ddb ldrb r3, [r3, #23] 800b3ca: 2b00 cmp r3, #0 800b3cc: d003 beq.n 800b3d6 800b3ce: 4b24 ldr r3, [pc, #144] @ (800b460 ) 800b3d0: 7a5b ldrb r3, [r3, #9] 800b3d2: 2b00 cmp r3, #0 800b3d4: d103 bne.n 800b3de PSU_SwitchState(PSU_CURRENT_DROP); 800b3d6: 2006 movs r0, #6 800b3d8: f7ff fb8c bl 800aaf4 break; 800b3dc: e0ba b.n 800b554 } // контроль контактора: 1 c таймаут if (IN_ReadInput(IN_CONT_FB_DC) != RELAY_Read(RELAY_DC)){ 800b3de: 2005 movs r0, #5 800b3e0: f7fe f9b4 bl 800974c 800b3e4: 4603 mov r3, r0 800b3e6: 461c mov r4, r3 800b3e8: 2003 movs r0, #3 800b3ea: f7fe f99f bl 800972c 800b3ee: 4603 mov r3, r0 800b3f0: 429c cmp r4, r3 800b3f2: d017 beq.n 800b424 if((HAL_GetTick() - cont_ok_tick) > 1000){ 800b3f4: f002 fc42 bl 800dc7c 800b3f8: 4602 mov r2, r0 800b3fa: 4b22 ldr r3, [pc, #136] @ (800b484 ) 800b3fc: 681b ldr r3, [r3, #0] 800b3fe: 1ad3 subs r3, r2, r3 800b400: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b404: f240 809d bls.w 800b542 CONN.chargingError = CONN_ERR_CONTACTOR; 800b408: 4b19 ldr r3, [pc, #100] @ (800b470 ) 800b40a: 2207 movs r2, #7 800b40c: 775a strb r2, [r3, #29] PSU0.cont_fault = 1; 800b40e: 4b14 ldr r3, [pc, #80] @ (800b460 ) 800b410: 2201 movs r2, #1 800b412: 731a strb r2, [r3, #12] PSU_SwitchState(PSU_CURRENT_DROP); 800b414: 2006 movs r0, #6 800b416: f7ff fb6d bl 800aaf4 log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b41a: 4919 ldr r1, [pc, #100] @ (800b480 ) 800b41c: 2004 movs r0, #4 800b41e: f7fe ffcf bl 800a3c0 } }else{ cont_ok_tick = HAL_GetTick(); } break; 800b422: e08e b.n 800b542 cont_ok_tick = HAL_GetTick(); 800b424: f002 fc2a bl 800dc7c 800b428: 4603 mov r3, r0 800b42a: 4a16 ldr r2, [pc, #88] @ (800b484 ) 800b42c: 6013 str r3, [r2, #0] break; 800b42e: e088 b.n 800b542 case PSU_CURRENT_DROP: // снижаем ток до нуля перед отключением DC CONN.RequestedCurrent = 0; 800b430: 4b0f ldr r3, [pc, #60] @ (800b470 ) 800b432: 2200 movs r2, #0 800b434: 745a strb r2, [r3, #17] 800b436: 2200 movs r2, #0 800b438: 749a strb r2, [r3, #18] // если ток действительно упал или вышло время, отключаем DC if((CONN.MeasuredCurrent < 30) || (PSU_StateTime() > 5000)){ 800b43a: 4b0d ldr r3, [pc, #52] @ (800b470 ) 800b43c: f8b3 3015 ldrh.w r3, [r3, #21] 800b440: b29b uxth r3, r3 800b442: 2b1d cmp r3, #29 800b444: d906 bls.n 800b454 800b446: f7ff fb69 bl 800ab1c 800b44a: 4603 mov r3, r0 800b44c: f241 3288 movw r2, #5000 @ 0x1388 800b450: 4293 cmp r3, r2 800b452: d978 bls.n 800b546 PSU_SwitchState(PSU_CONT_WAIT_ACK_OFF); 800b454: 2008 movs r0, #8 800b456: f7ff fb4d bl 800aaf4 } break; 800b45a: e074 b.n 800b546 800b45c: 200008cc .word 0x200008cc 800b460: 200008a4 .word 0x200008a4 800b464: 2000086c .word 0x2000086c 800b468: 20000878 .word 0x20000878 800b46c: 20000894 .word 0x20000894 800b470: 20000354 .word 0x20000354 800b474: 200008f4 .word 0x200008f4 800b478: 200008f8 .word 0x200008f8 800b47c: 08016118 .word 0x08016118 800b480: 08016128 .word 0x08016128 800b484: 200008fc .word 0x200008fc case PSU_CONT_WAIT_ACK_OFF: RELAY_Write(RELAY_DC, 0); 800b488: 2100 movs r1, #0 800b48a: 2003 movs r0, #3 800b48c: f7fe f8de bl 800964c if(!PSU0.CONT_enabled){ 800b490: 4b31 ldr r3, [pc, #196] @ (800b558 ) 800b492: 7adb ldrb r3, [r3, #11] 800b494: 2b00 cmp r3, #0 800b496: d107 bne.n 800b4a8 PSU_Enable(0, 0); 800b498: 2100 movs r1, #0 800b49a: 2000 movs r0, #0 800b49c: f7ff fcd6 bl 800ae4c PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b4a0: 2007 movs r0, #7 800b4a2: f7ff fb27 bl 800aaf4 CONN.chargingError = CONN_ERR_CONTACTOR; PSU_Enable(0, 0); PSU_SwitchState(PSU_WAIT_ACK_OFF); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b4a6: e050 b.n 800b54a }else if(PSU_StateTime() > 1000){ 800b4a8: f7ff fb38 bl 800ab1c 800b4ac: 4603 mov r3, r0 800b4ae: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b4b2: d94a bls.n 800b54a PSU0.cont_fault = 1; 800b4b4: 4b28 ldr r3, [pc, #160] @ (800b558 ) 800b4b6: 2201 movs r2, #1 800b4b8: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b4ba: 4b28 ldr r3, [pc, #160] @ (800b55c ) 800b4bc: 2207 movs r2, #7 800b4be: 775a strb r2, [r3, #29] PSU_Enable(0, 0); 800b4c0: 2100 movs r1, #0 800b4c2: 2000 movs r0, #0 800b4c4: f7ff fcc2 bl 800ae4c PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b4c8: 2007 movs r0, #7 800b4ca: f7ff fb13 bl 800aaf4 log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b4ce: 4924 ldr r1, [pc, #144] @ (800b560 ) 800b4d0: 2004 movs r0, #4 800b4d2: f7fe ff75 bl 800a3c0 break; 800b4d6: e038 b.n 800b54a case PSU_WAIT_ACK_OFF: if(!PSU0.PSU_enabled){ 800b4d8: 4b1f ldr r3, [pc, #124] @ (800b558 ) 800b4da: 7a9b ldrb r3, [r3, #10] 800b4dc: 2b00 cmp r3, #0 800b4de: d103 bne.n 800b4e8 PSU_SwitchState(PSU_OFF_PAUSE); 800b4e0: 2009 movs r0, #9 800b4e2: f7ff fb07 bl 800aaf4 PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU off timeout\n"); } break; 800b4e6: e032 b.n 800b54e }else if(PSU_StateTime() > 10000){ 800b4e8: f7ff fb18 bl 800ab1c 800b4ec: 4603 mov r3, r0 800b4ee: f242 7210 movw r2, #10000 @ 0x2710 800b4f2: 4293 cmp r3, r2 800b4f4: d92b bls.n 800b54e PSU0.psu_fault = 1; 800b4f6: 4b18 ldr r3, [pc, #96] @ (800b558 ) 800b4f8: 2201 movs r2, #1 800b4fa: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b4fc: 4b17 ldr r3, [pc, #92] @ (800b55c ) 800b4fe: 220a movs r2, #10 800b500: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b502: 2000 movs r0, #0 800b504: f7ff faf6 bl 800aaf4 log_printf(LOG_ERR, "PSU off timeout\n"); 800b508: 4916 ldr r1, [pc, #88] @ (800b564 ) 800b50a: 2004 movs r0, #4 800b50c: f7fe ff58 bl 800a3c0 break; 800b510: e01d b.n 800b54e case PSU_OFF_PAUSE: if(PSU_StateTime() > 4000){ 800b512: f7ff fb03 bl 800ab1c 800b516: 4603 mov r3, r0 800b518: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b51c: d919 bls.n 800b552 PSU_SwitchState(PSU_READY); 800b51e: 2002 movs r0, #2 800b520: f7ff fae8 bl 800aaf4 } break; 800b524: e015 b.n 800b552 default: PSU_SwitchState(PSU_UNREADY); 800b526: 2000 movs r0, #0 800b528: f7ff fae4 bl 800aaf4 break; 800b52c: e012 b.n 800b554 break; 800b52e: bf00 nop 800b530: e010 b.n 800b554 break; 800b532: bf00 nop 800b534: e00e b.n 800b554 break; 800b536: bf00 nop 800b538: e00c b.n 800b554 break; 800b53a: bf00 nop 800b53c: e00a b.n 800b554 break; 800b53e: bf00 nop 800b540: e008 b.n 800b554 break; 800b542: bf00 nop 800b544: e006 b.n 800b554 break; 800b546: bf00 nop 800b548: e004 b.n 800b554 break; 800b54a: bf00 nop 800b54c: e002 b.n 800b554 break; 800b54e: bf00 nop 800b550: e000 b.n 800b554 break; 800b552: bf00 nop } } 800b554: bf00 nop 800b556: bd98 pop {r3, r4, r7, pc} 800b558: 200008a4 .word 0x200008a4 800b55c: 20000354 .word 0x20000354 800b560: 08016128 .word 0x08016128 800b564: 08016148 .word 0x08016148 0800b568 : .Th = 10, .Tf = 50, .Tl = 0, }; void LED_Write(){ 800b568: b580 push {r7, lr} 800b56a: af00 add r7, sp, #0 if(CONN.chargingError != CONN_NO_ERROR){ 800b56c: 4b3c ldr r3, [pc, #240] @ (800b660 ) 800b56e: 7f5b ldrb r3, [r3, #29] 800b570: 2b00 cmp r3, #0 800b572: d003 beq.n 800b57c LED_SetColor(&color_error); 800b574: 483b ldr r0, [pc, #236] @ (800b664 ) 800b576: f000 f933 bl 800b7e0 return; 800b57a: e06f b.n 800b65c } if(CONN.connControl == CMD_FORCE_UNLOCK){ 800b57c: 4b38 ldr r3, [pc, #224] @ (800b660 ) 800b57e: 781b ldrb r3, [r3, #0] 800b580: 2b03 cmp r3, #3 800b582: d103 bne.n 800b58c LED_SetColor(&color_unlock); 800b584: 4838 ldr r0, [pc, #224] @ (800b668 ) 800b586: f000 f92b bl 800b7e0 return; 800b58a: e067 b.n 800b65c } if(CONN.connControl == CMD_STOP){ 800b58c: 4b34 ldr r3, [pc, #208] @ (800b660 ) 800b58e: 781b ldrb r3, [r3, #0] 800b590: 2b01 cmp r3, #1 800b592: d103 bne.n 800b59c LED_SetColor(&color_estop); 800b594: 4835 ldr r0, [pc, #212] @ (800b66c ) 800b596: f000 f923 bl 800b7e0 return; 800b59a: e05f b.n 800b65c } switch(CONN.connState){ 800b59c: 4b30 ldr r3, [pc, #192] @ (800b660 ) 800b59e: 785b ldrb r3, [r3, #1] 800b5a0: 2b0d cmp r3, #13 800b5a2: d857 bhi.n 800b654 800b5a4: a201 add r2, pc, #4 @ (adr r2, 800b5ac ) 800b5a6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b5aa: bf00 nop 800b5ac: 0800b5e5 .word 0x0800b5e5 800b5b0: 0800b5ed .word 0x0800b5ed 800b5b4: 0800b5f5 .word 0x0800b5f5 800b5b8: 0800b5fd .word 0x0800b5fd 800b5bc: 0800b605 .word 0x0800b605 800b5c0: 0800b60d .word 0x0800b60d 800b5c4: 0800b615 .word 0x0800b615 800b5c8: 0800b61d .word 0x0800b61d 800b5cc: 0800b625 .word 0x0800b625 800b5d0: 0800b62d .word 0x0800b62d 800b5d4: 0800b635 .word 0x0800b635 800b5d8: 0800b63d .word 0x0800b63d 800b5dc: 0800b645 .word 0x0800b645 800b5e0: 0800b64d .word 0x0800b64d case Unknown: LED_SetColor(&color_unknown); 800b5e4: 4822 ldr r0, [pc, #136] @ (800b670 ) 800b5e6: f000 f8fb bl 800b7e0 break; 800b5ea: e037 b.n 800b65c case Unplugged: LED_SetColor(&color_unplugged); 800b5ec: 4821 ldr r0, [pc, #132] @ (800b674 ) 800b5ee: f000 f8f7 bl 800b7e0 break; 800b5f2: e033 b.n 800b65c case Disabled: LED_SetColor(&color_error); 800b5f4: 481b ldr r0, [pc, #108] @ (800b664 ) 800b5f6: f000 f8f3 bl 800b7e0 break; 800b5fa: e02f b.n 800b65c case Preparing: LED_SetColor(&color_preparing); 800b5fc: 481e ldr r0, [pc, #120] @ (800b678 ) 800b5fe: f000 f8ef bl 800b7e0 break; 800b602: e02b b.n 800b65c case AuthRequired: LED_SetColor(&color_preparing); 800b604: 481c ldr r0, [pc, #112] @ (800b678 ) 800b606: f000 f8eb bl 800b7e0 break; 800b60a: e027 b.n 800b65c case WaitingForEnergy: LED_SetColor(&color_charging); 800b60c: 481b ldr r0, [pc, #108] @ (800b67c ) 800b60e: f000 f8e7 bl 800b7e0 break; 800b612: e023 b.n 800b65c case ChargingPausedEV: LED_SetColor(&color_charging); 800b614: 4819 ldr r0, [pc, #100] @ (800b67c ) 800b616: f000 f8e3 bl 800b7e0 break; 800b61a: e01f b.n 800b65c case ChargingPausedEVSE: LED_SetColor(&color_charging); 800b61c: 4817 ldr r0, [pc, #92] @ (800b67c ) 800b61e: f000 f8df bl 800b7e0 break; 800b622: e01b b.n 800b65c case Charging: LED_SetColor(&color_charging); 800b624: 4815 ldr r0, [pc, #84] @ (800b67c ) 800b626: f000 f8db bl 800b7e0 break; 800b62a: e017 b.n 800b65c case AuthTimeout: LED_SetColor(&color_finished); 800b62c: 4814 ldr r0, [pc, #80] @ (800b680 ) 800b62e: f000 f8d7 bl 800b7e0 break; 800b632: e013 b.n 800b65c case Finished: LED_SetColor(&color_finished); 800b634: 4812 ldr r0, [pc, #72] @ (800b680 ) 800b636: f000 f8d3 bl 800b7e0 break; 800b63a: e00f b.n 800b65c case FinishedEVSE: LED_SetColor(&color_finished); 800b63c: 4810 ldr r0, [pc, #64] @ (800b680 ) 800b63e: f000 f8cf bl 800b7e0 break; 800b642: e00b b.n 800b65c case FinishedEV: LED_SetColor(&color_finished); 800b644: 480e ldr r0, [pc, #56] @ (800b680 ) 800b646: f000 f8cb bl 800b7e0 break; 800b64a: e007 b.n 800b65c case Replugging: LED_SetColor(&color_preparing); 800b64c: 480a ldr r0, [pc, #40] @ (800b678 ) 800b64e: f000 f8c7 bl 800b7e0 break; 800b652: e003 b.n 800b65c default: LED_SetColor(&color_unknown); 800b654: 4806 ldr r0, [pc, #24] @ (800b670 ) 800b656: f000 f8c3 bl 800b7e0 break; 800b65a: bf00 nop } } 800b65c: bd80 pop {r7, pc} 800b65e: bf00 nop 800b660: 20000354 .word 0x20000354 800b664: 2000005c .word 0x2000005c 800b668: 20000014 .word 0x20000014 800b66c: 20000008 .word 0x20000008 800b670: 20000020 .word 0x20000020 800b674: 2000002c .word 0x2000002c 800b678: 20000038 .word 0x20000038 800b67c: 20000044 .word 0x20000044 800b680: 20000050 .word 0x20000050 0800b684 : void interpolateColors(RGB_t* color1, RGB_t* color2, uint16_t a, uint16_t b, RGB_t *result) { 800b684: b480 push {r7} 800b686: b087 sub sp, #28 800b688: af00 add r7, sp, #0 800b68a: 60f8 str r0, [r7, #12] 800b68c: 60b9 str r1, [r7, #8] 800b68e: 4611 mov r1, r2 800b690: 461a mov r2, r3 800b692: 460b mov r3, r1 800b694: 80fb strh r3, [r7, #6] 800b696: 4613 mov r3, r2 800b698: 80bb strh r3, [r7, #4] // Проверяем, чтобы a не выходила за пределы диапазона if (a > b) a = b; 800b69a: 88fa ldrh r2, [r7, #6] 800b69c: 88bb ldrh r3, [r7, #4] 800b69e: 429a cmp r2, r3 800b6a0: d901 bls.n 800b6a6 800b6a2: 88bb ldrh r3, [r7, #4] 800b6a4: 80fb strh r3, [r7, #6] if(b==0) b = 1; 800b6a6: 88bb ldrh r3, [r7, #4] 800b6a8: 2b00 cmp r3, #0 800b6aa: d101 bne.n 800b6b0 800b6ac: 2301 movs r3, #1 800b6ae: 80bb strh r3, [r7, #4] // Вычисляем коэффициент смешивания в виде целого числа uint16_t t = (a * 255) / b; // t будет от 0 до 255 800b6b0: 88fa ldrh r2, [r7, #6] 800b6b2: 4613 mov r3, r2 800b6b4: 021b lsls r3, r3, #8 800b6b6: 1a9a subs r2, r3, r2 800b6b8: 88bb ldrh r3, [r7, #4] 800b6ba: fb92 f3f3 sdiv r3, r2, r3 800b6be: 82fb strh r3, [r7, #22] // Линейная интерполяция с использованием целых чисел result->R = (color1->R * (255 - t) + color2->R * t) / 255; 800b6c0: 68fb ldr r3, [r7, #12] 800b6c2: 781b ldrb r3, [r3, #0] 800b6c4: 461a mov r2, r3 800b6c6: 8afb ldrh r3, [r7, #22] 800b6c8: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b6cc: fb03 f202 mul.w r2, r3, r2 800b6d0: 68bb ldr r3, [r7, #8] 800b6d2: 781b ldrb r3, [r3, #0] 800b6d4: 4619 mov r1, r3 800b6d6: 8afb ldrh r3, [r7, #22] 800b6d8: fb01 f303 mul.w r3, r1, r3 800b6dc: 4413 add r3, r2 800b6de: 4a20 ldr r2, [pc, #128] @ (800b760 ) 800b6e0: fb82 1203 smull r1, r2, r2, r3 800b6e4: 441a add r2, r3 800b6e6: 11d2 asrs r2, r2, #7 800b6e8: 17db asrs r3, r3, #31 800b6ea: 1ad3 subs r3, r2, r3 800b6ec: b2da uxtb r2, r3 800b6ee: 6a3b ldr r3, [r7, #32] 800b6f0: 701a strb r2, [r3, #0] result->G = (color1->G * (255 - t) + color2->G * t) / 255; 800b6f2: 68fb ldr r3, [r7, #12] 800b6f4: 785b ldrb r3, [r3, #1] 800b6f6: 461a mov r2, r3 800b6f8: 8afb ldrh r3, [r7, #22] 800b6fa: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b6fe: fb03 f202 mul.w r2, r3, r2 800b702: 68bb ldr r3, [r7, #8] 800b704: 785b ldrb r3, [r3, #1] 800b706: 4619 mov r1, r3 800b708: 8afb ldrh r3, [r7, #22] 800b70a: fb01 f303 mul.w r3, r1, r3 800b70e: 4413 add r3, r2 800b710: 4a13 ldr r2, [pc, #76] @ (800b760 ) 800b712: fb82 1203 smull r1, r2, r2, r3 800b716: 441a add r2, r3 800b718: 11d2 asrs r2, r2, #7 800b71a: 17db asrs r3, r3, #31 800b71c: 1ad3 subs r3, r2, r3 800b71e: b2da uxtb r2, r3 800b720: 6a3b ldr r3, [r7, #32] 800b722: 705a strb r2, [r3, #1] result->B = (color1->B * (255 - t) + color2->B * t) / 255; 800b724: 68fb ldr r3, [r7, #12] 800b726: 789b ldrb r3, [r3, #2] 800b728: 461a mov r2, r3 800b72a: 8afb ldrh r3, [r7, #22] 800b72c: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b730: fb03 f202 mul.w r2, r3, r2 800b734: 68bb ldr r3, [r7, #8] 800b736: 789b ldrb r3, [r3, #2] 800b738: 4619 mov r1, r3 800b73a: 8afb ldrh r3, [r7, #22] 800b73c: fb01 f303 mul.w r3, r1, r3 800b740: 4413 add r3, r2 800b742: 4a07 ldr r2, [pc, #28] @ (800b760 ) 800b744: fb82 1203 smull r1, r2, r2, r3 800b748: 441a add r2, r3 800b74a: 11d2 asrs r2, r2, #7 800b74c: 17db asrs r3, r3, #31 800b74e: 1ad3 subs r3, r2, r3 800b750: b2da uxtb r2, r3 800b752: 6a3b ldr r3, [r7, #32] 800b754: 709a strb r2, [r3, #2] } 800b756: bf00 nop 800b758: 371c adds r7, #28 800b75a: 46bd mov sp, r7 800b75c: bc80 pop {r7} 800b75e: 4770 bx lr 800b760: 80808081 .word 0x80808081 0800b764 : void RGB_SetColor(RGB_t *color){ 800b764: b480 push {r7} 800b766: b083 sub sp, #12 800b768: af00 add r7, sp, #0 800b76a: 6078 str r0, [r7, #4] htim4.Instance->CCR2 = color->R * 100 / 255; 800b76c: 687b ldr r3, [r7, #4] 800b76e: 781b ldrb r3, [r3, #0] 800b770: 461a mov r2, r3 800b772: 2364 movs r3, #100 @ 0x64 800b774: fb02 f303 mul.w r3, r2, r3 800b778: 4a17 ldr r2, [pc, #92] @ (800b7d8 ) 800b77a: fb82 1203 smull r1, r2, r2, r3 800b77e: 441a add r2, r3 800b780: 11d2 asrs r2, r2, #7 800b782: 17db asrs r3, r3, #31 800b784: 1ad2 subs r2, r2, r3 800b786: 4b15 ldr r3, [pc, #84] @ (800b7dc ) 800b788: 681b ldr r3, [r3, #0] 800b78a: 639a str r2, [r3, #56] @ 0x38 htim4.Instance->CCR3 = color->G * 100 / 255; 800b78c: 687b ldr r3, [r7, #4] 800b78e: 785b ldrb r3, [r3, #1] 800b790: 461a mov r2, r3 800b792: 2364 movs r3, #100 @ 0x64 800b794: fb02 f303 mul.w r3, r2, r3 800b798: 4a0f ldr r2, [pc, #60] @ (800b7d8 ) 800b79a: fb82 1203 smull r1, r2, r2, r3 800b79e: 441a add r2, r3 800b7a0: 11d2 asrs r2, r2, #7 800b7a2: 17db asrs r3, r3, #31 800b7a4: 1ad2 subs r2, r2, r3 800b7a6: 4b0d ldr r3, [pc, #52] @ (800b7dc ) 800b7a8: 681b ldr r3, [r3, #0] 800b7aa: 63da str r2, [r3, #60] @ 0x3c htim4.Instance->CCR4 = color->B * 100 / 255; 800b7ac: 687b ldr r3, [r7, #4] 800b7ae: 789b ldrb r3, [r3, #2] 800b7b0: 461a mov r2, r3 800b7b2: 2364 movs r3, #100 @ 0x64 800b7b4: fb02 f303 mul.w r3, r2, r3 800b7b8: 4a07 ldr r2, [pc, #28] @ (800b7d8 ) 800b7ba: fb82 1203 smull r1, r2, r2, r3 800b7be: 441a add r2, r3 800b7c0: 11d2 asrs r2, r2, #7 800b7c2: 17db asrs r3, r3, #31 800b7c4: 1ad2 subs r2, r2, r3 800b7c6: 4b05 ldr r3, [pc, #20] @ (800b7dc ) 800b7c8: 681b ldr r3, [r3, #0] 800b7ca: 641a str r2, [r3, #64] @ 0x40 } 800b7cc: bf00 nop 800b7ce: 370c adds r7, #12 800b7d0: 46bd mov sp, r7 800b7d2: bc80 pop {r7} 800b7d4: 4770 bx lr 800b7d6: bf00 nop 800b7d8: 80808081 .word 0x80808081 800b7dc: 2000109c .word 0x2000109c 0800b7e0 : void LED_SetColor(RGB_Cycle_t *color){ 800b7e0: b480 push {r7} 800b7e2: b083 sub sp, #12 800b7e4: af00 add r7, sp, #0 800b7e6: 6078 str r0, [r7, #4] memcpy(&LED_Cycle, color, sizeof(RGB_Cycle_t)); 800b7e8: 4b05 ldr r3, [pc, #20] @ (800b800 ) 800b7ea: 687a ldr r2, [r7, #4] 800b7ec: 6810 ldr r0, [r2, #0] 800b7ee: 6851 ldr r1, [r2, #4] 800b7f0: c303 stmia r3!, {r0, r1} 800b7f2: 8912 ldrh r2, [r2, #8] 800b7f4: 801a strh r2, [r3, #0] } 800b7f6: bf00 nop 800b7f8: 370c adds r7, #12 800b7fa: 46bd mov sp, r7 800b7fc: bc80 pop {r7} 800b7fe: 4770 bx lr 800b800: 20000908 .word 0x20000908 0800b804 : void LED_Init(){ 800b804: b580 push {r7, lr} 800b806: b082 sub sp, #8 800b808: af00 add r7, sp, #0 RGB_t color = {.R=0, .G=0, .B=0}; 800b80a: 2300 movs r3, #0 800b80c: 713b strb r3, [r7, #4] 800b80e: 2300 movs r3, #0 800b810: 717b strb r3, [r7, #5] 800b812: 2300 movs r3, #0 800b814: 71bb strb r3, [r7, #6] HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_2); 800b816: 2104 movs r1, #4 800b818: 4809 ldr r0, [pc, #36] @ (800b840 ) 800b81a: f005 fdc3 bl 80113a4 HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); 800b81e: 2108 movs r1, #8 800b820: 4807 ldr r0, [pc, #28] @ (800b840 ) 800b822: f005 fdbf bl 80113a4 HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_4); 800b826: 210c movs r1, #12 800b828: 4805 ldr r0, [pc, #20] @ (800b840 ) 800b82a: f005 fdbb bl 80113a4 RGB_SetColor(&color); 800b82e: 1d3b adds r3, r7, #4 800b830: 4618 mov r0, r3 800b832: f7ff ff97 bl 800b764 } 800b836: bf00 nop 800b838: 3708 adds r7, #8 800b83a: 46bd mov sp, r7 800b83c: bd80 pop {r7, pc} 800b83e: bf00 nop 800b840: 2000109c .word 0x2000109c 0800b844 : // } // } // } // } void LED_Task(){ 800b844: b580 push {r7, lr} 800b846: b082 sub sp, #8 800b848: af02 add r7, sp, #8 static uint32_t led_tick; if((HAL_GetTick() - led_tick) > 20){ 800b84a: f002 fa17 bl 800dc7c 800b84e: 4602 mov r2, r0 800b850: 4b46 ldr r3, [pc, #280] @ (800b96c ) 800b852: 681b ldr r3, [r3, #0] 800b854: 1ad3 subs r3, r2, r3 800b856: 2b14 cmp r3, #20 800b858: f240 8085 bls.w 800b966 led_tick = HAL_GetTick(); 800b85c: f002 fa0e bl 800dc7c 800b860: 4603 mov r3, r0 800b862: 4a42 ldr r2, [pc, #264] @ (800b96c ) 800b864: 6013 str r3, [r2, #0] LED_State.tick++; 800b866: 4b42 ldr r3, [pc, #264] @ (800b970 ) 800b868: 885b ldrh r3, [r3, #2] 800b86a: 3301 adds r3, #1 800b86c: b29a uxth r2, r3 800b86e: 4b40 ldr r3, [pc, #256] @ (800b970 ) 800b870: 805a strh r2, [r3, #2] // LED_PhaseSync(led_n); switch(LED_State.state){ 800b872: 4b3f ldr r3, [pc, #252] @ (800b970 ) 800b874: 781b ldrb r3, [r3, #0] 800b876: 2b03 cmp r3, #3 800b878: d867 bhi.n 800b94a 800b87a: a201 add r2, pc, #4 @ (adr r2, 800b880 ) 800b87c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b880: 0800b891 .word 0x0800b891 800b884: 0800b8c3 .word 0x0800b8c3 800b888: 0800b8ef .word 0x0800b8ef 800b88c: 0800b921 .word 0x0800b921 case LED_RISING: interpolateColors(&LED_Cycle.Color2, &LED_Cycle.Color1, LED_State.tick, LED_Cycle.Tr, &LED_State.color); 800b890: 4b37 ldr r3, [pc, #220] @ (800b970 ) 800b892: 885a ldrh r2, [r3, #2] 800b894: 4b37 ldr r3, [pc, #220] @ (800b974 ) 800b896: 78db ldrb r3, [r3, #3] 800b898: 4619 mov r1, r3 800b89a: 4b37 ldr r3, [pc, #220] @ (800b978 ) 800b89c: 9300 str r3, [sp, #0] 800b89e: 460b mov r3, r1 800b8a0: 4934 ldr r1, [pc, #208] @ (800b974 ) 800b8a2: 4836 ldr r0, [pc, #216] @ (800b97c ) 800b8a4: f7ff feee bl 800b684 if(LED_State.tick>LED_Cycle.Tr){ 800b8a8: 4b31 ldr r3, [pc, #196] @ (800b970 ) 800b8aa: 885b ldrh r3, [r3, #2] 800b8ac: 4a31 ldr r2, [pc, #196] @ (800b974 ) 800b8ae: 78d2 ldrb r2, [r2, #3] 800b8b0: 4293 cmp r3, r2 800b8b2: d94e bls.n 800b952 LED_State.state = LED_HIGH; 800b8b4: 4b2e ldr r3, [pc, #184] @ (800b970 ) 800b8b6: 2201 movs r2, #1 800b8b8: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b8ba: 4b2d ldr r3, [pc, #180] @ (800b970 ) 800b8bc: 2200 movs r2, #0 800b8be: 805a strh r2, [r3, #2] } break; 800b8c0: e047 b.n 800b952 case LED_HIGH: memcpy(&LED_State.color, &LED_Cycle.Color1, sizeof(RGB_t)); 800b8c2: 4b2b ldr r3, [pc, #172] @ (800b970 ) 800b8c4: 4a2b ldr r2, [pc, #172] @ (800b974 ) 800b8c6: 3304 adds r3, #4 800b8c8: 6812 ldr r2, [r2, #0] 800b8ca: 4611 mov r1, r2 800b8cc: 8019 strh r1, [r3, #0] 800b8ce: 3302 adds r3, #2 800b8d0: 0c12 lsrs r2, r2, #16 800b8d2: 701a strb r2, [r3, #0] if(LED_State.tick>LED_Cycle.Th){ 800b8d4: 4b26 ldr r3, [pc, #152] @ (800b970 ) 800b8d6: 885b ldrh r3, [r3, #2] 800b8d8: 4a26 ldr r2, [pc, #152] @ (800b974 ) 800b8da: 7912 ldrb r2, [r2, #4] 800b8dc: 4293 cmp r3, r2 800b8de: d93a bls.n 800b956 LED_State.state = LED_FALLING; 800b8e0: 4b23 ldr r3, [pc, #140] @ (800b970 ) 800b8e2: 2202 movs r2, #2 800b8e4: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b8e6: 4b22 ldr r3, [pc, #136] @ (800b970 ) 800b8e8: 2200 movs r2, #0 800b8ea: 805a strh r2, [r3, #2] } break; 800b8ec: e033 b.n 800b956 case LED_FALLING: interpolateColors(&LED_Cycle.Color1, &LED_Cycle.Color2, LED_State.tick, LED_Cycle.Tf, &LED_State.color); 800b8ee: 4b20 ldr r3, [pc, #128] @ (800b970 ) 800b8f0: 885a ldrh r2, [r3, #2] 800b8f2: 4b20 ldr r3, [pc, #128] @ (800b974 ) 800b8f4: 795b ldrb r3, [r3, #5] 800b8f6: 4619 mov r1, r3 800b8f8: 4b1f ldr r3, [pc, #124] @ (800b978 ) 800b8fa: 9300 str r3, [sp, #0] 800b8fc: 460b mov r3, r1 800b8fe: 491f ldr r1, [pc, #124] @ (800b97c ) 800b900: 481c ldr r0, [pc, #112] @ (800b974 ) 800b902: f7ff febf bl 800b684 if(LED_State.tick>LED_Cycle.Tf){ 800b906: 4b1a ldr r3, [pc, #104] @ (800b970 ) 800b908: 885b ldrh r3, [r3, #2] 800b90a: 4a1a ldr r2, [pc, #104] @ (800b974 ) 800b90c: 7952 ldrb r2, [r2, #5] 800b90e: 4293 cmp r3, r2 800b910: d923 bls.n 800b95a LED_State.state = LED_LOW; 800b912: 4b17 ldr r3, [pc, #92] @ (800b970 ) 800b914: 2203 movs r2, #3 800b916: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b918: 4b15 ldr r3, [pc, #84] @ (800b970 ) 800b91a: 2200 movs r2, #0 800b91c: 805a strh r2, [r3, #2] } break; 800b91e: e01c b.n 800b95a case LED_LOW: memcpy(&LED_State.color, &LED_Cycle.Color2, sizeof(RGB_t)); 800b920: 4b13 ldr r3, [pc, #76] @ (800b970 ) 800b922: 4a14 ldr r2, [pc, #80] @ (800b974 ) 800b924: 3304 adds r3, #4 800b926: 3207 adds r2, #7 800b928: 8811 ldrh r1, [r2, #0] 800b92a: 7892 ldrb r2, [r2, #2] 800b92c: 8019 strh r1, [r3, #0] 800b92e: 709a strb r2, [r3, #2] if(LED_State.tick>LED_Cycle.Tl){ 800b930: 4b0f ldr r3, [pc, #60] @ (800b970 ) 800b932: 885b ldrh r3, [r3, #2] 800b934: 4a0f ldr r2, [pc, #60] @ (800b974 ) 800b936: 7992 ldrb r2, [r2, #6] 800b938: 4293 cmp r3, r2 800b93a: d910 bls.n 800b95e LED_State.state = LED_RISING; 800b93c: 4b0c ldr r3, [pc, #48] @ (800b970 ) 800b93e: 2200 movs r2, #0 800b940: 701a strb r2, [r3, #0] LED_State.tick = 0; 800b942: 4b0b ldr r3, [pc, #44] @ (800b970 ) 800b944: 2200 movs r2, #0 800b946: 805a strh r2, [r3, #2] } break; 800b948: e009 b.n 800b95e default: LED_State.state = LED_RISING; 800b94a: 4b09 ldr r3, [pc, #36] @ (800b970 ) 800b94c: 2200 movs r2, #0 800b94e: 701a strb r2, [r3, #0] 800b950: e006 b.n 800b960 break; 800b952: bf00 nop 800b954: e004 b.n 800b960 break; 800b956: bf00 nop 800b958: e002 b.n 800b960 break; 800b95a: bf00 nop 800b95c: e000 b.n 800b960 break; 800b95e: bf00 nop } RGB_SetColor(&LED_State.color); 800b960: 4805 ldr r0, [pc, #20] @ (800b978 ) 800b962: f7ff feff bl 800b764 } } 800b966: bf00 nop 800b968: 46bd mov sp, r7 800b96a: bd80 pop {r7, pc} 800b96c: 20000914 .word 0x20000914 800b970: 20000900 .word 0x20000900 800b974: 20000908 .word 0x20000908 800b978: 20000904 .word 0x20000904 800b97c: 2000090f .word 0x2000090f 0800b980 : RTC_HandleTypeDef hrtc; /* RTC init function */ void MX_RTC_Init(void) { 800b980: b580 push {r7, lr} 800b982: af00 add r7, sp, #0 /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; 800b984: 4b0a ldr r3, [pc, #40] @ (800b9b0 ) 800b986: 4a0b ldr r2, [pc, #44] @ (800b9b4 ) 800b988: 601a str r2, [r3, #0] hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; 800b98a: 4b09 ldr r3, [pc, #36] @ (800b9b0 ) 800b98c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800b990: 605a str r2, [r3, #4] hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM; 800b992: 4b07 ldr r3, [pc, #28] @ (800b9b0 ) 800b994: f44f 7280 mov.w r2, #256 @ 0x100 800b998: 609a str r2, [r3, #8] if (HAL_RTC_Init(&hrtc) != HAL_OK) 800b99a: 4805 ldr r0, [pc, #20] @ (800b9b0 ) 800b99c: f005 fa04 bl 8010da8 800b9a0: 4603 mov r3, r0 800b9a2: 2b00 cmp r3, #0 800b9a4: d001 beq.n 800b9aa { Error_Handler(); 800b9a6: f7ff f835 bl 800aa14 } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } 800b9aa: bf00 nop 800b9ac: bd80 pop {r7, pc} 800b9ae: bf00 nop 800b9b0: 20000918 .word 0x20000918 800b9b4: 40002800 .word 0x40002800 0800b9b8 : void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) { 800b9b8: b580 push {r7, lr} 800b9ba: b084 sub sp, #16 800b9bc: af00 add r7, sp, #0 800b9be: 6078 str r0, [r7, #4] if(rtcHandle->Instance==RTC) 800b9c0: 687b ldr r3, [r7, #4] 800b9c2: 681b ldr r3, [r3, #0] 800b9c4: 4a0b ldr r2, [pc, #44] @ (800b9f4 ) 800b9c6: 4293 cmp r3, r2 800b9c8: d110 bne.n 800b9ec { /* USER CODE BEGIN RTC_MspInit 0 */ /* USER CODE END RTC_MspInit 0 */ HAL_PWR_EnableBkUpAccess(); 800b9ca: f004 f981 bl 800fcd0 /* Enable BKP CLK enable for backup registers */ __HAL_RCC_BKP_CLK_ENABLE(); 800b9ce: 4b0a ldr r3, [pc, #40] @ (800b9f8 ) 800b9d0: 69db ldr r3, [r3, #28] 800b9d2: 4a09 ldr r2, [pc, #36] @ (800b9f8 ) 800b9d4: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800b9d8: 61d3 str r3, [r2, #28] 800b9da: 4b07 ldr r3, [pc, #28] @ (800b9f8 ) 800b9dc: 69db ldr r3, [r3, #28] 800b9de: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800b9e2: 60fb str r3, [r7, #12] 800b9e4: 68fb ldr r3, [r7, #12] /* RTC clock enable */ __HAL_RCC_RTC_ENABLE(); 800b9e6: 4b05 ldr r3, [pc, #20] @ (800b9fc ) 800b9e8: 2201 movs r2, #1 800b9ea: 601a str r2, [r3, #0] /* USER CODE BEGIN RTC_MspInit 1 */ /* USER CODE END RTC_MspInit 1 */ } } 800b9ec: bf00 nop 800b9ee: 3710 adds r7, #16 800b9f0: 46bd mov sp, r7 800b9f2: bd80 pop {r7, pc} 800b9f4: 40002800 .word 0x40002800 800b9f8: 40021000 .word 0x40021000 800b9fc: 4242043c .word 0x4242043c 0800ba00 <__NVIC_SystemReset>: { 800ba00: b480 push {r7} 800ba02: af00 add r7, sp, #0 __ASM volatile ("dsb 0xF":::"memory"); 800ba04: f3bf 8f4f dsb sy } 800ba08: bf00 nop (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800ba0a: 4b06 ldr r3, [pc, #24] @ (800ba24 <__NVIC_SystemReset+0x24>) 800ba0c: 68db ldr r3, [r3, #12] 800ba0e: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800ba12: 4904 ldr r1, [pc, #16] @ (800ba24 <__NVIC_SystemReset+0x24>) 800ba14: 4b04 ldr r3, [pc, #16] @ (800ba28 <__NVIC_SystemReset+0x28>) 800ba16: 4313 orrs r3, r2 800ba18: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800ba1a: f3bf 8f4f dsb sy } 800ba1e: bf00 nop __NOP(); 800ba20: bf00 nop 800ba22: e7fd b.n 800ba20 <__NVIC_SystemReset+0x20> 800ba24: e000ed00 .word 0xe000ed00 800ba28: 05fa0004 .word 0x05fa0004 0800ba2c : CONN_State_t CCS_EvseState; CCS_ConnectorState_t CCS_ConnectorState = CCS_UNKNOWN; static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len); void CCS_RxEventCallback(UART_HandleTypeDef *huart, uint16_t size) { 800ba2c: b580 push {r7, lr} 800ba2e: b082 sub sp, #8 800ba30: af00 add r7, sp, #0 800ba32: 6078 str r0, [r7, #4] 800ba34: 460b mov r3, r1 800ba36: 807b strh r3, [r7, #2] if (huart != &huart3) { 800ba38: 687b ldr r3, [r7, #4] 800ba3a: 4a0a ldr r2, [pc, #40] @ (800ba64 ) 800ba3c: 4293 cmp r3, r2 800ba3e: d10c bne.n 800ba5a return; } if (size > 0 && size <= sizeof(rx_buffer)) { 800ba40: 887b ldrh r3, [r7, #2] 800ba42: 2b00 cmp r3, #0 800ba44: d00a beq.n 800ba5c 800ba46: 887b ldrh r3, [r7, #2] 800ba48: f5b3 7f80 cmp.w r3, #256 @ 0x100 800ba4c: d806 bhi.n 800ba5c process_received_packet(rx_buffer, size); 800ba4e: 887b ldrh r3, [r7, #2] 800ba50: 4619 mov r1, r3 800ba52: 4805 ldr r0, [pc, #20] @ (800ba68 ) 800ba54: f000 fd68 bl 800c528 800ba58: e000 b.n 800ba5c return; 800ba5a: bf00 nop } } 800ba5c: 3708 adds r7, #8 800ba5e: 46bd mov sp, r7 800ba60: bd80 pop {r7, pc} 800ba62: bf00 nop 800ba64: 200011bc .word 0x200011bc 800ba68: 20000950 .word 0x20000950 0800ba6c : void CCS_RxArm(void) { 800ba6c: b580 push {r7, lr} 800ba6e: af00 add r7, sp, #0 if ((&huart3)->RxState == HAL_UART_STATE_READY) { 800ba70: 4b06 ldr r3, [pc, #24] @ (800ba8c ) 800ba72: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800ba76: b2db uxtb r3, r3 800ba78: 2b20 cmp r3, #32 800ba7a: d105 bne.n 800ba88 (void)HAL_UARTEx_ReceiveToIdle_IT(&huart3, rx_buffer, sizeof(rx_buffer)); 800ba7c: f44f 7280 mov.w r2, #256 @ 0x100 800ba80: 4903 ldr r1, [pc, #12] @ (800ba90 ) 800ba82: 4802 ldr r0, [pc, #8] @ (800ba8c ) 800ba84: f006 fc74 bl 8012370 } } 800ba88: bf00 nop 800ba8a: bd80 pop {r7, pc} 800ba8c: 200011bc .word 0x200011bc 800ba90: 20000950 .word 0x20000950 0800ba94 : void CCS_SerialLoop(void) { 800ba94: b580 push {r7, lr} 800ba96: b082 sub sp, #8 800ba98: af00 add r7, sp, #0 static uint32_t replug_watchdog1_tick = 0; static uint32_t last_state_sent = 0; static uint32_t force_unlock_tick = 0; static uint32_t stop_tick = 0; CCS_RxArm(); 800ba9a: f7ff ffe7 bl 800ba6c /* Read CP once per loop and use buffered value below. */ cp_state_buffer = CP_GetState(); 800ba9e: f7fe fb03 bl 800a0a8 800baa2: 4603 mov r3, r0 800baa4: 461a mov r2, r3 800baa6: 4ba9 ldr r3, [pc, #676] @ (800bd4c ) 800baa8: 701a strb r2, [r3, #0] if (CONN.connControl == CMD_FORCE_UNLOCK) { 800baaa: 4ba9 ldr r3, [pc, #676] @ (800bd50 ) 800baac: 781b ldrb r3, [r3, #0] 800baae: 2b03 cmp r3, #3 800bab0: d11a bne.n 800bae8 if (force_unlock_tick == 0) { 800bab2: 4ba8 ldr r3, [pc, #672] @ (800bd54 ) 800bab4: 681b ldr r3, [r3, #0] 800bab6: 2b00 cmp r3, #0 800bab8: d105 bne.n 800bac6 force_unlock_tick = HAL_GetTick(); 800baba: f002 f8df bl 800dc7c 800babe: 4603 mov r3, r0 800bac0: 4aa4 ldr r2, [pc, #656] @ (800bd54 ) 800bac2: 6013 str r3, [r2, #0] 800bac4: e013 b.n 800baee } else if ((HAL_GetTick() - force_unlock_tick) >= 10000) { 800bac6: f002 f8d9 bl 800dc7c 800baca: 4602 mov r2, r0 800bacc: 4ba1 ldr r3, [pc, #644] @ (800bd54 ) 800bace: 681b ldr r3, [r3, #0] 800bad0: 1ad3 subs r3, r2, r3 800bad2: f242 720f movw r2, #9999 @ 0x270f 800bad6: 4293 cmp r3, r2 800bad8: d909 bls.n 800baee CONN.connControl = CMD_NONE; 800bada: 4b9d ldr r3, [pc, #628] @ (800bd50 ) 800badc: 2200 movs r2, #0 800bade: 701a strb r2, [r3, #0] force_unlock_tick = 0; 800bae0: 4b9c ldr r3, [pc, #624] @ (800bd54 ) 800bae2: 2200 movs r2, #0 800bae4: 601a str r2, [r3, #0] 800bae6: e002 b.n 800baee } } else { force_unlock_tick = 0; 800bae8: 4b9a ldr r3, [pc, #616] @ (800bd54 ) 800baea: 2200 movs r2, #0 800baec: 601a str r2, [r3, #0] } if (CONN.connControl == CMD_STOP) { 800baee: 4b98 ldr r3, [pc, #608] @ (800bd50 ) 800baf0: 781b ldrb r3, [r3, #0] 800baf2: 2b01 cmp r3, #1 800baf4: d119 bne.n 800bb2a if (stop_tick == 0) { 800baf6: 4b98 ldr r3, [pc, #608] @ (800bd58 ) 800baf8: 681b ldr r3, [r3, #0] 800bafa: 2b00 cmp r3, #0 800bafc: d105 bne.n 800bb0a stop_tick = HAL_GetTick(); 800bafe: f002 f8bd bl 800dc7c 800bb02: 4603 mov r3, r0 800bb04: 4a94 ldr r2, [pc, #592] @ (800bd58 ) 800bb06: 6013 str r3, [r2, #0] 800bb08: e012 b.n 800bb30 } else if ((HAL_GetTick() - stop_tick) >= 1000) { 800bb0a: f002 f8b7 bl 800dc7c 800bb0e: 4602 mov r2, r0 800bb10: 4b91 ldr r3, [pc, #580] @ (800bd58 ) 800bb12: 681b ldr r3, [r3, #0] 800bb14: 1ad3 subs r3, r2, r3 800bb16: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bb1a: d309 bcc.n 800bb30 CONN.connControl = CMD_NONE; 800bb1c: 4b8c ldr r3, [pc, #560] @ (800bd50 ) 800bb1e: 2200 movs r2, #0 800bb20: 701a strb r2, [r3, #0] stop_tick = 0; 800bb22: 4b8d ldr r3, [pc, #564] @ (800bd58 ) 800bb24: 2200 movs r2, #0 800bb26: 601a str r2, [r3, #0] 800bb28: e002 b.n 800bb30 } } else { stop_tick = 0; 800bb2a: 4b8b ldr r3, [pc, #556] @ (800bd58 ) 800bb2c: 2200 movs r2, #0 800bb2e: 601a str r2, [r3, #0] } if (CONN.connControl != CMD_NONE) { 800bb30: 4b87 ldr r3, [pc, #540] @ (800bd50 ) 800bb32: 781b ldrb r3, [r3, #0] 800bb34: 2b00 cmp r3, #0 800bb36: d003 beq.n 800bb40 last_cmd = CONN.connControl; 800bb38: 4b85 ldr r3, [pc, #532] @ (800bd50 ) 800bb3a: 781a ldrb r2, [r3, #0] 800bb3c: 4b87 ldr r3, [pc, #540] @ (800bd5c ) 800bb3e: 701a strb r2, [r3, #0] } if((HAL_GetTick() - last_cmd_sent) > CMD_INTERVAL){ 800bb40: f002 f89c bl 800dc7c 800bb44: 4602 mov r2, r0 800bb46: 4b86 ldr r3, [pc, #536] @ (800bd60 ) 800bb48: 681b ldr r3, [r3, #0] 800bb4a: 1ad3 subs r3, r2, r3 800bb4c: 2b0a cmp r3, #10 800bb4e: d95e bls.n 800bc0e if ((HAL_GetTick() - last_state_sent) >= 200) { 800bb50: f002 f894 bl 800dc7c 800bb54: 4602 mov r2, r0 800bb56: 4b83 ldr r3, [pc, #524] @ (800bd64 ) 800bb58: 681b ldr r3, [r3, #0] 800bb5a: 1ad3 subs r3, r2, r3 800bb5c: 2bc7 cmp r3, #199 @ 0xc7 800bb5e: d906 bls.n 800bb6e send_state(); 800bb60: f000 fb34 bl 800c1cc last_state_sent = HAL_GetTick(); 800bb64: f002 f88a bl 800dc7c 800bb68: 4603 mov r3, r0 800bb6a: 4a7e ldr r2, [pc, #504] @ (800bd64 ) 800bb6c: 6013 str r3, [r2, #0] } if (ESTOP) { 800bb6e: 4b7e ldr r3, [pc, #504] @ (800bd68 ) 800bb70: 781b ldrb r3, [r3, #0] 800bb72: 2b00 cmp r3, #0 800bb74: d008 beq.n 800bb88 log_printf(LOG_ERR, "ESTOP triggered\n"); 800bb76: 497d ldr r1, [pc, #500] @ (800bd6c ) 800bb78: 2004 movs r0, #4 800bb7a: f7fe fc21 bl 800a3c0 CCS_SendEmergencyStop(); 800bb7e: f000 fac6 bl 800c10e ESTOP = 0; 800bb82: 4b79 ldr r3, [pc, #484] @ (800bd68 ) 800bb84: 2200 movs r2, #0 800bb86: 701a strb r2, [r3, #0] } if (((CONN.connControl == CMD_STOP) || 800bb88: 4b71 ldr r3, [pc, #452] @ (800bd50 ) 800bb8a: 781b ldrb r3, [r3, #0] 800bb8c: 2b01 cmp r3, #1 800bb8e: d007 beq.n 800bba0 (CONN.connControl == CMD_FORCE_UNLOCK) || 800bb90: 4b6f ldr r3, [pc, #444] @ (800bd50 ) 800bb92: 781b ldrb r3, [r3, #0] if (((CONN.connControl == CMD_STOP) || 800bb94: 2b03 cmp r3, #3 800bb96: d003 beq.n 800bba0 (CONN.chargingError != CONN_NO_ERROR)) && 800bb98: 4b6d ldr r3, [pc, #436] @ (800bd50 ) 800bb9a: 7f5b ldrb r3, [r3, #29] (CONN.connControl == CMD_FORCE_UNLOCK) || 800bb9c: 2b00 cmp r3, #0 800bb9e: d01a beq.n 800bbd6 ((HAL_GetTick() - last_stop_sent) > 1000)) { 800bba0: f002 f86c bl 800dc7c 800bba4: 4602 mov r2, r0 800bba6: 4b72 ldr r3, [pc, #456] @ (800bd70 ) 800bba8: 681b ldr r3, [r3, #0] 800bbaa: 1ad3 subs r3, r2, r3 (CONN.chargingError != CONN_NO_ERROR)) && 800bbac: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bbb0: d911 bls.n 800bbd6 last_stop_sent = HAL_GetTick(); 800bbb2: f002 f863 bl 800dc7c 800bbb6: 4603 mov r3, r0 800bbb8: 4a6d ldr r2, [pc, #436] @ (800bd70 ) 800bbba: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "Stopping charging...\n"); 800bbbc: 496d ldr r1, [pc, #436] @ (800bd74 ) 800bbbe: 2005 movs r0, #5 800bbc0: f7fe fbfe bl 800a3c0 if (CONN.connControl == CMD_FORCE_UNLOCK) { 800bbc4: 4b62 ldr r3, [pc, #392] @ (800bd50 ) 800bbc6: 781b ldrb r3, [r3, #0] 800bbc8: 2b03 cmp r3, #3 800bbca: d102 bne.n 800bbd2 CP_SetDuty(100); 800bbcc: 2064 movs r0, #100 @ 0x64 800bbce: f7fe fa39 bl 800a044 } CCS_SendEmergencyStop(); 800bbd2: f000 fa9c bl 800c10e } if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800bbd6: 4b68 ldr r3, [pc, #416] @ (800bd78 ) 800bbd8: 781b ldrb r3, [r3, #0] 800bbda: 2b0c cmp r3, #12 800bbdc: d003 beq.n 800bbe6 800bbde: 4b66 ldr r3, [pc, #408] @ (800bd78 ) 800bbe0: 781b ldrb r3, [r3, #0] 800bbe2: 2b0b cmp r3, #11 800bbe4: d113 bne.n 800bc0e ((HAL_GetTick() - last_stop_sent) > 1000)) { 800bbe6: f002 f849 bl 800dc7c 800bbea: 4602 mov r2, r0 800bbec: 4b60 ldr r3, [pc, #384] @ (800bd70 ) 800bbee: 681b ldr r3, [r3, #0] 800bbf0: 1ad3 subs r3, r2, r3 if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800bbf2: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bbf6: d90a bls.n 800bc0e last_stop_sent = HAL_GetTick(); 800bbf8: f002 f840 bl 800dc7c 800bbfc: 4603 mov r3, r0 800bbfe: 4a5c ldr r2, [pc, #368] @ (800bd70 ) 800bc00: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "FinishedEV, stopping...\n"); 800bc02: 495e ldr r1, [pc, #376] @ (800bd7c ) 800bc04: 2005 movs r0, #5 800bc06: f7fe fbdb bl 800a3c0 CCS_SendEmergencyStop(); 800bc0a: f000 fa80 bl 800c10e } (void)replug_watchdog_tick; (void)replug_watchdog1_tick; uint8_t host_timed_out = (last_host_seen > 0 && (HAL_GetTick() - last_host_seen) > 5000u); 800bc0e: 4b5c ldr r3, [pc, #368] @ (800bd80 ) 800bc10: 681b ldr r3, [r3, #0] 800bc12: 2b00 cmp r3, #0 800bc14: d00b beq.n 800bc2e 800bc16: f002 f831 bl 800dc7c 800bc1a: 4602 mov r2, r0 800bc1c: 4b58 ldr r3, [pc, #352] @ (800bd80 ) 800bc1e: 681b ldr r3, [r3, #0] 800bc20: 1ad3 subs r3, r2, r3 800bc22: f241 3288 movw r2, #5000 @ 0x1388 800bc26: 4293 cmp r3, r2 800bc28: d901 bls.n 800bc2e 800bc2a: 2301 movs r3, #1 800bc2c: e000 b.n 800bc30 800bc2e: 2300 movs r3, #0 800bc30: 71fb strb r3, [r7, #7] uint8_t has_charging_error = 0;//(CONN.chargingError != CONN_NO_ERROR); 800bc32: 2300 movs r3, #0 800bc34: 71bb strb r3, [r7, #6] switch(CCS_ConnectorState){ 800bc36: 4b53 ldr r3, [pc, #332] @ (800bd84 ) 800bc38: 781b ldrb r3, [r3, #0] 800bc3a: 2b05 cmp r3, #5 800bc3c: f200 810e bhi.w 800be5c 800bc40: a201 add r2, pc, #4 @ (adr r2, 800bc48 ) 800bc42: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800bc46: bf00 nop 800bc48: 0800bc61 .word 0x0800bc61 800bc4c: 0800bc89 .word 0x0800bc89 800bc50: 0800bcb1 .word 0x0800bcb1 800bc54: 0800bcf5 .word 0x0800bcf5 800bc58: 0800bd33 .word 0x0800bd33 800bc5c: 0800bdd1 .word 0x0800bdd1 case CCS_UNKNOWN: RELAY_Write(RELAY_CP, 0); 800bc60: 2100 movs r1, #0 800bc62: 2005 movs r0, #5 800bc64: f7fd fcf2 bl 800964c CONN_SetState(Unknown); 800bc68: 2000 movs r0, #0 800bc6a: f7fe f8d1 bl 8009e10 if (config_initialized && !host_timed_out) { 800bc6e: 4b46 ldr r3, [pc, #280] @ (800bd88 ) 800bc70: 781b ldrb r3, [r3, #0] 800bc72: 2b00 cmp r3, #0 800bc74: f000 80e7 beq.w 800be46 800bc78: 79fb ldrb r3, [r7, #7] 800bc7a: 2b00 cmp r3, #0 800bc7c: f040 80e3 bne.w 800be46 CCS_ConnectorState = CCS_UNPLUGGED; 800bc80: 4b40 ldr r3, [pc, #256] @ (800bd84 ) 800bc82: 2202 movs r2, #2 800bc84: 701a strb r2, [r3, #0] } break; 800bc86: e0de b.n 800be46 case CCS_DISABLED: RELAY_Write(RELAY_CP, 0); 800bc88: 2100 movs r1, #0 800bc8a: 2005 movs r0, #5 800bc8c: f7fd fcde bl 800964c CONN_SetState(Disabled); 800bc90: 2002 movs r0, #2 800bc92: f7fe f8bd bl 8009e10 if ((CONN.chargingError == CONN_NO_ERROR) && !host_timed_out){ 800bc96: 4b2e ldr r3, [pc, #184] @ (800bd50 ) 800bc98: 7f5b ldrb r3, [r3, #29] 800bc9a: 2b00 cmp r3, #0 800bc9c: f040 80d5 bne.w 800be4a 800bca0: 79fb ldrb r3, [r7, #7] 800bca2: 2b00 cmp r3, #0 800bca4: f040 80d1 bne.w 800be4a CCS_ConnectorState = CCS_UNPLUGGED; 800bca8: 4b36 ldr r3, [pc, #216] @ (800bd84 ) 800bcaa: 2202 movs r2, #2 800bcac: 701a strb r2, [r3, #0] } break; 800bcae: e0cc b.n 800be4a case CCS_UNPLUGGED: RELAY_Write(RELAY_CP, 1); 800bcb0: 2101 movs r1, #1 800bcb2: 2005 movs r0, #5 800bcb4: f7fd fcca bl 800964c CONN_SetState(Unplugged); 800bcb8: 2001 movs r0, #1 800bcba: f7fe f8a9 bl 8009e10 if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || (cp_state_buffer == EV_STATE_C_CONN_ACTIVE)){ 800bcbe: 4b23 ldr r3, [pc, #140] @ (800bd4c ) 800bcc0: 781b ldrb r3, [r3, #0] 800bcc2: 2b01 cmp r3, #1 800bcc4: d003 beq.n 800bcce 800bcc6: 4b21 ldr r3, [pc, #132] @ (800bd4c ) 800bcc8: 781b ldrb r3, [r3, #0] 800bcca: 2b02 cmp r3, #2 800bccc: d102 bne.n 800bcd4 CCS_ConnectorState = CCS_AUTH_REQUIRED; 800bcce: 4b2d ldr r3, [pc, #180] @ (800bd84 ) 800bcd0: 2203 movs r2, #3 800bcd2: 701a strb r2, [r3, #0] } if (CONN.chargingError != CONN_NO_ERROR){ 800bcd4: 4b1e ldr r3, [pc, #120] @ (800bd50 ) 800bcd6: 7f5b ldrb r3, [r3, #29] 800bcd8: 2b00 cmp r3, #0 800bcda: f000 80b8 beq.w 800be4e log_printf(LOG_ERR, "Charging error %d, state -> disabled\n", CONN.chargingError); 800bcde: 4b1c ldr r3, [pc, #112] @ (800bd50 ) 800bce0: 7f5b ldrb r3, [r3, #29] 800bce2: 461a mov r2, r3 800bce4: 4929 ldr r1, [pc, #164] @ (800bd8c ) 800bce6: 2004 movs r0, #4 800bce8: f7fe fb6a bl 800a3c0 CCS_ConnectorState = CCS_DISABLED; 800bcec: 4b25 ldr r3, [pc, #148] @ (800bd84 ) 800bcee: 2201 movs r2, #1 800bcf0: 701a strb r2, [r3, #0] } break; 800bcf2: e0ac b.n 800be4e case CCS_AUTH_REQUIRED: RELAY_Write(RELAY_CP, 1); 800bcf4: 2101 movs r1, #1 800bcf6: 2005 movs r0, #5 800bcf8: f7fd fca8 bl 800964c CONN_SetState(AuthRequired); 800bcfc: 2004 movs r0, #4 800bcfe: f7fe f887 bl 8009e10 if(CONN.connControl == CMD_START){ 800bd02: 4b13 ldr r3, [pc, #76] @ (800bd50 ) 800bd04: 781b ldrb r3, [r3, #0] 800bd06: 2b02 cmp r3, #2 800bd08: d106 bne.n 800bd18 log_printf(LOG_INFO, "Charging permitted, start charging\n"); 800bd0a: 4921 ldr r1, [pc, #132] @ (800bd90 ) 800bd0c: 2007 movs r0, #7 800bd0e: f7fe fb57 bl 800a3c0 CCS_ConnectorState = CCS_CONNECTED; 800bd12: 4b1c ldr r3, [pc, #112] @ (800bd84 ) 800bd14: 2204 movs r2, #4 800bd16: 701a strb r2, [r3, #0] } if (cp_state_buffer == EV_STATE_A_IDLE){ 800bd18: 4b0c ldr r3, [pc, #48] @ (800bd4c ) 800bd1a: 781b ldrb r3, [r3, #0] 800bd1c: 2b00 cmp r3, #0 800bd1e: f040 8098 bne.w 800be52 log_printf(LOG_INFO, "Car unplugged\n"); 800bd22: 491c ldr r1, [pc, #112] @ (800bd94 ) 800bd24: 2007 movs r0, #7 800bd26: f7fe fb4b bl 800a3c0 CCS_ConnectorState = CCS_UNPLUGGED; 800bd2a: 4b16 ldr r3, [pc, #88] @ (800bd84 ) 800bd2c: 2202 movs r2, #2 800bd2e: 701a strb r2, [r3, #0] } break; 800bd30: e08f b.n 800be52 case CCS_CONNECTED: RELAY_Write(RELAY_CP, 1); 800bd32: 2101 movs r1, #1 800bd34: 2005 movs r0, #5 800bd36: f7fd fc89 bl 800964c if(CCS_EvseState < Preparing) { 800bd3a: 4b0f ldr r3, [pc, #60] @ (800bd78 ) 800bd3c: 781b ldrb r3, [r3, #0] 800bd3e: 2b02 cmp r3, #2 800bd40: d82a bhi.n 800bd98 CONN_SetState(Preparing); 800bd42: 2003 movs r0, #3 800bd44: f7fe f864 bl 8009e10 800bd48: e02b b.n 800bda2 800bd4a: bf00 nop 800bd4c: 20000067 .word 0x20000067 800bd50: 20000354 .word 0x20000354 800bd54: 20000bac .word 0x20000bac 800bd58: 20000bb0 .word 0x20000bb0 800bd5c: 2000094c .word 0x2000094c 800bd60: 20000944 .word 0x20000944 800bd64: 20000bb4 .word 0x20000bb4 800bd68: 20000b50 .word 0x20000b50 800bd6c: 0801615c .word 0x0801615c 800bd70: 20000948 .word 0x20000948 800bd74: 08016170 .word 0x08016170 800bd78: 20000ba8 .word 0x20000ba8 800bd7c: 08016188 .word 0x08016188 800bd80: 20000b54 .word 0x20000b54 800bd84: 20000ba9 .word 0x20000ba9 800bd88: 2000104e .word 0x2000104e 800bd8c: 080161a4 .word 0x080161a4 800bd90: 080161cc .word 0x080161cc 800bd94: 080161f0 .word 0x080161f0 } else { CONN_SetState(CCS_EvseState); 800bd98: 4b63 ldr r3, [pc, #396] @ (800bf28 ) 800bd9a: 781b ldrb r3, [r3, #0] 800bd9c: 4618 mov r0, r3 800bd9e: f7fe f837 bl 8009e10 } if (cp_state_buffer == EV_STATE_A_IDLE){ 800bda2: 4b62 ldr r3, [pc, #392] @ (800bf2c ) 800bda4: 781b ldrb r3, [r3, #0] 800bda6: 2b00 cmp r3, #0 800bda8: d106 bne.n 800bdb8 log_printf(LOG_INFO, "Car unplugged\n"); 800bdaa: 4961 ldr r1, [pc, #388] @ (800bf30 ) 800bdac: 2007 movs r0, #7 800bdae: f7fe fb07 bl 800a3c0 CCS_ConnectorState = CCS_UNPLUGGED; 800bdb2: 4b60 ldr r3, [pc, #384] @ (800bf34 ) 800bdb4: 2202 movs r2, #2 800bdb6: 701a strb r2, [r3, #0] } if(REPLUG > 0){ 800bdb8: 4b5f ldr r3, [pc, #380] @ (800bf38 ) 800bdba: 781b ldrb r3, [r3, #0] 800bdbc: 2b00 cmp r3, #0 800bdbe: d04a beq.n 800be56 log_printf(LOG_INFO, "Replugging...\n"); 800bdc0: 495e ldr r1, [pc, #376] @ (800bf3c ) 800bdc2: 2007 movs r0, #7 800bdc4: f7fe fafc bl 800a3c0 CCS_ConnectorState = CCS_REPLUGGING; 800bdc8: 4b5a ldr r3, [pc, #360] @ (800bf34 ) 800bdca: 2205 movs r2, #5 800bdcc: 701a strb r2, [r3, #0] } break; 800bdce: e042 b.n 800be56 case CCS_REPLUGGING: RELAY_Write(RELAY_CP, 0); 800bdd0: 2100 movs r1, #0 800bdd2: 2005 movs r0, #5 800bdd4: f7fd fc3a bl 800964c CONN_SetState(Replugging); 800bdd8: 200d movs r0, #13 800bdda: f7fe f819 bl 8009e10 if((HAL_GetTick() - replug_tick) > 1000){ 800bdde: f001 ff4d bl 800dc7c 800bde2: 4602 mov r2, r0 800bde4: 4b56 ldr r3, [pc, #344] @ (800bf40 ) 800bde6: 681b ldr r3, [r3, #0] 800bde8: 1ad3 subs r3, r2, r3 800bdea: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bdee: d91a bls.n 800be26 replug_tick = HAL_GetTick(); 800bdf0: f001 ff44 bl 800dc7c 800bdf4: 4603 mov r3, r0 800bdf6: 4a52 ldr r2, [pc, #328] @ (800bf40 ) 800bdf8: 6013 str r3, [r2, #0] if(REPLUG > 0){ 800bdfa: 4b4f ldr r3, [pc, #316] @ (800bf38 ) 800bdfc: 781b ldrb r3, [r3, #0] 800bdfe: 2b00 cmp r3, #0 800be00: d00a beq.n 800be18 if (REPLUG != 0xFF) REPLUG--; 800be02: 4b4d ldr r3, [pc, #308] @ (800bf38 ) 800be04: 781b ldrb r3, [r3, #0] 800be06: 2bff cmp r3, #255 @ 0xff 800be08: d00d beq.n 800be26 800be0a: 4b4b ldr r3, [pc, #300] @ (800bf38 ) 800be0c: 781b ldrb r3, [r3, #0] 800be0e: 3b01 subs r3, #1 800be10: b2da uxtb r2, r3 800be12: 4b49 ldr r3, [pc, #292] @ (800bf38 ) 800be14: 701a strb r2, [r3, #0] 800be16: e006 b.n 800be26 } else { log_printf(LOG_INFO, "Replugging finished, but car unplugged\n"); 800be18: 494a ldr r1, [pc, #296] @ (800bf44 ) 800be1a: 2007 movs r0, #7 800be1c: f7fe fad0 bl 800a3c0 CCS_ConnectorState = CCS_UNPLUGGED; 800be20: 4b44 ldr r3, [pc, #272] @ (800bf34 ) 800be22: 2202 movs r2, #2 800be24: 701a strb r2, [r3, #0] } } if(REPLUG == 0){ 800be26: 4b44 ldr r3, [pc, #272] @ (800bf38 ) 800be28: 781b ldrb r3, [r3, #0] 800be2a: 2b00 cmp r3, #0 800be2c: d115 bne.n 800be5a if(cp_state_buffer == EV_STATE_B_CONN_PREP){ 800be2e: 4b3f ldr r3, [pc, #252] @ (800bf2c ) 800be30: 781b ldrb r3, [r3, #0] 800be32: 2b01 cmp r3, #1 800be34: d111 bne.n 800be5a log_printf(LOG_INFO, "Replugging finished, car plugged, state -> auth required\n"); 800be36: 4944 ldr r1, [pc, #272] @ (800bf48 ) 800be38: 2007 movs r0, #7 800be3a: f7fe fac1 bl 800a3c0 CCS_ConnectorState = CCS_AUTH_REQUIRED; 800be3e: 4b3d ldr r3, [pc, #244] @ (800bf34 ) 800be40: 2203 movs r2, #3 800be42: 701a strb r2, [r3, #0] } } break; 800be44: e009 b.n 800be5a break; 800be46: bf00 nop 800be48: e008 b.n 800be5c break; 800be4a: bf00 nop 800be4c: e006 b.n 800be5c break; 800be4e: bf00 nop 800be50: e004 b.n 800be5c break; 800be52: bf00 nop 800be54: e002 b.n 800be5c break; 800be56: bf00 nop 800be58: e000 b.n 800be5c break; 800be5a: bf00 nop } if (has_charging_error && 800be5c: 79bb ldrb r3, [r7, #6] 800be5e: 2b00 cmp r3, #0 800be60: d011 beq.n 800be86 CCS_ConnectorState != CCS_DISABLED && 800be62: 4b34 ldr r3, [pc, #208] @ (800bf34 ) 800be64: 781b ldrb r3, [r3, #0] if (has_charging_error && 800be66: 2b01 cmp r3, #1 800be68: d00d beq.n 800be86 CCS_ConnectorState != CCS_UNKNOWN) { 800be6a: 4b32 ldr r3, [pc, #200] @ (800bf34 ) 800be6c: 781b ldrb r3, [r3, #0] CCS_ConnectorState != CCS_DISABLED && 800be6e: 2b00 cmp r3, #0 800be70: d009 beq.n 800be86 log_printf(LOG_ERR, "Charging error %d, state -> disabled\n", CONN.chargingError); 800be72: 4b36 ldr r3, [pc, #216] @ (800bf4c ) 800be74: 7f5b ldrb r3, [r3, #29] 800be76: 461a mov r2, r3 800be78: 4935 ldr r1, [pc, #212] @ (800bf50 ) 800be7a: 2004 movs r0, #4 800be7c: f7fe faa0 bl 800a3c0 CCS_ConnectorState = CCS_DISABLED; 800be80: 4b2c ldr r3, [pc, #176] @ (800bf34 ) 800be82: 2201 movs r2, #1 800be84: 701a strb r2, [r3, #0] } if (host_timed_out) { 800be86: 79fb ldrb r3, [r7, #7] 800be88: 2b00 cmp r3, #0 800be8a: d018 beq.n 800bebe CONN.EnableOutput = 0; 800be8c: 4b2f ldr r3, [pc, #188] @ (800bf4c ) 800be8e: 2200 movs r2, #0 800be90: 75da strb r2, [r3, #23] CCS_EvseState = Unknown; 800be92: 4b25 ldr r3, [pc, #148] @ (800bf28 ) 800be94: 2200 movs r2, #0 800be96: 701a strb r2, [r3, #0] CP_SetDuty(100); 800be98: 2064 movs r0, #100 @ 0x64 800be9a: f7fe f8d3 bl 800a044 if (CCS_ConnectorState != CCS_DISABLED && CCS_ConnectorState != CCS_UNKNOWN) { 800be9e: 4b25 ldr r3, [pc, #148] @ (800bf34 ) 800bea0: 781b ldrb r3, [r3, #0] 800bea2: 2b01 cmp r3, #1 800bea4: d028 beq.n 800bef8 800bea6: 4b23 ldr r3, [pc, #140] @ (800bf34 ) 800bea8: 781b ldrb r3, [r3, #0] 800beaa: 2b00 cmp r3, #0 800beac: d024 beq.n 800bef8 log_printf(LOG_ERR, "Everest timeout\n"); 800beae: 4929 ldr r1, [pc, #164] @ (800bf54 ) 800beb0: 2004 movs r0, #4 800beb2: f7fe fa85 bl 800a3c0 CCS_ConnectorState = CCS_DISABLED; 800beb6: 4b1f ldr r3, [pc, #124] @ (800bf34 ) 800beb8: 2201 movs r2, #1 800beba: 701a strb r2, [r3, #0] 800bebc: e01c b.n 800bef8 } } else { if (last_cmd == CMD_STOP) { 800bebe: 4b26 ldr r3, [pc, #152] @ (800bf58 ) 800bec0: 781b ldrb r3, [r3, #0] 800bec2: 2b01 cmp r3, #1 800bec4: d103 bne.n 800bece CONN.EnableOutput = 0; 800bec6: 4b21 ldr r3, [pc, #132] @ (800bf4c ) 800bec8: 2200 movs r2, #0 800beca: 75da strb r2, [r3, #23] 800becc: e014 b.n 800bef8 } else { CONN.EnableOutput = ev_enable_output ? 1 : 0; 800bece: 4b23 ldr r3, [pc, #140] @ (800bf5c ) 800bed0: 781b ldrb r3, [r3, #0] 800bed2: 2b00 cmp r3, #0 800bed4: bf14 ite ne 800bed6: 2301 movne r3, #1 800bed8: 2300 moveq r3, #0 800beda: b2db uxtb r3, r3 800bedc: 461a mov r2, r3 800bede: 4b1b ldr r3, [pc, #108] @ (800bf4c ) 800bee0: 75da strb r2, [r3, #23] if((CONN.EnableOutput == 0) && (CONN.connState == Preparing)){ 800bee2: 4b1a ldr r3, [pc, #104] @ (800bf4c ) 800bee4: 7ddb ldrb r3, [r3, #23] 800bee6: 2b00 cmp r3, #0 800bee8: d106 bne.n 800bef8 800beea: 4b18 ldr r3, [pc, #96] @ (800bf4c ) 800beec: 785b ldrb r3, [r3, #1] 800beee: 2b03 cmp r3, #3 800bef0: d102 bne.n 800bef8 CONN.EnableOutput = 0; 800bef2: 4b16 ldr r3, [pc, #88] @ (800bf4c ) 800bef4: 2200 movs r2, #0 800bef6: 75da strb r2, [r3, #23] } } } if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800bef8: 4b0c ldr r3, [pc, #48] @ (800bf2c ) 800befa: 781b ldrb r3, [r3, #0] 800befc: 2b01 cmp r3, #1 800befe: d007 beq.n 800bf10 (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800bf00: 4b0a ldr r3, [pc, #40] @ (800bf2c ) 800bf02: 781b ldrb r3, [r3, #0] if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800bf04: 2b02 cmp r3, #2 800bf06: d003 beq.n 800bf10 (cp_state_buffer == EV_STATE_D_CONN_ACT_VENT)) { 800bf08: 4b08 ldr r3, [pc, #32] @ (800bf2c ) 800bf0a: 781b ldrb r3, [r3, #0] (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800bf0c: 2b03 cmp r3, #3 800bf0e: d103 bne.n 800bf18 CONN.EvConnected = 1; 800bf10: 4b0e ldr r3, [pc, #56] @ (800bf4c ) 800bf12: 2201 movs r2, #1 800bf14: 779a strb r2, [r3, #30] 800bf16: e003 b.n 800bf20 } else { CONN.EvConnected = 0; 800bf18: 4b0c ldr r3, [pc, #48] @ (800bf4c ) 800bf1a: 2200 movs r2, #0 800bf1c: 779a strb r2, [r3, #30] } } 800bf1e: bf00 nop 800bf20: bf00 nop 800bf22: 3708 adds r7, #8 800bf24: 46bd mov sp, r7 800bf26: bd80 pop {r7, pc} 800bf28: 20000ba8 .word 0x20000ba8 800bf2c: 20000067 .word 0x20000067 800bf30: 080161f0 .word 0x080161f0 800bf34: 20000ba9 .word 0x20000ba9 800bf38: 20000b51 .word 0x20000b51 800bf3c: 08016200 .word 0x08016200 800bf40: 20000bb8 .word 0x20000bb8 800bf44: 08016210 .word 0x08016210 800bf48: 08016238 .word 0x08016238 800bf4c: 20000354 .word 0x20000354 800bf50: 080161a4 .word 0x080161a4 800bf54: 08016274 .word 0x08016274 800bf58: 2000094c .word 0x2000094c 800bf5c: 2000094d .word 0x2000094d 0800bf60 : void CCS_Init(void){ 800bf60: b580 push {r7, lr} 800bf62: af00 add r7, sp, #0 CP_Init(); 800bf64: f7fe f84c bl 800a000 CP_SetDuty(100); 800bf68: 2064 movs r0, #100 @ 0x64 800bf6a: f7fe f86b bl 800a044 CCS_MaxLoad.maxVoltage = PSU_MAX_VOLTAGE; // 1000V 800bf6e: 4b0d ldr r3, [pc, #52] @ (800bfa4 ) 800bf70: f44f 727a mov.w r2, #1000 @ 0x3e8 800bf74: 801a strh r2, [r3, #0] CCS_MaxLoad.minVoltage = PSU_MIN_VOLTAGE; //150V 800bf76: 4b0b ldr r3, [pc, #44] @ (800bfa4 ) 800bf78: 2296 movs r2, #150 @ 0x96 800bf7a: 805a strh r2, [r3, #2] CCS_MaxLoad.maxCurrent = PSU_MAX_CURRENT*10; //100A 800bf7c: 4b09 ldr r3, [pc, #36] @ (800bfa4 ) 800bf7e: f240 5232 movw r2, #1330 @ 0x532 800bf82: 809a strh r2, [r3, #4] CCS_MaxLoad.minCurrent = PSU_MIN_CURRENT*10; //1A 800bf84: 4b07 ldr r3, [pc, #28] @ (800bfa4 ) 800bf86: 220a movs r2, #10 800bf88: 80da strh r2, [r3, #6] CCS_MaxLoad.maxPower = PSU_MAX_POWER; //30000W 800bf8a: 4b06 ldr r3, [pc, #24] @ (800bfa4 ) 800bf8c: f247 5230 movw r2, #30000 @ 0x7530 800bf90: 609a str r2, [r3, #8] CCS_SendResetReason(); 800bf92: f000 f8b3 bl 800c0fc log_printf(LOG_INFO, "CCS init\n"); 800bf96: 4904 ldr r1, [pc, #16] @ (800bfa8 ) 800bf98: 2007 movs r0, #7 800bf9a: f7fe fa11 bl 800a3c0 } 800bf9e: bf00 nop 800bfa0: bd80 pop {r7, pc} 800bfa2: bf00 nop 800bfa4: 2000092c .word 0x2000092c 800bfa8: 08016288 .word 0x08016288 0800bfac : static uint16_t crc16_ibm(const uint8_t* data, uint16_t length) { 800bfac: b480 push {r7} 800bfae: b085 sub sp, #20 800bfb0: af00 add r7, sp, #0 800bfb2: 6078 str r0, [r7, #4] 800bfb4: 460b mov r3, r1 800bfb6: 807b strh r3, [r7, #2] uint16_t crc = 0xFFFFu; 800bfb8: f64f 73ff movw r3, #65535 @ 0xffff 800bfbc: 81fb strh r3, [r7, #14] for (uint16_t i = 0; i < length; i++) { 800bfbe: 2300 movs r3, #0 800bfc0: 81bb strh r3, [r7, #12] 800bfc2: e022 b.n 800c00a crc ^= data[i]; 800bfc4: 89bb ldrh r3, [r7, #12] 800bfc6: 687a ldr r2, [r7, #4] 800bfc8: 4413 add r3, r2 800bfca: 781b ldrb r3, [r3, #0] 800bfcc: 461a mov r2, r3 800bfce: 89fb ldrh r3, [r7, #14] 800bfd0: 4053 eors r3, r2 800bfd2: 81fb strh r3, [r7, #14] for (uint8_t j = 0; j < 8; j++) { 800bfd4: 2300 movs r3, #0 800bfd6: 72fb strb r3, [r7, #11] 800bfd8: e011 b.n 800bffe if (crc & 1u) { 800bfda: 89fb ldrh r3, [r7, #14] 800bfdc: f003 0301 and.w r3, r3, #1 800bfe0: 2b00 cmp r3, #0 800bfe2: d006 beq.n 800bff2 crc = (crc >> 1) ^ 0xA001u; 800bfe4: 89fb ldrh r3, [r7, #14] 800bfe6: 085b lsrs r3, r3, #1 800bfe8: b29a uxth r2, r3 800bfea: 4b0d ldr r3, [pc, #52] @ (800c020 ) 800bfec: 4053 eors r3, r2 800bfee: 81fb strh r3, [r7, #14] 800bff0: e002 b.n 800bff8 } else { crc >>= 1; 800bff2: 89fb ldrh r3, [r7, #14] 800bff4: 085b lsrs r3, r3, #1 800bff6: 81fb strh r3, [r7, #14] for (uint8_t j = 0; j < 8; j++) { 800bff8: 7afb ldrb r3, [r7, #11] 800bffa: 3301 adds r3, #1 800bffc: 72fb strb r3, [r7, #11] 800bffe: 7afb ldrb r3, [r7, #11] 800c000: 2b07 cmp r3, #7 800c002: d9ea bls.n 800bfda for (uint16_t i = 0; i < length; i++) { 800c004: 89bb ldrh r3, [r7, #12] 800c006: 3301 adds r3, #1 800c008: 81bb strh r3, [r7, #12] 800c00a: 89ba ldrh r2, [r7, #12] 800c00c: 887b ldrh r3, [r7, #2] 800c00e: 429a cmp r2, r3 800c010: d3d8 bcc.n 800bfc4 } } } return crc; 800c012: 89fb ldrh r3, [r7, #14] } 800c014: 4618 mov r0, r3 800c016: 3714 adds r7, #20 800c018: 46bd mov sp, r7 800c01a: bc80 pop {r7} 800c01c: 4770 bx lr 800c01e: bf00 nop 800c020: ffffa001 .word 0xffffa001 0800c024 : static uint16_t CCS_BuildPacket(uint8_t cmd, const void* payload, uint16_t payload_len, uint8_t* out, uint16_t out_max) { 800c024: b580 push {r7, lr} 800c026: b086 sub sp, #24 800c028: af00 add r7, sp, #0 800c02a: 60b9 str r1, [r7, #8] 800c02c: 607b str r3, [r7, #4] 800c02e: 4603 mov r3, r0 800c030: 73fb strb r3, [r7, #15] 800c032: 4613 mov r3, r2 800c034: 81bb strh r3, [r7, #12] uint16_t total_len = (uint16_t)(1u + payload_len + 2u); 800c036: 89bb ldrh r3, [r7, #12] 800c038: 3303 adds r3, #3 800c03a: 82fb strh r3, [r7, #22] if (total_len > out_max) return 0; 800c03c: 8afa ldrh r2, [r7, #22] 800c03e: 8c3b ldrh r3, [r7, #32] 800c040: 429a cmp r2, r3 800c042: d901 bls.n 800c048 800c044: 2300 movs r3, #0 800c046: e029 b.n 800c09c out[0] = cmd; 800c048: 687b ldr r3, [r7, #4] 800c04a: 7bfa ldrb r2, [r7, #15] 800c04c: 701a strb r2, [r3, #0] if (payload_len && payload != NULL) { 800c04e: 89bb ldrh r3, [r7, #12] 800c050: 2b00 cmp r3, #0 800c052: d009 beq.n 800c068 800c054: 68bb ldr r3, [r7, #8] 800c056: 2b00 cmp r3, #0 800c058: d006 beq.n 800c068 memcpy(&out[1], payload, payload_len); 800c05a: 687b ldr r3, [r7, #4] 800c05c: 3301 adds r3, #1 800c05e: 89ba ldrh r2, [r7, #12] 800c060: 68b9 ldr r1, [r7, #8] 800c062: 4618 mov r0, r3 800c064: f007 fe72 bl 8013d4c } uint16_t crc = crc16_ibm(out, (uint16_t)(1u + payload_len)); 800c068: 89bb ldrh r3, [r7, #12] 800c06a: 3301 adds r3, #1 800c06c: b29b uxth r3, r3 800c06e: 4619 mov r1, r3 800c070: 6878 ldr r0, [r7, #4] 800c072: f7ff ff9b bl 800bfac 800c076: 4603 mov r3, r0 800c078: 82bb strh r3, [r7, #20] out[1u + payload_len] = (uint8_t)(crc & 0xFFu); 800c07a: 89bb ldrh r3, [r7, #12] 800c07c: 3301 adds r3, #1 800c07e: 687a ldr r2, [r7, #4] 800c080: 4413 add r3, r2 800c082: 8aba ldrh r2, [r7, #20] 800c084: b2d2 uxtb r2, r2 800c086: 701a strb r2, [r3, #0] out[1u + payload_len + 1u] = (uint8_t)((crc >> 8) & 0xFFu); 800c088: 8abb ldrh r3, [r7, #20] 800c08a: 0a1b lsrs r3, r3, #8 800c08c: b299 uxth r1, r3 800c08e: 89bb ldrh r3, [r7, #12] 800c090: 3302 adds r3, #2 800c092: 687a ldr r2, [r7, #4] 800c094: 4413 add r3, r2 800c096: b2ca uxtb r2, r1 800c098: 701a strb r2, [r3, #0] return total_len; 800c09a: 8afb ldrh r3, [r7, #22] } 800c09c: 4618 mov r0, r3 800c09e: 3718 adds r7, #24 800c0a0: 46bd mov sp, r7 800c0a2: bd80 pop {r7, pc} 0800c0a4 : static void CCS_SendPacket(uint8_t cmd, const void* payload, uint16_t payload_len) { 800c0a4: b580 push {r7, lr} 800c0a6: b086 sub sp, #24 800c0a8: af02 add r7, sp, #8 800c0aa: 4603 mov r3, r0 800c0ac: 6039 str r1, [r7, #0] 800c0ae: 71fb strb r3, [r7, #7] 800c0b0: 4613 mov r3, r2 800c0b2: 80bb strh r3, [r7, #4] uint16_t len = CCS_BuildPacket(cmd, payload, payload_len, tx_buffer, sizeof(tx_buffer)); 800c0b4: 88ba ldrh r2, [r7, #4] 800c0b6: 79f8 ldrb r0, [r7, #7] 800c0b8: f44f 7380 mov.w r3, #256 @ 0x100 800c0bc: 9300 str r3, [sp, #0] 800c0be: 4b0c ldr r3, [pc, #48] @ (800c0f0 ) 800c0c0: 6839 ldr r1, [r7, #0] 800c0c2: f7ff ffaf bl 800c024 800c0c6: 4603 mov r3, r0 800c0c8: 81fb strh r3, [r7, #14] if (len > 0) { 800c0ca: 89fb ldrh r3, [r7, #14] 800c0cc: 2b00 cmp r3, #0 800c0ce: d006 beq.n 800c0de HAL_UART_Transmit(&huart3, tx_buffer, len, 1000); 800c0d0: 89fa ldrh r2, [r7, #14] 800c0d2: f44f 737a mov.w r3, #1000 @ 0x3e8 800c0d6: 4906 ldr r1, [pc, #24] @ (800c0f0 ) 800c0d8: 4806 ldr r0, [pc, #24] @ (800c0f4 ) 800c0da: f006 f889 bl 80121f0 } last_cmd_sent = HAL_GetTick(); 800c0de: f001 fdcd bl 800dc7c 800c0e2: 4603 mov r3, r0 800c0e4: 4a04 ldr r2, [pc, #16] @ (800c0f8 ) 800c0e6: 6013 str r3, [r2, #0] } 800c0e8: bf00 nop 800c0ea: 3710 adds r7, #16 800c0ec: 46bd mov sp, r7 800c0ee: bd80 pop {r7, pc} 800c0f0: 20000a50 .word 0x20000a50 800c0f4: 200011bc .word 0x200011bc 800c0f8: 20000944 .word 0x20000944 0800c0fc : static void CCS_SendResetReason(void) { 800c0fc: b580 push {r7, lr} 800c0fe: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_RESET, NULL, 0); 800c100: 2200 movs r2, #0 800c102: 2100 movs r1, #0 800c104: 2052 movs r0, #82 @ 0x52 800c106: f7ff ffcd bl 800c0a4 } 800c10a: bf00 nop 800c10c: bd80 pop {r7, pc} 0800c10e : void CCS_SendEmergencyStop(void) { 800c10e: b580 push {r7, lr} 800c110: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_ESTOP, NULL, 0); 800c112: 2200 movs r2, #0 800c114: 2100 movs r1, #0 800c116: 2053 movs r0, #83 @ 0x53 800c118: f7ff ffc4 bl 800c0a4 } 800c11c: bf00 nop 800c11e: bd80 pop {r7, pc} 0800c120 : void CCS_SendStart(void) { CCS_SendPacket(CMD_M2E_START, NULL, 0); } static void CCS_CalculateEnergy(void) { 800c120: b580 push {r7, lr} 800c122: b082 sub sp, #8 800c124: af00 add r7, sp, #0 static uint32_t lastTick = 0; uint32_t currentTick = HAL_GetTick(); 800c126: f001 fda9 bl 800dc7c 800c12a: 6078 str r0, [r7, #4] uint32_t elapsedTimeMs = currentTick - lastTick; 800c12c: 4b1e ldr r3, [pc, #120] @ (800c1a8 ) 800c12e: 681b ldr r3, [r3, #0] 800c130: 687a ldr r2, [r7, #4] 800c132: 1ad3 subs r3, r2, r3 800c134: 603b str r3, [r7, #0] lastTick = currentTick; 800c136: 4a1c ldr r2, [pc, #112] @ (800c1a8 ) 800c138: 687b ldr r3, [r7, #4] 800c13a: 6013 str r3, [r2, #0] CCS_Power = CONN.MeasuredVoltage * CONN.MeasuredCurrent / 10; 800c13c: 4b1b ldr r3, [pc, #108] @ (800c1ac ) 800c13e: f8b3 3013 ldrh.w r3, [r3, #19] 800c142: b29b uxth r3, r3 800c144: 461a mov r2, r3 800c146: 4b19 ldr r3, [pc, #100] @ (800c1ac ) 800c148: f8b3 3015 ldrh.w r3, [r3, #21] 800c14c: b29b uxth r3, r3 800c14e: fb02 f303 mul.w r3, r2, r3 800c152: 4a17 ldr r2, [pc, #92] @ (800c1b0 ) 800c154: fb82 1203 smull r1, r2, r2, r3 800c158: 1092 asrs r2, r2, #2 800c15a: 17db asrs r3, r3, #31 800c15c: 1ad3 subs r3, r2, r3 800c15e: 461a mov r2, r3 800c160: 4b14 ldr r3, [pc, #80] @ (800c1b4 ) 800c162: 601a str r2, [r3, #0] CCS_EnergyWs += (CCS_Power * elapsedTimeMs) / 1000; 800c164: 4b13 ldr r3, [pc, #76] @ (800c1b4 ) 800c166: 681b ldr r3, [r3, #0] 800c168: 683a ldr r2, [r7, #0] 800c16a: fb02 f303 mul.w r3, r2, r3 800c16e: 4a12 ldr r2, [pc, #72] @ (800c1b8 ) 800c170: fba2 2303 umull r2, r3, r2, r3 800c174: 099a lsrs r2, r3, #6 800c176: 4b11 ldr r3, [pc, #68] @ (800c1bc ) 800c178: 681b ldr r3, [r3, #0] 800c17a: 4413 add r3, r2 800c17c: 4a0f ldr r2, [pc, #60] @ (800c1bc ) 800c17e: 6013 str r3, [r2, #0] if(CCS_EvseState == Unplugged) { 800c180: 4b0f ldr r3, [pc, #60] @ (800c1c0 ) 800c182: 781b ldrb r3, [r3, #0] 800c184: 2b01 cmp r3, #1 800c186: d102 bne.n 800c18e CCS_EnergyWs = 0; 800c188: 4b0c ldr r3, [pc, #48] @ (800c1bc ) 800c18a: 2200 movs r2, #0 800c18c: 601a str r2, [r3, #0] } CCS_Energy = CCS_EnergyWs / 3600; 800c18e: 4b0b ldr r3, [pc, #44] @ (800c1bc ) 800c190: 681b ldr r3, [r3, #0] 800c192: 4a0c ldr r2, [pc, #48] @ (800c1c4 ) 800c194: fba2 2303 umull r2, r3, r2, r3 800c198: 0adb lsrs r3, r3, #11 800c19a: 4a0b ldr r2, [pc, #44] @ (800c1c8 ) 800c19c: 6013 str r3, [r2, #0] } 800c19e: bf00 nop 800c1a0: 3708 adds r7, #8 800c1a2: 46bd mov sp, r7 800c1a4: bd80 pop {r7, pc} 800c1a6: bf00 nop 800c1a8: 20000bbc .word 0x20000bbc 800c1ac: 20000354 .word 0x20000354 800c1b0: 66666667 .word 0x66666667 800c1b4: 20000938 .word 0x20000938 800c1b8: 10624dd3 .word 0x10624dd3 800c1bc: 2000093c .word 0x2000093c 800c1c0: 20000ba8 .word 0x20000ba8 800c1c4: 91a2b3c5 .word 0x91a2b3c5 800c1c8: 20000940 .word 0x20000940 0800c1cc : static void send_state(void) { 800c1cc: b580 push {r7, lr} 800c1ce: af00 add r7, sp, #0 CCS_CalculateEnergy(); 800c1d0: f7ff ffa6 bl 800c120 CCS_State.DutyCycle = CP_GetDuty(); 800c1d4: f7fd ff5e bl 800a094 800c1d8: 4603 mov r3, r0 800c1da: 461a mov r2, r3 800c1dc: 4b2e ldr r3, [pc, #184] @ (800c298 ) 800c1de: 701a strb r2, [r3, #0] CCS_State.OutputEnabled = PSU0.CONT_enabled; 800c1e0: 4b2e ldr r3, [pc, #184] @ (800c29c ) 800c1e2: 7ada ldrb r2, [r3, #11] 800c1e4: 4b2c ldr r3, [pc, #176] @ (800c298 ) 800c1e6: 705a strb r2, [r3, #1] CCS_State.MeasuredVoltage = (uint16_t)CONN.MeasuredVoltage; 800c1e8: 4b2d ldr r3, [pc, #180] @ (800c2a0 ) 800c1ea: f8b3 3013 ldrh.w r3, [r3, #19] 800c1ee: b29a uxth r2, r3 800c1f0: 4b29 ldr r3, [pc, #164] @ (800c298 ) 800c1f2: 805a strh r2, [r3, #2] if (fake_500_voltage_mode) { 800c1f4: 4b2b ldr r3, [pc, #172] @ (800c2a4 ) 800c1f6: 781b ldrb r3, [r3, #0] 800c1f8: 2b00 cmp r3, #0 800c1fa: d003 beq.n 800c204 CCS_State.MeasuredVoltage = FAKE_EVREQ_VOLTAGE_V; 800c1fc: 4b26 ldr r3, [pc, #152] @ (800c298 ) 800c1fe: f44f 72fa mov.w r2, #500 @ 0x1f4 800c202: 805a strh r2, [r3, #2] } CCS_State.MeasuredCurrent = (uint16_t)CONN.MeasuredCurrent; 800c204: 4b26 ldr r3, [pc, #152] @ (800c2a0 ) 800c206: f8b3 3015 ldrh.w r3, [r3, #21] 800c20a: b29a uxth r2, r3 800c20c: 4b22 ldr r3, [pc, #136] @ (800c298 ) 800c20e: 809a strh r2, [r3, #4] CCS_State.Power = CCS_Power; 800c210: 4b25 ldr r3, [pc, #148] @ (800c2a8 ) 800c212: 681b ldr r3, [r3, #0] 800c214: 4a20 ldr r2, [pc, #128] @ (800c298 ) 800c216: f8c2 3006 str.w r3, [r2, #6] CCS_State.Energy = CCS_Energy; 800c21a: 4b24 ldr r3, [pc, #144] @ (800c2ac ) 800c21c: 681b ldr r3, [r3, #0] 800c21e: 4a1e ldr r2, [pc, #120] @ (800c298 ) 800c220: f8c2 300a str.w r3, [r2, #10] if(CCS_ConnectorState == CCS_CONNECTED){ 800c224: 4b22 ldr r3, [pc, #136] @ (800c2b0 ) 800c226: 781b ldrb r3, [r3, #0] 800c228: 2b04 cmp r3, #4 800c22a: d104 bne.n 800c236 CCS_State.CpState = cp_state_buffer; 800c22c: 4b21 ldr r3, [pc, #132] @ (800c2b4 ) 800c22e: 781a ldrb r2, [r3, #0] 800c230: 4b19 ldr r3, [pc, #100] @ (800c298 ) 800c232: 74da strb r2, [r3, #19] 800c234: e002 b.n 800c23c } else { CCS_State.CpState = EV_STATE_A_IDLE; 800c236: 4b18 ldr r3, [pc, #96] @ (800c298 ) 800c238: 2200 movs r2, #0 800c23a: 74da strb r2, [r3, #19] } CCS_State.MaxVoltage = CCS_MaxLoad.maxVoltage; 800c23c: 4b1e ldr r3, [pc, #120] @ (800c2b8 ) 800c23e: 881a ldrh r2, [r3, #0] 800c240: 4b15 ldr r3, [pc, #84] @ (800c298 ) 800c242: 829a strh r2, [r3, #20] CCS_State.MinVoltage = CCS_MaxLoad.minVoltage; 800c244: 4b1c ldr r3, [pc, #112] @ (800c2b8 ) 800c246: 885a ldrh r2, [r3, #2] 800c248: 4b13 ldr r3, [pc, #76] @ (800c298 ) 800c24a: 82da strh r2, [r3, #22] CCS_State.MaxCurrent = CCS_MaxLoad.maxCurrent; 800c24c: 4b1a ldr r3, [pc, #104] @ (800c2b8 ) 800c24e: 889a ldrh r2, [r3, #4] 800c250: 4b11 ldr r3, [pc, #68] @ (800c298 ) 800c252: 831a strh r2, [r3, #24] CCS_State.MinCurrent = CCS_MaxLoad.minCurrent; 800c254: 4b18 ldr r3, [pc, #96] @ (800c2b8 ) 800c256: 88da ldrh r2, [r3, #6] 800c258: 4b0f ldr r3, [pc, #60] @ (800c298 ) 800c25a: 835a strh r2, [r3, #26] CCS_State.MaxPower = CCS_MaxLoad.maxPower; 800c25c: 4b16 ldr r3, [pc, #88] @ (800c2b8 ) 800c25e: 689b ldr r3, [r3, #8] 800c260: 4a0d ldr r2, [pc, #52] @ (800c298 ) 800c262: 61d3 str r3, [r2, #28] CCS_State.IsolationValid = isolation_enable; 800c264: 4b15 ldr r3, [pc, #84] @ (800c2bc ) 800c266: 781a ldrb r2, [r3, #0] 800c268: 4b0b ldr r3, [pc, #44] @ (800c298 ) 800c26a: 749a strb r2, [r3, #18] CCS_State.IsolationResistance = 900000; 800c26c: 4a0a ldr r2, [pc, #40] @ (800c298 ) 800c26e: 2300 movs r3, #0 800c270: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800c274: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800c278: f443 433b orr.w r3, r3, #47872 @ 0xbb00 800c27c: f043 03a0 orr.w r3, r3, #160 @ 0xa0 800c280: 81d3 strh r3, [r2, #14] 800c282: 2300 movs r3, #0 800c284: f043 030d orr.w r3, r3, #13 800c288: 8213 strh r3, [r2, #16] CCS_SendPacket(CMD_M2E_STATE, &CCS_State, sizeof(CCS_State)); 800c28a: 2220 movs r2, #32 800c28c: 4902 ldr r1, [pc, #8] @ (800c298 ) 800c28e: 2050 movs r0, #80 @ 0x50 800c290: f7ff ff08 bl 800c0a4 } 800c294: bf00 nop 800c296: bd80 pop {r7, pc} 800c298: 20000b5c .word 0x20000b5c 800c29c: 200008a4 .word 0x200008a4 800c2a0: 20000354 .word 0x20000354 800c2a4: 20000b58 .word 0x20000b58 800c2a8: 20000938 .word 0x20000938 800c2ac: 20000940 .word 0x20000940 800c2b0: 20000ba9 .word 0x20000ba9 800c2b4: 20000067 .word 0x20000067 800c2b8: 2000092c .word 0x2000092c 800c2bc: 20000b53 .word 0x20000b53 0800c2c0 : static uint16_t expected_payload_len(uint8_t cmd) { 800c2c0: b480 push {r7} 800c2c2: b083 sub sp, #12 800c2c4: af00 add r7, sp, #0 800c2c6: 4603 mov r3, r0 800c2c8: 71fb strb r3, [r7, #7] switch (cmd) { 800c2ca: 79fb ldrb r3, [r7, #7] 800c2cc: 3b40 subs r3, #64 @ 0x40 800c2ce: 2b09 cmp r3, #9 800c2d0: d82a bhi.n 800c328 800c2d2: a201 add r2, pc, #4 @ (adr r2, 800c2d8 ) 800c2d4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c2d8: 0800c301 .word 0x0800c301 800c2dc: 0800c305 .word 0x0800c305 800c2e0: 0800c309 .word 0x0800c309 800c2e4: 0800c30d .word 0x0800c30d 800c2e8: 0800c311 .word 0x0800c311 800c2ec: 0800c315 .word 0x0800c315 800c2f0: 0800c319 .word 0x0800c319 800c2f4: 0800c31d .word 0x0800c31d 800c2f8: 0800c321 .word 0x0800c321 800c2fc: 0800c325 .word 0x0800c325 case CMD_E2M_PWM_DUTY: return sizeof(e2m_pwm_duty_t); 800c300: 2301 movs r3, #1 800c302: e013 b.n 800c32c case CMD_E2M_ENABLE_OUTPUT: return sizeof(e2m_enable_output_t); 800c304: 2301 movs r3, #1 800c306: e011 b.n 800c32c case CMD_E2M_RESET: return sizeof(e2m_reset_t); 800c308: 2301 movs r3, #1 800c30a: e00f b.n 800c32c case CMD_E2M_ENABLE: return sizeof(e2m_enable_t); 800c30c: 2301 movs r3, #1 800c30e: e00d b.n 800c32c case CMD_E2M_REPLUG: return sizeof(e2m_replug_t); 800c310: 2301 movs r3, #1 800c312: e00b b.n 800c32c case CMD_E2M_SET_OUTPUT_VOLTAGE: return sizeof(e2m_set_output_t); 800c314: 2304 movs r3, #4 800c316: e009 b.n 800c32c case CMD_E2M_ISOLATION_CONTROL: return sizeof(e2m_isolation_control_t); 800c318: 2301 movs r3, #1 800c31a: e007 b.n 800c32c case CMD_E2M_EV_INFO: return sizeof(CCS_EvInfo_t); 800c31c: 232c movs r3, #44 @ 0x2c 800c31e: e005 b.n 800c32c case CMD_E2M_EVSE_STATE: return sizeof(CONN_State_t); 800c320: 2301 movs r3, #1 800c322: e003 b.n 800c32c case CMD_E2M_KEEP_ALIVE: return 0; 800c324: 2300 movs r3, #0 800c326: e001 b.n 800c32c default: return 0xFFFFu; 800c328: f64f 73ff movw r3, #65535 @ 0xffff } } 800c32c: 4618 mov r0, r3 800c32e: 370c adds r7, #12 800c330: 46bd mov sp, r7 800c332: bc80 pop {r7} 800c334: 4770 bx lr 800c336: bf00 nop 0800c338 : static void apply_command(uint8_t cmd, const uint8_t* payload, uint16_t payload_len) { 800c338: b5f0 push {r4, r5, r6, r7, lr} 800c33a: b08b sub sp, #44 @ 0x2c 800c33c: af00 add r7, sp, #0 800c33e: 4603 mov r3, r0 800c340: 6039 str r1, [r7, #0] 800c342: 71fb strb r3, [r7, #7] 800c344: 4613 mov r3, r2 800c346: 80bb strh r3, [r7, #4] (void)payload_len; last_host_seen = HAL_GetTick(); 800c348: f001 fc98 bl 800dc7c 800c34c: 4603 mov r3, r0 800c34e: 4a6b ldr r2, [pc, #428] @ (800c4fc ) 800c350: 6013 str r3, [r2, #0] switch (cmd) { 800c352: 79fb ldrb r3, [r7, #7] 800c354: 3b40 subs r3, #64 @ 0x40 800c356: 2b09 cmp r3, #9 800c358: f200 80c6 bhi.w 800c4e8 800c35c: a201 add r2, pc, #4 @ (adr r2, 800c364 ) 800c35e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c362: bf00 nop 800c364: 0800c38d .word 0x0800c38d 800c368: 0800c3c5 .word 0x0800c3c5 800c36c: 0800c3df .word 0x0800c3df 800c370: 0800c403 .word 0x0800c403 800c374: 0800c4d1 .word 0x0800c4d1 800c378: 0800c41d .word 0x0800c41d 800c37c: 0800c475 .word 0x0800c475 800c380: 0800c483 .word 0x0800c483 800c384: 0800c4c7 .word 0x0800c4c7 800c388: 0800c4dd .word 0x0800c4dd case CMD_E2M_PWM_DUTY: { const e2m_pwm_duty_t* p = (const e2m_pwm_duty_t*)payload; 800c38c: 683b ldr r3, [r7, #0] 800c38e: 60fb str r3, [r7, #12] uint8_t duty = p->pwm_duty_percent; 800c390: 68fb ldr r3, [r7, #12] 800c392: 781b ldrb r3, [r3, #0] 800c394: f887 3027 strb.w r3, [r7, #39] @ 0x27 if (duty > 100) duty = 100; 800c398: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 800c39c: 2b64 cmp r3, #100 @ 0x64 800c39e: d902 bls.n 800c3a6 800c3a0: 2364 movs r3, #100 @ 0x64 800c3a2: f887 3027 strb.w r3, [r7, #39] @ 0x27 pwm_duty_percent = duty; 800c3a6: 4a56 ldr r2, [pc, #344] @ (800c500 ) 800c3a8: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 800c3ac: 7013 strb r3, [r2, #0] if (CONN.connControl != CMD_FORCE_UNLOCK) { 800c3ae: 4b55 ldr r3, [pc, #340] @ (800c504 ) 800c3b0: 781b ldrb r3, [r3, #0] 800c3b2: 2b03 cmp r3, #3 800c3b4: f000 809a beq.w 800c4ec CP_SetDuty(duty); 800c3b8: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 800c3bc: 4618 mov r0, r3 800c3be: f7fd fe41 bl 800a044 } break; 800c3c2: e093 b.n 800c4ec } case CMD_E2M_ENABLE_OUTPUT: { const e2m_enable_output_t* p = (const e2m_enable_output_t*)payload; 800c3c4: 683b ldr r3, [r7, #0] 800c3c6: 613b str r3, [r7, #16] ev_enable_output = (p->enable_output != 0); 800c3c8: 693b ldr r3, [r7, #16] 800c3ca: 781b ldrb r3, [r3, #0] 800c3cc: 2b00 cmp r3, #0 800c3ce: bf14 ite ne 800c3d0: 2301 movne r3, #1 800c3d2: 2300 moveq r3, #0 800c3d4: b2db uxtb r3, r3 800c3d6: 461a mov r2, r3 800c3d8: 4b4b ldr r3, [pc, #300] @ (800c508 ) 800c3da: 701a strb r2, [r3, #0] break; 800c3dc: e089 b.n 800c4f2 } case CMD_E2M_RESET: { const e2m_reset_t* p = (const e2m_reset_t*)payload; 800c3de: 683b ldr r3, [r7, #0] 800c3e0: 617b str r3, [r7, #20] if (p->reset) { 800c3e2: 697b ldr r3, [r7, #20] 800c3e4: 781b ldrb r3, [r3, #0] 800c3e6: 2b00 cmp r3, #0 800c3e8: f000 8082 beq.w 800c4f0 log_printf(LOG_WARN, "Everest reset command\n"); 800c3ec: 4947 ldr r1, [pc, #284] @ (800c50c ) 800c3ee: 2005 movs r0, #5 800c3f0: f7fd ffe6 bl 800a3c0 CCS_SendResetReason(); 800c3f4: f7ff fe82 bl 800c0fc HAL_Delay(10); 800c3f8: 200a movs r0, #10 800c3fa: f001 fc49 bl 800dc90 NVIC_SystemReset(); 800c3fe: f7ff faff bl 800ba00 <__NVIC_SystemReset> } break; } case CMD_E2M_ENABLE: { const e2m_enable_t* p = (const e2m_enable_t*)payload; 800c402: 683b ldr r3, [r7, #0] 800c404: 61bb str r3, [r7, #24] enabled = (p->enable != 0); 800c406: 69bb ldr r3, [r7, #24] 800c408: 781b ldrb r3, [r3, #0] 800c40a: 2b00 cmp r3, #0 800c40c: bf14 ite ne 800c40e: 2301 movne r3, #1 800c410: 2300 moveq r3, #0 800c412: b2db uxtb r3, r3 800c414: 461a mov r2, r3 800c416: 4b3e ldr r3, [pc, #248] @ (800c510 ) 800c418: 701a strb r2, [r3, #0] (void)enabled; break; 800c41a: e06a b.n 800c4f2 } case CMD_E2M_SET_OUTPUT_VOLTAGE: { const e2m_set_output_t* p = (const e2m_set_output_t*)payload; 800c41c: 683b ldr r3, [r7, #0] 800c41e: 61fb str r3, [r7, #28] if (p->voltage_V == FAKE_EVREQ_VOLTAGE_V) { 800c420: 69fb ldr r3, [r7, #28] 800c422: 881b ldrh r3, [r3, #0] 800c424: b29b uxth r3, r3 800c426: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800c42a: d113 bne.n 800c454 fake_500_voltage_mode = 1u; 800c42c: 4b39 ldr r3, [pc, #228] @ (800c514 ) 800c42e: 2201 movs r2, #1 800c430: 701a strb r2, [r3, #0] CONN.RequestedVoltage = FAKE_PSU_VOLTAGE_V; 800c432: 4b34 ldr r3, [pc, #208] @ (800c504 ) 800c434: 2200 movs r2, #0 800c436: f042 022c orr.w r2, r2, #44 @ 0x2c 800c43a: 73da strb r2, [r3, #15] 800c43c: 2200 movs r2, #0 800c43e: f042 0201 orr.w r2, r2, #1 800c442: 741a strb r2, [r3, #16] CONN.WantedCurrent = FAKE_PSU_CURRENT_0P1A; 800c444: 4b2f ldr r3, [pc, #188] @ (800c504 ) 800c446: 2200 movs r2, #0 800c448: f042 020a orr.w r2, r2, #10 800c44c: 76da strb r2, [r3, #27] 800c44e: 2200 movs r2, #0 800c450: 771a strb r2, [r3, #28] } else { fake_500_voltage_mode = 0u; CONN.RequestedVoltage = p->voltage_V; CONN.WantedCurrent = p->current_0p1A; } break; 800c452: e04e b.n 800c4f2 fake_500_voltage_mode = 0u; 800c454: 4b2f ldr r3, [pc, #188] @ (800c514 ) 800c456: 2200 movs r2, #0 800c458: 701a strb r2, [r3, #0] CONN.RequestedVoltage = p->voltage_V; 800c45a: 69fb ldr r3, [r7, #28] 800c45c: 881b ldrh r3, [r3, #0] 800c45e: b29a uxth r2, r3 800c460: 4b28 ldr r3, [pc, #160] @ (800c504 ) 800c462: f8a3 200f strh.w r2, [r3, #15] CONN.WantedCurrent = p->current_0p1A; 800c466: 69fb ldr r3, [r7, #28] 800c468: 885b ldrh r3, [r3, #2] 800c46a: b29a uxth r2, r3 800c46c: 4b25 ldr r3, [pc, #148] @ (800c504 ) 800c46e: f8a3 201b strh.w r2, [r3, #27] break; 800c472: e03e b.n 800c4f2 } case CMD_E2M_ISOLATION_CONTROL: { const e2m_isolation_control_t* p = (const e2m_isolation_control_t*)payload; 800c474: 683b ldr r3, [r7, #0] 800c476: 623b str r3, [r7, #32] isolation_enable = p->command; 800c478: 6a3b ldr r3, [r7, #32] 800c47a: 781a ldrb r2, [r3, #0] 800c47c: 4b26 ldr r3, [pc, #152] @ (800c518 ) 800c47e: 701a strb r2, [r3, #0] break; 800c480: e037 b.n 800c4f2 } case CMD_E2M_EV_INFO: { memcpy(&CCS_EvInfo, payload, sizeof(CCS_EvInfo_t)); 800c482: 4a26 ldr r2, [pc, #152] @ (800c51c ) 800c484: 683b ldr r3, [r7, #0] 800c486: 461c mov r4, r3 800c488: 4616 mov r6, r2 800c48a: f104 0c20 add.w ip, r4, #32 800c48e: 4635 mov r5, r6 800c490: 4623 mov r3, r4 800c492: 6818 ldr r0, [r3, #0] 800c494: 6859 ldr r1, [r3, #4] 800c496: 689a ldr r2, [r3, #8] 800c498: 68db ldr r3, [r3, #12] 800c49a: c50f stmia r5!, {r0, r1, r2, r3} 800c49c: 3410 adds r4, #16 800c49e: 3610 adds r6, #16 800c4a0: 4564 cmp r4, ip 800c4a2: d1f4 bne.n 800c48e 800c4a4: 4633 mov r3, r6 800c4a6: 4622 mov r2, r4 800c4a8: 6810 ldr r0, [r2, #0] 800c4aa: 6851 ldr r1, [r2, #4] 800c4ac: 6892 ldr r2, [r2, #8] 800c4ae: c307 stmia r3!, {r0, r1, r2} CONN.SOC = (uint8_t)(CCS_EvInfo.soc / 10); 800c4b0: 4b1a ldr r3, [pc, #104] @ (800c51c ) 800c4b2: 885b ldrh r3, [r3, #2] 800c4b4: 4a1a ldr r2, [pc, #104] @ (800c520 ) 800c4b6: fba2 2303 umull r2, r3, r2, r3 800c4ba: 08db lsrs r3, r3, #3 800c4bc: b29b uxth r3, r3 800c4be: b2da uxtb r2, r3 800c4c0: 4b10 ldr r3, [pc, #64] @ (800c504 ) 800c4c2: 709a strb r2, [r3, #2] break; 800c4c4: e015 b.n 800c4f2 } case CMD_E2M_EVSE_STATE: { CCS_EvseState = (CONN_State_t)payload[0]; 800c4c6: 683b ldr r3, [r7, #0] 800c4c8: 781a ldrb r2, [r3, #0] 800c4ca: 4b16 ldr r3, [pc, #88] @ (800c524 ) 800c4cc: 701a strb r2, [r3, #0] break; 800c4ce: e010 b.n 800c4f2 } case CMD_E2M_REPLUG: { (void)payload; CP_SetDuty(pwm_duty_percent); 800c4d0: 4b0b ldr r3, [pc, #44] @ (800c500 ) 800c4d2: 781b ldrb r3, [r3, #0] 800c4d4: 4618 mov r0, r3 800c4d6: f7fd fdb5 bl 800a044 break; 800c4da: e00a b.n 800c4f2 } case CMD_E2M_KEEP_ALIVE: { last_host_seen = HAL_GetTick(); 800c4dc: f001 fbce bl 800dc7c 800c4e0: 4603 mov r3, r0 800c4e2: 4a06 ldr r2, [pc, #24] @ (800c4fc ) 800c4e4: 6013 str r3, [r2, #0] break; 800c4e6: e004 b.n 800c4f2 } default: break; 800c4e8: bf00 nop 800c4ea: e002 b.n 800c4f2 break; 800c4ec: bf00 nop 800c4ee: e000 b.n 800c4f2 break; 800c4f0: bf00 nop } } 800c4f2: bf00 nop 800c4f4: 372c adds r7, #44 @ 0x2c 800c4f6: 46bd mov sp, r7 800c4f8: bdf0 pop {r4, r5, r6, r7, pc} 800c4fa: bf00 nop 800c4fc: 20000b54 .word 0x20000b54 800c500: 20000066 .word 0x20000066 800c504: 20000354 .word 0x20000354 800c508: 2000094d .word 0x2000094d 800c50c: 08016294 .word 0x08016294 800c510: 20000b52 .word 0x20000b52 800c514: 20000b58 .word 0x20000b58 800c518: 20000b53 .word 0x20000b53 800c51c: 20000b7c .word 0x20000b7c 800c520: cccccccd .word 0xcccccccd 800c524: 20000ba8 .word 0x20000ba8 0800c528 : static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len) { 800c528: b580 push {r7, lr} 800c52a: b086 sub sp, #24 800c52c: af00 add r7, sp, #0 800c52e: 6078 str r0, [r7, #4] 800c530: 460b mov r3, r1 800c532: 807b strh r3, [r7, #2] if (packet_len < 3) return 0; 800c534: 887b ldrh r3, [r7, #2] 800c536: 2b02 cmp r3, #2 800c538: d801 bhi.n 800c53e 800c53a: 2300 movs r3, #0 800c53c: e05a b.n 800c5f4 uint8_t cmd = packet[0]; 800c53e: 687b ldr r3, [r7, #4] 800c540: 781b ldrb r3, [r3, #0] 800c542: 75fb strb r3, [r7, #23] uint16_t payload_len = (uint16_t)(packet_len - 3); 800c544: 887b ldrh r3, [r7, #2] 800c546: 3b03 subs r3, #3 800c548: 82bb strh r3, [r7, #20] uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800c54a: 887b ldrh r3, [r7, #2] 800c54c: 3b02 subs r3, #2 800c54e: 687a ldr r2, [r7, #4] 800c550: 4413 add r3, r2 800c552: 781b ldrb r3, [r3, #0] 800c554: b21a sxth r2, r3 (uint16_t)packet[packet_len - 1u] << 8; 800c556: 887b ldrh r3, [r7, #2] 800c558: 3b01 subs r3, #1 800c55a: 6879 ldr r1, [r7, #4] 800c55c: 440b add r3, r1 800c55e: 781b ldrb r3, [r3, #0] uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800c560: b21b sxth r3, r3 800c562: 021b lsls r3, r3, #8 800c564: b21b sxth r3, r3 800c566: 4313 orrs r3, r2 800c568: b21b sxth r3, r3 800c56a: 827b strh r3, [r7, #18] uint16_t calculated_crc = crc16_ibm(packet, (uint16_t)(1 + payload_len)); 800c56c: 8abb ldrh r3, [r7, #20] 800c56e: 3301 adds r3, #1 800c570: b29b uxth r3, r3 800c572: 4619 mov r1, r3 800c574: 6878 ldr r0, [r7, #4] 800c576: f7ff fd19 bl 800bfac 800c57a: 4603 mov r3, r0 800c57c: 823b strh r3, [r7, #16] if (received_crc != calculated_crc) { 800c57e: 8a7a ldrh r2, [r7, #18] 800c580: 8a3b ldrh r3, [r7, #16] 800c582: 429a cmp r2, r3 800c584: d005 beq.n 800c592 log_printf(LOG_ERR, "Packet CRC error\n"); 800c586: 491d ldr r1, [pc, #116] @ (800c5fc ) 800c588: 2004 movs r0, #4 800c58a: f7fd ff19 bl 800a3c0 return 0; 800c58e: 2300 movs r3, #0 800c590: e030 b.n 800c5f4 } uint16_t expected_len = expected_payload_len(cmd); 800c592: 7dfb ldrb r3, [r7, #23] 800c594: 4618 mov r0, r3 800c596: f7ff fe93 bl 800c2c0 800c59a: 4603 mov r3, r0 800c59c: 81fb strh r3, [r7, #14] if (expected_len == 0xFFFF) { 800c59e: 89fb ldrh r3, [r7, #14] 800c5a0: f64f 72ff movw r2, #65535 @ 0xffff 800c5a4: 4293 cmp r3, r2 800c5a6: d107 bne.n 800c5b8 log_printf(LOG_WARN, "Unknown cmd 0x%02x\n", cmd); 800c5a8: 7dfb ldrb r3, [r7, #23] 800c5aa: 461a mov r2, r3 800c5ac: 4914 ldr r1, [pc, #80] @ (800c600 ) 800c5ae: 2005 movs r0, #5 800c5b0: f7fd ff06 bl 800a3c0 return 0; 800c5b4: 2300 movs r3, #0 800c5b6: e01d b.n 800c5f4 } if (expected_len != payload_len) { 800c5b8: 89fa ldrh r2, [r7, #14] 800c5ba: 8abb ldrh r3, [r7, #20] 800c5bc: 429a cmp r2, r3 800c5be: d007 beq.n 800c5d0 log_printf(LOG_ERR, "Packet len mismatch cmd=0x%02x\n", cmd); 800c5c0: 7dfb ldrb r3, [r7, #23] 800c5c2: 461a mov r2, r3 800c5c4: 490f ldr r1, [pc, #60] @ (800c604 ) 800c5c6: 2004 movs r0, #4 800c5c8: f7fd fefa bl 800a3c0 return 0; 800c5cc: 2300 movs r3, #0 800c5ce: e011 b.n 800c5f4 } if (payload_len > 0) { 800c5d0: 8abb ldrh r3, [r7, #20] 800c5d2: 2b00 cmp r3, #0 800c5d4: d007 beq.n 800c5e6 apply_command(cmd, &packet[1], payload_len); 800c5d6: 687b ldr r3, [r7, #4] 800c5d8: 1c59 adds r1, r3, #1 800c5da: 8aba ldrh r2, [r7, #20] 800c5dc: 7dfb ldrb r3, [r7, #23] 800c5de: 4618 mov r0, r3 800c5e0: f7ff feaa bl 800c338 800c5e4: e005 b.n 800c5f2 } else { apply_command(cmd, NULL, 0); 800c5e6: 7dfb ldrb r3, [r7, #23] 800c5e8: 2200 movs r2, #0 800c5ea: 2100 movs r1, #0 800c5ec: 4618 mov r0, r3 800c5ee: f7ff fea3 bl 800c338 } return 1; 800c5f2: 2301 movs r3, #1 } 800c5f4: 4618 mov r0, r3 800c5f6: 3718 adds r7, #24 800c5f8: 46bd mov sp, r7 800c5fa: bd80 pop {r7, pc} 800c5fc: 080162ac .word 0x080162ac 800c600: 080162c0 .word 0x080162c0 800c604: 080162d4 .word 0x080162d4 0800c608 : .fw_version_major = 0, .fw_version_minor = 0, .fw_version_patch = 0, }; void ReadVersion(){ 800c608: b480 push {r7} 800c60a: af00 add r7, sp, #0 infoPacket.serialNumber = InfoBlock->serialNumber; 800c60c: 4b0e ldr r3, [pc, #56] @ (800c648 ) 800c60e: 681b ldr r3, [r3, #0] 800c610: 681b ldr r3, [r3, #0] 800c612: b29a uxth r2, r3 800c614: 4b0d ldr r3, [pc, #52] @ (800c64c ) 800c616: 801a strh r2, [r3, #0] infoPacket.boardVersion = InfoBlock->boardVersion; 800c618: 4b0b ldr r3, [pc, #44] @ (800c648 ) 800c61a: 681b ldr r3, [r3, #0] 800c61c: 795a ldrb r2, [r3, #5] 800c61e: 4b0b ldr r3, [pc, #44] @ (800c64c ) 800c620: 709a strb r2, [r3, #2] infoPacket.stationType = InfoBlock->stationType; 800c622: 4b09 ldr r3, [pc, #36] @ (800c648 ) 800c624: 681b ldr r3, [r3, #0] 800c626: 791a ldrb r2, [r3, #4] 800c628: 4b08 ldr r3, [pc, #32] @ (800c64c ) 800c62a: 70da strb r2, [r3, #3] infoPacket.fw_version_major = FW_VERSION_MAJOR; 800c62c: 4b07 ldr r3, [pc, #28] @ (800c64c ) 800c62e: 2201 movs r2, #1 800c630: 809a strh r2, [r3, #4] infoPacket.fw_version_minor = FW_VERSION_MINOR; 800c632: 4b06 ldr r3, [pc, #24] @ (800c64c ) 800c634: 2200 movs r2, #0 800c636: 80da strh r2, [r3, #6] infoPacket.fw_version_patch = FW_VERSION_PATCH; 800c638: 4b04 ldr r3, [pc, #16] @ (800c64c ) 800c63a: 220a movs r2, #10 800c63c: 811a strh r2, [r3, #8] } 800c63e: bf00 nop 800c640: 46bd mov sp, r7 800c642: bc80 pop {r7} 800c644: 4770 bx lr 800c646: bf00 nop 800c648: 20000000 .word 0x20000000 800c64c: 20001044 .word 0x20001044 0800c650 : // Внешняя функция обработки команд (определена в serial_handler.c) extern void SC_CommandHandler(ReceivedCommand_t* cmd); void SC_Init() { 800c650: b580 push {r7, lr} 800c652: af00 add r7, sp, #0 // Обнуляем структуру memset(&serial_control, 0, sizeof(SerialControl_t)); 800c654: f44f 7205 mov.w r2, #532 @ 0x214 800c658: 2100 movs r1, #0 800c65a: 4805 ldr r0, [pc, #20] @ (800c670 ) 800c65c: f007 fb2e bl 8013cbc memset(&serial_iso, 0, sizeof(serial_iso)); 800c660: f44f 7205 mov.w r2, #532 @ 0x214 800c664: 2100 movs r1, #0 800c666: 4803 ldr r0, [pc, #12] @ (800c674 ) 800c668: f007 fb28 bl 8013cbc } 800c66c: bf00 nop 800c66e: bd80 pop {r7, pc} 800c670: 20000bc0 .word 0x20000bc0 800c674: 20000dd4 .word 0x20000dd4 0800c678 : void SC_Task() { 800c678: b580 push {r7, lr} 800c67a: af00 add r7, sp, #0 // Запуск приема в режиме прерывания с ожиданием idle SC_ArmUart2Rx(); 800c67c: f000 f92e bl 800c8dc SC_ArmUart5Rx(); 800c680: f000 f948 bl 800c914 // Проверка таймаута отправки пакета (больше 100 мс) if (huart2.gState == HAL_UART_STATE_BUSY_TX && serial_control.tx_tick != 0) { 800c684: 4b32 ldr r3, [pc, #200] @ (800c750 ) 800c686: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800c68a: b2db uxtb r3, r3 800c68c: 2b21 cmp r3, #33 @ 0x21 800c68e: d119 bne.n 800c6c4 800c690: 4b30 ldr r3, [pc, #192] @ (800c754 ) 800c692: f8d3 3210 ldr.w r3, [r3, #528] @ 0x210 800c696: 2b00 cmp r3, #0 800c698: d014 beq.n 800c6c4 if ((HAL_GetTick() - serial_control.tx_tick) > 100) { 800c69a: f001 faef bl 800dc7c 800c69e: 4602 mov r2, r0 800c6a0: 4b2c ldr r3, [pc, #176] @ (800c754 ) 800c6a2: f8d3 3210 ldr.w r3, [r3, #528] @ 0x210 800c6a6: 1ad3 subs r3, r2, r3 800c6a8: 2b64 cmp r3, #100 @ 0x64 800c6aa: d90b bls.n 800c6c4 // Таймаут: принудительно сбрасываем передачу HAL_UART_Abort_IT(&huart2); 800c6ac: 4828 ldr r0, [pc, #160] @ (800c750 ) 800c6ae: f005 febd bl 801242c // Выключаем DIR при сбросе передачи HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800c6b2: 2200 movs r2, #0 800c6b4: 2110 movs r1, #16 800c6b6: 4828 ldr r0, [pc, #160] @ (800c758 ) 800c6b8: f003 faf1 bl 800fc9e serial_control.tx_tick = 0; // Сбрасываем tick 800c6bc: 4b25 ldr r3, [pc, #148] @ (800c754 ) 800c6be: 2200 movs r2, #0 800c6c0: f8c3 2210 str.w r2, [r3, #528] @ 0x210 } } // Проверка наличия принятой команды для обработки if (serial_control.command_ready && (huart2.gState != HAL_UART_STATE_BUSY_TX)) { 800c6c4: 4b23 ldr r3, [pc, #140] @ (800c754 ) 800c6c6: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800c6ca: b2db uxtb r3, r3 800c6cc: 2b00 cmp r3, #0 800c6ce: d011 beq.n 800c6f4 800c6d0: 4b1f ldr r3, [pc, #124] @ (800c750 ) 800c6d2: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800c6d6: b2db uxtb r3, r3 800c6d8: 2b21 cmp r3, #33 @ 0x21 800c6da: d00b beq.n 800c6f4 g_sc_command_source = SC_SOURCE_UART2; 800c6dc: 4b1f ldr r3, [pc, #124] @ (800c75c ) 800c6de: 2200 movs r2, #0 800c6e0: 701a strb r2, [r3, #0] SC_CommandHandler(&serial_control.received_command); 800c6e2: 481f ldr r0, [pc, #124] @ (800c760 ) 800c6e4: f000 fa88 bl 800cbf8 serial_control.command_ready = 0; // Сбрасываем флаг 800c6e8: 4b1a ldr r3, [pc, #104] @ (800c754 ) 800c6ea: 2200 movs r2, #0 800c6ec: f883 2208 strb.w r2, [r3, #520] @ 0x208 SC_ArmUart2Rx(); 800c6f0: f000 f8f4 bl 800c8dc } if (serial_control.response_pending && (huart2.gState != HAL_UART_STATE_BUSY_TX)) { 800c6f4: 4b17 ldr r3, [pc, #92] @ (800c754 ) 800c6f6: f893 3209 ldrb.w r3, [r3, #521] @ 0x209 800c6fa: b2db uxtb r3, r3 800c6fc: 2b00 cmp r3, #0 800c6fe: d012 beq.n 800c726 800c700: 4b13 ldr r3, [pc, #76] @ (800c750 ) 800c702: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800c706: b2db uxtb r3, r3 800c708: 2b21 cmp r3, #33 @ 0x21 800c70a: d00c beq.n 800c726 SC_SendPacket(NULL, 0, serial_control.response_code); 800c70c: 4b11 ldr r3, [pc, #68] @ (800c754 ) 800c70e: f893 320a ldrb.w r3, [r3, #522] @ 0x20a 800c712: b2db uxtb r3, r3 800c714: 461a mov r2, r3 800c716: 2100 movs r1, #0 800c718: 2000 movs r0, #0 800c71a: f000 f9ad bl 800ca78 serial_control.response_pending = 0; 800c71e: 4b0d ldr r3, [pc, #52] @ (800c754 ) 800c720: 2200 movs r2, #0 800c722: f883 2209 strb.w r2, [r3, #521] @ 0x209 } if (serial_iso.command_ready) { 800c726: 4b0f ldr r3, [pc, #60] @ (800c764 ) 800c728: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800c72c: b2db uxtb r3, r3 800c72e: 2b00 cmp r3, #0 800c730: d00b beq.n 800c74a g_sc_command_source = SC_SOURCE_UART5; 800c732: 4b0a ldr r3, [pc, #40] @ (800c75c ) 800c734: 2201 movs r2, #1 800c736: 701a strb r2, [r3, #0] SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); 800c738: 480b ldr r0, [pc, #44] @ (800c768 ) 800c73a: f000 fa5d bl 800cbf8 serial_iso.command_ready = 0; 800c73e: 4b09 ldr r3, [pc, #36] @ (800c764 ) 800c740: 2200 movs r2, #0 800c742: f883 2208 strb.w r2, [r3, #520] @ 0x208 SC_ArmUart5Rx(); 800c746: f000 f8e5 bl 800c914 } } 800c74a: bf00 nop 800c74c: bd80 pop {r7, pc} 800c74e: bf00 nop 800c750: 20001174 .word 0x20001174 800c754: 20000bc0 .word 0x20000bc0 800c758: 40011400 .word 0x40011400 800c75c: 20000fe8 .word 0x20000fe8 800c760: 20000dc0 .word 0x20000dc0 800c764: 20000dd4 .word 0x20000dd4 800c768: 20000fd4 .word 0x20000fd4 0800c76c : void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800c76c: b580 push {r7, lr} 800c76e: b082 sub sp, #8 800c770: af00 add r7, sp, #0 800c772: 6078 str r0, [r7, #4] 800c774: 460b mov r3, r1 800c776: 807b strh r3, [r7, #2] if (huart->Instance == huart2.Instance) { 800c778: 687b ldr r3, [r7, #4] 800c77a: 681a ldr r2, [r3, #0] 800c77c: 4b1c ldr r3, [pc, #112] @ (800c7f0 ) 800c77e: 681b ldr r3, [r3, #0] 800c780: 429a cmp r2, r3 800c782: d113 bne.n 800c7ac if (!process_received_packet(&serial_control, serial_control.rx_buffer, Size)) { 800c784: 887b ldrh r3, [r7, #2] 800c786: 461a mov r2, r3 800c788: 491a ldr r1, [pc, #104] @ (800c7f4 ) 800c78a: 481b ldr r0, [pc, #108] @ (800c7f8 ) 800c78c: f000 fa00 bl 800cb90 800c790: 4603 mov r3, r0 800c792: 2b00 cmp r3, #0 800c794: d127 bne.n 800c7e6 serial_control.response_pending = 1; 800c796: 4b18 ldr r3, [pc, #96] @ (800c7f8 ) 800c798: 2201 movs r2, #1 800c79a: f883 2209 strb.w r2, [r3, #521] @ 0x209 serial_control.response_code = RESP_INVALID; 800c79e: 4b16 ldr r3, [pc, #88] @ (800c7f8 ) 800c7a0: 2214 movs r2, #20 800c7a2: f883 220a strb.w r2, [r3, #522] @ 0x20a SC_ArmUart2Rx(); 800c7a6: f000 f899 bl 800c8dc SC_ArmUart5Rx(); } } else if (huart->Instance == huart3.Instance) { CCS_RxEventCallback(huart, Size); } } 800c7aa: e01c b.n 800c7e6 } else if (huart->Instance == huart5.Instance) { 800c7ac: 687b ldr r3, [r7, #4] 800c7ae: 681a ldr r2, [r3, #0] 800c7b0: 4b12 ldr r3, [pc, #72] @ (800c7fc ) 800c7b2: 681b ldr r3, [r3, #0] 800c7b4: 429a cmp r2, r3 800c7b6: d10b bne.n 800c7d0 if (!process_received_packet(&serial_iso, serial_iso.rx_buffer, Size)) { 800c7b8: 887b ldrh r3, [r7, #2] 800c7ba: 461a mov r2, r3 800c7bc: 4910 ldr r1, [pc, #64] @ (800c800 ) 800c7be: 4811 ldr r0, [pc, #68] @ (800c804 ) 800c7c0: f000 f9e6 bl 800cb90 800c7c4: 4603 mov r3, r0 800c7c6: 2b00 cmp r3, #0 800c7c8: d10d bne.n 800c7e6 SC_ArmUart5Rx(); 800c7ca: f000 f8a3 bl 800c914 } 800c7ce: e00a b.n 800c7e6 } else if (huart->Instance == huart3.Instance) { 800c7d0: 687b ldr r3, [r7, #4] 800c7d2: 681a ldr r2, [r3, #0] 800c7d4: 4b0c ldr r3, [pc, #48] @ (800c808 ) 800c7d6: 681b ldr r3, [r3, #0] 800c7d8: 429a cmp r2, r3 800c7da: d104 bne.n 800c7e6 CCS_RxEventCallback(huart, Size); 800c7dc: 887b ldrh r3, [r7, #2] 800c7de: 4619 mov r1, r3 800c7e0: 6878 ldr r0, [r7, #4] 800c7e2: f7ff f923 bl 800ba2c } 800c7e6: bf00 nop 800c7e8: 3708 adds r7, #8 800c7ea: 46bd mov sp, r7 800c7ec: bd80 pop {r7, pc} 800c7ee: bf00 nop 800c7f0: 20001174 .word 0x20001174 800c7f4: 20000cc0 .word 0x20000cc0 800c7f8: 20000bc0 .word 0x20000bc0 800c7fc: 200010e4 .word 0x200010e4 800c800: 20000ed4 .word 0x20000ed4 800c804: 20000dd4 .word 0x20000dd4 800c808: 200011bc .word 0x200011bc 0800c80c : void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 800c80c: b580 push {r7, lr} 800c80e: b086 sub sp, #24 800c810: af00 add r7, sp, #0 800c812: 6078 str r0, [r7, #4] if (huart->Instance == huart2.Instance) { 800c814: 687b ldr r3, [r7, #4] 800c816: 681a ldr r2, [r3, #0] 800c818: 4b1b ldr r3, [pc, #108] @ (800c888 ) 800c81a: 681b ldr r3, [r3, #0] 800c81c: 429a cmp r2, r3 800c81e: d10b bne.n 800c838 uint32_t uart_error = HAL_UART_GetError(huart); 800c820: 6878 ldr r0, [r7, #4] 800c822: f006 f9bb bl 8012b9c 800c826: 60f8 str r0, [r7, #12] log_printf(LOG_WARN, "USART2 rx error: 0x%08lx\n", uart_error); 800c828: 68fa ldr r2, [r7, #12] 800c82a: 4918 ldr r1, [pc, #96] @ (800c88c ) 800c82c: 2005 movs r0, #5 800c82e: f7fd fdc7 bl 800a3c0 SC_ArmUart2Rx(); 800c832: f000 f853 bl 800c8dc } else if (huart->Instance == huart3.Instance) { uint32_t uart_error = HAL_UART_GetError(huart); log_printf(LOG_WARN, "USART3 rx error: 0x%08lx\n", uart_error); CCS_RxArm(); } } 800c836: e022 b.n 800c87e } else if (huart->Instance == huart5.Instance) { 800c838: 687b ldr r3, [r7, #4] 800c83a: 681a ldr r2, [r3, #0] 800c83c: 4b14 ldr r3, [pc, #80] @ (800c890 ) 800c83e: 681b ldr r3, [r3, #0] 800c840: 429a cmp r2, r3 800c842: d10b bne.n 800c85c uint32_t uart_error = HAL_UART_GetError(huart); 800c844: 6878 ldr r0, [r7, #4] 800c846: f006 f9a9 bl 8012b9c 800c84a: 6138 str r0, [r7, #16] log_printf(LOG_WARN, "UART5 rx error: 0x%08lx\n", uart_error); 800c84c: 693a ldr r2, [r7, #16] 800c84e: 4911 ldr r1, [pc, #68] @ (800c894 ) 800c850: 2005 movs r0, #5 800c852: f7fd fdb5 bl 800a3c0 SC_ArmUart5Rx(); 800c856: f000 f85d bl 800c914 } 800c85a: e010 b.n 800c87e } else if (huart->Instance == huart3.Instance) { 800c85c: 687b ldr r3, [r7, #4] 800c85e: 681a ldr r2, [r3, #0] 800c860: 4b0d ldr r3, [pc, #52] @ (800c898 ) 800c862: 681b ldr r3, [r3, #0] 800c864: 429a cmp r2, r3 800c866: d10a bne.n 800c87e uint32_t uart_error = HAL_UART_GetError(huart); 800c868: 6878 ldr r0, [r7, #4] 800c86a: f006 f997 bl 8012b9c 800c86e: 6178 str r0, [r7, #20] log_printf(LOG_WARN, "USART3 rx error: 0x%08lx\n", uart_error); 800c870: 697a ldr r2, [r7, #20] 800c872: 490a ldr r1, [pc, #40] @ (800c89c ) 800c874: 2005 movs r0, #5 800c876: f7fd fda3 bl 800a3c0 CCS_RxArm(); 800c87a: f7ff f8f7 bl 800ba6c } 800c87e: bf00 nop 800c880: 3718 adds r7, #24 800c882: 46bd mov sp, r7 800c884: bd80 pop {r7, pc} 800c886: bf00 nop 800c888: 20001174 .word 0x20001174 800c88c: 080162f4 .word 0x080162f4 800c890: 200010e4 .word 0x200010e4 800c894: 08016310 .word 0x08016310 800c898: 200011bc .word 0x200011bc 800c89c: 0801632c .word 0x0801632c 0800c8a0 : void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 800c8a0: b580 push {r7, lr} 800c8a2: b082 sub sp, #8 800c8a4: af00 add r7, sp, #0 800c8a6: 6078 str r0, [r7, #4] if (huart->Instance == huart2.Instance) { 800c8a8: 687b ldr r3, [r7, #4] 800c8aa: 681a ldr r2, [r3, #0] 800c8ac: 4b08 ldr r3, [pc, #32] @ (800c8d0 ) 800c8ae: 681b ldr r3, [r3, #0] 800c8b0: 429a cmp r2, r3 800c8b2: d108 bne.n 800c8c6 HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800c8b4: 2200 movs r2, #0 800c8b6: 2110 movs r1, #16 800c8b8: 4806 ldr r0, [pc, #24] @ (800c8d4 ) 800c8ba: f003 f9f0 bl 800fc9e serial_control.tx_tick = 0; 800c8be: 4b06 ldr r3, [pc, #24] @ (800c8d8 ) 800c8c0: 2200 movs r2, #0 800c8c2: f8c3 2210 str.w r2, [r3, #528] @ 0x210 } } 800c8c6: bf00 nop 800c8c8: 3708 adds r7, #8 800c8ca: 46bd mov sp, r7 800c8cc: bd80 pop {r7, pc} 800c8ce: bf00 nop 800c8d0: 20001174 .word 0x20001174 800c8d4: 40011400 .word 0x40011400 800c8d8: 20000bc0 .word 0x20000bc0 0800c8dc : static void SC_ArmUart2Rx(void) { 800c8dc: b580 push {r7, lr} 800c8de: af00 add r7, sp, #0 if ((&huart2)->RxState == HAL_UART_STATE_READY && serial_control.command_ready == 0) { 800c8e0: 4b09 ldr r3, [pc, #36] @ (800c908 ) 800c8e2: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800c8e6: b2db uxtb r3, r3 800c8e8: 2b20 cmp r3, #32 800c8ea: d10a bne.n 800c902 800c8ec: 4b07 ldr r3, [pc, #28] @ (800c90c ) 800c8ee: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800c8f2: b2db uxtb r3, r3 800c8f4: 2b00 cmp r3, #0 800c8f6: d104 bne.n 800c902 (void)HAL_UARTEx_ReceiveToIdle_IT(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c8f8: 22ff movs r2, #255 @ 0xff 800c8fa: 4905 ldr r1, [pc, #20] @ (800c910 ) 800c8fc: 4802 ldr r0, [pc, #8] @ (800c908 ) 800c8fe: f005 fd37 bl 8012370 } } 800c902: bf00 nop 800c904: bd80 pop {r7, pc} 800c906: bf00 nop 800c908: 20001174 .word 0x20001174 800c90c: 20000bc0 .word 0x20000bc0 800c910: 20000cc0 .word 0x20000cc0 0800c914 : static void SC_ArmUart5Rx(void) { 800c914: b580 push {r7, lr} 800c916: af00 add r7, sp, #0 if ((&huart5)->RxState == HAL_UART_STATE_READY && serial_iso.command_ready == 0) { 800c918: 4b09 ldr r3, [pc, #36] @ (800c940 ) 800c91a: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800c91e: b2db uxtb r3, r3 800c920: 2b20 cmp r3, #32 800c922: d10a bne.n 800c93a 800c924: 4b07 ldr r3, [pc, #28] @ (800c944 ) 800c926: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800c92a: b2db uxtb r3, r3 800c92c: 2b00 cmp r3, #0 800c92e: d104 bne.n 800c93a (void)HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1); 800c930: 22ff movs r2, #255 @ 0xff 800c932: 4905 ldr r1, [pc, #20] @ (800c948 ) 800c934: 4802 ldr r0, [pc, #8] @ (800c940 ) 800c936: f005 fd1b bl 8012370 } } 800c93a: bf00 nop 800c93c: bd80 pop {r7, pc} 800c93e: bf00 nop 800c940: 200010e4 .word 0x200010e4 800c944: 20000dd4 .word 0x20000dd4 800c948: 20000ed4 .word 0x20000ed4 0800c94c : // Приватные функции реализации // Полностью программная реализация CRC-32 (полином CRC32_POLYNOMIAL, порядок little-endian) static uint32_t calculate_crc32(const uint8_t* data, uint16_t length) { 800c94c: b480 push {r7} 800c94e: b085 sub sp, #20 800c950: af00 add r7, sp, #0 800c952: 6078 str r0, [r7, #4] 800c954: 460b mov r3, r1 800c956: 807b strh r3, [r7, #2] uint32_t crc = 0xFFFFFFFFu; 800c958: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800c95c: 60fb str r3, [r7, #12] for (uint16_t i = 0; i < length; i++) { 800c95e: 2300 movs r3, #0 800c960: 817b strh r3, [r7, #10] 800c962: e021 b.n 800c9a8 crc ^= data[i]; 800c964: 897b ldrh r3, [r7, #10] 800c966: 687a ldr r2, [r7, #4] 800c968: 4413 add r3, r2 800c96a: 781b ldrb r3, [r3, #0] 800c96c: 461a mov r2, r3 800c96e: 68fb ldr r3, [r7, #12] 800c970: 4053 eors r3, r2 800c972: 60fb str r3, [r7, #12] for (uint8_t bit = 0; bit < 8; bit++) { 800c974: 2300 movs r3, #0 800c976: 727b strb r3, [r7, #9] 800c978: e010 b.n 800c99c if (crc & 0x1u) { 800c97a: 68fb ldr r3, [r7, #12] 800c97c: f003 0301 and.w r3, r3, #1 800c980: 2b00 cmp r3, #0 800c982: d005 beq.n 800c990 crc = (crc >> 1) ^ CRC32_POLYNOMIAL; 800c984: 68fb ldr r3, [r7, #12] 800c986: 085a lsrs r2, r3, #1 800c988: 4b0d ldr r3, [pc, #52] @ (800c9c0 ) 800c98a: 4053 eors r3, r2 800c98c: 60fb str r3, [r7, #12] 800c98e: e002 b.n 800c996 } else { crc >>= 1; 800c990: 68fb ldr r3, [r7, #12] 800c992: 085b lsrs r3, r3, #1 800c994: 60fb str r3, [r7, #12] for (uint8_t bit = 0; bit < 8; bit++) { 800c996: 7a7b ldrb r3, [r7, #9] 800c998: 3301 adds r3, #1 800c99a: 727b strb r3, [r7, #9] 800c99c: 7a7b ldrb r3, [r7, #9] 800c99e: 2b07 cmp r3, #7 800c9a0: d9eb bls.n 800c97a for (uint16_t i = 0; i < length; i++) { 800c9a2: 897b ldrh r3, [r7, #10] 800c9a4: 3301 adds r3, #1 800c9a6: 817b strh r3, [r7, #10] 800c9a8: 897a ldrh r2, [r7, #10] 800c9aa: 887b ldrh r3, [r7, #2] 800c9ac: 429a cmp r2, r3 800c9ae: d3d9 bcc.n 800c964 } } } return crc ^ 0xFFFFFFFFu; 800c9b0: 68fb ldr r3, [r7, #12] 800c9b2: 43db mvns r3, r3 } 800c9b4: 4618 mov r0, r3 800c9b6: 3714 adds r7, #20 800c9b8: 46bd mov sp, r7 800c9ba: bc80 pop {r7} 800c9bc: 4770 bx lr 800c9be: bf00 nop 800c9c0: edb88320 .word 0xedb88320 0800c9c4 : static uint16_t encode_packet(const uint8_t* payload, uint16_t payload_len, uint8_t* output, uint8_t response_code) { 800c9c4: b580 push {r7, lr} 800c9c6: b088 sub sp, #32 800c9c8: af00 add r7, sp, #0 800c9ca: 60f8 str r0, [r7, #12] 800c9cc: 607a str r2, [r7, #4] 800c9ce: 461a mov r2, r3 800c9d0: 460b mov r3, r1 800c9d2: 817b strh r3, [r7, #10] 800c9d4: 4613 mov r3, r2 800c9d6: 727b strb r3, [r7, #9] uint16_t out_index = 0; 800c9d8: 2300 movs r3, #0 800c9da: 83fb strh r3, [r7, #30] output[out_index++] = response_code; 800c9dc: 8bfb ldrh r3, [r7, #30] 800c9de: 1c5a adds r2, r3, #1 800c9e0: 83fa strh r2, [r7, #30] 800c9e2: 461a mov r2, r3 800c9e4: 687b ldr r3, [r7, #4] 800c9e6: 4413 add r3, r2 800c9e8: 7a7a ldrb r2, [r7, #9] 800c9ea: 701a strb r2, [r3, #0] if (payload != NULL) { 800c9ec: 68fb ldr r3, [r7, #12] 800c9ee: 2b00 cmp r3, #0 800c9f0: d019 beq.n 800ca26 // Просто копируем полезную нагрузку без какого‑либо экранирования for (uint16_t i = 0; i < payload_len; i++) { 800c9f2: 2300 movs r3, #0 800c9f4: 83bb strh r3, [r7, #28] 800c9f6: e012 b.n 800ca1e output[out_index++] = payload[i]; 800c9f8: 8bbb ldrh r3, [r7, #28] 800c9fa: 68fa ldr r2, [r7, #12] 800c9fc: 441a add r2, r3 800c9fe: 8bfb ldrh r3, [r7, #30] 800ca00: 1c59 adds r1, r3, #1 800ca02: 83f9 strh r1, [r7, #30] 800ca04: 4619 mov r1, r3 800ca06: 687b ldr r3, [r7, #4] 800ca08: 440b add r3, r1 800ca0a: 7812 ldrb r2, [r2, #0] 800ca0c: 701a strb r2, [r3, #0] // Проверка переполнения if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800ca0e: 8bfb ldrh r3, [r7, #30] 800ca10: 2bfa cmp r3, #250 @ 0xfa 800ca12: d901 bls.n 800ca18 return 0; 800ca14: 2300 movs r3, #0 800ca16: e02a b.n 800ca6e for (uint16_t i = 0; i < payload_len; i++) { 800ca18: 8bbb ldrh r3, [r7, #28] 800ca1a: 3301 adds r3, #1 800ca1c: 83bb strh r3, [r7, #28] 800ca1e: 8bba ldrh r2, [r7, #28] 800ca20: 897b ldrh r3, [r7, #10] 800ca22: 429a cmp r2, r3 800ca24: d3e8 bcc.n 800c9f8 } } } // Вычисляем CRC для всего содержимого (код ответа + полезная нагрузка) uint32_t crc = calculate_crc32(output, out_index); 800ca26: 8bfb ldrh r3, [r7, #30] 800ca28: 4619 mov r1, r3 800ca2a: 6878 ldr r0, [r7, #4] 800ca2c: f7ff ff8e bl 800c94c 800ca30: 4603 mov r3, r0 800ca32: 613b str r3, [r7, #16] uint8_t* crc_bytes = (uint8_t*)&crc; 800ca34: f107 0310 add.w r3, r7, #16 800ca38: 617b str r3, [r7, #20] // Добавляем CRC без экранирования for (int i = 0; i < 4; i++) { 800ca3a: 2300 movs r3, #0 800ca3c: 61bb str r3, [r7, #24] 800ca3e: e012 b.n 800ca66 output[out_index++] = crc_bytes[i]; 800ca40: 69bb ldr r3, [r7, #24] 800ca42: 697a ldr r2, [r7, #20] 800ca44: 441a add r2, r3 800ca46: 8bfb ldrh r3, [r7, #30] 800ca48: 1c59 adds r1, r3, #1 800ca4a: 83f9 strh r1, [r7, #30] 800ca4c: 4619 mov r1, r3 800ca4e: 687b ldr r3, [r7, #4] 800ca50: 440b add r3, r1 800ca52: 7812 ldrb r2, [r2, #0] 800ca54: 701a strb r2, [r3, #0] if (out_index >= MAX_TX_BUFFER_SIZE - 1) { // место для END_BYTE 800ca56: 8bfb ldrh r3, [r7, #30] 800ca58: 2bfe cmp r3, #254 @ 0xfe 800ca5a: d901 bls.n 800ca60 return 0; 800ca5c: 2300 movs r3, #0 800ca5e: e006 b.n 800ca6e for (int i = 0; i < 4; i++) { 800ca60: 69bb ldr r3, [r7, #24] 800ca62: 3301 adds r3, #1 800ca64: 61bb str r3, [r7, #24] 800ca66: 69bb ldr r3, [r7, #24] 800ca68: 2b03 cmp r3, #3 800ca6a: dde9 ble.n 800ca40 } } return out_index; 800ca6c: 8bfb ldrh r3, [r7, #30] } 800ca6e: 4618 mov r0, r3 800ca70: 3720 adds r7, #32 800ca72: 46bd mov sp, r7 800ca74: bd80 pop {r7, pc} ... 0800ca78 : void SC_SendPacket(const uint8_t* payload, uint16_t payload_len, uint8_t response_code) { 800ca78: b580 push {r7, lr} 800ca7a: b084 sub sp, #16 800ca7c: af00 add r7, sp, #0 800ca7e: 6078 str r0, [r7, #4] 800ca80: 460b mov r3, r1 800ca82: 807b strh r3, [r7, #2] 800ca84: 4613 mov r3, r2 800ca86: 707b strb r3, [r7, #1] uint16_t packet_len = encode_packet(payload, payload_len, serial_control.tx_buffer, response_code); 800ca88: 787b ldrb r3, [r7, #1] 800ca8a: 8879 ldrh r1, [r7, #2] 800ca8c: 4a15 ldr r2, [pc, #84] @ (800cae4 ) 800ca8e: 6878 ldr r0, [r7, #4] 800ca90: f7ff ff98 bl 800c9c4 800ca94: 4603 mov r3, r0 800ca96: 81fb strh r3, [r7, #14] if (packet_len > 0) { 800ca98: 89fb ldrh r3, [r7, #14] 800ca9a: 2b00 cmp r3, #0 800ca9c: d01e beq.n 800cadc if (huart2.gState == HAL_UART_STATE_BUSY_TX) { 800ca9e: 4b12 ldr r3, [pc, #72] @ (800cae8 ) 800caa0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800caa4: b2db uxtb r3, r3 800caa6: 2b21 cmp r3, #33 @ 0x21 800caa8: d107 bne.n 800caba HAL_UART_Abort_IT(&huart2); 800caaa: 480f ldr r0, [pc, #60] @ (800cae8 ) 800caac: f005 fcbe bl 801242c HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 800cab0: 2200 movs r2, #0 800cab2: 2110 movs r1, #16 800cab4: 480d ldr r0, [pc, #52] @ (800caec ) 800cab6: f003 f8f2 bl 800fc9e } HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_SET); 800caba: 2201 movs r2, #1 800cabc: 2110 movs r1, #16 800cabe: 480b ldr r0, [pc, #44] @ (800caec ) 800cac0: f003 f8ed bl 800fc9e HAL_UART_Transmit_IT(&huart2, serial_control.tx_buffer, packet_len); 800cac4: 89fb ldrh r3, [r7, #14] 800cac6: 461a mov r2, r3 800cac8: 4906 ldr r1, [pc, #24] @ (800cae4 ) 800caca: 4807 ldr r0, [pc, #28] @ (800cae8 ) 800cacc: f005 fc1b bl 8012306 serial_control.tx_tick = HAL_GetTick(); 800cad0: f001 f8d4 bl 800dc7c 800cad4: 4603 mov r3, r0 800cad6: 4a03 ldr r2, [pc, #12] @ (800cae4 ) 800cad8: f8c2 3210 str.w r3, [r2, #528] @ 0x210 } } 800cadc: bf00 nop 800cade: 3710 adds r7, #16 800cae0: 46bd mov sp, r7 800cae2: bd80 pop {r7, pc} 800cae4: 20000bc0 .word 0x20000bc0 800cae8: 20001174 .word 0x20001174 800caec: 40011400 .word 0x40011400 0800caf0 : static uint8_t parse_packet(const uint8_t* packet_data, uint16_t packet_len, ReceivedCommand_t* out_cmd) { 800caf0: b580 push {r7, lr} 800caf2: b088 sub sp, #32 800caf4: af00 add r7, sp, #0 800caf6: 60f8 str r0, [r7, #12] 800caf8: 460b mov r3, r1 800cafa: 607a str r2, [r7, #4] 800cafc: 817b strh r3, [r7, #10] // }else{ // test_crc_invalid = 5; // } // Минимальный размер: 1 байт команды + 4 байта CRC if (packet_len < 5) return 0; 800cafe: 897b ldrh r3, [r7, #10] 800cb00: 2b04 cmp r3, #4 800cb02: d801 bhi.n 800cb08 800cb04: 2300 movs r3, #0 800cb06: e03f b.n 800cb88 if (packet_len > MAX_RX_BUFFER_SIZE) return 0; 800cb08: 897b ldrh r3, [r7, #10] 800cb0a: f5b3 7f80 cmp.w r3, #256 @ 0x100 800cb0e: d901 bls.n 800cb14 800cb10: 2300 movs r3, #0 800cb12: e039 b.n 800cb88 uint16_t payload_length = packet_len - 4; 800cb14: 897b ldrh r3, [r7, #10] 800cb16: 3b04 subs r3, #4 800cb18: 83fb strh r3, [r7, #30] // Извлекаем принятую CRC (последние 4 байта, little-endian) uint32_t received_checksum = ((uint32_t)packet_data[payload_length] << 0) | 800cb1a: 8bfb ldrh r3, [r7, #30] 800cb1c: 68fa ldr r2, [r7, #12] 800cb1e: 4413 add r3, r2 800cb20: 781b ldrb r3, [r3, #0] 800cb22: 4619 mov r1, r3 ((uint32_t)packet_data[payload_length + 1] << 8) | 800cb24: 8bfb ldrh r3, [r7, #30] 800cb26: 3301 adds r3, #1 800cb28: 68fa ldr r2, [r7, #12] 800cb2a: 4413 add r3, r2 800cb2c: 781b ldrb r3, [r3, #0] 800cb2e: 021b lsls r3, r3, #8 ((uint32_t)packet_data[payload_length] << 0) | 800cb30: ea41 0203 orr.w r2, r1, r3 ((uint32_t)packet_data[payload_length + 2] << 16) | 800cb34: 8bfb ldrh r3, [r7, #30] 800cb36: 3302 adds r3, #2 800cb38: 68f9 ldr r1, [r7, #12] 800cb3a: 440b add r3, r1 800cb3c: 781b ldrb r3, [r3, #0] 800cb3e: 041b lsls r3, r3, #16 ((uint32_t)packet_data[payload_length + 1] << 8) | 800cb40: 431a orrs r2, r3 ((uint32_t)packet_data[payload_length + 3] << 24); 800cb42: 8bfb ldrh r3, [r7, #30] 800cb44: 3303 adds r3, #3 800cb46: 68f9 ldr r1, [r7, #12] 800cb48: 440b add r3, r1 800cb4a: 781b ldrb r3, [r3, #0] 800cb4c: 061b lsls r3, r3, #24 uint32_t received_checksum = 800cb4e: 4313 orrs r3, r2 800cb50: 61bb str r3, [r7, #24] // Вычисляем CRC для полезной нагрузки uint32_t calculated_checksum = calculate_crc32(packet_data, payload_length); 800cb52: 8bfb ldrh r3, [r7, #30] 800cb54: 4619 mov r1, r3 800cb56: 68f8 ldr r0, [r7, #12] 800cb58: f7ff fef8 bl 800c94c 800cb5c: 6178 str r0, [r7, #20] if (received_checksum != calculated_checksum) return 0; // CRC не совпадает 800cb5e: 69ba ldr r2, [r7, #24] 800cb60: 697b ldr r3, [r7, #20] 800cb62: 429a cmp r2, r3 800cb64: d001 beq.n 800cb6a 800cb66: 2300 movs r3, #0 800cb68: e00e b.n 800cb88 out_cmd->argument = (void *)&packet_data[1]; 800cb6a: 68fb ldr r3, [r7, #12] 800cb6c: 1c5a adds r2, r3, #1 800cb6e: 687b ldr r3, [r7, #4] 800cb70: 605a str r2, [r3, #4] out_cmd->command = packet_data[0]; 800cb72: 68fb ldr r3, [r7, #12] 800cb74: 781a ldrb r2, [r3, #0] 800cb76: 687b ldr r3, [r7, #4] 800cb78: 701a strb r2, [r3, #0] out_cmd->argument_length = (uint8_t)(payload_length - 1); 800cb7a: 8bfb ldrh r3, [r7, #30] 800cb7c: b2db uxtb r3, r3 800cb7e: 3b01 subs r3, #1 800cb80: b2da uxtb r2, r3 800cb82: 687b ldr r3, [r7, #4] 800cb84: 705a strb r2, [r3, #1] return 1; 800cb86: 2301 movs r3, #1 } 800cb88: 4618 mov r0, r3 800cb8a: 3720 adds r7, #32 800cb8c: 46bd mov sp, r7 800cb8e: bd80 pop {r7, pc} 0800cb90 : static uint8_t process_received_packet(SerialControl_t *ctx, const uint8_t* packet_data, uint16_t packet_len) { 800cb90: b580 push {r7, lr} 800cb92: b084 sub sp, #16 800cb94: af00 add r7, sp, #0 800cb96: 60f8 str r0, [r7, #12] 800cb98: 60b9 str r1, [r7, #8] 800cb9a: 4613 mov r3, r2 800cb9c: 80fb strh r3, [r7, #6] if (!parse_packet(packet_data, packet_len, (ReceivedCommand_t *)&ctx->received_command)) { 800cb9e: 68fb ldr r3, [r7, #12] 800cba0: f503 7200 add.w r2, r3, #512 @ 0x200 800cba4: 88fb ldrh r3, [r7, #6] 800cba6: 4619 mov r1, r3 800cba8: 68b8 ldr r0, [r7, #8] 800cbaa: f7ff ffa1 bl 800caf0 800cbae: 4603 mov r3, r0 800cbb0: 2b00 cmp r3, #0 800cbb2: d101 bne.n 800cbb8 return 0; 800cbb4: 2300 movs r3, #0 800cbb6: e004 b.n 800cbc2 } ctx->command_ready = 1; 800cbb8: 68fb ldr r3, [r7, #12] 800cbba: 2201 movs r2, #1 800cbbc: f883 2208 strb.w r2, [r3, #520] @ 0x208 return 1; 800cbc0: 2301 movs r3, #1 } 800cbc2: 4618 mov r0, r3 800cbc4: 3710 adds r7, #16 800cbc6: 46bd mov sp, r7 800cbc8: bd80 pop {r7, pc} ... 0800cbcc <__NVIC_SystemReset>: { 800cbcc: b480 push {r7} 800cbce: af00 add r7, sp, #0 __ASM volatile ("dsb 0xF":::"memory"); 800cbd0: f3bf 8f4f dsb sy } 800cbd4: bf00 nop (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800cbd6: 4b06 ldr r3, [pc, #24] @ (800cbf0 <__NVIC_SystemReset+0x24>) 800cbd8: 68db ldr r3, [r3, #12] 800cbda: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800cbde: 4904 ldr r1, [pc, #16] @ (800cbf0 <__NVIC_SystemReset+0x24>) 800cbe0: 4b04 ldr r3, [pc, #16] @ (800cbf4 <__NVIC_SystemReset+0x28>) 800cbe2: 4313 orrs r3, r2 800cbe4: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800cbe6: f3bf 8f4f dsb sy } 800cbea: bf00 nop __NOP(); 800cbec: bf00 nop 800cbee: e7fd b.n 800cbec <__NVIC_SystemReset+0x20> 800cbf0: e000ed00 .word 0xe000ed00 800cbf4: 05fa0004 .word 0x05fa0004 0800cbf8 : .chargerNumber = 00001, .unixTime = 1721651966, }; // Единая функция-обработчик всех команд со switch-case void SC_CommandHandler(ReceivedCommand_t* cmd) { 800cbf8: b580 push {r7, lr} 800cbfa: b084 sub sp, #16 800cbfc: af00 add r7, sp, #0 800cbfe: 6078 str r0, [r7, #4] uint8_t response_code = RESP_FAILED; 800cc00: 2313 movs r3, #19 800cc02: 73fb strb r3, [r7, #15] switch (cmd->command) { 800cc04: 687b ldr r3, [r7, #4] 800cc06: 781b ldrb r3, [r3, #0] 800cc08: 2bc2 cmp r3, #194 @ 0xc2 800cc0a: f300 80cc bgt.w 800cda6 800cc0e: 2bb0 cmp r3, #176 @ 0xb0 800cc10: da0f bge.n 800cc32 800cc12: 2b60 cmp r3, #96 @ 0x60 800cc14: d042 beq.n 800cc9c 800cc16: 2b60 cmp r3, #96 @ 0x60 800cc18: f300 80c5 bgt.w 800cda6 800cc1c: 2b50 cmp r3, #80 @ 0x50 800cc1e: d043 beq.n 800cca8 800cc20: 2b50 cmp r3, #80 @ 0x50 800cc22: f300 80c0 bgt.w 800cda6 800cc26: 2b01 cmp r3, #1 800cc28: f000 80a6 beq.w 800cd78 800cc2c: 2b40 cmp r3, #64 @ 0x40 800cc2e: d02d beq.n 800cc8c 800cc30: e0b9 b.n 800cda6 800cc32: 3bb0 subs r3, #176 @ 0xb0 800cc34: 2b12 cmp r3, #18 800cc36: f200 80b6 bhi.w 800cda6 800cc3a: a201 add r2, pc, #4 @ (adr r2, 800cc40 ) 800cc3c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800cc40: 0800ccaf .word 0x0800ccaf 800cc44: 0800cda7 .word 0x0800cda7 800cc48: 0800cda7 .word 0x0800cda7 800cc4c: 0800cda7 .word 0x0800cda7 800cc50: 0800cda7 .word 0x0800cda7 800cc54: 0800cd57 .word 0x0800cd57 800cc58: 0800cda7 .word 0x0800cda7 800cc5c: 0800cda7 .word 0x0800cda7 800cc60: 0800cda7 .word 0x0800cda7 800cc64: 0800cda7 .word 0x0800cda7 800cc68: 0800cda7 .word 0x0800cda7 800cc6c: 0800cda7 .word 0x0800cda7 800cc70: 0800cda7 .word 0x0800cda7 800cc74: 0800cda7 .word 0x0800cda7 800cc78: 0800cda7 .word 0x0800cda7 800cc7c: 0800cda7 .word 0x0800cda7 800cc80: 0800cced .word 0x0800cced 800cc84: 0800cd51 .word 0x0800cd51 800cc88: 0800cd25 .word 0x0800cd25 // Команды БЕЗ аргументов case CMD_GET_STATUS: // Логика получения информации monitoring_data_callback(); 800cc8c: f000 f8b2 bl 800cdf4 // Отправляем с нормальным приоритетом SC_SendPacket((uint8_t*)&statusPacket, sizeof(statusPacket), CMD_GET_STATUS); 800cc90: 2240 movs r2, #64 @ 0x40 800cc92: 2158 movs r1, #88 @ 0x58 800cc94: 484b ldr r0, [pc, #300] @ (800cdc4 ) 800cc96: f7ff feef bl 800ca78 return; // Специальный ответ уже отправлен 800cc9a: e08f b.n 800cdbc case CMD_GET_INFO: SC_SendPacket((uint8_t*)&infoPacket, sizeof(infoPacket), CMD_GET_INFO); 800cc9c: 2260 movs r2, #96 @ 0x60 800cc9e: 210a movs r1, #10 800cca0: 4849 ldr r0, [pc, #292] @ (800cdc8 ) 800cca2: f7ff fee9 bl 800ca78 return; 800cca6: e089 b.n 800cdbc case CMD_GET_LOG: debug_buffer_send(); 800cca8: f7fd fb28 bl 800a2fc return; // Ответ формируется внутри debug_buffer_send 800ccac: e086 b.n 800cdbc // Команды С аргументами case CMD_SET_CONFIG: if (cmd->argument_length == sizeof(ConfigBlock_t)) { 800ccae: 687b ldr r3, [r7, #4] 800ccb0: 785b ldrb r3, [r3, #1] 800ccb2: 2b0b cmp r3, #11 800ccb4: d117 bne.n 800cce6 memcpy(&config, cmd->argument, sizeof(ConfigBlock_t)); 800ccb6: 687b ldr r3, [r7, #4] 800ccb8: 685a ldr r2, [r3, #4] 800ccba: 4b44 ldr r3, [pc, #272] @ (800cdcc ) 800ccbc: 6810 ldr r0, [r2, #0] 800ccbe: 6851 ldr r1, [r2, #4] 800ccc0: c303 stmia r3!, {r0, r1} 800ccc2: 8911 ldrh r1, [r2, #8] 800ccc4: 7a92 ldrb r2, [r2, #10] 800ccc6: 8019 strh r1, [r3, #0] 800ccc8: 709a strb r2, [r3, #2] config_initialized = 1; 800ccca: 4b41 ldr r3, [pc, #260] @ (800cdd0 ) 800cccc: 2201 movs r2, #1 800ccce: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Set Config: %s %d\n", config.location, config.chargerNumber); 800ccd0: 4b3e ldr r3, [pc, #248] @ (800cdcc ) 800ccd2: f8d3 3003 ldr.w r3, [r3, #3] 800ccd6: 4a3d ldr r2, [pc, #244] @ (800cdcc ) 800ccd8: 493e ldr r1, [pc, #248] @ (800cdd4 ) 800ccda: 2007 movs r0, #7 800ccdc: f7fd fb70 bl 800a3c0 response_code = RESP_SUCCESS; 800cce0: 2312 movs r3, #18 800cce2: 73fb strb r3, [r7, #15] break; 800cce4: e062 b.n 800cdac } response_code = RESP_FAILED; 800cce6: 2313 movs r3, #19 800cce8: 73fb strb r3, [r7, #15] break; 800ccea: e05f b.n 800cdac case CMD_SET_POWER_LIMIT: if (cmd->argument_length == 1) { 800ccec: 687b ldr r3, [r7, #4] 800ccee: 785b ldrb r3, [r3, #1] 800ccf0: 2b01 cmp r3, #1 800ccf2: d114 bne.n 800cd1e PSU0.power_limit = ((uint8_t*)cmd->argument)[0] * 1000; 800ccf4: 687b ldr r3, [r7, #4] 800ccf6: 685b ldr r3, [r3, #4] 800ccf8: 781b ldrb r3, [r3, #0] 800ccfa: 461a mov r2, r3 800ccfc: f44f 737a mov.w r3, #1000 @ 0x3e8 800cd00: fb02 f303 mul.w r3, r2, r3 800cd04: 461a mov r2, r3 800cd06: 4b34 ldr r3, [pc, #208] @ (800cdd8 ) 800cd08: 615a str r2, [r3, #20] log_printf(LOG_INFO, "Power limit: %d\n", PSU0.power_limit); 800cd0a: 4b33 ldr r3, [pc, #204] @ (800cdd8 ) 800cd0c: 695b ldr r3, [r3, #20] 800cd0e: 461a mov r2, r3 800cd10: 4932 ldr r1, [pc, #200] @ (800cddc ) 800cd12: 2007 movs r0, #7 800cd14: f7fd fb54 bl 800a3c0 //CONN.connState = (((uint8_t*)cmd->argument)[0])/4; response_code = RESP_SUCCESS; 800cd18: 2312 movs r3, #18 800cd1a: 73fb strb r3, [r7, #15] break; 800cd1c: e046 b.n 800cdac } response_code = RESP_FAILED; 800cd1e: 2313 movs r3, #19 800cd20: 73fb strb r3, [r7, #15] break; 800cd22: e043 b.n 800cdac case CMD_CHARGE_PERMIT: if (cmd->argument_length == 1) { 800cd24: 687b ldr r3, [r7, #4] 800cd26: 785b ldrb r3, [r3, #1] 800cd28: 2b01 cmp r3, #1 800cd2a: d10e bne.n 800cd4a CONN.connControl = ((uint8_t*)cmd->argument)[0]; 800cd2c: 687b ldr r3, [r7, #4] 800cd2e: 685b ldr r3, [r3, #4] 800cd30: 781a ldrb r2, [r3, #0] 800cd32: 4b2b ldr r3, [pc, #172] @ (800cde0 ) 800cd34: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Charge permit: %d\n", CONN.connControl); 800cd36: 4b2a ldr r3, [pc, #168] @ (800cde0 ) 800cd38: 781b ldrb r3, [r3, #0] 800cd3a: 461a mov r2, r3 800cd3c: 4929 ldr r1, [pc, #164] @ (800cde4 ) 800cd3e: 2007 movs r0, #7 800cd40: f7fd fb3e bl 800a3c0 response_code = RESP_SUCCESS; 800cd44: 2312 movs r3, #18 800cd46: 73fb strb r3, [r7, #15] break; 800cd48: e030 b.n 800cdac } response_code = RESP_FAILED; 800cd4a: 2313 movs r3, #19 800cd4c: 73fb strb r3, [r7, #15] break; 800cd4e: e02d b.n 800cdac // memcpy(&PSU_TestMode, cmd->argument, sizeof(PSU_TestMode_t)); // log_printf(LOG_INFO, "Test PSU: %d %d %d\n", PSU_TestMode.enable, PSU_TestMode.voltage, PSU_TestMode.current); // response_code = RESP_SUCCESS; // break; // } response_code = RESP_FAILED; 800cd50: 2313 movs r3, #19 800cd52: 73fb strb r3, [r7, #15] break; 800cd54: e02a b.n 800cdac case CMD_DEVICE_RESET: // 2. Отправляем SUCCESS (хост может успеть получить его перед ребутом) SC_SendPacket(NULL, 0, RESP_SUCCESS); 800cd56: 2212 movs r2, #18 800cd58: 2100 movs r1, #0 800cd5a: 2000 movs r0, #0 800cd5c: f7ff fe8c bl 800ca78 while(huart2.gState == HAL_UART_STATE_BUSY_TX); // Ожидание завершения передачи 800cd60: bf00 nop 800cd62: 4b21 ldr r3, [pc, #132] @ (800cde8 ) 800cd64: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800cd68: b2db uxtb r3, r3 800cd6a: 2b21 cmp r3, #33 @ 0x21 800cd6c: d0f9 beq.n 800cd62 HAL_Delay(10); 800cd6e: 200a movs r0, #10 800cd70: f000 ff8e bl 800dc90 // 3. Выполняем программный сброс NVIC_SystemReset(); 800cd74: f7ff ff2a bl 800cbcc <__NVIC_SystemReset> return; // Сюда код уже не дойдет, но для компилятора нxужно case CMD_ISOLATION_STATUS: if (cmd->argument_length == sizeof(IsolationStatusPacket_t)) { 800cd78: 687b ldr r3, [r7, #4] 800cd7a: 785b ldrb r3, [r3, #1] 800cd7c: 2b09 cmp r3, #9 800cd7e: d10f bne.n 800cda0 memcpy(&ISO, cmd->argument, sizeof(IsolationStatusPacket_t)); 800cd80: 687b ldr r3, [r7, #4] 800cd82: 685a ldr r2, [r3, #4] 800cd84: 4b19 ldr r3, [pc, #100] @ (800cdec ) 800cd86: 6810 ldr r0, [r2, #0] 800cd88: 6851 ldr r1, [r2, #4] 800cd8a: c303 stmia r3!, {r0, r1} 800cd8c: 7a12 ldrb r2, [r2, #8] 800cd8e: 701a strb r2, [r3, #0] // Для однонаправленного UART5 ответ не нужен if (g_sc_command_source == SC_SOURCE_UART5) { 800cd90: 4b17 ldr r3, [pc, #92] @ (800cdf0 ) 800cd92: 781b ldrb r3, [r3, #0] 800cd94: b2db uxtb r3, r3 800cd96: 2b01 cmp r3, #1 800cd98: d00f beq.n 800cdba return; } response_code = RESP_SUCCESS; 800cd9a: 2312 movs r3, #18 800cd9c: 73fb strb r3, [r7, #15] break; 800cd9e: e005 b.n 800cdac } response_code = RESP_FAILED; 800cda0: 2313 movs r3, #19 800cda2: 73fb strb r3, [r7, #15] break; 800cda4: e002 b.n 800cdac default: // Неизвестная команда response_code = RESP_FAILED; 800cda6: 2313 movs r3, #19 800cda8: 73fb strb r3, [r7, #15] break; 800cdaa: bf00 nop } // Отправляем финальный ответ (для команд без собственного ответа) SC_SendPacket(NULL, 0, response_code); 800cdac: 7bfb ldrb r3, [r7, #15] 800cdae: 461a mov r2, r3 800cdb0: 2100 movs r1, #0 800cdb2: 2000 movs r0, #0 800cdb4: f7ff fe60 bl 800ca78 800cdb8: e000 b.n 800cdbc return; 800cdba: bf00 nop } 800cdbc: 3710 adds r7, #16 800cdbe: 46bd mov sp, r7 800cdc0: bd80 pop {r7, pc} 800cdc2: bf00 nop 800cdc4: 20000fec .word 0x20000fec 800cdc8: 20001044 .word 0x20001044 800cdcc: 20000074 .word 0x20000074 800cdd0: 2000104e .word 0x2000104e 800cdd4: 08016348 .word 0x08016348 800cdd8: 200008a4 .word 0x200008a4 800cddc: 0801635c .word 0x0801635c 800cde0: 20000354 .word 0x20000354 800cde4: 08016370 .word 0x08016370 800cde8: 20001174 .word 0x20001174 800cdec: 20000068 .word 0x20000068 800cdf0: 20000fe8 .word 0x20000fe8 0800cdf4 : // Колбэк для заполнения данных мониторинга void monitoring_data_callback() { 800cdf4: b580 push {r7, lr} 800cdf6: af00 add r7, sp, #0 // Информация о зарядной сессии statusPacket.SOC = CONN.SOC; 800cdf8: 4b8f ldr r3, [pc, #572] @ (800d038 ) 800cdfa: 789a ldrb r2, [r3, #2] 800cdfc: 4b8f ldr r3, [pc, #572] @ (800d03c ) 800cdfe: 709a strb r2, [r3, #2] statusPacket.Energy = CONN.Energy; 800ce00: 4b8d ldr r3, [pc, #564] @ (800d038 ) 800ce02: f8d3 3007 ldr.w r3, [r3, #7] 800ce06: 4a8d ldr r2, [pc, #564] @ (800d03c ) 800ce08: f8c2 3003 str.w r3, [r2, #3] statusPacket.RequestedVoltage = CONN.RequestedVoltage; 800ce0c: 4b8a ldr r3, [pc, #552] @ (800d038 ) 800ce0e: f8b3 300f ldrh.w r3, [r3, #15] 800ce12: b29a uxth r2, r3 800ce14: 4b89 ldr r3, [pc, #548] @ (800d03c ) 800ce16: f8a3 2007 strh.w r2, [r3, #7] statusPacket.RequestedCurrent = CONN.WantedCurrent; 800ce1a: 4b87 ldr r3, [pc, #540] @ (800d038 ) 800ce1c: f8b3 301b ldrh.w r3, [r3, #27] 800ce20: b29a uxth r2, r3 800ce22: 4b86 ldr r3, [pc, #536] @ (800d03c ) 800ce24: f8a3 2009 strh.w r2, [r3, #9] statusPacket.MeasuredVoltage = CONN.MeasuredVoltage; 800ce28: 4b83 ldr r3, [pc, #524] @ (800d038 ) 800ce2a: f8b3 3013 ldrh.w r3, [r3, #19] 800ce2e: b29a uxth r2, r3 800ce30: 4b82 ldr r3, [pc, #520] @ (800d03c ) 800ce32: f8a3 200b strh.w r2, [r3, #11] statusPacket.MeasuredCurrent = CONN.MeasuredCurrent; 800ce36: 4b80 ldr r3, [pc, #512] @ (800d038 ) 800ce38: f8b3 3015 ldrh.w r3, [r3, #21] 800ce3c: b29a uxth r2, r3 800ce3e: 4b7f ldr r3, [pc, #508] @ (800d03c ) 800ce40: f8a3 200d strh.w r2, [r3, #13] statusPacket.outputEnabled = CONN.outputEnabled; 800ce44: 4b7c ldr r3, [pc, #496] @ (800d038 ) 800ce46: 7e1a ldrb r2, [r3, #24] 800ce48: 4b7c ldr r3, [pc, #496] @ (800d03c ) 800ce4a: 73da strb r2, [r3, #15] statusPacket.chargingError = CONN.chargingError; 800ce4c: 4b7a ldr r3, [pc, #488] @ (800d038 ) 800ce4e: 7f5a ldrb r2, [r3, #29] 800ce50: 4b7a ldr r3, [pc, #488] @ (800d03c ) 800ce52: 705a strb r2, [r3, #1] statusPacket.connState = CONN.connState; 800ce54: 4b78 ldr r3, [pc, #480] @ (800d038 ) 800ce56: 785a ldrb r2, [r3, #1] 800ce58: 4b78 ldr r3, [pc, #480] @ (800d03c ) 800ce5a: 701a strb r2, [r3, #0] statusPacket.chargingElapsedTimeMin = 0; 800ce5c: 4b77 ldr r3, [pc, #476] @ (800d03c ) 800ce5e: 2200 movs r2, #0 800ce60: 741a strb r2, [r3, #16] 800ce62: 2200 movs r2, #0 800ce64: 745a strb r2, [r3, #17] statusPacket.chargingElapsedTimeSec = 0; 800ce66: 4b75 ldr r3, [pc, #468] @ (800d03c ) 800ce68: 2200 movs r2, #0 800ce6a: 749a strb r2, [r3, #18] statusPacket.estimatedRemainingChargingTime = 0; 800ce6c: 4b73 ldr r3, [pc, #460] @ (800d03c ) 800ce6e: 2200 movs r2, #0 800ce70: 74da strb r2, [r3, #19] 800ce72: 2200 movs r2, #0 800ce74: 751a strb r2, [r3, #20] // состояние зарядной станции statusPacket.relayAC = RELAY_Read(RELAY_AC); 800ce76: 2004 movs r0, #4 800ce78: f7fc fc58 bl 800972c 800ce7c: 4603 mov r3, r0 800ce7e: f003 0301 and.w r3, r3, #1 800ce82: b2d9 uxtb r1, r3 800ce84: 4a6d ldr r2, [pc, #436] @ (800d03c ) 800ce86: 7d53 ldrb r3, [r2, #21] 800ce88: f361 0300 bfi r3, r1, #0, #1 800ce8c: 7553 strb r3, [r2, #21] statusPacket.relayDC = RELAY_Read(RELAY_DC); 800ce8e: 2003 movs r0, #3 800ce90: f7fc fc4c bl 800972c 800ce94: 4603 mov r3, r0 800ce96: f003 0301 and.w r3, r3, #1 800ce9a: b2d9 uxtb r1, r3 800ce9c: 4a67 ldr r2, [pc, #412] @ (800d03c ) 800ce9e: 7d53 ldrb r3, [r2, #21] 800cea0: f361 0341 bfi r3, r1, #1, #1 800cea4: 7553 strb r3, [r2, #21] statusPacket.relayAUX = RELAY_Read(RELAY_AUX0); 800cea6: 2000 movs r0, #0 800cea8: f7fc fc40 bl 800972c 800ceac: 4603 mov r3, r0 800ceae: f003 0301 and.w r3, r3, #1 800ceb2: b2d9 uxtb r1, r3 800ceb4: 4a61 ldr r2, [pc, #388] @ (800d03c ) 800ceb6: 7d53 ldrb r3, [r2, #21] 800ceb8: f361 0382 bfi r3, r1, #2, #1 800cebc: 7553 strb r3, [r2, #21] statusPacket.lockState = 0; 800cebe: 4a5f ldr r2, [pc, #380] @ (800d03c ) 800cec0: 7d53 ldrb r3, [r2, #21] 800cec2: f023 0308 bic.w r3, r3, #8 800cec6: 7553 strb r3, [r2, #21] statusPacket.stopButton = !IN_ReadInput(IN_ESTOP); 800cec8: 2003 movs r0, #3 800ceca: f7fc fc3f bl 800974c 800cece: 4603 mov r3, r0 800ced0: 2b00 cmp r3, #0 800ced2: bf0c ite eq 800ced4: 2301 moveq r3, #1 800ced6: 2300 movne r3, #0 800ced8: b2d9 uxtb r1, r3 800ceda: 4a58 ldr r2, [pc, #352] @ (800d03c ) 800cedc: 7d53 ldrb r3, [r2, #21] 800cede: f361 1304 bfi r3, r1, #4, #1 800cee2: 7553 strb r3, [r2, #21] statusPacket.logAvailable = (debug_buffer_available()>0)?1:0; 800cee4: f7fd f9f6 bl 800a2d4 800cee8: 4603 mov r3, r0 800ceea: 2b00 cmp r3, #0 800ceec: bf14 ite ne 800ceee: 2301 movne r3, #1 800cef0: 2300 moveq r3, #0 800cef2: b2d9 uxtb r1, r3 800cef4: 4a51 ldr r2, [pc, #324] @ (800d03c ) 800cef6: 7d53 ldrb r3, [r2, #21] 800cef8: f361 1345 bfi r3, r1, #5, #1 800cefc: 7553 strb r3, [r2, #21] statusPacket.evInfoAvailable = 0; 800cefe: 4a4f ldr r2, [pc, #316] @ (800d03c ) 800cf00: 7d53 ldrb r3, [r2, #21] 800cf02: f023 0340 bic.w r3, r3, #64 @ 0x40 800cf06: 7553 strb r3, [r2, #21] statusPacket.psuOnline = PSU0.online; 800cf08: 4b4d ldr r3, [pc, #308] @ (800d040 ) 800cf0a: 7a1b ldrb r3, [r3, #8] 800cf0c: f003 0301 and.w r3, r3, #1 800cf10: b2d9 uxtb r1, r3 800cf12: 4a4a ldr r2, [pc, #296] @ (800d03c ) 800cf14: 7d53 ldrb r3, [r2, #21] 800cf16: f361 13c7 bfi r3, r1, #7, #1 800cf1a: 7553 strb r3, [r2, #21] statusPacket.tempConnector0 = CONN_ReadTemp(0); // температура коннектора 800cf1c: 2000 movs r0, #0 800cf1e: f7fc fd09 bl 8009934 800cf22: 4603 mov r3, r0 800cf24: b25a sxtb r2, r3 800cf26: 4b45 ldr r3, [pc, #276] @ (800d03c ) 800cf28: 765a strb r2, [r3, #25] statusPacket.tempConnector1 = CONN_ReadTemp(1); 800cf2a: 2001 movs r0, #1 800cf2c: f7fc fd02 bl 8009934 800cf30: 4603 mov r3, r0 800cf32: b25a sxtb r2, r3 800cf34: 4b41 ldr r3, [pc, #260] @ (800d03c ) 800cf36: 769a strb r2, [r3, #26] statusPacket.tempAmbient = PSU0.tempAmbient; // температура окружающего воздуха 800cf38: 4b41 ldr r3, [pc, #260] @ (800d040 ) 800cf3a: 6a1b ldr r3, [r3, #32] 800cf3c: b25a sxtb r2, r3 800cf3e: 4b3f ldr r3, [pc, #252] @ (800d03c ) 800cf40: 76da strb r2, [r3, #27] statusPacket.tempBatteryMax = 0; 800cf42: 4b3e ldr r3, [pc, #248] @ (800d03c ) 800cf44: 2200 movs r2, #0 800cf46: 771a strb r2, [r3, #28] statusPacket.tempBatteryMin = 0; 800cf48: 4b3c ldr r3, [pc, #240] @ (800d03c ) 800cf4a: 2200 movs r2, #0 800cf4c: 775a strb r2, [r3, #29] statusPacket.highestVoltageOfBatteryCell = 0; 800cf4e: 4b3b ldr r3, [pc, #236] @ (800d03c ) 800cf50: 2200 movs r2, #0 800cf52: 779a strb r2, [r3, #30] 800cf54: 2200 movs r2, #0 800cf56: 77da strb r2, [r3, #31] statusPacket.batteryStatus = 0; 800cf58: 4b38 ldr r3, [pc, #224] @ (800d03c ) 800cf5a: 2200 movs r2, #0 800cf5c: f883 2020 strb.w r2, [r3, #32] statusPacket.phaseVoltageAB = PSU_06.VAB; 800cf60: 4b38 ldr r3, [pc, #224] @ (800d044 ) 800cf62: 689b ldr r3, [r3, #8] 800cf64: b29a uxth r2, r3 800cf66: 4b35 ldr r3, [pc, #212] @ (800d03c ) 800cf68: f8a3 2021 strh.w r2, [r3, #33] @ 0x21 statusPacket.phaseVoltageBC = PSU_06.VBC; 800cf6c: 4b35 ldr r3, [pc, #212] @ (800d044 ) 800cf6e: 68db ldr r3, [r3, #12] 800cf70: b29a uxth r2, r3 800cf72: 4b32 ldr r3, [pc, #200] @ (800d03c ) 800cf74: f8a3 2023 strh.w r2, [r3, #35] @ 0x23 statusPacket.phaseVoltageCA = PSU_06.VCA; 800cf78: 4b32 ldr r3, [pc, #200] @ (800d044 ) 800cf7a: 691b ldr r3, [r3, #16] 800cf7c: b29a uxth r2, r3 800cf7e: 4b2f ldr r3, [pc, #188] @ (800d03c ) 800cf80: f8a3 2025 strh.w r2, [r3, #37] @ 0x25 // GBT TODO memset(statusPacket.VIN, 0, sizeof(statusPacket.VIN)); 800cf84: 2211 movs r2, #17 800cf86: 2100 movs r1, #0 800cf88: 482f ldr r0, [pc, #188] @ (800d048 ) 800cf8a: f006 fe97 bl 8013cbc // GBT TODO statusPacket.batteryType = 0; 800cf8e: 4b2b ldr r3, [pc, #172] @ (800d03c ) 800cf90: 2200 movs r2, #0 800cf92: f883 2038 strb.w r2, [r3, #56] @ 0x38 statusPacket.batteryCapacity = 0; 800cf96: 4b29 ldr r3, [pc, #164] @ (800d03c ) 800cf98: 2200 movs r2, #0 800cf9a: f883 2039 strb.w r2, [r3, #57] @ 0x39 800cf9e: 2200 movs r2, #0 800cfa0: f883 203a strb.w r2, [r3, #58] @ 0x3a statusPacket.batteryVoltage = 0; 800cfa4: 4b25 ldr r3, [pc, #148] @ (800d03c ) 800cfa6: 2200 movs r2, #0 800cfa8: f883 203b strb.w r2, [r3, #59] @ 0x3b 800cfac: 2200 movs r2, #0 800cfae: f883 203c strb.w r2, [r3, #60] @ 0x3c memset(statusPacket.batteryVendor, 0, sizeof(statusPacket.batteryVendor)); 800cfb2: 2204 movs r2, #4 800cfb4: 2100 movs r1, #0 800cfb6: 4825 ldr r0, [pc, #148] @ (800d04c ) 800cfb8: f006 fe80 bl 8013cbc statusPacket.batterySN = 0; 800cfbc: 4b1f ldr r3, [pc, #124] @ (800d03c ) 800cfbe: 2200 movs r2, #0 800cfc0: f883 2041 strb.w r2, [r3, #65] @ 0x41 800cfc4: 2200 movs r2, #0 800cfc6: f883 2042 strb.w r2, [r3, #66] @ 0x42 800cfca: 2200 movs r2, #0 800cfcc: f883 2043 strb.w r2, [r3, #67] @ 0x43 800cfd0: 2200 movs r2, #0 800cfd2: f883 2044 strb.w r2, [r3, #68] @ 0x44 statusPacket.batteryManuD = 0; 800cfd6: 4b19 ldr r3, [pc, #100] @ (800d03c ) 800cfd8: 2200 movs r2, #0 800cfda: f883 2047 strb.w r2, [r3, #71] @ 0x47 statusPacket.batteryManuM = 0; 800cfde: 4b17 ldr r3, [pc, #92] @ (800d03c ) 800cfe0: 2200 movs r2, #0 800cfe2: f883 2046 strb.w r2, [r3, #70] @ 0x46 statusPacket.batteryManuY = 0; 800cfe6: 4b15 ldr r3, [pc, #84] @ (800d03c ) 800cfe8: 2200 movs r2, #0 800cfea: f883 2045 strb.w r2, [r3, #69] @ 0x45 statusPacket.batteryCycleCount = 0; 800cfee: 4b13 ldr r3, [pc, #76] @ (800d03c ) 800cff0: 2200 movs r2, #0 800cff2: f883 2048 strb.w r2, [r3, #72] @ 0x48 800cff6: 2200 movs r2, #0 800cff8: f883 2049 strb.w r2, [r3, #73] @ 0x49 statusPacket.ownAuto = 0; 800cffc: 4b0f ldr r3, [pc, #60] @ (800d03c ) 800cffe: 2200 movs r2, #0 800d000: f883 204a strb.w r2, [r3, #74] @ 0x4a memset(statusPacket.EV_SW_VER, 0, sizeof(statusPacket.EV_SW_VER)); 800d004: 2208 movs r2, #8 800d006: 2100 movs r1, #0 800d008: 4811 ldr r0, [pc, #68] @ (800d050 ) 800d00a: f006 fe57 bl 8013cbc statusPacket.testMode = 0; 800d00e: 4b0b ldr r3, [pc, #44] @ (800d03c ) 800d010: 2200 movs r2, #0 800d012: f883 2053 strb.w r2, [r3, #83] @ 0x53 statusPacket.testVoltage = 0; 800d016: 4b09 ldr r3, [pc, #36] @ (800d03c ) 800d018: 2200 movs r2, #0 800d01a: f883 2054 strb.w r2, [r3, #84] @ 0x54 800d01e: 2200 movs r2, #0 800d020: f883 2055 strb.w r2, [r3, #85] @ 0x55 statusPacket.testCurrent = 0; 800d024: 4b05 ldr r3, [pc, #20] @ (800d03c ) 800d026: 2200 movs r2, #0 800d028: f883 2056 strb.w r2, [r3, #86] @ 0x56 800d02c: 2200 movs r2, #0 800d02e: f883 2057 strb.w r2, [r3, #87] @ 0x57 // В debug.c есть CONN_SetState, предполагаем наличие CONN_GetState() // Если такой функции нет, закомментируйте следующую строку: // statusPacket.connState = CONN_GetState(); } 800d032: bf00 nop 800d034: bd80 pop {r7, pc} 800d036: bf00 nop 800d038: 20000354 .word 0x20000354 800d03c: 20000fec .word 0x20000fec 800d040: 200008a4 .word 0x200008a4 800d044: 20000878 .word 0x20000878 800d048: 20001013 .word 0x20001013 800d04c: 20001029 .word 0x20001029 800d050: 20001037 .word 0x20001037 0800d054 : #include "sma_filter.h" void SMAFilter_Init(SMAFilter_t* f) { 800d054: b480 push {r7} 800d056: b085 sub sp, #20 800d058: af00 add r7, sp, #0 800d05a: 6078 str r0, [r7, #4] if (f == 0) return; 800d05c: 687b ldr r3, [r7, #4] 800d05e: 2b00 cmp r3, #0 800d060: d018 beq.n 800d094 f->sum = 0; 800d062: 687b ldr r3, [r7, #4] 800d064: 2200 movs r2, #0 800d066: 601a str r2, [r3, #0] f->idx = 0; 800d068: 687b ldr r3, [r7, #4] 800d06a: 2200 movs r2, #0 800d06c: 809a strh r2, [r3, #4] f->count = 0; 800d06e: 687b ldr r3, [r7, #4] 800d070: 2200 movs r2, #0 800d072: 80da strh r2, [r3, #6] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800d074: 2300 movs r3, #0 800d076: 81fb strh r3, [r7, #14] 800d078: e008 b.n 800d08c f->buffer[i] = 0; 800d07a: 89fa ldrh r2, [r7, #14] 800d07c: 687b ldr r3, [r7, #4] 800d07e: 3202 adds r2, #2 800d080: 2100 movs r1, #0 800d082: f843 1022 str.w r1, [r3, r2, lsl #2] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800d086: 89fb ldrh r3, [r7, #14] 800d088: 3301 adds r3, #1 800d08a: 81fb strh r3, [r7, #14] 800d08c: 89fb ldrh r3, [r7, #14] 800d08e: 2b07 cmp r3, #7 800d090: d9f3 bls.n 800d07a 800d092: e000 b.n 800d096 if (f == 0) return; 800d094: bf00 nop } } 800d096: 3714 adds r7, #20 800d098: 46bd mov sp, r7 800d09a: bc80 pop {r7} 800d09c: 4770 bx lr 0800d09e : int32_t SMAFilter_Update(SMAFilter_t* f, int32_t x) { 800d09e: b480 push {r7} 800d0a0: b085 sub sp, #20 800d0a2: af00 add r7, sp, #0 800d0a4: 6078 str r0, [r7, #4] 800d0a6: 6039 str r1, [r7, #0] if (f == 0) return x; 800d0a8: 687b ldr r3, [r7, #4] 800d0aa: 2b00 cmp r3, #0 800d0ac: d101 bne.n 800d0b2 800d0ae: 683b ldr r3, [r7, #0] 800d0b0: e056 b.n 800d160 // Пока окно не заполнено полностью, делим по фактическому count. if (f->count < SMA_FILTER_WINDOW) { 800d0b2: 687b ldr r3, [r7, #4] 800d0b4: 88db ldrh r3, [r3, #6] 800d0b6: 2b07 cmp r3, #7 800d0b8: d827 bhi.n 800d10a f->buffer[f->idx] = x; 800d0ba: 687b ldr r3, [r7, #4] 800d0bc: 889b ldrh r3, [r3, #4] 800d0be: 461a mov r2, r3 800d0c0: 687b ldr r3, [r7, #4] 800d0c2: 3202 adds r2, #2 800d0c4: 6839 ldr r1, [r7, #0] 800d0c6: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += x; 800d0ca: 687b ldr r3, [r7, #4] 800d0cc: 681a ldr r2, [r3, #0] 800d0ce: 683b ldr r3, [r7, #0] 800d0d0: 441a add r2, r3 800d0d2: 687b ldr r3, [r7, #4] 800d0d4: 601a str r2, [r3, #0] f->idx++; 800d0d6: 687b ldr r3, [r7, #4] 800d0d8: 889b ldrh r3, [r3, #4] 800d0da: 3301 adds r3, #1 800d0dc: b29a uxth r2, r3 800d0de: 687b ldr r3, [r7, #4] 800d0e0: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800d0e2: 687b ldr r3, [r7, #4] 800d0e4: 889b ldrh r3, [r3, #4] 800d0e6: 2b07 cmp r3, #7 800d0e8: d902 bls.n 800d0f0 800d0ea: 687b ldr r3, [r7, #4] 800d0ec: 2200 movs r2, #0 800d0ee: 809a strh r2, [r3, #4] f->count++; 800d0f0: 687b ldr r3, [r7, #4] 800d0f2: 88db ldrh r3, [r3, #6] 800d0f4: 3301 adds r3, #1 800d0f6: b29a uxth r2, r3 800d0f8: 687b ldr r3, [r7, #4] 800d0fa: 80da strh r2, [r3, #6] return (int32_t)(f->sum / (int32_t)f->count); 800d0fc: 687b ldr r3, [r7, #4] 800d0fe: 681b ldr r3, [r3, #0] 800d100: 687a ldr r2, [r7, #4] 800d102: 88d2 ldrh r2, [r2, #6] 800d104: fb93 f3f2 sdiv r3, r3, r2 800d108: e02a b.n 800d160 } // Окно заполнено: "вычитаем старое + добавляем новое". int32_t old = f->buffer[f->idx]; 800d10a: 687b ldr r3, [r7, #4] 800d10c: 889b ldrh r3, [r3, #4] 800d10e: 461a mov r2, r3 800d110: 687b ldr r3, [r7, #4] 800d112: 3202 adds r2, #2 800d114: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800d118: 60fb str r3, [r7, #12] f->buffer[f->idx] = x; 800d11a: 687b ldr r3, [r7, #4] 800d11c: 889b ldrh r3, [r3, #4] 800d11e: 461a mov r2, r3 800d120: 687b ldr r3, [r7, #4] 800d122: 3202 adds r2, #2 800d124: 6839 ldr r1, [r7, #0] 800d126: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += (x - old); 800d12a: 687b ldr r3, [r7, #4] 800d12c: 681a ldr r2, [r3, #0] 800d12e: 6839 ldr r1, [r7, #0] 800d130: 68fb ldr r3, [r7, #12] 800d132: 1acb subs r3, r1, r3 800d134: 441a add r2, r3 800d136: 687b ldr r3, [r7, #4] 800d138: 601a str r2, [r3, #0] f->idx++; 800d13a: 687b ldr r3, [r7, #4] 800d13c: 889b ldrh r3, [r3, #4] 800d13e: 3301 adds r3, #1 800d140: b29a uxth r2, r3 800d142: 687b ldr r3, [r7, #4] 800d144: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800d146: 687b ldr r3, [r7, #4] 800d148: 889b ldrh r3, [r3, #4] 800d14a: 2b07 cmp r3, #7 800d14c: d902 bls.n 800d154 800d14e: 687b ldr r3, [r7, #4] 800d150: 2200 movs r2, #0 800d152: 809a strh r2, [r3, #4] return (int32_t)(f->sum / (int32_t)SMA_FILTER_WINDOW); 800d154: 687b ldr r3, [r7, #4] 800d156: 681b ldr r3, [r3, #0] 800d158: 2b00 cmp r3, #0 800d15a: da00 bge.n 800d15e 800d15c: 3307 adds r3, #7 800d15e: 10db asrs r3, r3, #3 } 800d160: 4618 mov r0, r3 800d162: 3714 adds r7, #20 800d164: 46bd mov sp, r7 800d166: bc80 pop {r7} 800d168: 4770 bx lr ... 0800d16c : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800d16c: b480 push {r7} 800d16e: b085 sub sp, #20 800d170: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 800d172: 4b15 ldr r3, [pc, #84] @ (800d1c8 ) 800d174: 699b ldr r3, [r3, #24] 800d176: 4a14 ldr r2, [pc, #80] @ (800d1c8 ) 800d178: f043 0301 orr.w r3, r3, #1 800d17c: 6193 str r3, [r2, #24] 800d17e: 4b12 ldr r3, [pc, #72] @ (800d1c8 ) 800d180: 699b ldr r3, [r3, #24] 800d182: f003 0301 and.w r3, r3, #1 800d186: 60bb str r3, [r7, #8] 800d188: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800d18a: 4b0f ldr r3, [pc, #60] @ (800d1c8 ) 800d18c: 69db ldr r3, [r3, #28] 800d18e: 4a0e ldr r2, [pc, #56] @ (800d1c8 ) 800d190: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800d194: 61d3 str r3, [r2, #28] 800d196: 4b0c ldr r3, [pc, #48] @ (800d1c8 ) 800d198: 69db ldr r3, [r3, #28] 800d19a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800d19e: 607b str r3, [r7, #4] 800d1a0: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 800d1a2: 4b0a ldr r3, [pc, #40] @ (800d1cc ) 800d1a4: 685b ldr r3, [r3, #4] 800d1a6: 60fb str r3, [r7, #12] 800d1a8: 68fb ldr r3, [r7, #12] 800d1aa: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 800d1ae: 60fb str r3, [r7, #12] 800d1b0: 68fb ldr r3, [r7, #12] 800d1b2: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 800d1b6: 60fb str r3, [r7, #12] 800d1b8: 4a04 ldr r2, [pc, #16] @ (800d1cc ) 800d1ba: 68fb ldr r3, [r7, #12] 800d1bc: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800d1be: bf00 nop 800d1c0: 3714 adds r7, #20 800d1c2: 46bd mov sp, r7 800d1c4: bc80 pop {r7} 800d1c6: 4770 bx lr 800d1c8: 40021000 .word 0x40021000 800d1cc: 40010000 .word 0x40010000 0800d1d0 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 800d1d0: b480 push {r7} 800d1d2: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800d1d4: bf00 nop 800d1d6: e7fd b.n 800d1d4 0800d1d8 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800d1d8: b480 push {r7} 800d1da: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800d1dc: bf00 nop 800d1de: e7fd b.n 800d1dc 0800d1e0 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 800d1e0: b480 push {r7} 800d1e2: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800d1e4: bf00 nop 800d1e6: e7fd b.n 800d1e4 0800d1e8 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 800d1e8: b480 push {r7} 800d1ea: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800d1ec: bf00 nop 800d1ee: e7fd b.n 800d1ec 0800d1f0 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 800d1f0: b480 push {r7} 800d1f2: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 800d1f4: bf00 nop 800d1f6: e7fd b.n 800d1f4 0800d1f8 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 800d1f8: b480 push {r7} 800d1fa: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800d1fc: bf00 nop 800d1fe: 46bd mov sp, r7 800d200: bc80 pop {r7} 800d202: 4770 bx lr 0800d204 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 800d204: b480 push {r7} 800d206: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800d208: bf00 nop 800d20a: 46bd mov sp, r7 800d20c: bc80 pop {r7} 800d20e: 4770 bx lr 0800d210 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800d210: b480 push {r7} 800d212: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800d214: bf00 nop 800d216: 46bd mov sp, r7 800d218: bc80 pop {r7} 800d21a: 4770 bx lr 0800d21c : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800d21c: b580 push {r7, lr} 800d21e: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800d220: f000 fd1a bl 800dc58 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 800d224: bf00 nop 800d226: bd80 pop {r7, pc} 0800d228 : /** * @brief This function handles CAN1 RX0 interrupt. */ void CAN1_RX0_IRQHandler(void) { 800d228: b580 push {r7, lr} 800d22a: af00 add r7, sp, #0 /* USER CODE BEGIN CAN1_RX0_IRQn 0 */ /* USER CODE END CAN1_RX0_IRQn 0 */ HAL_CAN_IRQHandler(&hcan1); 800d22c: 4802 ldr r0, [pc, #8] @ (800d238 ) 800d22e: f001 ff0b bl 800f048 /* USER CODE BEGIN CAN1_RX0_IRQn 1 */ /* USER CODE END CAN1_RX0_IRQn 1 */ } 800d232: bf00 nop 800d234: bd80 pop {r7, pc} 800d236: bf00 nop 800d238: 20000300 .word 0x20000300 0800d23c : /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 800d23c: b580 push {r7, lr} 800d23e: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_IRQn 0 */ /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); 800d240: 4802 ldr r0, [pc, #8] @ (800d24c ) 800d242: f004 f959 bl 80114f8 /* USER CODE BEGIN TIM3_IRQn 1 */ /* USER CODE END TIM3_IRQn 1 */ } 800d246: bf00 nop 800d248: bd80 pop {r7, pc} 800d24a: bf00 nop 800d24c: 20001054 .word 0x20001054 0800d250 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 800d250: b580 push {r7, lr} 800d252: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 800d254: 4802 ldr r0, [pc, #8] @ (800d260 ) 800d256: f005 f9fd bl 8012654 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 800d25a: bf00 nop 800d25c: bd80 pop {r7, pc} 800d25e: bf00 nop 800d260: 2000112c .word 0x2000112c 0800d264 : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 800d264: b580 push {r7, lr} 800d266: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 800d268: 4802 ldr r0, [pc, #8] @ (800d274 ) 800d26a: f005 f9f3 bl 8012654 /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 800d26e: bf00 nop 800d270: bd80 pop {r7, pc} 800d272: bf00 nop 800d274: 20001174 .word 0x20001174 0800d278 : /** * @brief This function handles USART3 global interrupt. */ void USART3_IRQHandler(void) { 800d278: b580 push {r7, lr} 800d27a: af00 add r7, sp, #0 /* USER CODE BEGIN USART3_IRQn 0 */ /* USER CODE END USART3_IRQn 0 */ HAL_UART_IRQHandler(&huart3); 800d27c: 4802 ldr r0, [pc, #8] @ (800d288 ) 800d27e: f005 f9e9 bl 8012654 /* USER CODE BEGIN USART3_IRQn 1 */ /* USER CODE END USART3_IRQn 1 */ } 800d282: bf00 nop 800d284: bd80 pop {r7, pc} 800d286: bf00 nop 800d288: 200011bc .word 0x200011bc 0800d28c : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 800d28c: b580 push {r7, lr} 800d28e: af00 add r7, sp, #0 /* USER CODE BEGIN UART5_IRQn 0 */ /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 800d290: 4802 ldr r0, [pc, #8] @ (800d29c ) 800d292: f005 f9df bl 8012654 /* USER CODE BEGIN UART5_IRQn 1 */ /* USER CODE END UART5_IRQn 1 */ } 800d296: bf00 nop 800d298: bd80 pop {r7, pc} 800d29a: bf00 nop 800d29c: 200010e4 .word 0x200010e4 0800d2a0 : /** * @brief This function handles CAN2 TX interrupt. */ void CAN2_TX_IRQHandler(void) { 800d2a0: b580 push {r7, lr} 800d2a2: af00 add r7, sp, #0 /* USER CODE BEGIN CAN2_TX_IRQn 0 */ /* USER CODE END CAN2_TX_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800d2a4: 4802 ldr r0, [pc, #8] @ (800d2b0 ) 800d2a6: f001 fecf bl 800f048 /* USER CODE BEGIN CAN2_TX_IRQn 1 */ /* USER CODE END CAN2_TX_IRQn 1 */ } 800d2aa: bf00 nop 800d2ac: bd80 pop {r7, pc} 800d2ae: bf00 nop 800d2b0: 20000328 .word 0x20000328 0800d2b4 : /** * @brief This function handles CAN2 RX1 interrupt. */ void CAN2_RX1_IRQHandler(void) { 800d2b4: b580 push {r7, lr} 800d2b6: af00 add r7, sp, #0 /* USER CODE BEGIN CAN2_RX1_IRQn 0 */ /* USER CODE END CAN2_RX1_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800d2b8: 4802 ldr r0, [pc, #8] @ (800d2c4 ) 800d2ba: f001 fec5 bl 800f048 /* USER CODE BEGIN CAN2_RX1_IRQn 1 */ /* USER CODE END CAN2_RX1_IRQn 1 */ } 800d2be: bf00 nop 800d2c0: bd80 pop {r7, pc} 800d2c2: bf00 nop 800d2c4: 20000328 .word 0x20000328 0800d2c8 <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 800d2c8: b480 push {r7} 800d2ca: af00 add r7, sp, #0 return 1; 800d2cc: 2301 movs r3, #1 } 800d2ce: 4618 mov r0, r3 800d2d0: 46bd mov sp, r7 800d2d2: bc80 pop {r7} 800d2d4: 4770 bx lr 0800d2d6 <_kill>: int _kill(int pid, int sig) { 800d2d6: b580 push {r7, lr} 800d2d8: b082 sub sp, #8 800d2da: af00 add r7, sp, #0 800d2dc: 6078 str r0, [r7, #4] 800d2de: 6039 str r1, [r7, #0] (void)pid; (void)sig; errno = EINVAL; 800d2e0: f006 fcf4 bl 8013ccc <__errno> 800d2e4: 4603 mov r3, r0 800d2e6: 2216 movs r2, #22 800d2e8: 601a str r2, [r3, #0] return -1; 800d2ea: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800d2ee: 4618 mov r0, r3 800d2f0: 3708 adds r7, #8 800d2f2: 46bd mov sp, r7 800d2f4: bd80 pop {r7, pc} 0800d2f6 <_exit>: void _exit (int status) { 800d2f6: b580 push {r7, lr} 800d2f8: b082 sub sp, #8 800d2fa: af00 add r7, sp, #0 800d2fc: 6078 str r0, [r7, #4] _kill(status, -1); 800d2fe: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800d302: 6878 ldr r0, [r7, #4] 800d304: f7ff ffe7 bl 800d2d6 <_kill> while (1) {} /* Make sure we hang here */ 800d308: bf00 nop 800d30a: e7fd b.n 800d308 <_exit+0x12> 0800d30c <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 800d30c: b580 push {r7, lr} 800d30e: b086 sub sp, #24 800d310: af00 add r7, sp, #0 800d312: 60f8 str r0, [r7, #12] 800d314: 60b9 str r1, [r7, #8] 800d316: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800d318: 2300 movs r3, #0 800d31a: 617b str r3, [r7, #20] 800d31c: e00a b.n 800d334 <_read+0x28> { *ptr++ = __io_getchar(); 800d31e: f3af 8000 nop.w 800d322: 4601 mov r1, r0 800d324: 68bb ldr r3, [r7, #8] 800d326: 1c5a adds r2, r3, #1 800d328: 60ba str r2, [r7, #8] 800d32a: b2ca uxtb r2, r1 800d32c: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 800d32e: 697b ldr r3, [r7, #20] 800d330: 3301 adds r3, #1 800d332: 617b str r3, [r7, #20] 800d334: 697a ldr r2, [r7, #20] 800d336: 687b ldr r3, [r7, #4] 800d338: 429a cmp r2, r3 800d33a: dbf0 blt.n 800d31e <_read+0x12> } return len; 800d33c: 687b ldr r3, [r7, #4] } 800d33e: 4618 mov r0, r3 800d340: 3718 adds r7, #24 800d342: 46bd mov sp, r7 800d344: bd80 pop {r7, pc} 0800d346 <_close>: } return len; } int _close(int file) { 800d346: b480 push {r7} 800d348: b083 sub sp, #12 800d34a: af00 add r7, sp, #0 800d34c: 6078 str r0, [r7, #4] (void)file; return -1; 800d34e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800d352: 4618 mov r0, r3 800d354: 370c adds r7, #12 800d356: 46bd mov sp, r7 800d358: bc80 pop {r7} 800d35a: 4770 bx lr 0800d35c <_fstat>: int _fstat(int file, struct stat *st) { 800d35c: b480 push {r7} 800d35e: b083 sub sp, #12 800d360: af00 add r7, sp, #0 800d362: 6078 str r0, [r7, #4] 800d364: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 800d366: 683b ldr r3, [r7, #0] 800d368: f44f 5200 mov.w r2, #8192 @ 0x2000 800d36c: 605a str r2, [r3, #4] return 0; 800d36e: 2300 movs r3, #0 } 800d370: 4618 mov r0, r3 800d372: 370c adds r7, #12 800d374: 46bd mov sp, r7 800d376: bc80 pop {r7} 800d378: 4770 bx lr 0800d37a <_isatty>: int _isatty(int file) { 800d37a: b480 push {r7} 800d37c: b083 sub sp, #12 800d37e: af00 add r7, sp, #0 800d380: 6078 str r0, [r7, #4] (void)file; return 1; 800d382: 2301 movs r3, #1 } 800d384: 4618 mov r0, r3 800d386: 370c adds r7, #12 800d388: 46bd mov sp, r7 800d38a: bc80 pop {r7} 800d38c: 4770 bx lr 0800d38e <_lseek>: int _lseek(int file, int ptr, int dir) { 800d38e: b480 push {r7} 800d390: b085 sub sp, #20 800d392: af00 add r7, sp, #0 800d394: 60f8 str r0, [r7, #12] 800d396: 60b9 str r1, [r7, #8] 800d398: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 800d39a: 2300 movs r3, #0 } 800d39c: 4618 mov r0, r3 800d39e: 3714 adds r7, #20 800d3a0: 46bd mov sp, r7 800d3a2: bc80 pop {r7} 800d3a4: 4770 bx lr ... 0800d3a8 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 800d3a8: b580 push {r7, lr} 800d3aa: b086 sub sp, #24 800d3ac: af00 add r7, sp, #0 800d3ae: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 800d3b0: 4a14 ldr r2, [pc, #80] @ (800d404 <_sbrk+0x5c>) 800d3b2: 4b15 ldr r3, [pc, #84] @ (800d408 <_sbrk+0x60>) 800d3b4: 1ad3 subs r3, r2, r3 800d3b6: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 800d3b8: 697b ldr r3, [r7, #20] 800d3ba: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 800d3bc: 4b13 ldr r3, [pc, #76] @ (800d40c <_sbrk+0x64>) 800d3be: 681b ldr r3, [r3, #0] 800d3c0: 2b00 cmp r3, #0 800d3c2: d102 bne.n 800d3ca <_sbrk+0x22> { __sbrk_heap_end = &_end; 800d3c4: 4b11 ldr r3, [pc, #68] @ (800d40c <_sbrk+0x64>) 800d3c6: 4a12 ldr r2, [pc, #72] @ (800d410 <_sbrk+0x68>) 800d3c8: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 800d3ca: 4b10 ldr r3, [pc, #64] @ (800d40c <_sbrk+0x64>) 800d3cc: 681a ldr r2, [r3, #0] 800d3ce: 687b ldr r3, [r7, #4] 800d3d0: 4413 add r3, r2 800d3d2: 693a ldr r2, [r7, #16] 800d3d4: 429a cmp r2, r3 800d3d6: d207 bcs.n 800d3e8 <_sbrk+0x40> { errno = ENOMEM; 800d3d8: f006 fc78 bl 8013ccc <__errno> 800d3dc: 4603 mov r3, r0 800d3de: 220c movs r2, #12 800d3e0: 601a str r2, [r3, #0] return (void *)-1; 800d3e2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800d3e6: e009 b.n 800d3fc <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 800d3e8: 4b08 ldr r3, [pc, #32] @ (800d40c <_sbrk+0x64>) 800d3ea: 681b ldr r3, [r3, #0] 800d3ec: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 800d3ee: 4b07 ldr r3, [pc, #28] @ (800d40c <_sbrk+0x64>) 800d3f0: 681a ldr r2, [r3, #0] 800d3f2: 687b ldr r3, [r7, #4] 800d3f4: 4413 add r3, r2 800d3f6: 4a05 ldr r2, [pc, #20] @ (800d40c <_sbrk+0x64>) 800d3f8: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 800d3fa: 68fb ldr r3, [r7, #12] } 800d3fc: 4618 mov r0, r3 800d3fe: 3718 adds r7, #24 800d400: 46bd mov sp, r7 800d402: bd80 pop {r7, pc} 800d404: 20010000 .word 0x20010000 800d408: 00000400 .word 0x00000400 800d40c: 20001050 .word 0x20001050 800d410: 20001358 .word 0x20001358 0800d414 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 800d414: b480 push {r7} 800d416: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 800d418: bf00 nop 800d41a: 46bd mov sp, r7 800d41c: bc80 pop {r7} 800d41e: 4770 bx lr 0800d420 : TIM_HandleTypeDef htim3; TIM_HandleTypeDef htim4; /* TIM3 init function */ void MX_TIM3_Init(void) { 800d420: b580 push {r7, lr} 800d422: b08e sub sp, #56 @ 0x38 800d424: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800d426: f107 0328 add.w r3, r7, #40 @ 0x28 800d42a: 2200 movs r2, #0 800d42c: 601a str r2, [r3, #0] 800d42e: 605a str r2, [r3, #4] 800d430: 609a str r2, [r3, #8] 800d432: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800d434: f107 0320 add.w r3, r7, #32 800d438: 2200 movs r2, #0 800d43a: 601a str r2, [r3, #0] 800d43c: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800d43e: 1d3b adds r3, r7, #4 800d440: 2200 movs r2, #0 800d442: 601a str r2, [r3, #0] 800d444: 605a str r2, [r3, #4] 800d446: 609a str r2, [r3, #8] 800d448: 60da str r2, [r3, #12] 800d44a: 611a str r2, [r3, #16] 800d44c: 615a str r2, [r3, #20] 800d44e: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 800d450: 4b38 ldr r3, [pc, #224] @ (800d534 ) 800d452: 4a39 ldr r2, [pc, #228] @ (800d538 ) 800d454: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 800d456: 4b37 ldr r3, [pc, #220] @ (800d534 ) 800d458: 2200 movs r2, #0 800d45a: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 800d45c: 4b35 ldr r3, [pc, #212] @ (800d534 ) 800d45e: 2200 movs r2, #0 800d460: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 800d462: 4b34 ldr r3, [pc, #208] @ (800d534 ) 800d464: f64f 72ff movw r2, #65535 @ 0xffff 800d468: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800d46a: 4b32 ldr r3, [pc, #200] @ (800d534 ) 800d46c: 2200 movs r2, #0 800d46e: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800d470: 4b30 ldr r3, [pc, #192] @ (800d534 ) 800d472: 2200 movs r2, #0 800d474: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 800d476: 482f ldr r0, [pc, #188] @ (800d534 ) 800d478: f003 fd9f bl 8010fba 800d47c: 4603 mov r3, r0 800d47e: 2b00 cmp r3, #0 800d480: d001 beq.n 800d486 { Error_Handler(); 800d482: f7fd fac7 bl 800aa14 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800d486: f44f 5380 mov.w r3, #4096 @ 0x1000 800d48a: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 800d48c: f107 0328 add.w r3, r7, #40 @ 0x28 800d490: 4619 mov r1, r3 800d492: 4828 ldr r0, [pc, #160] @ (800d534 ) 800d494: f004 fa3e bl 8011914 800d498: 4603 mov r3, r0 800d49a: 2b00 cmp r3, #0 800d49c: d001 beq.n 800d4a2 { Error_Handler(); 800d49e: f7fd fab9 bl 800aa14 } if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 800d4a2: 4824 ldr r0, [pc, #144] @ (800d534 ) 800d4a4: f003 ff26 bl 80112f4 800d4a8: 4603 mov r3, r0 800d4aa: 2b00 cmp r3, #0 800d4ac: d001 beq.n 800d4b2 { Error_Handler(); 800d4ae: f7fd fab1 bl 800aa14 } if (HAL_TIM_OC_Init(&htim3) != HAL_OK) 800d4b2: 4820 ldr r0, [pc, #128] @ (800d534 ) 800d4b4: f003 fdd0 bl 8011058 800d4b8: 4603 mov r3, r0 800d4ba: 2b00 cmp r3, #0 800d4bc: d001 beq.n 800d4c2 { Error_Handler(); 800d4be: f7fd faa9 bl 800aa14 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800d4c2: 2300 movs r3, #0 800d4c4: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800d4c6: 2300 movs r3, #0 800d4c8: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800d4ca: f107 0320 add.w r3, r7, #32 800d4ce: 4619 mov r1, r3 800d4d0: 4818 ldr r0, [pc, #96] @ (800d534 ) 800d4d2: f004 fdc5 bl 8012060 800d4d6: 4603 mov r3, r0 800d4d8: 2b00 cmp r3, #0 800d4da: d001 beq.n 800d4e0 { Error_Handler(); 800d4dc: f7fd fa9a bl 800aa14 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800d4e0: 2360 movs r3, #96 @ 0x60 800d4e2: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800d4e4: 2300 movs r3, #0 800d4e6: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800d4e8: 2300 movs r3, #0 800d4ea: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800d4ec: 2300 movs r3, #0 800d4ee: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800d4f0: 1d3b adds r3, r7, #4 800d4f2: 2204 movs r2, #4 800d4f4: 4619 mov r1, r3 800d4f6: 480f ldr r0, [pc, #60] @ (800d534 ) 800d4f8: f004 f94a bl 8011790 800d4fc: 4603 mov r3, r0 800d4fe: 2b00 cmp r3, #0 800d500: d001 beq.n 800d506 { Error_Handler(); 800d502: f7fd fa87 bl 800aa14 } sConfigOC.OCMode = TIM_OCMODE_TIMING; 800d506: 2300 movs r3, #0 800d508: 607b str r3, [r7, #4] sConfigOC.Pulse = 1; 800d50a: 2301 movs r3, #1 800d50c: 60bb str r3, [r7, #8] if (HAL_TIM_OC_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 800d50e: 1d3b adds r3, r7, #4 800d510: 2200 movs r2, #0 800d512: 4619 mov r1, r3 800d514: 4807 ldr r0, [pc, #28] @ (800d534 ) 800d516: f004 f8df bl 80116d8 800d51a: 4603 mov r3, r0 800d51c: 2b00 cmp r3, #0 800d51e: d001 beq.n 800d524 { Error_Handler(); 800d520: f7fd fa78 bl 800aa14 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 800d524: 4803 ldr r0, [pc, #12] @ (800d534 ) 800d526: f000 f8cf bl 800d6c8 } 800d52a: bf00 nop 800d52c: 3738 adds r7, #56 @ 0x38 800d52e: 46bd mov sp, r7 800d530: bd80 pop {r7, pc} 800d532: bf00 nop 800d534: 20001054 .word 0x20001054 800d538: 40000400 .word 0x40000400 0800d53c : /* TIM4 init function */ void MX_TIM4_Init(void) { 800d53c: b580 push {r7, lr} 800d53e: b08e sub sp, #56 @ 0x38 800d540: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800d542: f107 0328 add.w r3, r7, #40 @ 0x28 800d546: 2200 movs r2, #0 800d548: 601a str r2, [r3, #0] 800d54a: 605a str r2, [r3, #4] 800d54c: 609a str r2, [r3, #8] 800d54e: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800d550: f107 0320 add.w r3, r7, #32 800d554: 2200 movs r2, #0 800d556: 601a str r2, [r3, #0] 800d558: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800d55a: 1d3b adds r3, r7, #4 800d55c: 2200 movs r2, #0 800d55e: 601a str r2, [r3, #0] 800d560: 605a str r2, [r3, #4] 800d562: 609a str r2, [r3, #8] 800d564: 60da str r2, [r3, #12] 800d566: 611a str r2, [r3, #16] 800d568: 615a str r2, [r3, #20] 800d56a: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM4_Init 1 */ /* USER CODE END TIM4_Init 1 */ htim4.Instance = TIM4; 800d56c: 4b37 ldr r3, [pc, #220] @ (800d64c ) 800d56e: 4a38 ldr r2, [pc, #224] @ (800d650 ) 800d570: 601a str r2, [r3, #0] htim4.Init.Prescaler = 720; 800d572: 4b36 ldr r3, [pc, #216] @ (800d64c ) 800d574: f44f 7234 mov.w r2, #720 @ 0x2d0 800d578: 605a str r2, [r3, #4] htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 800d57a: 4b34 ldr r3, [pc, #208] @ (800d64c ) 800d57c: 2200 movs r2, #0 800d57e: 609a str r2, [r3, #8] htim4.Init.Period = 100; 800d580: 4b32 ldr r3, [pc, #200] @ (800d64c ) 800d582: 2264 movs r2, #100 @ 0x64 800d584: 60da str r2, [r3, #12] htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800d586: 4b31 ldr r3, [pc, #196] @ (800d64c ) 800d588: 2200 movs r2, #0 800d58a: 611a str r2, [r3, #16] htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800d58c: 4b2f ldr r3, [pc, #188] @ (800d64c ) 800d58e: 2200 movs r2, #0 800d590: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 800d592: 482e ldr r0, [pc, #184] @ (800d64c ) 800d594: f003 fd11 bl 8010fba 800d598: 4603 mov r3, r0 800d59a: 2b00 cmp r3, #0 800d59c: d001 beq.n 800d5a2 { Error_Handler(); 800d59e: f7fd fa39 bl 800aa14 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800d5a2: f44f 5380 mov.w r3, #4096 @ 0x1000 800d5a6: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 800d5a8: f107 0328 add.w r3, r7, #40 @ 0x28 800d5ac: 4619 mov r1, r3 800d5ae: 4827 ldr r0, [pc, #156] @ (800d64c ) 800d5b0: f004 f9b0 bl 8011914 800d5b4: 4603 mov r3, r0 800d5b6: 2b00 cmp r3, #0 800d5b8: d001 beq.n 800d5be { Error_Handler(); 800d5ba: f7fd fa2b bl 800aa14 } if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) 800d5be: 4823 ldr r0, [pc, #140] @ (800d64c ) 800d5c0: f003 fe98 bl 80112f4 800d5c4: 4603 mov r3, r0 800d5c6: 2b00 cmp r3, #0 800d5c8: d001 beq.n 800d5ce { Error_Handler(); 800d5ca: f7fd fa23 bl 800aa14 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800d5ce: 2300 movs r3, #0 800d5d0: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800d5d2: 2300 movs r3, #0 800d5d4: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 800d5d6: f107 0320 add.w r3, r7, #32 800d5da: 4619 mov r1, r3 800d5dc: 481b ldr r0, [pc, #108] @ (800d64c ) 800d5de: f004 fd3f bl 8012060 800d5e2: 4603 mov r3, r0 800d5e4: 2b00 cmp r3, #0 800d5e6: d001 beq.n 800d5ec { Error_Handler(); 800d5e8: f7fd fa14 bl 800aa14 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800d5ec: 2360 movs r3, #96 @ 0x60 800d5ee: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800d5f0: 2300 movs r3, #0 800d5f2: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800d5f4: 2300 movs r3, #0 800d5f6: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800d5f8: 2300 movs r3, #0 800d5fa: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800d5fc: 1d3b adds r3, r7, #4 800d5fe: 2204 movs r2, #4 800d600: 4619 mov r1, r3 800d602: 4812 ldr r0, [pc, #72] @ (800d64c ) 800d604: f004 f8c4 bl 8011790 800d608: 4603 mov r3, r0 800d60a: 2b00 cmp r3, #0 800d60c: d001 beq.n 800d612 { Error_Handler(); 800d60e: f7fd fa01 bl 800aa14 } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 800d612: 1d3b adds r3, r7, #4 800d614: 2208 movs r2, #8 800d616: 4619 mov r1, r3 800d618: 480c ldr r0, [pc, #48] @ (800d64c ) 800d61a: f004 f8b9 bl 8011790 800d61e: 4603 mov r3, r0 800d620: 2b00 cmp r3, #0 800d622: d001 beq.n 800d628 { Error_Handler(); 800d624: f7fd f9f6 bl 800aa14 } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 800d628: 1d3b adds r3, r7, #4 800d62a: 220c movs r2, #12 800d62c: 4619 mov r1, r3 800d62e: 4807 ldr r0, [pc, #28] @ (800d64c ) 800d630: f004 f8ae bl 8011790 800d634: 4603 mov r3, r0 800d636: 2b00 cmp r3, #0 800d638: d001 beq.n 800d63e { Error_Handler(); 800d63a: f7fd f9eb bl 800aa14 } /* USER CODE BEGIN TIM4_Init 2 */ /* USER CODE END TIM4_Init 2 */ HAL_TIM_MspPostInit(&htim4); 800d63e: 4803 ldr r0, [pc, #12] @ (800d64c ) 800d640: f000 f842 bl 800d6c8 } 800d644: bf00 nop 800d646: 3738 adds r7, #56 @ 0x38 800d648: 46bd mov sp, r7 800d64a: bd80 pop {r7, pc} 800d64c: 2000109c .word 0x2000109c 800d650: 40000800 .word 0x40000800 0800d654 : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 800d654: b580 push {r7, lr} 800d656: b084 sub sp, #16 800d658: af00 add r7, sp, #0 800d65a: 6078 str r0, [r7, #4] if(tim_baseHandle->Instance==TIM3) 800d65c: 687b ldr r3, [r7, #4] 800d65e: 681b ldr r3, [r3, #0] 800d660: 4a16 ldr r2, [pc, #88] @ (800d6bc ) 800d662: 4293 cmp r3, r2 800d664: d114 bne.n 800d690 { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 800d666: 4b16 ldr r3, [pc, #88] @ (800d6c0 ) 800d668: 69db ldr r3, [r3, #28] 800d66a: 4a15 ldr r2, [pc, #84] @ (800d6c0 ) 800d66c: f043 0302 orr.w r3, r3, #2 800d670: 61d3 str r3, [r2, #28] 800d672: 4b13 ldr r3, [pc, #76] @ (800d6c0 ) 800d674: 69db ldr r3, [r3, #28] 800d676: f003 0302 and.w r3, r3, #2 800d67a: 60fb str r3, [r7, #12] 800d67c: 68fb ldr r3, [r7, #12] /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0); 800d67e: 2200 movs r2, #0 800d680: 2100 movs r1, #0 800d682: 201d movs r0, #29 800d684: f001 ffdb bl 800f63e HAL_NVIC_EnableIRQ(TIM3_IRQn); 800d688: 201d movs r0, #29 800d68a: f001 fff4 bl 800f676 __HAL_RCC_TIM4_CLK_ENABLE(); /* USER CODE BEGIN TIM4_MspInit 1 */ /* USER CODE END TIM4_MspInit 1 */ } } 800d68e: e010 b.n 800d6b2 else if(tim_baseHandle->Instance==TIM4) 800d690: 687b ldr r3, [r7, #4] 800d692: 681b ldr r3, [r3, #0] 800d694: 4a0b ldr r2, [pc, #44] @ (800d6c4 ) 800d696: 4293 cmp r3, r2 800d698: d10b bne.n 800d6b2 __HAL_RCC_TIM4_CLK_ENABLE(); 800d69a: 4b09 ldr r3, [pc, #36] @ (800d6c0 ) 800d69c: 69db ldr r3, [r3, #28] 800d69e: 4a08 ldr r2, [pc, #32] @ (800d6c0 ) 800d6a0: f043 0304 orr.w r3, r3, #4 800d6a4: 61d3 str r3, [r2, #28] 800d6a6: 4b06 ldr r3, [pc, #24] @ (800d6c0 ) 800d6a8: 69db ldr r3, [r3, #28] 800d6aa: f003 0304 and.w r3, r3, #4 800d6ae: 60bb str r3, [r7, #8] 800d6b0: 68bb ldr r3, [r7, #8] } 800d6b2: bf00 nop 800d6b4: 3710 adds r7, #16 800d6b6: 46bd mov sp, r7 800d6b8: bd80 pop {r7, pc} 800d6ba: bf00 nop 800d6bc: 40000400 .word 0x40000400 800d6c0: 40021000 .word 0x40021000 800d6c4: 40000800 .word 0x40000800 0800d6c8 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 800d6c8: b580 push {r7, lr} 800d6ca: b08a sub sp, #40 @ 0x28 800d6cc: af00 add r7, sp, #0 800d6ce: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800d6d0: f107 0314 add.w r3, r7, #20 800d6d4: 2200 movs r2, #0 800d6d6: 601a str r2, [r3, #0] 800d6d8: 605a str r2, [r3, #4] 800d6da: 609a str r2, [r3, #8] 800d6dc: 60da str r2, [r3, #12] if(timHandle->Instance==TIM3) 800d6de: 687b ldr r3, [r7, #4] 800d6e0: 681b ldr r3, [r3, #0] 800d6e2: 4a26 ldr r2, [pc, #152] @ (800d77c ) 800d6e4: 4293 cmp r3, r2 800d6e6: d118 bne.n 800d71a { /* USER CODE BEGIN TIM3_MspPostInit 0 */ /* USER CODE END TIM3_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800d6e8: 4b25 ldr r3, [pc, #148] @ (800d780 ) 800d6ea: 699b ldr r3, [r3, #24] 800d6ec: 4a24 ldr r2, [pc, #144] @ (800d780 ) 800d6ee: f043 0304 orr.w r3, r3, #4 800d6f2: 6193 str r3, [r2, #24] 800d6f4: 4b22 ldr r3, [pc, #136] @ (800d780 ) 800d6f6: 699b ldr r3, [r3, #24] 800d6f8: f003 0304 and.w r3, r3, #4 800d6fc: 613b str r3, [r7, #16] 800d6fe: 693b ldr r3, [r7, #16] /**TIM3 GPIO Configuration PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = CP_PWM_Pin; 800d700: 2380 movs r3, #128 @ 0x80 800d702: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d704: 2302 movs r3, #2 800d706: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800d708: 2302 movs r3, #2 800d70a: 623b str r3, [r7, #32] HAL_GPIO_Init(CP_PWM_GPIO_Port, &GPIO_InitStruct); 800d70c: f107 0314 add.w r3, r7, #20 800d710: 4619 mov r1, r3 800d712: 481c ldr r0, [pc, #112] @ (800d784 ) 800d714: f002 f928 bl 800f968 /* USER CODE BEGIN TIM4_MspPostInit 1 */ /* USER CODE END TIM4_MspPostInit 1 */ } } 800d718: e02b b.n 800d772 else if(timHandle->Instance==TIM4) 800d71a: 687b ldr r3, [r7, #4] 800d71c: 681b ldr r3, [r3, #0] 800d71e: 4a1a ldr r2, [pc, #104] @ (800d788 ) 800d720: 4293 cmp r3, r2 800d722: d126 bne.n 800d772 __HAL_RCC_GPIOD_CLK_ENABLE(); 800d724: 4b16 ldr r3, [pc, #88] @ (800d780 ) 800d726: 699b ldr r3, [r3, #24] 800d728: 4a15 ldr r2, [pc, #84] @ (800d780 ) 800d72a: f043 0320 orr.w r3, r3, #32 800d72e: 6193 str r3, [r2, #24] 800d730: 4b13 ldr r3, [pc, #76] @ (800d780 ) 800d732: 699b ldr r3, [r3, #24] 800d734: f003 0320 and.w r3, r3, #32 800d738: 60fb str r3, [r7, #12] 800d73a: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; 800d73c: f44f 4360 mov.w r3, #57344 @ 0xe000 800d740: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d742: 2302 movs r3, #2 800d744: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800d746: 2302 movs r3, #2 800d748: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800d74a: f107 0314 add.w r3, r7, #20 800d74e: 4619 mov r1, r3 800d750: 480e ldr r0, [pc, #56] @ (800d78c ) 800d752: f002 f909 bl 800f968 __HAL_AFIO_REMAP_TIM4_ENABLE(); 800d756: 4b0e ldr r3, [pc, #56] @ (800d790 ) 800d758: 685b ldr r3, [r3, #4] 800d75a: 627b str r3, [r7, #36] @ 0x24 800d75c: 6a7b ldr r3, [r7, #36] @ 0x24 800d75e: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800d762: 627b str r3, [r7, #36] @ 0x24 800d764: 6a7b ldr r3, [r7, #36] @ 0x24 800d766: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800d76a: 627b str r3, [r7, #36] @ 0x24 800d76c: 4a08 ldr r2, [pc, #32] @ (800d790 ) 800d76e: 6a7b ldr r3, [r7, #36] @ 0x24 800d770: 6053 str r3, [r2, #4] } 800d772: bf00 nop 800d774: 3728 adds r7, #40 @ 0x28 800d776: 46bd mov sp, r7 800d778: bd80 pop {r7, pc} 800d77a: bf00 nop 800d77c: 40000400 .word 0x40000400 800d780: 40021000 .word 0x40021000 800d784: 40010800 .word 0x40010800 800d788: 40000800 .word 0x40000800 800d78c: 40011400 .word 0x40011400 800d790: 40010000 .word 0x40010000 0800d794 : UART_HandleTypeDef huart2; UART_HandleTypeDef huart3; /* UART5 init function */ void MX_UART5_Init(void) { 800d794: b580 push {r7, lr} 800d796: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 800d798: 4b11 ldr r3, [pc, #68] @ (800d7e0 ) 800d79a: 4a12 ldr r2, [pc, #72] @ (800d7e4 ) 800d79c: 601a str r2, [r3, #0] huart5.Init.BaudRate = 9600; 800d79e: 4b10 ldr r3, [pc, #64] @ (800d7e0 ) 800d7a0: f44f 5216 mov.w r2, #9600 @ 0x2580 800d7a4: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 800d7a6: 4b0e ldr r3, [pc, #56] @ (800d7e0 ) 800d7a8: 2200 movs r2, #0 800d7aa: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 800d7ac: 4b0c ldr r3, [pc, #48] @ (800d7e0 ) 800d7ae: 2200 movs r2, #0 800d7b0: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 800d7b2: 4b0b ldr r3, [pc, #44] @ (800d7e0 ) 800d7b4: 2200 movs r2, #0 800d7b6: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 800d7b8: 4b09 ldr r3, [pc, #36] @ (800d7e0 ) 800d7ba: 220c movs r2, #12 800d7bc: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d7be: 4b08 ldr r3, [pc, #32] @ (800d7e0 ) 800d7c0: 2200 movs r2, #0 800d7c2: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 800d7c4: 4b06 ldr r3, [pc, #24] @ (800d7e0 ) 800d7c6: 2200 movs r2, #0 800d7c8: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 800d7ca: 4805 ldr r0, [pc, #20] @ (800d7e0 ) 800d7cc: f004 fcc0 bl 8012150 800d7d0: 4603 mov r3, r0 800d7d2: 2b00 cmp r3, #0 800d7d4: d001 beq.n 800d7da { Error_Handler(); 800d7d6: f7fd f91d bl 800aa14 } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 800d7da: bf00 nop 800d7dc: bd80 pop {r7, pc} 800d7de: bf00 nop 800d7e0: 200010e4 .word 0x200010e4 800d7e4: 40005000 .word 0x40005000 0800d7e8 : /* USART1 init function */ void MX_USART1_UART_Init(void) { 800d7e8: b580 push {r7, lr} 800d7ea: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 800d7ec: 4b11 ldr r3, [pc, #68] @ (800d834 ) 800d7ee: 4a12 ldr r2, [pc, #72] @ (800d838 ) 800d7f0: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800d7f2: 4b10 ldr r3, [pc, #64] @ (800d834 ) 800d7f4: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800d7f8: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800d7fa: 4b0e ldr r3, [pc, #56] @ (800d834 ) 800d7fc: 2200 movs r2, #0 800d7fe: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 800d800: 4b0c ldr r3, [pc, #48] @ (800d834 ) 800d802: 2200 movs r2, #0 800d804: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800d806: 4b0b ldr r3, [pc, #44] @ (800d834 ) 800d808: 2200 movs r2, #0 800d80a: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 800d80c: 4b09 ldr r3, [pc, #36] @ (800d834 ) 800d80e: 220c movs r2, #12 800d810: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d812: 4b08 ldr r3, [pc, #32] @ (800d834 ) 800d814: 2200 movs r2, #0 800d816: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 800d818: 4b06 ldr r3, [pc, #24] @ (800d834 ) 800d81a: 2200 movs r2, #0 800d81c: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 800d81e: 4805 ldr r0, [pc, #20] @ (800d834 ) 800d820: f004 fc96 bl 8012150 800d824: 4603 mov r3, r0 800d826: 2b00 cmp r3, #0 800d828: d001 beq.n 800d82e { Error_Handler(); 800d82a: f7fd f8f3 bl 800aa14 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 800d82e: bf00 nop 800d830: bd80 pop {r7, pc} 800d832: bf00 nop 800d834: 2000112c .word 0x2000112c 800d838: 40013800 .word 0x40013800 0800d83c : /* USART2 init function */ void MX_USART2_UART_Init(void) { 800d83c: b580 push {r7, lr} 800d83e: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 800d840: 4b11 ldr r3, [pc, #68] @ (800d888 ) 800d842: 4a12 ldr r2, [pc, #72] @ (800d88c ) 800d844: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 800d846: 4b10 ldr r3, [pc, #64] @ (800d888 ) 800d848: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800d84c: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 800d84e: 4b0e ldr r3, [pc, #56] @ (800d888 ) 800d850: 2200 movs r2, #0 800d852: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 800d854: 4b0c ldr r3, [pc, #48] @ (800d888 ) 800d856: 2200 movs r2, #0 800d858: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 800d85a: 4b0b ldr r3, [pc, #44] @ (800d888 ) 800d85c: 2200 movs r2, #0 800d85e: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 800d860: 4b09 ldr r3, [pc, #36] @ (800d888 ) 800d862: 220c movs r2, #12 800d864: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d866: 4b08 ldr r3, [pc, #32] @ (800d888 ) 800d868: 2200 movs r2, #0 800d86a: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 800d86c: 4b06 ldr r3, [pc, #24] @ (800d888 ) 800d86e: 2200 movs r2, #0 800d870: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 800d872: 4805 ldr r0, [pc, #20] @ (800d888 ) 800d874: f004 fc6c bl 8012150 800d878: 4603 mov r3, r0 800d87a: 2b00 cmp r3, #0 800d87c: d001 beq.n 800d882 { Error_Handler(); 800d87e: f7fd f8c9 bl 800aa14 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 800d882: bf00 nop 800d884: bd80 pop {r7, pc} 800d886: bf00 nop 800d888: 20001174 .word 0x20001174 800d88c: 40004400 .word 0x40004400 0800d890 : /* USART3 init function */ void MX_USART3_UART_Init(void) { 800d890: b580 push {r7, lr} 800d892: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 800d894: 4b11 ldr r3, [pc, #68] @ (800d8dc ) 800d896: 4a12 ldr r2, [pc, #72] @ (800d8e0 ) 800d898: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 800d89a: 4b10 ldr r3, [pc, #64] @ (800d8dc ) 800d89c: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800d8a0: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 800d8a2: 4b0e ldr r3, [pc, #56] @ (800d8dc ) 800d8a4: 2200 movs r2, #0 800d8a6: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 800d8a8: 4b0c ldr r3, [pc, #48] @ (800d8dc ) 800d8aa: 2200 movs r2, #0 800d8ac: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 800d8ae: 4b0b ldr r3, [pc, #44] @ (800d8dc ) 800d8b0: 2200 movs r2, #0 800d8b2: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 800d8b4: 4b09 ldr r3, [pc, #36] @ (800d8dc ) 800d8b6: 220c movs r2, #12 800d8b8: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800d8ba: 4b08 ldr r3, [pc, #32] @ (800d8dc ) 800d8bc: 2200 movs r2, #0 800d8be: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 800d8c0: 4b06 ldr r3, [pc, #24] @ (800d8dc ) 800d8c2: 2200 movs r2, #0 800d8c4: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart3) != HAL_OK) 800d8c6: 4805 ldr r0, [pc, #20] @ (800d8dc ) 800d8c8: f004 fc42 bl 8012150 800d8cc: 4603 mov r3, r0 800d8ce: 2b00 cmp r3, #0 800d8d0: d001 beq.n 800d8d6 { Error_Handler(); 800d8d2: f7fd f89f bl 800aa14 } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 800d8d6: bf00 nop 800d8d8: bd80 pop {r7, pc} 800d8da: bf00 nop 800d8dc: 200011bc .word 0x200011bc 800d8e0: 40004800 .word 0x40004800 0800d8e4 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 800d8e4: b580 push {r7, lr} 800d8e6: b092 sub sp, #72 @ 0x48 800d8e8: af00 add r7, sp, #0 800d8ea: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800d8ec: f107 0330 add.w r3, r7, #48 @ 0x30 800d8f0: 2200 movs r2, #0 800d8f2: 601a str r2, [r3, #0] 800d8f4: 605a str r2, [r3, #4] 800d8f6: 609a str r2, [r3, #8] 800d8f8: 60da str r2, [r3, #12] if(uartHandle->Instance==UART5) 800d8fa: 687b ldr r3, [r7, #4] 800d8fc: 681b ldr r3, [r3, #0] 800d8fe: 4a95 ldr r2, [pc, #596] @ (800db54 ) 800d900: 4293 cmp r3, r2 800d902: d145 bne.n 800d990 { /* USER CODE BEGIN UART5_MspInit 0 */ /* USER CODE END UART5_MspInit 0 */ /* UART5 clock enable */ __HAL_RCC_UART5_CLK_ENABLE(); 800d904: 4b94 ldr r3, [pc, #592] @ (800db58 ) 800d906: 69db ldr r3, [r3, #28] 800d908: 4a93 ldr r2, [pc, #588] @ (800db58 ) 800d90a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800d90e: 61d3 str r3, [r2, #28] 800d910: 4b91 ldr r3, [pc, #580] @ (800db58 ) 800d912: 69db ldr r3, [r3, #28] 800d914: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800d918: 62fb str r3, [r7, #44] @ 0x2c 800d91a: 6afb ldr r3, [r7, #44] @ 0x2c __HAL_RCC_GPIOC_CLK_ENABLE(); 800d91c: 4b8e ldr r3, [pc, #568] @ (800db58 ) 800d91e: 699b ldr r3, [r3, #24] 800d920: 4a8d ldr r2, [pc, #564] @ (800db58 ) 800d922: f043 0310 orr.w r3, r3, #16 800d926: 6193 str r3, [r2, #24] 800d928: 4b8b ldr r3, [pc, #556] @ (800db58 ) 800d92a: 699b ldr r3, [r3, #24] 800d92c: f003 0310 and.w r3, r3, #16 800d930: 62bb str r3, [r7, #40] @ 0x28 800d932: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOD_CLK_ENABLE(); 800d934: 4b88 ldr r3, [pc, #544] @ (800db58 ) 800d936: 699b ldr r3, [r3, #24] 800d938: 4a87 ldr r2, [pc, #540] @ (800db58 ) 800d93a: f043 0320 orr.w r3, r3, #32 800d93e: 6193 str r3, [r2, #24] 800d940: 4b85 ldr r3, [pc, #532] @ (800db58 ) 800d942: 699b ldr r3, [r3, #24] 800d944: f003 0320 and.w r3, r3, #32 800d948: 627b str r3, [r7, #36] @ 0x24 800d94a: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART5 GPIO Configuration PC12 ------> UART5_TX PD2 ------> UART5_RX */ GPIO_InitStruct.Pin = GPIO_PIN_12; 800d94c: f44f 5380 mov.w r3, #4096 @ 0x1000 800d950: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d952: 2302 movs r3, #2 800d954: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800d956: 2303 movs r3, #3 800d958: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800d95a: f107 0330 add.w r3, r7, #48 @ 0x30 800d95e: 4619 mov r1, r3 800d960: 487e ldr r0, [pc, #504] @ (800db5c ) 800d962: f002 f801 bl 800f968 GPIO_InitStruct.Pin = GPIO_PIN_2; 800d966: 2304 movs r3, #4 800d968: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800d96a: 2300 movs r3, #0 800d96c: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800d96e: 2300 movs r3, #0 800d970: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800d972: f107 0330 add.w r3, r7, #48 @ 0x30 800d976: 4619 mov r1, r3 800d978: 4879 ldr r0, [pc, #484] @ (800db60 ) 800d97a: f001 fff5 bl 800f968 /* UART5 interrupt Init */ HAL_NVIC_SetPriority(UART5_IRQn, 0, 0); 800d97e: 2200 movs r2, #0 800d980: 2100 movs r1, #0 800d982: 2035 movs r0, #53 @ 0x35 800d984: f001 fe5b bl 800f63e HAL_NVIC_EnableIRQ(UART5_IRQn); 800d988: 2035 movs r0, #53 @ 0x35 800d98a: f001 fe74 bl 800f676 HAL_NVIC_EnableIRQ(USART3_IRQn); /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } 800d98e: e0dc b.n 800db4a else if(uartHandle->Instance==USART1) 800d990: 687b ldr r3, [r7, #4] 800d992: 681b ldr r3, [r3, #0] 800d994: 4a73 ldr r2, [pc, #460] @ (800db64 ) 800d996: 4293 cmp r3, r2 800d998: d13a bne.n 800da10 __HAL_RCC_USART1_CLK_ENABLE(); 800d99a: 4b6f ldr r3, [pc, #444] @ (800db58 ) 800d99c: 699b ldr r3, [r3, #24] 800d99e: 4a6e ldr r2, [pc, #440] @ (800db58 ) 800d9a0: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800d9a4: 6193 str r3, [r2, #24] 800d9a6: 4b6c ldr r3, [pc, #432] @ (800db58 ) 800d9a8: 699b ldr r3, [r3, #24] 800d9aa: f403 4380 and.w r3, r3, #16384 @ 0x4000 800d9ae: 623b str r3, [r7, #32] 800d9b0: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOA_CLK_ENABLE(); 800d9b2: 4b69 ldr r3, [pc, #420] @ (800db58 ) 800d9b4: 699b ldr r3, [r3, #24] 800d9b6: 4a68 ldr r2, [pc, #416] @ (800db58 ) 800d9b8: f043 0304 orr.w r3, r3, #4 800d9bc: 6193 str r3, [r2, #24] 800d9be: 4b66 ldr r3, [pc, #408] @ (800db58 ) 800d9c0: 699b ldr r3, [r3, #24] 800d9c2: f003 0304 and.w r3, r3, #4 800d9c6: 61fb str r3, [r7, #28] 800d9c8: 69fb ldr r3, [r7, #28] GPIO_InitStruct.Pin = GPIO_PIN_9; 800d9ca: f44f 7300 mov.w r3, #512 @ 0x200 800d9ce: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800d9d0: 2302 movs r3, #2 800d9d2: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800d9d4: 2303 movs r3, #3 800d9d6: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800d9d8: f107 0330 add.w r3, r7, #48 @ 0x30 800d9dc: 4619 mov r1, r3 800d9de: 4862 ldr r0, [pc, #392] @ (800db68 ) 800d9e0: f001 ffc2 bl 800f968 GPIO_InitStruct.Pin = GPIO_PIN_10; 800d9e4: f44f 6380 mov.w r3, #1024 @ 0x400 800d9e8: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800d9ea: 2300 movs r3, #0 800d9ec: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800d9ee: 2300 movs r3, #0 800d9f0: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800d9f2: f107 0330 add.w r3, r7, #48 @ 0x30 800d9f6: 4619 mov r1, r3 800d9f8: 485b ldr r0, [pc, #364] @ (800db68 ) 800d9fa: f001 ffb5 bl 800f968 HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 800d9fe: 2200 movs r2, #0 800da00: 2100 movs r1, #0 800da02: 2025 movs r0, #37 @ 0x25 800da04: f001 fe1b bl 800f63e HAL_NVIC_EnableIRQ(USART1_IRQn); 800da08: 2025 movs r0, #37 @ 0x25 800da0a: f001 fe34 bl 800f676 } 800da0e: e09c b.n 800db4a else if(uartHandle->Instance==USART2) 800da10: 687b ldr r3, [r7, #4] 800da12: 681b ldr r3, [r3, #0] 800da14: 4a55 ldr r2, [pc, #340] @ (800db6c ) 800da16: 4293 cmp r3, r2 800da18: d146 bne.n 800daa8 __HAL_RCC_USART2_CLK_ENABLE(); 800da1a: 4b4f ldr r3, [pc, #316] @ (800db58 ) 800da1c: 69db ldr r3, [r3, #28] 800da1e: 4a4e ldr r2, [pc, #312] @ (800db58 ) 800da20: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800da24: 61d3 str r3, [r2, #28] 800da26: 4b4c ldr r3, [pc, #304] @ (800db58 ) 800da28: 69db ldr r3, [r3, #28] 800da2a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800da2e: 61bb str r3, [r7, #24] 800da30: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOD_CLK_ENABLE(); 800da32: 4b49 ldr r3, [pc, #292] @ (800db58 ) 800da34: 699b ldr r3, [r3, #24] 800da36: 4a48 ldr r2, [pc, #288] @ (800db58 ) 800da38: f043 0320 orr.w r3, r3, #32 800da3c: 6193 str r3, [r2, #24] 800da3e: 4b46 ldr r3, [pc, #280] @ (800db58 ) 800da40: 699b ldr r3, [r3, #24] 800da42: f003 0320 and.w r3, r3, #32 800da46: 617b str r3, [r7, #20] 800da48: 697b ldr r3, [r7, #20] GPIO_InitStruct.Pin = GPIO_PIN_5; 800da4a: 2320 movs r3, #32 800da4c: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800da4e: 2302 movs r3, #2 800da50: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800da52: 2303 movs r3, #3 800da54: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800da56: f107 0330 add.w r3, r7, #48 @ 0x30 800da5a: 4619 mov r1, r3 800da5c: 4840 ldr r0, [pc, #256] @ (800db60 ) 800da5e: f001 ff83 bl 800f968 GPIO_InitStruct.Pin = GPIO_PIN_6; 800da62: 2340 movs r3, #64 @ 0x40 800da64: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800da66: 2300 movs r3, #0 800da68: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800da6a: 2300 movs r3, #0 800da6c: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800da6e: f107 0330 add.w r3, r7, #48 @ 0x30 800da72: 4619 mov r1, r3 800da74: 483a ldr r0, [pc, #232] @ (800db60 ) 800da76: f001 ff77 bl 800f968 __HAL_AFIO_REMAP_USART2_ENABLE(); 800da7a: 4b3d ldr r3, [pc, #244] @ (800db70 ) 800da7c: 685b ldr r3, [r3, #4] 800da7e: 643b str r3, [r7, #64] @ 0x40 800da80: 6c3b ldr r3, [r7, #64] @ 0x40 800da82: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800da86: 643b str r3, [r7, #64] @ 0x40 800da88: 6c3b ldr r3, [r7, #64] @ 0x40 800da8a: f043 0308 orr.w r3, r3, #8 800da8e: 643b str r3, [r7, #64] @ 0x40 800da90: 4a37 ldr r2, [pc, #220] @ (800db70 ) 800da92: 6c3b ldr r3, [r7, #64] @ 0x40 800da94: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); 800da96: 2200 movs r2, #0 800da98: 2100 movs r1, #0 800da9a: 2026 movs r0, #38 @ 0x26 800da9c: f001 fdcf bl 800f63e HAL_NVIC_EnableIRQ(USART2_IRQn); 800daa0: 2026 movs r0, #38 @ 0x26 800daa2: f001 fde8 bl 800f676 } 800daa6: e050 b.n 800db4a else if(uartHandle->Instance==USART3) 800daa8: 687b ldr r3, [r7, #4] 800daaa: 681b ldr r3, [r3, #0] 800daac: 4a31 ldr r2, [pc, #196] @ (800db74 ) 800daae: 4293 cmp r3, r2 800dab0: d14b bne.n 800db4a __HAL_RCC_USART3_CLK_ENABLE(); 800dab2: 4b29 ldr r3, [pc, #164] @ (800db58 ) 800dab4: 69db ldr r3, [r3, #28] 800dab6: 4a28 ldr r2, [pc, #160] @ (800db58 ) 800dab8: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800dabc: 61d3 str r3, [r2, #28] 800dabe: 4b26 ldr r3, [pc, #152] @ (800db58 ) 800dac0: 69db ldr r3, [r3, #28] 800dac2: f403 2380 and.w r3, r3, #262144 @ 0x40000 800dac6: 613b str r3, [r7, #16] 800dac8: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 800daca: 4b23 ldr r3, [pc, #140] @ (800db58 ) 800dacc: 699b ldr r3, [r3, #24] 800dace: 4a22 ldr r2, [pc, #136] @ (800db58 ) 800dad0: f043 0310 orr.w r3, r3, #16 800dad4: 6193 str r3, [r2, #24] 800dad6: 4b20 ldr r3, [pc, #128] @ (800db58 ) 800dad8: 699b ldr r3, [r3, #24] 800dada: f003 0310 and.w r3, r3, #16 800dade: 60fb str r3, [r7, #12] 800dae0: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_10; 800dae2: f44f 6380 mov.w r3, #1024 @ 0x400 800dae6: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800dae8: 2302 movs r3, #2 800daea: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800daec: 2303 movs r3, #3 800daee: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800daf0: f107 0330 add.w r3, r7, #48 @ 0x30 800daf4: 4619 mov r1, r3 800daf6: 4819 ldr r0, [pc, #100] @ (800db5c ) 800daf8: f001 ff36 bl 800f968 GPIO_InitStruct.Pin = GPIO_PIN_11; 800dafc: f44f 6300 mov.w r3, #2048 @ 0x800 800db00: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800db02: 2300 movs r3, #0 800db04: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800db06: 2300 movs r3, #0 800db08: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800db0a: f107 0330 add.w r3, r7, #48 @ 0x30 800db0e: 4619 mov r1, r3 800db10: 4812 ldr r0, [pc, #72] @ (800db5c ) 800db12: f001 ff29 bl 800f968 __HAL_AFIO_REMAP_USART3_PARTIAL(); 800db16: 4b16 ldr r3, [pc, #88] @ (800db70 ) 800db18: 685b ldr r3, [r3, #4] 800db1a: 647b str r3, [r7, #68] @ 0x44 800db1c: 6c7b ldr r3, [r7, #68] @ 0x44 800db1e: f023 0330 bic.w r3, r3, #48 @ 0x30 800db22: 647b str r3, [r7, #68] @ 0x44 800db24: 6c7b ldr r3, [r7, #68] @ 0x44 800db26: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800db2a: 647b str r3, [r7, #68] @ 0x44 800db2c: 6c7b ldr r3, [r7, #68] @ 0x44 800db2e: f043 0310 orr.w r3, r3, #16 800db32: 647b str r3, [r7, #68] @ 0x44 800db34: 4a0e ldr r2, [pc, #56] @ (800db70 ) 800db36: 6c7b ldr r3, [r7, #68] @ 0x44 800db38: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); 800db3a: 2200 movs r2, #0 800db3c: 2100 movs r1, #0 800db3e: 2027 movs r0, #39 @ 0x27 800db40: f001 fd7d bl 800f63e HAL_NVIC_EnableIRQ(USART3_IRQn); 800db44: 2027 movs r0, #39 @ 0x27 800db46: f001 fd96 bl 800f676 } 800db4a: bf00 nop 800db4c: 3748 adds r7, #72 @ 0x48 800db4e: 46bd mov sp, r7 800db50: bd80 pop {r7, pc} 800db52: bf00 nop 800db54: 40005000 .word 0x40005000 800db58: 40021000 .word 0x40021000 800db5c: 40011000 .word 0x40011000 800db60: 40011400 .word 0x40011400 800db64: 40013800 .word 0x40013800 800db68: 40010800 .word 0x40010800 800db6c: 40004400 .word 0x40004400 800db70: 40010000 .word 0x40010000 800db74: 40004800 .word 0x40004800 0800db78 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 800db78: f8df d034 ldr.w sp, [pc, #52] @ 800dbb0 /* Call the clock system initialization function.*/ bl SystemInit 800db7c: f7ff fc4a bl 800d414 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 800db80: 480c ldr r0, [pc, #48] @ (800dbb4 ) ldr r1, =_edata 800db82: 490d ldr r1, [pc, #52] @ (800dbb8 ) ldr r2, =_sidata 800db84: 4a0d ldr r2, [pc, #52] @ (800dbbc ) movs r3, #0 800db86: 2300 movs r3, #0 b LoopCopyDataInit 800db88: e002 b.n 800db90 0800db8a : CopyDataInit: ldr r4, [r2, r3] 800db8a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800db8c: 50c4 str r4, [r0, r3] adds r3, r3, #4 800db8e: 3304 adds r3, #4 0800db90 : LoopCopyDataInit: adds r4, r0, r3 800db90: 18c4 adds r4, r0, r3 cmp r4, r1 800db92: 428c cmp r4, r1 bcc CopyDataInit 800db94: d3f9 bcc.n 800db8a /* Zero fill the bss segment. */ ldr r2, =_sbss 800db96: 4a0a ldr r2, [pc, #40] @ (800dbc0 ) ldr r4, =_ebss 800db98: 4c0a ldr r4, [pc, #40] @ (800dbc4 ) movs r3, #0 800db9a: 2300 movs r3, #0 b LoopFillZerobss 800db9c: e001 b.n 800dba2 0800db9e : FillZerobss: str r3, [r2] 800db9e: 6013 str r3, [r2, #0] adds r2, r2, #4 800dba0: 3204 adds r2, #4 0800dba2 : LoopFillZerobss: cmp r2, r4 800dba2: 42a2 cmp r2, r4 bcc FillZerobss 800dba4: d3fb bcc.n 800db9e /* Call static constructors */ bl __libc_init_array 800dba6: f006 f897 bl 8013cd8 <__libc_init_array> /* Call the application's entry point.*/ bl main 800dbaa: f7fc fe4b bl 800a844
bx lr 800dbae: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 800dbb0: 20010000 .word 0x20010000 ldr r0, =_sdata 800dbb4: 20000000 .word 0x20000000 ldr r1, =_edata 800dbb8: 20000254 .word 0x20000254 ldr r2, =_sidata 800dbbc: 08016764 .word 0x08016764 ldr r2, =_sbss 800dbc0: 20000258 .word 0x20000258 ldr r4, =_ebss 800dbc4: 20001354 .word 0x20001354 0800dbc8 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 800dbc8: e7fe b.n 800dbc8 ... 0800dbcc : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800dbcc: b580 push {r7, lr} 800dbce: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 800dbd0: 4b08 ldr r3, [pc, #32] @ (800dbf4 ) 800dbd2: 681b ldr r3, [r3, #0] 800dbd4: 4a07 ldr r2, [pc, #28] @ (800dbf4 ) 800dbd6: f043 0310 orr.w r3, r3, #16 800dbda: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800dbdc: 2003 movs r0, #3 800dbde: f001 fd23 bl 800f628 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800dbe2: 200f movs r0, #15 800dbe4: f000 f808 bl 800dbf8 /* Init the low level hardware */ HAL_MspInit(); 800dbe8: f7ff fac0 bl 800d16c /* Return function status */ return HAL_OK; 800dbec: 2300 movs r3, #0 } 800dbee: 4618 mov r0, r3 800dbf0: bd80 pop {r7, pc} 800dbf2: bf00 nop 800dbf4: 40022000 .word 0x40022000 0800dbf8 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800dbf8: b580 push {r7, lr} 800dbfa: b082 sub sp, #8 800dbfc: af00 add r7, sp, #0 800dbfe: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 800dc00: 4b12 ldr r3, [pc, #72] @ (800dc4c ) 800dc02: 681a ldr r2, [r3, #0] 800dc04: 4b12 ldr r3, [pc, #72] @ (800dc50 ) 800dc06: 781b ldrb r3, [r3, #0] 800dc08: 4619 mov r1, r3 800dc0a: f44f 737a mov.w r3, #1000 @ 0x3e8 800dc0e: fbb3 f3f1 udiv r3, r3, r1 800dc12: fbb2 f3f3 udiv r3, r2, r3 800dc16: 4618 mov r0, r3 800dc18: f001 fd3b bl 800f692 800dc1c: 4603 mov r3, r0 800dc1e: 2b00 cmp r3, #0 800dc20: d001 beq.n 800dc26 { return HAL_ERROR; 800dc22: 2301 movs r3, #1 800dc24: e00e b.n 800dc44 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800dc26: 687b ldr r3, [r7, #4] 800dc28: 2b0f cmp r3, #15 800dc2a: d80a bhi.n 800dc42 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800dc2c: 2200 movs r2, #0 800dc2e: 6879 ldr r1, [r7, #4] 800dc30: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800dc34: f001 fd03 bl 800f63e uwTickPrio = TickPriority; 800dc38: 4a06 ldr r2, [pc, #24] @ (800dc54 ) 800dc3a: 687b ldr r3, [r7, #4] 800dc3c: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800dc3e: 2300 movs r3, #0 800dc40: e000 b.n 800dc44 return HAL_ERROR; 800dc42: 2301 movs r3, #1 } 800dc44: 4618 mov r0, r3 800dc46: 3708 adds r7, #8 800dc48: 46bd mov sp, r7 800dc4a: bd80 pop {r7, pc} 800dc4c: 20000080 .word 0x20000080 800dc50: 20000088 .word 0x20000088 800dc54: 20000084 .word 0x20000084 0800dc58 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800dc58: b480 push {r7} 800dc5a: af00 add r7, sp, #0 uwTick += uwTickFreq; 800dc5c: 4b05 ldr r3, [pc, #20] @ (800dc74 ) 800dc5e: 781b ldrb r3, [r3, #0] 800dc60: 461a mov r2, r3 800dc62: 4b05 ldr r3, [pc, #20] @ (800dc78 ) 800dc64: 681b ldr r3, [r3, #0] 800dc66: 4413 add r3, r2 800dc68: 4a03 ldr r2, [pc, #12] @ (800dc78 ) 800dc6a: 6013 str r3, [r2, #0] } 800dc6c: bf00 nop 800dc6e: 46bd mov sp, r7 800dc70: bc80 pop {r7} 800dc72: 4770 bx lr 800dc74: 20000088 .word 0x20000088 800dc78: 20001204 .word 0x20001204 0800dc7c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 800dc7c: b480 push {r7} 800dc7e: af00 add r7, sp, #0 return uwTick; 800dc80: 4b02 ldr r3, [pc, #8] @ (800dc8c ) 800dc82: 681b ldr r3, [r3, #0] } 800dc84: 4618 mov r0, r3 800dc86: 46bd mov sp, r7 800dc88: bc80 pop {r7} 800dc8a: 4770 bx lr 800dc8c: 20001204 .word 0x20001204 0800dc90 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 800dc90: b580 push {r7, lr} 800dc92: b084 sub sp, #16 800dc94: af00 add r7, sp, #0 800dc96: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800dc98: f7ff fff0 bl 800dc7c 800dc9c: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800dc9e: 687b ldr r3, [r7, #4] 800dca0: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800dca2: 68fb ldr r3, [r7, #12] 800dca4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800dca8: d005 beq.n 800dcb6 { wait += (uint32_t)(uwTickFreq); 800dcaa: 4b0a ldr r3, [pc, #40] @ (800dcd4 ) 800dcac: 781b ldrb r3, [r3, #0] 800dcae: 461a mov r2, r3 800dcb0: 68fb ldr r3, [r7, #12] 800dcb2: 4413 add r3, r2 800dcb4: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 800dcb6: bf00 nop 800dcb8: f7ff ffe0 bl 800dc7c 800dcbc: 4602 mov r2, r0 800dcbe: 68bb ldr r3, [r7, #8] 800dcc0: 1ad3 subs r3, r2, r3 800dcc2: 68fa ldr r2, [r7, #12] 800dcc4: 429a cmp r2, r3 800dcc6: d8f7 bhi.n 800dcb8 { } } 800dcc8: bf00 nop 800dcca: bf00 nop 800dccc: 3710 adds r7, #16 800dcce: 46bd mov sp, r7 800dcd0: bd80 pop {r7, pc} 800dcd2: bf00 nop 800dcd4: 20000088 .word 0x20000088 0800dcd8 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 800dcd8: b580 push {r7, lr} 800dcda: b086 sub sp, #24 800dcdc: af00 add r7, sp, #0 800dcde: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800dce0: 2300 movs r3, #0 800dce2: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 800dce4: 2300 movs r3, #0 800dce6: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 800dce8: 2300 movs r3, #0 800dcea: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 800dcec: 2300 movs r3, #0 800dcee: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 800dcf0: 687b ldr r3, [r7, #4] 800dcf2: 2b00 cmp r3, #0 800dcf4: d101 bne.n 800dcfa { return HAL_ERROR; 800dcf6: 2301 movs r3, #1 800dcf8: e0be b.n 800de78 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 800dcfa: 687b ldr r3, [r7, #4] 800dcfc: 689b ldr r3, [r3, #8] 800dcfe: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 800dd00: 687b ldr r3, [r7, #4] 800dd02: 6a9b ldr r3, [r3, #40] @ 0x28 800dd04: 2b00 cmp r3, #0 800dd06: d109 bne.n 800dd1c { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 800dd08: 687b ldr r3, [r7, #4] 800dd0a: 2200 movs r2, #0 800dd0c: 62da str r2, [r3, #44] @ 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 800dd0e: 687b ldr r3, [r7, #4] 800dd10: 2200 movs r2, #0 800dd12: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800dd16: 6878 ldr r0, [r7, #4] 800dd18: f7fb fc44 bl 80095a4 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800dd1c: 6878 ldr r0, [r7, #4] 800dd1e: f000 fbf1 bl 800e504 800dd22: 4603 mov r3, r0 800dd24: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 800dd26: 687b ldr r3, [r7, #4] 800dd28: 6a9b ldr r3, [r3, #40] @ 0x28 800dd2a: f003 0310 and.w r3, r3, #16 800dd2e: 2b00 cmp r3, #0 800dd30: f040 8099 bne.w 800de66 800dd34: 7dfb ldrb r3, [r7, #23] 800dd36: 2b00 cmp r3, #0 800dd38: f040 8095 bne.w 800de66 (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800dd3c: 687b ldr r3, [r7, #4] 800dd3e: 6a9b ldr r3, [r3, #40] @ 0x28 800dd40: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800dd44: f023 0302 bic.w r3, r3, #2 800dd48: f043 0202 orr.w r2, r3, #2 800dd4c: 687b ldr r3, [r7, #4] 800dd4e: 629a str r2, [r3, #40] @ 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 800dd50: 687b ldr r3, [r7, #4] 800dd52: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800dd54: 687b ldr r3, [r7, #4] 800dd56: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 800dd58: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 800dd5a: 687b ldr r3, [r7, #4] 800dd5c: 7b1b ldrb r3, [r3, #12] 800dd5e: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800dd60: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 800dd62: 68ba ldr r2, [r7, #8] 800dd64: 4313 orrs r3, r2 800dd66: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 800dd68: 687b ldr r3, [r7, #4] 800dd6a: 689b ldr r3, [r3, #8] 800dd6c: f5b3 7f80 cmp.w r3, #256 @ 0x100 800dd70: d003 beq.n 800dd7a 800dd72: 687b ldr r3, [r7, #4] 800dd74: 689b ldr r3, [r3, #8] 800dd76: 2b01 cmp r3, #1 800dd78: d102 bne.n 800dd80 800dd7a: f44f 7380 mov.w r3, #256 @ 0x100 800dd7e: e000 b.n 800dd82 800dd80: 2300 movs r3, #0 800dd82: 693a ldr r2, [r7, #16] 800dd84: 4313 orrs r3, r2 800dd86: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 800dd88: 687b ldr r3, [r7, #4] 800dd8a: 7d1b ldrb r3, [r3, #20] 800dd8c: 2b01 cmp r3, #1 800dd8e: d119 bne.n 800ddc4 { if (hadc->Init.ContinuousConvMode == DISABLE) 800dd90: 687b ldr r3, [r7, #4] 800dd92: 7b1b ldrb r3, [r3, #12] 800dd94: 2b00 cmp r3, #0 800dd96: d109 bne.n 800ddac { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 800dd98: 687b ldr r3, [r7, #4] 800dd9a: 699b ldr r3, [r3, #24] 800dd9c: 3b01 subs r3, #1 800dd9e: 035a lsls r2, r3, #13 800dda0: 693b ldr r3, [r7, #16] 800dda2: 4313 orrs r3, r2 800dda4: f443 6300 orr.w r3, r3, #2048 @ 0x800 800dda8: 613b str r3, [r7, #16] 800ddaa: e00b b.n 800ddc4 { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800ddac: 687b ldr r3, [r7, #4] 800ddae: 6a9b ldr r3, [r3, #40] @ 0x28 800ddb0: f043 0220 orr.w r2, r3, #32 800ddb4: 687b ldr r3, [r7, #4] 800ddb6: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800ddb8: 687b ldr r3, [r7, #4] 800ddba: 6adb ldr r3, [r3, #44] @ 0x2c 800ddbc: f043 0201 orr.w r2, r3, #1 800ddc0: 687b ldr r3, [r7, #4] 800ddc2: 62da str r2, [r3, #44] @ 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 800ddc4: 687b ldr r3, [r7, #4] 800ddc6: 681b ldr r3, [r3, #0] 800ddc8: 685b ldr r3, [r3, #4] 800ddca: f423 4169 bic.w r1, r3, #59648 @ 0xe900 800ddce: 687b ldr r3, [r7, #4] 800ddd0: 681b ldr r3, [r3, #0] 800ddd2: 693a ldr r2, [r7, #16] 800ddd4: 430a orrs r2, r1 800ddd6: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 800ddd8: 687b ldr r3, [r7, #4] 800ddda: 681b ldr r3, [r3, #0] 800dddc: 689a ldr r2, [r3, #8] 800ddde: 4b28 ldr r3, [pc, #160] @ (800de80 ) 800dde0: 4013 ands r3, r2 800dde2: 687a ldr r2, [r7, #4] 800dde4: 6812 ldr r2, [r2, #0] 800dde6: 68b9 ldr r1, [r7, #8] 800dde8: 430b orrs r3, r1 800ddea: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 800ddec: 687b ldr r3, [r7, #4] 800ddee: 689b ldr r3, [r3, #8] 800ddf0: f5b3 7f80 cmp.w r3, #256 @ 0x100 800ddf4: d003 beq.n 800ddfe 800ddf6: 687b ldr r3, [r7, #4] 800ddf8: 689b ldr r3, [r3, #8] 800ddfa: 2b01 cmp r3, #1 800ddfc: d104 bne.n 800de08 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 800ddfe: 687b ldr r3, [r7, #4] 800de00: 691b ldr r3, [r3, #16] 800de02: 3b01 subs r3, #1 800de04: 051b lsls r3, r3, #20 800de06: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 800de08: 687b ldr r3, [r7, #4] 800de0a: 681b ldr r3, [r3, #0] 800de0c: 6adb ldr r3, [r3, #44] @ 0x2c 800de0e: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 800de12: 687b ldr r3, [r7, #4] 800de14: 681b ldr r3, [r3, #0] 800de16: 68fa ldr r2, [r7, #12] 800de18: 430a orrs r2, r1 800de1a: 62da str r2, [r3, #44] @ 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800de1c: 687b ldr r3, [r7, #4] 800de1e: 681b ldr r3, [r3, #0] 800de20: 689a ldr r2, [r3, #8] 800de22: 4b18 ldr r3, [pc, #96] @ (800de84 ) 800de24: 4013 ands r3, r2 800de26: 68ba ldr r2, [r7, #8] 800de28: 429a cmp r2, r3 800de2a: d10b bne.n 800de44 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 800de2c: 687b ldr r3, [r7, #4] 800de2e: 2200 movs r2, #0 800de30: 62da str r2, [r3, #44] @ 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 800de32: 687b ldr r3, [r7, #4] 800de34: 6a9b ldr r3, [r3, #40] @ 0x28 800de36: f023 0303 bic.w r3, r3, #3 800de3a: f043 0201 orr.w r2, r3, #1 800de3e: 687b ldr r3, [r7, #4] 800de40: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800de42: e018 b.n 800de76 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800de44: 687b ldr r3, [r7, #4] 800de46: 6a9b ldr r3, [r3, #40] @ 0x28 800de48: f023 0312 bic.w r3, r3, #18 800de4c: f043 0210 orr.w r2, r3, #16 800de50: 687b ldr r3, [r7, #4] 800de52: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800de54: 687b ldr r3, [r7, #4] 800de56: 6adb ldr r3, [r3, #44] @ 0x2c 800de58: f043 0201 orr.w r2, r3, #1 800de5c: 687b ldr r3, [r7, #4] 800de5e: 62da str r2, [r3, #44] @ 0x2c tmp_hal_status = HAL_ERROR; 800de60: 2301 movs r3, #1 800de62: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800de64: e007 b.n 800de76 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800de66: 687b ldr r3, [r7, #4] 800de68: 6a9b ldr r3, [r3, #40] @ 0x28 800de6a: f043 0210 orr.w r2, r3, #16 800de6e: 687b ldr r3, [r7, #4] 800de70: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800de72: 2301 movs r3, #1 800de74: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800de76: 7dfb ldrb r3, [r7, #23] } 800de78: 4618 mov r0, r3 800de7a: 3718 adds r7, #24 800de7c: 46bd mov sp, r7 800de7e: bd80 pop {r7, pc} 800de80: ffe1f7fd .word 0xffe1f7fd 800de84: ff1f0efe .word 0xff1f0efe 0800de88 : * Interruptions enabled in this function: None. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { 800de88: b580 push {r7, lr} 800de8a: b084 sub sp, #16 800de8c: af00 add r7, sp, #0 800de8e: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800de90: 2300 movs r3, #0 800de92: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800de94: 687b ldr r3, [r7, #4] 800de96: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800de9a: 2b01 cmp r3, #1 800de9c: d101 bne.n 800dea2 800de9e: 2302 movs r3, #2 800dea0: e098 b.n 800dfd4 800dea2: 687b ldr r3, [r7, #4] 800dea4: 2201 movs r2, #1 800dea6: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 800deaa: 6878 ldr r0, [r7, #4] 800deac: f000 fad0 bl 800e450 800deb0: 4603 mov r3, r0 800deb2: 73fb strb r3, [r7, #15] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800deb4: 7bfb ldrb r3, [r7, #15] 800deb6: 2b00 cmp r3, #0 800deb8: f040 8087 bne.w 800dfca { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 800debc: 687b ldr r3, [r7, #4] 800debe: 6a9b ldr r3, [r3, #40] @ 0x28 800dec0: f423 7340 bic.w r3, r3, #768 @ 0x300 800dec4: f023 0301 bic.w r3, r3, #1 800dec8: f443 7280 orr.w r2, r3, #256 @ 0x100 800decc: 687b ldr r3, [r7, #4] 800dece: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 800ded0: 687b ldr r3, [r7, #4] 800ded2: 681b ldr r3, [r3, #0] 800ded4: 4a41 ldr r2, [pc, #260] @ (800dfdc ) 800ded6: 4293 cmp r3, r2 800ded8: d105 bne.n 800dee6 800deda: 4b41 ldr r3, [pc, #260] @ (800dfe0 ) 800dedc: 685b ldr r3, [r3, #4] 800dede: f403 2370 and.w r3, r3, #983040 @ 0xf0000 800dee2: 2b00 cmp r3, #0 800dee4: d115 bne.n 800df12 { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800dee6: 687b ldr r3, [r7, #4] 800dee8: 6a9b ldr r3, [r3, #40] @ 0x28 800deea: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 800deee: 687b ldr r3, [r7, #4] 800def0: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800def2: 687b ldr r3, [r7, #4] 800def4: 681b ldr r3, [r3, #0] 800def6: 685b ldr r3, [r3, #4] 800def8: f403 6380 and.w r3, r3, #1024 @ 0x400 800defc: 2b00 cmp r3, #0 800defe: d026 beq.n 800df4e { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800df00: 687b ldr r3, [r7, #4] 800df02: 6a9b ldr r3, [r3, #40] @ 0x28 800df04: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800df08: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800df0c: 687b ldr r3, [r7, #4] 800df0e: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800df10: e01d b.n 800df4e } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800df12: 687b ldr r3, [r7, #4] 800df14: 6a9b ldr r3, [r3, #40] @ 0x28 800df16: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800df1a: 687b ldr r3, [r7, #4] 800df1c: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 800df1e: 687b ldr r3, [r7, #4] 800df20: 681b ldr r3, [r3, #0] 800df22: 4a2f ldr r2, [pc, #188] @ (800dfe0 ) 800df24: 4293 cmp r3, r2 800df26: d004 beq.n 800df32 800df28: 687b ldr r3, [r7, #4] 800df2a: 681b ldr r3, [r3, #0] 800df2c: 4a2b ldr r2, [pc, #172] @ (800dfdc ) 800df2e: 4293 cmp r3, r2 800df30: d10d bne.n 800df4e 800df32: 4b2b ldr r3, [pc, #172] @ (800dfe0 ) 800df34: 685b ldr r3, [r3, #4] 800df36: f403 6380 and.w r3, r3, #1024 @ 0x400 800df3a: 2b00 cmp r3, #0 800df3c: d007 beq.n 800df4e { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800df3e: 687b ldr r3, [r7, #4] 800df40: 6a9b ldr r3, [r3, #40] @ 0x28 800df42: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800df46: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800df4a: 687b ldr r3, [r7, #4] 800df4c: 629a str r2, [r3, #40] @ 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800df4e: 687b ldr r3, [r7, #4] 800df50: 6a9b ldr r3, [r3, #40] @ 0x28 800df52: f403 5380 and.w r3, r3, #4096 @ 0x1000 800df56: 2b00 cmp r3, #0 800df58: d006 beq.n 800df68 { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 800df5a: 687b ldr r3, [r7, #4] 800df5c: 6adb ldr r3, [r3, #44] @ 0x2c 800df5e: f023 0206 bic.w r2, r3, #6 800df62: 687b ldr r3, [r7, #4] 800df64: 62da str r2, [r3, #44] @ 0x2c 800df66: e002 b.n 800df6e } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 800df68: 687b ldr r3, [r7, #4] 800df6a: 2200 movs r2, #0 800df6c: 62da str r2, [r3, #44] @ 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 800df6e: 687b ldr r3, [r7, #4] 800df70: 2200 movs r2, #0 800df72: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Clear regular group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 800df76: 687b ldr r3, [r7, #4] 800df78: 681b ldr r3, [r3, #0] 800df7a: f06f 0202 mvn.w r2, #2 800df7e: 601a str r2, [r3, #0] /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ /* If ADC is master, ADC is enabled and conversion is started. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800df80: 687b ldr r3, [r7, #4] 800df82: 681b ldr r3, [r3, #0] 800df84: 689b ldr r3, [r3, #8] 800df86: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800df8a: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800df8e: d113 bne.n 800dfb8 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 800df90: 687b ldr r3, [r7, #4] 800df92: 681b ldr r3, [r3, #0] if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800df94: 4a11 ldr r2, [pc, #68] @ (800dfdc ) 800df96: 4293 cmp r3, r2 800df98: d105 bne.n 800dfa6 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 800df9a: 4b11 ldr r3, [pc, #68] @ (800dfe0 ) 800df9c: 685b ldr r3, [r3, #4] 800df9e: f403 2370 and.w r3, r3, #983040 @ 0xf0000 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800dfa2: 2b00 cmp r3, #0 800dfa4: d108 bne.n 800dfb8 { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 800dfa6: 687b ldr r3, [r7, #4] 800dfa8: 681b ldr r3, [r3, #0] 800dfaa: 689a ldr r2, [r3, #8] 800dfac: 687b ldr r3, [r7, #4] 800dfae: 681b ldr r3, [r3, #0] 800dfb0: f442 02a0 orr.w r2, r2, #5242880 @ 0x500000 800dfb4: 609a str r2, [r3, #8] 800dfb6: e00c b.n 800dfd2 } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 800dfb8: 687b ldr r3, [r7, #4] 800dfba: 681b ldr r3, [r3, #0] 800dfbc: 689a ldr r2, [r3, #8] 800dfbe: 687b ldr r3, [r7, #4] 800dfc0: 681b ldr r3, [r3, #0] 800dfc2: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 800dfc6: 609a str r2, [r3, #8] 800dfc8: e003 b.n 800dfd2 } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 800dfca: 687b ldr r3, [r7, #4] 800dfcc: 2200 movs r2, #0 800dfce: f883 2024 strb.w r2, [r3, #36] @ 0x24 } /* Return function status */ return tmp_hal_status; 800dfd2: 7bfb ldrb r3, [r7, #15] } 800dfd4: 4618 mov r0, r3 800dfd6: 3710 adds r7, #16 800dfd8: 46bd mov sp, r7 800dfda: bd80 pop {r7, pc} 800dfdc: 40012800 .word 0x40012800 800dfe0: 40012400 .word 0x40012400 0800dfe4 : * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { 800dfe4: b580 push {r7, lr} 800dfe6: b084 sub sp, #16 800dfe8: af00 add r7, sp, #0 800dfea: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800dfec: 2300 movs r3, #0 800dfee: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800dff0: 687b ldr r3, [r7, #4] 800dff2: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800dff6: 2b01 cmp r3, #1 800dff8: d101 bne.n 800dffe 800dffa: 2302 movs r3, #2 800dffc: e01a b.n 800e034 800dffe: 687b ldr r3, [r7, #4] 800e000: 2201 movs r2, #1 800e002: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800e006: 6878 ldr r0, [r7, #4] 800e008: f000 fa7c bl 800e504 800e00c: 4603 mov r3, r0 800e00e: 73fb strb r3, [r7, #15] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 800e010: 7bfb ldrb r3, [r7, #15] 800e012: 2b00 cmp r3, #0 800e014: d109 bne.n 800e02a { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e016: 687b ldr r3, [r7, #4] 800e018: 6a9b ldr r3, [r3, #40] @ 0x28 800e01a: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800e01e: f023 0301 bic.w r3, r3, #1 800e022: f043 0201 orr.w r2, r3, #1 800e026: 687b ldr r3, [r7, #4] 800e028: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 800e02a: 687b ldr r3, [r7, #4] 800e02c: 2200 movs r2, #0 800e02e: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800e032: 7bfb ldrb r3, [r7, #15] } 800e034: 4618 mov r0, r3 800e036: 3710 adds r7, #16 800e038: 46bd mov sp, r7 800e03a: bd80 pop {r7, pc} 0800e03c : * @param hadc: ADC handle * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { 800e03c: b590 push {r4, r7, lr} 800e03e: b087 sub sp, #28 800e040: af00 add r7, sp, #0 800e042: 6078 str r0, [r7, #4] 800e044: 6039 str r1, [r7, #0] uint32_t tickstart = 0U; 800e046: 2300 movs r3, #0 800e048: 617b str r3, [r7, #20] /* Variables for polling in case of scan mode enabled and polling for each */ /* conversion. */ __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; 800e04a: 2300 movs r3, #0 800e04c: 60fb str r3, [r7, #12] uint32_t Conversion_Timeout_CPU_cycles_max = 0U; 800e04e: 2300 movs r3, #0 800e050: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Get tick count */ tickstart = HAL_GetTick(); 800e052: f7ff fe13 bl 800dc7c 800e056: 6178 str r0, [r7, #20] /* Verification that ADC configuration is compliant with polling for */ /* each conversion: */ /* Particular case is ADC configured in DMA mode */ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) 800e058: 687b ldr r3, [r7, #4] 800e05a: 681b ldr r3, [r3, #0] 800e05c: 689b ldr r3, [r3, #8] 800e05e: f403 7380 and.w r3, r3, #256 @ 0x100 800e062: 2b00 cmp r3, #0 800e064: d00b beq.n 800e07e { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800e066: 687b ldr r3, [r7, #4] 800e068: 6a9b ldr r3, [r3, #40] @ 0x28 800e06a: f043 0220 orr.w r2, r3, #32 800e06e: 687b ldr r3, [r7, #4] 800e070: 629a str r2, [r3, #40] @ 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 800e072: 687b ldr r3, [r7, #4] 800e074: 2200 movs r2, #0 800e076: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e07a: 2301 movs r3, #1 800e07c: e0d3 b.n 800e226 /* from ADC conversion time (selected sampling time + conversion time of */ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ /* As flag EOC is not set after each conversion, no timeout status can */ /* be set. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 800e07e: 687b ldr r3, [r7, #4] 800e080: 681b ldr r3, [r3, #0] 800e082: 685b ldr r3, [r3, #4] 800e084: f403 7380 and.w r3, r3, #256 @ 0x100 800e088: 2b00 cmp r3, #0 800e08a: d131 bne.n 800e0f0 HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ) 800e08c: 687b ldr r3, [r7, #4] 800e08e: 681b ldr r3, [r3, #0] 800e090: 6adb ldr r3, [r3, #44] @ 0x2c 800e092: f403 0370 and.w r3, r3, #15728640 @ 0xf00000 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 800e096: 2b00 cmp r3, #0 800e098: d12a bne.n 800e0f0 { /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 800e09a: e021 b.n 800e0e0 { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 800e09c: 683b ldr r3, [r7, #0] 800e09e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800e0a2: d01d beq.n 800e0e0 { if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) 800e0a4: 683b ldr r3, [r7, #0] 800e0a6: 2b00 cmp r3, #0 800e0a8: d007 beq.n 800e0ba 800e0aa: f7ff fde7 bl 800dc7c 800e0ae: 4602 mov r2, r0 800e0b0: 697b ldr r3, [r7, #20] 800e0b2: 1ad3 subs r3, r2, r3 800e0b4: 683a ldr r2, [r7, #0] 800e0b6: 429a cmp r2, r3 800e0b8: d212 bcs.n 800e0e0 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 800e0ba: 687b ldr r3, [r7, #4] 800e0bc: 681b ldr r3, [r3, #0] 800e0be: 681b ldr r3, [r3, #0] 800e0c0: f003 0302 and.w r3, r3, #2 800e0c4: 2b00 cmp r3, #0 800e0c6: d10b bne.n 800e0e0 { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 800e0c8: 687b ldr r3, [r7, #4] 800e0ca: 6a9b ldr r3, [r3, #40] @ 0x28 800e0cc: f043 0204 orr.w r2, r3, #4 800e0d0: 687b ldr r3, [r7, #4] 800e0d2: 629a str r2, [r3, #40] @ 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 800e0d4: 687b ldr r3, [r7, #4] 800e0d6: 2200 movs r2, #0 800e0d8: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_TIMEOUT; 800e0dc: 2303 movs r3, #3 800e0de: e0a2 b.n 800e226 while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 800e0e0: 687b ldr r3, [r7, #4] 800e0e2: 681b ldr r3, [r3, #0] 800e0e4: 681b ldr r3, [r3, #0] 800e0e6: f003 0302 and.w r3, r3, #2 800e0ea: 2b00 cmp r3, #0 800e0ec: d0d6 beq.n 800e09c if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 800e0ee: e070 b.n 800e1d2 /* Replace polling by wait for maximum conversion time */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ /* and ADC maximum conversion cycles on all channels. */ /* - Wait for the expected ADC clock cycles delay */ Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 800e0f0: 4b4f ldr r3, [pc, #316] @ (800e230 ) 800e0f2: 681c ldr r4, [r3, #0] 800e0f4: 2002 movs r0, #2 800e0f6: f002 fd05 bl 8010b04 800e0fa: 4603 mov r3, r0 800e0fc: fbb4 f2f3 udiv r2, r4, r3 * ADC_CONVCYCLES_MAX_RANGE(hadc) ); 800e100: 687b ldr r3, [r7, #4] 800e102: 681b ldr r3, [r3, #0] 800e104: 6919 ldr r1, [r3, #16] 800e106: 4b4b ldr r3, [pc, #300] @ (800e234 ) 800e108: 400b ands r3, r1 800e10a: 2b00 cmp r3, #0 800e10c: d118 bne.n 800e140 800e10e: 687b ldr r3, [r7, #4] 800e110: 681b ldr r3, [r3, #0] 800e112: 68d9 ldr r1, [r3, #12] 800e114: 4b48 ldr r3, [pc, #288] @ (800e238 ) 800e116: 400b ands r3, r1 800e118: 2b00 cmp r3, #0 800e11a: d111 bne.n 800e140 800e11c: 687b ldr r3, [r7, #4] 800e11e: 681b ldr r3, [r3, #0] 800e120: 6919 ldr r1, [r3, #16] 800e122: 4b46 ldr r3, [pc, #280] @ (800e23c ) 800e124: 400b ands r3, r1 800e126: 2b00 cmp r3, #0 800e128: d108 bne.n 800e13c 800e12a: 687b ldr r3, [r7, #4] 800e12c: 681b ldr r3, [r3, #0] 800e12e: 68d9 ldr r1, [r3, #12] 800e130: 4b43 ldr r3, [pc, #268] @ (800e240 ) 800e132: 400b ands r3, r1 800e134: 2b00 cmp r3, #0 800e136: d101 bne.n 800e13c 800e138: 2314 movs r3, #20 800e13a: e020 b.n 800e17e 800e13c: 2329 movs r3, #41 @ 0x29 800e13e: e01e b.n 800e17e 800e140: 687b ldr r3, [r7, #4] 800e142: 681b ldr r3, [r3, #0] 800e144: 6919 ldr r1, [r3, #16] 800e146: 4b3d ldr r3, [pc, #244] @ (800e23c ) 800e148: 400b ands r3, r1 800e14a: 2b00 cmp r3, #0 800e14c: d106 bne.n 800e15c 800e14e: 687b ldr r3, [r7, #4] 800e150: 681b ldr r3, [r3, #0] 800e152: 68d9 ldr r1, [r3, #12] 800e154: 4b3a ldr r3, [pc, #232] @ (800e240 ) 800e156: 400b ands r3, r1 800e158: 2b00 cmp r3, #0 800e15a: d00d beq.n 800e178 800e15c: 687b ldr r3, [r7, #4] 800e15e: 681b ldr r3, [r3, #0] 800e160: 6919 ldr r1, [r3, #16] 800e162: 4b38 ldr r3, [pc, #224] @ (800e244 ) 800e164: 400b ands r3, r1 800e166: 2b00 cmp r3, #0 800e168: d108 bne.n 800e17c 800e16a: 687b ldr r3, [r7, #4] 800e16c: 681b ldr r3, [r3, #0] 800e16e: 68d9 ldr r1, [r3, #12] 800e170: 4b34 ldr r3, [pc, #208] @ (800e244 ) 800e172: 400b ands r3, r1 800e174: 2b00 cmp r3, #0 800e176: d101 bne.n 800e17c 800e178: 2354 movs r3, #84 @ 0x54 800e17a: e000 b.n 800e17e 800e17c: 23fc movs r3, #252 @ 0xfc Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock 800e17e: fb02 f303 mul.w r3, r2, r3 800e182: 613b str r3, [r7, #16] while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 800e184: e021 b.n 800e1ca { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 800e186: 683b ldr r3, [r7, #0] 800e188: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800e18c: d01a beq.n 800e1c4 { if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) 800e18e: 683b ldr r3, [r7, #0] 800e190: 2b00 cmp r3, #0 800e192: d007 beq.n 800e1a4 800e194: f7ff fd72 bl 800dc7c 800e198: 4602 mov r2, r0 800e19a: 697b ldr r3, [r7, #20] 800e19c: 1ad3 subs r3, r2, r3 800e19e: 683a ldr r2, [r7, #0] 800e1a0: 429a cmp r2, r3 800e1a2: d20f bcs.n 800e1c4 { /* New check to avoid false timeout detection in case of preemption */ if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 800e1a4: 68fb ldr r3, [r7, #12] 800e1a6: 693a ldr r2, [r7, #16] 800e1a8: 429a cmp r2, r3 800e1aa: d90b bls.n 800e1c4 { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 800e1ac: 687b ldr r3, [r7, #4] 800e1ae: 6a9b ldr r3, [r3, #40] @ 0x28 800e1b0: f043 0204 orr.w r2, r3, #4 800e1b4: 687b ldr r3, [r7, #4] 800e1b6: 629a str r2, [r3, #40] @ 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 800e1b8: 687b ldr r3, [r7, #4] 800e1ba: 2200 movs r2, #0 800e1bc: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_TIMEOUT; 800e1c0: 2303 movs r3, #3 800e1c2: e030 b.n 800e226 } } } Conversion_Timeout_CPU_cycles ++; 800e1c4: 68fb ldr r3, [r7, #12] 800e1c6: 3301 adds r3, #1 800e1c8: 60fb str r3, [r7, #12] while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 800e1ca: 68fb ldr r3, [r7, #12] 800e1cc: 693a ldr r2, [r7, #16] 800e1ce: 429a cmp r2, r3 800e1d0: d8d9 bhi.n 800e186 } } /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 800e1d2: 687b ldr r3, [r7, #4] 800e1d4: 681b ldr r3, [r3, #0] 800e1d6: f06f 0212 mvn.w r2, #18 800e1da: 601a str r2, [r3, #0] /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800e1dc: 687b ldr r3, [r7, #4] 800e1de: 6a9b ldr r3, [r3, #40] @ 0x28 800e1e0: f443 7200 orr.w r2, r3, #512 @ 0x200 800e1e4: 687b ldr r3, [r7, #4] 800e1e6: 629a str r2, [r3, #40] @ 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e1e8: 687b ldr r3, [r7, #4] 800e1ea: 681b ldr r3, [r3, #0] 800e1ec: 689b ldr r3, [r3, #8] 800e1ee: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800e1f2: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e1f6: d115 bne.n 800e224 (hadc->Init.ContinuousConvMode == DISABLE) ) 800e1f8: 687b ldr r3, [r7, #4] 800e1fa: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e1fc: 2b00 cmp r3, #0 800e1fe: d111 bne.n 800e224 { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800e200: 687b ldr r3, [r7, #4] 800e202: 6a9b ldr r3, [r3, #40] @ 0x28 800e204: f423 7280 bic.w r2, r3, #256 @ 0x100 800e208: 687b ldr r3, [r7, #4] 800e20a: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800e20c: 687b ldr r3, [r7, #4] 800e20e: 6a9b ldr r3, [r3, #40] @ 0x28 800e210: f403 5380 and.w r3, r3, #4096 @ 0x1000 800e214: 2b00 cmp r3, #0 800e216: d105 bne.n 800e224 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800e218: 687b ldr r3, [r7, #4] 800e21a: 6a9b ldr r3, [r3, #40] @ 0x28 800e21c: f043 0201 orr.w r2, r3, #1 800e220: 687b ldr r3, [r7, #4] 800e222: 629a str r2, [r3, #40] @ 0x28 } } /* Return ADC state */ return HAL_OK; 800e224: 2300 movs r3, #0 } 800e226: 4618 mov r0, r3 800e228: 371c adds r7, #28 800e22a: 46bd mov sp, r7 800e22c: bd90 pop {r4, r7, pc} 800e22e: bf00 nop 800e230: 20000080 .word 0x20000080 800e234: 24924924 .word 0x24924924 800e238: 00924924 .word 0x00924924 800e23c: 12492492 .word 0x12492492 800e240: 00492492 .word 0x00492492 800e244: 00249249 .word 0x00249249 0800e248 : * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc: ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { 800e248: b480 push {r7} 800e24a: b083 sub sp, #12 800e24c: af00 add r7, sp, #0 800e24e: 6078 str r0, [r7, #4] /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; 800e250: 687b ldr r3, [r7, #4] 800e252: 681b ldr r3, [r3, #0] 800e254: 6cdb ldr r3, [r3, #76] @ 0x4c } 800e256: 4618 mov r0, r3 800e258: 370c adds r7, #12 800e25a: 46bd mov sp, r7 800e25c: bc80 pop {r7} 800e25e: 4770 bx lr 0800e260 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 800e260: b480 push {r7} 800e262: b085 sub sp, #20 800e264: af00 add r7, sp, #0 800e266: 6078 str r0, [r7, #4] 800e268: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e26a: 2300 movs r3, #0 800e26c: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 800e26e: 2300 movs r3, #0 800e270: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 800e272: 687b ldr r3, [r7, #4] 800e274: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800e278: 2b01 cmp r3, #1 800e27a: d101 bne.n 800e280 800e27c: 2302 movs r3, #2 800e27e: e0dc b.n 800e43a 800e280: 687b ldr r3, [r7, #4] 800e282: 2201 movs r2, #1 800e284: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 800e288: 683b ldr r3, [r7, #0] 800e28a: 685b ldr r3, [r3, #4] 800e28c: 2b06 cmp r3, #6 800e28e: d81c bhi.n 800e2ca { MODIFY_REG(hadc->Instance->SQR3 , 800e290: 687b ldr r3, [r7, #4] 800e292: 681b ldr r3, [r3, #0] 800e294: 6b59 ldr r1, [r3, #52] @ 0x34 800e296: 683b ldr r3, [r7, #0] 800e298: 685a ldr r2, [r3, #4] 800e29a: 4613 mov r3, r2 800e29c: 009b lsls r3, r3, #2 800e29e: 4413 add r3, r2 800e2a0: 3b05 subs r3, #5 800e2a2: 221f movs r2, #31 800e2a4: fa02 f303 lsl.w r3, r2, r3 800e2a8: 43db mvns r3, r3 800e2aa: 4019 ands r1, r3 800e2ac: 683b ldr r3, [r7, #0] 800e2ae: 6818 ldr r0, [r3, #0] 800e2b0: 683b ldr r3, [r7, #0] 800e2b2: 685a ldr r2, [r3, #4] 800e2b4: 4613 mov r3, r2 800e2b6: 009b lsls r3, r3, #2 800e2b8: 4413 add r3, r2 800e2ba: 3b05 subs r3, #5 800e2bc: fa00 f203 lsl.w r2, r0, r3 800e2c0: 687b ldr r3, [r7, #4] 800e2c2: 681b ldr r3, [r3, #0] 800e2c4: 430a orrs r2, r1 800e2c6: 635a str r2, [r3, #52] @ 0x34 800e2c8: e03c b.n 800e344 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 800e2ca: 683b ldr r3, [r7, #0] 800e2cc: 685b ldr r3, [r3, #4] 800e2ce: 2b0c cmp r3, #12 800e2d0: d81c bhi.n 800e30c { MODIFY_REG(hadc->Instance->SQR2 , 800e2d2: 687b ldr r3, [r7, #4] 800e2d4: 681b ldr r3, [r3, #0] 800e2d6: 6b19 ldr r1, [r3, #48] @ 0x30 800e2d8: 683b ldr r3, [r7, #0] 800e2da: 685a ldr r2, [r3, #4] 800e2dc: 4613 mov r3, r2 800e2de: 009b lsls r3, r3, #2 800e2e0: 4413 add r3, r2 800e2e2: 3b23 subs r3, #35 @ 0x23 800e2e4: 221f movs r2, #31 800e2e6: fa02 f303 lsl.w r3, r2, r3 800e2ea: 43db mvns r3, r3 800e2ec: 4019 ands r1, r3 800e2ee: 683b ldr r3, [r7, #0] 800e2f0: 6818 ldr r0, [r3, #0] 800e2f2: 683b ldr r3, [r7, #0] 800e2f4: 685a ldr r2, [r3, #4] 800e2f6: 4613 mov r3, r2 800e2f8: 009b lsls r3, r3, #2 800e2fa: 4413 add r3, r2 800e2fc: 3b23 subs r3, #35 @ 0x23 800e2fe: fa00 f203 lsl.w r2, r0, r3 800e302: 687b ldr r3, [r7, #4] 800e304: 681b ldr r3, [r3, #0] 800e306: 430a orrs r2, r1 800e308: 631a str r2, [r3, #48] @ 0x30 800e30a: e01b b.n 800e344 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 800e30c: 687b ldr r3, [r7, #4] 800e30e: 681b ldr r3, [r3, #0] 800e310: 6ad9 ldr r1, [r3, #44] @ 0x2c 800e312: 683b ldr r3, [r7, #0] 800e314: 685a ldr r2, [r3, #4] 800e316: 4613 mov r3, r2 800e318: 009b lsls r3, r3, #2 800e31a: 4413 add r3, r2 800e31c: 3b41 subs r3, #65 @ 0x41 800e31e: 221f movs r2, #31 800e320: fa02 f303 lsl.w r3, r2, r3 800e324: 43db mvns r3, r3 800e326: 4019 ands r1, r3 800e328: 683b ldr r3, [r7, #0] 800e32a: 6818 ldr r0, [r3, #0] 800e32c: 683b ldr r3, [r7, #0] 800e32e: 685a ldr r2, [r3, #4] 800e330: 4613 mov r3, r2 800e332: 009b lsls r3, r3, #2 800e334: 4413 add r3, r2 800e336: 3b41 subs r3, #65 @ 0x41 800e338: fa00 f203 lsl.w r2, r0, r3 800e33c: 687b ldr r3, [r7, #4] 800e33e: 681b ldr r3, [r3, #0] 800e340: 430a orrs r2, r1 800e342: 62da str r2, [r3, #44] @ 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 800e344: 683b ldr r3, [r7, #0] 800e346: 681b ldr r3, [r3, #0] 800e348: 2b09 cmp r3, #9 800e34a: d91c bls.n 800e386 { MODIFY_REG(hadc->Instance->SMPR1 , 800e34c: 687b ldr r3, [r7, #4] 800e34e: 681b ldr r3, [r3, #0] 800e350: 68d9 ldr r1, [r3, #12] 800e352: 683b ldr r3, [r7, #0] 800e354: 681a ldr r2, [r3, #0] 800e356: 4613 mov r3, r2 800e358: 005b lsls r3, r3, #1 800e35a: 4413 add r3, r2 800e35c: 3b1e subs r3, #30 800e35e: 2207 movs r2, #7 800e360: fa02 f303 lsl.w r3, r2, r3 800e364: 43db mvns r3, r3 800e366: 4019 ands r1, r3 800e368: 683b ldr r3, [r7, #0] 800e36a: 6898 ldr r0, [r3, #8] 800e36c: 683b ldr r3, [r7, #0] 800e36e: 681a ldr r2, [r3, #0] 800e370: 4613 mov r3, r2 800e372: 005b lsls r3, r3, #1 800e374: 4413 add r3, r2 800e376: 3b1e subs r3, #30 800e378: fa00 f203 lsl.w r2, r0, r3 800e37c: 687b ldr r3, [r7, #4] 800e37e: 681b ldr r3, [r3, #0] 800e380: 430a orrs r2, r1 800e382: 60da str r2, [r3, #12] 800e384: e019 b.n 800e3ba ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 800e386: 687b ldr r3, [r7, #4] 800e388: 681b ldr r3, [r3, #0] 800e38a: 6919 ldr r1, [r3, #16] 800e38c: 683b ldr r3, [r7, #0] 800e38e: 681a ldr r2, [r3, #0] 800e390: 4613 mov r3, r2 800e392: 005b lsls r3, r3, #1 800e394: 4413 add r3, r2 800e396: 2207 movs r2, #7 800e398: fa02 f303 lsl.w r3, r2, r3 800e39c: 43db mvns r3, r3 800e39e: 4019 ands r1, r3 800e3a0: 683b ldr r3, [r7, #0] 800e3a2: 6898 ldr r0, [r3, #8] 800e3a4: 683b ldr r3, [r7, #0] 800e3a6: 681a ldr r2, [r3, #0] 800e3a8: 4613 mov r3, r2 800e3aa: 005b lsls r3, r3, #1 800e3ac: 4413 add r3, r2 800e3ae: fa00 f203 lsl.w r2, r0, r3 800e3b2: 687b ldr r3, [r7, #4] 800e3b4: 681b ldr r3, [r3, #0] 800e3b6: 430a orrs r2, r1 800e3b8: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800e3ba: 683b ldr r3, [r7, #0] 800e3bc: 681b ldr r3, [r3, #0] 800e3be: 2b10 cmp r3, #16 800e3c0: d003 beq.n 800e3ca (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 800e3c2: 683b ldr r3, [r7, #0] 800e3c4: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800e3c6: 2b11 cmp r3, #17 800e3c8: d132 bne.n 800e430 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 800e3ca: 687b ldr r3, [r7, #4] 800e3cc: 681b ldr r3, [r3, #0] 800e3ce: 4a1d ldr r2, [pc, #116] @ (800e444 ) 800e3d0: 4293 cmp r3, r2 800e3d2: d125 bne.n 800e420 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 800e3d4: 687b ldr r3, [r7, #4] 800e3d6: 681b ldr r3, [r3, #0] 800e3d8: 689b ldr r3, [r3, #8] 800e3da: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800e3de: 2b00 cmp r3, #0 800e3e0: d126 bne.n 800e430 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 800e3e2: 687b ldr r3, [r7, #4] 800e3e4: 681b ldr r3, [r3, #0] 800e3e6: 689a ldr r2, [r3, #8] 800e3e8: 687b ldr r3, [r7, #4] 800e3ea: 681b ldr r3, [r3, #0] 800e3ec: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 800e3f0: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 800e3f2: 683b ldr r3, [r7, #0] 800e3f4: 681b ldr r3, [r3, #0] 800e3f6: 2b10 cmp r3, #16 800e3f8: d11a bne.n 800e430 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 800e3fa: 4b13 ldr r3, [pc, #76] @ (800e448 ) 800e3fc: 681b ldr r3, [r3, #0] 800e3fe: 4a13 ldr r2, [pc, #76] @ (800e44c ) 800e400: fba2 2303 umull r2, r3, r2, r3 800e404: 0c9a lsrs r2, r3, #18 800e406: 4613 mov r3, r2 800e408: 009b lsls r3, r3, #2 800e40a: 4413 add r3, r2 800e40c: 005b lsls r3, r3, #1 800e40e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e410: e002 b.n 800e418 { wait_loop_index--; 800e412: 68bb ldr r3, [r7, #8] 800e414: 3b01 subs r3, #1 800e416: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e418: 68bb ldr r3, [r7, #8] 800e41a: 2b00 cmp r3, #0 800e41c: d1f9 bne.n 800e412 800e41e: e007 b.n 800e430 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800e420: 687b ldr r3, [r7, #4] 800e422: 6a9b ldr r3, [r3, #40] @ 0x28 800e424: f043 0220 orr.w r2, r3, #32 800e428: 687b ldr r3, [r7, #4] 800e42a: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800e42c: 2301 movs r3, #1 800e42e: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 800e430: 687b ldr r3, [r7, #4] 800e432: 2200 movs r2, #0 800e434: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800e438: 7bfb ldrb r3, [r7, #15] } 800e43a: 4618 mov r0, r3 800e43c: 3714 adds r7, #20 800e43e: 46bd mov sp, r7 800e440: bc80 pop {r7} 800e442: 4770 bx lr 800e444: 40012400 .word 0x40012400 800e448: 20000080 .word 0x20000080 800e44c: 431bde83 .word 0x431bde83 0800e450 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 800e450: b580 push {r7, lr} 800e452: b084 sub sp, #16 800e454: af00 add r7, sp, #0 800e456: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800e458: 2300 movs r3, #0 800e45a: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 800e45c: 2300 movs r3, #0 800e45e: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 800e460: 687b ldr r3, [r7, #4] 800e462: 681b ldr r3, [r3, #0] 800e464: 689b ldr r3, [r3, #8] 800e466: f003 0301 and.w r3, r3, #1 800e46a: 2b01 cmp r3, #1 800e46c: d040 beq.n 800e4f0 { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 800e46e: 687b ldr r3, [r7, #4] 800e470: 681b ldr r3, [r3, #0] 800e472: 689a ldr r2, [r3, #8] 800e474: 687b ldr r3, [r7, #4] 800e476: 681b ldr r3, [r3, #0] 800e478: f042 0201 orr.w r2, r2, #1 800e47c: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 800e47e: 4b1f ldr r3, [pc, #124] @ (800e4fc ) 800e480: 681b ldr r3, [r3, #0] 800e482: 4a1f ldr r2, [pc, #124] @ (800e500 ) 800e484: fba2 2303 umull r2, r3, r2, r3 800e488: 0c9b lsrs r3, r3, #18 800e48a: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e48c: e002 b.n 800e494 { wait_loop_index--; 800e48e: 68bb ldr r3, [r7, #8] 800e490: 3b01 subs r3, #1 800e492: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800e494: 68bb ldr r3, [r7, #8] 800e496: 2b00 cmp r3, #0 800e498: d1f9 bne.n 800e48e } /* Get tick count */ tickstart = HAL_GetTick(); 800e49a: f7ff fbef bl 800dc7c 800e49e: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 800e4a0: e01f b.n 800e4e2 { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 800e4a2: f7ff fbeb bl 800dc7c 800e4a6: 4602 mov r2, r0 800e4a8: 68fb ldr r3, [r7, #12] 800e4aa: 1ad3 subs r3, r2, r3 800e4ac: 2b02 cmp r3, #2 800e4ae: d918 bls.n 800e4e2 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) 800e4b0: 687b ldr r3, [r7, #4] 800e4b2: 681b ldr r3, [r3, #0] 800e4b4: 689b ldr r3, [r3, #8] 800e4b6: f003 0301 and.w r3, r3, #1 800e4ba: 2b01 cmp r3, #1 800e4bc: d011 beq.n 800e4e2 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800e4be: 687b ldr r3, [r7, #4] 800e4c0: 6a9b ldr r3, [r3, #40] @ 0x28 800e4c2: f043 0210 orr.w r2, r3, #16 800e4c6: 687b ldr r3, [r7, #4] 800e4c8: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e4ca: 687b ldr r3, [r7, #4] 800e4cc: 6adb ldr r3, [r3, #44] @ 0x2c 800e4ce: f043 0201 orr.w r2, r3, #1 800e4d2: 687b ldr r3, [r7, #4] 800e4d4: 62da str r2, [r3, #44] @ 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 800e4d6: 687b ldr r3, [r7, #4] 800e4d8: 2200 movs r2, #0 800e4da: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e4de: 2301 movs r3, #1 800e4e0: e007 b.n 800e4f2 while(ADC_IS_ENABLE(hadc) == RESET) 800e4e2: 687b ldr r3, [r7, #4] 800e4e4: 681b ldr r3, [r3, #0] 800e4e6: 689b ldr r3, [r3, #8] 800e4e8: f003 0301 and.w r3, r3, #1 800e4ec: 2b01 cmp r3, #1 800e4ee: d1d8 bne.n 800e4a2 } } } /* Return HAL status */ return HAL_OK; 800e4f0: 2300 movs r3, #0 } 800e4f2: 4618 mov r0, r3 800e4f4: 3710 adds r7, #16 800e4f6: 46bd mov sp, r7 800e4f8: bd80 pop {r7, pc} 800e4fa: bf00 nop 800e4fc: 20000080 .word 0x20000080 800e500: 431bde83 .word 0x431bde83 0800e504 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 800e504: b580 push {r7, lr} 800e506: b084 sub sp, #16 800e508: af00 add r7, sp, #0 800e50a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800e50c: 2300 movs r3, #0 800e50e: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 800e510: 687b ldr r3, [r7, #4] 800e512: 681b ldr r3, [r3, #0] 800e514: 689b ldr r3, [r3, #8] 800e516: f003 0301 and.w r3, r3, #1 800e51a: 2b01 cmp r3, #1 800e51c: d12e bne.n 800e57c { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 800e51e: 687b ldr r3, [r7, #4] 800e520: 681b ldr r3, [r3, #0] 800e522: 689a ldr r2, [r3, #8] 800e524: 687b ldr r3, [r7, #4] 800e526: 681b ldr r3, [r3, #0] 800e528: f022 0201 bic.w r2, r2, #1 800e52c: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 800e52e: f7ff fba5 bl 800dc7c 800e532: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 800e534: e01b b.n 800e56e { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800e536: f7ff fba1 bl 800dc7c 800e53a: 4602 mov r2, r0 800e53c: 68fb ldr r3, [r7, #12] 800e53e: 1ad3 subs r3, r2, r3 800e540: 2b02 cmp r3, #2 800e542: d914 bls.n 800e56e { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 800e544: 687b ldr r3, [r7, #4] 800e546: 681b ldr r3, [r3, #0] 800e548: 689b ldr r3, [r3, #8] 800e54a: f003 0301 and.w r3, r3, #1 800e54e: 2b01 cmp r3, #1 800e550: d10d bne.n 800e56e { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800e552: 687b ldr r3, [r7, #4] 800e554: 6a9b ldr r3, [r3, #40] @ 0x28 800e556: f043 0210 orr.w r2, r3, #16 800e55a: 687b ldr r3, [r7, #4] 800e55c: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e55e: 687b ldr r3, [r7, #4] 800e560: 6adb ldr r3, [r3, #44] @ 0x2c 800e562: f043 0201 orr.w r2, r3, #1 800e566: 687b ldr r3, [r7, #4] 800e568: 62da str r2, [r3, #44] @ 0x2c return HAL_ERROR; 800e56a: 2301 movs r3, #1 800e56c: e007 b.n 800e57e while(ADC_IS_ENABLE(hadc) != RESET) 800e56e: 687b ldr r3, [r7, #4] 800e570: 681b ldr r3, [r3, #0] 800e572: 689b ldr r3, [r3, #8] 800e574: f003 0301 and.w r3, r3, #1 800e578: 2b01 cmp r3, #1 800e57a: d0dc beq.n 800e536 } } } /* Return HAL status */ return HAL_OK; 800e57c: 2300 movs r3, #0 } 800e57e: 4618 mov r0, r3 800e580: 3710 adds r7, #16 800e582: 46bd mov sp, r7 800e584: bd80 pop {r7, pc} ... 0800e588 : * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { 800e588: b590 push {r4, r7, lr} 800e58a: b087 sub sp, #28 800e58c: af00 add r7, sp, #0 800e58e: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e590: 2300 movs r3, #0 800e592: 75fb strb r3, [r7, #23] uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; 800e594: 2300 movs r3, #0 800e596: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800e598: 687b ldr r3, [r7, #4] 800e59a: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800e59e: 2b01 cmp r3, #1 800e5a0: d101 bne.n 800e5a6 800e5a2: 2302 movs r3, #2 800e5a4: e097 b.n 800e6d6 800e5a6: 687b ldr r3, [r7, #4] 800e5a8: 2201 movs r2, #1 800e5aa: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* 1. Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800e5ae: 6878 ldr r0, [r7, #4] 800e5b0: f7ff ffa8 bl 800e504 800e5b4: 4603 mov r3, r0 800e5b6: 75fb strb r3, [r7, #23] /* 2. Calibration prerequisite delay before starting the calibration. */ /* - ADC must be enabled for at least two ADC clock cycles */ tmp_hal_status = ADC_Enable(hadc); 800e5b8: 6878 ldr r0, [r7, #4] 800e5ba: f7ff ff49 bl 800e450 800e5be: 4603 mov r3, r0 800e5c0: 75fb strb r3, [r7, #23] /* Check if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800e5c2: 7dfb ldrb r3, [r7, #23] 800e5c4: 2b00 cmp r3, #0 800e5c6: f040 8081 bne.w 800e6cc { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e5ca: 687b ldr r3, [r7, #4] 800e5cc: 6a9b ldr r3, [r3, #40] @ 0x28 800e5ce: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800e5d2: f023 0302 bic.w r3, r3, #2 800e5d6: f043 0202 orr.w r2, r3, #2 800e5da: 687b ldr r3, [r7, #4] 800e5dc: 629a str r2, [r3, #40] @ 0x28 /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 800e5de: 4b40 ldr r3, [pc, #256] @ (800e6e0 ) 800e5e0: 681c ldr r4, [r3, #0] 800e5e2: 2002 movs r0, #2 800e5e4: f002 fa8e bl 8010b04 800e5e8: 4603 mov r3, r0 800e5ea: fbb4 f3f3 udiv r3, r4, r3 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); 800e5ee: 005b lsls r3, r3, #1 wait_loop_index = ((SystemCoreClock 800e5f0: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800e5f2: e002 b.n 800e5fa { wait_loop_index--; 800e5f4: 68fb ldr r3, [r7, #12] 800e5f6: 3b01 subs r3, #1 800e5f8: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800e5fa: 68fb ldr r3, [r7, #12] 800e5fc: 2b00 cmp r3, #0 800e5fe: d1f9 bne.n 800e5f4 } /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); 800e600: 687b ldr r3, [r7, #4] 800e602: 681b ldr r3, [r3, #0] 800e604: 689a ldr r2, [r3, #8] 800e606: 687b ldr r3, [r7, #4] 800e608: 681b ldr r3, [r3, #0] 800e60a: f042 0208 orr.w r2, r2, #8 800e60e: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800e610: f7ff fb34 bl 800dc7c 800e614: 6138 str r0, [r7, #16] /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800e616: e01b b.n 800e650 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800e618: f7ff fb30 bl 800dc7c 800e61c: 4602 mov r2, r0 800e61e: 693b ldr r3, [r7, #16] 800e620: 1ad3 subs r3, r2, r3 800e622: 2b0a cmp r3, #10 800e624: d914 bls.n 800e650 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800e626: 687b ldr r3, [r7, #4] 800e628: 681b ldr r3, [r3, #0] 800e62a: 689b ldr r3, [r3, #8] 800e62c: f003 0308 and.w r3, r3, #8 800e630: 2b00 cmp r3, #0 800e632: d00d beq.n 800e650 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800e634: 687b ldr r3, [r7, #4] 800e636: 6a9b ldr r3, [r3, #40] @ 0x28 800e638: f023 0312 bic.w r3, r3, #18 800e63c: f043 0210 orr.w r2, r3, #16 800e640: 687b ldr r3, [r7, #4] 800e642: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800e644: 687b ldr r3, [r7, #4] 800e646: 2200 movs r2, #0 800e648: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e64c: 2301 movs r3, #1 800e64e: e042 b.n 800e6d6 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800e650: 687b ldr r3, [r7, #4] 800e652: 681b ldr r3, [r3, #0] 800e654: 689b ldr r3, [r3, #8] 800e656: f003 0308 and.w r3, r3, #8 800e65a: 2b00 cmp r3, #0 800e65c: d1dc bne.n 800e618 } } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); 800e65e: 687b ldr r3, [r7, #4] 800e660: 681b ldr r3, [r3, #0] 800e662: 689a ldr r2, [r3, #8] 800e664: 687b ldr r3, [r7, #4] 800e666: 681b ldr r3, [r3, #0] 800e668: f042 0204 orr.w r2, r2, #4 800e66c: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800e66e: f7ff fb05 bl 800dc7c 800e672: 6138 str r0, [r7, #16] /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800e674: e01b b.n 800e6ae { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800e676: f7ff fb01 bl 800dc7c 800e67a: 4602 mov r2, r0 800e67c: 693b ldr r3, [r7, #16] 800e67e: 1ad3 subs r3, r2, r3 800e680: 2b0a cmp r3, #10 800e682: d914 bls.n 800e6ae { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800e684: 687b ldr r3, [r7, #4] 800e686: 681b ldr r3, [r3, #0] 800e688: 689b ldr r3, [r3, #8] 800e68a: f003 0304 and.w r3, r3, #4 800e68e: 2b00 cmp r3, #0 800e690: d00d beq.n 800e6ae { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800e692: 687b ldr r3, [r7, #4] 800e694: 6a9b ldr r3, [r3, #40] @ 0x28 800e696: f023 0312 bic.w r3, r3, #18 800e69a: f043 0210 orr.w r2, r3, #16 800e69e: 687b ldr r3, [r7, #4] 800e6a0: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800e6a2: 687b ldr r3, [r7, #4] 800e6a4: 2200 movs r2, #0 800e6a6: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800e6aa: 2301 movs r3, #1 800e6ac: e013 b.n 800e6d6 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800e6ae: 687b ldr r3, [r7, #4] 800e6b0: 681b ldr r3, [r3, #0] 800e6b2: 689b ldr r3, [r3, #8] 800e6b4: f003 0304 and.w r3, r3, #4 800e6b8: 2b00 cmp r3, #0 800e6ba: d1dc bne.n 800e676 } } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e6bc: 687b ldr r3, [r7, #4] 800e6be: 6a9b ldr r3, [r3, #40] @ 0x28 800e6c0: f023 0303 bic.w r3, r3, #3 800e6c4: f043 0201 orr.w r2, r3, #1 800e6c8: 687b ldr r3, [r7, #4] 800e6ca: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 800e6cc: 687b ldr r3, [r7, #4] 800e6ce: 2200 movs r2, #0 800e6d0: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800e6d4: 7dfb ldrb r3, [r7, #23] } 800e6d6: 4618 mov r0, r3 800e6d8: 371c adds r7, #28 800e6da: 46bd mov sp, r7 800e6dc: bd90 pop {r4, r7, pc} 800e6de: bf00 nop 800e6e0: 20000080 .word 0x20000080 0800e6e4 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { 800e6e4: b580 push {r7, lr} 800e6e6: b084 sub sp, #16 800e6e8: af00 add r7, sp, #0 800e6ea: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) 800e6ec: 687b ldr r3, [r7, #4] 800e6ee: 2b00 cmp r3, #0 800e6f0: d101 bne.n 800e6f6 { return HAL_ERROR; 800e6f2: 2301 movs r3, #1 800e6f4: e0ed b.n 800e8d2 /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); } #else if (hcan->State == HAL_CAN_STATE_RESET) 800e6f6: 687b ldr r3, [r7, #4] 800e6f8: f893 3020 ldrb.w r3, [r3, #32] 800e6fc: b2db uxtb r3, r3 800e6fe: 2b00 cmp r3, #0 800e700: d102 bne.n 800e708 { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); 800e702: 6878 ldr r0, [r7, #4] 800e704: f7fb fa4a bl 8009b9c } #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800e708: 687b ldr r3, [r7, #4] 800e70a: 681b ldr r3, [r3, #0] 800e70c: 681a ldr r2, [r3, #0] 800e70e: 687b ldr r3, [r7, #4] 800e710: 681b ldr r3, [r3, #0] 800e712: f042 0201 orr.w r2, r2, #1 800e716: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800e718: f7ff fab0 bl 800dc7c 800e71c: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800e71e: e012 b.n 800e746 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800e720: f7ff faac bl 800dc7c 800e724: 4602 mov r2, r0 800e726: 68fb ldr r3, [r7, #12] 800e728: 1ad3 subs r3, r2, r3 800e72a: 2b0a cmp r3, #10 800e72c: d90b bls.n 800e746 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800e72e: 687b ldr r3, [r7, #4] 800e730: 6a5b ldr r3, [r3, #36] @ 0x24 800e732: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800e736: 687b ldr r3, [r7, #4] 800e738: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800e73a: 687b ldr r3, [r7, #4] 800e73c: 2205 movs r2, #5 800e73e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800e742: 2301 movs r3, #1 800e744: e0c5 b.n 800e8d2 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800e746: 687b ldr r3, [r7, #4] 800e748: 681b ldr r3, [r3, #0] 800e74a: 685b ldr r3, [r3, #4] 800e74c: f003 0301 and.w r3, r3, #1 800e750: 2b00 cmp r3, #0 800e752: d0e5 beq.n 800e720 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800e754: 687b ldr r3, [r7, #4] 800e756: 681b ldr r3, [r3, #0] 800e758: 681a ldr r2, [r3, #0] 800e75a: 687b ldr r3, [r7, #4] 800e75c: 681b ldr r3, [r3, #0] 800e75e: f022 0202 bic.w r2, r2, #2 800e762: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800e764: f7ff fa8a bl 800dc7c 800e768: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800e76a: e012 b.n 800e792 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800e76c: f7ff fa86 bl 800dc7c 800e770: 4602 mov r2, r0 800e772: 68fb ldr r3, [r7, #12] 800e774: 1ad3 subs r3, r2, r3 800e776: 2b0a cmp r3, #10 800e778: d90b bls.n 800e792 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800e77a: 687b ldr r3, [r7, #4] 800e77c: 6a5b ldr r3, [r3, #36] @ 0x24 800e77e: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800e782: 687b ldr r3, [r7, #4] 800e784: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800e786: 687b ldr r3, [r7, #4] 800e788: 2205 movs r2, #5 800e78a: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800e78e: 2301 movs r3, #1 800e790: e09f b.n 800e8d2 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800e792: 687b ldr r3, [r7, #4] 800e794: 681b ldr r3, [r3, #0] 800e796: 685b ldr r3, [r3, #4] 800e798: f003 0302 and.w r3, r3, #2 800e79c: 2b00 cmp r3, #0 800e79e: d1e5 bne.n 800e76c } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) 800e7a0: 687b ldr r3, [r7, #4] 800e7a2: 7e1b ldrb r3, [r3, #24] 800e7a4: 2b01 cmp r3, #1 800e7a6: d108 bne.n 800e7ba { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800e7a8: 687b ldr r3, [r7, #4] 800e7aa: 681b ldr r3, [r3, #0] 800e7ac: 681a ldr r2, [r3, #0] 800e7ae: 687b ldr r3, [r7, #4] 800e7b0: 681b ldr r3, [r3, #0] 800e7b2: f042 0280 orr.w r2, r2, #128 @ 0x80 800e7b6: 601a str r2, [r3, #0] 800e7b8: e007 b.n 800e7ca } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800e7ba: 687b ldr r3, [r7, #4] 800e7bc: 681b ldr r3, [r3, #0] 800e7be: 681a ldr r2, [r3, #0] 800e7c0: 687b ldr r3, [r7, #4] 800e7c2: 681b ldr r3, [r3, #0] 800e7c4: f022 0280 bic.w r2, r2, #128 @ 0x80 800e7c8: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) 800e7ca: 687b ldr r3, [r7, #4] 800e7cc: 7e5b ldrb r3, [r3, #25] 800e7ce: 2b01 cmp r3, #1 800e7d0: d108 bne.n 800e7e4 { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800e7d2: 687b ldr r3, [r7, #4] 800e7d4: 681b ldr r3, [r3, #0] 800e7d6: 681a ldr r2, [r3, #0] 800e7d8: 687b ldr r3, [r7, #4] 800e7da: 681b ldr r3, [r3, #0] 800e7dc: f042 0240 orr.w r2, r2, #64 @ 0x40 800e7e0: 601a str r2, [r3, #0] 800e7e2: e007 b.n 800e7f4 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800e7e4: 687b ldr r3, [r7, #4] 800e7e6: 681b ldr r3, [r3, #0] 800e7e8: 681a ldr r2, [r3, #0] 800e7ea: 687b ldr r3, [r7, #4] 800e7ec: 681b ldr r3, [r3, #0] 800e7ee: f022 0240 bic.w r2, r2, #64 @ 0x40 800e7f2: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) 800e7f4: 687b ldr r3, [r7, #4] 800e7f6: 7e9b ldrb r3, [r3, #26] 800e7f8: 2b01 cmp r3, #1 800e7fa: d108 bne.n 800e80e { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800e7fc: 687b ldr r3, [r7, #4] 800e7fe: 681b ldr r3, [r3, #0] 800e800: 681a ldr r2, [r3, #0] 800e802: 687b ldr r3, [r7, #4] 800e804: 681b ldr r3, [r3, #0] 800e806: f042 0220 orr.w r2, r2, #32 800e80a: 601a str r2, [r3, #0] 800e80c: e007 b.n 800e81e } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800e80e: 687b ldr r3, [r7, #4] 800e810: 681b ldr r3, [r3, #0] 800e812: 681a ldr r2, [r3, #0] 800e814: 687b ldr r3, [r7, #4] 800e816: 681b ldr r3, [r3, #0] 800e818: f022 0220 bic.w r2, r2, #32 800e81c: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) 800e81e: 687b ldr r3, [r7, #4] 800e820: 7edb ldrb r3, [r3, #27] 800e822: 2b01 cmp r3, #1 800e824: d108 bne.n 800e838 { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800e826: 687b ldr r3, [r7, #4] 800e828: 681b ldr r3, [r3, #0] 800e82a: 681a ldr r2, [r3, #0] 800e82c: 687b ldr r3, [r7, #4] 800e82e: 681b ldr r3, [r3, #0] 800e830: f022 0210 bic.w r2, r2, #16 800e834: 601a str r2, [r3, #0] 800e836: e007 b.n 800e848 } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800e838: 687b ldr r3, [r7, #4] 800e83a: 681b ldr r3, [r3, #0] 800e83c: 681a ldr r2, [r3, #0] 800e83e: 687b ldr r3, [r7, #4] 800e840: 681b ldr r3, [r3, #0] 800e842: f042 0210 orr.w r2, r2, #16 800e846: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) 800e848: 687b ldr r3, [r7, #4] 800e84a: 7f1b ldrb r3, [r3, #28] 800e84c: 2b01 cmp r3, #1 800e84e: d108 bne.n 800e862 { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800e850: 687b ldr r3, [r7, #4] 800e852: 681b ldr r3, [r3, #0] 800e854: 681a ldr r2, [r3, #0] 800e856: 687b ldr r3, [r7, #4] 800e858: 681b ldr r3, [r3, #0] 800e85a: f042 0208 orr.w r2, r2, #8 800e85e: 601a str r2, [r3, #0] 800e860: e007 b.n 800e872 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800e862: 687b ldr r3, [r7, #4] 800e864: 681b ldr r3, [r3, #0] 800e866: 681a ldr r2, [r3, #0] 800e868: 687b ldr r3, [r7, #4] 800e86a: 681b ldr r3, [r3, #0] 800e86c: f022 0208 bic.w r2, r2, #8 800e870: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) 800e872: 687b ldr r3, [r7, #4] 800e874: 7f5b ldrb r3, [r3, #29] 800e876: 2b01 cmp r3, #1 800e878: d108 bne.n 800e88c { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800e87a: 687b ldr r3, [r7, #4] 800e87c: 681b ldr r3, [r3, #0] 800e87e: 681a ldr r2, [r3, #0] 800e880: 687b ldr r3, [r7, #4] 800e882: 681b ldr r3, [r3, #0] 800e884: f042 0204 orr.w r2, r2, #4 800e888: 601a str r2, [r3, #0] 800e88a: e007 b.n 800e89c } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800e88c: 687b ldr r3, [r7, #4] 800e88e: 681b ldr r3, [r3, #0] 800e890: 681a ldr r2, [r3, #0] 800e892: 687b ldr r3, [r7, #4] 800e894: 681b ldr r3, [r3, #0] 800e896: f022 0204 bic.w r2, r2, #4 800e89a: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | 800e89c: 687b ldr r3, [r7, #4] 800e89e: 689a ldr r2, [r3, #8] 800e8a0: 687b ldr r3, [r7, #4] 800e8a2: 68db ldr r3, [r3, #12] 800e8a4: 431a orrs r2, r3 800e8a6: 687b ldr r3, [r7, #4] 800e8a8: 691b ldr r3, [r3, #16] 800e8aa: 431a orrs r2, r3 800e8ac: 687b ldr r3, [r7, #4] 800e8ae: 695b ldr r3, [r3, #20] 800e8b0: ea42 0103 orr.w r1, r2, r3 800e8b4: 687b ldr r3, [r7, #4] 800e8b6: 685b ldr r3, [r3, #4] 800e8b8: 1e5a subs r2, r3, #1 800e8ba: 687b ldr r3, [r7, #4] 800e8bc: 681b ldr r3, [r3, #0] 800e8be: 430a orrs r2, r1 800e8c0: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800e8c2: 687b ldr r3, [r7, #4] 800e8c4: 2200 movs r2, #0 800e8c6: 625a str r2, [r3, #36] @ 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; 800e8c8: 687b ldr r3, [r7, #4] 800e8ca: 2201 movs r2, #1 800e8cc: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800e8d0: 2300 movs r3, #0 } 800e8d2: 4618 mov r0, r3 800e8d4: 3710 adds r7, #16 800e8d6: 46bd mov sp, r7 800e8d8: bd80 pop {r7, pc} ... 0800e8dc : * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) { 800e8dc: b480 push {r7} 800e8de: b087 sub sp, #28 800e8e0: af00 add r7, sp, #0 800e8e2: 6078 str r0, [r7, #4] 800e8e4: 6039 str r1, [r7, #0] uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; 800e8e6: 687b ldr r3, [r7, #4] 800e8e8: 681b ldr r3, [r3, #0] 800e8ea: 617b str r3, [r7, #20] HAL_CAN_StateTypeDef state = hcan->State; 800e8ec: 687b ldr r3, [r7, #4] 800e8ee: f893 3020 ldrb.w r3, [r3, #32] 800e8f2: 74fb strb r3, [r7, #19] if ((state == HAL_CAN_STATE_READY) || 800e8f4: 7cfb ldrb r3, [r7, #19] 800e8f6: 2b01 cmp r3, #1 800e8f8: d003 beq.n 800e902 800e8fa: 7cfb ldrb r3, [r7, #19] 800e8fc: 2b02 cmp r3, #2 800e8fe: f040 80be bne.w 800ea7e assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); #if defined(CAN2) /* CAN1 and CAN2 are dual instances with 28 common filters banks */ /* Select master instance to access the filter banks */ can_ip = CAN1; 800e902: 4b65 ldr r3, [pc, #404] @ (800ea98 ) 800e904: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); #endif /* CAN3 */ /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); 800e906: 697b ldr r3, [r7, #20] 800e908: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800e90c: f043 0201 orr.w r2, r3, #1 800e910: 697b ldr r3, [r7, #20] 800e912: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #if defined(CAN2) /* Select the start filter number of CAN2 slave instance */ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); 800e916: 697b ldr r3, [r7, #20] 800e918: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800e91c: f423 527c bic.w r2, r3, #16128 @ 0x3f00 800e920: 697b ldr r3, [r7, #20] 800e922: f8c3 2200 str.w r2, [r3, #512] @ 0x200 SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); 800e926: 697b ldr r3, [r7, #20] 800e928: f8d3 2200 ldr.w r2, [r3, #512] @ 0x200 800e92c: 683b ldr r3, [r7, #0] 800e92e: 6a5b ldr r3, [r3, #36] @ 0x24 800e930: 021b lsls r3, r3, #8 800e932: 431a orrs r2, r3 800e934: 697b ldr r3, [r7, #20] 800e936: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #endif /* CAN3 */ /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); 800e93a: 683b ldr r3, [r7, #0] 800e93c: 695b ldr r3, [r3, #20] 800e93e: f003 031f and.w r3, r3, #31 800e942: 2201 movs r2, #1 800e944: fa02 f303 lsl.w r3, r2, r3 800e948: 60fb str r3, [r7, #12] /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); 800e94a: 697b ldr r3, [r7, #20] 800e94c: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800e950: 68fb ldr r3, [r7, #12] 800e952: 43db mvns r3, r3 800e954: 401a ands r2, r3 800e956: 697b ldr r3, [r7, #20] 800e958: f8c3 221c str.w r2, [r3, #540] @ 0x21c /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) 800e95c: 683b ldr r3, [r7, #0] 800e95e: 69db ldr r3, [r3, #28] 800e960: 2b00 cmp r3, #0 800e962: d123 bne.n 800e9ac { /* 16-bit scale for the filter */ CLEAR_BIT(can_ip->FS1R, filternbrbitpos); 800e964: 697b ldr r3, [r7, #20] 800e966: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800e96a: 68fb ldr r3, [r7, #12] 800e96c: 43db mvns r3, r3 800e96e: 401a ands r2, r3 800e970: 697b ldr r3, [r7, #20] 800e972: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800e976: 683b ldr r3, [r7, #0] 800e978: 68db ldr r3, [r3, #12] 800e97a: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800e97c: 683b ldr r3, [r7, #0] 800e97e: 685b ldr r3, [r3, #4] 800e980: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800e982: 683a ldr r2, [r7, #0] 800e984: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800e986: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800e988: 697b ldr r3, [r7, #20] 800e98a: 3248 adds r2, #72 @ 0x48 800e98c: f843 1032 str.w r1, [r3, r2, lsl #3] /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800e990: 683b ldr r3, [r7, #0] 800e992: 689b ldr r3, [r3, #8] 800e994: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); 800e996: 683b ldr r3, [r7, #0] 800e998: 681b ldr r3, [r3, #0] 800e99a: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800e99c: 683b ldr r3, [r7, #0] 800e99e: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800e9a0: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800e9a2: 6979 ldr r1, [r7, #20] 800e9a4: 3348 adds r3, #72 @ 0x48 800e9a6: 00db lsls r3, r3, #3 800e9a8: 440b add r3, r1 800e9aa: 605a str r2, [r3, #4] } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) 800e9ac: 683b ldr r3, [r7, #0] 800e9ae: 69db ldr r3, [r3, #28] 800e9b0: 2b01 cmp r3, #1 800e9b2: d122 bne.n 800e9fa { /* 32-bit scale for the filter */ SET_BIT(can_ip->FS1R, filternbrbitpos); 800e9b4: 697b ldr r3, [r7, #20] 800e9b6: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800e9ba: 68fb ldr r3, [r7, #12] 800e9bc: 431a orrs r2, r3 800e9be: 697b ldr r3, [r7, #20] 800e9c0: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* 32-bit identifier or First 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800e9c4: 683b ldr r3, [r7, #0] 800e9c6: 681b ldr r3, [r3, #0] 800e9c8: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800e9ca: 683b ldr r3, [r7, #0] 800e9cc: 685b ldr r3, [r3, #4] 800e9ce: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800e9d0: 683a ldr r2, [r7, #0] 800e9d2: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800e9d4: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800e9d6: 697b ldr r3, [r7, #20] 800e9d8: 3248 adds r2, #72 @ 0x48 800e9da: f843 1032 str.w r1, [r3, r2, lsl #3] /* 32-bit mask or Second 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800e9de: 683b ldr r3, [r7, #0] 800e9e0: 689b ldr r3, [r3, #8] 800e9e2: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); 800e9e4: 683b ldr r3, [r7, #0] 800e9e6: 68db ldr r3, [r3, #12] 800e9e8: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800e9ea: 683b ldr r3, [r7, #0] 800e9ec: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800e9ee: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800e9f0: 6979 ldr r1, [r7, #20] 800e9f2: 3348 adds r3, #72 @ 0x48 800e9f4: 00db lsls r3, r3, #3 800e9f6: 440b add r3, r1 800e9f8: 605a str r2, [r3, #4] } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) 800e9fa: 683b ldr r3, [r7, #0] 800e9fc: 699b ldr r3, [r3, #24] 800e9fe: 2b00 cmp r3, #0 800ea00: d109 bne.n 800ea16 { /* Id/Mask mode for the filter*/ CLEAR_BIT(can_ip->FM1R, filternbrbitpos); 800ea02: 697b ldr r3, [r7, #20] 800ea04: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800ea08: 68fb ldr r3, [r7, #12] 800ea0a: 43db mvns r3, r3 800ea0c: 401a ands r2, r3 800ea0e: 697b ldr r3, [r7, #20] 800ea10: f8c3 2204 str.w r2, [r3, #516] @ 0x204 800ea14: e007 b.n 800ea26 } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /* Identifier list mode for the filter*/ SET_BIT(can_ip->FM1R, filternbrbitpos); 800ea16: 697b ldr r3, [r7, #20] 800ea18: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800ea1c: 68fb ldr r3, [r7, #12] 800ea1e: 431a orrs r2, r3 800ea20: 697b ldr r3, [r7, #20] 800ea22: f8c3 2204 str.w r2, [r3, #516] @ 0x204 } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) 800ea26: 683b ldr r3, [r7, #0] 800ea28: 691b ldr r3, [r3, #16] 800ea2a: 2b00 cmp r3, #0 800ea2c: d109 bne.n 800ea42 { /* FIFO 0 assignation for the filter */ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); 800ea2e: 697b ldr r3, [r7, #20] 800ea30: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800ea34: 68fb ldr r3, [r7, #12] 800ea36: 43db mvns r3, r3 800ea38: 401a ands r2, r3 800ea3a: 697b ldr r3, [r7, #20] 800ea3c: f8c3 2214 str.w r2, [r3, #532] @ 0x214 800ea40: e007 b.n 800ea52 } else { /* FIFO 1 assignation for the filter */ SET_BIT(can_ip->FFA1R, filternbrbitpos); 800ea42: 697b ldr r3, [r7, #20] 800ea44: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800ea48: 68fb ldr r3, [r7, #12] 800ea4a: 431a orrs r2, r3 800ea4c: 697b ldr r3, [r7, #20] 800ea4e: f8c3 2214 str.w r2, [r3, #532] @ 0x214 } /* Filter activation */ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) 800ea52: 683b ldr r3, [r7, #0] 800ea54: 6a1b ldr r3, [r3, #32] 800ea56: 2b01 cmp r3, #1 800ea58: d107 bne.n 800ea6a { SET_BIT(can_ip->FA1R, filternbrbitpos); 800ea5a: 697b ldr r3, [r7, #20] 800ea5c: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800ea60: 68fb ldr r3, [r7, #12] 800ea62: 431a orrs r2, r3 800ea64: 697b ldr r3, [r7, #20] 800ea66: f8c3 221c str.w r2, [r3, #540] @ 0x21c } /* Leave the initialisation mode for the filter */ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); 800ea6a: 697b ldr r3, [r7, #20] 800ea6c: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800ea70: f023 0201 bic.w r2, r3, #1 800ea74: 697b ldr r3, [r7, #20] 800ea76: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Return function status */ return HAL_OK; 800ea7a: 2300 movs r3, #0 800ea7c: e006 b.n 800ea8c } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800ea7e: 687b ldr r3, [r7, #4] 800ea80: 6a5b ldr r3, [r3, #36] @ 0x24 800ea82: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800ea86: 687b ldr r3, [r7, #4] 800ea88: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ea8a: 2301 movs r3, #1 } } 800ea8c: 4618 mov r0, r3 800ea8e: 371c adds r7, #28 800ea90: 46bd mov sp, r7 800ea92: bc80 pop {r7} 800ea94: 4770 bx lr 800ea96: bf00 nop 800ea98: 40006400 .word 0x40006400 0800ea9c : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { 800ea9c: b580 push {r7, lr} 800ea9e: b084 sub sp, #16 800eaa0: af00 add r7, sp, #0 800eaa2: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) 800eaa4: 687b ldr r3, [r7, #4] 800eaa6: f893 3020 ldrb.w r3, [r3, #32] 800eaaa: b2db uxtb r3, r3 800eaac: 2b01 cmp r3, #1 800eaae: d12e bne.n 800eb0e { /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_LISTENING; 800eab0: 687b ldr r3, [r7, #4] 800eab2: 2202 movs r2, #2 800eab4: f883 2020 strb.w r2, [r3, #32] /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800eab8: 687b ldr r3, [r7, #4] 800eaba: 681b ldr r3, [r3, #0] 800eabc: 681a ldr r2, [r3, #0] 800eabe: 687b ldr r3, [r7, #4] 800eac0: 681b ldr r3, [r3, #0] 800eac2: f022 0201 bic.w r2, r2, #1 800eac6: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800eac8: f7ff f8d8 bl 800dc7c 800eacc: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800eace: e012 b.n 800eaf6 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800ead0: f7ff f8d4 bl 800dc7c 800ead4: 4602 mov r2, r0 800ead6: 68fb ldr r3, [r7, #12] 800ead8: 1ad3 subs r3, r2, r3 800eada: 2b0a cmp r3, #10 800eadc: d90b bls.n 800eaf6 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800eade: 687b ldr r3, [r7, #4] 800eae0: 6a5b ldr r3, [r3, #36] @ 0x24 800eae2: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800eae6: 687b ldr r3, [r7, #4] 800eae8: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800eaea: 687b ldr r3, [r7, #4] 800eaec: 2205 movs r2, #5 800eaee: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800eaf2: 2301 movs r3, #1 800eaf4: e012 b.n 800eb1c while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800eaf6: 687b ldr r3, [r7, #4] 800eaf8: 681b ldr r3, [r3, #0] 800eafa: 685b ldr r3, [r3, #4] 800eafc: f003 0301 and.w r3, r3, #1 800eb00: 2b00 cmp r3, #0 800eb02: d1e5 bne.n 800ead0 } } /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800eb04: 687b ldr r3, [r7, #4] 800eb06: 2200 movs r2, #0 800eb08: 625a str r2, [r3, #36] @ 0x24 /* Return function status */ return HAL_OK; 800eb0a: 2300 movs r3, #0 800eb0c: e006 b.n 800eb1c } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; 800eb0e: 687b ldr r3, [r7, #4] 800eb10: 6a5b ldr r3, [r3, #36] @ 0x24 800eb12: f443 2200 orr.w r2, r3, #524288 @ 0x80000 800eb16: 687b ldr r3, [r7, #4] 800eb18: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800eb1a: 2301 movs r3, #1 } } 800eb1c: 4618 mov r0, r3 800eb1e: 3710 adds r7, #16 800eb20: 46bd mov sp, r7 800eb22: bd80 pop {r7, pc} 0800eb24 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { 800eb24: b580 push {r7, lr} 800eb26: b084 sub sp, #16 800eb28: af00 add r7, sp, #0 800eb2a: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_LISTENING) 800eb2c: 687b ldr r3, [r7, #4] 800eb2e: f893 3020 ldrb.w r3, [r3, #32] 800eb32: b2db uxtb r3, r3 800eb34: 2b02 cmp r3, #2 800eb36: d133 bne.n 800eba0 { /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800eb38: 687b ldr r3, [r7, #4] 800eb3a: 681b ldr r3, [r3, #0] 800eb3c: 681a ldr r2, [r3, #0] 800eb3e: 687b ldr r3, [r7, #4] 800eb40: 681b ldr r3, [r3, #0] 800eb42: f042 0201 orr.w r2, r2, #1 800eb46: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800eb48: f7ff f898 bl 800dc7c 800eb4c: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800eb4e: e012 b.n 800eb76 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800eb50: f7ff f894 bl 800dc7c 800eb54: 4602 mov r2, r0 800eb56: 68fb ldr r3, [r7, #12] 800eb58: 1ad3 subs r3, r2, r3 800eb5a: 2b0a cmp r3, #10 800eb5c: d90b bls.n 800eb76 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800eb5e: 687b ldr r3, [r7, #4] 800eb60: 6a5b ldr r3, [r3, #36] @ 0x24 800eb62: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800eb66: 687b ldr r3, [r7, #4] 800eb68: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800eb6a: 687b ldr r3, [r7, #4] 800eb6c: 2205 movs r2, #5 800eb6e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800eb72: 2301 movs r3, #1 800eb74: e01b b.n 800ebae while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800eb76: 687b ldr r3, [r7, #4] 800eb78: 681b ldr r3, [r3, #0] 800eb7a: 685b ldr r3, [r3, #4] 800eb7c: f003 0301 and.w r3, r3, #1 800eb80: 2b00 cmp r3, #0 800eb82: d0e5 beq.n 800eb50 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800eb84: 687b ldr r3, [r7, #4] 800eb86: 681b ldr r3, [r3, #0] 800eb88: 681a ldr r2, [r3, #0] 800eb8a: 687b ldr r3, [r7, #4] 800eb8c: 681b ldr r3, [r3, #0] 800eb8e: f022 0202 bic.w r2, r2, #2 800eb92: 601a str r2, [r3, #0] /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_READY; 800eb94: 687b ldr r3, [r7, #4] 800eb96: 2201 movs r2, #1 800eb98: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800eb9c: 2300 movs r3, #0 800eb9e: e006 b.n 800ebae } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; 800eba0: 687b ldr r3, [r7, #4] 800eba2: 6a5b ldr r3, [r3, #36] @ 0x24 800eba4: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800eba8: 687b ldr r3, [r7, #4] 800ebaa: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ebac: 2301 movs r3, #1 } } 800ebae: 4618 mov r0, r3 800ebb0: 3710 adds r7, #16 800ebb2: 46bd mov sp, r7 800ebb4: bd80 pop {r7, pc} 0800ebb6 : * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, const uint8_t aData[], uint32_t *pTxMailbox) { 800ebb6: b480 push {r7} 800ebb8: b089 sub sp, #36 @ 0x24 800ebba: af00 add r7, sp, #0 800ebbc: 60f8 str r0, [r7, #12] 800ebbe: 60b9 str r1, [r7, #8] 800ebc0: 607a str r2, [r7, #4] 800ebc2: 603b str r3, [r7, #0] uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; 800ebc4: 68fb ldr r3, [r7, #12] 800ebc6: f893 3020 ldrb.w r3, [r3, #32] 800ebca: 77fb strb r3, [r7, #31] uint32_t tsr = READ_REG(hcan->Instance->TSR); 800ebcc: 68fb ldr r3, [r7, #12] 800ebce: 681b ldr r3, [r3, #0] 800ebd0: 689b ldr r3, [r3, #8] 800ebd2: 61bb str r3, [r7, #24] { assert_param(IS_CAN_EXTID(pHeader->ExtId)); } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); if ((state == HAL_CAN_STATE_READY) || 800ebd4: 7ffb ldrb r3, [r7, #31] 800ebd6: 2b01 cmp r3, #1 800ebd8: d003 beq.n 800ebe2 800ebda: 7ffb ldrb r3, [r7, #31] 800ebdc: 2b02 cmp r3, #2 800ebde: f040 80ad bne.w 800ed3c (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ if (((tsr & CAN_TSR_TME0) != 0U) || 800ebe2: 69bb ldr r3, [r7, #24] 800ebe4: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800ebe8: 2b00 cmp r3, #0 800ebea: d10a bne.n 800ec02 ((tsr & CAN_TSR_TME1) != 0U) || 800ebec: 69bb ldr r3, [r7, #24] 800ebee: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 if (((tsr & CAN_TSR_TME0) != 0U) || 800ebf2: 2b00 cmp r3, #0 800ebf4: d105 bne.n 800ec02 ((tsr & CAN_TSR_TME2) != 0U)) 800ebf6: 69bb ldr r3, [r7, #24] 800ebf8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 ((tsr & CAN_TSR_TME1) != 0U) || 800ebfc: 2b00 cmp r3, #0 800ebfe: f000 8095 beq.w 800ed2c { /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; 800ec02: 69bb ldr r3, [r7, #24] 800ec04: 0e1b lsrs r3, r3, #24 800ec06: f003 0303 and.w r3, r3, #3 800ec0a: 617b str r3, [r7, #20] /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; 800ec0c: 2201 movs r2, #1 800ec0e: 697b ldr r3, [r7, #20] 800ec10: 409a lsls r2, r3 800ec12: 683b ldr r3, [r7, #0] 800ec14: 601a str r2, [r3, #0] /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) 800ec16: 68bb ldr r3, [r7, #8] 800ec18: 689b ldr r3, [r3, #8] 800ec1a: 2b00 cmp r3, #0 800ec1c: d10d bne.n 800ec3a { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800ec1e: 68bb ldr r3, [r7, #8] 800ec20: 681b ldr r3, [r3, #0] 800ec22: 055a lsls r2, r3, #21 pHeader->RTR); 800ec24: 68bb ldr r3, [r7, #8] 800ec26: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800ec28: 68f9 ldr r1, [r7, #12] 800ec2a: 6809 ldr r1, [r1, #0] 800ec2c: 431a orrs r2, r3 800ec2e: 697b ldr r3, [r7, #20] 800ec30: 3318 adds r3, #24 800ec32: 011b lsls r3, r3, #4 800ec34: 440b add r3, r1 800ec36: 601a str r2, [r3, #0] 800ec38: e00f b.n 800ec5a } else { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800ec3a: 68bb ldr r3, [r7, #8] 800ec3c: 685b ldr r3, [r3, #4] 800ec3e: 00da lsls r2, r3, #3 pHeader->IDE | 800ec40: 68bb ldr r3, [r7, #8] 800ec42: 689b ldr r3, [r3, #8] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800ec44: 431a orrs r2, r3 pHeader->RTR); 800ec46: 68bb ldr r3, [r7, #8] 800ec48: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800ec4a: 68f9 ldr r1, [r7, #12] 800ec4c: 6809 ldr r1, [r1, #0] pHeader->IDE | 800ec4e: 431a orrs r2, r3 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800ec50: 697b ldr r3, [r7, #20] 800ec52: 3318 adds r3, #24 800ec54: 011b lsls r3, r3, #4 800ec56: 440b add r3, r1 800ec58: 601a str r2, [r3, #0] } /* Set up the DLC */ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); 800ec5a: 68fb ldr r3, [r7, #12] 800ec5c: 6819 ldr r1, [r3, #0] 800ec5e: 68bb ldr r3, [r7, #8] 800ec60: 691a ldr r2, [r3, #16] 800ec62: 697b ldr r3, [r7, #20] 800ec64: 3318 adds r3, #24 800ec66: 011b lsls r3, r3, #4 800ec68: 440b add r3, r1 800ec6a: 3304 adds r3, #4 800ec6c: 601a str r2, [r3, #0] /* Set up the Transmit Global Time mode */ if (pHeader->TransmitGlobalTime == ENABLE) 800ec6e: 68bb ldr r3, [r7, #8] 800ec70: 7d1b ldrb r3, [r3, #20] 800ec72: 2b01 cmp r3, #1 800ec74: d111 bne.n 800ec9a { SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); 800ec76: 68fb ldr r3, [r7, #12] 800ec78: 681a ldr r2, [r3, #0] 800ec7a: 697b ldr r3, [r7, #20] 800ec7c: 3318 adds r3, #24 800ec7e: 011b lsls r3, r3, #4 800ec80: 4413 add r3, r2 800ec82: 3304 adds r3, #4 800ec84: 681b ldr r3, [r3, #0] 800ec86: 68fa ldr r2, [r7, #12] 800ec88: 6811 ldr r1, [r2, #0] 800ec8a: f443 7280 orr.w r2, r3, #256 @ 0x100 800ec8e: 697b ldr r3, [r7, #20] 800ec90: 3318 adds r3, #24 800ec92: 011b lsls r3, r3, #4 800ec94: 440b add r3, r1 800ec96: 3304 adds r3, #4 800ec98: 601a str r2, [r3, #0] } /* Set up the data field */ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, 800ec9a: 687b ldr r3, [r7, #4] 800ec9c: 3307 adds r3, #7 800ec9e: 781b ldrb r3, [r3, #0] 800eca0: 061a lsls r2, r3, #24 800eca2: 687b ldr r3, [r7, #4] 800eca4: 3306 adds r3, #6 800eca6: 781b ldrb r3, [r3, #0] 800eca8: 041b lsls r3, r3, #16 800ecaa: 431a orrs r2, r3 800ecac: 687b ldr r3, [r7, #4] 800ecae: 3305 adds r3, #5 800ecb0: 781b ldrb r3, [r3, #0] 800ecb2: 021b lsls r3, r3, #8 800ecb4: 4313 orrs r3, r2 800ecb6: 687a ldr r2, [r7, #4] 800ecb8: 3204 adds r2, #4 800ecba: 7812 ldrb r2, [r2, #0] 800ecbc: 4610 mov r0, r2 800ecbe: 68fa ldr r2, [r7, #12] 800ecc0: 6811 ldr r1, [r2, #0] 800ecc2: ea43 0200 orr.w r2, r3, r0 800ecc6: 697b ldr r3, [r7, #20] 800ecc8: 011b lsls r3, r3, #4 800ecca: 440b add r3, r1 800eccc: f503 73c6 add.w r3, r3, #396 @ 0x18c 800ecd0: 601a str r2, [r3, #0] ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, 800ecd2: 687b ldr r3, [r7, #4] 800ecd4: 3303 adds r3, #3 800ecd6: 781b ldrb r3, [r3, #0] 800ecd8: 061a lsls r2, r3, #24 800ecda: 687b ldr r3, [r7, #4] 800ecdc: 3302 adds r3, #2 800ecde: 781b ldrb r3, [r3, #0] 800ece0: 041b lsls r3, r3, #16 800ece2: 431a orrs r2, r3 800ece4: 687b ldr r3, [r7, #4] 800ece6: 3301 adds r3, #1 800ece8: 781b ldrb r3, [r3, #0] 800ecea: 021b lsls r3, r3, #8 800ecec: 4313 orrs r3, r2 800ecee: 687a ldr r2, [r7, #4] 800ecf0: 7812 ldrb r2, [r2, #0] 800ecf2: 4610 mov r0, r2 800ecf4: 68fa ldr r2, [r7, #12] 800ecf6: 6811 ldr r1, [r2, #0] 800ecf8: ea43 0200 orr.w r2, r3, r0 800ecfc: 697b ldr r3, [r7, #20] 800ecfe: 011b lsls r3, r3, #4 800ed00: 440b add r3, r1 800ed02: f503 73c4 add.w r3, r3, #392 @ 0x188 800ed06: 601a str r2, [r3, #0] ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); 800ed08: 68fb ldr r3, [r7, #12] 800ed0a: 681a ldr r2, [r3, #0] 800ed0c: 697b ldr r3, [r7, #20] 800ed0e: 3318 adds r3, #24 800ed10: 011b lsls r3, r3, #4 800ed12: 4413 add r3, r2 800ed14: 681b ldr r3, [r3, #0] 800ed16: 68fa ldr r2, [r7, #12] 800ed18: 6811 ldr r1, [r2, #0] 800ed1a: f043 0201 orr.w r2, r3, #1 800ed1e: 697b ldr r3, [r7, #20] 800ed20: 3318 adds r3, #24 800ed22: 011b lsls r3, r3, #4 800ed24: 440b add r3, r1 800ed26: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 800ed28: 2300 movs r3, #0 800ed2a: e00e b.n 800ed4a } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800ed2c: 68fb ldr r3, [r7, #12] 800ed2e: 6a5b ldr r3, [r3, #36] @ 0x24 800ed30: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800ed34: 68fb ldr r3, [r7, #12] 800ed36: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ed38: 2301 movs r3, #1 800ed3a: e006 b.n 800ed4a } } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800ed3c: 68fb ldr r3, [r7, #12] 800ed3e: 6a5b ldr r3, [r3, #36] @ 0x24 800ed40: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800ed44: 68fb ldr r3, [r7, #12] 800ed46: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ed48: 2301 movs r3, #1 } } 800ed4a: 4618 mov r0, r3 800ed4c: 3724 adds r7, #36 @ 0x24 800ed4e: 46bd mov sp, r7 800ed50: bc80 pop {r7} 800ed52: 4770 bx lr 0800ed54 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval Number of free Tx Mailboxes. */ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) { 800ed54: b480 push {r7} 800ed56: b085 sub sp, #20 800ed58: af00 add r7, sp, #0 800ed5a: 6078 str r0, [r7, #4] uint32_t freelevel = 0U; 800ed5c: 2300 movs r3, #0 800ed5e: 60fb str r3, [r7, #12] HAL_CAN_StateTypeDef state = hcan->State; 800ed60: 687b ldr r3, [r7, #4] 800ed62: f893 3020 ldrb.w r3, [r3, #32] 800ed66: 72fb strb r3, [r7, #11] if ((state == HAL_CAN_STATE_READY) || 800ed68: 7afb ldrb r3, [r7, #11] 800ed6a: 2b01 cmp r3, #1 800ed6c: d002 beq.n 800ed74 800ed6e: 7afb ldrb r3, [r7, #11] 800ed70: 2b02 cmp r3, #2 800ed72: d11d bne.n 800edb0 (state == HAL_CAN_STATE_LISTENING)) { /* Check Tx Mailbox 0 status */ if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) 800ed74: 687b ldr r3, [r7, #4] 800ed76: 681b ldr r3, [r3, #0] 800ed78: 689b ldr r3, [r3, #8] 800ed7a: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800ed7e: 2b00 cmp r3, #0 800ed80: d002 beq.n 800ed88 { freelevel++; 800ed82: 68fb ldr r3, [r7, #12] 800ed84: 3301 adds r3, #1 800ed86: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 1 status */ if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) 800ed88: 687b ldr r3, [r7, #4] 800ed8a: 681b ldr r3, [r3, #0] 800ed8c: 689b ldr r3, [r3, #8] 800ed8e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800ed92: 2b00 cmp r3, #0 800ed94: d002 beq.n 800ed9c { freelevel++; 800ed96: 68fb ldr r3, [r7, #12] 800ed98: 3301 adds r3, #1 800ed9a: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 2 status */ if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) 800ed9c: 687b ldr r3, [r7, #4] 800ed9e: 681b ldr r3, [r3, #0] 800eda0: 689b ldr r3, [r3, #8] 800eda2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800eda6: 2b00 cmp r3, #0 800eda8: d002 beq.n 800edb0 { freelevel++; 800edaa: 68fb ldr r3, [r7, #12] 800edac: 3301 adds r3, #1 800edae: 60fb str r3, [r7, #12] } } /* Return Tx Mailboxes free level */ return freelevel; 800edb0: 68fb ldr r3, [r7, #12] } 800edb2: 4618 mov r0, r3 800edb4: 3714 adds r7, #20 800edb6: 46bd mov sp, r7 800edb8: bc80 pop {r7} 800edba: 4770 bx lr 0800edbc : * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { 800edbc: b480 push {r7} 800edbe: b087 sub sp, #28 800edc0: af00 add r7, sp, #0 800edc2: 60f8 str r0, [r7, #12] 800edc4: 60b9 str r1, [r7, #8] 800edc6: 607a str r2, [r7, #4] 800edc8: 603b str r3, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800edca: 68fb ldr r3, [r7, #12] 800edcc: f893 3020 ldrb.w r3, [r3, #32] 800edd0: 75fb strb r3, [r7, #23] assert_param(IS_CAN_RX_FIFO(RxFifo)); if ((state == HAL_CAN_STATE_READY) || 800edd2: 7dfb ldrb r3, [r7, #23] 800edd4: 2b01 cmp r3, #1 800edd6: d003 beq.n 800ede0 800edd8: 7dfb ldrb r3, [r7, #23] 800edda: 2b02 cmp r3, #2 800eddc: f040 8103 bne.w 800efe6 (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800ede0: 68bb ldr r3, [r7, #8] 800ede2: 2b00 cmp r3, #0 800ede4: d10e bne.n 800ee04 { /* Check that the Rx FIFO 0 is not empty */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) 800ede6: 68fb ldr r3, [r7, #12] 800ede8: 681b ldr r3, [r3, #0] 800edea: 68db ldr r3, [r3, #12] 800edec: f003 0303 and.w r3, r3, #3 800edf0: 2b00 cmp r3, #0 800edf2: d116 bne.n 800ee22 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800edf4: 68fb ldr r3, [r7, #12] 800edf6: 6a5b ldr r3, [r3, #36] @ 0x24 800edf8: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800edfc: 68fb ldr r3, [r7, #12] 800edfe: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ee00: 2301 movs r3, #1 800ee02: e0f7 b.n 800eff4 } } else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) 800ee04: 68fb ldr r3, [r7, #12] 800ee06: 681b ldr r3, [r3, #0] 800ee08: 691b ldr r3, [r3, #16] 800ee0a: f003 0303 and.w r3, r3, #3 800ee0e: 2b00 cmp r3, #0 800ee10: d107 bne.n 800ee22 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800ee12: 68fb ldr r3, [r7, #12] 800ee14: 6a5b ldr r3, [r3, #36] @ 0x24 800ee16: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800ee1a: 68fb ldr r3, [r7, #12] 800ee1c: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ee1e: 2301 movs r3, #1 800ee20: e0e8 b.n 800eff4 } } /* Get the header */ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; 800ee22: 68fb ldr r3, [r7, #12] 800ee24: 681a ldr r2, [r3, #0] 800ee26: 68bb ldr r3, [r7, #8] 800ee28: 331b adds r3, #27 800ee2a: 011b lsls r3, r3, #4 800ee2c: 4413 add r3, r2 800ee2e: 681b ldr r3, [r3, #0] 800ee30: f003 0204 and.w r2, r3, #4 800ee34: 687b ldr r3, [r7, #4] 800ee36: 609a str r2, [r3, #8] if (pHeader->IDE == CAN_ID_STD) 800ee38: 687b ldr r3, [r7, #4] 800ee3a: 689b ldr r3, [r3, #8] 800ee3c: 2b00 cmp r3, #0 800ee3e: d10c bne.n 800ee5a { pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; 800ee40: 68fb ldr r3, [r7, #12] 800ee42: 681a ldr r2, [r3, #0] 800ee44: 68bb ldr r3, [r7, #8] 800ee46: 331b adds r3, #27 800ee48: 011b lsls r3, r3, #4 800ee4a: 4413 add r3, r2 800ee4c: 681b ldr r3, [r3, #0] 800ee4e: 0d5b lsrs r3, r3, #21 800ee50: f3c3 020a ubfx r2, r3, #0, #11 800ee54: 687b ldr r3, [r7, #4] 800ee56: 601a str r2, [r3, #0] 800ee58: e00b b.n 800ee72 } else { pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; 800ee5a: 68fb ldr r3, [r7, #12] 800ee5c: 681a ldr r2, [r3, #0] 800ee5e: 68bb ldr r3, [r7, #8] 800ee60: 331b adds r3, #27 800ee62: 011b lsls r3, r3, #4 800ee64: 4413 add r3, r2 800ee66: 681b ldr r3, [r3, #0] 800ee68: 08db lsrs r3, r3, #3 800ee6a: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & 800ee6e: 687b ldr r3, [r7, #4] 800ee70: 605a str r2, [r3, #4] } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); 800ee72: 68fb ldr r3, [r7, #12] 800ee74: 681a ldr r2, [r3, #0] 800ee76: 68bb ldr r3, [r7, #8] 800ee78: 331b adds r3, #27 800ee7a: 011b lsls r3, r3, #4 800ee7c: 4413 add r3, r2 800ee7e: 681b ldr r3, [r3, #0] 800ee80: f003 0202 and.w r2, r3, #2 800ee84: 687b ldr r3, [r7, #4] 800ee86: 60da str r2, [r3, #12] if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) 800ee88: 68fb ldr r3, [r7, #12] 800ee8a: 681a ldr r2, [r3, #0] 800ee8c: 68bb ldr r3, [r7, #8] 800ee8e: 331b adds r3, #27 800ee90: 011b lsls r3, r3, #4 800ee92: 4413 add r3, r2 800ee94: 3304 adds r3, #4 800ee96: 681b ldr r3, [r3, #0] 800ee98: f003 0308 and.w r3, r3, #8 800ee9c: 2b00 cmp r3, #0 800ee9e: d003 beq.n 800eea8 { /* Truncate DLC to 8 if received field is over range */ pHeader->DLC = 8U; 800eea0: 687b ldr r3, [r7, #4] 800eea2: 2208 movs r2, #8 800eea4: 611a str r2, [r3, #16] 800eea6: e00b b.n 800eec0 } else { pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; 800eea8: 68fb ldr r3, [r7, #12] 800eeaa: 681a ldr r2, [r3, #0] 800eeac: 68bb ldr r3, [r7, #8] 800eeae: 331b adds r3, #27 800eeb0: 011b lsls r3, r3, #4 800eeb2: 4413 add r3, r2 800eeb4: 3304 adds r3, #4 800eeb6: 681b ldr r3, [r3, #0] 800eeb8: f003 020f and.w r2, r3, #15 800eebc: 687b ldr r3, [r7, #4] 800eebe: 611a str r2, [r3, #16] } pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; 800eec0: 68fb ldr r3, [r7, #12] 800eec2: 681a ldr r2, [r3, #0] 800eec4: 68bb ldr r3, [r7, #8] 800eec6: 331b adds r3, #27 800eec8: 011b lsls r3, r3, #4 800eeca: 4413 add r3, r2 800eecc: 3304 adds r3, #4 800eece: 681b ldr r3, [r3, #0] 800eed0: 0a1b lsrs r3, r3, #8 800eed2: b2da uxtb r2, r3 800eed4: 687b ldr r3, [r7, #4] 800eed6: 619a str r2, [r3, #24] pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; 800eed8: 68fb ldr r3, [r7, #12] 800eeda: 681a ldr r2, [r3, #0] 800eedc: 68bb ldr r3, [r7, #8] 800eede: 331b adds r3, #27 800eee0: 011b lsls r3, r3, #4 800eee2: 4413 add r3, r2 800eee4: 3304 adds r3, #4 800eee6: 681b ldr r3, [r3, #0] 800eee8: 0c1b lsrs r3, r3, #16 800eeea: b29a uxth r2, r3 800eeec: 687b ldr r3, [r7, #4] 800eeee: 615a str r2, [r3, #20] /* Get the data */ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); 800eef0: 68fb ldr r3, [r7, #12] 800eef2: 681a ldr r2, [r3, #0] 800eef4: 68bb ldr r3, [r7, #8] 800eef6: 011b lsls r3, r3, #4 800eef8: 4413 add r3, r2 800eefa: f503 73dc add.w r3, r3, #440 @ 0x1b8 800eefe: 681b ldr r3, [r3, #0] 800ef00: b2da uxtb r2, r3 800ef02: 683b ldr r3, [r7, #0] 800ef04: 701a strb r2, [r3, #0] aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); 800ef06: 68fb ldr r3, [r7, #12] 800ef08: 681a ldr r2, [r3, #0] 800ef0a: 68bb ldr r3, [r7, #8] 800ef0c: 011b lsls r3, r3, #4 800ef0e: 4413 add r3, r2 800ef10: f503 73dc add.w r3, r3, #440 @ 0x1b8 800ef14: 681b ldr r3, [r3, #0] 800ef16: 0a1a lsrs r2, r3, #8 800ef18: 683b ldr r3, [r7, #0] 800ef1a: 3301 adds r3, #1 800ef1c: b2d2 uxtb r2, r2 800ef1e: 701a strb r2, [r3, #0] aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); 800ef20: 68fb ldr r3, [r7, #12] 800ef22: 681a ldr r2, [r3, #0] 800ef24: 68bb ldr r3, [r7, #8] 800ef26: 011b lsls r3, r3, #4 800ef28: 4413 add r3, r2 800ef2a: f503 73dc add.w r3, r3, #440 @ 0x1b8 800ef2e: 681b ldr r3, [r3, #0] 800ef30: 0c1a lsrs r2, r3, #16 800ef32: 683b ldr r3, [r7, #0] 800ef34: 3302 adds r3, #2 800ef36: b2d2 uxtb r2, r2 800ef38: 701a strb r2, [r3, #0] aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); 800ef3a: 68fb ldr r3, [r7, #12] 800ef3c: 681a ldr r2, [r3, #0] 800ef3e: 68bb ldr r3, [r7, #8] 800ef40: 011b lsls r3, r3, #4 800ef42: 4413 add r3, r2 800ef44: f503 73dc add.w r3, r3, #440 @ 0x1b8 800ef48: 681b ldr r3, [r3, #0] 800ef4a: 0e1a lsrs r2, r3, #24 800ef4c: 683b ldr r3, [r7, #0] 800ef4e: 3303 adds r3, #3 800ef50: b2d2 uxtb r2, r2 800ef52: 701a strb r2, [r3, #0] aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); 800ef54: 68fb ldr r3, [r7, #12] 800ef56: 681a ldr r2, [r3, #0] 800ef58: 68bb ldr r3, [r7, #8] 800ef5a: 011b lsls r3, r3, #4 800ef5c: 4413 add r3, r2 800ef5e: f503 73de add.w r3, r3, #444 @ 0x1bc 800ef62: 681a ldr r2, [r3, #0] 800ef64: 683b ldr r3, [r7, #0] 800ef66: 3304 adds r3, #4 800ef68: b2d2 uxtb r2, r2 800ef6a: 701a strb r2, [r3, #0] aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); 800ef6c: 68fb ldr r3, [r7, #12] 800ef6e: 681a ldr r2, [r3, #0] 800ef70: 68bb ldr r3, [r7, #8] 800ef72: 011b lsls r3, r3, #4 800ef74: 4413 add r3, r2 800ef76: f503 73de add.w r3, r3, #444 @ 0x1bc 800ef7a: 681b ldr r3, [r3, #0] 800ef7c: 0a1a lsrs r2, r3, #8 800ef7e: 683b ldr r3, [r7, #0] 800ef80: 3305 adds r3, #5 800ef82: b2d2 uxtb r2, r2 800ef84: 701a strb r2, [r3, #0] aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); 800ef86: 68fb ldr r3, [r7, #12] 800ef88: 681a ldr r2, [r3, #0] 800ef8a: 68bb ldr r3, [r7, #8] 800ef8c: 011b lsls r3, r3, #4 800ef8e: 4413 add r3, r2 800ef90: f503 73de add.w r3, r3, #444 @ 0x1bc 800ef94: 681b ldr r3, [r3, #0] 800ef96: 0c1a lsrs r2, r3, #16 800ef98: 683b ldr r3, [r7, #0] 800ef9a: 3306 adds r3, #6 800ef9c: b2d2 uxtb r2, r2 800ef9e: 701a strb r2, [r3, #0] aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); 800efa0: 68fb ldr r3, [r7, #12] 800efa2: 681a ldr r2, [r3, #0] 800efa4: 68bb ldr r3, [r7, #8] 800efa6: 011b lsls r3, r3, #4 800efa8: 4413 add r3, r2 800efaa: f503 73de add.w r3, r3, #444 @ 0x1bc 800efae: 681b ldr r3, [r3, #0] 800efb0: 0e1a lsrs r2, r3, #24 800efb2: 683b ldr r3, [r7, #0] 800efb4: 3307 adds r3, #7 800efb6: b2d2 uxtb r2, r2 800efb8: 701a strb r2, [r3, #0] /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800efba: 68bb ldr r3, [r7, #8] 800efbc: 2b00 cmp r3, #0 800efbe: d108 bne.n 800efd2 { /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); 800efc0: 68fb ldr r3, [r7, #12] 800efc2: 681b ldr r3, [r3, #0] 800efc4: 68da ldr r2, [r3, #12] 800efc6: 68fb ldr r3, [r7, #12] 800efc8: 681b ldr r3, [r3, #0] 800efca: f042 0220 orr.w r2, r2, #32 800efce: 60da str r2, [r3, #12] 800efd0: e007 b.n 800efe2 } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); 800efd2: 68fb ldr r3, [r7, #12] 800efd4: 681b ldr r3, [r3, #0] 800efd6: 691a ldr r2, [r3, #16] 800efd8: 68fb ldr r3, [r7, #12] 800efda: 681b ldr r3, [r3, #0] 800efdc: f042 0220 orr.w r2, r2, #32 800efe0: 611a str r2, [r3, #16] } /* Return function status */ return HAL_OK; 800efe2: 2300 movs r3, #0 800efe4: e006 b.n 800eff4 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800efe6: 68fb ldr r3, [r7, #12] 800efe8: 6a5b ldr r3, [r3, #36] @ 0x24 800efea: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800efee: 68fb ldr r3, [r7, #12] 800eff0: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800eff2: 2301 movs r3, #1 } } 800eff4: 4618 mov r0, r3 800eff6: 371c adds r7, #28 800eff8: 46bd mov sp, r7 800effa: bc80 pop {r7} 800effc: 4770 bx lr 0800effe : * @param ActiveITs indicates which interrupts will be enabled. * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { 800effe: b480 push {r7} 800f000: b085 sub sp, #20 800f002: af00 add r7, sp, #0 800f004: 6078 str r0, [r7, #4] 800f006: 6039 str r1, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800f008: 687b ldr r3, [r7, #4] 800f00a: f893 3020 ldrb.w r3, [r3, #32] 800f00e: 73fb strb r3, [r7, #15] /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); if ((state == HAL_CAN_STATE_READY) || 800f010: 7bfb ldrb r3, [r7, #15] 800f012: 2b01 cmp r3, #1 800f014: d002 beq.n 800f01c 800f016: 7bfb ldrb r3, [r7, #15] 800f018: 2b02 cmp r3, #2 800f01a: d109 bne.n 800f030 (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); 800f01c: 687b ldr r3, [r7, #4] 800f01e: 681b ldr r3, [r3, #0] 800f020: 6959 ldr r1, [r3, #20] 800f022: 687b ldr r3, [r7, #4] 800f024: 681b ldr r3, [r3, #0] 800f026: 683a ldr r2, [r7, #0] 800f028: 430a orrs r2, r1 800f02a: 615a str r2, [r3, #20] /* Return function status */ return HAL_OK; 800f02c: 2300 movs r3, #0 800f02e: e006 b.n 800f03e } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f030: 687b ldr r3, [r7, #4] 800f032: 6a5b ldr r3, [r3, #36] @ 0x24 800f034: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f038: 687b ldr r3, [r7, #4] 800f03a: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f03c: 2301 movs r3, #1 } } 800f03e: 4618 mov r0, r3 800f040: 3714 adds r7, #20 800f042: 46bd mov sp, r7 800f044: bc80 pop {r7} 800f046: 4770 bx lr 0800f048 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { 800f048: b580 push {r7, lr} 800f04a: b08a sub sp, #40 @ 0x28 800f04c: af00 add r7, sp, #0 800f04e: 6078 str r0, [r7, #4] uint32_t errorcode = HAL_CAN_ERROR_NONE; 800f050: 2300 movs r3, #0 800f052: 627b str r3, [r7, #36] @ 0x24 uint32_t interrupts = READ_REG(hcan->Instance->IER); 800f054: 687b ldr r3, [r7, #4] 800f056: 681b ldr r3, [r3, #0] 800f058: 695b ldr r3, [r3, #20] 800f05a: 623b str r3, [r7, #32] uint32_t msrflags = READ_REG(hcan->Instance->MSR); 800f05c: 687b ldr r3, [r7, #4] 800f05e: 681b ldr r3, [r3, #0] 800f060: 685b ldr r3, [r3, #4] 800f062: 61fb str r3, [r7, #28] uint32_t tsrflags = READ_REG(hcan->Instance->TSR); 800f064: 687b ldr r3, [r7, #4] 800f066: 681b ldr r3, [r3, #0] 800f068: 689b ldr r3, [r3, #8] 800f06a: 61bb str r3, [r7, #24] uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); 800f06c: 687b ldr r3, [r7, #4] 800f06e: 681b ldr r3, [r3, #0] 800f070: 68db ldr r3, [r3, #12] 800f072: 617b str r3, [r7, #20] uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); 800f074: 687b ldr r3, [r7, #4] 800f076: 681b ldr r3, [r3, #0] 800f078: 691b ldr r3, [r3, #16] 800f07a: 613b str r3, [r7, #16] uint32_t esrflags = READ_REG(hcan->Instance->ESR); 800f07c: 687b ldr r3, [r7, #4] 800f07e: 681b ldr r3, [r3, #0] 800f080: 699b ldr r3, [r3, #24] 800f082: 60fb str r3, [r7, #12] /* Transmit Mailbox empty interrupt management *****************************/ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) 800f084: 6a3b ldr r3, [r7, #32] 800f086: f003 0301 and.w r3, r3, #1 800f08a: 2b00 cmp r3, #0 800f08c: d07c beq.n 800f188 { /* Transmit Mailbox 0 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP0) != 0U) 800f08e: 69bb ldr r3, [r7, #24] 800f090: f003 0301 and.w r3, r3, #1 800f094: 2b00 cmp r3, #0 800f096: d023 beq.n 800f0e0 { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); 800f098: 687b ldr r3, [r7, #4] 800f09a: 681b ldr r3, [r3, #0] 800f09c: 2201 movs r2, #1 800f09e: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK0) != 0U) 800f0a0: 69bb ldr r3, [r7, #24] 800f0a2: f003 0302 and.w r3, r3, #2 800f0a6: 2b00 cmp r3, #0 800f0a8: d003 beq.n 800f0b2 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); 800f0aa: 6878 ldr r0, [r7, #4] 800f0ac: f000 f983 bl 800f3b6 800f0b0: e016 b.n 800f0e0 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST0) != 0U) 800f0b2: 69bb ldr r3, [r7, #24] 800f0b4: f003 0304 and.w r3, r3, #4 800f0b8: 2b00 cmp r3, #0 800f0ba: d004 beq.n 800f0c6 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; 800f0bc: 6a7b ldr r3, [r7, #36] @ 0x24 800f0be: f443 6300 orr.w r3, r3, #2048 @ 0x800 800f0c2: 627b str r3, [r7, #36] @ 0x24 800f0c4: e00c b.n 800f0e0 } else if ((tsrflags & CAN_TSR_TERR0) != 0U) 800f0c6: 69bb ldr r3, [r7, #24] 800f0c8: f003 0308 and.w r3, r3, #8 800f0cc: 2b00 cmp r3, #0 800f0ce: d004 beq.n 800f0da { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; 800f0d0: 6a7b ldr r3, [r7, #36] @ 0x24 800f0d2: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800f0d6: 627b str r3, [r7, #36] @ 0x24 800f0d8: e002 b.n 800f0e0 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); 800f0da: 6878 ldr r0, [r7, #4] 800f0dc: f000 f986 bl 800f3ec } } } /* Transmit Mailbox 1 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP1) != 0U) 800f0e0: 69bb ldr r3, [r7, #24] 800f0e2: f403 7380 and.w r3, r3, #256 @ 0x100 800f0e6: 2b00 cmp r3, #0 800f0e8: d024 beq.n 800f134 { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); 800f0ea: 687b ldr r3, [r7, #4] 800f0ec: 681b ldr r3, [r3, #0] 800f0ee: f44f 7280 mov.w r2, #256 @ 0x100 800f0f2: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK1) != 0U) 800f0f4: 69bb ldr r3, [r7, #24] 800f0f6: f403 7300 and.w r3, r3, #512 @ 0x200 800f0fa: 2b00 cmp r3, #0 800f0fc: d003 beq.n 800f106 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); 800f0fe: 6878 ldr r0, [r7, #4] 800f100: f000 f962 bl 800f3c8 800f104: e016 b.n 800f134 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST1) != 0U) 800f106: 69bb ldr r3, [r7, #24] 800f108: f403 6380 and.w r3, r3, #1024 @ 0x400 800f10c: 2b00 cmp r3, #0 800f10e: d004 beq.n 800f11a { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; 800f110: 6a7b ldr r3, [r7, #36] @ 0x24 800f112: f443 5300 orr.w r3, r3, #8192 @ 0x2000 800f116: 627b str r3, [r7, #36] @ 0x24 800f118: e00c b.n 800f134 } else if ((tsrflags & CAN_TSR_TERR1) != 0U) 800f11a: 69bb ldr r3, [r7, #24] 800f11c: f403 6300 and.w r3, r3, #2048 @ 0x800 800f120: 2b00 cmp r3, #0 800f122: d004 beq.n 800f12e { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; 800f124: 6a7b ldr r3, [r7, #36] @ 0x24 800f126: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800f12a: 627b str r3, [r7, #36] @ 0x24 800f12c: e002 b.n 800f134 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); 800f12e: 6878 ldr r0, [r7, #4] 800f130: f000 f965 bl 800f3fe } } } /* Transmit Mailbox 2 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP2) != 0U) 800f134: 69bb ldr r3, [r7, #24] 800f136: f403 3380 and.w r3, r3, #65536 @ 0x10000 800f13a: 2b00 cmp r3, #0 800f13c: d024 beq.n 800f188 { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); 800f13e: 687b ldr r3, [r7, #4] 800f140: 681b ldr r3, [r3, #0] 800f142: f44f 3280 mov.w r2, #65536 @ 0x10000 800f146: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK2) != 0U) 800f148: 69bb ldr r3, [r7, #24] 800f14a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800f14e: 2b00 cmp r3, #0 800f150: d003 beq.n 800f15a #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); 800f152: 6878 ldr r0, [r7, #4] 800f154: f000 f941 bl 800f3da 800f158: e016 b.n 800f188 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST2) != 0U) 800f15a: 69bb ldr r3, [r7, #24] 800f15c: f403 2380 and.w r3, r3, #262144 @ 0x40000 800f160: 2b00 cmp r3, #0 800f162: d004 beq.n 800f16e { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; 800f164: 6a7b ldr r3, [r7, #36] @ 0x24 800f166: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f16a: 627b str r3, [r7, #36] @ 0x24 800f16c: e00c b.n 800f188 } else if ((tsrflags & CAN_TSR_TERR2) != 0U) 800f16e: 69bb ldr r3, [r7, #24] 800f170: f403 2300 and.w r3, r3, #524288 @ 0x80000 800f174: 2b00 cmp r3, #0 800f176: d004 beq.n 800f182 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; 800f178: 6a7b ldr r3, [r7, #36] @ 0x24 800f17a: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800f17e: 627b str r3, [r7, #36] @ 0x24 800f180: e002 b.n 800f188 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); 800f182: 6878 ldr r0, [r7, #4] 800f184: f000 f944 bl 800f410 } } } /* Receive FIFO 0 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) 800f188: 6a3b ldr r3, [r7, #32] 800f18a: f003 0308 and.w r3, r3, #8 800f18e: 2b00 cmp r3, #0 800f190: d00c beq.n 800f1ac { if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) 800f192: 697b ldr r3, [r7, #20] 800f194: f003 0310 and.w r3, r3, #16 800f198: 2b00 cmp r3, #0 800f19a: d007 beq.n 800f1ac { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; 800f19c: 6a7b ldr r3, [r7, #36] @ 0x24 800f19e: f443 7300 orr.w r3, r3, #512 @ 0x200 800f1a2: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO0 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); 800f1a4: 687b ldr r3, [r7, #4] 800f1a6: 681b ldr r3, [r3, #0] 800f1a8: 2210 movs r2, #16 800f1aa: 60da str r2, [r3, #12] } } /* Receive FIFO 0 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) 800f1ac: 6a3b ldr r3, [r7, #32] 800f1ae: f003 0304 and.w r3, r3, #4 800f1b2: 2b00 cmp r3, #0 800f1b4: d00b beq.n 800f1ce { if ((rf0rflags & CAN_RF0R_FULL0) != 0U) 800f1b6: 697b ldr r3, [r7, #20] 800f1b8: f003 0308 and.w r3, r3, #8 800f1bc: 2b00 cmp r3, #0 800f1be: d006 beq.n 800f1ce { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); 800f1c0: 687b ldr r3, [r7, #4] 800f1c2: 681b ldr r3, [r3, #0] 800f1c4: 2208 movs r2, #8 800f1c6: 60da str r2, [r3, #12] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); 800f1c8: 6878 ldr r0, [r7, #4] 800f1ca: f000 f933 bl 800f434 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) 800f1ce: 6a3b ldr r3, [r7, #32] 800f1d0: f003 0302 and.w r3, r3, #2 800f1d4: 2b00 cmp r3, #0 800f1d6: d009 beq.n 800f1ec { /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) 800f1d8: 687b ldr r3, [r7, #4] 800f1da: 681b ldr r3, [r3, #0] 800f1dc: 68db ldr r3, [r3, #12] 800f1de: f003 0303 and.w r3, r3, #3 800f1e2: 2b00 cmp r3, #0 800f1e4: d002 beq.n 800f1ec #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); 800f1e6: 6878 ldr r0, [r7, #4] 800f1e8: f000 f91b bl 800f422 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) 800f1ec: 6a3b ldr r3, [r7, #32] 800f1ee: f003 0340 and.w r3, r3, #64 @ 0x40 800f1f2: 2b00 cmp r3, #0 800f1f4: d00c beq.n 800f210 { if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) 800f1f6: 693b ldr r3, [r7, #16] 800f1f8: f003 0310 and.w r3, r3, #16 800f1fc: 2b00 cmp r3, #0 800f1fe: d007 beq.n 800f210 { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; 800f200: 6a7b ldr r3, [r7, #36] @ 0x24 800f202: f443 6380 orr.w r3, r3, #1024 @ 0x400 800f206: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO1 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); 800f208: 687b ldr r3, [r7, #4] 800f20a: 681b ldr r3, [r3, #0] 800f20c: 2210 movs r2, #16 800f20e: 611a str r2, [r3, #16] } } /* Receive FIFO 1 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) 800f210: 6a3b ldr r3, [r7, #32] 800f212: f003 0320 and.w r3, r3, #32 800f216: 2b00 cmp r3, #0 800f218: d00b beq.n 800f232 { if ((rf1rflags & CAN_RF1R_FULL1) != 0U) 800f21a: 693b ldr r3, [r7, #16] 800f21c: f003 0308 and.w r3, r3, #8 800f220: 2b00 cmp r3, #0 800f222: d006 beq.n 800f232 { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); 800f224: 687b ldr r3, [r7, #4] 800f226: 681b ldr r3, [r3, #0] 800f228: 2208 movs r2, #8 800f22a: 611a str r2, [r3, #16] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); 800f22c: 6878 ldr r0, [r7, #4] 800f22e: f000 f90a bl 800f446 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) 800f232: 6a3b ldr r3, [r7, #32] 800f234: f003 0310 and.w r3, r3, #16 800f238: 2b00 cmp r3, #0 800f23a: d009 beq.n 800f250 { /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) 800f23c: 687b ldr r3, [r7, #4] 800f23e: 681b ldr r3, [r3, #0] 800f240: 691b ldr r3, [r3, #16] 800f242: f003 0303 and.w r3, r3, #3 800f246: 2b00 cmp r3, #0 800f248: d002 beq.n 800f250 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); 800f24a: 6878 ldr r0, [r7, #4] 800f24c: f7fb fc72 bl 800ab34 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) 800f250: 6a3b ldr r3, [r7, #32] 800f252: f403 3300 and.w r3, r3, #131072 @ 0x20000 800f256: 2b00 cmp r3, #0 800f258: d00b beq.n 800f272 { if ((msrflags & CAN_MSR_SLAKI) != 0U) 800f25a: 69fb ldr r3, [r7, #28] 800f25c: f003 0310 and.w r3, r3, #16 800f260: 2b00 cmp r3, #0 800f262: d006 beq.n 800f272 { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); 800f264: 687b ldr r3, [r7, #4] 800f266: 681b ldr r3, [r3, #0] 800f268: 2210 movs r2, #16 800f26a: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->SleepCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); 800f26c: 6878 ldr r0, [r7, #4] 800f26e: f000 f8f3 bl 800f458 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ if ((interrupts & CAN_IT_WAKEUP) != 0U) 800f272: 6a3b ldr r3, [r7, #32] 800f274: f403 3380 and.w r3, r3, #65536 @ 0x10000 800f278: 2b00 cmp r3, #0 800f27a: d00b beq.n 800f294 { if ((msrflags & CAN_MSR_WKUI) != 0U) 800f27c: 69fb ldr r3, [r7, #28] 800f27e: f003 0308 and.w r3, r3, #8 800f282: 2b00 cmp r3, #0 800f284: d006 beq.n 800f294 { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); 800f286: 687b ldr r3, [r7, #4] 800f288: 681b ldr r3, [r3, #0] 800f28a: 2208 movs r2, #8 800f28c: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->WakeUpFromRxMsgCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); 800f28e: 6878 ldr r0, [r7, #4] 800f290: f000 f8eb bl 800f46a #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ if ((interrupts & CAN_IT_ERROR) != 0U) 800f294: 6a3b ldr r3, [r7, #32] 800f296: f403 4300 and.w r3, r3, #32768 @ 0x8000 800f29a: 2b00 cmp r3, #0 800f29c: d07b beq.n 800f396 { if ((msrflags & CAN_MSR_ERRI) != 0U) 800f29e: 69fb ldr r3, [r7, #28] 800f2a0: f003 0304 and.w r3, r3, #4 800f2a4: 2b00 cmp r3, #0 800f2a6: d072 beq.n 800f38e { /* Check Error Warning Flag */ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800f2a8: 6a3b ldr r3, [r7, #32] 800f2aa: f403 7380 and.w r3, r3, #256 @ 0x100 800f2ae: 2b00 cmp r3, #0 800f2b0: d008 beq.n 800f2c4 ((esrflags & CAN_ESR_EWGF) != 0U)) 800f2b2: 68fb ldr r3, [r7, #12] 800f2b4: f003 0301 and.w r3, r3, #1 if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800f2b8: 2b00 cmp r3, #0 800f2ba: d003 beq.n 800f2c4 { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; 800f2bc: 6a7b ldr r3, [r7, #36] @ 0x24 800f2be: f043 0301 orr.w r3, r3, #1 800f2c2: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Warning Flag as read-only */ } /* Check Error Passive Flag */ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800f2c4: 6a3b ldr r3, [r7, #32] 800f2c6: f403 7300 and.w r3, r3, #512 @ 0x200 800f2ca: 2b00 cmp r3, #0 800f2cc: d008 beq.n 800f2e0 ((esrflags & CAN_ESR_EPVF) != 0U)) 800f2ce: 68fb ldr r3, [r7, #12] 800f2d0: f003 0302 and.w r3, r3, #2 if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800f2d4: 2b00 cmp r3, #0 800f2d6: d003 beq.n 800f2e0 { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; 800f2d8: 6a7b ldr r3, [r7, #36] @ 0x24 800f2da: f043 0302 orr.w r3, r3, #2 800f2de: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-off Flag */ if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800f2e0: 6a3b ldr r3, [r7, #32] 800f2e2: f403 6380 and.w r3, r3, #1024 @ 0x400 800f2e6: 2b00 cmp r3, #0 800f2e8: d008 beq.n 800f2fc ((esrflags & CAN_ESR_BOFF) != 0U)) 800f2ea: 68fb ldr r3, [r7, #12] 800f2ec: f003 0304 and.w r3, r3, #4 if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800f2f0: 2b00 cmp r3, #0 800f2f2: d003 beq.n 800f2fc { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; 800f2f4: 6a7b ldr r3, [r7, #36] @ 0x24 800f2f6: f043 0304 orr.w r3, r3, #4 800f2fa: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Bus-Off as read-only */ } /* Check Last Error Code Flag */ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800f2fc: 6a3b ldr r3, [r7, #32] 800f2fe: f403 6300 and.w r3, r3, #2048 @ 0x800 800f302: 2b00 cmp r3, #0 800f304: d043 beq.n 800f38e ((esrflags & CAN_ESR_LEC) != 0U)) 800f306: 68fb ldr r3, [r7, #12] 800f308: f003 0370 and.w r3, r3, #112 @ 0x70 if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800f30c: 2b00 cmp r3, #0 800f30e: d03e beq.n 800f38e { switch (esrflags & CAN_ESR_LEC) 800f310: 68fb ldr r3, [r7, #12] 800f312: f003 0370 and.w r3, r3, #112 @ 0x70 800f316: 2b60 cmp r3, #96 @ 0x60 800f318: d02b beq.n 800f372 800f31a: 2b60 cmp r3, #96 @ 0x60 800f31c: d82e bhi.n 800f37c 800f31e: 2b50 cmp r3, #80 @ 0x50 800f320: d022 beq.n 800f368 800f322: 2b50 cmp r3, #80 @ 0x50 800f324: d82a bhi.n 800f37c 800f326: 2b40 cmp r3, #64 @ 0x40 800f328: d019 beq.n 800f35e 800f32a: 2b40 cmp r3, #64 @ 0x40 800f32c: d826 bhi.n 800f37c 800f32e: 2b30 cmp r3, #48 @ 0x30 800f330: d010 beq.n 800f354 800f332: 2b30 cmp r3, #48 @ 0x30 800f334: d822 bhi.n 800f37c 800f336: 2b10 cmp r3, #16 800f338: d002 beq.n 800f340 800f33a: 2b20 cmp r3, #32 800f33c: d005 beq.n 800f34a case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): /* Set CAN error code to CRC error */ errorcode |= HAL_CAN_ERROR_CRC; break; default: break; 800f33e: e01d b.n 800f37c errorcode |= HAL_CAN_ERROR_STF; 800f340: 6a7b ldr r3, [r7, #36] @ 0x24 800f342: f043 0308 orr.w r3, r3, #8 800f346: 627b str r3, [r7, #36] @ 0x24 break; 800f348: e019 b.n 800f37e errorcode |= HAL_CAN_ERROR_FOR; 800f34a: 6a7b ldr r3, [r7, #36] @ 0x24 800f34c: f043 0310 orr.w r3, r3, #16 800f350: 627b str r3, [r7, #36] @ 0x24 break; 800f352: e014 b.n 800f37e errorcode |= HAL_CAN_ERROR_ACK; 800f354: 6a7b ldr r3, [r7, #36] @ 0x24 800f356: f043 0320 orr.w r3, r3, #32 800f35a: 627b str r3, [r7, #36] @ 0x24 break; 800f35c: e00f b.n 800f37e errorcode |= HAL_CAN_ERROR_BR; 800f35e: 6a7b ldr r3, [r7, #36] @ 0x24 800f360: f043 0340 orr.w r3, r3, #64 @ 0x40 800f364: 627b str r3, [r7, #36] @ 0x24 break; 800f366: e00a b.n 800f37e errorcode |= HAL_CAN_ERROR_BD; 800f368: 6a7b ldr r3, [r7, #36] @ 0x24 800f36a: f043 0380 orr.w r3, r3, #128 @ 0x80 800f36e: 627b str r3, [r7, #36] @ 0x24 break; 800f370: e005 b.n 800f37e errorcode |= HAL_CAN_ERROR_CRC; 800f372: 6a7b ldr r3, [r7, #36] @ 0x24 800f374: f443 7380 orr.w r3, r3, #256 @ 0x100 800f378: 627b str r3, [r7, #36] @ 0x24 break; 800f37a: e000 b.n 800f37e break; 800f37c: bf00 nop } /* Clear Last error code Flag */ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); 800f37e: 687b ldr r3, [r7, #4] 800f380: 681b ldr r3, [r3, #0] 800f382: 699a ldr r2, [r3, #24] 800f384: 687b ldr r3, [r7, #4] 800f386: 681b ldr r3, [r3, #0] 800f388: f022 0270 bic.w r2, r2, #112 @ 0x70 800f38c: 619a str r2, [r3, #24] } } /* Clear ERRI Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); 800f38e: 687b ldr r3, [r7, #4] 800f390: 681b ldr r3, [r3, #0] 800f392: 2204 movs r2, #4 800f394: 605a str r2, [r3, #4] } /* Call the Error call Back in case of Errors */ if (errorcode != HAL_CAN_ERROR_NONE) 800f396: 6a7b ldr r3, [r7, #36] @ 0x24 800f398: 2b00 cmp r3, #0 800f39a: d008 beq.n 800f3ae { /* Update error code in handle */ hcan->ErrorCode |= errorcode; 800f39c: 687b ldr r3, [r7, #4] 800f39e: 6a5a ldr r2, [r3, #36] @ 0x24 800f3a0: 6a7b ldr r3, [r7, #36] @ 0x24 800f3a2: 431a orrs r2, r3 800f3a4: 687b ldr r3, [r7, #4] 800f3a6: 625a str r2, [r3, #36] @ 0x24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->ErrorCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); 800f3a8: 6878 ldr r0, [r7, #4] 800f3aa: f000 f867 bl 800f47c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } 800f3ae: bf00 nop 800f3b0: 3728 adds r7, #40 @ 0x28 800f3b2: 46bd mov sp, r7 800f3b4: bd80 pop {r7, pc} 0800f3b6 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { 800f3b6: b480 push {r7} 800f3b8: b083 sub sp, #12 800f3ba: af00 add r7, sp, #0 800f3bc: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the user file */ } 800f3be: bf00 nop 800f3c0: 370c adds r7, #12 800f3c2: 46bd mov sp, r7 800f3c4: bc80 pop {r7} 800f3c6: 4770 bx lr 0800f3c8 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { 800f3c8: b480 push {r7} 800f3ca: b083 sub sp, #12 800f3cc: af00 add r7, sp, #0 800f3ce: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the user file */ } 800f3d0: bf00 nop 800f3d2: 370c adds r7, #12 800f3d4: 46bd mov sp, r7 800f3d6: bc80 pop {r7} 800f3d8: 4770 bx lr 0800f3da : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) { 800f3da: b480 push {r7} 800f3dc: b083 sub sp, #12 800f3de: af00 add r7, sp, #0 800f3e0: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the user file */ } 800f3e2: bf00 nop 800f3e4: 370c adds r7, #12 800f3e6: 46bd mov sp, r7 800f3e8: bc80 pop {r7} 800f3ea: 4770 bx lr 0800f3ec : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { 800f3ec: b480 push {r7} 800f3ee: b083 sub sp, #12 800f3f0: af00 add r7, sp, #0 800f3f2: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0AbortCallback could be implemented in the user file */ } 800f3f4: bf00 nop 800f3f6: 370c adds r7, #12 800f3f8: 46bd mov sp, r7 800f3fa: bc80 pop {r7} 800f3fc: 4770 bx lr 0800f3fe : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { 800f3fe: b480 push {r7} 800f400: b083 sub sp, #12 800f402: af00 add r7, sp, #0 800f404: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1AbortCallback could be implemented in the user file */ } 800f406: bf00 nop 800f408: 370c adds r7, #12 800f40a: 46bd mov sp, r7 800f40c: bc80 pop {r7} 800f40e: 4770 bx lr 0800f410 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { 800f410: b480 push {r7} 800f412: b083 sub sp, #12 800f414: af00 add r7, sp, #0 800f416: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2AbortCallback could be implemented in the user file */ } 800f418: bf00 nop 800f41a: 370c adds r7, #12 800f41c: 46bd mov sp, r7 800f41e: bc80 pop {r7} 800f420: 4770 bx lr 0800f422 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) { 800f422: b480 push {r7} 800f424: b083 sub sp, #12 800f426: af00 add r7, sp, #0 800f428: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the user file */ } 800f42a: bf00 nop 800f42c: 370c adds r7, #12 800f42e: 46bd mov sp, r7 800f430: bc80 pop {r7} 800f432: 4770 bx lr 0800f434 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { 800f434: b480 push {r7} 800f436: b083 sub sp, #12 800f438: af00 add r7, sp, #0 800f43a: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0FullCallback could be implemented in the user file */ } 800f43c: bf00 nop 800f43e: 370c adds r7, #12 800f440: 46bd mov sp, r7 800f442: bc80 pop {r7} 800f444: 4770 bx lr 0800f446 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { 800f446: b480 push {r7} 800f448: b083 sub sp, #12 800f44a: af00 add r7, sp, #0 800f44c: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1FullCallback could be implemented in the user file */ } 800f44e: bf00 nop 800f450: 370c adds r7, #12 800f452: 46bd mov sp, r7 800f454: bc80 pop {r7} 800f456: 4770 bx lr 0800f458 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { 800f458: b480 push {r7} 800f45a: b083 sub sp, #12 800f45c: af00 add r7, sp, #0 800f45e: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_SleepCallback could be implemented in the user file */ } 800f460: bf00 nop 800f462: 370c adds r7, #12 800f464: 46bd mov sp, r7 800f466: bc80 pop {r7} 800f468: 4770 bx lr 0800f46a : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { 800f46a: b480 push {r7} 800f46c: b083 sub sp, #12 800f46e: af00 add r7, sp, #0 800f470: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the user file */ } 800f472: bf00 nop 800f474: 370c adds r7, #12 800f476: 46bd mov sp, r7 800f478: bc80 pop {r7} 800f47a: 4770 bx lr 0800f47c : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { 800f47c: b480 push {r7} 800f47e: b083 sub sp, #12 800f480: af00 add r7, sp, #0 800f482: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } 800f484: bf00 nop 800f486: 370c adds r7, #12 800f488: 46bd mov sp, r7 800f48a: bc80 pop {r7} 800f48c: 4770 bx lr ... 0800f490 <__NVIC_SetPriorityGrouping>: { 800f490: b480 push {r7} 800f492: b085 sub sp, #20 800f494: af00 add r7, sp, #0 800f496: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800f498: 687b ldr r3, [r7, #4] 800f49a: f003 0307 and.w r3, r3, #7 800f49e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 800f4a0: 4b0c ldr r3, [pc, #48] @ (800f4d4 <__NVIC_SetPriorityGrouping+0x44>) 800f4a2: 68db ldr r3, [r3, #12] 800f4a4: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800f4a6: 68ba ldr r2, [r7, #8] 800f4a8: f64f 03ff movw r3, #63743 @ 0xf8ff 800f4ac: 4013 ands r3, r2 800f4ae: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 800f4b0: 68fb ldr r3, [r7, #12] 800f4b2: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800f4b4: 68bb ldr r3, [r7, #8] 800f4b6: 4313 orrs r3, r2 reg_value = (reg_value | 800f4b8: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 800f4bc: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800f4c0: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800f4c2: 4a04 ldr r2, [pc, #16] @ (800f4d4 <__NVIC_SetPriorityGrouping+0x44>) 800f4c4: 68bb ldr r3, [r7, #8] 800f4c6: 60d3 str r3, [r2, #12] } 800f4c8: bf00 nop 800f4ca: 3714 adds r7, #20 800f4cc: 46bd mov sp, r7 800f4ce: bc80 pop {r7} 800f4d0: 4770 bx lr 800f4d2: bf00 nop 800f4d4: e000ed00 .word 0xe000ed00 0800f4d8 <__NVIC_GetPriorityGrouping>: { 800f4d8: b480 push {r7} 800f4da: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800f4dc: 4b04 ldr r3, [pc, #16] @ (800f4f0 <__NVIC_GetPriorityGrouping+0x18>) 800f4de: 68db ldr r3, [r3, #12] 800f4e0: 0a1b lsrs r3, r3, #8 800f4e2: f003 0307 and.w r3, r3, #7 } 800f4e6: 4618 mov r0, r3 800f4e8: 46bd mov sp, r7 800f4ea: bc80 pop {r7} 800f4ec: 4770 bx lr 800f4ee: bf00 nop 800f4f0: e000ed00 .word 0xe000ed00 0800f4f4 <__NVIC_EnableIRQ>: { 800f4f4: b480 push {r7} 800f4f6: b083 sub sp, #12 800f4f8: af00 add r7, sp, #0 800f4fa: 4603 mov r3, r0 800f4fc: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800f4fe: f997 3007 ldrsb.w r3, [r7, #7] 800f502: 2b00 cmp r3, #0 800f504: db0b blt.n 800f51e <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800f506: 79fb ldrb r3, [r7, #7] 800f508: f003 021f and.w r2, r3, #31 800f50c: 4906 ldr r1, [pc, #24] @ (800f528 <__NVIC_EnableIRQ+0x34>) 800f50e: f997 3007 ldrsb.w r3, [r7, #7] 800f512: 095b lsrs r3, r3, #5 800f514: 2001 movs r0, #1 800f516: fa00 f202 lsl.w r2, r0, r2 800f51a: f841 2023 str.w r2, [r1, r3, lsl #2] } 800f51e: bf00 nop 800f520: 370c adds r7, #12 800f522: 46bd mov sp, r7 800f524: bc80 pop {r7} 800f526: 4770 bx lr 800f528: e000e100 .word 0xe000e100 0800f52c <__NVIC_SetPriority>: { 800f52c: b480 push {r7} 800f52e: b083 sub sp, #12 800f530: af00 add r7, sp, #0 800f532: 4603 mov r3, r0 800f534: 6039 str r1, [r7, #0] 800f536: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800f538: f997 3007 ldrsb.w r3, [r7, #7] 800f53c: 2b00 cmp r3, #0 800f53e: db0a blt.n 800f556 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800f540: 683b ldr r3, [r7, #0] 800f542: b2da uxtb r2, r3 800f544: 490c ldr r1, [pc, #48] @ (800f578 <__NVIC_SetPriority+0x4c>) 800f546: f997 3007 ldrsb.w r3, [r7, #7] 800f54a: 0112 lsls r2, r2, #4 800f54c: b2d2 uxtb r2, r2 800f54e: 440b add r3, r1 800f550: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 800f554: e00a b.n 800f56c <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800f556: 683b ldr r3, [r7, #0] 800f558: b2da uxtb r2, r3 800f55a: 4908 ldr r1, [pc, #32] @ (800f57c <__NVIC_SetPriority+0x50>) 800f55c: 79fb ldrb r3, [r7, #7] 800f55e: f003 030f and.w r3, r3, #15 800f562: 3b04 subs r3, #4 800f564: 0112 lsls r2, r2, #4 800f566: b2d2 uxtb r2, r2 800f568: 440b add r3, r1 800f56a: 761a strb r2, [r3, #24] } 800f56c: bf00 nop 800f56e: 370c adds r7, #12 800f570: 46bd mov sp, r7 800f572: bc80 pop {r7} 800f574: 4770 bx lr 800f576: bf00 nop 800f578: e000e100 .word 0xe000e100 800f57c: e000ed00 .word 0xe000ed00 0800f580 : { 800f580: b480 push {r7} 800f582: b089 sub sp, #36 @ 0x24 800f584: af00 add r7, sp, #0 800f586: 60f8 str r0, [r7, #12] 800f588: 60b9 str r1, [r7, #8] 800f58a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800f58c: 68fb ldr r3, [r7, #12] 800f58e: f003 0307 and.w r3, r3, #7 800f592: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 800f594: 69fb ldr r3, [r7, #28] 800f596: f1c3 0307 rsb r3, r3, #7 800f59a: 2b04 cmp r3, #4 800f59c: bf28 it cs 800f59e: 2304 movcs r3, #4 800f5a0: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800f5a2: 69fb ldr r3, [r7, #28] 800f5a4: 3304 adds r3, #4 800f5a6: 2b06 cmp r3, #6 800f5a8: d902 bls.n 800f5b0 800f5aa: 69fb ldr r3, [r7, #28] 800f5ac: 3b03 subs r3, #3 800f5ae: e000 b.n 800f5b2 800f5b0: 2300 movs r3, #0 800f5b2: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800f5b4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800f5b8: 69bb ldr r3, [r7, #24] 800f5ba: fa02 f303 lsl.w r3, r2, r3 800f5be: 43da mvns r2, r3 800f5c0: 68bb ldr r3, [r7, #8] 800f5c2: 401a ands r2, r3 800f5c4: 697b ldr r3, [r7, #20] 800f5c6: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 800f5c8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800f5cc: 697b ldr r3, [r7, #20] 800f5ce: fa01 f303 lsl.w r3, r1, r3 800f5d2: 43d9 mvns r1, r3 800f5d4: 687b ldr r3, [r7, #4] 800f5d6: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800f5d8: 4313 orrs r3, r2 } 800f5da: 4618 mov r0, r3 800f5dc: 3724 adds r7, #36 @ 0x24 800f5de: 46bd mov sp, r7 800f5e0: bc80 pop {r7} 800f5e2: 4770 bx lr 0800f5e4 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800f5e4: b580 push {r7, lr} 800f5e6: b082 sub sp, #8 800f5e8: af00 add r7, sp, #0 800f5ea: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 800f5ec: 687b ldr r3, [r7, #4] 800f5ee: 3b01 subs r3, #1 800f5f0: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800f5f4: d301 bcc.n 800f5fa { return (1UL); /* Reload value impossible */ 800f5f6: 2301 movs r3, #1 800f5f8: e00f b.n 800f61a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800f5fa: 4a0a ldr r2, [pc, #40] @ (800f624 ) 800f5fc: 687b ldr r3, [r7, #4] 800f5fe: 3b01 subs r3, #1 800f600: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800f602: 210f movs r1, #15 800f604: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800f608: f7ff ff90 bl 800f52c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 800f60c: 4b05 ldr r3, [pc, #20] @ (800f624 ) 800f60e: 2200 movs r2, #0 800f610: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800f612: 4b04 ldr r3, [pc, #16] @ (800f624 ) 800f614: 2207 movs r2, #7 800f616: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 800f618: 2300 movs r3, #0 } 800f61a: 4618 mov r0, r3 800f61c: 3708 adds r7, #8 800f61e: 46bd mov sp, r7 800f620: bd80 pop {r7, pc} 800f622: bf00 nop 800f624: e000e010 .word 0xe000e010 0800f628 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 800f628: b580 push {r7, lr} 800f62a: b082 sub sp, #8 800f62c: af00 add r7, sp, #0 800f62e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800f630: 6878 ldr r0, [r7, #4] 800f632: f7ff ff2d bl 800f490 <__NVIC_SetPriorityGrouping> } 800f636: bf00 nop 800f638: 3708 adds r7, #8 800f63a: 46bd mov sp, r7 800f63c: bd80 pop {r7, pc} 0800f63e : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800f63e: b580 push {r7, lr} 800f640: b086 sub sp, #24 800f642: af00 add r7, sp, #0 800f644: 4603 mov r3, r0 800f646: 60b9 str r1, [r7, #8] 800f648: 607a str r2, [r7, #4] 800f64a: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 800f64c: 2300 movs r3, #0 800f64e: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800f650: f7ff ff42 bl 800f4d8 <__NVIC_GetPriorityGrouping> 800f654: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 800f656: 687a ldr r2, [r7, #4] 800f658: 68b9 ldr r1, [r7, #8] 800f65a: 6978 ldr r0, [r7, #20] 800f65c: f7ff ff90 bl 800f580 800f660: 4602 mov r2, r0 800f662: f997 300f ldrsb.w r3, [r7, #15] 800f666: 4611 mov r1, r2 800f668: 4618 mov r0, r3 800f66a: f7ff ff5f bl 800f52c <__NVIC_SetPriority> } 800f66e: bf00 nop 800f670: 3718 adds r7, #24 800f672: 46bd mov sp, r7 800f674: bd80 pop {r7, pc} 0800f676 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 800f676: b580 push {r7, lr} 800f678: b082 sub sp, #8 800f67a: af00 add r7, sp, #0 800f67c: 4603 mov r3, r0 800f67e: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800f680: f997 3007 ldrsb.w r3, [r7, #7] 800f684: 4618 mov r0, r3 800f686: f7ff ff35 bl 800f4f4 <__NVIC_EnableIRQ> } 800f68a: bf00 nop 800f68c: 3708 adds r7, #8 800f68e: 46bd mov sp, r7 800f690: bd80 pop {r7, pc} 0800f692 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800f692: b580 push {r7, lr} 800f694: b082 sub sp, #8 800f696: af00 add r7, sp, #0 800f698: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800f69a: 6878 ldr r0, [r7, #4] 800f69c: f7ff ffa2 bl 800f5e4 800f6a0: 4603 mov r3, r0 } 800f6a2: 4618 mov r0, r3 800f6a4: 3708 adds r7, #8 800f6a6: 46bd mov sp, r7 800f6a8: bd80 pop {r7, pc} 0800f6aa : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 800f6aa: b580 push {r7, lr} 800f6ac: b082 sub sp, #8 800f6ae: af00 add r7, sp, #0 800f6b0: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 800f6b2: 687b ldr r3, [r7, #4] 800f6b4: 2b00 cmp r3, #0 800f6b6: d101 bne.n 800f6bc { return HAL_ERROR; 800f6b8: 2301 movs r3, #1 800f6ba: e00e b.n 800f6da } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 800f6bc: 687b ldr r3, [r7, #4] 800f6be: 795b ldrb r3, [r3, #5] 800f6c0: b2db uxtb r3, r3 800f6c2: 2b00 cmp r3, #0 800f6c4: d105 bne.n 800f6d2 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 800f6c6: 687b ldr r3, [r7, #4] 800f6c8: 2200 movs r2, #0 800f6ca: 711a strb r2, [r3, #4] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 800f6cc: 6878 ldr r0, [r7, #4] 800f6ce: f7fa fd73 bl 800a1b8 } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 800f6d2: 687b ldr r3, [r7, #4] 800f6d4: 2201 movs r2, #1 800f6d6: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 800f6d8: 2300 movs r3, #0 } 800f6da: 4618 mov r0, r3 800f6dc: 3708 adds r7, #8 800f6de: 46bd mov sp, r7 800f6e0: bd80 pop {r7, pc} 0800f6e2 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 800f6e2: b480 push {r7} 800f6e4: b085 sub sp, #20 800f6e6: af00 add r7, sp, #0 800f6e8: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800f6ea: 2300 movs r3, #0 800f6ec: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 800f6ee: 687b ldr r3, [r7, #4] 800f6f0: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800f6f4: b2db uxtb r3, r3 800f6f6: 2b02 cmp r3, #2 800f6f8: d008 beq.n 800f70c { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800f6fa: 687b ldr r3, [r7, #4] 800f6fc: 2204 movs r2, #4 800f6fe: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800f700: 687b ldr r3, [r7, #4] 800f702: 2200 movs r2, #0 800f704: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800f708: 2301 movs r3, #1 800f70a: e020 b.n 800f74e } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800f70c: 687b ldr r3, [r7, #4] 800f70e: 681b ldr r3, [r3, #0] 800f710: 681a ldr r2, [r3, #0] 800f712: 687b ldr r3, [r7, #4] 800f714: 681b ldr r3, [r3, #0] 800f716: f022 020e bic.w r2, r2, #14 800f71a: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800f71c: 687b ldr r3, [r7, #4] 800f71e: 681b ldr r3, [r3, #0] 800f720: 681a ldr r2, [r3, #0] 800f722: 687b ldr r3, [r7, #4] 800f724: 681b ldr r3, [r3, #0] 800f726: f022 0201 bic.w r2, r2, #1 800f72a: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 800f72c: 687b ldr r3, [r7, #4] 800f72e: 6c1a ldr r2, [r3, #64] @ 0x40 800f730: 687b ldr r3, [r7, #4] 800f732: 6bdb ldr r3, [r3, #60] @ 0x3c 800f734: 2101 movs r1, #1 800f736: fa01 f202 lsl.w r2, r1, r2 800f73a: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800f73c: 687b ldr r3, [r7, #4] 800f73e: 2201 movs r2, #1 800f740: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800f744: 687b ldr r3, [r7, #4] 800f746: 2200 movs r2, #0 800f748: f883 2020 strb.w r2, [r3, #32] return status; 800f74c: 7bfb ldrb r3, [r7, #15] } 800f74e: 4618 mov r0, r3 800f750: 3714 adds r7, #20 800f752: 46bd mov sp, r7 800f754: bc80 pop {r7} 800f756: 4770 bx lr 0800f758 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 800f758: b580 push {r7, lr} 800f75a: b084 sub sp, #16 800f75c: af00 add r7, sp, #0 800f75e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800f760: 2300 movs r3, #0 800f762: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 800f764: 687b ldr r3, [r7, #4] 800f766: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800f76a: b2db uxtb r3, r3 800f76c: 2b02 cmp r3, #2 800f76e: d005 beq.n 800f77c { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800f770: 687b ldr r3, [r7, #4] 800f772: 2204 movs r2, #4 800f774: 639a str r2, [r3, #56] @ 0x38 status = HAL_ERROR; 800f776: 2301 movs r3, #1 800f778: 73fb strb r3, [r7, #15] 800f77a: e0d6 b.n 800f92a } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800f77c: 687b ldr r3, [r7, #4] 800f77e: 681b ldr r3, [r3, #0] 800f780: 681a ldr r2, [r3, #0] 800f782: 687b ldr r3, [r7, #4] 800f784: 681b ldr r3, [r3, #0] 800f786: f022 020e bic.w r2, r2, #14 800f78a: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800f78c: 687b ldr r3, [r7, #4] 800f78e: 681b ldr r3, [r3, #0] 800f790: 681a ldr r2, [r3, #0] 800f792: 687b ldr r3, [r7, #4] 800f794: 681b ldr r3, [r3, #0] 800f796: f022 0201 bic.w r2, r2, #1 800f79a: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 800f79c: 687b ldr r3, [r7, #4] 800f79e: 681b ldr r3, [r3, #0] 800f7a0: 461a mov r2, r3 800f7a2: 4b64 ldr r3, [pc, #400] @ (800f934 ) 800f7a4: 429a cmp r2, r3 800f7a6: d958 bls.n 800f85a 800f7a8: 687b ldr r3, [r7, #4] 800f7aa: 681b ldr r3, [r3, #0] 800f7ac: 4a62 ldr r2, [pc, #392] @ (800f938 ) 800f7ae: 4293 cmp r3, r2 800f7b0: d04f beq.n 800f852 800f7b2: 687b ldr r3, [r7, #4] 800f7b4: 681b ldr r3, [r3, #0] 800f7b6: 4a61 ldr r2, [pc, #388] @ (800f93c ) 800f7b8: 4293 cmp r3, r2 800f7ba: d048 beq.n 800f84e 800f7bc: 687b ldr r3, [r7, #4] 800f7be: 681b ldr r3, [r3, #0] 800f7c0: 4a5f ldr r2, [pc, #380] @ (800f940 ) 800f7c2: 4293 cmp r3, r2 800f7c4: d040 beq.n 800f848 800f7c6: 687b ldr r3, [r7, #4] 800f7c8: 681b ldr r3, [r3, #0] 800f7ca: 4a5e ldr r2, [pc, #376] @ (800f944 ) 800f7cc: 4293 cmp r3, r2 800f7ce: d038 beq.n 800f842 800f7d0: 687b ldr r3, [r7, #4] 800f7d2: 681b ldr r3, [r3, #0] 800f7d4: 4a5c ldr r2, [pc, #368] @ (800f948 ) 800f7d6: 4293 cmp r3, r2 800f7d8: d030 beq.n 800f83c 800f7da: 687b ldr r3, [r7, #4] 800f7dc: 681b ldr r3, [r3, #0] 800f7de: 4a5b ldr r2, [pc, #364] @ (800f94c ) 800f7e0: 4293 cmp r3, r2 800f7e2: d028 beq.n 800f836 800f7e4: 687b ldr r3, [r7, #4] 800f7e6: 681b ldr r3, [r3, #0] 800f7e8: 4a52 ldr r2, [pc, #328] @ (800f934 ) 800f7ea: 4293 cmp r3, r2 800f7ec: d020 beq.n 800f830 800f7ee: 687b ldr r3, [r7, #4] 800f7f0: 681b ldr r3, [r3, #0] 800f7f2: 4a57 ldr r2, [pc, #348] @ (800f950 ) 800f7f4: 4293 cmp r3, r2 800f7f6: d019 beq.n 800f82c 800f7f8: 687b ldr r3, [r7, #4] 800f7fa: 681b ldr r3, [r3, #0] 800f7fc: 4a55 ldr r2, [pc, #340] @ (800f954 ) 800f7fe: 4293 cmp r3, r2 800f800: d012 beq.n 800f828 800f802: 687b ldr r3, [r7, #4] 800f804: 681b ldr r3, [r3, #0] 800f806: 4a54 ldr r2, [pc, #336] @ (800f958 ) 800f808: 4293 cmp r3, r2 800f80a: d00a beq.n 800f822 800f80c: 687b ldr r3, [r7, #4] 800f80e: 681b ldr r3, [r3, #0] 800f810: 4a52 ldr r2, [pc, #328] @ (800f95c ) 800f812: 4293 cmp r3, r2 800f814: d102 bne.n 800f81c 800f816: f44f 5380 mov.w r3, #4096 @ 0x1000 800f81a: e01b b.n 800f854 800f81c: f44f 3380 mov.w r3, #65536 @ 0x10000 800f820: e018 b.n 800f854 800f822: f44f 7380 mov.w r3, #256 @ 0x100 800f826: e015 b.n 800f854 800f828: 2310 movs r3, #16 800f82a: e013 b.n 800f854 800f82c: 2301 movs r3, #1 800f82e: e011 b.n 800f854 800f830: f04f 7380 mov.w r3, #16777216 @ 0x1000000 800f834: e00e b.n 800f854 800f836: f44f 1380 mov.w r3, #1048576 @ 0x100000 800f83a: e00b b.n 800f854 800f83c: f44f 3380 mov.w r3, #65536 @ 0x10000 800f840: e008 b.n 800f854 800f842: f44f 5380 mov.w r3, #4096 @ 0x1000 800f846: e005 b.n 800f854 800f848: f44f 7380 mov.w r3, #256 @ 0x100 800f84c: e002 b.n 800f854 800f84e: 2310 movs r3, #16 800f850: e000 b.n 800f854 800f852: 2301 movs r3, #1 800f854: 4a42 ldr r2, [pc, #264] @ (800f960 ) 800f856: 6053 str r3, [r2, #4] 800f858: e057 b.n 800f90a 800f85a: 687b ldr r3, [r7, #4] 800f85c: 681b ldr r3, [r3, #0] 800f85e: 4a36 ldr r2, [pc, #216] @ (800f938 ) 800f860: 4293 cmp r3, r2 800f862: d04f beq.n 800f904 800f864: 687b ldr r3, [r7, #4] 800f866: 681b ldr r3, [r3, #0] 800f868: 4a34 ldr r2, [pc, #208] @ (800f93c ) 800f86a: 4293 cmp r3, r2 800f86c: d048 beq.n 800f900 800f86e: 687b ldr r3, [r7, #4] 800f870: 681b ldr r3, [r3, #0] 800f872: 4a33 ldr r2, [pc, #204] @ (800f940 ) 800f874: 4293 cmp r3, r2 800f876: d040 beq.n 800f8fa 800f878: 687b ldr r3, [r7, #4] 800f87a: 681b ldr r3, [r3, #0] 800f87c: 4a31 ldr r2, [pc, #196] @ (800f944 ) 800f87e: 4293 cmp r3, r2 800f880: d038 beq.n 800f8f4 800f882: 687b ldr r3, [r7, #4] 800f884: 681b ldr r3, [r3, #0] 800f886: 4a30 ldr r2, [pc, #192] @ (800f948 ) 800f888: 4293 cmp r3, r2 800f88a: d030 beq.n 800f8ee 800f88c: 687b ldr r3, [r7, #4] 800f88e: 681b ldr r3, [r3, #0] 800f890: 4a2e ldr r2, [pc, #184] @ (800f94c ) 800f892: 4293 cmp r3, r2 800f894: d028 beq.n 800f8e8 800f896: 687b ldr r3, [r7, #4] 800f898: 681b ldr r3, [r3, #0] 800f89a: 4a26 ldr r2, [pc, #152] @ (800f934 ) 800f89c: 4293 cmp r3, r2 800f89e: d020 beq.n 800f8e2 800f8a0: 687b ldr r3, [r7, #4] 800f8a2: 681b ldr r3, [r3, #0] 800f8a4: 4a2a ldr r2, [pc, #168] @ (800f950 ) 800f8a6: 4293 cmp r3, r2 800f8a8: d019 beq.n 800f8de 800f8aa: 687b ldr r3, [r7, #4] 800f8ac: 681b ldr r3, [r3, #0] 800f8ae: 4a29 ldr r2, [pc, #164] @ (800f954 ) 800f8b0: 4293 cmp r3, r2 800f8b2: d012 beq.n 800f8da 800f8b4: 687b ldr r3, [r7, #4] 800f8b6: 681b ldr r3, [r3, #0] 800f8b8: 4a27 ldr r2, [pc, #156] @ (800f958 ) 800f8ba: 4293 cmp r3, r2 800f8bc: d00a beq.n 800f8d4 800f8be: 687b ldr r3, [r7, #4] 800f8c0: 681b ldr r3, [r3, #0] 800f8c2: 4a26 ldr r2, [pc, #152] @ (800f95c ) 800f8c4: 4293 cmp r3, r2 800f8c6: d102 bne.n 800f8ce 800f8c8: f44f 5380 mov.w r3, #4096 @ 0x1000 800f8cc: e01b b.n 800f906 800f8ce: f44f 3380 mov.w r3, #65536 @ 0x10000 800f8d2: e018 b.n 800f906 800f8d4: f44f 7380 mov.w r3, #256 @ 0x100 800f8d8: e015 b.n 800f906 800f8da: 2310 movs r3, #16 800f8dc: e013 b.n 800f906 800f8de: 2301 movs r3, #1 800f8e0: e011 b.n 800f906 800f8e2: f04f 7380 mov.w r3, #16777216 @ 0x1000000 800f8e6: e00e b.n 800f906 800f8e8: f44f 1380 mov.w r3, #1048576 @ 0x100000 800f8ec: e00b b.n 800f906 800f8ee: f44f 3380 mov.w r3, #65536 @ 0x10000 800f8f2: e008 b.n 800f906 800f8f4: f44f 5380 mov.w r3, #4096 @ 0x1000 800f8f8: e005 b.n 800f906 800f8fa: f44f 7380 mov.w r3, #256 @ 0x100 800f8fe: e002 b.n 800f906 800f900: 2310 movs r3, #16 800f902: e000 b.n 800f906 800f904: 2301 movs r3, #1 800f906: 4a17 ldr r2, [pc, #92] @ (800f964 ) 800f908: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800f90a: 687b ldr r3, [r7, #4] 800f90c: 2201 movs r2, #1 800f90e: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800f912: 687b ldr r3, [r7, #4] 800f914: 2200 movs r2, #0 800f916: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 800f91a: 687b ldr r3, [r7, #4] 800f91c: 6b5b ldr r3, [r3, #52] @ 0x34 800f91e: 2b00 cmp r3, #0 800f920: d003 beq.n 800f92a { hdma->XferAbortCallback(hdma); 800f922: 687b ldr r3, [r7, #4] 800f924: 6b5b ldr r3, [r3, #52] @ 0x34 800f926: 6878 ldr r0, [r7, #4] 800f928: 4798 blx r3 } } return status; 800f92a: 7bfb ldrb r3, [r7, #15] } 800f92c: 4618 mov r0, r3 800f92e: 3710 adds r7, #16 800f930: 46bd mov sp, r7 800f932: bd80 pop {r7, pc} 800f934: 40020080 .word 0x40020080 800f938: 40020008 .word 0x40020008 800f93c: 4002001c .word 0x4002001c 800f940: 40020030 .word 0x40020030 800f944: 40020044 .word 0x40020044 800f948: 40020058 .word 0x40020058 800f94c: 4002006c .word 0x4002006c 800f950: 40020408 .word 0x40020408 800f954: 4002041c .word 0x4002041c 800f958: 40020430 .word 0x40020430 800f95c: 40020444 .word 0x40020444 800f960: 40020400 .word 0x40020400 800f964: 40020000 .word 0x40020000 0800f968 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800f968: b480 push {r7} 800f96a: b08b sub sp, #44 @ 0x2c 800f96c: af00 add r7, sp, #0 800f96e: 6078 str r0, [r7, #4] 800f970: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 800f972: 2300 movs r3, #0 800f974: 627b str r3, [r7, #36] @ 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 800f976: 2300 movs r3, #0 800f978: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800f97a: e169 b.n 800fc50 { /* Get the IO position */ ioposition = (0x01uL << position); 800f97c: 2201 movs r2, #1 800f97e: 6a7b ldr r3, [r7, #36] @ 0x24 800f980: fa02 f303 lsl.w r3, r2, r3 800f984: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 800f986: 683b ldr r3, [r7, #0] 800f988: 681b ldr r3, [r3, #0] 800f98a: 69fa ldr r2, [r7, #28] 800f98c: 4013 ands r3, r2 800f98e: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 800f990: 69ba ldr r2, [r7, #24] 800f992: 69fb ldr r3, [r7, #28] 800f994: 429a cmp r2, r3 800f996: f040 8158 bne.w 800fc4a { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 800f99a: 683b ldr r3, [r7, #0] 800f99c: 685b ldr r3, [r3, #4] 800f99e: 4a9a ldr r2, [pc, #616] @ (800fc08 ) 800f9a0: 4293 cmp r3, r2 800f9a2: d05e beq.n 800fa62 800f9a4: 4a98 ldr r2, [pc, #608] @ (800fc08 ) 800f9a6: 4293 cmp r3, r2 800f9a8: d875 bhi.n 800fa96 800f9aa: 4a98 ldr r2, [pc, #608] @ (800fc0c ) 800f9ac: 4293 cmp r3, r2 800f9ae: d058 beq.n 800fa62 800f9b0: 4a96 ldr r2, [pc, #600] @ (800fc0c ) 800f9b2: 4293 cmp r3, r2 800f9b4: d86f bhi.n 800fa96 800f9b6: 4a96 ldr r2, [pc, #600] @ (800fc10 ) 800f9b8: 4293 cmp r3, r2 800f9ba: d052 beq.n 800fa62 800f9bc: 4a94 ldr r2, [pc, #592] @ (800fc10 ) 800f9be: 4293 cmp r3, r2 800f9c0: d869 bhi.n 800fa96 800f9c2: 4a94 ldr r2, [pc, #592] @ (800fc14 ) 800f9c4: 4293 cmp r3, r2 800f9c6: d04c beq.n 800fa62 800f9c8: 4a92 ldr r2, [pc, #584] @ (800fc14 ) 800f9ca: 4293 cmp r3, r2 800f9cc: d863 bhi.n 800fa96 800f9ce: 4a92 ldr r2, [pc, #584] @ (800fc18 ) 800f9d0: 4293 cmp r3, r2 800f9d2: d046 beq.n 800fa62 800f9d4: 4a90 ldr r2, [pc, #576] @ (800fc18 ) 800f9d6: 4293 cmp r3, r2 800f9d8: d85d bhi.n 800fa96 800f9da: 2b12 cmp r3, #18 800f9dc: d82a bhi.n 800fa34 800f9de: 2b12 cmp r3, #18 800f9e0: d859 bhi.n 800fa96 800f9e2: a201 add r2, pc, #4 @ (adr r2, 800f9e8 ) 800f9e4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800f9e8: 0800fa63 .word 0x0800fa63 800f9ec: 0800fa3d .word 0x0800fa3d 800f9f0: 0800fa4f .word 0x0800fa4f 800f9f4: 0800fa91 .word 0x0800fa91 800f9f8: 0800fa97 .word 0x0800fa97 800f9fc: 0800fa97 .word 0x0800fa97 800fa00: 0800fa97 .word 0x0800fa97 800fa04: 0800fa97 .word 0x0800fa97 800fa08: 0800fa97 .word 0x0800fa97 800fa0c: 0800fa97 .word 0x0800fa97 800fa10: 0800fa97 .word 0x0800fa97 800fa14: 0800fa97 .word 0x0800fa97 800fa18: 0800fa97 .word 0x0800fa97 800fa1c: 0800fa97 .word 0x0800fa97 800fa20: 0800fa97 .word 0x0800fa97 800fa24: 0800fa97 .word 0x0800fa97 800fa28: 0800fa97 .word 0x0800fa97 800fa2c: 0800fa45 .word 0x0800fa45 800fa30: 0800fa59 .word 0x0800fa59 800fa34: 4a79 ldr r2, [pc, #484] @ (800fc1c ) 800fa36: 4293 cmp r3, r2 800fa38: d013 beq.n 800fa62 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 800fa3a: e02c b.n 800fa96 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 800fa3c: 683b ldr r3, [r7, #0] 800fa3e: 68db ldr r3, [r3, #12] 800fa40: 623b str r3, [r7, #32] break; 800fa42: e029 b.n 800fa98 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 800fa44: 683b ldr r3, [r7, #0] 800fa46: 68db ldr r3, [r3, #12] 800fa48: 3304 adds r3, #4 800fa4a: 623b str r3, [r7, #32] break; 800fa4c: e024 b.n 800fa98 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 800fa4e: 683b ldr r3, [r7, #0] 800fa50: 68db ldr r3, [r3, #12] 800fa52: 3308 adds r3, #8 800fa54: 623b str r3, [r7, #32] break; 800fa56: e01f b.n 800fa98 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 800fa58: 683b ldr r3, [r7, #0] 800fa5a: 68db ldr r3, [r3, #12] 800fa5c: 330c adds r3, #12 800fa5e: 623b str r3, [r7, #32] break; 800fa60: e01a b.n 800fa98 if (GPIO_Init->Pull == GPIO_NOPULL) 800fa62: 683b ldr r3, [r7, #0] 800fa64: 689b ldr r3, [r3, #8] 800fa66: 2b00 cmp r3, #0 800fa68: d102 bne.n 800fa70 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 800fa6a: 2304 movs r3, #4 800fa6c: 623b str r3, [r7, #32] break; 800fa6e: e013 b.n 800fa98 else if (GPIO_Init->Pull == GPIO_PULLUP) 800fa70: 683b ldr r3, [r7, #0] 800fa72: 689b ldr r3, [r3, #8] 800fa74: 2b01 cmp r3, #1 800fa76: d105 bne.n 800fa84 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 800fa78: 2308 movs r3, #8 800fa7a: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 800fa7c: 687b ldr r3, [r7, #4] 800fa7e: 69fa ldr r2, [r7, #28] 800fa80: 611a str r2, [r3, #16] break; 800fa82: e009 b.n 800fa98 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 800fa84: 2308 movs r3, #8 800fa86: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 800fa88: 687b ldr r3, [r7, #4] 800fa8a: 69fa ldr r2, [r7, #28] 800fa8c: 615a str r2, [r3, #20] break; 800fa8e: e003 b.n 800fa98 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 800fa90: 2300 movs r3, #0 800fa92: 623b str r3, [r7, #32] break; 800fa94: e000 b.n 800fa98 break; 800fa96: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 800fa98: 69bb ldr r3, [r7, #24] 800fa9a: 2bff cmp r3, #255 @ 0xff 800fa9c: d801 bhi.n 800faa2 800fa9e: 687b ldr r3, [r7, #4] 800faa0: e001 b.n 800faa6 800faa2: 687b ldr r3, [r7, #4] 800faa4: 3304 adds r3, #4 800faa6: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 800faa8: 69bb ldr r3, [r7, #24] 800faaa: 2bff cmp r3, #255 @ 0xff 800faac: d802 bhi.n 800fab4 800faae: 6a7b ldr r3, [r7, #36] @ 0x24 800fab0: 009b lsls r3, r3, #2 800fab2: e002 b.n 800faba 800fab4: 6a7b ldr r3, [r7, #36] @ 0x24 800fab6: 3b08 subs r3, #8 800fab8: 009b lsls r3, r3, #2 800faba: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 800fabc: 697b ldr r3, [r7, #20] 800fabe: 681a ldr r2, [r3, #0] 800fac0: 210f movs r1, #15 800fac2: 693b ldr r3, [r7, #16] 800fac4: fa01 f303 lsl.w r3, r1, r3 800fac8: 43db mvns r3, r3 800faca: 401a ands r2, r3 800facc: 6a39 ldr r1, [r7, #32] 800face: 693b ldr r3, [r7, #16] 800fad0: fa01 f303 lsl.w r3, r1, r3 800fad4: 431a orrs r2, r3 800fad6: 697b ldr r3, [r7, #20] 800fad8: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 800fada: 683b ldr r3, [r7, #0] 800fadc: 685b ldr r3, [r3, #4] 800fade: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800fae2: 2b00 cmp r3, #0 800fae4: f000 80b1 beq.w 800fc4a { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 800fae8: 4b4d ldr r3, [pc, #308] @ (800fc20 ) 800faea: 699b ldr r3, [r3, #24] 800faec: 4a4c ldr r2, [pc, #304] @ (800fc20 ) 800faee: f043 0301 orr.w r3, r3, #1 800faf2: 6193 str r3, [r2, #24] 800faf4: 4b4a ldr r3, [pc, #296] @ (800fc20 ) 800faf6: 699b ldr r3, [r3, #24] 800faf8: f003 0301 and.w r3, r3, #1 800fafc: 60bb str r3, [r7, #8] 800fafe: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 800fb00: 4a48 ldr r2, [pc, #288] @ (800fc24 ) 800fb02: 6a7b ldr r3, [r7, #36] @ 0x24 800fb04: 089b lsrs r3, r3, #2 800fb06: 3302 adds r3, #2 800fb08: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800fb0c: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 800fb0e: 6a7b ldr r3, [r7, #36] @ 0x24 800fb10: f003 0303 and.w r3, r3, #3 800fb14: 009b lsls r3, r3, #2 800fb16: 220f movs r2, #15 800fb18: fa02 f303 lsl.w r3, r2, r3 800fb1c: 43db mvns r3, r3 800fb1e: 68fa ldr r2, [r7, #12] 800fb20: 4013 ands r3, r2 800fb22: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 800fb24: 687b ldr r3, [r7, #4] 800fb26: 4a40 ldr r2, [pc, #256] @ (800fc28 ) 800fb28: 4293 cmp r3, r2 800fb2a: d013 beq.n 800fb54 800fb2c: 687b ldr r3, [r7, #4] 800fb2e: 4a3f ldr r2, [pc, #252] @ (800fc2c ) 800fb30: 4293 cmp r3, r2 800fb32: d00d beq.n 800fb50 800fb34: 687b ldr r3, [r7, #4] 800fb36: 4a3e ldr r2, [pc, #248] @ (800fc30 ) 800fb38: 4293 cmp r3, r2 800fb3a: d007 beq.n 800fb4c 800fb3c: 687b ldr r3, [r7, #4] 800fb3e: 4a3d ldr r2, [pc, #244] @ (800fc34 ) 800fb40: 4293 cmp r3, r2 800fb42: d101 bne.n 800fb48 800fb44: 2303 movs r3, #3 800fb46: e006 b.n 800fb56 800fb48: 2304 movs r3, #4 800fb4a: e004 b.n 800fb56 800fb4c: 2302 movs r3, #2 800fb4e: e002 b.n 800fb56 800fb50: 2301 movs r3, #1 800fb52: e000 b.n 800fb56 800fb54: 2300 movs r3, #0 800fb56: 6a7a ldr r2, [r7, #36] @ 0x24 800fb58: f002 0203 and.w r2, r2, #3 800fb5c: 0092 lsls r2, r2, #2 800fb5e: 4093 lsls r3, r2 800fb60: 68fa ldr r2, [r7, #12] 800fb62: 4313 orrs r3, r2 800fb64: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 800fb66: 492f ldr r1, [pc, #188] @ (800fc24 ) 800fb68: 6a7b ldr r3, [r7, #36] @ 0x24 800fb6a: 089b lsrs r3, r3, #2 800fb6c: 3302 adds r3, #2 800fb6e: 68fa ldr r2, [r7, #12] 800fb70: f841 2023 str.w r2, [r1, r3, lsl #2] /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 800fb74: 683b ldr r3, [r7, #0] 800fb76: 685b ldr r3, [r3, #4] 800fb78: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800fb7c: 2b00 cmp r3, #0 800fb7e: d006 beq.n 800fb8e { SET_BIT(EXTI->RTSR, iocurrent); 800fb80: 4b2d ldr r3, [pc, #180] @ (800fc38 ) 800fb82: 689a ldr r2, [r3, #8] 800fb84: 492c ldr r1, [pc, #176] @ (800fc38 ) 800fb86: 69bb ldr r3, [r7, #24] 800fb88: 4313 orrs r3, r2 800fb8a: 608b str r3, [r1, #8] 800fb8c: e006 b.n 800fb9c } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 800fb8e: 4b2a ldr r3, [pc, #168] @ (800fc38 ) 800fb90: 689a ldr r2, [r3, #8] 800fb92: 69bb ldr r3, [r7, #24] 800fb94: 43db mvns r3, r3 800fb96: 4928 ldr r1, [pc, #160] @ (800fc38 ) 800fb98: 4013 ands r3, r2 800fb9a: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 800fb9c: 683b ldr r3, [r7, #0] 800fb9e: 685b ldr r3, [r3, #4] 800fba0: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800fba4: 2b00 cmp r3, #0 800fba6: d006 beq.n 800fbb6 { SET_BIT(EXTI->FTSR, iocurrent); 800fba8: 4b23 ldr r3, [pc, #140] @ (800fc38 ) 800fbaa: 68da ldr r2, [r3, #12] 800fbac: 4922 ldr r1, [pc, #136] @ (800fc38 ) 800fbae: 69bb ldr r3, [r7, #24] 800fbb0: 4313 orrs r3, r2 800fbb2: 60cb str r3, [r1, #12] 800fbb4: e006 b.n 800fbc4 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 800fbb6: 4b20 ldr r3, [pc, #128] @ (800fc38 ) 800fbb8: 68da ldr r2, [r3, #12] 800fbba: 69bb ldr r3, [r7, #24] 800fbbc: 43db mvns r3, r3 800fbbe: 491e ldr r1, [pc, #120] @ (800fc38 ) 800fbc0: 4013 ands r3, r2 800fbc2: 60cb str r3, [r1, #12] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 800fbc4: 683b ldr r3, [r7, #0] 800fbc6: 685b ldr r3, [r3, #4] 800fbc8: f403 3300 and.w r3, r3, #131072 @ 0x20000 800fbcc: 2b00 cmp r3, #0 800fbce: d006 beq.n 800fbde { SET_BIT(EXTI->EMR, iocurrent); 800fbd0: 4b19 ldr r3, [pc, #100] @ (800fc38 ) 800fbd2: 685a ldr r2, [r3, #4] 800fbd4: 4918 ldr r1, [pc, #96] @ (800fc38 ) 800fbd6: 69bb ldr r3, [r7, #24] 800fbd8: 4313 orrs r3, r2 800fbda: 604b str r3, [r1, #4] 800fbdc: e006 b.n 800fbec } else { CLEAR_BIT(EXTI->EMR, iocurrent); 800fbde: 4b16 ldr r3, [pc, #88] @ (800fc38 ) 800fbe0: 685a ldr r2, [r3, #4] 800fbe2: 69bb ldr r3, [r7, #24] 800fbe4: 43db mvns r3, r3 800fbe6: 4914 ldr r1, [pc, #80] @ (800fc38 ) 800fbe8: 4013 ands r3, r2 800fbea: 604b str r3, [r1, #4] } /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 800fbec: 683b ldr r3, [r7, #0] 800fbee: 685b ldr r3, [r3, #4] 800fbf0: f403 3380 and.w r3, r3, #65536 @ 0x10000 800fbf4: 2b00 cmp r3, #0 800fbf6: d021 beq.n 800fc3c { SET_BIT(EXTI->IMR, iocurrent); 800fbf8: 4b0f ldr r3, [pc, #60] @ (800fc38 ) 800fbfa: 681a ldr r2, [r3, #0] 800fbfc: 490e ldr r1, [pc, #56] @ (800fc38 ) 800fbfe: 69bb ldr r3, [r7, #24] 800fc00: 4313 orrs r3, r2 800fc02: 600b str r3, [r1, #0] 800fc04: e021 b.n 800fc4a 800fc06: bf00 nop 800fc08: 10320000 .word 0x10320000 800fc0c: 10310000 .word 0x10310000 800fc10: 10220000 .word 0x10220000 800fc14: 10210000 .word 0x10210000 800fc18: 10120000 .word 0x10120000 800fc1c: 10110000 .word 0x10110000 800fc20: 40021000 .word 0x40021000 800fc24: 40010000 .word 0x40010000 800fc28: 40010800 .word 0x40010800 800fc2c: 40010c00 .word 0x40010c00 800fc30: 40011000 .word 0x40011000 800fc34: 40011400 .word 0x40011400 800fc38: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 800fc3c: 4b0b ldr r3, [pc, #44] @ (800fc6c ) 800fc3e: 681a ldr r2, [r3, #0] 800fc40: 69bb ldr r3, [r7, #24] 800fc42: 43db mvns r3, r3 800fc44: 4909 ldr r1, [pc, #36] @ (800fc6c ) 800fc46: 4013 ands r3, r2 800fc48: 600b str r3, [r1, #0] } } } position++; 800fc4a: 6a7b ldr r3, [r7, #36] @ 0x24 800fc4c: 3301 adds r3, #1 800fc4e: 627b str r3, [r7, #36] @ 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 800fc50: 683b ldr r3, [r7, #0] 800fc52: 681a ldr r2, [r3, #0] 800fc54: 6a7b ldr r3, [r7, #36] @ 0x24 800fc56: fa22 f303 lsr.w r3, r2, r3 800fc5a: 2b00 cmp r3, #0 800fc5c: f47f ae8e bne.w 800f97c } } 800fc60: bf00 nop 800fc62: bf00 nop 800fc64: 372c adds r7, #44 @ 0x2c 800fc66: 46bd mov sp, r7 800fc68: bc80 pop {r7} 800fc6a: 4770 bx lr 800fc6c: 40010400 .word 0x40010400 0800fc70 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800fc70: b480 push {r7} 800fc72: b085 sub sp, #20 800fc74: af00 add r7, sp, #0 800fc76: 6078 str r0, [r7, #4] 800fc78: 460b mov r3, r1 800fc7a: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 800fc7c: 687b ldr r3, [r7, #4] 800fc7e: 689a ldr r2, [r3, #8] 800fc80: 887b ldrh r3, [r7, #2] 800fc82: 4013 ands r3, r2 800fc84: 2b00 cmp r3, #0 800fc86: d002 beq.n 800fc8e { bitstatus = GPIO_PIN_SET; 800fc88: 2301 movs r3, #1 800fc8a: 73fb strb r3, [r7, #15] 800fc8c: e001 b.n 800fc92 } else { bitstatus = GPIO_PIN_RESET; 800fc8e: 2300 movs r3, #0 800fc90: 73fb strb r3, [r7, #15] } return bitstatus; 800fc92: 7bfb ldrb r3, [r7, #15] } 800fc94: 4618 mov r0, r3 800fc96: 3714 adds r7, #20 800fc98: 46bd mov sp, r7 800fc9a: bc80 pop {r7} 800fc9c: 4770 bx lr 0800fc9e : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 800fc9e: b480 push {r7} 800fca0: b083 sub sp, #12 800fca2: af00 add r7, sp, #0 800fca4: 6078 str r0, [r7, #4] 800fca6: 460b mov r3, r1 800fca8: 807b strh r3, [r7, #2] 800fcaa: 4613 mov r3, r2 800fcac: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800fcae: 787b ldrb r3, [r7, #1] 800fcb0: 2b00 cmp r3, #0 800fcb2: d003 beq.n 800fcbc { GPIOx->BSRR = GPIO_Pin; 800fcb4: 887a ldrh r2, [r7, #2] 800fcb6: 687b ldr r3, [r7, #4] 800fcb8: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 800fcba: e003 b.n 800fcc4 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 800fcbc: 887b ldrh r3, [r7, #2] 800fcbe: 041a lsls r2, r3, #16 800fcc0: 687b ldr r3, [r7, #4] 800fcc2: 611a str r2, [r3, #16] } 800fcc4: bf00 nop 800fcc6: 370c adds r7, #12 800fcc8: 46bd mov sp, r7 800fcca: bc80 pop {r7} 800fccc: 4770 bx lr ... 0800fcd0 : * @note If the HSE divided by 128 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { 800fcd0: b480 push {r7} 800fcd2: af00 add r7, sp, #0 /* Enable access to RTC and backup registers */ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 800fcd4: 4b03 ldr r3, [pc, #12] @ (800fce4 ) 800fcd6: 2201 movs r2, #1 800fcd8: 601a str r2, [r3, #0] } 800fcda: bf00 nop 800fcdc: 46bd mov sp, r7 800fcde: bc80 pop {r7} 800fce0: 4770 bx lr 800fce2: bf00 nop 800fce4: 420e0020 .word 0x420e0020 0800fce8 : * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval HAL_StatusTypeDef */ HAL_StatusTypeDef HAL_RCC_DeInit(void) { 800fce8: b580 push {r7, lr} 800fcea: b082 sub sp, #8 800fcec: af00 add r7, sp, #0 uint32_t tickstart; /* Get Start Tick */ tickstart = HAL_GetTick(); 800fcee: f7fd ffc5 bl 800dc7c 800fcf2: 6078 str r0, [r7, #4] /* Set HSION bit */ SET_BIT(RCC->CR, RCC_CR_HSION); 800fcf4: 4b60 ldr r3, [pc, #384] @ (800fe78 ) 800fcf6: 681b ldr r3, [r3, #0] 800fcf8: 4a5f ldr r2, [pc, #380] @ (800fe78 ) 800fcfa: f043 0301 orr.w r3, r3, #1 800fcfe: 6013 str r3, [r2, #0] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 800fd00: e008 b.n 800fd14 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800fd02: f7fd ffbb bl 800dc7c 800fd06: 4602 mov r2, r0 800fd08: 687b ldr r3, [r7, #4] 800fd0a: 1ad3 subs r3, r2, r3 800fd0c: 2b02 cmp r3, #2 800fd0e: d901 bls.n 800fd14 { return HAL_TIMEOUT; 800fd10: 2303 movs r3, #3 800fd12: e0ac b.n 800fe6e while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 800fd14: 4b58 ldr r3, [pc, #352] @ (800fe78 ) 800fd16: 681b ldr r3, [r3, #0] 800fd18: f003 0302 and.w r3, r3, #2 800fd1c: 2b00 cmp r3, #0 800fd1e: d0f0 beq.n 800fd02 } } /* Set HSITRIM bits to the reset value */ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos)); 800fd20: 4b55 ldr r3, [pc, #340] @ (800fe78 ) 800fd22: 681b ldr r3, [r3, #0] 800fd24: f023 03f8 bic.w r3, r3, #248 @ 0xf8 800fd28: 4a53 ldr r2, [pc, #332] @ (800fe78 ) 800fd2a: f043 0380 orr.w r3, r3, #128 @ 0x80 800fd2e: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800fd30: f7fd ffa4 bl 800dc7c 800fd34: 6078 str r0, [r7, #4] /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); 800fd36: 4b50 ldr r3, [pc, #320] @ (800fe78 ) 800fd38: 2200 movs r2, #0 800fd3a: 605a str r2, [r3, #4] /* Wait till clock switch is ready */ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 800fd3c: e00a b.n 800fd54 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800fd3e: f7fd ff9d bl 800dc7c 800fd42: 4602 mov r2, r0 800fd44: 687b ldr r3, [r7, #4] 800fd46: 1ad3 subs r3, r2, r3 800fd48: f241 3288 movw r2, #5000 @ 0x1388 800fd4c: 4293 cmp r3, r2 800fd4e: d901 bls.n 800fd54 { return HAL_TIMEOUT; 800fd50: 2303 movs r3, #3 800fd52: e08c b.n 800fe6e while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 800fd54: 4b48 ldr r3, [pc, #288] @ (800fe78 ) 800fd56: 685b ldr r3, [r3, #4] 800fd58: f003 030c and.w r3, r3, #12 800fd5c: 2b00 cmp r3, #0 800fd5e: d1ee bne.n 800fd3e } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HSI_VALUE; 800fd60: 4b46 ldr r3, [pc, #280] @ (800fe7c ) 800fd62: 4a47 ldr r2, [pc, #284] @ (800fe80 ) 800fd64: 601a str r2, [r3, #0] /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 800fd66: 4b47 ldr r3, [pc, #284] @ (800fe84 ) 800fd68: 681b ldr r3, [r3, #0] 800fd6a: 4618 mov r0, r3 800fd6c: f7fd ff44 bl 800dbf8 800fd70: 4603 mov r3, r0 800fd72: 2b00 cmp r3, #0 800fd74: d001 beq.n 800fd7a { return HAL_ERROR; 800fd76: 2301 movs r3, #1 800fd78: e079 b.n 800fe6e } /* Get Start Tick */ tickstart = HAL_GetTick(); 800fd7a: f7fd ff7f bl 800dc7c 800fd7e: 6078 str r0, [r7, #4] /* Second step is to clear PLLON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 800fd80: 4b3d ldr r3, [pc, #244] @ (800fe78 ) 800fd82: 681b ldr r3, [r3, #0] 800fd84: 4a3c ldr r2, [pc, #240] @ (800fe78 ) 800fd86: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800fd8a: 6013 str r3, [r2, #0] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 800fd8c: e008 b.n 800fda0 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800fd8e: f7fd ff75 bl 800dc7c 800fd92: 4602 mov r2, r0 800fd94: 687b ldr r3, [r7, #4] 800fd96: 1ad3 subs r3, r2, r3 800fd98: 2b02 cmp r3, #2 800fd9a: d901 bls.n 800fda0 { return HAL_TIMEOUT; 800fd9c: 2303 movs r3, #3 800fd9e: e066 b.n 800fe6e while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 800fda0: 4b35 ldr r3, [pc, #212] @ (800fe78 ) 800fda2: 681b ldr r3, [r3, #0] 800fda4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800fda8: 2b00 cmp r3, #0 800fdaa: d1f0 bne.n 800fd8e } } /* Ensure to reset PLLSRC and PLLMUL bits */ CLEAR_REG(RCC->CFGR); 800fdac: 4b32 ldr r3, [pc, #200] @ (800fe78 ) 800fdae: 2200 movs r2, #0 800fdb0: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 800fdb2: f7fd ff63 bl 800dc7c 800fdb6: 6078 str r0, [r7, #4] /* Reset HSEON & CSSON bits */ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON); 800fdb8: 4b2f ldr r3, [pc, #188] @ (800fe78 ) 800fdba: 681b ldr r3, [r3, #0] 800fdbc: 4a2e ldr r2, [pc, #184] @ (800fe78 ) 800fdbe: f423 2310 bic.w r3, r3, #589824 @ 0x90000 800fdc2: 6013 str r3, [r2, #0] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 800fdc4: e008 b.n 800fdd8 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800fdc6: f7fd ff59 bl 800dc7c 800fdca: 4602 mov r2, r0 800fdcc: 687b ldr r3, [r7, #4] 800fdce: 1ad3 subs r3, r2, r3 800fdd0: 2b64 cmp r3, #100 @ 0x64 800fdd2: d901 bls.n 800fdd8 { return HAL_TIMEOUT; 800fdd4: 2303 movs r3, #3 800fdd6: e04a b.n 800fe6e while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 800fdd8: 4b27 ldr r3, [pc, #156] @ (800fe78 ) 800fdda: 681b ldr r3, [r3, #0] 800fddc: f403 3300 and.w r3, r3, #131072 @ 0x20000 800fde0: 2b00 cmp r3, #0 800fde2: d1f0 bne.n 800fdc6 } } /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 800fde4: 4b24 ldr r3, [pc, #144] @ (800fe78 ) 800fde6: 681b ldr r3, [r3, #0] 800fde8: 4a23 ldr r2, [pc, #140] @ (800fe78 ) 800fdea: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800fdee: 6013 str r3, [r2, #0] #if defined(RCC_PLL2_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 800fdf0: f7fd ff44 bl 800dc7c 800fdf4: 6078 str r0, [r7, #4] /* Clear PLL2ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); 800fdf6: 4b20 ldr r3, [pc, #128] @ (800fe78 ) 800fdf8: 681b ldr r3, [r3, #0] 800fdfa: 4a1f ldr r2, [pc, #124] @ (800fe78 ) 800fdfc: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800fe00: 6013 str r3, [r2, #0] /* Wait till PLL2 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 800fe02: e008 b.n 800fe16 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800fe04: f7fd ff3a bl 800dc7c 800fe08: 4602 mov r2, r0 800fe0a: 687b ldr r3, [r7, #4] 800fe0c: 1ad3 subs r3, r2, r3 800fe0e: 2b64 cmp r3, #100 @ 0x64 800fe10: d901 bls.n 800fe16 { return HAL_TIMEOUT; 800fe12: 2303 movs r3, #3 800fe14: e02b b.n 800fe6e while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 800fe16: 4b18 ldr r3, [pc, #96] @ (800fe78 ) 800fe18: 681b ldr r3, [r3, #0] 800fe1a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800fe1e: 2b00 cmp r3, #0 800fe20: d1f0 bne.n 800fe04 } #endif /* RCC_PLL2_SUPPORT */ #if defined(RCC_PLLI2S_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 800fe22: f7fd ff2b bl 800dc7c 800fe26: 6078 str r0, [r7, #4] /* Clear PLL3ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); 800fe28: 4b13 ldr r3, [pc, #76] @ (800fe78 ) 800fe2a: 681b ldr r3, [r3, #0] 800fe2c: 4a12 ldr r2, [pc, #72] @ (800fe78 ) 800fe2e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800fe32: 6013 str r3, [r2, #0] /* Wait till PLL3 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 800fe34: e008 b.n 800fe48 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 800fe36: f7fd ff21 bl 800dc7c 800fe3a: 4602 mov r2, r0 800fe3c: 687b ldr r3, [r7, #4] 800fe3e: 1ad3 subs r3, r2, r3 800fe40: 2b64 cmp r3, #100 @ 0x64 800fe42: d901 bls.n 800fe48 { return HAL_TIMEOUT; 800fe44: 2303 movs r3, #3 800fe46: e012 b.n 800fe6e while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 800fe48: 4b0b ldr r3, [pc, #44] @ (800fe78 ) 800fe4a: 681b ldr r3, [r3, #0] 800fe4c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800fe50: 2b00 cmp r3, #0 800fe52: d1f0 bne.n 800fe36 } #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_CFGR2_PREDIV1) /* Reset CFGR2 register */ CLEAR_REG(RCC->CFGR2); 800fe54: 4b08 ldr r3, [pc, #32] @ (800fe78 ) 800fe56: 2200 movs r2, #0 800fe58: 62da str r2, [r3, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1 */ /* Reset all CSR flags */ SET_BIT(RCC->CSR, RCC_CSR_RMVF); 800fe5a: 4b07 ldr r3, [pc, #28] @ (800fe78 ) 800fe5c: 6a5b ldr r3, [r3, #36] @ 0x24 800fe5e: 4a06 ldr r2, [pc, #24] @ (800fe78 ) 800fe60: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800fe64: 6253 str r3, [r2, #36] @ 0x24 /* Disable all interrupts */ CLEAR_REG(RCC->CIR); 800fe66: 4b04 ldr r3, [pc, #16] @ (800fe78 ) 800fe68: 2200 movs r2, #0 800fe6a: 609a str r2, [r3, #8] return HAL_OK; 800fe6c: 2300 movs r3, #0 } 800fe6e: 4618 mov r0, r3 800fe70: 3708 adds r7, #8 800fe72: 46bd mov sp, r7 800fe74: bd80 pop {r7, pc} 800fe76: bf00 nop 800fe78: 40021000 .word 0x40021000 800fe7c: 20000080 .word 0x20000080 800fe80: 007a1200 .word 0x007a1200 800fe84: 20000084 .word 0x20000084 0800fe88 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800fe88: b580 push {r7, lr} 800fe8a: b086 sub sp, #24 800fe8c: af00 add r7, sp, #0 800fe8e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 800fe90: 687b ldr r3, [r7, #4] 800fe92: 2b00 cmp r3, #0 800fe94: d101 bne.n 800fe9a { return HAL_ERROR; 800fe96: 2301 movs r3, #1 800fe98: e304 b.n 80104a4 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800fe9a: 687b ldr r3, [r7, #4] 800fe9c: 681b ldr r3, [r3, #0] 800fe9e: f003 0301 and.w r3, r3, #1 800fea2: 2b00 cmp r3, #0 800fea4: f000 8087 beq.w 800ffb6 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 800fea8: 4b92 ldr r3, [pc, #584] @ (80100f4 ) 800feaa: 685b ldr r3, [r3, #4] 800feac: f003 030c and.w r3, r3, #12 800feb0: 2b04 cmp r3, #4 800feb2: d00c beq.n 800fece || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 800feb4: 4b8f ldr r3, [pc, #572] @ (80100f4 ) 800feb6: 685b ldr r3, [r3, #4] 800feb8: f003 030c and.w r3, r3, #12 800febc: 2b08 cmp r3, #8 800febe: d112 bne.n 800fee6 800fec0: 4b8c ldr r3, [pc, #560] @ (80100f4 ) 800fec2: 685b ldr r3, [r3, #4] 800fec4: f403 3380 and.w r3, r3, #65536 @ 0x10000 800fec8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800fecc: d10b bne.n 800fee6 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800fece: 4b89 ldr r3, [pc, #548] @ (80100f4 ) 800fed0: 681b ldr r3, [r3, #0] 800fed2: f403 3300 and.w r3, r3, #131072 @ 0x20000 800fed6: 2b00 cmp r3, #0 800fed8: d06c beq.n 800ffb4 800feda: 687b ldr r3, [r7, #4] 800fedc: 689b ldr r3, [r3, #8] 800fede: 2b00 cmp r3, #0 800fee0: d168 bne.n 800ffb4 { return HAL_ERROR; 800fee2: 2301 movs r3, #1 800fee4: e2de b.n 80104a4 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800fee6: 687b ldr r3, [r7, #4] 800fee8: 689b ldr r3, [r3, #8] 800feea: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800feee: d106 bne.n 800fefe 800fef0: 4b80 ldr r3, [pc, #512] @ (80100f4 ) 800fef2: 681b ldr r3, [r3, #0] 800fef4: 4a7f ldr r2, [pc, #508] @ (80100f4 ) 800fef6: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800fefa: 6013 str r3, [r2, #0] 800fefc: e02e b.n 800ff5c 800fefe: 687b ldr r3, [r7, #4] 800ff00: 689b ldr r3, [r3, #8] 800ff02: 2b00 cmp r3, #0 800ff04: d10c bne.n 800ff20 800ff06: 4b7b ldr r3, [pc, #492] @ (80100f4 ) 800ff08: 681b ldr r3, [r3, #0] 800ff0a: 4a7a ldr r2, [pc, #488] @ (80100f4 ) 800ff0c: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800ff10: 6013 str r3, [r2, #0] 800ff12: 4b78 ldr r3, [pc, #480] @ (80100f4 ) 800ff14: 681b ldr r3, [r3, #0] 800ff16: 4a77 ldr r2, [pc, #476] @ (80100f4 ) 800ff18: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800ff1c: 6013 str r3, [r2, #0] 800ff1e: e01d b.n 800ff5c 800ff20: 687b ldr r3, [r7, #4] 800ff22: 689b ldr r3, [r3, #8] 800ff24: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800ff28: d10c bne.n 800ff44 800ff2a: 4b72 ldr r3, [pc, #456] @ (80100f4 ) 800ff2c: 681b ldr r3, [r3, #0] 800ff2e: 4a71 ldr r2, [pc, #452] @ (80100f4 ) 800ff30: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800ff34: 6013 str r3, [r2, #0] 800ff36: 4b6f ldr r3, [pc, #444] @ (80100f4 ) 800ff38: 681b ldr r3, [r3, #0] 800ff3a: 4a6e ldr r2, [pc, #440] @ (80100f4 ) 800ff3c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800ff40: 6013 str r3, [r2, #0] 800ff42: e00b b.n 800ff5c 800ff44: 4b6b ldr r3, [pc, #428] @ (80100f4 ) 800ff46: 681b ldr r3, [r3, #0] 800ff48: 4a6a ldr r2, [pc, #424] @ (80100f4 ) 800ff4a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800ff4e: 6013 str r3, [r2, #0] 800ff50: 4b68 ldr r3, [pc, #416] @ (80100f4 ) 800ff52: 681b ldr r3, [r3, #0] 800ff54: 4a67 ldr r2, [pc, #412] @ (80100f4 ) 800ff56: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800ff5a: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 800ff5c: 687b ldr r3, [r7, #4] 800ff5e: 689b ldr r3, [r3, #8] 800ff60: 2b00 cmp r3, #0 800ff62: d013 beq.n 800ff8c { /* Get Start Tick */ tickstart = HAL_GetTick(); 800ff64: f7fd fe8a bl 800dc7c 800ff68: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800ff6a: e008 b.n 800ff7e { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800ff6c: f7fd fe86 bl 800dc7c 800ff70: 4602 mov r2, r0 800ff72: 693b ldr r3, [r7, #16] 800ff74: 1ad3 subs r3, r2, r3 800ff76: 2b64 cmp r3, #100 @ 0x64 800ff78: d901 bls.n 800ff7e { return HAL_TIMEOUT; 800ff7a: 2303 movs r3, #3 800ff7c: e292 b.n 80104a4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800ff7e: 4b5d ldr r3, [pc, #372] @ (80100f4 ) 800ff80: 681b ldr r3, [r3, #0] 800ff82: f403 3300 and.w r3, r3, #131072 @ 0x20000 800ff86: 2b00 cmp r3, #0 800ff88: d0f0 beq.n 800ff6c 800ff8a: e014 b.n 800ffb6 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 800ff8c: f7fd fe76 bl 800dc7c 800ff90: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800ff92: e008 b.n 800ffa6 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800ff94: f7fd fe72 bl 800dc7c 800ff98: 4602 mov r2, r0 800ff9a: 693b ldr r3, [r7, #16] 800ff9c: 1ad3 subs r3, r2, r3 800ff9e: 2b64 cmp r3, #100 @ 0x64 800ffa0: d901 bls.n 800ffa6 { return HAL_TIMEOUT; 800ffa2: 2303 movs r3, #3 800ffa4: e27e b.n 80104a4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800ffa6: 4b53 ldr r3, [pc, #332] @ (80100f4 ) 800ffa8: 681b ldr r3, [r3, #0] 800ffaa: f403 3300 and.w r3, r3, #131072 @ 0x20000 800ffae: 2b00 cmp r3, #0 800ffb0: d1f0 bne.n 800ff94 800ffb2: e000 b.n 800ffb6 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800ffb4: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800ffb6: 687b ldr r3, [r7, #4] 800ffb8: 681b ldr r3, [r3, #0] 800ffba: f003 0302 and.w r3, r3, #2 800ffbe: 2b00 cmp r3, #0 800ffc0: d063 beq.n 801008a /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 800ffc2: 4b4c ldr r3, [pc, #304] @ (80100f4 ) 800ffc4: 685b ldr r3, [r3, #4] 800ffc6: f003 030c and.w r3, r3, #12 800ffca: 2b00 cmp r3, #0 800ffcc: d00b beq.n 800ffe6 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 800ffce: 4b49 ldr r3, [pc, #292] @ (80100f4 ) 800ffd0: 685b ldr r3, [r3, #4] 800ffd2: f003 030c and.w r3, r3, #12 800ffd6: 2b08 cmp r3, #8 800ffd8: d11c bne.n 8010014 800ffda: 4b46 ldr r3, [pc, #280] @ (80100f4 ) 800ffdc: 685b ldr r3, [r3, #4] 800ffde: f403 3380 and.w r3, r3, #65536 @ 0x10000 800ffe2: 2b00 cmp r3, #0 800ffe4: d116 bne.n 8010014 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800ffe6: 4b43 ldr r3, [pc, #268] @ (80100f4 ) 800ffe8: 681b ldr r3, [r3, #0] 800ffea: f003 0302 and.w r3, r3, #2 800ffee: 2b00 cmp r3, #0 800fff0: d005 beq.n 800fffe 800fff2: 687b ldr r3, [r7, #4] 800fff4: 695b ldr r3, [r3, #20] 800fff6: 2b01 cmp r3, #1 800fff8: d001 beq.n 800fffe { return HAL_ERROR; 800fffa: 2301 movs r3, #1 800fffc: e252 b.n 80104a4 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800fffe: 4b3d ldr r3, [pc, #244] @ (80100f4 ) 8010000: 681b ldr r3, [r3, #0] 8010002: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8010006: 687b ldr r3, [r7, #4] 8010008: 699b ldr r3, [r3, #24] 801000a: 00db lsls r3, r3, #3 801000c: 4939 ldr r1, [pc, #228] @ (80100f4 ) 801000e: 4313 orrs r3, r2 8010010: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8010012: e03a b.n 801008a } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8010014: 687b ldr r3, [r7, #4] 8010016: 695b ldr r3, [r3, #20] 8010018: 2b00 cmp r3, #0 801001a: d020 beq.n 801005e { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 801001c: 4b36 ldr r3, [pc, #216] @ (80100f8 ) 801001e: 2201 movs r2, #1 8010020: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010022: f7fd fe2b bl 800dc7c 8010026: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8010028: e008 b.n 801003c { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 801002a: f7fd fe27 bl 800dc7c 801002e: 4602 mov r2, r0 8010030: 693b ldr r3, [r7, #16] 8010032: 1ad3 subs r3, r2, r3 8010034: 2b02 cmp r3, #2 8010036: d901 bls.n 801003c { return HAL_TIMEOUT; 8010038: 2303 movs r3, #3 801003a: e233 b.n 80104a4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 801003c: 4b2d ldr r3, [pc, #180] @ (80100f4 ) 801003e: 681b ldr r3, [r3, #0] 8010040: f003 0302 and.w r3, r3, #2 8010044: 2b00 cmp r3, #0 8010046: d0f0 beq.n 801002a } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8010048: 4b2a ldr r3, [pc, #168] @ (80100f4 ) 801004a: 681b ldr r3, [r3, #0] 801004c: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8010050: 687b ldr r3, [r7, #4] 8010052: 699b ldr r3, [r3, #24] 8010054: 00db lsls r3, r3, #3 8010056: 4927 ldr r1, [pc, #156] @ (80100f4 ) 8010058: 4313 orrs r3, r2 801005a: 600b str r3, [r1, #0] 801005c: e015 b.n 801008a } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 801005e: 4b26 ldr r3, [pc, #152] @ (80100f8 ) 8010060: 2200 movs r2, #0 8010062: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010064: f7fd fe0a bl 800dc7c 8010068: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 801006a: e008 b.n 801007e { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 801006c: f7fd fe06 bl 800dc7c 8010070: 4602 mov r2, r0 8010072: 693b ldr r3, [r7, #16] 8010074: 1ad3 subs r3, r2, r3 8010076: 2b02 cmp r3, #2 8010078: d901 bls.n 801007e { return HAL_TIMEOUT; 801007a: 2303 movs r3, #3 801007c: e212 b.n 80104a4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 801007e: 4b1d ldr r3, [pc, #116] @ (80100f4 ) 8010080: 681b ldr r3, [r3, #0] 8010082: f003 0302 and.w r3, r3, #2 8010086: 2b00 cmp r3, #0 8010088: d1f0 bne.n 801006c } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 801008a: 687b ldr r3, [r7, #4] 801008c: 681b ldr r3, [r3, #0] 801008e: f003 0308 and.w r3, r3, #8 8010092: 2b00 cmp r3, #0 8010094: d03a beq.n 801010c { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8010096: 687b ldr r3, [r7, #4] 8010098: 69db ldr r3, [r3, #28] 801009a: 2b00 cmp r3, #0 801009c: d019 beq.n 80100d2 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 801009e: 4b17 ldr r3, [pc, #92] @ (80100fc ) 80100a0: 2201 movs r2, #1 80100a2: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80100a4: f7fd fdea bl 800dc7c 80100a8: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 80100aa: e008 b.n 80100be { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80100ac: f7fd fde6 bl 800dc7c 80100b0: 4602 mov r2, r0 80100b2: 693b ldr r3, [r7, #16] 80100b4: 1ad3 subs r3, r2, r3 80100b6: 2b02 cmp r3, #2 80100b8: d901 bls.n 80100be { return HAL_TIMEOUT; 80100ba: 2303 movs r3, #3 80100bc: e1f2 b.n 80104a4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 80100be: 4b0d ldr r3, [pc, #52] @ (80100f4 ) 80100c0: 6a5b ldr r3, [r3, #36] @ 0x24 80100c2: f003 0302 and.w r3, r3, #2 80100c6: 2b00 cmp r3, #0 80100c8: d0f0 beq.n 80100ac } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 80100ca: 2001 movs r0, #1 80100cc: f000 fbca bl 8010864 80100d0: e01c b.n 801010c } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 80100d2: 4b0a ldr r3, [pc, #40] @ (80100fc ) 80100d4: 2200 movs r2, #0 80100d6: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80100d8: f7fd fdd0 bl 800dc7c 80100dc: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80100de: e00f b.n 8010100 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80100e0: f7fd fdcc bl 800dc7c 80100e4: 4602 mov r2, r0 80100e6: 693b ldr r3, [r7, #16] 80100e8: 1ad3 subs r3, r2, r3 80100ea: 2b02 cmp r3, #2 80100ec: d908 bls.n 8010100 { return HAL_TIMEOUT; 80100ee: 2303 movs r3, #3 80100f0: e1d8 b.n 80104a4 80100f2: bf00 nop 80100f4: 40021000 .word 0x40021000 80100f8: 42420000 .word 0x42420000 80100fc: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8010100: 4b9b ldr r3, [pc, #620] @ (8010370 ) 8010102: 6a5b ldr r3, [r3, #36] @ 0x24 8010104: f003 0302 and.w r3, r3, #2 8010108: 2b00 cmp r3, #0 801010a: d1e9 bne.n 80100e0 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 801010c: 687b ldr r3, [r7, #4] 801010e: 681b ldr r3, [r3, #0] 8010110: f003 0304 and.w r3, r3, #4 8010114: 2b00 cmp r3, #0 8010116: f000 80a6 beq.w 8010266 { FlagStatus pwrclkchanged = RESET; 801011a: 2300 movs r3, #0 801011c: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 801011e: 4b94 ldr r3, [pc, #592] @ (8010370 ) 8010120: 69db ldr r3, [r3, #28] 8010122: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010126: 2b00 cmp r3, #0 8010128: d10d bne.n 8010146 { __HAL_RCC_PWR_CLK_ENABLE(); 801012a: 4b91 ldr r3, [pc, #580] @ (8010370 ) 801012c: 69db ldr r3, [r3, #28] 801012e: 4a90 ldr r2, [pc, #576] @ (8010370 ) 8010130: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8010134: 61d3 str r3, [r2, #28] 8010136: 4b8e ldr r3, [pc, #568] @ (8010370 ) 8010138: 69db ldr r3, [r3, #28] 801013a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 801013e: 60bb str r3, [r7, #8] 8010140: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8010142: 2301 movs r3, #1 8010144: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010146: 4b8b ldr r3, [pc, #556] @ (8010374 ) 8010148: 681b ldr r3, [r3, #0] 801014a: f403 7380 and.w r3, r3, #256 @ 0x100 801014e: 2b00 cmp r3, #0 8010150: d118 bne.n 8010184 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8010152: 4b88 ldr r3, [pc, #544] @ (8010374 ) 8010154: 681b ldr r3, [r3, #0] 8010156: 4a87 ldr r2, [pc, #540] @ (8010374 ) 8010158: f443 7380 orr.w r3, r3, #256 @ 0x100 801015c: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 801015e: f7fd fd8d bl 800dc7c 8010162: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010164: e008 b.n 8010178 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8010166: f7fd fd89 bl 800dc7c 801016a: 4602 mov r2, r0 801016c: 693b ldr r3, [r7, #16] 801016e: 1ad3 subs r3, r2, r3 8010170: 2b64 cmp r3, #100 @ 0x64 8010172: d901 bls.n 8010178 { return HAL_TIMEOUT; 8010174: 2303 movs r3, #3 8010176: e195 b.n 80104a4 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010178: 4b7e ldr r3, [pc, #504] @ (8010374 ) 801017a: 681b ldr r3, [r3, #0] 801017c: f403 7380 and.w r3, r3, #256 @ 0x100 8010180: 2b00 cmp r3, #0 8010182: d0f0 beq.n 8010166 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8010184: 687b ldr r3, [r7, #4] 8010186: 691b ldr r3, [r3, #16] 8010188: 2b01 cmp r3, #1 801018a: d106 bne.n 801019a 801018c: 4b78 ldr r3, [pc, #480] @ (8010370 ) 801018e: 6a1b ldr r3, [r3, #32] 8010190: 4a77 ldr r2, [pc, #476] @ (8010370 ) 8010192: f043 0301 orr.w r3, r3, #1 8010196: 6213 str r3, [r2, #32] 8010198: e02d b.n 80101f6 801019a: 687b ldr r3, [r7, #4] 801019c: 691b ldr r3, [r3, #16] 801019e: 2b00 cmp r3, #0 80101a0: d10c bne.n 80101bc 80101a2: 4b73 ldr r3, [pc, #460] @ (8010370 ) 80101a4: 6a1b ldr r3, [r3, #32] 80101a6: 4a72 ldr r2, [pc, #456] @ (8010370 ) 80101a8: f023 0301 bic.w r3, r3, #1 80101ac: 6213 str r3, [r2, #32] 80101ae: 4b70 ldr r3, [pc, #448] @ (8010370 ) 80101b0: 6a1b ldr r3, [r3, #32] 80101b2: 4a6f ldr r2, [pc, #444] @ (8010370 ) 80101b4: f023 0304 bic.w r3, r3, #4 80101b8: 6213 str r3, [r2, #32] 80101ba: e01c b.n 80101f6 80101bc: 687b ldr r3, [r7, #4] 80101be: 691b ldr r3, [r3, #16] 80101c0: 2b05 cmp r3, #5 80101c2: d10c bne.n 80101de 80101c4: 4b6a ldr r3, [pc, #424] @ (8010370 ) 80101c6: 6a1b ldr r3, [r3, #32] 80101c8: 4a69 ldr r2, [pc, #420] @ (8010370 ) 80101ca: f043 0304 orr.w r3, r3, #4 80101ce: 6213 str r3, [r2, #32] 80101d0: 4b67 ldr r3, [pc, #412] @ (8010370 ) 80101d2: 6a1b ldr r3, [r3, #32] 80101d4: 4a66 ldr r2, [pc, #408] @ (8010370 ) 80101d6: f043 0301 orr.w r3, r3, #1 80101da: 6213 str r3, [r2, #32] 80101dc: e00b b.n 80101f6 80101de: 4b64 ldr r3, [pc, #400] @ (8010370 ) 80101e0: 6a1b ldr r3, [r3, #32] 80101e2: 4a63 ldr r2, [pc, #396] @ (8010370 ) 80101e4: f023 0301 bic.w r3, r3, #1 80101e8: 6213 str r3, [r2, #32] 80101ea: 4b61 ldr r3, [pc, #388] @ (8010370 ) 80101ec: 6a1b ldr r3, [r3, #32] 80101ee: 4a60 ldr r2, [pc, #384] @ (8010370 ) 80101f0: f023 0304 bic.w r3, r3, #4 80101f4: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 80101f6: 687b ldr r3, [r7, #4] 80101f8: 691b ldr r3, [r3, #16] 80101fa: 2b00 cmp r3, #0 80101fc: d015 beq.n 801022a { /* Get Start Tick */ tickstart = HAL_GetTick(); 80101fe: f7fd fd3d bl 800dc7c 8010202: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8010204: e00a b.n 801021c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8010206: f7fd fd39 bl 800dc7c 801020a: 4602 mov r2, r0 801020c: 693b ldr r3, [r7, #16] 801020e: 1ad3 subs r3, r2, r3 8010210: f241 3288 movw r2, #5000 @ 0x1388 8010214: 4293 cmp r3, r2 8010216: d901 bls.n 801021c { return HAL_TIMEOUT; 8010218: 2303 movs r3, #3 801021a: e143 b.n 80104a4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 801021c: 4b54 ldr r3, [pc, #336] @ (8010370 ) 801021e: 6a1b ldr r3, [r3, #32] 8010220: f003 0302 and.w r3, r3, #2 8010224: 2b00 cmp r3, #0 8010226: d0ee beq.n 8010206 8010228: e014 b.n 8010254 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 801022a: f7fd fd27 bl 800dc7c 801022e: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8010230: e00a b.n 8010248 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8010232: f7fd fd23 bl 800dc7c 8010236: 4602 mov r2, r0 8010238: 693b ldr r3, [r7, #16] 801023a: 1ad3 subs r3, r2, r3 801023c: f241 3288 movw r2, #5000 @ 0x1388 8010240: 4293 cmp r3, r2 8010242: d901 bls.n 8010248 { return HAL_TIMEOUT; 8010244: 2303 movs r3, #3 8010246: e12d b.n 80104a4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8010248: 4b49 ldr r3, [pc, #292] @ (8010370 ) 801024a: 6a1b ldr r3, [r3, #32] 801024c: f003 0302 and.w r3, r3, #2 8010250: 2b00 cmp r3, #0 8010252: d1ee bne.n 8010232 } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8010254: 7dfb ldrb r3, [r7, #23] 8010256: 2b01 cmp r3, #1 8010258: d105 bne.n 8010266 { __HAL_RCC_PWR_CLK_DISABLE(); 801025a: 4b45 ldr r3, [pc, #276] @ (8010370 ) 801025c: 69db ldr r3, [r3, #28] 801025e: 4a44 ldr r2, [pc, #272] @ (8010370 ) 8010260: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8010264: 61d3 str r3, [r2, #28] #if defined(RCC_CR_PLL2ON) /*-------------------------------- PLL2 Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) 8010266: 687b ldr r3, [r7, #4] 8010268: 6adb ldr r3, [r3, #44] @ 0x2c 801026a: 2b00 cmp r3, #0 801026c: f000 808c beq.w 8010388 { /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 8010270: 4b3f ldr r3, [pc, #252] @ (8010370 ) 8010272: 685b ldr r3, [r3, #4] 8010274: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010278: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 801027c: d10e bne.n 801029c (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 801027e: 4b3c ldr r3, [pc, #240] @ (8010370 ) 8010280: 685b ldr r3, [r3, #4] 8010282: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 8010286: 2b08 cmp r3, #8 8010288: d108 bne.n 801029c ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) 801028a: 4b39 ldr r3, [pc, #228] @ (8010370 ) 801028c: 6adb ldr r3, [r3, #44] @ 0x2c 801028e: f403 3380 and.w r3, r3, #65536 @ 0x10000 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 8010292: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010296: d101 bne.n 801029c { return HAL_ERROR; 8010298: 2301 movs r3, #1 801029a: e103 b.n 80104a4 } else { if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) 801029c: 687b ldr r3, [r7, #4] 801029e: 6adb ldr r3, [r3, #44] @ 0x2c 80102a0: 2b02 cmp r3, #2 80102a2: d14e bne.n 8010342 assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); /* Prediv2 can be written only when the PLLI2S is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 80102a4: 4b32 ldr r3, [pc, #200] @ (8010370 ) 80102a6: 681b ldr r3, [r3, #0] 80102a8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80102ac: 2b00 cmp r3, #0 80102ae: d009 beq.n 80102c4 (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) 80102b0: 4b2f ldr r3, [pc, #188] @ (8010370 ) 80102b2: 6adb ldr r3, [r3, #44] @ 0x2c 80102b4: f003 02f0 and.w r2, r3, #240 @ 0xf0 80102b8: 687b ldr r3, [r7, #4] 80102ba: 6b5b ldr r3, [r3, #52] @ 0x34 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 80102bc: 429a cmp r2, r3 80102be: d001 beq.n 80102c4 { return HAL_ERROR; 80102c0: 2301 movs r3, #1 80102c2: e0ef b.n 80104a4 } /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 80102c4: 4b2c ldr r3, [pc, #176] @ (8010378 ) 80102c6: 2200 movs r2, #0 80102c8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80102ca: f7fd fcd7 bl 800dc7c 80102ce: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 80102d0: e008 b.n 80102e4 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 80102d2: f7fd fcd3 bl 800dc7c 80102d6: 4602 mov r2, r0 80102d8: 693b ldr r3, [r7, #16] 80102da: 1ad3 subs r3, r2, r3 80102dc: 2b64 cmp r3, #100 @ 0x64 80102de: d901 bls.n 80102e4 { return HAL_TIMEOUT; 80102e0: 2303 movs r3, #3 80102e2: e0df b.n 80104a4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 80102e4: 4b22 ldr r3, [pc, #136] @ (8010370 ) 80102e6: 681b ldr r3, [r3, #0] 80102e8: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80102ec: 2b00 cmp r3, #0 80102ee: d1f0 bne.n 80102d2 } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); 80102f0: 4b1f ldr r3, [pc, #124] @ (8010370 ) 80102f2: 6adb ldr r3, [r3, #44] @ 0x2c 80102f4: f023 02f0 bic.w r2, r3, #240 @ 0xf0 80102f8: 687b ldr r3, [r7, #4] 80102fa: 6b5b ldr r3, [r3, #52] @ 0x34 80102fc: 491c ldr r1, [pc, #112] @ (8010370 ) 80102fe: 4313 orrs r3, r2 8010300: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); 8010302: 4b1b ldr r3, [pc, #108] @ (8010370 ) 8010304: 6adb ldr r3, [r3, #44] @ 0x2c 8010306: f423 6270 bic.w r2, r3, #3840 @ 0xf00 801030a: 687b ldr r3, [r7, #4] 801030c: 6b1b ldr r3, [r3, #48] @ 0x30 801030e: 4918 ldr r1, [pc, #96] @ (8010370 ) 8010310: 4313 orrs r3, r2 8010312: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); 8010314: 4b18 ldr r3, [pc, #96] @ (8010378 ) 8010316: 2201 movs r2, #1 8010318: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 801031a: f7fd fcaf bl 800dc7c 801031e: 6138 str r0, [r7, #16] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 8010320: e008 b.n 8010334 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8010322: f7fd fcab bl 800dc7c 8010326: 4602 mov r2, r0 8010328: 693b ldr r3, [r7, #16] 801032a: 1ad3 subs r3, r2, r3 801032c: 2b64 cmp r3, #100 @ 0x64 801032e: d901 bls.n 8010334 { return HAL_TIMEOUT; 8010330: 2303 movs r3, #3 8010332: e0b7 b.n 80104a4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 8010334: 4b0e ldr r3, [pc, #56] @ (8010370 ) 8010336: 681b ldr r3, [r3, #0] 8010338: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 801033c: 2b00 cmp r3, #0 801033e: d0f0 beq.n 8010322 8010340: e022 b.n 8010388 } } else { /* Set PREDIV1 source to HSE */ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); 8010342: 4b0b ldr r3, [pc, #44] @ (8010370 ) 8010344: 6adb ldr r3, [r3, #44] @ 0x2c 8010346: 4a0a ldr r2, [pc, #40] @ (8010370 ) 8010348: f423 3380 bic.w r3, r3, #65536 @ 0x10000 801034c: 62d3 str r3, [r2, #44] @ 0x2c /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 801034e: 4b0a ldr r3, [pc, #40] @ (8010378 ) 8010350: 2200 movs r2, #0 8010352: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010354: f7fd fc92 bl 800dc7c 8010358: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 801035a: e00f b.n 801037c { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 801035c: f7fd fc8e bl 800dc7c 8010360: 4602 mov r2, r0 8010362: 693b ldr r3, [r7, #16] 8010364: 1ad3 subs r3, r2, r3 8010366: 2b64 cmp r3, #100 @ 0x64 8010368: d908 bls.n 801037c { return HAL_TIMEOUT; 801036a: 2303 movs r3, #3 801036c: e09a b.n 80104a4 801036e: bf00 nop 8010370: 40021000 .word 0x40021000 8010374: 40007000 .word 0x40007000 8010378: 42420068 .word 0x42420068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 801037c: 4b4b ldr r3, [pc, #300] @ (80104ac ) 801037e: 681b ldr r3, [r3, #0] 8010380: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8010384: 2b00 cmp r3, #0 8010386: d1e9 bne.n 801035c #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8010388: 687b ldr r3, [r7, #4] 801038a: 6a1b ldr r3, [r3, #32] 801038c: 2b00 cmp r3, #0 801038e: f000 8088 beq.w 80104a2 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8010392: 4b46 ldr r3, [pc, #280] @ (80104ac ) 8010394: 685b ldr r3, [r3, #4] 8010396: f003 030c and.w r3, r3, #12 801039a: 2b08 cmp r3, #8 801039c: d068 beq.n 8010470 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 801039e: 687b ldr r3, [r7, #4] 80103a0: 6a1b ldr r3, [r3, #32] 80103a2: 2b02 cmp r3, #2 80103a4: d14d bne.n 8010442 /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80103a6: 4b42 ldr r3, [pc, #264] @ (80104b0 ) 80103a8: 2200 movs r2, #0 80103aa: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80103ac: f7fd fc66 bl 800dc7c 80103b0: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80103b2: e008 b.n 80103c6 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80103b4: f7fd fc62 bl 800dc7c 80103b8: 4602 mov r2, r0 80103ba: 693b ldr r3, [r7, #16] 80103bc: 1ad3 subs r3, r2, r3 80103be: 2b02 cmp r3, #2 80103c0: d901 bls.n 80103c6 { return HAL_TIMEOUT; 80103c2: 2303 movs r3, #3 80103c4: e06e b.n 80104a4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80103c6: 4b39 ldr r3, [pc, #228] @ (80104ac ) 80103c8: 681b ldr r3, [r3, #0] 80103ca: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80103ce: 2b00 cmp r3, #0 80103d0: d1f0 bne.n 80103b4 } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 80103d2: 687b ldr r3, [r7, #4] 80103d4: 6a5b ldr r3, [r3, #36] @ 0x24 80103d6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80103da: d10f bne.n 80103fc assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); #if defined(RCC_CFGR2_PREDIV1SRC) assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); 80103dc: 4b33 ldr r3, [pc, #204] @ (80104ac ) 80103de: 6ada ldr r2, [r3, #44] @ 0x2c 80103e0: 687b ldr r3, [r7, #4] 80103e2: 685b ldr r3, [r3, #4] 80103e4: 4931 ldr r1, [pc, #196] @ (80104ac ) 80103e6: 4313 orrs r3, r2 80103e8: 62cb str r3, [r1, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 80103ea: 4b30 ldr r3, [pc, #192] @ (80104ac ) 80103ec: 6adb ldr r3, [r3, #44] @ 0x2c 80103ee: f023 020f bic.w r2, r3, #15 80103f2: 687b ldr r3, [r7, #4] 80103f4: 68db ldr r3, [r3, #12] 80103f6: 492d ldr r1, [pc, #180] @ (80104ac ) 80103f8: 4313 orrs r3, r2 80103fa: 62cb str r3, [r1, #44] @ 0x2c } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80103fc: 4b2b ldr r3, [pc, #172] @ (80104ac ) 80103fe: 685b ldr r3, [r3, #4] 8010400: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 8010404: 687b ldr r3, [r7, #4] 8010406: 6a59 ldr r1, [r3, #36] @ 0x24 8010408: 687b ldr r3, [r7, #4] 801040a: 6a9b ldr r3, [r3, #40] @ 0x28 801040c: 430b orrs r3, r1 801040e: 4927 ldr r1, [pc, #156] @ (80104ac ) 8010410: 4313 orrs r3, r2 8010412: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8010414: 4b26 ldr r3, [pc, #152] @ (80104b0 ) 8010416: 2201 movs r2, #1 8010418: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 801041a: f7fd fc2f bl 800dc7c 801041e: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8010420: e008 b.n 8010434 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8010422: f7fd fc2b bl 800dc7c 8010426: 4602 mov r2, r0 8010428: 693b ldr r3, [r7, #16] 801042a: 1ad3 subs r3, r2, r3 801042c: 2b02 cmp r3, #2 801042e: d901 bls.n 8010434 { return HAL_TIMEOUT; 8010430: 2303 movs r3, #3 8010432: e037 b.n 80104a4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8010434: 4b1d ldr r3, [pc, #116] @ (80104ac ) 8010436: 681b ldr r3, [r3, #0] 8010438: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 801043c: 2b00 cmp r3, #0 801043e: d0f0 beq.n 8010422 8010440: e02f b.n 80104a2 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8010442: 4b1b ldr r3, [pc, #108] @ (80104b0 ) 8010444: 2200 movs r2, #0 8010446: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010448: f7fd fc18 bl 800dc7c 801044c: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 801044e: e008 b.n 8010462 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8010450: f7fd fc14 bl 800dc7c 8010454: 4602 mov r2, r0 8010456: 693b ldr r3, [r7, #16] 8010458: 1ad3 subs r3, r2, r3 801045a: 2b02 cmp r3, #2 801045c: d901 bls.n 8010462 { return HAL_TIMEOUT; 801045e: 2303 movs r3, #3 8010460: e020 b.n 80104a4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8010462: 4b12 ldr r3, [pc, #72] @ (80104ac ) 8010464: 681b ldr r3, [r3, #0] 8010466: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 801046a: 2b00 cmp r3, #0 801046c: d1f0 bne.n 8010450 801046e: e018 b.n 80104a2 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8010470: 687b ldr r3, [r7, #4] 8010472: 6a1b ldr r3, [r3, #32] 8010474: 2b01 cmp r3, #1 8010476: d101 bne.n 801047c { return HAL_ERROR; 8010478: 2301 movs r3, #1 801047a: e013 b.n 80104a4 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 801047c: 4b0b ldr r3, [pc, #44] @ (80104ac ) 801047e: 685b ldr r3, [r3, #4] 8010480: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8010482: 68fb ldr r3, [r7, #12] 8010484: f403 3280 and.w r2, r3, #65536 @ 0x10000 8010488: 687b ldr r3, [r7, #4] 801048a: 6a5b ldr r3, [r3, #36] @ 0x24 801048c: 429a cmp r2, r3 801048e: d106 bne.n 801049e (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 8010490: 68fb ldr r3, [r7, #12] 8010492: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 8010496: 687b ldr r3, [r7, #4] 8010498: 6a9b ldr r3, [r3, #40] @ 0x28 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 801049a: 429a cmp r2, r3 801049c: d001 beq.n 80104a2 { return HAL_ERROR; 801049e: 2301 movs r3, #1 80104a0: e000 b.n 80104a4 } } } } return HAL_OK; 80104a2: 2300 movs r3, #0 } 80104a4: 4618 mov r0, r3 80104a6: 3718 adds r7, #24 80104a8: 46bd mov sp, r7 80104aa: bd80 pop {r7, pc} 80104ac: 40021000 .word 0x40021000 80104b0: 42420060 .word 0x42420060 080104b4 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 80104b4: b580 push {r7, lr} 80104b6: b084 sub sp, #16 80104b8: af00 add r7, sp, #0 80104ba: 6078 str r0, [r7, #4] 80104bc: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 80104be: 687b ldr r3, [r7, #4] 80104c0: 2b00 cmp r3, #0 80104c2: d101 bne.n 80104c8 { return HAL_ERROR; 80104c4: 2301 movs r3, #1 80104c6: e0d0 b.n 801066a must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 80104c8: 4b6a ldr r3, [pc, #424] @ (8010674 ) 80104ca: 681b ldr r3, [r3, #0] 80104cc: f003 0307 and.w r3, r3, #7 80104d0: 683a ldr r2, [r7, #0] 80104d2: 429a cmp r2, r3 80104d4: d910 bls.n 80104f8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80104d6: 4b67 ldr r3, [pc, #412] @ (8010674 ) 80104d8: 681b ldr r3, [r3, #0] 80104da: f023 0207 bic.w r2, r3, #7 80104de: 4965 ldr r1, [pc, #404] @ (8010674 ) 80104e0: 683b ldr r3, [r7, #0] 80104e2: 4313 orrs r3, r2 80104e4: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80104e6: 4b63 ldr r3, [pc, #396] @ (8010674 ) 80104e8: 681b ldr r3, [r3, #0] 80104ea: f003 0307 and.w r3, r3, #7 80104ee: 683a ldr r2, [r7, #0] 80104f0: 429a cmp r2, r3 80104f2: d001 beq.n 80104f8 { return HAL_ERROR; 80104f4: 2301 movs r3, #1 80104f6: e0b8 b.n 801066a } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 80104f8: 687b ldr r3, [r7, #4] 80104fa: 681b ldr r3, [r3, #0] 80104fc: f003 0302 and.w r3, r3, #2 8010500: 2b00 cmp r3, #0 8010502: d020 beq.n 8010546 { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8010504: 687b ldr r3, [r7, #4] 8010506: 681b ldr r3, [r3, #0] 8010508: f003 0304 and.w r3, r3, #4 801050c: 2b00 cmp r3, #0 801050e: d005 beq.n 801051c { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8010510: 4b59 ldr r3, [pc, #356] @ (8010678 ) 8010512: 685b ldr r3, [r3, #4] 8010514: 4a58 ldr r2, [pc, #352] @ (8010678 ) 8010516: f443 63e0 orr.w r3, r3, #1792 @ 0x700 801051a: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 801051c: 687b ldr r3, [r7, #4] 801051e: 681b ldr r3, [r3, #0] 8010520: f003 0308 and.w r3, r3, #8 8010524: 2b00 cmp r3, #0 8010526: d005 beq.n 8010534 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8010528: 4b53 ldr r3, [pc, #332] @ (8010678 ) 801052a: 685b ldr r3, [r3, #4] 801052c: 4a52 ldr r2, [pc, #328] @ (8010678 ) 801052e: f443 5360 orr.w r3, r3, #14336 @ 0x3800 8010532: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8010534: 4b50 ldr r3, [pc, #320] @ (8010678 ) 8010536: 685b ldr r3, [r3, #4] 8010538: f023 02f0 bic.w r2, r3, #240 @ 0xf0 801053c: 687b ldr r3, [r7, #4] 801053e: 689b ldr r3, [r3, #8] 8010540: 494d ldr r1, [pc, #308] @ (8010678 ) 8010542: 4313 orrs r3, r2 8010544: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8010546: 687b ldr r3, [r7, #4] 8010548: 681b ldr r3, [r3, #0] 801054a: f003 0301 and.w r3, r3, #1 801054e: 2b00 cmp r3, #0 8010550: d040 beq.n 80105d4 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8010552: 687b ldr r3, [r7, #4] 8010554: 685b ldr r3, [r3, #4] 8010556: 2b01 cmp r3, #1 8010558: d107 bne.n 801056a { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 801055a: 4b47 ldr r3, [pc, #284] @ (8010678 ) 801055c: 681b ldr r3, [r3, #0] 801055e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010562: 2b00 cmp r3, #0 8010564: d115 bne.n 8010592 { return HAL_ERROR; 8010566: 2301 movs r3, #1 8010568: e07f b.n 801066a } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 801056a: 687b ldr r3, [r7, #4] 801056c: 685b ldr r3, [r3, #4] 801056e: 2b02 cmp r3, #2 8010570: d107 bne.n 8010582 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8010572: 4b41 ldr r3, [pc, #260] @ (8010678 ) 8010574: 681b ldr r3, [r3, #0] 8010576: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 801057a: 2b00 cmp r3, #0 801057c: d109 bne.n 8010592 { return HAL_ERROR; 801057e: 2301 movs r3, #1 8010580: e073 b.n 801066a } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8010582: 4b3d ldr r3, [pc, #244] @ (8010678 ) 8010584: 681b ldr r3, [r3, #0] 8010586: f003 0302 and.w r3, r3, #2 801058a: 2b00 cmp r3, #0 801058c: d101 bne.n 8010592 { return HAL_ERROR; 801058e: 2301 movs r3, #1 8010590: e06b b.n 801066a } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8010592: 4b39 ldr r3, [pc, #228] @ (8010678 ) 8010594: 685b ldr r3, [r3, #4] 8010596: f023 0203 bic.w r2, r3, #3 801059a: 687b ldr r3, [r7, #4] 801059c: 685b ldr r3, [r3, #4] 801059e: 4936 ldr r1, [pc, #216] @ (8010678 ) 80105a0: 4313 orrs r3, r2 80105a2: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 80105a4: f7fd fb6a bl 800dc7c 80105a8: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80105aa: e00a b.n 80105c2 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80105ac: f7fd fb66 bl 800dc7c 80105b0: 4602 mov r2, r0 80105b2: 68fb ldr r3, [r7, #12] 80105b4: 1ad3 subs r3, r2, r3 80105b6: f241 3288 movw r2, #5000 @ 0x1388 80105ba: 4293 cmp r3, r2 80105bc: d901 bls.n 80105c2 { return HAL_TIMEOUT; 80105be: 2303 movs r3, #3 80105c0: e053 b.n 801066a while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80105c2: 4b2d ldr r3, [pc, #180] @ (8010678 ) 80105c4: 685b ldr r3, [r3, #4] 80105c6: f003 020c and.w r2, r3, #12 80105ca: 687b ldr r3, [r7, #4] 80105cc: 685b ldr r3, [r3, #4] 80105ce: 009b lsls r3, r3, #2 80105d0: 429a cmp r2, r3 80105d2: d1eb bne.n 80105ac } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 80105d4: 4b27 ldr r3, [pc, #156] @ (8010674 ) 80105d6: 681b ldr r3, [r3, #0] 80105d8: f003 0307 and.w r3, r3, #7 80105dc: 683a ldr r2, [r7, #0] 80105de: 429a cmp r2, r3 80105e0: d210 bcs.n 8010604 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80105e2: 4b24 ldr r3, [pc, #144] @ (8010674 ) 80105e4: 681b ldr r3, [r3, #0] 80105e6: f023 0207 bic.w r2, r3, #7 80105ea: 4922 ldr r1, [pc, #136] @ (8010674 ) 80105ec: 683b ldr r3, [r7, #0] 80105ee: 4313 orrs r3, r2 80105f0: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80105f2: 4b20 ldr r3, [pc, #128] @ (8010674 ) 80105f4: 681b ldr r3, [r3, #0] 80105f6: f003 0307 and.w r3, r3, #7 80105fa: 683a ldr r2, [r7, #0] 80105fc: 429a cmp r2, r3 80105fe: d001 beq.n 8010604 { return HAL_ERROR; 8010600: 2301 movs r3, #1 8010602: e032 b.n 801066a } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8010604: 687b ldr r3, [r7, #4] 8010606: 681b ldr r3, [r3, #0] 8010608: f003 0304 and.w r3, r3, #4 801060c: 2b00 cmp r3, #0 801060e: d008 beq.n 8010622 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8010610: 4b19 ldr r3, [pc, #100] @ (8010678 ) 8010612: 685b ldr r3, [r3, #4] 8010614: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8010618: 687b ldr r3, [r7, #4] 801061a: 68db ldr r3, [r3, #12] 801061c: 4916 ldr r1, [pc, #88] @ (8010678 ) 801061e: 4313 orrs r3, r2 8010620: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8010622: 687b ldr r3, [r7, #4] 8010624: 681b ldr r3, [r3, #0] 8010626: f003 0308 and.w r3, r3, #8 801062a: 2b00 cmp r3, #0 801062c: d009 beq.n 8010642 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 801062e: 4b12 ldr r3, [pc, #72] @ (8010678 ) 8010630: 685b ldr r3, [r3, #4] 8010632: f423 5260 bic.w r2, r3, #14336 @ 0x3800 8010636: 687b ldr r3, [r7, #4] 8010638: 691b ldr r3, [r3, #16] 801063a: 00db lsls r3, r3, #3 801063c: 490e ldr r1, [pc, #56] @ (8010678 ) 801063e: 4313 orrs r3, r2 8010640: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 8010642: f000 f821 bl 8010688 8010646: 4602 mov r2, r0 8010648: 4b0b ldr r3, [pc, #44] @ (8010678 ) 801064a: 685b ldr r3, [r3, #4] 801064c: 091b lsrs r3, r3, #4 801064e: f003 030f and.w r3, r3, #15 8010652: 490a ldr r1, [pc, #40] @ (801067c ) 8010654: 5ccb ldrb r3, [r1, r3] 8010656: fa22 f303 lsr.w r3, r2, r3 801065a: 4a09 ldr r2, [pc, #36] @ (8010680 ) 801065c: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 801065e: 4b09 ldr r3, [pc, #36] @ (8010684 ) 8010660: 681b ldr r3, [r3, #0] 8010662: 4618 mov r0, r3 8010664: f7fd fac8 bl 800dbf8 return HAL_OK; 8010668: 2300 movs r3, #0 } 801066a: 4618 mov r0, r3 801066c: 3710 adds r7, #16 801066e: 46bd mov sp, r7 8010670: bd80 pop {r7, pc} 8010672: bf00 nop 8010674: 40022000 .word 0x40022000 8010678: 40021000 .word 0x40021000 801067c: 08016384 .word 0x08016384 8010680: 20000080 .word 0x20000080 8010684: 20000084 .word 0x20000084 08010688 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8010688: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 801068c: b08e sub sp, #56 @ 0x38 801068e: af00 add r7, sp, #0 #else static const uint8_t aPredivFactorTable[2U] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8010690: 2300 movs r3, #0 8010692: 62fb str r3, [r7, #44] @ 0x2c 8010694: 2300 movs r3, #0 8010696: 62bb str r3, [r7, #40] @ 0x28 8010698: 2300 movs r3, #0 801069a: 637b str r3, [r7, #52] @ 0x34 801069c: 2300 movs r3, #0 801069e: 627b str r3, [r7, #36] @ 0x24 uint32_t sysclockfreq = 0U; 80106a0: 2300 movs r3, #0 80106a2: 633b str r3, [r7, #48] @ 0x30 #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; 80106a4: 2300 movs r3, #0 80106a6: 623b str r3, [r7, #32] 80106a8: 2300 movs r3, #0 80106aa: 61fb str r3, [r7, #28] #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 80106ac: 4b4e ldr r3, [pc, #312] @ (80107e8 ) 80106ae: 685b ldr r3, [r3, #4] 80106b0: 62fb str r3, [r7, #44] @ 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 80106b2: 6afb ldr r3, [r7, #44] @ 0x2c 80106b4: f003 030c and.w r3, r3, #12 80106b8: 2b04 cmp r3, #4 80106ba: d002 beq.n 80106c2 80106bc: 2b08 cmp r3, #8 80106be: d003 beq.n 80106c8 80106c0: e089 b.n 80107d6 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 80106c2: 4b4a ldr r3, [pc, #296] @ (80107ec ) 80106c4: 633b str r3, [r7, #48] @ 0x30 break; 80106c6: e089 b.n 80107dc } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 80106c8: 6afb ldr r3, [r7, #44] @ 0x2c 80106ca: 0c9b lsrs r3, r3, #18 80106cc: f003 020f and.w r2, r3, #15 80106d0: 4b47 ldr r3, [pc, #284] @ (80107f0 ) 80106d2: 5c9b ldrb r3, [r3, r2] 80106d4: 627b str r3, [r7, #36] @ 0x24 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 80106d6: 6afb ldr r3, [r7, #44] @ 0x2c 80106d8: f403 3380 and.w r3, r3, #65536 @ 0x10000 80106dc: 2b00 cmp r3, #0 80106de: d072 beq.n 80107c6 { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 80106e0: 4b41 ldr r3, [pc, #260] @ (80107e8 ) 80106e2: 6adb ldr r3, [r3, #44] @ 0x2c 80106e4: f003 020f and.w r2, r3, #15 80106e8: 4b42 ldr r3, [pc, #264] @ (80107f4 ) 80106ea: 5c9b ldrb r3, [r3, r2] 80106ec: 62bb str r3, [r7, #40] @ 0x28 #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /*RCC_CFGR2_PREDIV1*/ #if defined(RCC_CFGR2_PREDIV1SRC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 80106ee: 4b3e ldr r3, [pc, #248] @ (80107e8 ) 80106f0: 6adb ldr r3, [r3, #44] @ 0x2c 80106f2: f403 3380 and.w r3, r3, #65536 @ 0x10000 80106f6: 2b00 cmp r3, #0 80106f8: d053 beq.n 80107a2 { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 80106fa: 4b3b ldr r3, [pc, #236] @ (80107e8 ) 80106fc: 6adb ldr r3, [r3, #44] @ 0x2c 80106fe: 091b lsrs r3, r3, #4 8010700: f003 030f and.w r3, r3, #15 8010704: 3301 adds r3, #1 8010706: 623b str r3, [r7, #32] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 8010708: 4b37 ldr r3, [pc, #220] @ (80107e8 ) 801070a: 6adb ldr r3, [r3, #44] @ 0x2c 801070c: 0a1b lsrs r3, r3, #8 801070e: f003 030f and.w r3, r3, #15 8010712: 3302 adds r3, #2 8010714: 61fb str r3, [r7, #28] pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); 8010716: 69fb ldr r3, [r7, #28] 8010718: 2200 movs r2, #0 801071a: 469a mov sl, r3 801071c: 4693 mov fp, r2 801071e: 6a7b ldr r3, [r7, #36] @ 0x24 8010720: 2200 movs r2, #0 8010722: 613b str r3, [r7, #16] 8010724: 617a str r2, [r7, #20] 8010726: 693b ldr r3, [r7, #16] 8010728: fb03 f20b mul.w r2, r3, fp 801072c: 697b ldr r3, [r7, #20] 801072e: fb0a f303 mul.w r3, sl, r3 8010732: 4413 add r3, r2 8010734: 693a ldr r2, [r7, #16] 8010736: fbaa 0102 umull r0, r1, sl, r2 801073a: 440b add r3, r1 801073c: 4619 mov r1, r3 801073e: 4b2b ldr r3, [pc, #172] @ (80107ec ) 8010740: fb03 f201 mul.w r2, r3, r1 8010744: 2300 movs r3, #0 8010746: fb00 f303 mul.w r3, r0, r3 801074a: 4413 add r3, r2 801074c: 4a27 ldr r2, [pc, #156] @ (80107ec ) 801074e: fba0 4502 umull r4, r5, r0, r2 8010752: 442b add r3, r5 8010754: 461d mov r5, r3 8010756: 6a3b ldr r3, [r7, #32] 8010758: 2200 movs r2, #0 801075a: 60bb str r3, [r7, #8] 801075c: 60fa str r2, [r7, #12] 801075e: 6abb ldr r3, [r7, #40] @ 0x28 8010760: 2200 movs r2, #0 8010762: 603b str r3, [r7, #0] 8010764: 607a str r2, [r7, #4] 8010766: e9d7 0102 ldrd r0, r1, [r7, #8] 801076a: 460b mov r3, r1 801076c: e9d7 ab00 ldrd sl, fp, [r7] 8010770: 4652 mov r2, sl 8010772: fb02 f203 mul.w r2, r2, r3 8010776: 465b mov r3, fp 8010778: 4684 mov ip, r0 801077a: fb0c f303 mul.w r3, ip, r3 801077e: 4413 add r3, r2 8010780: 4602 mov r2, r0 8010782: 4651 mov r1, sl 8010784: fba2 8901 umull r8, r9, r2, r1 8010788: 444b add r3, r9 801078a: 4699 mov r9, r3 801078c: 4642 mov r2, r8 801078e: 464b mov r3, r9 8010790: 4620 mov r0, r4 8010792: 4629 mov r1, r5 8010794: f7f8 fd2e bl 80091f4 <__aeabi_uldivmod> 8010798: 4602 mov r2, r0 801079a: 460b mov r3, r1 801079c: 4613 mov r3, r2 801079e: 637b str r3, [r7, #52] @ 0x34 80107a0: e007 b.n 80107b2 } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 80107a2: 6a7b ldr r3, [r7, #36] @ 0x24 80107a4: 4a11 ldr r2, [pc, #68] @ (80107ec ) 80107a6: fb03 f202 mul.w r2, r3, r2 80107aa: 6abb ldr r3, [r7, #40] @ 0x28 80107ac: fbb2 f3f3 udiv r3, r2, r3 80107b0: 637b str r3, [r7, #52] @ 0x34 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 80107b2: 4b0f ldr r3, [pc, #60] @ (80107f0 ) 80107b4: 7b5b ldrb r3, [r3, #13] 80107b6: 461a mov r2, r3 80107b8: 6a7b ldr r3, [r7, #36] @ 0x24 80107ba: 4293 cmp r3, r2 80107bc: d108 bne.n 80107d0 { pllclk = pllclk / 2; 80107be: 6b7b ldr r3, [r7, #52] @ 0x34 80107c0: 085b lsrs r3, r3, #1 80107c2: 637b str r3, [r7, #52] @ 0x34 80107c4: e004 b.n 80107d0 #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 80107c6: 6a7b ldr r3, [r7, #36] @ 0x24 80107c8: 4a0b ldr r2, [pc, #44] @ (80107f8 ) 80107ca: fb02 f303 mul.w r3, r2, r3 80107ce: 637b str r3, [r7, #52] @ 0x34 } sysclockfreq = pllclk; 80107d0: 6b7b ldr r3, [r7, #52] @ 0x34 80107d2: 633b str r3, [r7, #48] @ 0x30 break; 80107d4: e002 b.n 80107dc } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 80107d6: 4b09 ldr r3, [pc, #36] @ (80107fc ) 80107d8: 633b str r3, [r7, #48] @ 0x30 break; 80107da: bf00 nop } } return sysclockfreq; 80107dc: 6b3b ldr r3, [r7, #48] @ 0x30 } 80107de: 4618 mov r0, r3 80107e0: 3738 adds r7, #56 @ 0x38 80107e2: 46bd mov sp, r7 80107e4: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 80107e8: 40021000 .word 0x40021000 80107ec: 017d7840 .word 0x017d7840 80107f0: 0801639c .word 0x0801639c 80107f4: 080163ac .word 0x080163ac 80107f8: 003d0900 .word 0x003d0900 80107fc: 007a1200 .word 0x007a1200 08010800 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8010800: b480 push {r7} 8010802: af00 add r7, sp, #0 return SystemCoreClock; 8010804: 4b02 ldr r3, [pc, #8] @ (8010810 ) 8010806: 681b ldr r3, [r3, #0] } 8010808: 4618 mov r0, r3 801080a: 46bd mov sp, r7 801080c: bc80 pop {r7} 801080e: 4770 bx lr 8010810: 20000080 .word 0x20000080 08010814 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8010814: b580 push {r7, lr} 8010816: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8010818: f7ff fff2 bl 8010800 801081c: 4602 mov r2, r0 801081e: 4b05 ldr r3, [pc, #20] @ (8010834 ) 8010820: 685b ldr r3, [r3, #4] 8010822: 0a1b lsrs r3, r3, #8 8010824: f003 0307 and.w r3, r3, #7 8010828: 4903 ldr r1, [pc, #12] @ (8010838 ) 801082a: 5ccb ldrb r3, [r1, r3] 801082c: fa22 f303 lsr.w r3, r2, r3 } 8010830: 4618 mov r0, r3 8010832: bd80 pop {r7, pc} 8010834: 40021000 .word 0x40021000 8010838: 08016394 .word 0x08016394 0801083c : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 801083c: b580 push {r7, lr} 801083e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8010840: f7ff ffde bl 8010800 8010844: 4602 mov r2, r0 8010846: 4b05 ldr r3, [pc, #20] @ (801085c ) 8010848: 685b ldr r3, [r3, #4] 801084a: 0adb lsrs r3, r3, #11 801084c: f003 0307 and.w r3, r3, #7 8010850: 4903 ldr r1, [pc, #12] @ (8010860 ) 8010852: 5ccb ldrb r3, [r1, r3] 8010854: fa22 f303 lsr.w r3, r2, r3 } 8010858: 4618 mov r0, r3 801085a: bd80 pop {r7, pc} 801085c: 40021000 .word 0x40021000 8010860: 08016394 .word 0x08016394 08010864 : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 8010864: b480 push {r7} 8010866: b085 sub sp, #20 8010868: af00 add r7, sp, #0 801086a: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 801086c: 4b0a ldr r3, [pc, #40] @ (8010898 ) 801086e: 681b ldr r3, [r3, #0] 8010870: 4a0a ldr r2, [pc, #40] @ (801089c ) 8010872: fba2 2303 umull r2, r3, r2, r3 8010876: 0a5b lsrs r3, r3, #9 8010878: 687a ldr r2, [r7, #4] 801087a: fb02 f303 mul.w r3, r2, r3 801087e: 60fb str r3, [r7, #12] do { __NOP(); 8010880: bf00 nop } while (Delay --); 8010882: 68fb ldr r3, [r7, #12] 8010884: 1e5a subs r2, r3, #1 8010886: 60fa str r2, [r7, #12] 8010888: 2b00 cmp r3, #0 801088a: d1f9 bne.n 8010880 } 801088c: bf00 nop 801088e: bf00 nop 8010890: 3714 adds r7, #20 8010892: 46bd mov sp, r7 8010894: bc80 pop {r7} 8010896: 4770 bx lr 8010898: 20000080 .word 0x20000080 801089c: 10624dd3 .word 0x10624dd3 080108a0 : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 80108a0: b580 push {r7, lr} 80108a2: b088 sub sp, #32 80108a4: af00 add r7, sp, #0 80108a6: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 80108a8: 2300 movs r3, #0 80108aa: 617b str r3, [r7, #20] 80108ac: 2300 movs r3, #0 80108ae: 613b str r3, [r7, #16] #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t pllactive = 0U; 80108b0: 2300 movs r3, #0 80108b2: 61fb str r3, [r7, #28] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 80108b4: 687b ldr r3, [r7, #4] 80108b6: 681b ldr r3, [r3, #0] 80108b8: f003 0301 and.w r3, r3, #1 80108bc: 2b00 cmp r3, #0 80108be: d07d beq.n 80109bc { FlagStatus pwrclkchanged = RESET; 80108c0: 2300 movs r3, #0 80108c2: 76fb strb r3, [r7, #27] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80108c4: 4b8b ldr r3, [pc, #556] @ (8010af4 ) 80108c6: 69db ldr r3, [r3, #28] 80108c8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80108cc: 2b00 cmp r3, #0 80108ce: d10d bne.n 80108ec { __HAL_RCC_PWR_CLK_ENABLE(); 80108d0: 4b88 ldr r3, [pc, #544] @ (8010af4 ) 80108d2: 69db ldr r3, [r3, #28] 80108d4: 4a87 ldr r2, [pc, #540] @ (8010af4 ) 80108d6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80108da: 61d3 str r3, [r2, #28] 80108dc: 4b85 ldr r3, [pc, #532] @ (8010af4 ) 80108de: 69db ldr r3, [r3, #28] 80108e0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80108e4: 60fb str r3, [r7, #12] 80108e6: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 80108e8: 2301 movs r3, #1 80108ea: 76fb strb r3, [r7, #27] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80108ec: 4b82 ldr r3, [pc, #520] @ (8010af8 ) 80108ee: 681b ldr r3, [r3, #0] 80108f0: f403 7380 and.w r3, r3, #256 @ 0x100 80108f4: 2b00 cmp r3, #0 80108f6: d118 bne.n 801092a { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 80108f8: 4b7f ldr r3, [pc, #508] @ (8010af8 ) 80108fa: 681b ldr r3, [r3, #0] 80108fc: 4a7e ldr r2, [pc, #504] @ (8010af8 ) 80108fe: f443 7380 orr.w r3, r3, #256 @ 0x100 8010902: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8010904: f7fd f9ba bl 800dc7c 8010908: 6178 str r0, [r7, #20] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 801090a: e008 b.n 801091e { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 801090c: f7fd f9b6 bl 800dc7c 8010910: 4602 mov r2, r0 8010912: 697b ldr r3, [r7, #20] 8010914: 1ad3 subs r3, r2, r3 8010916: 2b64 cmp r3, #100 @ 0x64 8010918: d901 bls.n 801091e { return HAL_TIMEOUT; 801091a: 2303 movs r3, #3 801091c: e0e5 b.n 8010aea while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 801091e: 4b76 ldr r3, [pc, #472] @ (8010af8 ) 8010920: 681b ldr r3, [r3, #0] 8010922: f403 7380 and.w r3, r3, #256 @ 0x100 8010926: 2b00 cmp r3, #0 8010928: d0f0 beq.n 801090c } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 801092a: 4b72 ldr r3, [pc, #456] @ (8010af4 ) 801092c: 6a1b ldr r3, [r3, #32] 801092e: f403 7340 and.w r3, r3, #768 @ 0x300 8010932: 613b str r3, [r7, #16] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8010934: 693b ldr r3, [r7, #16] 8010936: 2b00 cmp r3, #0 8010938: d02e beq.n 8010998 801093a: 687b ldr r3, [r7, #4] 801093c: 685b ldr r3, [r3, #4] 801093e: f403 7340 and.w r3, r3, #768 @ 0x300 8010942: 693a ldr r2, [r7, #16] 8010944: 429a cmp r2, r3 8010946: d027 beq.n 8010998 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8010948: 4b6a ldr r3, [pc, #424] @ (8010af4 ) 801094a: 6a1b ldr r3, [r3, #32] 801094c: f423 7340 bic.w r3, r3, #768 @ 0x300 8010950: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8010952: 4b6a ldr r3, [pc, #424] @ (8010afc ) 8010954: 2201 movs r2, #1 8010956: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8010958: 4b68 ldr r3, [pc, #416] @ (8010afc ) 801095a: 2200 movs r2, #0 801095c: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 801095e: 4a65 ldr r2, [pc, #404] @ (8010af4 ) 8010960: 693b ldr r3, [r7, #16] 8010962: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8010964: 693b ldr r3, [r7, #16] 8010966: f003 0301 and.w r3, r3, #1 801096a: 2b00 cmp r3, #0 801096c: d014 beq.n 8010998 { /* Get Start Tick */ tickstart = HAL_GetTick(); 801096e: f7fd f985 bl 800dc7c 8010972: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8010974: e00a b.n 801098c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8010976: f7fd f981 bl 800dc7c 801097a: 4602 mov r2, r0 801097c: 697b ldr r3, [r7, #20] 801097e: 1ad3 subs r3, r2, r3 8010980: f241 3288 movw r2, #5000 @ 0x1388 8010984: 4293 cmp r3, r2 8010986: d901 bls.n 801098c { return HAL_TIMEOUT; 8010988: 2303 movs r3, #3 801098a: e0ae b.n 8010aea while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 801098c: 4b59 ldr r3, [pc, #356] @ (8010af4 ) 801098e: 6a1b ldr r3, [r3, #32] 8010990: f003 0302 and.w r3, r3, #2 8010994: 2b00 cmp r3, #0 8010996: d0ee beq.n 8010976 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8010998: 4b56 ldr r3, [pc, #344] @ (8010af4 ) 801099a: 6a1b ldr r3, [r3, #32] 801099c: f423 7240 bic.w r2, r3, #768 @ 0x300 80109a0: 687b ldr r3, [r7, #4] 80109a2: 685b ldr r3, [r3, #4] 80109a4: 4953 ldr r1, [pc, #332] @ (8010af4 ) 80109a6: 4313 orrs r3, r2 80109a8: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 80109aa: 7efb ldrb r3, [r7, #27] 80109ac: 2b01 cmp r3, #1 80109ae: d105 bne.n 80109bc { __HAL_RCC_PWR_CLK_DISABLE(); 80109b0: 4b50 ldr r3, [pc, #320] @ (8010af4 ) 80109b2: 69db ldr r3, [r3, #28] 80109b4: 4a4f ldr r2, [pc, #316] @ (8010af4 ) 80109b6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80109ba: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 80109bc: 687b ldr r3, [r7, #4] 80109be: 681b ldr r3, [r3, #0] 80109c0: f003 0302 and.w r3, r3, #2 80109c4: 2b00 cmp r3, #0 80109c6: d008 beq.n 80109da { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 80109c8: 4b4a ldr r3, [pc, #296] @ (8010af4 ) 80109ca: 685b ldr r3, [r3, #4] 80109cc: f423 4240 bic.w r2, r3, #49152 @ 0xc000 80109d0: 687b ldr r3, [r7, #4] 80109d2: 689b ldr r3, [r3, #8] 80109d4: 4947 ldr r1, [pc, #284] @ (8010af4 ) 80109d6: 4313 orrs r3, r2 80109d8: 604b str r3, [r1, #4] } #if defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ I2S2 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) 80109da: 687b ldr r3, [r7, #4] 80109dc: 681b ldr r3, [r3, #0] 80109de: f003 0304 and.w r3, r3, #4 80109e2: 2b00 cmp r3, #0 80109e4: d008 beq.n 80109f8 { /* Check the parameters */ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); /* Configure the I2S2 clock source */ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); 80109e6: 4b43 ldr r3, [pc, #268] @ (8010af4 ) 80109e8: 6adb ldr r3, [r3, #44] @ 0x2c 80109ea: f423 3200 bic.w r2, r3, #131072 @ 0x20000 80109ee: 687b ldr r3, [r7, #4] 80109f0: 68db ldr r3, [r3, #12] 80109f2: 4940 ldr r1, [pc, #256] @ (8010af4 ) 80109f4: 4313 orrs r3, r2 80109f6: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ I2S3 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) 80109f8: 687b ldr r3, [r7, #4] 80109fa: 681b ldr r3, [r3, #0] 80109fc: f003 0308 and.w r3, r3, #8 8010a00: 2b00 cmp r3, #0 8010a02: d008 beq.n 8010a16 { /* Check the parameters */ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); /* Configure the I2S3 clock source */ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); 8010a04: 4b3b ldr r3, [pc, #236] @ (8010af4 ) 8010a06: 6adb ldr r3, [r3, #44] @ 0x2c 8010a08: f423 2280 bic.w r2, r3, #262144 @ 0x40000 8010a0c: 687b ldr r3, [r7, #4] 8010a0e: 691b ldr r3, [r3, #16] 8010a10: 4938 ldr r1, [pc, #224] @ (8010af4 ) 8010a12: 4313 orrs r3, r2 8010a14: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ PLL I2S Configuration ----------------------*/ /* Check that PLLI2S need to be enabled */ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) 8010a16: 4b37 ldr r3, [pc, #220] @ (8010af4 ) 8010a18: 6adb ldr r3, [r3, #44] @ 0x2c 8010a1a: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010a1e: 2b00 cmp r3, #0 8010a20: d105 bne.n 8010a2e 8010a22: 4b34 ldr r3, [pc, #208] @ (8010af4 ) 8010a24: 6adb ldr r3, [r3, #44] @ 0x2c 8010a26: f403 2380 and.w r3, r3, #262144 @ 0x40000 8010a2a: 2b00 cmp r3, #0 8010a2c: d001 beq.n 8010a32 { /* Update flag to indicate that PLL I2S should be active */ pllactive = 1; 8010a2e: 2301 movs r3, #1 8010a30: 61fb str r3, [r7, #28] } /* Check if PLL I2S need to be enabled */ if (pllactive == 1) 8010a32: 69fb ldr r3, [r7, #28] 8010a34: 2b01 cmp r3, #1 8010a36: d148 bne.n 8010aca { /* Enable PLL I2S only if not active */ if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) 8010a38: 4b2e ldr r3, [pc, #184] @ (8010af4 ) 8010a3a: 681b ldr r3, [r3, #0] 8010a3c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010a40: 2b00 cmp r3, #0 8010a42: d138 bne.n 8010ab6 assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); /* Prediv2 can be written only when the PLL2 is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 8010a44: 4b2b ldr r3, [pc, #172] @ (8010af4 ) 8010a46: 681b ldr r3, [r3, #0] 8010a48: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8010a4c: 2b00 cmp r3, #0 8010a4e: d009 beq.n 8010a64 (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) 8010a50: 4b28 ldr r3, [pc, #160] @ (8010af4 ) 8010a52: 6adb ldr r3, [r3, #44] @ 0x2c 8010a54: f003 02f0 and.w r2, r3, #240 @ 0xf0 8010a58: 687b ldr r3, [r7, #4] 8010a5a: 699b ldr r3, [r3, #24] if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 8010a5c: 429a cmp r2, r3 8010a5e: d001 beq.n 8010a64 { return HAL_ERROR; 8010a60: 2301 movs r3, #1 8010a62: e042 b.n 8010aea } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); 8010a64: 4b23 ldr r3, [pc, #140] @ (8010af4 ) 8010a66: 6adb ldr r3, [r3, #44] @ 0x2c 8010a68: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8010a6c: 687b ldr r3, [r7, #4] 8010a6e: 699b ldr r3, [r3, #24] 8010a70: 4920 ldr r1, [pc, #128] @ (8010af4 ) 8010a72: 4313 orrs r3, r2 8010a74: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); 8010a76: 4b1f ldr r3, [pc, #124] @ (8010af4 ) 8010a78: 6adb ldr r3, [r3, #44] @ 0x2c 8010a7a: f423 4270 bic.w r2, r3, #61440 @ 0xf000 8010a7e: 687b ldr r3, [r7, #4] 8010a80: 695b ldr r3, [r3, #20] 8010a82: 491c ldr r1, [pc, #112] @ (8010af4 ) 8010a84: 4313 orrs r3, r2 8010a86: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); 8010a88: 4b1d ldr r3, [pc, #116] @ (8010b00 ) 8010a8a: 2201 movs r2, #1 8010a8c: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8010a8e: f7fd f8f5 bl 800dc7c 8010a92: 6178 str r0, [r7, #20] /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8010a94: e008 b.n 8010aa8 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8010a96: f7fd f8f1 bl 800dc7c 8010a9a: 4602 mov r2, r0 8010a9c: 697b ldr r3, [r7, #20] 8010a9e: 1ad3 subs r3, r2, r3 8010aa0: 2b64 cmp r3, #100 @ 0x64 8010aa2: d901 bls.n 8010aa8 { return HAL_TIMEOUT; 8010aa4: 2303 movs r3, #3 8010aa6: e020 b.n 8010aea while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8010aa8: 4b12 ldr r3, [pc, #72] @ (8010af4 ) 8010aaa: 681b ldr r3, [r3, #0] 8010aac: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8010ab0: 2b00 cmp r3, #0 8010ab2: d0f0 beq.n 8010a96 8010ab4: e009 b.n 8010aca } } else { /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) 8010ab6: 4b0f ldr r3, [pc, #60] @ (8010af4 ) 8010ab8: 6adb ldr r3, [r3, #44] @ 0x2c 8010aba: f403 4270 and.w r2, r3, #61440 @ 0xf000 8010abe: 687b ldr r3, [r7, #4] 8010ac0: 695b ldr r3, [r3, #20] 8010ac2: 429a cmp r2, r3 8010ac4: d001 beq.n 8010aca { return HAL_ERROR; 8010ac6: 2301 movs r3, #1 8010ac8: e00f b.n 8010aea #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8010aca: 687b ldr r3, [r7, #4] 8010acc: 681b ldr r3, [r3, #0] 8010ace: f003 0310 and.w r3, r3, #16 8010ad2: 2b00 cmp r3, #0 8010ad4: d008 beq.n 8010ae8 { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8010ad6: 4b07 ldr r3, [pc, #28] @ (8010af4 ) 8010ad8: 685b ldr r3, [r3, #4] 8010ada: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 8010ade: 687b ldr r3, [r7, #4] 8010ae0: 69db ldr r3, [r3, #28] 8010ae2: 4904 ldr r1, [pc, #16] @ (8010af4 ) 8010ae4: 4313 orrs r3, r2 8010ae6: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 8010ae8: 2300 movs r3, #0 } 8010aea: 4618 mov r0, r3 8010aec: 3720 adds r7, #32 8010aee: 46bd mov sp, r7 8010af0: bd80 pop {r7, pc} 8010af2: bf00 nop 8010af4: 40021000 .word 0x40021000 8010af8: 40007000 .word 0x40007000 8010afc: 42420440 .word 0x42420440 8010b00: 42420070 .word 0x42420070 08010b04 : * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 8010b04: b580 push {r7, lr} 8010b06: b08a sub sp, #40 @ 0x28 8010b08: af00 add r7, sp, #0 8010b0a: 6078 str r0, [r7, #4] #if defined(STM32F105xC) || defined(STM32F107xC) static const uint8_t aPLLMULFactorTable[14U] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; 8010b0c: 2300 movs r3, #0 8010b0e: 61fb str r3, [r7, #28] 8010b10: 2300 movs r3, #0 8010b12: 627b str r3, [r7, #36] @ 0x24 8010b14: 2300 movs r3, #0 8010b16: 61bb str r3, [r7, #24] uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; 8010b18: 2300 movs r3, #0 8010b1a: 617b str r3, [r7, #20] 8010b1c: 2300 movs r3, #0 8010b1e: 613b str r3, [r7, #16] 8010b20: 2300 movs r3, #0 8010b22: 60fb str r3, [r7, #12] static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; static const uint8_t aPredivFactorTable[2U] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 8010b24: 2300 movs r3, #0 8010b26: 60bb str r3, [r7, #8] 8010b28: 2300 movs r3, #0 8010b2a: 623b str r3, [r7, #32] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 8010b2c: 687b ldr r3, [r7, #4] 8010b2e: 3b01 subs r3, #1 8010b30: 2b0f cmp r3, #15 8010b32: f200 811d bhi.w 8010d70 8010b36: a201 add r2, pc, #4 @ (adr r2, 8010b3c ) 8010b38: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8010b3c: 08010cf1 .word 0x08010cf1 8010b40: 08010d55 .word 0x08010d55 8010b44: 08010d71 .word 0x08010d71 8010b48: 08010c4f .word 0x08010c4f 8010b4c: 08010d71 .word 0x08010d71 8010b50: 08010d71 .word 0x08010d71 8010b54: 08010d71 .word 0x08010d71 8010b58: 08010ca1 .word 0x08010ca1 8010b5c: 08010d71 .word 0x08010d71 8010b60: 08010d71 .word 0x08010d71 8010b64: 08010d71 .word 0x08010d71 8010b68: 08010d71 .word 0x08010d71 8010b6c: 08010d71 .word 0x08010d71 8010b70: 08010d71 .word 0x08010d71 8010b74: 08010d71 .word 0x08010d71 8010b78: 08010b7d .word 0x08010b7d || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) case RCC_PERIPHCLK_USB: { /* Get RCC configuration ------------------------------------------------------*/ temp_reg = RCC->CFGR; 8010b7c: 4b83 ldr r3, [pc, #524] @ (8010d8c ) 8010b7e: 685b ldr r3, [r3, #4] 8010b80: 60bb str r3, [r7, #8] /* Check if PLL is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) 8010b82: 4b82 ldr r3, [pc, #520] @ (8010d8c ) 8010b84: 681b ldr r3, [r3, #0] 8010b86: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8010b8a: 2b00 cmp r3, #0 8010b8c: f000 80f2 beq.w 8010d74 { pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8010b90: 68bb ldr r3, [r7, #8] 8010b92: 0c9b lsrs r3, r3, #18 8010b94: f003 030f and.w r3, r3, #15 8010b98: 4a7d ldr r2, [pc, #500] @ (8010d90 ) 8010b9a: 5cd3 ldrb r3, [r2, r3] 8010b9c: 61bb str r3, [r7, #24] if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8010b9e: 68bb ldr r3, [r7, #8] 8010ba0: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010ba4: 2b00 cmp r3, #0 8010ba6: d03b beq.n 8010c20 { #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ || defined(STM32F100xE) prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 8010ba8: 4b78 ldr r3, [pc, #480] @ (8010d8c ) 8010baa: 6adb ldr r3, [r3, #44] @ 0x2c 8010bac: f003 030f and.w r3, r3, #15 8010bb0: 4a78 ldr r2, [pc, #480] @ (8010d94 ) 8010bb2: 5cd3 ldrb r3, [r2, r3] 8010bb4: 61fb str r3, [r7, #28] #else prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 8010bb6: 4b75 ldr r3, [pc, #468] @ (8010d8c ) 8010bb8: 6adb ldr r3, [r3, #44] @ 0x2c 8010bba: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010bbe: 2b00 cmp r3, #0 8010bc0: d01c beq.n 8010bfc { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8010bc2: 4b72 ldr r3, [pc, #456] @ (8010d8c ) 8010bc4: 6adb ldr r3, [r3, #44] @ 0x2c 8010bc6: 091b lsrs r3, r3, #4 8010bc8: f003 030f and.w r3, r3, #15 8010bcc: 3301 adds r3, #1 8010bce: 60fb str r3, [r7, #12] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 8010bd0: 4b6e ldr r3, [pc, #440] @ (8010d8c ) 8010bd2: 6adb ldr r3, [r3, #44] @ 0x2c 8010bd4: 0a1b lsrs r3, r3, #8 8010bd6: f003 030f and.w r3, r3, #15 8010bda: 3302 adds r3, #2 8010bdc: 617b str r3, [r7, #20] pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); 8010bde: 4a6e ldr r2, [pc, #440] @ (8010d98 ) 8010be0: 68fb ldr r3, [r7, #12] 8010be2: fbb2 f3f3 udiv r3, r2, r3 8010be6: 697a ldr r2, [r7, #20] 8010be8: fb03 f202 mul.w r2, r3, r2 8010bec: 69fb ldr r3, [r7, #28] 8010bee: fbb2 f2f3 udiv r2, r2, r3 8010bf2: 69bb ldr r3, [r7, #24] 8010bf4: fb02 f303 mul.w r3, r2, r3 8010bf8: 627b str r3, [r7, #36] @ 0x24 8010bfa: e007 b.n 8010c0c } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); 8010bfc: 4a66 ldr r2, [pc, #408] @ (8010d98 ) 8010bfe: 69fb ldr r3, [r7, #28] 8010c00: fbb2 f2f3 udiv r2, r2, r3 8010c04: 69bb ldr r3, [r7, #24] 8010c06: fb02 f303 mul.w r3, r2, r3 8010c0a: 627b str r3, [r7, #36] @ 0x24 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 8010c0c: 4b60 ldr r3, [pc, #384] @ (8010d90 ) 8010c0e: 7b5b ldrb r3, [r3, #13] 8010c10: 461a mov r2, r3 8010c12: 69bb ldr r3, [r7, #24] 8010c14: 4293 cmp r3, r2 8010c16: d108 bne.n 8010c2a { pllclk = pllclk / 2; 8010c18: 6a7b ldr r3, [r7, #36] @ 0x24 8010c1a: 085b lsrs r3, r3, #1 8010c1c: 627b str r3, [r7, #36] @ 0x24 8010c1e: e004 b.n 8010c2a #endif /* STM32F105xC || STM32F107xC */ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8010c20: 69bb ldr r3, [r7, #24] 8010c22: 4a5e ldr r2, [pc, #376] @ (8010d9c ) 8010c24: fb02 f303 mul.w r3, r2, r3 8010c28: 627b str r3, [r7, #36] @ 0x24 } /* Calcul of the USB frequency*/ #if defined(STM32F105xC) || defined(STM32F107xC) /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) 8010c2a: 4b58 ldr r3, [pc, #352] @ (8010d8c ) 8010c2c: 685b ldr r3, [r3, #4] 8010c2e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8010c32: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8010c36: d102 bne.n 8010c3e { /* Prescaler of 2 selected for USB */ frequency = pllclk; 8010c38: 6a7b ldr r3, [r7, #36] @ 0x24 8010c3a: 623b str r3, [r7, #32] /* Prescaler of 1.5 selected for USB */ frequency = (pllclk * 2) / 3; } #endif } break; 8010c3c: e09a b.n 8010d74 frequency = (2 * pllclk) / 3; 8010c3e: 6a7b ldr r3, [r7, #36] @ 0x24 8010c40: 005b lsls r3, r3, #1 8010c42: 4a57 ldr r2, [pc, #348] @ (8010da0 ) 8010c44: fba2 2303 umull r2, r3, r2, r3 8010c48: 085b lsrs r3, r3, #1 8010c4a: 623b str r3, [r7, #32] break; 8010c4c: e092 b.n 8010d74 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) 8010c4e: 4b4f ldr r3, [pc, #316] @ (8010d8c ) 8010c50: 6adb ldr r3, [r3, #44] @ 0x2c 8010c52: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010c56: 2b00 cmp r3, #0 8010c58: d103 bne.n 8010c62 { /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); 8010c5a: f7ff fd15 bl 8010688 8010c5e: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 8010c60: e08a b.n 8010d78 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8010c62: 4b4a ldr r3, [pc, #296] @ (8010d8c ) 8010c64: 681b ldr r3, [r3, #0] 8010c66: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010c6a: 2b00 cmp r3, #0 8010c6c: f000 8084 beq.w 8010d78 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8010c70: 4b46 ldr r3, [pc, #280] @ (8010d8c ) 8010c72: 6adb ldr r3, [r3, #44] @ 0x2c 8010c74: 091b lsrs r3, r3, #4 8010c76: f003 030f and.w r3, r3, #15 8010c7a: 3301 adds r3, #1 8010c7c: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 8010c7e: 4b43 ldr r3, [pc, #268] @ (8010d8c ) 8010c80: 6adb ldr r3, [r3, #44] @ 0x2c 8010c82: 0b1b lsrs r3, r3, #12 8010c84: f003 030f and.w r3, r3, #15 8010c88: 3302 adds r3, #2 8010c8a: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 8010c8c: 4a42 ldr r2, [pc, #264] @ (8010d98 ) 8010c8e: 68fb ldr r3, [r7, #12] 8010c90: fbb2 f3f3 udiv r3, r2, r3 8010c94: 693a ldr r2, [r7, #16] 8010c96: fb02 f303 mul.w r3, r2, r3 8010c9a: 005b lsls r3, r3, #1 8010c9c: 623b str r3, [r7, #32] break; 8010c9e: e06b b.n 8010d78 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) 8010ca0: 4b3a ldr r3, [pc, #232] @ (8010d8c ) 8010ca2: 6adb ldr r3, [r3, #44] @ 0x2c 8010ca4: f403 2380 and.w r3, r3, #262144 @ 0x40000 8010ca8: 2b00 cmp r3, #0 8010caa: d103 bne.n 8010cb4 { /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); 8010cac: f7ff fcec bl 8010688 8010cb0: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 8010cb2: e063 b.n 8010d7c if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8010cb4: 4b35 ldr r3, [pc, #212] @ (8010d8c ) 8010cb6: 681b ldr r3, [r3, #0] 8010cb8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010cbc: 2b00 cmp r3, #0 8010cbe: d05d beq.n 8010d7c prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8010cc0: 4b32 ldr r3, [pc, #200] @ (8010d8c ) 8010cc2: 6adb ldr r3, [r3, #44] @ 0x2c 8010cc4: 091b lsrs r3, r3, #4 8010cc6: f003 030f and.w r3, r3, #15 8010cca: 3301 adds r3, #1 8010ccc: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 8010cce: 4b2f ldr r3, [pc, #188] @ (8010d8c ) 8010cd0: 6adb ldr r3, [r3, #44] @ 0x2c 8010cd2: 0b1b lsrs r3, r3, #12 8010cd4: f003 030f and.w r3, r3, #15 8010cd8: 3302 adds r3, #2 8010cda: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 8010cdc: 4a2e ldr r2, [pc, #184] @ (8010d98 ) 8010cde: 68fb ldr r3, [r7, #12] 8010ce0: fbb2 f3f3 udiv r3, r2, r3 8010ce4: 693a ldr r2, [r7, #16] 8010ce6: fb02 f303 mul.w r3, r2, r3 8010cea: 005b lsls r3, r3, #1 8010cec: 623b str r3, [r7, #32] break; 8010cee: e045 b.n 8010d7c } #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ case RCC_PERIPHCLK_RTC: { /* Get RCC BDCR configuration ------------------------------------------------------*/ temp_reg = RCC->BDCR; 8010cf0: 4b26 ldr r3, [pc, #152] @ (8010d8c ) 8010cf2: 6a1b ldr r3, [r3, #32] 8010cf4: 60bb str r3, [r7, #8] /* Check if LSE is ready if RTC clock selection is LSE */ if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 8010cf6: 68bb ldr r3, [r7, #8] 8010cf8: f403 7340 and.w r3, r3, #768 @ 0x300 8010cfc: f5b3 7f80 cmp.w r3, #256 @ 0x100 8010d00: d108 bne.n 8010d14 8010d02: 68bb ldr r3, [r7, #8] 8010d04: f003 0302 and.w r3, r3, #2 8010d08: 2b00 cmp r3, #0 8010d0a: d003 beq.n 8010d14 { frequency = LSE_VALUE; 8010d0c: f44f 4300 mov.w r3, #32768 @ 0x8000 8010d10: 623b str r3, [r7, #32] 8010d12: e01e b.n 8010d52 } /* Check if LSI is ready if RTC clock selection is LSI */ else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 8010d14: 68bb ldr r3, [r7, #8] 8010d16: f403 7340 and.w r3, r3, #768 @ 0x300 8010d1a: f5b3 7f00 cmp.w r3, #512 @ 0x200 8010d1e: d109 bne.n 8010d34 8010d20: 4b1a ldr r3, [pc, #104] @ (8010d8c ) 8010d22: 6a5b ldr r3, [r3, #36] @ 0x24 8010d24: f003 0302 and.w r3, r3, #2 8010d28: 2b00 cmp r3, #0 8010d2a: d003 beq.n 8010d34 { frequency = LSI_VALUE; 8010d2c: f649 4340 movw r3, #40000 @ 0x9c40 8010d30: 623b str r3, [r7, #32] 8010d32: e00e b.n 8010d52 } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 8010d34: 68bb ldr r3, [r7, #8] 8010d36: f403 7340 and.w r3, r3, #768 @ 0x300 8010d3a: f5b3 7f40 cmp.w r3, #768 @ 0x300 8010d3e: d11f bne.n 8010d80 8010d40: 4b12 ldr r3, [pc, #72] @ (8010d8c ) 8010d42: 681b ldr r3, [r3, #0] 8010d44: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010d48: 2b00 cmp r3, #0 8010d4a: d019 beq.n 8010d80 { frequency = HSE_VALUE / 128U; 8010d4c: 4b15 ldr r3, [pc, #84] @ (8010da4 ) 8010d4e: 623b str r3, [r7, #32] /* Clock not enabled for RTC*/ else { /* nothing to do: frequency already initialized to 0U */ } break; 8010d50: e016 b.n 8010d80 8010d52: e015 b.n 8010d80 } case RCC_PERIPHCLK_ADC: { frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 8010d54: f7ff fd72 bl 801083c 8010d58: 4602 mov r2, r0 8010d5a: 4b0c ldr r3, [pc, #48] @ (8010d8c ) 8010d5c: 685b ldr r3, [r3, #4] 8010d5e: 0b9b lsrs r3, r3, #14 8010d60: f003 0303 and.w r3, r3, #3 8010d64: 3301 adds r3, #1 8010d66: 005b lsls r3, r3, #1 8010d68: fbb2 f3f3 udiv r3, r2, r3 8010d6c: 623b str r3, [r7, #32] break; 8010d6e: e008 b.n 8010d82 } default: { break; 8010d70: bf00 nop 8010d72: e006 b.n 8010d82 break; 8010d74: bf00 nop 8010d76: e004 b.n 8010d82 break; 8010d78: bf00 nop 8010d7a: e002 b.n 8010d82 break; 8010d7c: bf00 nop 8010d7e: e000 b.n 8010d82 break; 8010d80: bf00 nop } } return (frequency); 8010d82: 6a3b ldr r3, [r7, #32] } 8010d84: 4618 mov r0, r3 8010d86: 3728 adds r7, #40 @ 0x28 8010d88: 46bd mov sp, r7 8010d8a: bd80 pop {r7, pc} 8010d8c: 40021000 .word 0x40021000 8010d90: 080163bc .word 0x080163bc 8010d94: 080163cc .word 0x080163cc 8010d98: 017d7840 .word 0x017d7840 8010d9c: 003d0900 .word 0x003d0900 8010da0: aaaaaaab .word 0xaaaaaaab 8010da4: 0002faf0 .word 0x0002faf0 08010da8 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { 8010da8: b580 push {r7, lr} 8010daa: b084 sub sp, #16 8010dac: af00 add r7, sp, #0 8010dae: 6078 str r0, [r7, #4] uint32_t prescaler = 0U; 8010db0: 2300 movs r3, #0 8010db2: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8010db4: 687b ldr r3, [r7, #4] 8010db6: 2b00 cmp r3, #0 8010db8: d101 bne.n 8010dbe { return HAL_ERROR; 8010dba: 2301 movs r3, #1 8010dbc: e07a b.n 8010eb4 { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } #else if (hrtc->State == HAL_RTC_STATE_RESET) 8010dbe: 687b ldr r3, [r7, #4] 8010dc0: 7c5b ldrb r3, [r3, #17] 8010dc2: b2db uxtb r3, r3 8010dc4: 2b00 cmp r3, #0 8010dc6: d105 bne.n 8010dd4 { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; 8010dc8: 687b ldr r3, [r7, #4] 8010dca: 2200 movs r2, #0 8010dcc: 741a strb r2, [r3, #16] /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); 8010dce: 6878 ldr r0, [r7, #4] 8010dd0: f7fa fdf2 bl 800b9b8 } #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; 8010dd4: 687b ldr r3, [r7, #4] 8010dd6: 2202 movs r2, #2 8010dd8: 745a strb r2, [r3, #17] /* Waiting for synchro */ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 8010dda: 6878 ldr r0, [r7, #4] 8010ddc: f000 f870 bl 8010ec0 8010de0: 4603 mov r3, r0 8010de2: 2b00 cmp r3, #0 8010de4: d004 beq.n 8010df0 { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8010de6: 687b ldr r3, [r7, #4] 8010de8: 2204 movs r2, #4 8010dea: 745a strb r2, [r3, #17] return HAL_ERROR; 8010dec: 2301 movs r3, #1 8010dee: e061 b.n 8010eb4 } /* Set Initialization mode */ if (RTC_EnterInitMode(hrtc) != HAL_OK) 8010df0: 6878 ldr r0, [r7, #4] 8010df2: f000 f892 bl 8010f1a 8010df6: 4603 mov r3, r0 8010df8: 2b00 cmp r3, #0 8010dfa: d004 beq.n 8010e06 { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8010dfc: 687b ldr r3, [r7, #4] 8010dfe: 2204 movs r2, #4 8010e00: 745a strb r2, [r3, #17] return HAL_ERROR; 8010e02: 2301 movs r3, #1 8010e04: e056 b.n 8010eb4 } else { /* Clear Flags Bits */ CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC)); 8010e06: 687b ldr r3, [r7, #4] 8010e08: 681b ldr r3, [r3, #0] 8010e0a: 685a ldr r2, [r3, #4] 8010e0c: 687b ldr r3, [r7, #4] 8010e0e: 681b ldr r3, [r3, #0] 8010e10: f022 0207 bic.w r2, r2, #7 8010e14: 605a str r2, [r3, #4] if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE) 8010e16: 687b ldr r3, [r7, #4] 8010e18: 689b ldr r3, [r3, #8] 8010e1a: 2b00 cmp r3, #0 8010e1c: d005 beq.n 8010e2a { /* Disable the selected Tamper pin */ CLEAR_BIT(BKP->CR, BKP_CR_TPE); 8010e1e: 4b27 ldr r3, [pc, #156] @ (8010ebc ) 8010e20: 6b1b ldr r3, [r3, #48] @ 0x30 8010e22: 4a26 ldr r2, [pc, #152] @ (8010ebc ) 8010e24: f023 0301 bic.w r3, r3, #1 8010e28: 6313 str r3, [r2, #48] @ 0x30 } /* Set the signal which will be routed to RTC Tamper pin*/ MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut); 8010e2a: 4b24 ldr r3, [pc, #144] @ (8010ebc ) 8010e2c: 6adb ldr r3, [r3, #44] @ 0x2c 8010e2e: f423 7260 bic.w r2, r3, #896 @ 0x380 8010e32: 687b ldr r3, [r7, #4] 8010e34: 689b ldr r3, [r3, #8] 8010e36: 4921 ldr r1, [pc, #132] @ (8010ebc ) 8010e38: 4313 orrs r3, r2 8010e3a: 62cb str r3, [r1, #44] @ 0x2c if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND) 8010e3c: 687b ldr r3, [r7, #4] 8010e3e: 685b ldr r3, [r3, #4] 8010e40: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8010e44: d003 beq.n 8010e4e { /* RTC Prescaler provided directly by end-user*/ prescaler = hrtc->Init.AsynchPrediv; 8010e46: 687b ldr r3, [r7, #4] 8010e48: 685b ldr r3, [r3, #4] 8010e4a: 60fb str r3, [r7, #12] 8010e4c: e00e b.n 8010e6c } else { /* RTC Prescaler will be automatically calculated to get 1 second timebase */ /* Get the RTCCLK frequency */ prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); 8010e4e: 2001 movs r0, #1 8010e50: f7ff fe58 bl 8010b04 8010e54: 60f8 str r0, [r7, #12] /* Check that RTC clock is enabled*/ if (prescaler == 0U) 8010e56: 68fb ldr r3, [r7, #12] 8010e58: 2b00 cmp r3, #0 8010e5a: d104 bne.n 8010e66 { /* Should not happen. Frequency is not available*/ hrtc->State = HAL_RTC_STATE_ERROR; 8010e5c: 687b ldr r3, [r7, #4] 8010e5e: 2204 movs r2, #4 8010e60: 745a strb r2, [r3, #17] return HAL_ERROR; 8010e62: 2301 movs r3, #1 8010e64: e026 b.n 8010eb4 } else { /* RTC period = RTCCLK/(RTC_PR + 1) */ prescaler = prescaler - 1U; 8010e66: 68fb ldr r3, [r7, #12] 8010e68: 3b01 subs r3, #1 8010e6a: 60fb str r3, [r7, #12] } } /* Configure the RTC_PRLH / RTC_PRLL */ WRITE_REG(hrtc->Instance->PRLH, ((prescaler >> 16U) & RTC_PRLH_PRL)); 8010e6c: 68fb ldr r3, [r7, #12] 8010e6e: 0c1a lsrs r2, r3, #16 8010e70: 687b ldr r3, [r7, #4] 8010e72: 681b ldr r3, [r3, #0] 8010e74: f002 020f and.w r2, r2, #15 8010e78: 609a str r2, [r3, #8] WRITE_REG(hrtc->Instance->PRLL, (prescaler & RTC_PRLL_PRL)); 8010e7a: 687b ldr r3, [r7, #4] 8010e7c: 681b ldr r3, [r3, #0] 8010e7e: 68fa ldr r2, [r7, #12] 8010e80: b292 uxth r2, r2 8010e82: 60da str r2, [r3, #12] /* Wait for synchro */ if (RTC_ExitInitMode(hrtc) != HAL_OK) 8010e84: 6878 ldr r0, [r7, #4] 8010e86: f000 f870 bl 8010f6a 8010e8a: 4603 mov r3, r0 8010e8c: 2b00 cmp r3, #0 8010e8e: d004 beq.n 8010e9a { hrtc->State = HAL_RTC_STATE_ERROR; 8010e90: 687b ldr r3, [r7, #4] 8010e92: 2204 movs r2, #4 8010e94: 745a strb r2, [r3, #17] return HAL_ERROR; 8010e96: 2301 movs r3, #1 8010e98: e00c b.n 8010eb4 } /* Initialize date to 1st of January 2000 */ hrtc->DateToUpdate.Year = 0x00U; 8010e9a: 687b ldr r3, [r7, #4] 8010e9c: 2200 movs r2, #0 8010e9e: 73da strb r2, [r3, #15] hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; 8010ea0: 687b ldr r3, [r7, #4] 8010ea2: 2201 movs r2, #1 8010ea4: 735a strb r2, [r3, #13] hrtc->DateToUpdate.Date = 0x01U; 8010ea6: 687b ldr r3, [r7, #4] 8010ea8: 2201 movs r2, #1 8010eaa: 739a strb r2, [r3, #14] /* Set RTC state */ hrtc->State = HAL_RTC_STATE_READY; 8010eac: 687b ldr r3, [r7, #4] 8010eae: 2201 movs r2, #1 8010eb0: 745a strb r2, [r3, #17] return HAL_OK; 8010eb2: 2300 movs r3, #0 } } 8010eb4: 4618 mov r0, r3 8010eb6: 3710 adds r7, #16 8010eb8: 46bd mov sp, r7 8010eba: bd80 pop {r7, pc} 8010ebc: 40006c00 .word 0x40006c00 08010ec0 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { 8010ec0: b580 push {r7, lr} 8010ec2: b084 sub sp, #16 8010ec4: af00 add r7, sp, #0 8010ec6: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8010ec8: 2300 movs r3, #0 8010eca: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8010ecc: 687b ldr r3, [r7, #4] 8010ece: 2b00 cmp r3, #0 8010ed0: d101 bne.n 8010ed6 { return HAL_ERROR; 8010ed2: 2301 movs r3, #1 8010ed4: e01d b.n 8010f12 } /* Clear RSF flag */ CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); 8010ed6: 687b ldr r3, [r7, #4] 8010ed8: 681b ldr r3, [r3, #0] 8010eda: 685a ldr r2, [r3, #4] 8010edc: 687b ldr r3, [r7, #4] 8010ede: 681b ldr r3, [r3, #0] 8010ee0: f022 0208 bic.w r2, r2, #8 8010ee4: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8010ee6: f7fc fec9 bl 800dc7c 8010eea: 60f8 str r0, [r7, #12] /* Wait the registers to be synchronised */ while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8010eec: e009 b.n 8010f02 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8010eee: f7fc fec5 bl 800dc7c 8010ef2: 4602 mov r2, r0 8010ef4: 68fb ldr r3, [r7, #12] 8010ef6: 1ad3 subs r3, r2, r3 8010ef8: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8010efc: d901 bls.n 8010f02 { return HAL_TIMEOUT; 8010efe: 2303 movs r3, #3 8010f00: e007 b.n 8010f12 while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8010f02: 687b ldr r3, [r7, #4] 8010f04: 681b ldr r3, [r3, #0] 8010f06: 685b ldr r3, [r3, #4] 8010f08: f003 0308 and.w r3, r3, #8 8010f0c: 2b00 cmp r3, #0 8010f0e: d0ee beq.n 8010eee } } return HAL_OK; 8010f10: 2300 movs r3, #0 } 8010f12: 4618 mov r0, r3 8010f14: 3710 adds r7, #16 8010f16: 46bd mov sp, r7 8010f18: bd80 pop {r7, pc} 08010f1a : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { 8010f1a: b580 push {r7, lr} 8010f1c: b084 sub sp, #16 8010f1e: af00 add r7, sp, #0 8010f20: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8010f22: 2300 movs r3, #0 8010f24: 60fb str r3, [r7, #12] tickstart = HAL_GetTick(); 8010f26: f7fc fea9 bl 800dc7c 8010f2a: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8010f2c: e009 b.n 8010f42 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8010f2e: f7fc fea5 bl 800dc7c 8010f32: 4602 mov r2, r0 8010f34: 68fb ldr r3, [r7, #12] 8010f36: 1ad3 subs r3, r2, r3 8010f38: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8010f3c: d901 bls.n 8010f42 { return HAL_TIMEOUT; 8010f3e: 2303 movs r3, #3 8010f40: e00f b.n 8010f62 while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8010f42: 687b ldr r3, [r7, #4] 8010f44: 681b ldr r3, [r3, #0] 8010f46: 685b ldr r3, [r3, #4] 8010f48: f003 0320 and.w r3, r3, #32 8010f4c: 2b00 cmp r3, #0 8010f4e: d0ee beq.n 8010f2e } } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 8010f50: 687b ldr r3, [r7, #4] 8010f52: 681b ldr r3, [r3, #0] 8010f54: 685a ldr r2, [r3, #4] 8010f56: 687b ldr r3, [r7, #4] 8010f58: 681b ldr r3, [r3, #0] 8010f5a: f042 0210 orr.w r2, r2, #16 8010f5e: 605a str r2, [r3, #4] return HAL_OK; 8010f60: 2300 movs r3, #0 } 8010f62: 4618 mov r0, r3 8010f64: 3710 adds r7, #16 8010f66: 46bd mov sp, r7 8010f68: bd80 pop {r7, pc} 08010f6a : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) { 8010f6a: b580 push {r7, lr} 8010f6c: b084 sub sp, #16 8010f6e: af00 add r7, sp, #0 8010f70: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8010f72: 2300 movs r3, #0 8010f74: 60fb str r3, [r7, #12] /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 8010f76: 687b ldr r3, [r7, #4] 8010f78: 681b ldr r3, [r3, #0] 8010f7a: 685a ldr r2, [r3, #4] 8010f7c: 687b ldr r3, [r7, #4] 8010f7e: 681b ldr r3, [r3, #0] 8010f80: f022 0210 bic.w r2, r2, #16 8010f84: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8010f86: f7fc fe79 bl 800dc7c 8010f8a: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8010f8c: e009 b.n 8010fa2 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8010f8e: f7fc fe75 bl 800dc7c 8010f92: 4602 mov r2, r0 8010f94: 68fb ldr r3, [r7, #12] 8010f96: 1ad3 subs r3, r2, r3 8010f98: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8010f9c: d901 bls.n 8010fa2 { return HAL_TIMEOUT; 8010f9e: 2303 movs r3, #3 8010fa0: e007 b.n 8010fb2 while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8010fa2: 687b ldr r3, [r7, #4] 8010fa4: 681b ldr r3, [r3, #0] 8010fa6: 685b ldr r3, [r3, #4] 8010fa8: f003 0320 and.w r3, r3, #32 8010fac: 2b00 cmp r3, #0 8010fae: d0ee beq.n 8010f8e } } return HAL_OK; 8010fb0: 2300 movs r3, #0 } 8010fb2: 4618 mov r0, r3 8010fb4: 3710 adds r7, #16 8010fb6: 46bd mov sp, r7 8010fb8: bd80 pop {r7, pc} 08010fba : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8010fba: b580 push {r7, lr} 8010fbc: b082 sub sp, #8 8010fbe: af00 add r7, sp, #0 8010fc0: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8010fc2: 687b ldr r3, [r7, #4] 8010fc4: 2b00 cmp r3, #0 8010fc6: d101 bne.n 8010fcc { return HAL_ERROR; 8010fc8: 2301 movs r3, #1 8010fca: e041 b.n 8011050 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8010fcc: 687b ldr r3, [r7, #4] 8010fce: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8010fd2: b2db uxtb r3, r3 8010fd4: 2b00 cmp r3, #0 8010fd6: d106 bne.n 8010fe6 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8010fd8: 687b ldr r3, [r7, #4] 8010fda: 2200 movs r2, #0 8010fdc: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8010fe0: 6878 ldr r0, [r7, #4] 8010fe2: f7fc fb37 bl 800d654 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8010fe6: 687b ldr r3, [r7, #4] 8010fe8: 2202 movs r2, #2 8010fea: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8010fee: 687b ldr r3, [r7, #4] 8010ff0: 681a ldr r2, [r3, #0] 8010ff2: 687b ldr r3, [r7, #4] 8010ff4: 3304 adds r3, #4 8010ff6: 4619 mov r1, r3 8010ff8: 4610 mov r0, r2 8010ffa: f000 fd77 bl 8011aec /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8010ffe: 687b ldr r3, [r7, #4] 8011000: 2201 movs r2, #1 8011002: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011006: 687b ldr r3, [r7, #4] 8011008: 2201 movs r2, #1 801100a: f883 203e strb.w r2, [r3, #62] @ 0x3e 801100e: 687b ldr r3, [r7, #4] 8011010: 2201 movs r2, #1 8011012: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011016: 687b ldr r3, [r7, #4] 8011018: 2201 movs r2, #1 801101a: f883 2040 strb.w r2, [r3, #64] @ 0x40 801101e: 687b ldr r3, [r7, #4] 8011020: 2201 movs r2, #1 8011022: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011026: 687b ldr r3, [r7, #4] 8011028: 2201 movs r2, #1 801102a: f883 2042 strb.w r2, [r3, #66] @ 0x42 801102e: 687b ldr r3, [r7, #4] 8011030: 2201 movs r2, #1 8011032: f883 2043 strb.w r2, [r3, #67] @ 0x43 8011036: 687b ldr r3, [r7, #4] 8011038: 2201 movs r2, #1 801103a: f883 2044 strb.w r2, [r3, #68] @ 0x44 801103e: 687b ldr r3, [r7, #4] 8011040: 2201 movs r2, #1 8011042: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8011046: 687b ldr r3, [r7, #4] 8011048: 2201 movs r2, #1 801104a: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 801104e: 2300 movs r3, #0 } 8011050: 4618 mov r0, r3 8011052: 3708 adds r7, #8 8011054: 46bd mov sp, r7 8011056: bd80 pop {r7, pc} 08011058 : * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { 8011058: b580 push {r7, lr} 801105a: b082 sub sp, #8 801105c: af00 add r7, sp, #0 801105e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8011060: 687b ldr r3, [r7, #4] 8011062: 2b00 cmp r3, #0 8011064: d101 bne.n 801106a { return HAL_ERROR; 8011066: 2301 movs r3, #1 8011068: e041 b.n 80110ee assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 801106a: 687b ldr r3, [r7, #4] 801106c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8011070: b2db uxtb r3, r3 8011072: 2b00 cmp r3, #0 8011074: d106 bne.n 8011084 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8011076: 687b ldr r3, [r7, #4] 8011078: 2200 movs r2, #0 801107a: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); 801107e: 6878 ldr r0, [r7, #4] 8011080: f000 f839 bl 80110f6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8011084: 687b ldr r3, [r7, #4] 8011086: 2202 movs r2, #2 8011088: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 801108c: 687b ldr r3, [r7, #4] 801108e: 681a ldr r2, [r3, #0] 8011090: 687b ldr r3, [r7, #4] 8011092: 3304 adds r3, #4 8011094: 4619 mov r1, r3 8011096: 4610 mov r0, r2 8011098: f000 fd28 bl 8011aec /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 801109c: 687b ldr r3, [r7, #4] 801109e: 2201 movs r2, #1 80110a0: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80110a4: 687b ldr r3, [r7, #4] 80110a6: 2201 movs r2, #1 80110a8: f883 203e strb.w r2, [r3, #62] @ 0x3e 80110ac: 687b ldr r3, [r7, #4] 80110ae: 2201 movs r2, #1 80110b0: f883 203f strb.w r2, [r3, #63] @ 0x3f 80110b4: 687b ldr r3, [r7, #4] 80110b6: 2201 movs r2, #1 80110b8: f883 2040 strb.w r2, [r3, #64] @ 0x40 80110bc: 687b ldr r3, [r7, #4] 80110be: 2201 movs r2, #1 80110c0: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80110c4: 687b ldr r3, [r7, #4] 80110c6: 2201 movs r2, #1 80110c8: f883 2042 strb.w r2, [r3, #66] @ 0x42 80110cc: 687b ldr r3, [r7, #4] 80110ce: 2201 movs r2, #1 80110d0: f883 2043 strb.w r2, [r3, #67] @ 0x43 80110d4: 687b ldr r3, [r7, #4] 80110d6: 2201 movs r2, #1 80110d8: f883 2044 strb.w r2, [r3, #68] @ 0x44 80110dc: 687b ldr r3, [r7, #4] 80110de: 2201 movs r2, #1 80110e0: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80110e4: 687b ldr r3, [r7, #4] 80110e6: 2201 movs r2, #1 80110e8: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 80110ec: 2300 movs r3, #0 } 80110ee: 4618 mov r0, r3 80110f0: 3708 adds r7, #8 80110f2: 46bd mov sp, r7 80110f4: bd80 pop {r7, pc} 080110f6 : * @brief Initializes the TIM Output Compare MSP. * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) { 80110f6: b480 push {r7} 80110f8: b083 sub sp, #12 80110fa: af00 add r7, sp, #0 80110fc: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_MspInit could be implemented in the user file */ } 80110fe: bf00 nop 8011100: 370c adds r7, #12 8011102: 46bd mov sp, r7 8011104: bc80 pop {r7} 8011106: 4770 bx lr 08011108 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { 8011108: b580 push {r7, lr} 801110a: b084 sub sp, #16 801110c: af00 add r7, sp, #0 801110e: 6078 str r0, [r7, #4] 8011110: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8011112: 2300 movs r3, #0 8011114: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 8011116: 683b ldr r3, [r7, #0] 8011118: 2b00 cmp r3, #0 801111a: d109 bne.n 8011130 801111c: 687b ldr r3, [r7, #4] 801111e: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8011122: b2db uxtb r3, r3 8011124: 2b01 cmp r3, #1 8011126: bf14 ite ne 8011128: 2301 movne r3, #1 801112a: 2300 moveq r3, #0 801112c: b2db uxtb r3, r3 801112e: e022 b.n 8011176 8011130: 683b ldr r3, [r7, #0] 8011132: 2b04 cmp r3, #4 8011134: d109 bne.n 801114a 8011136: 687b ldr r3, [r7, #4] 8011138: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 801113c: b2db uxtb r3, r3 801113e: 2b01 cmp r3, #1 8011140: bf14 ite ne 8011142: 2301 movne r3, #1 8011144: 2300 moveq r3, #0 8011146: b2db uxtb r3, r3 8011148: e015 b.n 8011176 801114a: 683b ldr r3, [r7, #0] 801114c: 2b08 cmp r3, #8 801114e: d109 bne.n 8011164 8011150: 687b ldr r3, [r7, #4] 8011152: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8011156: b2db uxtb r3, r3 8011158: 2b01 cmp r3, #1 801115a: bf14 ite ne 801115c: 2301 movne r3, #1 801115e: 2300 moveq r3, #0 8011160: b2db uxtb r3, r3 8011162: e008 b.n 8011176 8011164: 687b ldr r3, [r7, #4] 8011166: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 801116a: b2db uxtb r3, r3 801116c: 2b01 cmp r3, #1 801116e: bf14 ite ne 8011170: 2301 movne r3, #1 8011172: 2300 moveq r3, #0 8011174: b2db uxtb r3, r3 8011176: 2b00 cmp r3, #0 8011178: d001 beq.n 801117e { return HAL_ERROR; 801117a: 2301 movs r3, #1 801117c: e0ae b.n 80112dc } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 801117e: 683b ldr r3, [r7, #0] 8011180: 2b00 cmp r3, #0 8011182: d104 bne.n 801118e 8011184: 687b ldr r3, [r7, #4] 8011186: 2202 movs r2, #2 8011188: f883 203e strb.w r2, [r3, #62] @ 0x3e 801118c: e013 b.n 80111b6 801118e: 683b ldr r3, [r7, #0] 8011190: 2b04 cmp r3, #4 8011192: d104 bne.n 801119e 8011194: 687b ldr r3, [r7, #4] 8011196: 2202 movs r2, #2 8011198: f883 203f strb.w r2, [r3, #63] @ 0x3f 801119c: e00b b.n 80111b6 801119e: 683b ldr r3, [r7, #0] 80111a0: 2b08 cmp r3, #8 80111a2: d104 bne.n 80111ae 80111a4: 687b ldr r3, [r7, #4] 80111a6: 2202 movs r2, #2 80111a8: f883 2040 strb.w r2, [r3, #64] @ 0x40 80111ac: e003 b.n 80111b6 80111ae: 687b ldr r3, [r7, #4] 80111b0: 2202 movs r2, #2 80111b2: f883 2041 strb.w r2, [r3, #65] @ 0x41 switch (Channel) 80111b6: 683b ldr r3, [r7, #0] 80111b8: 2b0c cmp r3, #12 80111ba: d841 bhi.n 8011240 80111bc: a201 add r2, pc, #4 @ (adr r2, 80111c4 ) 80111be: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80111c2: bf00 nop 80111c4: 080111f9 .word 0x080111f9 80111c8: 08011241 .word 0x08011241 80111cc: 08011241 .word 0x08011241 80111d0: 08011241 .word 0x08011241 80111d4: 0801120b .word 0x0801120b 80111d8: 08011241 .word 0x08011241 80111dc: 08011241 .word 0x08011241 80111e0: 08011241 .word 0x08011241 80111e4: 0801121d .word 0x0801121d 80111e8: 08011241 .word 0x08011241 80111ec: 08011241 .word 0x08011241 80111f0: 08011241 .word 0x08011241 80111f4: 0801122f .word 0x0801122f { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 80111f8: 687b ldr r3, [r7, #4] 80111fa: 681b ldr r3, [r3, #0] 80111fc: 68da ldr r2, [r3, #12] 80111fe: 687b ldr r3, [r7, #4] 8011200: 681b ldr r3, [r3, #0] 8011202: f042 0202 orr.w r2, r2, #2 8011206: 60da str r2, [r3, #12] break; 8011208: e01d b.n 8011246 } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 801120a: 687b ldr r3, [r7, #4] 801120c: 681b ldr r3, [r3, #0] 801120e: 68da ldr r2, [r3, #12] 8011210: 687b ldr r3, [r7, #4] 8011212: 681b ldr r3, [r3, #0] 8011214: f042 0204 orr.w r2, r2, #4 8011218: 60da str r2, [r3, #12] break; 801121a: e014 b.n 8011246 } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 801121c: 687b ldr r3, [r7, #4] 801121e: 681b ldr r3, [r3, #0] 8011220: 68da ldr r2, [r3, #12] 8011222: 687b ldr r3, [r7, #4] 8011224: 681b ldr r3, [r3, #0] 8011226: f042 0208 orr.w r2, r2, #8 801122a: 60da str r2, [r3, #12] break; 801122c: e00b b.n 8011246 } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); 801122e: 687b ldr r3, [r7, #4] 8011230: 681b ldr r3, [r3, #0] 8011232: 68da ldr r2, [r3, #12] 8011234: 687b ldr r3, [r7, #4] 8011236: 681b ldr r3, [r3, #0] 8011238: f042 0210 orr.w r2, r2, #16 801123c: 60da str r2, [r3, #12] break; 801123e: e002 b.n 8011246 } default: status = HAL_ERROR; 8011240: 2301 movs r3, #1 8011242: 73fb strb r3, [r7, #15] break; 8011244: bf00 nop } if (status == HAL_OK) 8011246: 7bfb ldrb r3, [r7, #15] 8011248: 2b00 cmp r3, #0 801124a: d146 bne.n 80112da { /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 801124c: 687b ldr r3, [r7, #4] 801124e: 681b ldr r3, [r3, #0] 8011250: 2201 movs r2, #1 8011252: 6839 ldr r1, [r7, #0] 8011254: 4618 mov r0, r3 8011256: f000 fedf bl 8012018 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 801125a: 687b ldr r3, [r7, #4] 801125c: 681b ldr r3, [r3, #0] 801125e: 4a21 ldr r2, [pc, #132] @ (80112e4 ) 8011260: 4293 cmp r3, r2 8011262: d107 bne.n 8011274 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8011264: 687b ldr r3, [r7, #4] 8011266: 681b ldr r3, [r3, #0] 8011268: 6c5a ldr r2, [r3, #68] @ 0x44 801126a: 687b ldr r3, [r7, #4] 801126c: 681b ldr r3, [r3, #0] 801126e: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8011272: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8011274: 687b ldr r3, [r7, #4] 8011276: 681b ldr r3, [r3, #0] 8011278: 4a1a ldr r2, [pc, #104] @ (80112e4 ) 801127a: 4293 cmp r3, r2 801127c: d013 beq.n 80112a6 801127e: 687b ldr r3, [r7, #4] 8011280: 681b ldr r3, [r3, #0] 8011282: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8011286: d00e beq.n 80112a6 8011288: 687b ldr r3, [r7, #4] 801128a: 681b ldr r3, [r3, #0] 801128c: 4a16 ldr r2, [pc, #88] @ (80112e8 ) 801128e: 4293 cmp r3, r2 8011290: d009 beq.n 80112a6 8011292: 687b ldr r3, [r7, #4] 8011294: 681b ldr r3, [r3, #0] 8011296: 4a15 ldr r2, [pc, #84] @ (80112ec ) 8011298: 4293 cmp r3, r2 801129a: d004 beq.n 80112a6 801129c: 687b ldr r3, [r7, #4] 801129e: 681b ldr r3, [r3, #0] 80112a0: 4a13 ldr r2, [pc, #76] @ (80112f0 ) 80112a2: 4293 cmp r3, r2 80112a4: d111 bne.n 80112ca { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 80112a6: 687b ldr r3, [r7, #4] 80112a8: 681b ldr r3, [r3, #0] 80112aa: 689b ldr r3, [r3, #8] 80112ac: f003 0307 and.w r3, r3, #7 80112b0: 60bb str r3, [r7, #8] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80112b2: 68bb ldr r3, [r7, #8] 80112b4: 2b06 cmp r3, #6 80112b6: d010 beq.n 80112da { __HAL_TIM_ENABLE(htim); 80112b8: 687b ldr r3, [r7, #4] 80112ba: 681b ldr r3, [r3, #0] 80112bc: 681a ldr r2, [r3, #0] 80112be: 687b ldr r3, [r7, #4] 80112c0: 681b ldr r3, [r3, #0] 80112c2: f042 0201 orr.w r2, r2, #1 80112c6: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80112c8: e007 b.n 80112da } } else { __HAL_TIM_ENABLE(htim); 80112ca: 687b ldr r3, [r7, #4] 80112cc: 681b ldr r3, [r3, #0] 80112ce: 681a ldr r2, [r3, #0] 80112d0: 687b ldr r3, [r7, #4] 80112d2: 681b ldr r3, [r3, #0] 80112d4: f042 0201 orr.w r2, r2, #1 80112d8: 601a str r2, [r3, #0] } } /* Return function status */ return status; 80112da: 7bfb ldrb r3, [r7, #15] } 80112dc: 4618 mov r0, r3 80112de: 3710 adds r7, #16 80112e0: 46bd mov sp, r7 80112e2: bd80 pop {r7, pc} 80112e4: 40012c00 .word 0x40012c00 80112e8: 40000400 .word 0x40000400 80112ec: 40000800 .word 0x40000800 80112f0: 40000c00 .word 0x40000c00 080112f4 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 80112f4: b580 push {r7, lr} 80112f6: b082 sub sp, #8 80112f8: af00 add r7, sp, #0 80112fa: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 80112fc: 687b ldr r3, [r7, #4] 80112fe: 2b00 cmp r3, #0 8011300: d101 bne.n 8011306 { return HAL_ERROR; 8011302: 2301 movs r3, #1 8011304: e041 b.n 801138a assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8011306: 687b ldr r3, [r7, #4] 8011308: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 801130c: b2db uxtb r3, r3 801130e: 2b00 cmp r3, #0 8011310: d106 bne.n 8011320 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8011312: 687b ldr r3, [r7, #4] 8011314: 2200 movs r2, #0 8011316: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 801131a: 6878 ldr r0, [r7, #4] 801131c: f000 f839 bl 8011392 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8011320: 687b ldr r3, [r7, #4] 8011322: 2202 movs r2, #2 8011324: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8011328: 687b ldr r3, [r7, #4] 801132a: 681a ldr r2, [r3, #0] 801132c: 687b ldr r3, [r7, #4] 801132e: 3304 adds r3, #4 8011330: 4619 mov r1, r3 8011332: 4610 mov r0, r2 8011334: f000 fbda bl 8011aec /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8011338: 687b ldr r3, [r7, #4] 801133a: 2201 movs r2, #1 801133c: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011340: 687b ldr r3, [r7, #4] 8011342: 2201 movs r2, #1 8011344: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011348: 687b ldr r3, [r7, #4] 801134a: 2201 movs r2, #1 801134c: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011350: 687b ldr r3, [r7, #4] 8011352: 2201 movs r2, #1 8011354: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011358: 687b ldr r3, [r7, #4] 801135a: 2201 movs r2, #1 801135c: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011360: 687b ldr r3, [r7, #4] 8011362: 2201 movs r2, #1 8011364: f883 2042 strb.w r2, [r3, #66] @ 0x42 8011368: 687b ldr r3, [r7, #4] 801136a: 2201 movs r2, #1 801136c: f883 2043 strb.w r2, [r3, #67] @ 0x43 8011370: 687b ldr r3, [r7, #4] 8011372: 2201 movs r2, #1 8011374: f883 2044 strb.w r2, [r3, #68] @ 0x44 8011378: 687b ldr r3, [r7, #4] 801137a: 2201 movs r2, #1 801137c: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8011380: 687b ldr r3, [r7, #4] 8011382: 2201 movs r2, #1 8011384: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8011388: 2300 movs r3, #0 } 801138a: 4618 mov r0, r3 801138c: 3708 adds r7, #8 801138e: 46bd mov sp, r7 8011390: bd80 pop {r7, pc} 08011392 : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 8011392: b480 push {r7} 8011394: b083 sub sp, #12 8011396: af00 add r7, sp, #0 8011398: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 801139a: bf00 nop 801139c: 370c adds r7, #12 801139e: 46bd mov sp, r7 80113a0: bc80 pop {r7} 80113a2: 4770 bx lr 080113a4 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 80113a4: b580 push {r7, lr} 80113a6: b084 sub sp, #16 80113a8: af00 add r7, sp, #0 80113aa: 6078 str r0, [r7, #4] 80113ac: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 80113ae: 683b ldr r3, [r7, #0] 80113b0: 2b00 cmp r3, #0 80113b2: d109 bne.n 80113c8 80113b4: 687b ldr r3, [r7, #4] 80113b6: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 80113ba: b2db uxtb r3, r3 80113bc: 2b01 cmp r3, #1 80113be: bf14 ite ne 80113c0: 2301 movne r3, #1 80113c2: 2300 moveq r3, #0 80113c4: b2db uxtb r3, r3 80113c6: e022 b.n 801140e 80113c8: 683b ldr r3, [r7, #0] 80113ca: 2b04 cmp r3, #4 80113cc: d109 bne.n 80113e2 80113ce: 687b ldr r3, [r7, #4] 80113d0: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 80113d4: b2db uxtb r3, r3 80113d6: 2b01 cmp r3, #1 80113d8: bf14 ite ne 80113da: 2301 movne r3, #1 80113dc: 2300 moveq r3, #0 80113de: b2db uxtb r3, r3 80113e0: e015 b.n 801140e 80113e2: 683b ldr r3, [r7, #0] 80113e4: 2b08 cmp r3, #8 80113e6: d109 bne.n 80113fc 80113e8: 687b ldr r3, [r7, #4] 80113ea: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 80113ee: b2db uxtb r3, r3 80113f0: 2b01 cmp r3, #1 80113f2: bf14 ite ne 80113f4: 2301 movne r3, #1 80113f6: 2300 moveq r3, #0 80113f8: b2db uxtb r3, r3 80113fa: e008 b.n 801140e 80113fc: 687b ldr r3, [r7, #4] 80113fe: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8011402: b2db uxtb r3, r3 8011404: 2b01 cmp r3, #1 8011406: bf14 ite ne 8011408: 2301 movne r3, #1 801140a: 2300 moveq r3, #0 801140c: b2db uxtb r3, r3 801140e: 2b00 cmp r3, #0 8011410: d001 beq.n 8011416 { return HAL_ERROR; 8011412: 2301 movs r3, #1 8011414: e063 b.n 80114de } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8011416: 683b ldr r3, [r7, #0] 8011418: 2b00 cmp r3, #0 801141a: d104 bne.n 8011426 801141c: 687b ldr r3, [r7, #4] 801141e: 2202 movs r2, #2 8011420: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011424: e013 b.n 801144e 8011426: 683b ldr r3, [r7, #0] 8011428: 2b04 cmp r3, #4 801142a: d104 bne.n 8011436 801142c: 687b ldr r3, [r7, #4] 801142e: 2202 movs r2, #2 8011430: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011434: e00b b.n 801144e 8011436: 683b ldr r3, [r7, #0] 8011438: 2b08 cmp r3, #8 801143a: d104 bne.n 8011446 801143c: 687b ldr r3, [r7, #4] 801143e: 2202 movs r2, #2 8011440: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011444: e003 b.n 801144e 8011446: 687b ldr r3, [r7, #4] 8011448: 2202 movs r2, #2 801144a: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 801144e: 687b ldr r3, [r7, #4] 8011450: 681b ldr r3, [r3, #0] 8011452: 2201 movs r2, #1 8011454: 6839 ldr r1, [r7, #0] 8011456: 4618 mov r0, r3 8011458: f000 fdde bl 8012018 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 801145c: 687b ldr r3, [r7, #4] 801145e: 681b ldr r3, [r3, #0] 8011460: 4a21 ldr r2, [pc, #132] @ (80114e8 ) 8011462: 4293 cmp r3, r2 8011464: d107 bne.n 8011476 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8011466: 687b ldr r3, [r7, #4] 8011468: 681b ldr r3, [r3, #0] 801146a: 6c5a ldr r2, [r3, #68] @ 0x44 801146c: 687b ldr r3, [r7, #4] 801146e: 681b ldr r3, [r3, #0] 8011470: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8011474: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8011476: 687b ldr r3, [r7, #4] 8011478: 681b ldr r3, [r3, #0] 801147a: 4a1b ldr r2, [pc, #108] @ (80114e8 ) 801147c: 4293 cmp r3, r2 801147e: d013 beq.n 80114a8 8011480: 687b ldr r3, [r7, #4] 8011482: 681b ldr r3, [r3, #0] 8011484: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8011488: d00e beq.n 80114a8 801148a: 687b ldr r3, [r7, #4] 801148c: 681b ldr r3, [r3, #0] 801148e: 4a17 ldr r2, [pc, #92] @ (80114ec ) 8011490: 4293 cmp r3, r2 8011492: d009 beq.n 80114a8 8011494: 687b ldr r3, [r7, #4] 8011496: 681b ldr r3, [r3, #0] 8011498: 4a15 ldr r2, [pc, #84] @ (80114f0 ) 801149a: 4293 cmp r3, r2 801149c: d004 beq.n 80114a8 801149e: 687b ldr r3, [r7, #4] 80114a0: 681b ldr r3, [r3, #0] 80114a2: 4a14 ldr r2, [pc, #80] @ (80114f4 ) 80114a4: 4293 cmp r3, r2 80114a6: d111 bne.n 80114cc { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 80114a8: 687b ldr r3, [r7, #4] 80114aa: 681b ldr r3, [r3, #0] 80114ac: 689b ldr r3, [r3, #8] 80114ae: f003 0307 and.w r3, r3, #7 80114b2: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80114b4: 68fb ldr r3, [r7, #12] 80114b6: 2b06 cmp r3, #6 80114b8: d010 beq.n 80114dc { __HAL_TIM_ENABLE(htim); 80114ba: 687b ldr r3, [r7, #4] 80114bc: 681b ldr r3, [r3, #0] 80114be: 681a ldr r2, [r3, #0] 80114c0: 687b ldr r3, [r7, #4] 80114c2: 681b ldr r3, [r3, #0] 80114c4: f042 0201 orr.w r2, r2, #1 80114c8: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80114ca: e007 b.n 80114dc } } else { __HAL_TIM_ENABLE(htim); 80114cc: 687b ldr r3, [r7, #4] 80114ce: 681b ldr r3, [r3, #0] 80114d0: 681a ldr r2, [r3, #0] 80114d2: 687b ldr r3, [r7, #4] 80114d4: 681b ldr r3, [r3, #0] 80114d6: f042 0201 orr.w r2, r2, #1 80114da: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 80114dc: 2300 movs r3, #0 } 80114de: 4618 mov r0, r3 80114e0: 3710 adds r7, #16 80114e2: 46bd mov sp, r7 80114e4: bd80 pop {r7, pc} 80114e6: bf00 nop 80114e8: 40012c00 .word 0x40012c00 80114ec: 40000400 .word 0x40000400 80114f0: 40000800 .word 0x40000800 80114f4: 40000c00 .word 0x40000c00 080114f8 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 80114f8: b580 push {r7, lr} 80114fa: b084 sub sp, #16 80114fc: af00 add r7, sp, #0 80114fe: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 8011500: 687b ldr r3, [r7, #4] 8011502: 681b ldr r3, [r3, #0] 8011504: 68db ldr r3, [r3, #12] 8011506: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 8011508: 687b ldr r3, [r7, #4] 801150a: 681b ldr r3, [r3, #0] 801150c: 691b ldr r3, [r3, #16] 801150e: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 8011510: 68bb ldr r3, [r7, #8] 8011512: f003 0302 and.w r3, r3, #2 8011516: 2b00 cmp r3, #0 8011518: d020 beq.n 801155c { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 801151a: 68fb ldr r3, [r7, #12] 801151c: f003 0302 and.w r3, r3, #2 8011520: 2b00 cmp r3, #0 8011522: d01b beq.n 801155c { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 8011524: 687b ldr r3, [r7, #4] 8011526: 681b ldr r3, [r3, #0] 8011528: f06f 0202 mvn.w r2, #2 801152c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 801152e: 687b ldr r3, [r7, #4] 8011530: 2201 movs r2, #1 8011532: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8011534: 687b ldr r3, [r7, #4] 8011536: 681b ldr r3, [r3, #0] 8011538: 699b ldr r3, [r3, #24] 801153a: f003 0303 and.w r3, r3, #3 801153e: 2b00 cmp r3, #0 8011540: d003 beq.n 801154a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8011542: 6878 ldr r0, [r7, #4] 8011544: f000 fab6 bl 8011ab4 8011548: e005 b.n 8011556 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 801154a: 6878 ldr r0, [r7, #4] 801154c: f7f8 fdfe bl 800a14c HAL_TIM_PWM_PulseFinishedCallback(htim); 8011550: 6878 ldr r0, [r7, #4] 8011552: f000 fab8 bl 8011ac6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8011556: 687b ldr r3, [r7, #4] 8011558: 2200 movs r2, #0 801155a: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 801155c: 68bb ldr r3, [r7, #8] 801155e: f003 0304 and.w r3, r3, #4 8011562: 2b00 cmp r3, #0 8011564: d020 beq.n 80115a8 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 8011566: 68fb ldr r3, [r7, #12] 8011568: f003 0304 and.w r3, r3, #4 801156c: 2b00 cmp r3, #0 801156e: d01b beq.n 80115a8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 8011570: 687b ldr r3, [r7, #4] 8011572: 681b ldr r3, [r3, #0] 8011574: f06f 0204 mvn.w r2, #4 8011578: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 801157a: 687b ldr r3, [r7, #4] 801157c: 2202 movs r2, #2 801157e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8011580: 687b ldr r3, [r7, #4] 8011582: 681b ldr r3, [r3, #0] 8011584: 699b ldr r3, [r3, #24] 8011586: f403 7340 and.w r3, r3, #768 @ 0x300 801158a: 2b00 cmp r3, #0 801158c: d003 beq.n 8011596 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 801158e: 6878 ldr r0, [r7, #4] 8011590: f000 fa90 bl 8011ab4 8011594: e005 b.n 80115a2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8011596: 6878 ldr r0, [r7, #4] 8011598: f7f8 fdd8 bl 800a14c HAL_TIM_PWM_PulseFinishedCallback(htim); 801159c: 6878 ldr r0, [r7, #4] 801159e: f000 fa92 bl 8011ac6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80115a2: 687b ldr r3, [r7, #4] 80115a4: 2200 movs r2, #0 80115a6: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 80115a8: 68bb ldr r3, [r7, #8] 80115aa: f003 0308 and.w r3, r3, #8 80115ae: 2b00 cmp r3, #0 80115b0: d020 beq.n 80115f4 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 80115b2: 68fb ldr r3, [r7, #12] 80115b4: f003 0308 and.w r3, r3, #8 80115b8: 2b00 cmp r3, #0 80115ba: d01b beq.n 80115f4 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 80115bc: 687b ldr r3, [r7, #4] 80115be: 681b ldr r3, [r3, #0] 80115c0: f06f 0208 mvn.w r2, #8 80115c4: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 80115c6: 687b ldr r3, [r7, #4] 80115c8: 2204 movs r2, #4 80115ca: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 80115cc: 687b ldr r3, [r7, #4] 80115ce: 681b ldr r3, [r3, #0] 80115d0: 69db ldr r3, [r3, #28] 80115d2: f003 0303 and.w r3, r3, #3 80115d6: 2b00 cmp r3, #0 80115d8: d003 beq.n 80115e2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80115da: 6878 ldr r0, [r7, #4] 80115dc: f000 fa6a bl 8011ab4 80115e0: e005 b.n 80115ee { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80115e2: 6878 ldr r0, [r7, #4] 80115e4: f7f8 fdb2 bl 800a14c HAL_TIM_PWM_PulseFinishedCallback(htim); 80115e8: 6878 ldr r0, [r7, #4] 80115ea: f000 fa6c bl 8011ac6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80115ee: 687b ldr r3, [r7, #4] 80115f0: 2200 movs r2, #0 80115f2: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 80115f4: 68bb ldr r3, [r7, #8] 80115f6: f003 0310 and.w r3, r3, #16 80115fa: 2b00 cmp r3, #0 80115fc: d020 beq.n 8011640 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 80115fe: 68fb ldr r3, [r7, #12] 8011600: f003 0310 and.w r3, r3, #16 8011604: 2b00 cmp r3, #0 8011606: d01b beq.n 8011640 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 8011608: 687b ldr r3, [r7, #4] 801160a: 681b ldr r3, [r3, #0] 801160c: f06f 0210 mvn.w r2, #16 8011610: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8011612: 687b ldr r3, [r7, #4] 8011614: 2208 movs r2, #8 8011616: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8011618: 687b ldr r3, [r7, #4] 801161a: 681b ldr r3, [r3, #0] 801161c: 69db ldr r3, [r3, #28] 801161e: f403 7340 and.w r3, r3, #768 @ 0x300 8011622: 2b00 cmp r3, #0 8011624: d003 beq.n 801162e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8011626: 6878 ldr r0, [r7, #4] 8011628: f000 fa44 bl 8011ab4 801162c: e005 b.n 801163a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 801162e: 6878 ldr r0, [r7, #4] 8011630: f7f8 fd8c bl 800a14c HAL_TIM_PWM_PulseFinishedCallback(htim); 8011634: 6878 ldr r0, [r7, #4] 8011636: f000 fa46 bl 8011ac6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 801163a: 687b ldr r3, [r7, #4] 801163c: 2200 movs r2, #0 801163e: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 8011640: 68bb ldr r3, [r7, #8] 8011642: f003 0301 and.w r3, r3, #1 8011646: 2b00 cmp r3, #0 8011648: d00c beq.n 8011664 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 801164a: 68fb ldr r3, [r7, #12] 801164c: f003 0301 and.w r3, r3, #1 8011650: 2b00 cmp r3, #0 8011652: d007 beq.n 8011664 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 8011654: 687b ldr r3, [r7, #4] 8011656: 681b ldr r3, [r3, #0] 8011658: f06f 0201 mvn.w r2, #1 801165c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 801165e: 6878 ldr r0, [r7, #4] 8011660: f000 fa1f bl 8011aa2 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) 8011664: 68bb ldr r3, [r7, #8] 8011666: f003 0380 and.w r3, r3, #128 @ 0x80 801166a: 2b00 cmp r3, #0 801166c: d00c beq.n 8011688 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 801166e: 68fb ldr r3, [r7, #12] 8011670: f003 0380 and.w r3, r3, #128 @ 0x80 8011674: 2b00 cmp r3, #0 8011676: d007 beq.n 8011688 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); 8011678: 687b ldr r3, [r7, #4] 801167a: 681b ldr r3, [r3, #0] 801167c: f06f 0280 mvn.w r2, #128 @ 0x80 8011680: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8011682: 6878 ldr r0, [r7, #4] 8011684: f000 fd5b bl 801213e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 8011688: 68bb ldr r3, [r7, #8] 801168a: f003 0340 and.w r3, r3, #64 @ 0x40 801168e: 2b00 cmp r3, #0 8011690: d00c beq.n 80116ac { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 8011692: 68fb ldr r3, [r7, #12] 8011694: f003 0340 and.w r3, r3, #64 @ 0x40 8011698: 2b00 cmp r3, #0 801169a: d007 beq.n 80116ac { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 801169c: 687b ldr r3, [r7, #4] 801169e: 681b ldr r3, [r3, #0] 80116a0: f06f 0240 mvn.w r2, #64 @ 0x40 80116a4: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 80116a6: 6878 ldr r0, [r7, #4] 80116a8: f000 fa16 bl 8011ad8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 80116ac: 68bb ldr r3, [r7, #8] 80116ae: f003 0320 and.w r3, r3, #32 80116b2: 2b00 cmp r3, #0 80116b4: d00c beq.n 80116d0 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 80116b6: 68fb ldr r3, [r7, #12] 80116b8: f003 0320 and.w r3, r3, #32 80116bc: 2b00 cmp r3, #0 80116be: d007 beq.n 80116d0 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 80116c0: 687b ldr r3, [r7, #4] 80116c2: 681b ldr r3, [r3, #0] 80116c4: f06f 0220 mvn.w r2, #32 80116c8: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 80116ca: 6878 ldr r0, [r7, #4] 80116cc: f000 fd2e bl 801212c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 80116d0: bf00 nop 80116d2: 3710 adds r7, #16 80116d4: 46bd mov sp, r7 80116d6: bd80 pop {r7, pc} 080116d8 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 80116d8: b580 push {r7, lr} 80116da: b086 sub sp, #24 80116dc: af00 add r7, sp, #0 80116de: 60f8 str r0, [r7, #12] 80116e0: 60b9 str r1, [r7, #8] 80116e2: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80116e4: 2300 movs r3, #0 80116e6: 75fb strb r3, [r7, #23] assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); 80116e8: 68fb ldr r3, [r7, #12] 80116ea: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80116ee: 2b01 cmp r3, #1 80116f0: d101 bne.n 80116f6 80116f2: 2302 movs r3, #2 80116f4: e048 b.n 8011788 80116f6: 68fb ldr r3, [r7, #12] 80116f8: 2201 movs r2, #1 80116fa: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 80116fe: 687b ldr r3, [r7, #4] 8011700: 2b0c cmp r3, #12 8011702: d839 bhi.n 8011778 8011704: a201 add r2, pc, #4 @ (adr r2, 801170c ) 8011706: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801170a: bf00 nop 801170c: 08011741 .word 0x08011741 8011710: 08011779 .word 0x08011779 8011714: 08011779 .word 0x08011779 8011718: 08011779 .word 0x08011779 801171c: 0801174f .word 0x0801174f 8011720: 08011779 .word 0x08011779 8011724: 08011779 .word 0x08011779 8011728: 08011779 .word 0x08011779 801172c: 0801175d .word 0x0801175d 8011730: 08011779 .word 0x08011779 8011734: 08011779 .word 0x08011779 8011738: 08011779 .word 0x08011779 801173c: 0801176b .word 0x0801176b { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8011740: 68fb ldr r3, [r7, #12] 8011742: 681b ldr r3, [r3, #0] 8011744: 68b9 ldr r1, [r7, #8] 8011746: 4618 mov r0, r3 8011748: f000 fa48 bl 8011bdc break; 801174c: e017 b.n 801177e { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); 801174e: 68fb ldr r3, [r7, #12] 8011750: 681b ldr r3, [r3, #0] 8011752: 68b9 ldr r1, [r7, #8] 8011754: 4618 mov r0, r3 8011756: f000 faa7 bl 8011ca8 break; 801175a: e010 b.n 801177e { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); 801175c: 68fb ldr r3, [r7, #12] 801175e: 681b ldr r3, [r3, #0] 8011760: 68b9 ldr r1, [r7, #8] 8011762: 4618 mov r0, r3 8011764: f000 fb0a bl 8011d7c break; 8011768: e009 b.n 801177e { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); 801176a: 68fb ldr r3, [r7, #12] 801176c: 681b ldr r3, [r3, #0] 801176e: 68b9 ldr r1, [r7, #8] 8011770: 4618 mov r0, r3 8011772: f000 fb6d bl 8011e50 break; 8011776: e002 b.n 801177e } default: status = HAL_ERROR; 8011778: 2301 movs r3, #1 801177a: 75fb strb r3, [r7, #23] break; 801177c: bf00 nop } __HAL_UNLOCK(htim); 801177e: 68fb ldr r3, [r7, #12] 8011780: 2200 movs r2, #0 8011782: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8011786: 7dfb ldrb r3, [r7, #23] } 8011788: 4618 mov r0, r3 801178a: 3718 adds r7, #24 801178c: 46bd mov sp, r7 801178e: bd80 pop {r7, pc} 08011790 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8011790: b580 push {r7, lr} 8011792: b086 sub sp, #24 8011794: af00 add r7, sp, #0 8011796: 60f8 str r0, [r7, #12] 8011798: 60b9 str r1, [r7, #8] 801179a: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 801179c: 2300 movs r3, #0 801179e: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 80117a0: 68fb ldr r3, [r7, #12] 80117a2: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80117a6: 2b01 cmp r3, #1 80117a8: d101 bne.n 80117ae 80117aa: 2302 movs r3, #2 80117ac: e0ae b.n 801190c 80117ae: 68fb ldr r3, [r7, #12] 80117b0: 2201 movs r2, #1 80117b2: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 80117b6: 687b ldr r3, [r7, #4] 80117b8: 2b0c cmp r3, #12 80117ba: f200 809f bhi.w 80118fc 80117be: a201 add r2, pc, #4 @ (adr r2, 80117c4 ) 80117c0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80117c4: 080117f9 .word 0x080117f9 80117c8: 080118fd .word 0x080118fd 80117cc: 080118fd .word 0x080118fd 80117d0: 080118fd .word 0x080118fd 80117d4: 08011839 .word 0x08011839 80117d8: 080118fd .word 0x080118fd 80117dc: 080118fd .word 0x080118fd 80117e0: 080118fd .word 0x080118fd 80117e4: 0801187b .word 0x0801187b 80117e8: 080118fd .word 0x080118fd 80117ec: 080118fd .word 0x080118fd 80117f0: 080118fd .word 0x080118fd 80117f4: 080118bb .word 0x080118bb { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 80117f8: 68fb ldr r3, [r7, #12] 80117fa: 681b ldr r3, [r3, #0] 80117fc: 68b9 ldr r1, [r7, #8] 80117fe: 4618 mov r0, r3 8011800: f000 f9ec bl 8011bdc /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 8011804: 68fb ldr r3, [r7, #12] 8011806: 681b ldr r3, [r3, #0] 8011808: 699a ldr r2, [r3, #24] 801180a: 68fb ldr r3, [r7, #12] 801180c: 681b ldr r3, [r3, #0] 801180e: f042 0208 orr.w r2, r2, #8 8011812: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 8011814: 68fb ldr r3, [r7, #12] 8011816: 681b ldr r3, [r3, #0] 8011818: 699a ldr r2, [r3, #24] 801181a: 68fb ldr r3, [r7, #12] 801181c: 681b ldr r3, [r3, #0] 801181e: f022 0204 bic.w r2, r2, #4 8011822: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 8011824: 68fb ldr r3, [r7, #12] 8011826: 681b ldr r3, [r3, #0] 8011828: 6999 ldr r1, [r3, #24] 801182a: 68bb ldr r3, [r7, #8] 801182c: 691a ldr r2, [r3, #16] 801182e: 68fb ldr r3, [r7, #12] 8011830: 681b ldr r3, [r3, #0] 8011832: 430a orrs r2, r1 8011834: 619a str r2, [r3, #24] break; 8011836: e064 b.n 8011902 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8011838: 68fb ldr r3, [r7, #12] 801183a: 681b ldr r3, [r3, #0] 801183c: 68b9 ldr r1, [r7, #8] 801183e: 4618 mov r0, r3 8011840: f000 fa32 bl 8011ca8 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8011844: 68fb ldr r3, [r7, #12] 8011846: 681b ldr r3, [r3, #0] 8011848: 699a ldr r2, [r3, #24] 801184a: 68fb ldr r3, [r7, #12] 801184c: 681b ldr r3, [r3, #0] 801184e: f442 6200 orr.w r2, r2, #2048 @ 0x800 8011852: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 8011854: 68fb ldr r3, [r7, #12] 8011856: 681b ldr r3, [r3, #0] 8011858: 699a ldr r2, [r3, #24] 801185a: 68fb ldr r3, [r7, #12] 801185c: 681b ldr r3, [r3, #0] 801185e: f422 6280 bic.w r2, r2, #1024 @ 0x400 8011862: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8011864: 68fb ldr r3, [r7, #12] 8011866: 681b ldr r3, [r3, #0] 8011868: 6999 ldr r1, [r3, #24] 801186a: 68bb ldr r3, [r7, #8] 801186c: 691b ldr r3, [r3, #16] 801186e: 021a lsls r2, r3, #8 8011870: 68fb ldr r3, [r7, #12] 8011872: 681b ldr r3, [r3, #0] 8011874: 430a orrs r2, r1 8011876: 619a str r2, [r3, #24] break; 8011878: e043 b.n 8011902 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 801187a: 68fb ldr r3, [r7, #12] 801187c: 681b ldr r3, [r3, #0] 801187e: 68b9 ldr r1, [r7, #8] 8011880: 4618 mov r0, r3 8011882: f000 fa7b bl 8011d7c /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 8011886: 68fb ldr r3, [r7, #12] 8011888: 681b ldr r3, [r3, #0] 801188a: 69da ldr r2, [r3, #28] 801188c: 68fb ldr r3, [r7, #12] 801188e: 681b ldr r3, [r3, #0] 8011890: f042 0208 orr.w r2, r2, #8 8011894: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 8011896: 68fb ldr r3, [r7, #12] 8011898: 681b ldr r3, [r3, #0] 801189a: 69da ldr r2, [r3, #28] 801189c: 68fb ldr r3, [r7, #12] 801189e: 681b ldr r3, [r3, #0] 80118a0: f022 0204 bic.w r2, r2, #4 80118a4: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 80118a6: 68fb ldr r3, [r7, #12] 80118a8: 681b ldr r3, [r3, #0] 80118aa: 69d9 ldr r1, [r3, #28] 80118ac: 68bb ldr r3, [r7, #8] 80118ae: 691a ldr r2, [r3, #16] 80118b0: 68fb ldr r3, [r7, #12] 80118b2: 681b ldr r3, [r3, #0] 80118b4: 430a orrs r2, r1 80118b6: 61da str r2, [r3, #28] break; 80118b8: e023 b.n 8011902 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 80118ba: 68fb ldr r3, [r7, #12] 80118bc: 681b ldr r3, [r3, #0] 80118be: 68b9 ldr r1, [r7, #8] 80118c0: 4618 mov r0, r3 80118c2: f000 fac5 bl 8011e50 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 80118c6: 68fb ldr r3, [r7, #12] 80118c8: 681b ldr r3, [r3, #0] 80118ca: 69da ldr r2, [r3, #28] 80118cc: 68fb ldr r3, [r7, #12] 80118ce: 681b ldr r3, [r3, #0] 80118d0: f442 6200 orr.w r2, r2, #2048 @ 0x800 80118d4: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 80118d6: 68fb ldr r3, [r7, #12] 80118d8: 681b ldr r3, [r3, #0] 80118da: 69da ldr r2, [r3, #28] 80118dc: 68fb ldr r3, [r7, #12] 80118de: 681b ldr r3, [r3, #0] 80118e0: f422 6280 bic.w r2, r2, #1024 @ 0x400 80118e4: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 80118e6: 68fb ldr r3, [r7, #12] 80118e8: 681b ldr r3, [r3, #0] 80118ea: 69d9 ldr r1, [r3, #28] 80118ec: 68bb ldr r3, [r7, #8] 80118ee: 691b ldr r3, [r3, #16] 80118f0: 021a lsls r2, r3, #8 80118f2: 68fb ldr r3, [r7, #12] 80118f4: 681b ldr r3, [r3, #0] 80118f6: 430a orrs r2, r1 80118f8: 61da str r2, [r3, #28] break; 80118fa: e002 b.n 8011902 } default: status = HAL_ERROR; 80118fc: 2301 movs r3, #1 80118fe: 75fb strb r3, [r7, #23] break; 8011900: bf00 nop } __HAL_UNLOCK(htim); 8011902: 68fb ldr r3, [r7, #12] 8011904: 2200 movs r2, #0 8011906: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 801190a: 7dfb ldrb r3, [r7, #23] } 801190c: 4618 mov r0, r3 801190e: 3718 adds r7, #24 8011910: 46bd mov sp, r7 8011912: bd80 pop {r7, pc} 08011914 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 8011914: b580 push {r7, lr} 8011916: b084 sub sp, #16 8011918: af00 add r7, sp, #0 801191a: 6078 str r0, [r7, #4] 801191c: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 801191e: 2300 movs r3, #0 8011920: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 8011922: 687b ldr r3, [r7, #4] 8011924: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8011928: 2b01 cmp r3, #1 801192a: d101 bne.n 8011930 801192c: 2302 movs r3, #2 801192e: e0b4 b.n 8011a9a 8011930: 687b ldr r3, [r7, #4] 8011932: 2201 movs r2, #1 8011934: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 8011938: 687b ldr r3, [r7, #4] 801193a: 2202 movs r2, #2 801193c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 8011940: 687b ldr r3, [r7, #4] 8011942: 681b ldr r3, [r3, #0] 8011944: 689b ldr r3, [r3, #8] 8011946: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 8011948: 68bb ldr r3, [r7, #8] 801194a: f023 0377 bic.w r3, r3, #119 @ 0x77 801194e: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8011950: 68bb ldr r3, [r7, #8] 8011952: f423 437f bic.w r3, r3, #65280 @ 0xff00 8011956: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 8011958: 687b ldr r3, [r7, #4] 801195a: 681b ldr r3, [r3, #0] 801195c: 68ba ldr r2, [r7, #8] 801195e: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 8011960: 683b ldr r3, [r7, #0] 8011962: 681b ldr r3, [r3, #0] 8011964: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8011968: d03e beq.n 80119e8 801196a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 801196e: f200 8087 bhi.w 8011a80 8011972: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8011976: f000 8086 beq.w 8011a86 801197a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 801197e: d87f bhi.n 8011a80 8011980: 2b70 cmp r3, #112 @ 0x70 8011982: d01a beq.n 80119ba 8011984: 2b70 cmp r3, #112 @ 0x70 8011986: d87b bhi.n 8011a80 8011988: 2b60 cmp r3, #96 @ 0x60 801198a: d050 beq.n 8011a2e 801198c: 2b60 cmp r3, #96 @ 0x60 801198e: d877 bhi.n 8011a80 8011990: 2b50 cmp r3, #80 @ 0x50 8011992: d03c beq.n 8011a0e 8011994: 2b50 cmp r3, #80 @ 0x50 8011996: d873 bhi.n 8011a80 8011998: 2b40 cmp r3, #64 @ 0x40 801199a: d058 beq.n 8011a4e 801199c: 2b40 cmp r3, #64 @ 0x40 801199e: d86f bhi.n 8011a80 80119a0: 2b30 cmp r3, #48 @ 0x30 80119a2: d064 beq.n 8011a6e 80119a4: 2b30 cmp r3, #48 @ 0x30 80119a6: d86b bhi.n 8011a80 80119a8: 2b20 cmp r3, #32 80119aa: d060 beq.n 8011a6e 80119ac: 2b20 cmp r3, #32 80119ae: d867 bhi.n 8011a80 80119b0: 2b00 cmp r3, #0 80119b2: d05c beq.n 8011a6e 80119b4: 2b10 cmp r3, #16 80119b6: d05a beq.n 8011a6e 80119b8: e062 b.n 8011a80 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 80119ba: 687b ldr r3, [r7, #4] 80119bc: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 80119be: 683b ldr r3, [r7, #0] 80119c0: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 80119c2: 683b ldr r3, [r7, #0] 80119c4: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 80119c6: 683b ldr r3, [r7, #0] 80119c8: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 80119ca: f000 fb06 bl 8011fda /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 80119ce: 687b ldr r3, [r7, #4] 80119d0: 681b ldr r3, [r3, #0] 80119d2: 689b ldr r3, [r3, #8] 80119d4: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 80119d6: 68bb ldr r3, [r7, #8] 80119d8: f043 0377 orr.w r3, r3, #119 @ 0x77 80119dc: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80119de: 687b ldr r3, [r7, #4] 80119e0: 681b ldr r3, [r3, #0] 80119e2: 68ba ldr r2, [r7, #8] 80119e4: 609a str r2, [r3, #8] break; 80119e6: e04f b.n 8011a88 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 80119e8: 687b ldr r3, [r7, #4] 80119ea: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 80119ec: 683b ldr r3, [r7, #0] 80119ee: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 80119f0: 683b ldr r3, [r7, #0] 80119f2: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 80119f4: 683b ldr r3, [r7, #0] 80119f6: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 80119f8: f000 faef bl 8011fda /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 80119fc: 687b ldr r3, [r7, #4] 80119fe: 681b ldr r3, [r3, #0] 8011a00: 689a ldr r2, [r3, #8] 8011a02: 687b ldr r3, [r7, #4] 8011a04: 681b ldr r3, [r3, #0] 8011a06: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8011a0a: 609a str r2, [r3, #8] break; 8011a0c: e03c b.n 8011a88 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8011a0e: 687b ldr r3, [r7, #4] 8011a10: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8011a12: 683b ldr r3, [r7, #0] 8011a14: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8011a16: 683b ldr r3, [r7, #0] 8011a18: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 8011a1a: 461a mov r2, r3 8011a1c: f000 fa66 bl 8011eec TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 8011a20: 687b ldr r3, [r7, #4] 8011a22: 681b ldr r3, [r3, #0] 8011a24: 2150 movs r1, #80 @ 0x50 8011a26: 4618 mov r0, r3 8011a28: f000 fabd bl 8011fa6 break; 8011a2c: e02c b.n 8011a88 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 8011a2e: 687b ldr r3, [r7, #4] 8011a30: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8011a32: 683b ldr r3, [r7, #0] 8011a34: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8011a36: 683b ldr r3, [r7, #0] 8011a38: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 8011a3a: 461a mov r2, r3 8011a3c: f000 fa84 bl 8011f48 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 8011a40: 687b ldr r3, [r7, #4] 8011a42: 681b ldr r3, [r3, #0] 8011a44: 2160 movs r1, #96 @ 0x60 8011a46: 4618 mov r0, r3 8011a48: f000 faad bl 8011fa6 break; 8011a4c: e01c b.n 8011a88 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8011a4e: 687b ldr r3, [r7, #4] 8011a50: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8011a52: 683b ldr r3, [r7, #0] 8011a54: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8011a56: 683b ldr r3, [r7, #0] 8011a58: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 8011a5a: 461a mov r2, r3 8011a5c: f000 fa46 bl 8011eec TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 8011a60: 687b ldr r3, [r7, #4] 8011a62: 681b ldr r3, [r3, #0] 8011a64: 2140 movs r1, #64 @ 0x40 8011a66: 4618 mov r0, r3 8011a68: f000 fa9d bl 8011fa6 break; 8011a6c: e00c b.n 8011a88 case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 8011a6e: 687b ldr r3, [r7, #4] 8011a70: 681a ldr r2, [r3, #0] 8011a72: 683b ldr r3, [r7, #0] 8011a74: 681b ldr r3, [r3, #0] 8011a76: 4619 mov r1, r3 8011a78: 4610 mov r0, r2 8011a7a: f000 fa94 bl 8011fa6 break; 8011a7e: e003 b.n 8011a88 } default: status = HAL_ERROR; 8011a80: 2301 movs r3, #1 8011a82: 73fb strb r3, [r7, #15] break; 8011a84: e000 b.n 8011a88 break; 8011a86: bf00 nop } htim->State = HAL_TIM_STATE_READY; 8011a88: 687b ldr r3, [r7, #4] 8011a8a: 2201 movs r2, #1 8011a8c: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8011a90: 687b ldr r3, [r7, #4] 8011a92: 2200 movs r2, #0 8011a94: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8011a98: 7bfb ldrb r3, [r7, #15] } 8011a9a: 4618 mov r0, r3 8011a9c: 3710 adds r7, #16 8011a9e: 46bd mov sp, r7 8011aa0: bd80 pop {r7, pc} 08011aa2 : * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8011aa2: b480 push {r7} 8011aa4: b083 sub sp, #12 8011aa6: af00 add r7, sp, #0 8011aa8: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } 8011aaa: bf00 nop 8011aac: 370c adds r7, #12 8011aae: 46bd mov sp, r7 8011ab0: bc80 pop {r7} 8011ab2: 4770 bx lr 08011ab4 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 8011ab4: b480 push {r7} 8011ab6: b083 sub sp, #12 8011ab8: af00 add r7, sp, #0 8011aba: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 8011abc: bf00 nop 8011abe: 370c adds r7, #12 8011ac0: 46bd mov sp, r7 8011ac2: bc80 pop {r7} 8011ac4: 4770 bx lr 08011ac6 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8011ac6: b480 push {r7} 8011ac8: b083 sub sp, #12 8011aca: af00 add r7, sp, #0 8011acc: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8011ace: bf00 nop 8011ad0: 370c adds r7, #12 8011ad2: 46bd mov sp, r7 8011ad4: bc80 pop {r7} 8011ad6: 4770 bx lr 08011ad8 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 8011ad8: b480 push {r7} 8011ada: b083 sub sp, #12 8011adc: af00 add r7, sp, #0 8011ade: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 8011ae0: bf00 nop 8011ae2: 370c adds r7, #12 8011ae4: 46bd mov sp, r7 8011ae6: bc80 pop {r7} 8011ae8: 4770 bx lr ... 08011aec : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8011aec: b480 push {r7} 8011aee: b085 sub sp, #20 8011af0: af00 add r7, sp, #0 8011af2: 6078 str r0, [r7, #4] 8011af4: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8011af6: 687b ldr r3, [r7, #4] 8011af8: 681b ldr r3, [r3, #0] 8011afa: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8011afc: 687b ldr r3, [r7, #4] 8011afe: 4a33 ldr r2, [pc, #204] @ (8011bcc ) 8011b00: 4293 cmp r3, r2 8011b02: d00f beq.n 8011b24 8011b04: 687b ldr r3, [r7, #4] 8011b06: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8011b0a: d00b beq.n 8011b24 8011b0c: 687b ldr r3, [r7, #4] 8011b0e: 4a30 ldr r2, [pc, #192] @ (8011bd0 ) 8011b10: 4293 cmp r3, r2 8011b12: d007 beq.n 8011b24 8011b14: 687b ldr r3, [r7, #4] 8011b16: 4a2f ldr r2, [pc, #188] @ (8011bd4 ) 8011b18: 4293 cmp r3, r2 8011b1a: d003 beq.n 8011b24 8011b1c: 687b ldr r3, [r7, #4] 8011b1e: 4a2e ldr r2, [pc, #184] @ (8011bd8 ) 8011b20: 4293 cmp r3, r2 8011b22: d108 bne.n 8011b36 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8011b24: 68fb ldr r3, [r7, #12] 8011b26: f023 0370 bic.w r3, r3, #112 @ 0x70 8011b2a: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8011b2c: 683b ldr r3, [r7, #0] 8011b2e: 685b ldr r3, [r3, #4] 8011b30: 68fa ldr r2, [r7, #12] 8011b32: 4313 orrs r3, r2 8011b34: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8011b36: 687b ldr r3, [r7, #4] 8011b38: 4a24 ldr r2, [pc, #144] @ (8011bcc ) 8011b3a: 4293 cmp r3, r2 8011b3c: d00f beq.n 8011b5e 8011b3e: 687b ldr r3, [r7, #4] 8011b40: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8011b44: d00b beq.n 8011b5e 8011b46: 687b ldr r3, [r7, #4] 8011b48: 4a21 ldr r2, [pc, #132] @ (8011bd0 ) 8011b4a: 4293 cmp r3, r2 8011b4c: d007 beq.n 8011b5e 8011b4e: 687b ldr r3, [r7, #4] 8011b50: 4a20 ldr r2, [pc, #128] @ (8011bd4 ) 8011b52: 4293 cmp r3, r2 8011b54: d003 beq.n 8011b5e 8011b56: 687b ldr r3, [r7, #4] 8011b58: 4a1f ldr r2, [pc, #124] @ (8011bd8 ) 8011b5a: 4293 cmp r3, r2 8011b5c: d108 bne.n 8011b70 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8011b5e: 68fb ldr r3, [r7, #12] 8011b60: f423 7340 bic.w r3, r3, #768 @ 0x300 8011b64: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8011b66: 683b ldr r3, [r7, #0] 8011b68: 68db ldr r3, [r3, #12] 8011b6a: 68fa ldr r2, [r7, #12] 8011b6c: 4313 orrs r3, r2 8011b6e: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8011b70: 68fb ldr r3, [r7, #12] 8011b72: f023 0280 bic.w r2, r3, #128 @ 0x80 8011b76: 683b ldr r3, [r7, #0] 8011b78: 695b ldr r3, [r3, #20] 8011b7a: 4313 orrs r3, r2 8011b7c: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 8011b7e: 687b ldr r3, [r7, #4] 8011b80: 68fa ldr r2, [r7, #12] 8011b82: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8011b84: 683b ldr r3, [r7, #0] 8011b86: 689a ldr r2, [r3, #8] 8011b88: 687b ldr r3, [r7, #4] 8011b8a: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8011b8c: 683b ldr r3, [r7, #0] 8011b8e: 681a ldr r2, [r3, #0] 8011b90: 687b ldr r3, [r7, #4] 8011b92: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8011b94: 687b ldr r3, [r7, #4] 8011b96: 4a0d ldr r2, [pc, #52] @ (8011bcc ) 8011b98: 4293 cmp r3, r2 8011b9a: d103 bne.n 8011ba4 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8011b9c: 683b ldr r3, [r7, #0] 8011b9e: 691a ldr r2, [r3, #16] 8011ba0: 687b ldr r3, [r7, #4] 8011ba2: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8011ba4: 687b ldr r3, [r7, #4] 8011ba6: 2201 movs r2, #1 8011ba8: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 8011baa: 687b ldr r3, [r7, #4] 8011bac: 691b ldr r3, [r3, #16] 8011bae: f003 0301 and.w r3, r3, #1 8011bb2: 2b00 cmp r3, #0 8011bb4: d005 beq.n 8011bc2 { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 8011bb6: 687b ldr r3, [r7, #4] 8011bb8: 691b ldr r3, [r3, #16] 8011bba: f023 0201 bic.w r2, r3, #1 8011bbe: 687b ldr r3, [r7, #4] 8011bc0: 611a str r2, [r3, #16] } } 8011bc2: bf00 nop 8011bc4: 3714 adds r7, #20 8011bc6: 46bd mov sp, r7 8011bc8: bc80 pop {r7} 8011bca: 4770 bx lr 8011bcc: 40012c00 .word 0x40012c00 8011bd0: 40000400 .word 0x40000400 8011bd4: 40000800 .word 0x40000800 8011bd8: 40000c00 .word 0x40000c00 08011bdc : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8011bdc: b480 push {r7} 8011bde: b087 sub sp, #28 8011be0: af00 add r7, sp, #0 8011be2: 6078 str r0, [r7, #4] 8011be4: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8011be6: 687b ldr r3, [r7, #4] 8011be8: 6a1b ldr r3, [r3, #32] 8011bea: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 8011bec: 687b ldr r3, [r7, #4] 8011bee: 6a1b ldr r3, [r3, #32] 8011bf0: f023 0201 bic.w r2, r3, #1 8011bf4: 687b ldr r3, [r7, #4] 8011bf6: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8011bf8: 687b ldr r3, [r7, #4] 8011bfa: 685b ldr r3, [r3, #4] 8011bfc: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8011bfe: 687b ldr r3, [r7, #4] 8011c00: 699b ldr r3, [r3, #24] 8011c02: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 8011c04: 68fb ldr r3, [r7, #12] 8011c06: f023 0370 bic.w r3, r3, #112 @ 0x70 8011c0a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 8011c0c: 68fb ldr r3, [r7, #12] 8011c0e: f023 0303 bic.w r3, r3, #3 8011c12: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8011c14: 683b ldr r3, [r7, #0] 8011c16: 681b ldr r3, [r3, #0] 8011c18: 68fa ldr r2, [r7, #12] 8011c1a: 4313 orrs r3, r2 8011c1c: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 8011c1e: 697b ldr r3, [r7, #20] 8011c20: f023 0302 bic.w r3, r3, #2 8011c24: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 8011c26: 683b ldr r3, [r7, #0] 8011c28: 689b ldr r3, [r3, #8] 8011c2a: 697a ldr r2, [r7, #20] 8011c2c: 4313 orrs r3, r2 8011c2e: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8011c30: 687b ldr r3, [r7, #4] 8011c32: 4a1c ldr r2, [pc, #112] @ (8011ca4 ) 8011c34: 4293 cmp r3, r2 8011c36: d10c bne.n 8011c52 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 8011c38: 697b ldr r3, [r7, #20] 8011c3a: f023 0308 bic.w r3, r3, #8 8011c3e: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8011c40: 683b ldr r3, [r7, #0] 8011c42: 68db ldr r3, [r3, #12] 8011c44: 697a ldr r2, [r7, #20] 8011c46: 4313 orrs r3, r2 8011c48: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 8011c4a: 697b ldr r3, [r7, #20] 8011c4c: f023 0304 bic.w r3, r3, #4 8011c50: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8011c52: 687b ldr r3, [r7, #4] 8011c54: 4a13 ldr r2, [pc, #76] @ (8011ca4 ) 8011c56: 4293 cmp r3, r2 8011c58: d111 bne.n 8011c7e /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 8011c5a: 693b ldr r3, [r7, #16] 8011c5c: f423 7380 bic.w r3, r3, #256 @ 0x100 8011c60: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 8011c62: 693b ldr r3, [r7, #16] 8011c64: f423 7300 bic.w r3, r3, #512 @ 0x200 8011c68: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 8011c6a: 683b ldr r3, [r7, #0] 8011c6c: 695b ldr r3, [r3, #20] 8011c6e: 693a ldr r2, [r7, #16] 8011c70: 4313 orrs r3, r2 8011c72: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 8011c74: 683b ldr r3, [r7, #0] 8011c76: 699b ldr r3, [r3, #24] 8011c78: 693a ldr r2, [r7, #16] 8011c7a: 4313 orrs r3, r2 8011c7c: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8011c7e: 687b ldr r3, [r7, #4] 8011c80: 693a ldr r2, [r7, #16] 8011c82: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8011c84: 687b ldr r3, [r7, #4] 8011c86: 68fa ldr r2, [r7, #12] 8011c88: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 8011c8a: 683b ldr r3, [r7, #0] 8011c8c: 685a ldr r2, [r3, #4] 8011c8e: 687b ldr r3, [r7, #4] 8011c90: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8011c92: 687b ldr r3, [r7, #4] 8011c94: 697a ldr r2, [r7, #20] 8011c96: 621a str r2, [r3, #32] } 8011c98: bf00 nop 8011c9a: 371c adds r7, #28 8011c9c: 46bd mov sp, r7 8011c9e: bc80 pop {r7} 8011ca0: 4770 bx lr 8011ca2: bf00 nop 8011ca4: 40012c00 .word 0x40012c00 08011ca8 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8011ca8: b480 push {r7} 8011caa: b087 sub sp, #28 8011cac: af00 add r7, sp, #0 8011cae: 6078 str r0, [r7, #4] 8011cb0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8011cb2: 687b ldr r3, [r7, #4] 8011cb4: 6a1b ldr r3, [r3, #32] 8011cb6: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8011cb8: 687b ldr r3, [r7, #4] 8011cba: 6a1b ldr r3, [r3, #32] 8011cbc: f023 0210 bic.w r2, r3, #16 8011cc0: 687b ldr r3, [r7, #4] 8011cc2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8011cc4: 687b ldr r3, [r7, #4] 8011cc6: 685b ldr r3, [r3, #4] 8011cc8: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8011cca: 687b ldr r3, [r7, #4] 8011ccc: 699b ldr r3, [r3, #24] 8011cce: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 8011cd0: 68fb ldr r3, [r7, #12] 8011cd2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8011cd6: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 8011cd8: 68fb ldr r3, [r7, #12] 8011cda: f423 7340 bic.w r3, r3, #768 @ 0x300 8011cde: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8011ce0: 683b ldr r3, [r7, #0] 8011ce2: 681b ldr r3, [r3, #0] 8011ce4: 021b lsls r3, r3, #8 8011ce6: 68fa ldr r2, [r7, #12] 8011ce8: 4313 orrs r3, r2 8011cea: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 8011cec: 697b ldr r3, [r7, #20] 8011cee: f023 0320 bic.w r3, r3, #32 8011cf2: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 8011cf4: 683b ldr r3, [r7, #0] 8011cf6: 689b ldr r3, [r3, #8] 8011cf8: 011b lsls r3, r3, #4 8011cfa: 697a ldr r2, [r7, #20] 8011cfc: 4313 orrs r3, r2 8011cfe: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 8011d00: 687b ldr r3, [r7, #4] 8011d02: 4a1d ldr r2, [pc, #116] @ (8011d78 ) 8011d04: 4293 cmp r3, r2 8011d06: d10d bne.n 8011d24 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 8011d08: 697b ldr r3, [r7, #20] 8011d0a: f023 0380 bic.w r3, r3, #128 @ 0x80 8011d0e: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8011d10: 683b ldr r3, [r7, #0] 8011d12: 68db ldr r3, [r3, #12] 8011d14: 011b lsls r3, r3, #4 8011d16: 697a ldr r2, [r7, #20] 8011d18: 4313 orrs r3, r2 8011d1a: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8011d1c: 697b ldr r3, [r7, #20] 8011d1e: f023 0340 bic.w r3, r3, #64 @ 0x40 8011d22: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8011d24: 687b ldr r3, [r7, #4] 8011d26: 4a14 ldr r2, [pc, #80] @ (8011d78 ) 8011d28: 4293 cmp r3, r2 8011d2a: d113 bne.n 8011d54 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8011d2c: 693b ldr r3, [r7, #16] 8011d2e: f423 6380 bic.w r3, r3, #1024 @ 0x400 8011d32: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8011d34: 693b ldr r3, [r7, #16] 8011d36: f423 6300 bic.w r3, r3, #2048 @ 0x800 8011d3a: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8011d3c: 683b ldr r3, [r7, #0] 8011d3e: 695b ldr r3, [r3, #20] 8011d40: 009b lsls r3, r3, #2 8011d42: 693a ldr r2, [r7, #16] 8011d44: 4313 orrs r3, r2 8011d46: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8011d48: 683b ldr r3, [r7, #0] 8011d4a: 699b ldr r3, [r3, #24] 8011d4c: 009b lsls r3, r3, #2 8011d4e: 693a ldr r2, [r7, #16] 8011d50: 4313 orrs r3, r2 8011d52: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8011d54: 687b ldr r3, [r7, #4] 8011d56: 693a ldr r2, [r7, #16] 8011d58: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8011d5a: 687b ldr r3, [r7, #4] 8011d5c: 68fa ldr r2, [r7, #12] 8011d5e: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8011d60: 683b ldr r3, [r7, #0] 8011d62: 685a ldr r2, [r3, #4] 8011d64: 687b ldr r3, [r7, #4] 8011d66: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8011d68: 687b ldr r3, [r7, #4] 8011d6a: 697a ldr r2, [r7, #20] 8011d6c: 621a str r2, [r3, #32] } 8011d6e: bf00 nop 8011d70: 371c adds r7, #28 8011d72: 46bd mov sp, r7 8011d74: bc80 pop {r7} 8011d76: 4770 bx lr 8011d78: 40012c00 .word 0x40012c00 08011d7c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8011d7c: b480 push {r7} 8011d7e: b087 sub sp, #28 8011d80: af00 add r7, sp, #0 8011d82: 6078 str r0, [r7, #4] 8011d84: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8011d86: 687b ldr r3, [r7, #4] 8011d88: 6a1b ldr r3, [r3, #32] 8011d8a: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8011d8c: 687b ldr r3, [r7, #4] 8011d8e: 6a1b ldr r3, [r3, #32] 8011d90: f423 7280 bic.w r2, r3, #256 @ 0x100 8011d94: 687b ldr r3, [r7, #4] 8011d96: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8011d98: 687b ldr r3, [r7, #4] 8011d9a: 685b ldr r3, [r3, #4] 8011d9c: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8011d9e: 687b ldr r3, [r7, #4] 8011da0: 69db ldr r3, [r3, #28] 8011da2: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8011da4: 68fb ldr r3, [r7, #12] 8011da6: f023 0370 bic.w r3, r3, #112 @ 0x70 8011daa: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8011dac: 68fb ldr r3, [r7, #12] 8011dae: f023 0303 bic.w r3, r3, #3 8011db2: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8011db4: 683b ldr r3, [r7, #0] 8011db6: 681b ldr r3, [r3, #0] 8011db8: 68fa ldr r2, [r7, #12] 8011dba: 4313 orrs r3, r2 8011dbc: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8011dbe: 697b ldr r3, [r7, #20] 8011dc0: f423 7300 bic.w r3, r3, #512 @ 0x200 8011dc4: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 8011dc6: 683b ldr r3, [r7, #0] 8011dc8: 689b ldr r3, [r3, #8] 8011dca: 021b lsls r3, r3, #8 8011dcc: 697a ldr r2, [r7, #20] 8011dce: 4313 orrs r3, r2 8011dd0: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8011dd2: 687b ldr r3, [r7, #4] 8011dd4: 4a1d ldr r2, [pc, #116] @ (8011e4c ) 8011dd6: 4293 cmp r3, r2 8011dd8: d10d bne.n 8011df6 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8011dda: 697b ldr r3, [r7, #20] 8011ddc: f423 6300 bic.w r3, r3, #2048 @ 0x800 8011de0: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 8011de2: 683b ldr r3, [r7, #0] 8011de4: 68db ldr r3, [r3, #12] 8011de6: 021b lsls r3, r3, #8 8011de8: 697a ldr r2, [r7, #20] 8011dea: 4313 orrs r3, r2 8011dec: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8011dee: 697b ldr r3, [r7, #20] 8011df0: f423 6380 bic.w r3, r3, #1024 @ 0x400 8011df4: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8011df6: 687b ldr r3, [r7, #4] 8011df8: 4a14 ldr r2, [pc, #80] @ (8011e4c ) 8011dfa: 4293 cmp r3, r2 8011dfc: d113 bne.n 8011e26 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8011dfe: 693b ldr r3, [r7, #16] 8011e00: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8011e04: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 8011e06: 693b ldr r3, [r7, #16] 8011e08: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8011e0c: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8011e0e: 683b ldr r3, [r7, #0] 8011e10: 695b ldr r3, [r3, #20] 8011e12: 011b lsls r3, r3, #4 8011e14: 693a ldr r2, [r7, #16] 8011e16: 4313 orrs r3, r2 8011e18: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 8011e1a: 683b ldr r3, [r7, #0] 8011e1c: 699b ldr r3, [r3, #24] 8011e1e: 011b lsls r3, r3, #4 8011e20: 693a ldr r2, [r7, #16] 8011e22: 4313 orrs r3, r2 8011e24: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8011e26: 687b ldr r3, [r7, #4] 8011e28: 693a ldr r2, [r7, #16] 8011e2a: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8011e2c: 687b ldr r3, [r7, #4] 8011e2e: 68fa ldr r2, [r7, #12] 8011e30: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8011e32: 683b ldr r3, [r7, #0] 8011e34: 685a ldr r2, [r3, #4] 8011e36: 687b ldr r3, [r7, #4] 8011e38: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8011e3a: 687b ldr r3, [r7, #4] 8011e3c: 697a ldr r2, [r7, #20] 8011e3e: 621a str r2, [r3, #32] } 8011e40: bf00 nop 8011e42: 371c adds r7, #28 8011e44: 46bd mov sp, r7 8011e46: bc80 pop {r7} 8011e48: 4770 bx lr 8011e4a: bf00 nop 8011e4c: 40012c00 .word 0x40012c00 08011e50 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8011e50: b480 push {r7} 8011e52: b087 sub sp, #28 8011e54: af00 add r7, sp, #0 8011e56: 6078 str r0, [r7, #4] 8011e58: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8011e5a: 687b ldr r3, [r7, #4] 8011e5c: 6a1b ldr r3, [r3, #32] 8011e5e: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8011e60: 687b ldr r3, [r7, #4] 8011e62: 6a1b ldr r3, [r3, #32] 8011e64: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8011e68: 687b ldr r3, [r7, #4] 8011e6a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8011e6c: 687b ldr r3, [r7, #4] 8011e6e: 685b ldr r3, [r3, #4] 8011e70: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8011e72: 687b ldr r3, [r7, #4] 8011e74: 69db ldr r3, [r3, #28] 8011e76: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8011e78: 68fb ldr r3, [r7, #12] 8011e7a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8011e7e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8011e80: 68fb ldr r3, [r7, #12] 8011e82: f423 7340 bic.w r3, r3, #768 @ 0x300 8011e86: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8011e88: 683b ldr r3, [r7, #0] 8011e8a: 681b ldr r3, [r3, #0] 8011e8c: 021b lsls r3, r3, #8 8011e8e: 68fa ldr r2, [r7, #12] 8011e90: 4313 orrs r3, r2 8011e92: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8011e94: 693b ldr r3, [r7, #16] 8011e96: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8011e9a: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8011e9c: 683b ldr r3, [r7, #0] 8011e9e: 689b ldr r3, [r3, #8] 8011ea0: 031b lsls r3, r3, #12 8011ea2: 693a ldr r2, [r7, #16] 8011ea4: 4313 orrs r3, r2 8011ea6: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8011ea8: 687b ldr r3, [r7, #4] 8011eaa: 4a0f ldr r2, [pc, #60] @ (8011ee8 ) 8011eac: 4293 cmp r3, r2 8011eae: d109 bne.n 8011ec4 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8011eb0: 697b ldr r3, [r7, #20] 8011eb2: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8011eb6: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8011eb8: 683b ldr r3, [r7, #0] 8011eba: 695b ldr r3, [r3, #20] 8011ebc: 019b lsls r3, r3, #6 8011ebe: 697a ldr r2, [r7, #20] 8011ec0: 4313 orrs r3, r2 8011ec2: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8011ec4: 687b ldr r3, [r7, #4] 8011ec6: 697a ldr r2, [r7, #20] 8011ec8: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8011eca: 687b ldr r3, [r7, #4] 8011ecc: 68fa ldr r2, [r7, #12] 8011ece: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8011ed0: 683b ldr r3, [r7, #0] 8011ed2: 685a ldr r2, [r3, #4] 8011ed4: 687b ldr r3, [r7, #4] 8011ed6: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8011ed8: 687b ldr r3, [r7, #4] 8011eda: 693a ldr r2, [r7, #16] 8011edc: 621a str r2, [r3, #32] } 8011ede: bf00 nop 8011ee0: 371c adds r7, #28 8011ee2: 46bd mov sp, r7 8011ee4: bc80 pop {r7} 8011ee6: 4770 bx lr 8011ee8: 40012c00 .word 0x40012c00 08011eec : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8011eec: b480 push {r7} 8011eee: b087 sub sp, #28 8011ef0: af00 add r7, sp, #0 8011ef2: 60f8 str r0, [r7, #12] 8011ef4: 60b9 str r1, [r7, #8] 8011ef6: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8011ef8: 68fb ldr r3, [r7, #12] 8011efa: 6a1b ldr r3, [r3, #32] 8011efc: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8011efe: 68fb ldr r3, [r7, #12] 8011f00: 6a1b ldr r3, [r3, #32] 8011f02: f023 0201 bic.w r2, r3, #1 8011f06: 68fb ldr r3, [r7, #12] 8011f08: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8011f0a: 68fb ldr r3, [r7, #12] 8011f0c: 699b ldr r3, [r3, #24] 8011f0e: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8011f10: 693b ldr r3, [r7, #16] 8011f12: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8011f16: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8011f18: 687b ldr r3, [r7, #4] 8011f1a: 011b lsls r3, r3, #4 8011f1c: 693a ldr r2, [r7, #16] 8011f1e: 4313 orrs r3, r2 8011f20: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8011f22: 697b ldr r3, [r7, #20] 8011f24: f023 030a bic.w r3, r3, #10 8011f28: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8011f2a: 697a ldr r2, [r7, #20] 8011f2c: 68bb ldr r3, [r7, #8] 8011f2e: 4313 orrs r3, r2 8011f30: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8011f32: 68fb ldr r3, [r7, #12] 8011f34: 693a ldr r2, [r7, #16] 8011f36: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8011f38: 68fb ldr r3, [r7, #12] 8011f3a: 697a ldr r2, [r7, #20] 8011f3c: 621a str r2, [r3, #32] } 8011f3e: bf00 nop 8011f40: 371c adds r7, #28 8011f42: 46bd mov sp, r7 8011f44: bc80 pop {r7} 8011f46: 4770 bx lr 08011f48 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8011f48: b480 push {r7} 8011f4a: b087 sub sp, #28 8011f4c: af00 add r7, sp, #0 8011f4e: 60f8 str r0, [r7, #12] 8011f50: 60b9 str r1, [r7, #8] 8011f52: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8011f54: 68fb ldr r3, [r7, #12] 8011f56: 6a1b ldr r3, [r3, #32] 8011f58: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8011f5a: 68fb ldr r3, [r7, #12] 8011f5c: 6a1b ldr r3, [r3, #32] 8011f5e: f023 0210 bic.w r2, r3, #16 8011f62: 68fb ldr r3, [r7, #12] 8011f64: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8011f66: 68fb ldr r3, [r7, #12] 8011f68: 699b ldr r3, [r3, #24] 8011f6a: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8011f6c: 693b ldr r3, [r7, #16] 8011f6e: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8011f72: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8011f74: 687b ldr r3, [r7, #4] 8011f76: 031b lsls r3, r3, #12 8011f78: 693a ldr r2, [r7, #16] 8011f7a: 4313 orrs r3, r2 8011f7c: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8011f7e: 697b ldr r3, [r7, #20] 8011f80: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8011f84: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8011f86: 68bb ldr r3, [r7, #8] 8011f88: 011b lsls r3, r3, #4 8011f8a: 697a ldr r2, [r7, #20] 8011f8c: 4313 orrs r3, r2 8011f8e: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8011f90: 68fb ldr r3, [r7, #12] 8011f92: 693a ldr r2, [r7, #16] 8011f94: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8011f96: 68fb ldr r3, [r7, #12] 8011f98: 697a ldr r2, [r7, #20] 8011f9a: 621a str r2, [r3, #32] } 8011f9c: bf00 nop 8011f9e: 371c adds r7, #28 8011fa0: 46bd mov sp, r7 8011fa2: bc80 pop {r7} 8011fa4: 4770 bx lr 08011fa6 : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8011fa6: b480 push {r7} 8011fa8: b085 sub sp, #20 8011faa: af00 add r7, sp, #0 8011fac: 6078 str r0, [r7, #4] 8011fae: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8011fb0: 687b ldr r3, [r7, #4] 8011fb2: 689b ldr r3, [r3, #8] 8011fb4: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8011fb6: 68fb ldr r3, [r7, #12] 8011fb8: f023 0370 bic.w r3, r3, #112 @ 0x70 8011fbc: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8011fbe: 683a ldr r2, [r7, #0] 8011fc0: 68fb ldr r3, [r7, #12] 8011fc2: 4313 orrs r3, r2 8011fc4: f043 0307 orr.w r3, r3, #7 8011fc8: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8011fca: 687b ldr r3, [r7, #4] 8011fcc: 68fa ldr r2, [r7, #12] 8011fce: 609a str r2, [r3, #8] } 8011fd0: bf00 nop 8011fd2: 3714 adds r7, #20 8011fd4: 46bd mov sp, r7 8011fd6: bc80 pop {r7} 8011fd8: 4770 bx lr 08011fda : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8011fda: b480 push {r7} 8011fdc: b087 sub sp, #28 8011fde: af00 add r7, sp, #0 8011fe0: 60f8 str r0, [r7, #12] 8011fe2: 60b9 str r1, [r7, #8] 8011fe4: 607a str r2, [r7, #4] 8011fe6: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8011fe8: 68fb ldr r3, [r7, #12] 8011fea: 689b ldr r3, [r3, #8] 8011fec: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8011fee: 697b ldr r3, [r7, #20] 8011ff0: f423 437f bic.w r3, r3, #65280 @ 0xff00 8011ff4: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8011ff6: 683b ldr r3, [r7, #0] 8011ff8: 021a lsls r2, r3, #8 8011ffa: 687b ldr r3, [r7, #4] 8011ffc: 431a orrs r2, r3 8011ffe: 68bb ldr r3, [r7, #8] 8012000: 4313 orrs r3, r2 8012002: 697a ldr r2, [r7, #20] 8012004: 4313 orrs r3, r2 8012006: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8012008: 68fb ldr r3, [r7, #12] 801200a: 697a ldr r2, [r7, #20] 801200c: 609a str r2, [r3, #8] } 801200e: bf00 nop 8012010: 371c adds r7, #28 8012012: 46bd mov sp, r7 8012014: bc80 pop {r7} 8012016: 4770 bx lr 08012018 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8012018: b480 push {r7} 801201a: b087 sub sp, #28 801201c: af00 add r7, sp, #0 801201e: 60f8 str r0, [r7, #12] 8012020: 60b9 str r1, [r7, #8] 8012022: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8012024: 68bb ldr r3, [r7, #8] 8012026: f003 031f and.w r3, r3, #31 801202a: 2201 movs r2, #1 801202c: fa02 f303 lsl.w r3, r2, r3 8012030: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 8012032: 68fb ldr r3, [r7, #12] 8012034: 6a1a ldr r2, [r3, #32] 8012036: 697b ldr r3, [r7, #20] 8012038: 43db mvns r3, r3 801203a: 401a ands r2, r3 801203c: 68fb ldr r3, [r7, #12] 801203e: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8012040: 68fb ldr r3, [r7, #12] 8012042: 6a1a ldr r2, [r3, #32] 8012044: 68bb ldr r3, [r7, #8] 8012046: f003 031f and.w r3, r3, #31 801204a: 6879 ldr r1, [r7, #4] 801204c: fa01 f303 lsl.w r3, r1, r3 8012050: 431a orrs r2, r3 8012052: 68fb ldr r3, [r7, #12] 8012054: 621a str r2, [r3, #32] } 8012056: bf00 nop 8012058: 371c adds r7, #28 801205a: 46bd mov sp, r7 801205c: bc80 pop {r7} 801205e: 4770 bx lr 08012060 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8012060: b480 push {r7} 8012062: b085 sub sp, #20 8012064: af00 add r7, sp, #0 8012066: 6078 str r0, [r7, #4] 8012068: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 801206a: 687b ldr r3, [r7, #4] 801206c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8012070: 2b01 cmp r3, #1 8012072: d101 bne.n 8012078 8012074: 2302 movs r3, #2 8012076: e04b b.n 8012110 8012078: 687b ldr r3, [r7, #4] 801207a: 2201 movs r2, #1 801207c: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8012080: 687b ldr r3, [r7, #4] 8012082: 2202 movs r2, #2 8012084: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8012088: 687b ldr r3, [r7, #4] 801208a: 681b ldr r3, [r3, #0] 801208c: 685b ldr r3, [r3, #4] 801208e: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8012090: 687b ldr r3, [r7, #4] 8012092: 681b ldr r3, [r3, #0] 8012094: 689b ldr r3, [r3, #8] 8012096: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8012098: 68fb ldr r3, [r7, #12] 801209a: f023 0370 bic.w r3, r3, #112 @ 0x70 801209e: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 80120a0: 683b ldr r3, [r7, #0] 80120a2: 681b ldr r3, [r3, #0] 80120a4: 68fa ldr r2, [r7, #12] 80120a6: 4313 orrs r3, r2 80120a8: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 80120aa: 687b ldr r3, [r7, #4] 80120ac: 681b ldr r3, [r3, #0] 80120ae: 68fa ldr r2, [r7, #12] 80120b0: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80120b2: 687b ldr r3, [r7, #4] 80120b4: 681b ldr r3, [r3, #0] 80120b6: 4a19 ldr r2, [pc, #100] @ (801211c ) 80120b8: 4293 cmp r3, r2 80120ba: d013 beq.n 80120e4 80120bc: 687b ldr r3, [r7, #4] 80120be: 681b ldr r3, [r3, #0] 80120c0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80120c4: d00e beq.n 80120e4 80120c6: 687b ldr r3, [r7, #4] 80120c8: 681b ldr r3, [r3, #0] 80120ca: 4a15 ldr r2, [pc, #84] @ (8012120 ) 80120cc: 4293 cmp r3, r2 80120ce: d009 beq.n 80120e4 80120d0: 687b ldr r3, [r7, #4] 80120d2: 681b ldr r3, [r3, #0] 80120d4: 4a13 ldr r2, [pc, #76] @ (8012124 ) 80120d6: 4293 cmp r3, r2 80120d8: d004 beq.n 80120e4 80120da: 687b ldr r3, [r7, #4] 80120dc: 681b ldr r3, [r3, #0] 80120de: 4a12 ldr r2, [pc, #72] @ (8012128 ) 80120e0: 4293 cmp r3, r2 80120e2: d10c bne.n 80120fe { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 80120e4: 68bb ldr r3, [r7, #8] 80120e6: f023 0380 bic.w r3, r3, #128 @ 0x80 80120ea: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 80120ec: 683b ldr r3, [r7, #0] 80120ee: 685b ldr r3, [r3, #4] 80120f0: 68ba ldr r2, [r7, #8] 80120f2: 4313 orrs r3, r2 80120f4: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80120f6: 687b ldr r3, [r7, #4] 80120f8: 681b ldr r3, [r3, #0] 80120fa: 68ba ldr r2, [r7, #8] 80120fc: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 80120fe: 687b ldr r3, [r7, #4] 8012100: 2201 movs r2, #1 8012102: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8012106: 687b ldr r3, [r7, #4] 8012108: 2200 movs r2, #0 801210a: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 801210e: 2300 movs r3, #0 } 8012110: 4618 mov r0, r3 8012112: 3714 adds r7, #20 8012114: 46bd mov sp, r7 8012116: bc80 pop {r7} 8012118: 4770 bx lr 801211a: bf00 nop 801211c: 40012c00 .word 0x40012c00 8012120: 40000400 .word 0x40000400 8012124: 40000800 .word 0x40000800 8012128: 40000c00 .word 0x40000c00 0801212c : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 801212c: b480 push {r7} 801212e: b083 sub sp, #12 8012130: af00 add r7, sp, #0 8012132: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8012134: bf00 nop 8012136: 370c adds r7, #12 8012138: 46bd mov sp, r7 801213a: bc80 pop {r7} 801213c: 4770 bx lr 0801213e : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 801213e: b480 push {r7} 8012140: b083 sub sp, #12 8012142: af00 add r7, sp, #0 8012144: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8012146: bf00 nop 8012148: 370c adds r7, #12 801214a: 46bd mov sp, r7 801214c: bc80 pop {r7} 801214e: 4770 bx lr 08012150 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8012150: b580 push {r7, lr} 8012152: b082 sub sp, #8 8012154: af00 add r7, sp, #0 8012156: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8012158: 687b ldr r3, [r7, #4] 801215a: 2b00 cmp r3, #0 801215c: d101 bne.n 8012162 { return HAL_ERROR; 801215e: 2301 movs r3, #1 8012160: e042 b.n 80121e8 assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 8012162: 687b ldr r3, [r7, #4] 8012164: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8012168: b2db uxtb r3, r3 801216a: 2b00 cmp r3, #0 801216c: d106 bne.n 801217c { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 801216e: 687b ldr r3, [r7, #4] 8012170: 2200 movs r2, #0 8012172: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8012176: 6878 ldr r0, [r7, #4] 8012178: f7fb fbb4 bl 800d8e4 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 801217c: 687b ldr r3, [r7, #4] 801217e: 2224 movs r2, #36 @ 0x24 8012180: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8012184: 687b ldr r3, [r7, #4] 8012186: 681b ldr r3, [r3, #0] 8012188: 68da ldr r2, [r3, #12] 801218a: 687b ldr r3, [r7, #4] 801218c: 681b ldr r3, [r3, #0] 801218e: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8012192: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8012194: 6878 ldr r0, [r7, #4] 8012196: f000 ff99 bl 80130cc /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 801219a: 687b ldr r3, [r7, #4] 801219c: 681b ldr r3, [r3, #0] 801219e: 691a ldr r2, [r3, #16] 80121a0: 687b ldr r3, [r7, #4] 80121a2: 681b ldr r3, [r3, #0] 80121a4: f422 4290 bic.w r2, r2, #18432 @ 0x4800 80121a8: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 80121aa: 687b ldr r3, [r7, #4] 80121ac: 681b ldr r3, [r3, #0] 80121ae: 695a ldr r2, [r3, #20] 80121b0: 687b ldr r3, [r7, #4] 80121b2: 681b ldr r3, [r3, #0] 80121b4: f022 022a bic.w r2, r2, #42 @ 0x2a 80121b8: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 80121ba: 687b ldr r3, [r7, #4] 80121bc: 681b ldr r3, [r3, #0] 80121be: 68da ldr r2, [r3, #12] 80121c0: 687b ldr r3, [r7, #4] 80121c2: 681b ldr r3, [r3, #0] 80121c4: f442 5200 orr.w r2, r2, #8192 @ 0x2000 80121c8: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80121ca: 687b ldr r3, [r7, #4] 80121cc: 2200 movs r2, #0 80121ce: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 80121d0: 687b ldr r3, [r7, #4] 80121d2: 2220 movs r2, #32 80121d4: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 80121d8: 687b ldr r3, [r7, #4] 80121da: 2220 movs r2, #32 80121dc: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 80121e0: 687b ldr r3, [r7, #4] 80121e2: 2200 movs r2, #0 80121e4: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 80121e6: 2300 movs r3, #0 } 80121e8: 4618 mov r0, r3 80121ea: 3708 adds r7, #8 80121ec: 46bd mov sp, r7 80121ee: bd80 pop {r7, pc} 080121f0 : * @param Size Amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 80121f0: b580 push {r7, lr} 80121f2: b08a sub sp, #40 @ 0x28 80121f4: af02 add r7, sp, #8 80121f6: 60f8 str r0, [r7, #12] 80121f8: 60b9 str r1, [r7, #8] 80121fa: 603b str r3, [r7, #0] 80121fc: 4613 mov r3, r2 80121fe: 80fb strh r3, [r7, #6] const uint8_t *pdata8bits; const uint16_t *pdata16bits; uint32_t tickstart = 0U; 8012200: 2300 movs r3, #0 8012202: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8012204: 68fb ldr r3, [r7, #12] 8012206: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 801220a: b2db uxtb r3, r3 801220c: 2b20 cmp r3, #32 801220e: d175 bne.n 80122fc { if ((pData == NULL) || (Size == 0U)) 8012210: 68bb ldr r3, [r7, #8] 8012212: 2b00 cmp r3, #0 8012214: d002 beq.n 801221c 8012216: 88fb ldrh r3, [r7, #6] 8012218: 2b00 cmp r3, #0 801221a: d101 bne.n 8012220 { return HAL_ERROR; 801221c: 2301 movs r3, #1 801221e: e06e b.n 80122fe } huart->ErrorCode = HAL_UART_ERROR_NONE; 8012220: 68fb ldr r3, [r7, #12] 8012222: 2200 movs r2, #0 8012224: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8012226: 68fb ldr r3, [r7, #12] 8012228: 2221 movs r2, #33 @ 0x21 801222a: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 801222e: f7fb fd25 bl 800dc7c 8012232: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 8012234: 68fb ldr r3, [r7, #12] 8012236: 88fa ldrh r2, [r7, #6] 8012238: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 801223a: 68fb ldr r3, [r7, #12] 801223c: 88fa ldrh r2, [r7, #6] 801223e: 84da strh r2, [r3, #38] @ 0x26 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012240: 68fb ldr r3, [r7, #12] 8012242: 689b ldr r3, [r3, #8] 8012244: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012248: d108 bne.n 801225c 801224a: 68fb ldr r3, [r7, #12] 801224c: 691b ldr r3, [r3, #16] 801224e: 2b00 cmp r3, #0 8012250: d104 bne.n 801225c { pdata8bits = NULL; 8012252: 2300 movs r3, #0 8012254: 61fb str r3, [r7, #28] pdata16bits = (const uint16_t *) pData; 8012256: 68bb ldr r3, [r7, #8] 8012258: 61bb str r3, [r7, #24] 801225a: e003 b.n 8012264 } else { pdata8bits = pData; 801225c: 68bb ldr r3, [r7, #8] 801225e: 61fb str r3, [r7, #28] pdata16bits = NULL; 8012260: 2300 movs r3, #0 8012262: 61bb str r3, [r7, #24] } while (huart->TxXferCount > 0U) 8012264: e02e b.n 80122c4 { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8012266: 683b ldr r3, [r7, #0] 8012268: 9300 str r3, [sp, #0] 801226a: 697b ldr r3, [r7, #20] 801226c: 2200 movs r2, #0 801226e: 2180 movs r1, #128 @ 0x80 8012270: 68f8 ldr r0, [r7, #12] 8012272: f000 fc9e bl 8012bb2 8012276: 4603 mov r3, r0 8012278: 2b00 cmp r3, #0 801227a: d005 beq.n 8012288 { huart->gState = HAL_UART_STATE_READY; 801227c: 68fb ldr r3, [r7, #12] 801227e: 2220 movs r2, #32 8012280: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_TIMEOUT; 8012284: 2303 movs r3, #3 8012286: e03a b.n 80122fe } if (pdata8bits == NULL) 8012288: 69fb ldr r3, [r7, #28] 801228a: 2b00 cmp r3, #0 801228c: d10b bne.n 80122a6 { huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); 801228e: 69bb ldr r3, [r7, #24] 8012290: 881b ldrh r3, [r3, #0] 8012292: 461a mov r2, r3 8012294: 68fb ldr r3, [r7, #12] 8012296: 681b ldr r3, [r3, #0] 8012298: f3c2 0208 ubfx r2, r2, #0, #9 801229c: 605a str r2, [r3, #4] pdata16bits++; 801229e: 69bb ldr r3, [r7, #24] 80122a0: 3302 adds r3, #2 80122a2: 61bb str r3, [r7, #24] 80122a4: e007 b.n 80122b6 } else { huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); 80122a6: 69fb ldr r3, [r7, #28] 80122a8: 781a ldrb r2, [r3, #0] 80122aa: 68fb ldr r3, [r7, #12] 80122ac: 681b ldr r3, [r3, #0] 80122ae: 605a str r2, [r3, #4] pdata8bits++; 80122b0: 69fb ldr r3, [r7, #28] 80122b2: 3301 adds r3, #1 80122b4: 61fb str r3, [r7, #28] } huart->TxXferCount--; 80122b6: 68fb ldr r3, [r7, #12] 80122b8: 8cdb ldrh r3, [r3, #38] @ 0x26 80122ba: b29b uxth r3, r3 80122bc: 3b01 subs r3, #1 80122be: b29a uxth r2, r3 80122c0: 68fb ldr r3, [r7, #12] 80122c2: 84da strh r2, [r3, #38] @ 0x26 while (huart->TxXferCount > 0U) 80122c4: 68fb ldr r3, [r7, #12] 80122c6: 8cdb ldrh r3, [r3, #38] @ 0x26 80122c8: b29b uxth r3, r3 80122ca: 2b00 cmp r3, #0 80122cc: d1cb bne.n 8012266 } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 80122ce: 683b ldr r3, [r7, #0] 80122d0: 9300 str r3, [sp, #0] 80122d2: 697b ldr r3, [r7, #20] 80122d4: 2200 movs r2, #0 80122d6: 2140 movs r1, #64 @ 0x40 80122d8: 68f8 ldr r0, [r7, #12] 80122da: f000 fc6a bl 8012bb2 80122de: 4603 mov r3, r0 80122e0: 2b00 cmp r3, #0 80122e2: d005 beq.n 80122f0 { huart->gState = HAL_UART_STATE_READY; 80122e4: 68fb ldr r3, [r7, #12] 80122e6: 2220 movs r2, #32 80122e8: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_TIMEOUT; 80122ec: 2303 movs r3, #3 80122ee: e006 b.n 80122fe } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80122f0: 68fb ldr r3, [r7, #12] 80122f2: 2220 movs r2, #32 80122f4: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_OK; 80122f8: 2300 movs r3, #0 80122fa: e000 b.n 80122fe } else { return HAL_BUSY; 80122fc: 2302 movs r3, #2 } } 80122fe: 4618 mov r0, r3 8012300: 3720 adds r7, #32 8012302: 46bd mov sp, r7 8012304: bd80 pop {r7, pc} 08012306 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8012306: b480 push {r7} 8012308: b085 sub sp, #20 801230a: af00 add r7, sp, #0 801230c: 60f8 str r0, [r7, #12] 801230e: 60b9 str r1, [r7, #8] 8012310: 4613 mov r3, r2 8012312: 80fb strh r3, [r7, #6] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8012314: 68fb ldr r3, [r7, #12] 8012316: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 801231a: b2db uxtb r3, r3 801231c: 2b20 cmp r3, #32 801231e: d121 bne.n 8012364 { if ((pData == NULL) || (Size == 0U)) 8012320: 68bb ldr r3, [r7, #8] 8012322: 2b00 cmp r3, #0 8012324: d002 beq.n 801232c 8012326: 88fb ldrh r3, [r7, #6] 8012328: 2b00 cmp r3, #0 801232a: d101 bne.n 8012330 { return HAL_ERROR; 801232c: 2301 movs r3, #1 801232e: e01a b.n 8012366 } huart->pTxBuffPtr = pData; 8012330: 68fb ldr r3, [r7, #12] 8012332: 68ba ldr r2, [r7, #8] 8012334: 621a str r2, [r3, #32] huart->TxXferSize = Size; 8012336: 68fb ldr r3, [r7, #12] 8012338: 88fa ldrh r2, [r7, #6] 801233a: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 801233c: 68fb ldr r3, [r7, #12] 801233e: 88fa ldrh r2, [r7, #6] 8012340: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 8012342: 68fb ldr r3, [r7, #12] 8012344: 2200 movs r2, #0 8012346: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8012348: 68fb ldr r3, [r7, #12] 801234a: 2221 movs r2, #33 @ 0x21 801234c: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the UART Transmit data register empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); 8012350: 68fb ldr r3, [r7, #12] 8012352: 681b ldr r3, [r3, #0] 8012354: 68da ldr r2, [r3, #12] 8012356: 68fb ldr r3, [r7, #12] 8012358: 681b ldr r3, [r3, #0] 801235a: f042 0280 orr.w r2, r2, #128 @ 0x80 801235e: 60da str r2, [r3, #12] return HAL_OK; 8012360: 2300 movs r3, #0 8012362: e000 b.n 8012366 } else { return HAL_BUSY; 8012364: 2302 movs r3, #2 } } 8012366: 4618 mov r0, r3 8012368: 3714 adds r7, #20 801236a: 46bd mov sp, r7 801236c: bc80 pop {r7} 801236e: 4770 bx lr 08012370 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8012370: b580 push {r7, lr} 8012372: b08c sub sp, #48 @ 0x30 8012374: af00 add r7, sp, #0 8012376: 60f8 str r0, [r7, #12] 8012378: 60b9 str r1, [r7, #8] 801237a: 4613 mov r3, r2 801237c: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 801237e: 68fb ldr r3, [r7, #12] 8012380: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8012384: b2db uxtb r3, r3 8012386: 2b20 cmp r3, #32 8012388: d14a bne.n 8012420 { if ((pData == NULL) || (Size == 0U)) 801238a: 68bb ldr r3, [r7, #8] 801238c: 2b00 cmp r3, #0 801238e: d002 beq.n 8012396 8012390: 88fb ldrh r3, [r7, #6] 8012392: 2b00 cmp r3, #0 8012394: d101 bne.n 801239a { return HAL_ERROR; 8012396: 2301 movs r3, #1 8012398: e043 b.n 8012422 } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 801239a: 68fb ldr r3, [r7, #12] 801239c: 2201 movs r2, #1 801239e: 631a str r2, [r3, #48] @ 0x30 huart->RxEventType = HAL_UART_RXEVENT_TC; 80123a0: 68fb ldr r3, [r7, #12] 80123a2: 2200 movs r2, #0 80123a4: 635a str r2, [r3, #52] @ 0x34 status = UART_Start_Receive_IT(huart, pData, Size); 80123a6: 88fb ldrh r3, [r7, #6] 80123a8: 461a mov r2, r3 80123aa: 68b9 ldr r1, [r7, #8] 80123ac: 68f8 ldr r0, [r7, #12] 80123ae: f000 fc59 bl 8012c64 80123b2: 4603 mov r3, r0 80123b4: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check Rx process has been successfully started */ if (status == HAL_OK) 80123b8: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 80123bc: 2b00 cmp r3, #0 80123be: d12c bne.n 801241a { if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80123c0: 68fb ldr r3, [r7, #12] 80123c2: 6b1b ldr r3, [r3, #48] @ 0x30 80123c4: 2b01 cmp r3, #1 80123c6: d125 bne.n 8012414 { __HAL_UART_CLEAR_IDLEFLAG(huart); 80123c8: 2300 movs r3, #0 80123ca: 613b str r3, [r7, #16] 80123cc: 68fb ldr r3, [r7, #12] 80123ce: 681b ldr r3, [r3, #0] 80123d0: 681b ldr r3, [r3, #0] 80123d2: 613b str r3, [r7, #16] 80123d4: 68fb ldr r3, [r7, #12] 80123d6: 681b ldr r3, [r3, #0] 80123d8: 685b ldr r3, [r3, #4] 80123da: 613b str r3, [r7, #16] 80123dc: 693b ldr r3, [r7, #16] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80123de: 68fb ldr r3, [r7, #12] 80123e0: 681b ldr r3, [r3, #0] 80123e2: 330c adds r3, #12 80123e4: 61bb str r3, [r7, #24] */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80123e6: 69bb ldr r3, [r7, #24] 80123e8: e853 3f00 ldrex r3, [r3] 80123ec: 617b str r3, [r7, #20] return(result); 80123ee: 697b ldr r3, [r7, #20] 80123f0: f043 0310 orr.w r3, r3, #16 80123f4: 62bb str r3, [r7, #40] @ 0x28 80123f6: 68fb ldr r3, [r7, #12] 80123f8: 681b ldr r3, [r3, #0] 80123fa: 330c adds r3, #12 80123fc: 6aba ldr r2, [r7, #40] @ 0x28 80123fe: 627a str r2, [r7, #36] @ 0x24 8012400: 623b str r3, [r7, #32] */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012402: 6a39 ldr r1, [r7, #32] 8012404: 6a7a ldr r2, [r7, #36] @ 0x24 8012406: e841 2300 strex r3, r2, [r1] 801240a: 61fb str r3, [r7, #28] return(result); 801240c: 69fb ldr r3, [r7, #28] 801240e: 2b00 cmp r3, #0 8012410: d1e5 bne.n 80123de 8012412: e002 b.n 801241a { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8012414: 2301 movs r3, #1 8012416: f887 302f strb.w r3, [r7, #47] @ 0x2f } } return status; 801241a: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 801241e: e000 b.n 8012422 } else { return HAL_BUSY; 8012420: 2302 movs r3, #2 } } 8012422: 4618 mov r0, r3 8012424: 3730 adds r7, #48 @ 0x30 8012426: 46bd mov sp, r7 8012428: bd80 pop {r7, pc} ... 0801242c : * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { 801242c: b580 push {r7, lr} 801242e: b0a2 sub sp, #136 @ 0x88 8012430: af00 add r7, sp, #0 8012432: 6078 str r0, [r7, #4] uint32_t AbortCplt = 0x01U; 8012434: 2301 movs r3, #1 8012436: f8c7 3084 str.w r3, [r7, #132] @ 0x84 /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); 801243a: 687b ldr r3, [r7, #4] 801243c: 681b ldr r3, [r3, #0] 801243e: 330c adds r3, #12 8012440: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012442: 6e3b ldr r3, [r7, #96] @ 0x60 8012444: e853 3f00 ldrex r3, [r3] 8012448: 65fb str r3, [r7, #92] @ 0x5c return(result); 801244a: 6dfb ldr r3, [r7, #92] @ 0x5c 801244c: f423 73f0 bic.w r3, r3, #480 @ 0x1e0 8012450: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8012454: 687b ldr r3, [r7, #4] 8012456: 681b ldr r3, [r3, #0] 8012458: 330c adds r3, #12 801245a: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 801245e: 66fa str r2, [r7, #108] @ 0x6c 8012460: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012462: 6eb9 ldr r1, [r7, #104] @ 0x68 8012464: 6efa ldr r2, [r7, #108] @ 0x6c 8012466: e841 2300 strex r3, r2, [r1] 801246a: 667b str r3, [r7, #100] @ 0x64 return(result); 801246c: 6e7b ldr r3, [r7, #100] @ 0x64 801246e: 2b00 cmp r3, #0 8012470: d1e3 bne.n 801243a ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012472: 687b ldr r3, [r7, #4] 8012474: 681b ldr r3, [r3, #0] 8012476: 3314 adds r3, #20 8012478: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801247a: 6cfb ldr r3, [r7, #76] @ 0x4c 801247c: e853 3f00 ldrex r3, [r3] 8012480: 64bb str r3, [r7, #72] @ 0x48 return(result); 8012482: 6cbb ldr r3, [r7, #72] @ 0x48 8012484: f023 0301 bic.w r3, r3, #1 8012488: 67fb str r3, [r7, #124] @ 0x7c 801248a: 687b ldr r3, [r7, #4] 801248c: 681b ldr r3, [r3, #0] 801248e: 3314 adds r3, #20 8012490: 6ffa ldr r2, [r7, #124] @ 0x7c 8012492: 65ba str r2, [r7, #88] @ 0x58 8012494: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012496: 6d79 ldr r1, [r7, #84] @ 0x54 8012498: 6dba ldr r2, [r7, #88] @ 0x58 801249a: e841 2300 strex r3, r2, [r1] 801249e: 653b str r3, [r7, #80] @ 0x50 return(result); 80124a0: 6d3b ldr r3, [r7, #80] @ 0x50 80124a2: 2b00 cmp r3, #0 80124a4: d1e5 bne.n 8012472 /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80124a6: 687b ldr r3, [r7, #4] 80124a8: 6b1b ldr r3, [r3, #48] @ 0x30 80124aa: 2b01 cmp r3, #1 80124ac: d119 bne.n 80124e2 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); 80124ae: 687b ldr r3, [r7, #4] 80124b0: 681b ldr r3, [r3, #0] 80124b2: 330c adds r3, #12 80124b4: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80124b6: 6bbb ldr r3, [r7, #56] @ 0x38 80124b8: e853 3f00 ldrex r3, [r3] 80124bc: 637b str r3, [r7, #52] @ 0x34 return(result); 80124be: 6b7b ldr r3, [r7, #52] @ 0x34 80124c0: f023 0310 bic.w r3, r3, #16 80124c4: 67bb str r3, [r7, #120] @ 0x78 80124c6: 687b ldr r3, [r7, #4] 80124c8: 681b ldr r3, [r3, #0] 80124ca: 330c adds r3, #12 80124cc: 6fba ldr r2, [r7, #120] @ 0x78 80124ce: 647a str r2, [r7, #68] @ 0x44 80124d0: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80124d2: 6c39 ldr r1, [r7, #64] @ 0x40 80124d4: 6c7a ldr r2, [r7, #68] @ 0x44 80124d6: e841 2300 strex r3, r2, [r1] 80124da: 63fb str r3, [r7, #60] @ 0x3c return(result); 80124dc: 6bfb ldr r3, [r7, #60] @ 0x3c 80124de: 2b00 cmp r3, #0 80124e0: d1e5 bne.n 80124ae } /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ if (huart->hdmatx != NULL) 80124e2: 687b ldr r3, [r7, #4] 80124e4: 6b9b ldr r3, [r3, #56] @ 0x38 80124e6: 2b00 cmp r3, #0 80124e8: d00f beq.n 801250a { /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. Otherwise, set it to NULL */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) 80124ea: 687b ldr r3, [r7, #4] 80124ec: 681b ldr r3, [r3, #0] 80124ee: 695b ldr r3, [r3, #20] 80124f0: f003 0380 and.w r3, r3, #128 @ 0x80 80124f4: 2b00 cmp r3, #0 80124f6: d004 beq.n 8012502 { huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; 80124f8: 687b ldr r3, [r7, #4] 80124fa: 6b9b ldr r3, [r3, #56] @ 0x38 80124fc: 4a53 ldr r2, [pc, #332] @ (801264c ) 80124fe: 635a str r2, [r3, #52] @ 0x34 8012500: e003 b.n 801250a } else { huart->hdmatx->XferAbortCallback = NULL; 8012502: 687b ldr r3, [r7, #4] 8012504: 6b9b ldr r3, [r3, #56] @ 0x38 8012506: 2200 movs r2, #0 8012508: 635a str r2, [r3, #52] @ 0x34 } } /* DMA Rx Handle is valid */ if (huart->hdmarx != NULL) 801250a: 687b ldr r3, [r7, #4] 801250c: 6bdb ldr r3, [r3, #60] @ 0x3c 801250e: 2b00 cmp r3, #0 8012510: d00f beq.n 8012532 { /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. Otherwise, set it to NULL */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8012512: 687b ldr r3, [r7, #4] 8012514: 681b ldr r3, [r3, #0] 8012516: 695b ldr r3, [r3, #20] 8012518: f003 0340 and.w r3, r3, #64 @ 0x40 801251c: 2b00 cmp r3, #0 801251e: d004 beq.n 801252a { huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; 8012520: 687b ldr r3, [r7, #4] 8012522: 6bdb ldr r3, [r3, #60] @ 0x3c 8012524: 4a4a ldr r2, [pc, #296] @ (8012650 ) 8012526: 635a str r2, [r3, #52] @ 0x34 8012528: e003 b.n 8012532 } else { huart->hdmarx->XferAbortCallback = NULL; 801252a: 687b ldr r3, [r7, #4] 801252c: 6bdb ldr r3, [r3, #60] @ 0x3c 801252e: 2200 movs r2, #0 8012530: 635a str r2, [r3, #52] @ 0x34 } } /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) 8012532: 687b ldr r3, [r7, #4] 8012534: 681b ldr r3, [r3, #0] 8012536: 695b ldr r3, [r3, #20] 8012538: f003 0380 and.w r3, r3, #128 @ 0x80 801253c: 2b00 cmp r3, #0 801253e: d02d beq.n 801259c { /* Disable DMA Tx at UART level */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8012540: 687b ldr r3, [r7, #4] 8012542: 681b ldr r3, [r3, #0] 8012544: 3314 adds r3, #20 8012546: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012548: 6a7b ldr r3, [r7, #36] @ 0x24 801254a: e853 3f00 ldrex r3, [r3] 801254e: 623b str r3, [r7, #32] return(result); 8012550: 6a3b ldr r3, [r7, #32] 8012552: f023 0380 bic.w r3, r3, #128 @ 0x80 8012556: 677b str r3, [r7, #116] @ 0x74 8012558: 687b ldr r3, [r7, #4] 801255a: 681b ldr r3, [r3, #0] 801255c: 3314 adds r3, #20 801255e: 6f7a ldr r2, [r7, #116] @ 0x74 8012560: 633a str r2, [r7, #48] @ 0x30 8012562: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012564: 6af9 ldr r1, [r7, #44] @ 0x2c 8012566: 6b3a ldr r2, [r7, #48] @ 0x30 8012568: e841 2300 strex r3, r2, [r1] 801256c: 62bb str r3, [r7, #40] @ 0x28 return(result); 801256e: 6abb ldr r3, [r7, #40] @ 0x28 8012570: 2b00 cmp r3, #0 8012572: d1e5 bne.n 8012540 /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) 8012574: 687b ldr r3, [r7, #4] 8012576: 6b9b ldr r3, [r3, #56] @ 0x38 8012578: 2b00 cmp r3, #0 801257a: d00f beq.n 801259c { /* UART Tx DMA Abort callback has already been initialised : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA TX */ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) 801257c: 687b ldr r3, [r7, #4] 801257e: 6b9b ldr r3, [r3, #56] @ 0x38 8012580: 4618 mov r0, r3 8012582: f7fd f8e9 bl 800f758 8012586: 4603 mov r3, r0 8012588: 2b00 cmp r3, #0 801258a: d004 beq.n 8012596 { huart->hdmatx->XferAbortCallback = NULL; 801258c: 687b ldr r3, [r7, #4] 801258e: 6b9b ldr r3, [r3, #56] @ 0x38 8012590: 2200 movs r2, #0 8012592: 635a str r2, [r3, #52] @ 0x34 8012594: e002 b.n 801259c } else { AbortCplt = 0x00U; 8012596: 2300 movs r3, #0 8012598: f8c7 3084 str.w r3, [r7, #132] @ 0x84 } } } /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801259c: 687b ldr r3, [r7, #4] 801259e: 681b ldr r3, [r3, #0] 80125a0: 695b ldr r3, [r3, #20] 80125a2: f003 0340 and.w r3, r3, #64 @ 0x40 80125a6: 2b00 cmp r3, #0 80125a8: d030 beq.n 801260c { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80125aa: 687b ldr r3, [r7, #4] 80125ac: 681b ldr r3, [r3, #0] 80125ae: 3314 adds r3, #20 80125b0: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80125b2: 693b ldr r3, [r7, #16] 80125b4: e853 3f00 ldrex r3, [r3] 80125b8: 60fb str r3, [r7, #12] return(result); 80125ba: 68fb ldr r3, [r7, #12] 80125bc: f023 0340 bic.w r3, r3, #64 @ 0x40 80125c0: 673b str r3, [r7, #112] @ 0x70 80125c2: 687b ldr r3, [r7, #4] 80125c4: 681b ldr r3, [r3, #0] 80125c6: 3314 adds r3, #20 80125c8: 6f3a ldr r2, [r7, #112] @ 0x70 80125ca: 61fa str r2, [r7, #28] 80125cc: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80125ce: 69b9 ldr r1, [r7, #24] 80125d0: 69fa ldr r2, [r7, #28] 80125d2: e841 2300 strex r3, r2, [r1] 80125d6: 617b str r3, [r7, #20] return(result); 80125d8: 697b ldr r3, [r7, #20] 80125da: 2b00 cmp r3, #0 80125dc: d1e5 bne.n 80125aa /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) 80125de: 687b ldr r3, [r7, #4] 80125e0: 6bdb ldr r3, [r3, #60] @ 0x3c 80125e2: 2b00 cmp r3, #0 80125e4: d012 beq.n 801260c { /* UART Rx DMA Abort callback has already been initialised : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 80125e6: 687b ldr r3, [r7, #4] 80125e8: 6bdb ldr r3, [r3, #60] @ 0x3c 80125ea: 4618 mov r0, r3 80125ec: f7fd f8b4 bl 800f758 80125f0: 4603 mov r3, r0 80125f2: 2b00 cmp r3, #0 80125f4: d007 beq.n 8012606 { huart->hdmarx->XferAbortCallback = NULL; 80125f6: 687b ldr r3, [r7, #4] 80125f8: 6bdb ldr r3, [r3, #60] @ 0x3c 80125fa: 2200 movs r2, #0 80125fc: 635a str r2, [r3, #52] @ 0x34 AbortCplt = 0x01U; 80125fe: 2301 movs r3, #1 8012600: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8012604: e002 b.n 801260c } else { AbortCplt = 0x00U; 8012606: 2300 movs r3, #0 8012608: f8c7 3084 str.w r3, [r7, #132] @ 0x84 } } } /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (AbortCplt == 0x01U) 801260c: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8012610: 2b01 cmp r3, #1 8012612: d116 bne.n 8012642 { /* Reset Tx and Rx transfer counters */ huart->TxXferCount = 0x00U; 8012614: 687b ldr r3, [r7, #4] 8012616: 2200 movs r2, #0 8012618: 84da strh r2, [r3, #38] @ 0x26 huart->RxXferCount = 0x00U; 801261a: 687b ldr r3, [r7, #4] 801261c: 2200 movs r2, #0 801261e: 85da strh r2, [r3, #46] @ 0x2e /* Reset ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012620: 687b ldr r3, [r7, #4] 8012622: 2200 movs r2, #0 8012624: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; 8012626: 687b ldr r3, [r7, #4] 8012628: 2220 movs r2, #32 801262a: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 801262e: 687b ldr r3, [r7, #4] 8012630: 2220 movs r2, #32 8012632: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012636: 687b ldr r3, [r7, #4] 8012638: 2200 movs r2, #0 801263a: 631a str r2, [r3, #48] @ 0x30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Abort complete callback */ huart->AbortCpltCallback(huart); #else /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); 801263c: 6878 ldr r0, [r7, #4] 801263e: f000 faa4 bl 8012b8a #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8012642: 2300 movs r3, #0 } 8012644: 4618 mov r0, r3 8012646: 3788 adds r7, #136 @ 0x88 8012648: 46bd mov sp, r7 801264a: bd80 pop {r7, pc} 801264c: 08012dc3 .word 0x08012dc3 8012650: 08012e23 .word 0x08012e23 08012654 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8012654: b580 push {r7, lr} 8012656: b0ba sub sp, #232 @ 0xe8 8012658: af00 add r7, sp, #0 801265a: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 801265c: 687b ldr r3, [r7, #4] 801265e: 681b ldr r3, [r3, #0] 8012660: 681b ldr r3, [r3, #0] 8012662: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8012666: 687b ldr r3, [r7, #4] 8012668: 681b ldr r3, [r3, #0] 801266a: 68db ldr r3, [r3, #12] 801266c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8012670: 687b ldr r3, [r7, #4] 8012672: 681b ldr r3, [r3, #0] 8012674: 695b ldr r3, [r3, #20] 8012676: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 801267a: 2300 movs r3, #0 801267c: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 8012680: 2300 movs r3, #0 8012682: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 8012686: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801268a: f003 030f and.w r3, r3, #15 801268e: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 8012692: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8012696: 2b00 cmp r3, #0 8012698: d10f bne.n 80126ba { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 801269a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801269e: f003 0320 and.w r3, r3, #32 80126a2: 2b00 cmp r3, #0 80126a4: d009 beq.n 80126ba 80126a6: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80126aa: f003 0320 and.w r3, r3, #32 80126ae: 2b00 cmp r3, #0 80126b0: d003 beq.n 80126ba { UART_Receive_IT(huart); 80126b2: 6878 ldr r0, [r7, #4] 80126b4: f000 fc4c bl 8012f50 return; 80126b8: e25b b.n 8012b72 } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 80126ba: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 80126be: 2b00 cmp r3, #0 80126c0: f000 80de beq.w 8012880 80126c4: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80126c8: f003 0301 and.w r3, r3, #1 80126cc: 2b00 cmp r3, #0 80126ce: d106 bne.n 80126de || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 80126d0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80126d4: f403 7390 and.w r3, r3, #288 @ 0x120 80126d8: 2b00 cmp r3, #0 80126da: f000 80d1 beq.w 8012880 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 80126de: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80126e2: f003 0301 and.w r3, r3, #1 80126e6: 2b00 cmp r3, #0 80126e8: d00b beq.n 8012702 80126ea: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80126ee: f403 7380 and.w r3, r3, #256 @ 0x100 80126f2: 2b00 cmp r3, #0 80126f4: d005 beq.n 8012702 { huart->ErrorCode |= HAL_UART_ERROR_PE; 80126f6: 687b ldr r3, [r7, #4] 80126f8: 6c5b ldr r3, [r3, #68] @ 0x44 80126fa: f043 0201 orr.w r2, r3, #1 80126fe: 687b ldr r3, [r7, #4] 8012700: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8012702: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012706: f003 0304 and.w r3, r3, #4 801270a: 2b00 cmp r3, #0 801270c: d00b beq.n 8012726 801270e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8012712: f003 0301 and.w r3, r3, #1 8012716: 2b00 cmp r3, #0 8012718: d005 beq.n 8012726 { huart->ErrorCode |= HAL_UART_ERROR_NE; 801271a: 687b ldr r3, [r7, #4] 801271c: 6c5b ldr r3, [r3, #68] @ 0x44 801271e: f043 0202 orr.w r2, r3, #2 8012722: 687b ldr r3, [r7, #4] 8012724: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8012726: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801272a: f003 0302 and.w r3, r3, #2 801272e: 2b00 cmp r3, #0 8012730: d00b beq.n 801274a 8012732: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8012736: f003 0301 and.w r3, r3, #1 801273a: 2b00 cmp r3, #0 801273c: d005 beq.n 801274a { huart->ErrorCode |= HAL_UART_ERROR_FE; 801273e: 687b ldr r3, [r7, #4] 8012740: 6c5b ldr r3, [r3, #68] @ 0x44 8012742: f043 0204 orr.w r2, r3, #4 8012746: 687b ldr r3, [r7, #4] 8012748: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 801274a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801274e: f003 0308 and.w r3, r3, #8 8012752: 2b00 cmp r3, #0 8012754: d011 beq.n 801277a 8012756: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801275a: f003 0320 and.w r3, r3, #32 801275e: 2b00 cmp r3, #0 8012760: d105 bne.n 801276e || ((cr3its & USART_CR3_EIE) != RESET))) 8012762: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8012766: f003 0301 and.w r3, r3, #1 801276a: 2b00 cmp r3, #0 801276c: d005 beq.n 801277a { huart->ErrorCode |= HAL_UART_ERROR_ORE; 801276e: 687b ldr r3, [r7, #4] 8012770: 6c5b ldr r3, [r3, #68] @ 0x44 8012772: f043 0208 orr.w r2, r3, #8 8012776: 687b ldr r3, [r7, #4] 8012778: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 801277a: 687b ldr r3, [r7, #4] 801277c: 6c5b ldr r3, [r3, #68] @ 0x44 801277e: 2b00 cmp r3, #0 8012780: f000 81f2 beq.w 8012b68 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8012784: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012788: f003 0320 and.w r3, r3, #32 801278c: 2b00 cmp r3, #0 801278e: d008 beq.n 80127a2 8012790: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8012794: f003 0320 and.w r3, r3, #32 8012798: 2b00 cmp r3, #0 801279a: d002 beq.n 80127a2 { UART_Receive_IT(huart); 801279c: 6878 ldr r0, [r7, #4] 801279e: f000 fbd7 bl 8012f50 } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 80127a2: 687b ldr r3, [r7, #4] 80127a4: 681b ldr r3, [r3, #0] 80127a6: 695b ldr r3, [r3, #20] 80127a8: f003 0340 and.w r3, r3, #64 @ 0x40 80127ac: 2b00 cmp r3, #0 80127ae: bf14 ite ne 80127b0: 2301 movne r3, #1 80127b2: 2300 moveq r3, #0 80127b4: b2db uxtb r3, r3 80127b6: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 80127ba: 687b ldr r3, [r7, #4] 80127bc: 6c5b ldr r3, [r3, #68] @ 0x44 80127be: f003 0308 and.w r3, r3, #8 80127c2: 2b00 cmp r3, #0 80127c4: d103 bne.n 80127ce 80127c6: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 80127ca: 2b00 cmp r3, #0 80127cc: d04f beq.n 801286e { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 80127ce: 6878 ldr r0, [r7, #4] 80127d0: f000 fa81 bl 8012cd6 /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80127d4: 687b ldr r3, [r7, #4] 80127d6: 681b ldr r3, [r3, #0] 80127d8: 695b ldr r3, [r3, #20] 80127da: f003 0340 and.w r3, r3, #64 @ 0x40 80127de: 2b00 cmp r3, #0 80127e0: d041 beq.n 8012866 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80127e2: 687b ldr r3, [r7, #4] 80127e4: 681b ldr r3, [r3, #0] 80127e6: 3314 adds r3, #20 80127e8: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80127ec: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 80127f0: e853 3f00 ldrex r3, [r3] 80127f4: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 80127f8: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 80127fc: f023 0340 bic.w r3, r3, #64 @ 0x40 8012800: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8012804: 687b ldr r3, [r7, #4] 8012806: 681b ldr r3, [r3, #0] 8012808: 3314 adds r3, #20 801280a: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 801280e: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 8012812: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012816: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 801281a: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 801281e: e841 2300 strex r3, r2, [r1] 8012822: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8012826: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 801282a: 2b00 cmp r3, #0 801282c: d1d9 bne.n 80127e2 /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 801282e: 687b ldr r3, [r7, #4] 8012830: 6bdb ldr r3, [r3, #60] @ 0x3c 8012832: 2b00 cmp r3, #0 8012834: d013 beq.n 801285e { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8012836: 687b ldr r3, [r7, #4] 8012838: 6bdb ldr r3, [r3, #60] @ 0x3c 801283a: 4a7e ldr r2, [pc, #504] @ (8012a34 ) 801283c: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 801283e: 687b ldr r3, [r7, #4] 8012840: 6bdb ldr r3, [r3, #60] @ 0x3c 8012842: 4618 mov r0, r3 8012844: f7fc ff88 bl 800f758 8012848: 4603 mov r3, r0 801284a: 2b00 cmp r3, #0 801284c: d016 beq.n 801287c { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 801284e: 687b ldr r3, [r7, #4] 8012850: 6bdb ldr r3, [r3, #60] @ 0x3c 8012852: 6b5b ldr r3, [r3, #52] @ 0x34 8012854: 687a ldr r2, [r7, #4] 8012856: 6bd2 ldr r2, [r2, #60] @ 0x3c 8012858: 4610 mov r0, r2 801285a: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801285c: e00e b.n 801287c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 801285e: 6878 ldr r0, [r7, #4] 8012860: f7f9 ffd4 bl 800c80c if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8012864: e00a b.n 801287c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8012866: 6878 ldr r0, [r7, #4] 8012868: f7f9 ffd0 bl 800c80c if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801286c: e006 b.n 801287c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 801286e: 6878 ldr r0, [r7, #4] 8012870: f7f9 ffcc bl 800c80c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012874: 687b ldr r3, [r7, #4] 8012876: 2200 movs r2, #0 8012878: 645a str r2, [r3, #68] @ 0x44 } } return; 801287a: e175 b.n 8012b68 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801287c: bf00 nop return; 801287e: e173 b.n 8012b68 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012880: 687b ldr r3, [r7, #4] 8012882: 6b1b ldr r3, [r3, #48] @ 0x30 8012884: 2b01 cmp r3, #1 8012886: f040 814f bne.w 8012b28 && ((isrflags & USART_SR_IDLE) != 0U) 801288a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801288e: f003 0310 and.w r3, r3, #16 8012892: 2b00 cmp r3, #0 8012894: f000 8148 beq.w 8012b28 && ((cr1its & USART_SR_IDLE) != 0U)) 8012898: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801289c: f003 0310 and.w r3, r3, #16 80128a0: 2b00 cmp r3, #0 80128a2: f000 8141 beq.w 8012b28 { __HAL_UART_CLEAR_IDLEFLAG(huart); 80128a6: 2300 movs r3, #0 80128a8: 60bb str r3, [r7, #8] 80128aa: 687b ldr r3, [r7, #4] 80128ac: 681b ldr r3, [r3, #0] 80128ae: 681b ldr r3, [r3, #0] 80128b0: 60bb str r3, [r7, #8] 80128b2: 687b ldr r3, [r7, #4] 80128b4: 681b ldr r3, [r3, #0] 80128b6: 685b ldr r3, [r3, #4] 80128b8: 60bb str r3, [r7, #8] 80128ba: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80128bc: 687b ldr r3, [r7, #4] 80128be: 681b ldr r3, [r3, #0] 80128c0: 695b ldr r3, [r3, #20] 80128c2: f003 0340 and.w r3, r3, #64 @ 0x40 80128c6: 2b00 cmp r3, #0 80128c8: f000 80b6 beq.w 8012a38 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 80128cc: 687b ldr r3, [r7, #4] 80128ce: 6bdb ldr r3, [r3, #60] @ 0x3c 80128d0: 681b ldr r3, [r3, #0] 80128d2: 685b ldr r3, [r3, #4] 80128d4: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 80128d8: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 80128dc: 2b00 cmp r3, #0 80128de: f000 8145 beq.w 8012b6c && (nb_remaining_rx_data < huart->RxXferSize)) 80128e2: 687b ldr r3, [r7, #4] 80128e4: 8d9b ldrh r3, [r3, #44] @ 0x2c 80128e6: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80128ea: 429a cmp r2, r3 80128ec: f080 813e bcs.w 8012b6c { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 80128f0: 687b ldr r3, [r7, #4] 80128f2: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80128f6: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 80128f8: 687b ldr r3, [r7, #4] 80128fa: 6bdb ldr r3, [r3, #60] @ 0x3c 80128fc: 699b ldr r3, [r3, #24] 80128fe: 2b20 cmp r3, #32 8012900: f000 8088 beq.w 8012a14 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8012904: 687b ldr r3, [r7, #4] 8012906: 681b ldr r3, [r3, #0] 8012908: 330c adds r3, #12 801290a: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801290e: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8012912: e853 3f00 ldrex r3, [r3] 8012916: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 801291a: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 801291e: f423 7380 bic.w r3, r3, #256 @ 0x100 8012922: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8012926: 687b ldr r3, [r7, #4] 8012928: 681b ldr r3, [r3, #0] 801292a: 330c adds r3, #12 801292c: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 8012930: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8012934: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012938: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 801293c: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8012940: e841 2300 strex r3, r2, [r1] 8012944: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8012948: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 801294c: 2b00 cmp r3, #0 801294e: d1d9 bne.n 8012904 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012950: 687b ldr r3, [r7, #4] 8012952: 681b ldr r3, [r3, #0] 8012954: 3314 adds r3, #20 8012956: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012958: 6f7b ldr r3, [r7, #116] @ 0x74 801295a: e853 3f00 ldrex r3, [r3] 801295e: 673b str r3, [r7, #112] @ 0x70 return(result); 8012960: 6f3b ldr r3, [r7, #112] @ 0x70 8012962: f023 0301 bic.w r3, r3, #1 8012966: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 801296a: 687b ldr r3, [r7, #4] 801296c: 681b ldr r3, [r3, #0] 801296e: 3314 adds r3, #20 8012970: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8012974: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8012978: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801297a: 6ff9 ldr r1, [r7, #124] @ 0x7c 801297c: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8012980: e841 2300 strex r3, r2, [r1] 8012984: 67bb str r3, [r7, #120] @ 0x78 return(result); 8012986: 6fbb ldr r3, [r7, #120] @ 0x78 8012988: 2b00 cmp r3, #0 801298a: d1e1 bne.n 8012950 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 801298c: 687b ldr r3, [r7, #4] 801298e: 681b ldr r3, [r3, #0] 8012990: 3314 adds r3, #20 8012992: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012994: 6e3b ldr r3, [r7, #96] @ 0x60 8012996: e853 3f00 ldrex r3, [r3] 801299a: 65fb str r3, [r7, #92] @ 0x5c return(result); 801299c: 6dfb ldr r3, [r7, #92] @ 0x5c 801299e: f023 0340 bic.w r3, r3, #64 @ 0x40 80129a2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 80129a6: 687b ldr r3, [r7, #4] 80129a8: 681b ldr r3, [r3, #0] 80129aa: 3314 adds r3, #20 80129ac: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 80129b0: 66fa str r2, [r7, #108] @ 0x6c 80129b2: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80129b4: 6eb9 ldr r1, [r7, #104] @ 0x68 80129b6: 6efa ldr r2, [r7, #108] @ 0x6c 80129b8: e841 2300 strex r3, r2, [r1] 80129bc: 667b str r3, [r7, #100] @ 0x64 return(result); 80129be: 6e7b ldr r3, [r7, #100] @ 0x64 80129c0: 2b00 cmp r3, #0 80129c2: d1e3 bne.n 801298c /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80129c4: 687b ldr r3, [r7, #4] 80129c6: 2220 movs r2, #32 80129c8: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80129cc: 687b ldr r3, [r7, #4] 80129ce: 2200 movs r2, #0 80129d0: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80129d2: 687b ldr r3, [r7, #4] 80129d4: 681b ldr r3, [r3, #0] 80129d6: 330c adds r3, #12 80129d8: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80129da: 6cfb ldr r3, [r7, #76] @ 0x4c 80129dc: e853 3f00 ldrex r3, [r3] 80129e0: 64bb str r3, [r7, #72] @ 0x48 return(result); 80129e2: 6cbb ldr r3, [r7, #72] @ 0x48 80129e4: f023 0310 bic.w r3, r3, #16 80129e8: f8c7 30ac str.w r3, [r7, #172] @ 0xac 80129ec: 687b ldr r3, [r7, #4] 80129ee: 681b ldr r3, [r3, #0] 80129f0: 330c adds r3, #12 80129f2: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 80129f6: 65ba str r2, [r7, #88] @ 0x58 80129f8: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80129fa: 6d79 ldr r1, [r7, #84] @ 0x54 80129fc: 6dba ldr r2, [r7, #88] @ 0x58 80129fe: e841 2300 strex r3, r2, [r1] 8012a02: 653b str r3, [r7, #80] @ 0x50 return(result); 8012a04: 6d3b ldr r3, [r7, #80] @ 0x50 8012a06: 2b00 cmp r3, #0 8012a08: d1e3 bne.n 80129d2 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8012a0a: 687b ldr r3, [r7, #4] 8012a0c: 6bdb ldr r3, [r3, #60] @ 0x3c 8012a0e: 4618 mov r0, r3 8012a10: f7fc fe67 bl 800f6e2 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8012a14: 687b ldr r3, [r7, #4] 8012a16: 2202 movs r2, #2 8012a18: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8012a1a: 687b ldr r3, [r7, #4] 8012a1c: 8d9a ldrh r2, [r3, #44] @ 0x2c 8012a1e: 687b ldr r3, [r7, #4] 8012a20: 8ddb ldrh r3, [r3, #46] @ 0x2e 8012a22: b29b uxth r3, r3 8012a24: 1ad3 subs r3, r2, r3 8012a26: b29b uxth r3, r3 8012a28: 4619 mov r1, r3 8012a2a: 6878 ldr r0, [r7, #4] 8012a2c: f7f9 fe9e bl 800c76c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8012a30: e09c b.n 8012b6c 8012a32: bf00 nop 8012a34: 08012d9b .word 0x08012d9b else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8012a38: 687b ldr r3, [r7, #4] 8012a3a: 8d9a ldrh r2, [r3, #44] @ 0x2c 8012a3c: 687b ldr r3, [r7, #4] 8012a3e: 8ddb ldrh r3, [r3, #46] @ 0x2e 8012a40: b29b uxth r3, r3 8012a42: 1ad3 subs r3, r2, r3 8012a44: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8012a48: 687b ldr r3, [r7, #4] 8012a4a: 8ddb ldrh r3, [r3, #46] @ 0x2e 8012a4c: b29b uxth r3, r3 8012a4e: 2b00 cmp r3, #0 8012a50: f000 808e beq.w 8012b70 && (nb_rx_data > 0U)) 8012a54: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8012a58: 2b00 cmp r3, #0 8012a5a: f000 8089 beq.w 8012b70 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8012a5e: 687b ldr r3, [r7, #4] 8012a60: 681b ldr r3, [r3, #0] 8012a62: 330c adds r3, #12 8012a64: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012a66: 6bbb ldr r3, [r7, #56] @ 0x38 8012a68: e853 3f00 ldrex r3, [r3] 8012a6c: 637b str r3, [r7, #52] @ 0x34 return(result); 8012a6e: 6b7b ldr r3, [r7, #52] @ 0x34 8012a70: f423 7390 bic.w r3, r3, #288 @ 0x120 8012a74: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8012a78: 687b ldr r3, [r7, #4] 8012a7a: 681b ldr r3, [r3, #0] 8012a7c: 330c adds r3, #12 8012a7e: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 8012a82: 647a str r2, [r7, #68] @ 0x44 8012a84: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012a86: 6c39 ldr r1, [r7, #64] @ 0x40 8012a88: 6c7a ldr r2, [r7, #68] @ 0x44 8012a8a: e841 2300 strex r3, r2, [r1] 8012a8e: 63fb str r3, [r7, #60] @ 0x3c return(result); 8012a90: 6bfb ldr r3, [r7, #60] @ 0x3c 8012a92: 2b00 cmp r3, #0 8012a94: d1e3 bne.n 8012a5e /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012a96: 687b ldr r3, [r7, #4] 8012a98: 681b ldr r3, [r3, #0] 8012a9a: 3314 adds r3, #20 8012a9c: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012a9e: 6a7b ldr r3, [r7, #36] @ 0x24 8012aa0: e853 3f00 ldrex r3, [r3] 8012aa4: 623b str r3, [r7, #32] return(result); 8012aa6: 6a3b ldr r3, [r7, #32] 8012aa8: f023 0301 bic.w r3, r3, #1 8012aac: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8012ab0: 687b ldr r3, [r7, #4] 8012ab2: 681b ldr r3, [r3, #0] 8012ab4: 3314 adds r3, #20 8012ab6: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 8012aba: 633a str r2, [r7, #48] @ 0x30 8012abc: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012abe: 6af9 ldr r1, [r7, #44] @ 0x2c 8012ac0: 6b3a ldr r2, [r7, #48] @ 0x30 8012ac2: e841 2300 strex r3, r2, [r1] 8012ac6: 62bb str r3, [r7, #40] @ 0x28 return(result); 8012ac8: 6abb ldr r3, [r7, #40] @ 0x28 8012aca: 2b00 cmp r3, #0 8012acc: d1e3 bne.n 8012a96 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012ace: 687b ldr r3, [r7, #4] 8012ad0: 2220 movs r2, #32 8012ad2: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012ad6: 687b ldr r3, [r7, #4] 8012ad8: 2200 movs r2, #0 8012ada: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012adc: 687b ldr r3, [r7, #4] 8012ade: 681b ldr r3, [r3, #0] 8012ae0: 330c adds r3, #12 8012ae2: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012ae4: 693b ldr r3, [r7, #16] 8012ae6: e853 3f00 ldrex r3, [r3] 8012aea: 60fb str r3, [r7, #12] return(result); 8012aec: 68fb ldr r3, [r7, #12] 8012aee: f023 0310 bic.w r3, r3, #16 8012af2: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8012af6: 687b ldr r3, [r7, #4] 8012af8: 681b ldr r3, [r3, #0] 8012afa: 330c adds r3, #12 8012afc: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 8012b00: 61fa str r2, [r7, #28] 8012b02: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012b04: 69b9 ldr r1, [r7, #24] 8012b06: 69fa ldr r2, [r7, #28] 8012b08: e841 2300 strex r3, r2, [r1] 8012b0c: 617b str r3, [r7, #20] return(result); 8012b0e: 697b ldr r3, [r7, #20] 8012b10: 2b00 cmp r3, #0 8012b12: d1e3 bne.n 8012adc /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8012b14: 687b ldr r3, [r7, #4] 8012b16: 2202 movs r2, #2 8012b18: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8012b1a: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8012b1e: 4619 mov r1, r3 8012b20: 6878 ldr r0, [r7, #4] 8012b22: f7f9 fe23 bl 800c76c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8012b26: e023 b.n 8012b70 } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8012b28: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012b2c: f003 0380 and.w r3, r3, #128 @ 0x80 8012b30: 2b00 cmp r3, #0 8012b32: d009 beq.n 8012b48 8012b34: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8012b38: f003 0380 and.w r3, r3, #128 @ 0x80 8012b3c: 2b00 cmp r3, #0 8012b3e: d003 beq.n 8012b48 { UART_Transmit_IT(huart); 8012b40: 6878 ldr r0, [r7, #4] 8012b42: f000 f99e bl 8012e82 return; 8012b46: e014 b.n 8012b72 } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8012b48: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8012b4c: f003 0340 and.w r3, r3, #64 @ 0x40 8012b50: 2b00 cmp r3, #0 8012b52: d00e beq.n 8012b72 8012b54: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8012b58: f003 0340 and.w r3, r3, #64 @ 0x40 8012b5c: 2b00 cmp r3, #0 8012b5e: d008 beq.n 8012b72 { UART_EndTransmit_IT(huart); 8012b60: 6878 ldr r0, [r7, #4] 8012b62: f000 f9dd bl 8012f20 return; 8012b66: e004 b.n 8012b72 return; 8012b68: bf00 nop 8012b6a: e002 b.n 8012b72 return; 8012b6c: bf00 nop 8012b6e: e000 b.n 8012b72 return; 8012b70: bf00 nop } } 8012b72: 37e8 adds r7, #232 @ 0xe8 8012b74: 46bd mov sp, r7 8012b76: bd80 pop {r7, pc} 08012b78 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8012b78: b480 push {r7} 8012b7a: b083 sub sp, #12 8012b7c: af00 add r7, sp, #0 8012b7e: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback could be implemented in the user file */ } 8012b80: bf00 nop 8012b82: 370c adds r7, #12 8012b84: 46bd mov sp, r7 8012b86: bc80 pop {r7} 8012b88: 4770 bx lr 08012b8a : * @brief UART Abort Complete callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) { 8012b8a: b480 push {r7} 8012b8c: b083 sub sp, #12 8012b8e: af00 add r7, sp, #0 8012b90: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_AbortCpltCallback can be implemented in the user file. */ } 8012b92: bf00 nop 8012b94: 370c adds r7, #12 8012b96: 46bd mov sp, r7 8012b98: bc80 pop {r7} 8012b9a: 4770 bx lr 08012b9c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART. * @retval UART Error Code */ uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) { 8012b9c: b480 push {r7} 8012b9e: b083 sub sp, #12 8012ba0: af00 add r7, sp, #0 8012ba2: 6078 str r0, [r7, #4] return huart->ErrorCode; 8012ba4: 687b ldr r3, [r7, #4] 8012ba6: 6c5b ldr r3, [r3, #68] @ 0x44 } 8012ba8: 4618 mov r0, r3 8012baa: 370c adds r7, #12 8012bac: 46bd mov sp, r7 8012bae: bc80 pop {r7} 8012bb0: 4770 bx lr 08012bb2 : * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8012bb2: b580 push {r7, lr} 8012bb4: b086 sub sp, #24 8012bb6: af00 add r7, sp, #0 8012bb8: 60f8 str r0, [r7, #12] 8012bba: 60b9 str r1, [r7, #8] 8012bbc: 603b str r3, [r7, #0] 8012bbe: 4613 mov r3, r2 8012bc0: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8012bc2: e03b b.n 8012c3c { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8012bc4: 6a3b ldr r3, [r7, #32] 8012bc6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8012bca: d037 beq.n 8012c3c { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8012bcc: f7fb f856 bl 800dc7c 8012bd0: 4602 mov r2, r0 8012bd2: 683b ldr r3, [r7, #0] 8012bd4: 1ad3 subs r3, r2, r3 8012bd6: 6a3a ldr r2, [r7, #32] 8012bd8: 429a cmp r2, r3 8012bda: d302 bcc.n 8012be2 8012bdc: 6a3b ldr r3, [r7, #32] 8012bde: 2b00 cmp r3, #0 8012be0: d101 bne.n 8012be6 { return HAL_TIMEOUT; 8012be2: 2303 movs r3, #3 8012be4: e03a b.n 8012c5c } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 8012be6: 68fb ldr r3, [r7, #12] 8012be8: 681b ldr r3, [r3, #0] 8012bea: 68db ldr r3, [r3, #12] 8012bec: f003 0304 and.w r3, r3, #4 8012bf0: 2b00 cmp r3, #0 8012bf2: d023 beq.n 8012c3c 8012bf4: 68bb ldr r3, [r7, #8] 8012bf6: 2b80 cmp r3, #128 @ 0x80 8012bf8: d020 beq.n 8012c3c 8012bfa: 68bb ldr r3, [r7, #8] 8012bfc: 2b40 cmp r3, #64 @ 0x40 8012bfe: d01d beq.n 8012c3c { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8012c00: 68fb ldr r3, [r7, #12] 8012c02: 681b ldr r3, [r3, #0] 8012c04: 681b ldr r3, [r3, #0] 8012c06: f003 0308 and.w r3, r3, #8 8012c0a: 2b08 cmp r3, #8 8012c0c: d116 bne.n 8012c3c { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_OREFLAG(huart); 8012c0e: 2300 movs r3, #0 8012c10: 617b str r3, [r7, #20] 8012c12: 68fb ldr r3, [r7, #12] 8012c14: 681b ldr r3, [r3, #0] 8012c16: 681b ldr r3, [r3, #0] 8012c18: 617b str r3, [r7, #20] 8012c1a: 68fb ldr r3, [r7, #12] 8012c1c: 681b ldr r3, [r3, #0] 8012c1e: 685b ldr r3, [r3, #4] 8012c20: 617b str r3, [r7, #20] 8012c22: 697b ldr r3, [r7, #20] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8012c24: 68f8 ldr r0, [r7, #12] 8012c26: f000 f856 bl 8012cd6 huart->ErrorCode = HAL_UART_ERROR_ORE; 8012c2a: 68fb ldr r3, [r7, #12] 8012c2c: 2208 movs r2, #8 8012c2e: 645a str r2, [r3, #68] @ 0x44 /* Process Unlocked */ __HAL_UNLOCK(huart); 8012c30: 68fb ldr r3, [r7, #12] 8012c32: 2200 movs r2, #0 8012c34: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_ERROR; 8012c38: 2301 movs r3, #1 8012c3a: e00f b.n 8012c5c while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8012c3c: 68fb ldr r3, [r7, #12] 8012c3e: 681b ldr r3, [r3, #0] 8012c40: 681a ldr r2, [r3, #0] 8012c42: 68bb ldr r3, [r7, #8] 8012c44: 4013 ands r3, r2 8012c46: 68ba ldr r2, [r7, #8] 8012c48: 429a cmp r2, r3 8012c4a: bf0c ite eq 8012c4c: 2301 moveq r3, #1 8012c4e: 2300 movne r3, #0 8012c50: b2db uxtb r3, r3 8012c52: 461a mov r2, r3 8012c54: 79fb ldrb r3, [r7, #7] 8012c56: 429a cmp r2, r3 8012c58: d0b4 beq.n 8012bc4 } } } } return HAL_OK; 8012c5a: 2300 movs r3, #0 } 8012c5c: 4618 mov r0, r3 8012c5e: 3718 adds r7, #24 8012c60: 46bd mov sp, r7 8012c62: bd80 pop {r7, pc} 08012c64 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8012c64: b480 push {r7} 8012c66: b085 sub sp, #20 8012c68: af00 add r7, sp, #0 8012c6a: 60f8 str r0, [r7, #12] 8012c6c: 60b9 str r1, [r7, #8] 8012c6e: 4613 mov r3, r2 8012c70: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 8012c72: 68fb ldr r3, [r7, #12] 8012c74: 68ba ldr r2, [r7, #8] 8012c76: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 8012c78: 68fb ldr r3, [r7, #12] 8012c7a: 88fa ldrh r2, [r7, #6] 8012c7c: 859a strh r2, [r3, #44] @ 0x2c huart->RxXferCount = Size; 8012c7e: 68fb ldr r3, [r7, #12] 8012c80: 88fa ldrh r2, [r7, #6] 8012c82: 85da strh r2, [r3, #46] @ 0x2e huart->ErrorCode = HAL_UART_ERROR_NONE; 8012c84: 68fb ldr r3, [r7, #12] 8012c86: 2200 movs r2, #0 8012c88: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 8012c8a: 68fb ldr r3, [r7, #12] 8012c8c: 2222 movs r2, #34 @ 0x22 8012c8e: f883 2042 strb.w r2, [r3, #66] @ 0x42 if (huart->Init.Parity != UART_PARITY_NONE) 8012c92: 68fb ldr r3, [r7, #12] 8012c94: 691b ldr r3, [r3, #16] 8012c96: 2b00 cmp r3, #0 8012c98: d007 beq.n 8012caa { /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); 8012c9a: 68fb ldr r3, [r7, #12] 8012c9c: 681b ldr r3, [r3, #0] 8012c9e: 68da ldr r2, [r3, #12] 8012ca0: 68fb ldr r3, [r7, #12] 8012ca2: 681b ldr r3, [r3, #0] 8012ca4: f442 7280 orr.w r2, r2, #256 @ 0x100 8012ca8: 60da str r2, [r3, #12] } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); 8012caa: 68fb ldr r3, [r7, #12] 8012cac: 681b ldr r3, [r3, #0] 8012cae: 695a ldr r2, [r3, #20] 8012cb0: 68fb ldr r3, [r7, #12] 8012cb2: 681b ldr r3, [r3, #0] 8012cb4: f042 0201 orr.w r2, r2, #1 8012cb8: 615a str r2, [r3, #20] /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); 8012cba: 68fb ldr r3, [r7, #12] 8012cbc: 681b ldr r3, [r3, #0] 8012cbe: 68da ldr r2, [r3, #12] 8012cc0: 68fb ldr r3, [r7, #12] 8012cc2: 681b ldr r3, [r3, #0] 8012cc4: f042 0220 orr.w r2, r2, #32 8012cc8: 60da str r2, [r3, #12] return HAL_OK; 8012cca: 2300 movs r3, #0 } 8012ccc: 4618 mov r0, r3 8012cce: 3714 adds r7, #20 8012cd0: 46bd mov sp, r7 8012cd2: bc80 pop {r7} 8012cd4: 4770 bx lr 08012cd6 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8012cd6: b480 push {r7} 8012cd8: b095 sub sp, #84 @ 0x54 8012cda: af00 add r7, sp, #0 8012cdc: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8012cde: 687b ldr r3, [r7, #4] 8012ce0: 681b ldr r3, [r3, #0] 8012ce2: 330c adds r3, #12 8012ce4: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012ce6: 6b7b ldr r3, [r7, #52] @ 0x34 8012ce8: e853 3f00 ldrex r3, [r3] 8012cec: 633b str r3, [r7, #48] @ 0x30 return(result); 8012cee: 6b3b ldr r3, [r7, #48] @ 0x30 8012cf0: f423 7390 bic.w r3, r3, #288 @ 0x120 8012cf4: 64fb str r3, [r7, #76] @ 0x4c 8012cf6: 687b ldr r3, [r7, #4] 8012cf8: 681b ldr r3, [r3, #0] 8012cfa: 330c adds r3, #12 8012cfc: 6cfa ldr r2, [r7, #76] @ 0x4c 8012cfe: 643a str r2, [r7, #64] @ 0x40 8012d00: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012d02: 6bf9 ldr r1, [r7, #60] @ 0x3c 8012d04: 6c3a ldr r2, [r7, #64] @ 0x40 8012d06: e841 2300 strex r3, r2, [r1] 8012d0a: 63bb str r3, [r7, #56] @ 0x38 return(result); 8012d0c: 6bbb ldr r3, [r7, #56] @ 0x38 8012d0e: 2b00 cmp r3, #0 8012d10: d1e5 bne.n 8012cde ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012d12: 687b ldr r3, [r7, #4] 8012d14: 681b ldr r3, [r3, #0] 8012d16: 3314 adds r3, #20 8012d18: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012d1a: 6a3b ldr r3, [r7, #32] 8012d1c: e853 3f00 ldrex r3, [r3] 8012d20: 61fb str r3, [r7, #28] return(result); 8012d22: 69fb ldr r3, [r7, #28] 8012d24: f023 0301 bic.w r3, r3, #1 8012d28: 64bb str r3, [r7, #72] @ 0x48 8012d2a: 687b ldr r3, [r7, #4] 8012d2c: 681b ldr r3, [r3, #0] 8012d2e: 3314 adds r3, #20 8012d30: 6cba ldr r2, [r7, #72] @ 0x48 8012d32: 62fa str r2, [r7, #44] @ 0x2c 8012d34: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012d36: 6ab9 ldr r1, [r7, #40] @ 0x28 8012d38: 6afa ldr r2, [r7, #44] @ 0x2c 8012d3a: e841 2300 strex r3, r2, [r1] 8012d3e: 627b str r3, [r7, #36] @ 0x24 return(result); 8012d40: 6a7b ldr r3, [r7, #36] @ 0x24 8012d42: 2b00 cmp r3, #0 8012d44: d1e5 bne.n 8012d12 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012d46: 687b ldr r3, [r7, #4] 8012d48: 6b1b ldr r3, [r3, #48] @ 0x30 8012d4a: 2b01 cmp r3, #1 8012d4c: d119 bne.n 8012d82 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012d4e: 687b ldr r3, [r7, #4] 8012d50: 681b ldr r3, [r3, #0] 8012d52: 330c adds r3, #12 8012d54: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012d56: 68fb ldr r3, [r7, #12] 8012d58: e853 3f00 ldrex r3, [r3] 8012d5c: 60bb str r3, [r7, #8] return(result); 8012d5e: 68bb ldr r3, [r7, #8] 8012d60: f023 0310 bic.w r3, r3, #16 8012d64: 647b str r3, [r7, #68] @ 0x44 8012d66: 687b ldr r3, [r7, #4] 8012d68: 681b ldr r3, [r3, #0] 8012d6a: 330c adds r3, #12 8012d6c: 6c7a ldr r2, [r7, #68] @ 0x44 8012d6e: 61ba str r2, [r7, #24] 8012d70: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012d72: 6979 ldr r1, [r7, #20] 8012d74: 69ba ldr r2, [r7, #24] 8012d76: e841 2300 strex r3, r2, [r1] 8012d7a: 613b str r3, [r7, #16] return(result); 8012d7c: 693b ldr r3, [r7, #16] 8012d7e: 2b00 cmp r3, #0 8012d80: d1e5 bne.n 8012d4e } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012d82: 687b ldr r3, [r7, #4] 8012d84: 2220 movs r2, #32 8012d86: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012d8a: 687b ldr r3, [r7, #4] 8012d8c: 2200 movs r2, #0 8012d8e: 631a str r2, [r3, #48] @ 0x30 } 8012d90: bf00 nop 8012d92: 3754 adds r7, #84 @ 0x54 8012d94: 46bd mov sp, r7 8012d96: bc80 pop {r7} 8012d98: 4770 bx lr 08012d9a : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8012d9a: b580 push {r7, lr} 8012d9c: b084 sub sp, #16 8012d9e: af00 add r7, sp, #0 8012da0: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8012da2: 687b ldr r3, [r7, #4] 8012da4: 6a5b ldr r3, [r3, #36] @ 0x24 8012da6: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 8012da8: 68fb ldr r3, [r7, #12] 8012daa: 2200 movs r2, #0 8012dac: 85da strh r2, [r3, #46] @ 0x2e huart->TxXferCount = 0x00U; 8012dae: 68fb ldr r3, [r7, #12] 8012db0: 2200 movs r2, #0 8012db2: 84da strh r2, [r3, #38] @ 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8012db4: 68f8 ldr r0, [r7, #12] 8012db6: f7f9 fd29 bl 800c80c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8012dba: bf00 nop 8012dbc: 3710 adds r7, #16 8012dbe: 46bd mov sp, r7 8012dc0: bd80 pop {r7, pc} 08012dc2 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { 8012dc2: b580 push {r7, lr} 8012dc4: b084 sub sp, #16 8012dc6: af00 add r7, sp, #0 8012dc8: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8012dca: 687b ldr r3, [r7, #4] 8012dcc: 6a5b ldr r3, [r3, #36] @ 0x24 8012dce: 60fb str r3, [r7, #12] huart->hdmatx->XferAbortCallback = NULL; 8012dd0: 68fb ldr r3, [r7, #12] 8012dd2: 6b9b ldr r3, [r3, #56] @ 0x38 8012dd4: 2200 movs r2, #0 8012dd6: 635a str r2, [r3, #52] @ 0x34 /* Check if an Abort process is still ongoing */ if (huart->hdmarx != NULL) 8012dd8: 68fb ldr r3, [r7, #12] 8012dda: 6bdb ldr r3, [r3, #60] @ 0x3c 8012ddc: 2b00 cmp r3, #0 8012dde: d004 beq.n 8012dea { if (huart->hdmarx->XferAbortCallback != NULL) 8012de0: 68fb ldr r3, [r7, #12] 8012de2: 6bdb ldr r3, [r3, #60] @ 0x3c 8012de4: 6b5b ldr r3, [r3, #52] @ 0x34 8012de6: 2b00 cmp r3, #0 8012de8: d117 bne.n 8012e1a return; } } /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ huart->TxXferCount = 0x00U; 8012dea: 68fb ldr r3, [r7, #12] 8012dec: 2200 movs r2, #0 8012dee: 84da strh r2, [r3, #38] @ 0x26 huart->RxXferCount = 0x00U; 8012df0: 68fb ldr r3, [r7, #12] 8012df2: 2200 movs r2, #0 8012df4: 85da strh r2, [r3, #46] @ 0x2e /* Reset ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012df6: 68fb ldr r3, [r7, #12] 8012df8: 2200 movs r2, #0 8012dfa: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; 8012dfc: 68fb ldr r3, [r7, #12] 8012dfe: 2220 movs r2, #32 8012e00: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8012e04: 68fb ldr r3, [r7, #12] 8012e06: 2220 movs r2, #32 8012e08: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012e0c: 68fb ldr r3, [r7, #12] 8012e0e: 2200 movs r2, #0 8012e10: 631a str r2, [r3, #48] @ 0x30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Abort complete callback */ huart->AbortCpltCallback(huart); #else /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); 8012e12: 68f8 ldr r0, [r7, #12] 8012e14: f7ff feb9 bl 8012b8a 8012e18: e000 b.n 8012e1c return; 8012e1a: bf00 nop #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8012e1c: 3710 adds r7, #16 8012e1e: 46bd mov sp, r7 8012e20: bd80 pop {r7, pc} 08012e22 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { 8012e22: b580 push {r7, lr} 8012e24: b084 sub sp, #16 8012e26: af00 add r7, sp, #0 8012e28: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8012e2a: 687b ldr r3, [r7, #4] 8012e2c: 6a5b ldr r3, [r3, #36] @ 0x24 8012e2e: 60fb str r3, [r7, #12] huart->hdmarx->XferAbortCallback = NULL; 8012e30: 68fb ldr r3, [r7, #12] 8012e32: 6bdb ldr r3, [r3, #60] @ 0x3c 8012e34: 2200 movs r2, #0 8012e36: 635a str r2, [r3, #52] @ 0x34 /* Check if an Abort process is still ongoing */ if (huart->hdmatx != NULL) 8012e38: 68fb ldr r3, [r7, #12] 8012e3a: 6b9b ldr r3, [r3, #56] @ 0x38 8012e3c: 2b00 cmp r3, #0 8012e3e: d004 beq.n 8012e4a { if (huart->hdmatx->XferAbortCallback != NULL) 8012e40: 68fb ldr r3, [r7, #12] 8012e42: 6b9b ldr r3, [r3, #56] @ 0x38 8012e44: 6b5b ldr r3, [r3, #52] @ 0x34 8012e46: 2b00 cmp r3, #0 8012e48: d117 bne.n 8012e7a return; } } /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ huart->TxXferCount = 0x00U; 8012e4a: 68fb ldr r3, [r7, #12] 8012e4c: 2200 movs r2, #0 8012e4e: 84da strh r2, [r3, #38] @ 0x26 huart->RxXferCount = 0x00U; 8012e50: 68fb ldr r3, [r7, #12] 8012e52: 2200 movs r2, #0 8012e54: 85da strh r2, [r3, #46] @ 0x2e /* Reset ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012e56: 68fb ldr r3, [r7, #12] 8012e58: 2200 movs r2, #0 8012e5a: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; 8012e5c: 68fb ldr r3, [r7, #12] 8012e5e: 2220 movs r2, #32 8012e60: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8012e64: 68fb ldr r3, [r7, #12] 8012e66: 2220 movs r2, #32 8012e68: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012e6c: 68fb ldr r3, [r7, #12] 8012e6e: 2200 movs r2, #0 8012e70: 631a str r2, [r3, #48] @ 0x30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Abort complete callback */ huart->AbortCpltCallback(huart); #else /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); 8012e72: 68f8 ldr r0, [r7, #12] 8012e74: f7ff fe89 bl 8012b8a 8012e78: e000 b.n 8012e7c return; 8012e7a: bf00 nop #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8012e7c: 3710 adds r7, #16 8012e7e: 46bd mov sp, r7 8012e80: bd80 pop {r7, pc} 08012e82 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 8012e82: b480 push {r7} 8012e84: b085 sub sp, #20 8012e86: af00 add r7, sp, #0 8012e88: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8012e8a: 687b ldr r3, [r7, #4] 8012e8c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8012e90: b2db uxtb r3, r3 8012e92: 2b21 cmp r3, #33 @ 0x21 8012e94: d13e bne.n 8012f14 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012e96: 687b ldr r3, [r7, #4] 8012e98: 689b ldr r3, [r3, #8] 8012e9a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012e9e: d114 bne.n 8012eca 8012ea0: 687b ldr r3, [r7, #4] 8012ea2: 691b ldr r3, [r3, #16] 8012ea4: 2b00 cmp r3, #0 8012ea6: d110 bne.n 8012eca { tmp = (const uint16_t *) huart->pTxBuffPtr; 8012ea8: 687b ldr r3, [r7, #4] 8012eaa: 6a1b ldr r3, [r3, #32] 8012eac: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8012eae: 68fb ldr r3, [r7, #12] 8012eb0: 881b ldrh r3, [r3, #0] 8012eb2: 461a mov r2, r3 8012eb4: 687b ldr r3, [r7, #4] 8012eb6: 681b ldr r3, [r3, #0] 8012eb8: f3c2 0208 ubfx r2, r2, #0, #9 8012ebc: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 8012ebe: 687b ldr r3, [r7, #4] 8012ec0: 6a1b ldr r3, [r3, #32] 8012ec2: 1c9a adds r2, r3, #2 8012ec4: 687b ldr r3, [r7, #4] 8012ec6: 621a str r2, [r3, #32] 8012ec8: e008 b.n 8012edc } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 8012eca: 687b ldr r3, [r7, #4] 8012ecc: 6a1b ldr r3, [r3, #32] 8012ece: 1c59 adds r1, r3, #1 8012ed0: 687a ldr r2, [r7, #4] 8012ed2: 6211 str r1, [r2, #32] 8012ed4: 781a ldrb r2, [r3, #0] 8012ed6: 687b ldr r3, [r7, #4] 8012ed8: 681b ldr r3, [r3, #0] 8012eda: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 8012edc: 687b ldr r3, [r7, #4] 8012ede: 8cdb ldrh r3, [r3, #38] @ 0x26 8012ee0: b29b uxth r3, r3 8012ee2: 3b01 subs r3, #1 8012ee4: b29b uxth r3, r3 8012ee6: 687a ldr r2, [r7, #4] 8012ee8: 4619 mov r1, r3 8012eea: 84d1 strh r1, [r2, #38] @ 0x26 8012eec: 2b00 cmp r3, #0 8012eee: d10f bne.n 8012f10 { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8012ef0: 687b ldr r3, [r7, #4] 8012ef2: 681b ldr r3, [r3, #0] 8012ef4: 68da ldr r2, [r3, #12] 8012ef6: 687b ldr r3, [r7, #4] 8012ef8: 681b ldr r3, [r3, #0] 8012efa: f022 0280 bic.w r2, r2, #128 @ 0x80 8012efe: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 8012f00: 687b ldr r3, [r7, #4] 8012f02: 681b ldr r3, [r3, #0] 8012f04: 68da ldr r2, [r3, #12] 8012f06: 687b ldr r3, [r7, #4] 8012f08: 681b ldr r3, [r3, #0] 8012f0a: f042 0240 orr.w r2, r2, #64 @ 0x40 8012f0e: 60da str r2, [r3, #12] } return HAL_OK; 8012f10: 2300 movs r3, #0 8012f12: e000 b.n 8012f16 } else { return HAL_BUSY; 8012f14: 2302 movs r3, #2 } } 8012f16: 4618 mov r0, r3 8012f18: 3714 adds r7, #20 8012f1a: 46bd mov sp, r7 8012f1c: bc80 pop {r7} 8012f1e: 4770 bx lr 08012f20 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8012f20: b580 push {r7, lr} 8012f22: b082 sub sp, #8 8012f24: af00 add r7, sp, #0 8012f26: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 8012f28: 687b ldr r3, [r7, #4] 8012f2a: 681b ldr r3, [r3, #0] 8012f2c: 68da ldr r2, [r3, #12] 8012f2e: 687b ldr r3, [r7, #4] 8012f30: 681b ldr r3, [r3, #0] 8012f32: f022 0240 bic.w r2, r2, #64 @ 0x40 8012f36: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8012f38: 687b ldr r3, [r7, #4] 8012f3a: 2220 movs r2, #32 8012f3c: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8012f40: 6878 ldr r0, [r7, #4] 8012f42: f7f9 fcad bl 800c8a0 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8012f46: 2300 movs r3, #0 } 8012f48: 4618 mov r0, r3 8012f4a: 3708 adds r7, #8 8012f4c: 46bd mov sp, r7 8012f4e: bd80 pop {r7, pc} 08012f50 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 8012f50: b580 push {r7, lr} 8012f52: b08c sub sp, #48 @ 0x30 8012f54: af00 add r7, sp, #0 8012f56: 6078 str r0, [r7, #4] uint8_t *pdata8bits; uint16_t *pdata16bits; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8012f58: 687b ldr r3, [r7, #4] 8012f5a: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8012f5e: b2db uxtb r3, r3 8012f60: 2b22 cmp r3, #34 @ 0x22 8012f62: f040 80ae bne.w 80130c2 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012f66: 687b ldr r3, [r7, #4] 8012f68: 689b ldr r3, [r3, #8] 8012f6a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012f6e: d117 bne.n 8012fa0 8012f70: 687b ldr r3, [r7, #4] 8012f72: 691b ldr r3, [r3, #16] 8012f74: 2b00 cmp r3, #0 8012f76: d113 bne.n 8012fa0 { pdata8bits = NULL; 8012f78: 2300 movs r3, #0 8012f7a: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = (uint16_t *) huart->pRxBuffPtr; 8012f7c: 687b ldr r3, [r7, #4] 8012f7e: 6a9b ldr r3, [r3, #40] @ 0x28 8012f80: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8012f82: 687b ldr r3, [r7, #4] 8012f84: 681b ldr r3, [r3, #0] 8012f86: 685b ldr r3, [r3, #4] 8012f88: b29b uxth r3, r3 8012f8a: f3c3 0308 ubfx r3, r3, #0, #9 8012f8e: b29a uxth r2, r3 8012f90: 6abb ldr r3, [r7, #40] @ 0x28 8012f92: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8012f94: 687b ldr r3, [r7, #4] 8012f96: 6a9b ldr r3, [r3, #40] @ 0x28 8012f98: 1c9a adds r2, r3, #2 8012f9a: 687b ldr r3, [r7, #4] 8012f9c: 629a str r2, [r3, #40] @ 0x28 8012f9e: e026 b.n 8012fee } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8012fa0: 687b ldr r3, [r7, #4] 8012fa2: 6a9b ldr r3, [r3, #40] @ 0x28 8012fa4: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = NULL; 8012fa6: 2300 movs r3, #0 8012fa8: 62bb str r3, [r7, #40] @ 0x28 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 8012faa: 687b ldr r3, [r7, #4] 8012fac: 689b ldr r3, [r3, #8] 8012fae: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012fb2: d007 beq.n 8012fc4 8012fb4: 687b ldr r3, [r7, #4] 8012fb6: 689b ldr r3, [r3, #8] 8012fb8: 2b00 cmp r3, #0 8012fba: d10a bne.n 8012fd2 8012fbc: 687b ldr r3, [r7, #4] 8012fbe: 691b ldr r3, [r3, #16] 8012fc0: 2b00 cmp r3, #0 8012fc2: d106 bne.n 8012fd2 { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8012fc4: 687b ldr r3, [r7, #4] 8012fc6: 681b ldr r3, [r3, #0] 8012fc8: 685b ldr r3, [r3, #4] 8012fca: b2da uxtb r2, r3 8012fcc: 6afb ldr r3, [r7, #44] @ 0x2c 8012fce: 701a strb r2, [r3, #0] 8012fd0: e008 b.n 8012fe4 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8012fd2: 687b ldr r3, [r7, #4] 8012fd4: 681b ldr r3, [r3, #0] 8012fd6: 685b ldr r3, [r3, #4] 8012fd8: b2db uxtb r3, r3 8012fda: f003 037f and.w r3, r3, #127 @ 0x7f 8012fde: b2da uxtb r2, r3 8012fe0: 6afb ldr r3, [r7, #44] @ 0x2c 8012fe2: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 8012fe4: 687b ldr r3, [r7, #4] 8012fe6: 6a9b ldr r3, [r3, #40] @ 0x28 8012fe8: 1c5a adds r2, r3, #1 8012fea: 687b ldr r3, [r7, #4] 8012fec: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 8012fee: 687b ldr r3, [r7, #4] 8012ff0: 8ddb ldrh r3, [r3, #46] @ 0x2e 8012ff2: b29b uxth r3, r3 8012ff4: 3b01 subs r3, #1 8012ff6: b29b uxth r3, r3 8012ff8: 687a ldr r2, [r7, #4] 8012ffa: 4619 mov r1, r3 8012ffc: 85d1 strh r1, [r2, #46] @ 0x2e 8012ffe: 2b00 cmp r3, #0 8013000: d15d bne.n 80130be { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8013002: 687b ldr r3, [r7, #4] 8013004: 681b ldr r3, [r3, #0] 8013006: 68da ldr r2, [r3, #12] 8013008: 687b ldr r3, [r7, #4] 801300a: 681b ldr r3, [r3, #0] 801300c: f022 0220 bic.w r2, r2, #32 8013010: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8013012: 687b ldr r3, [r7, #4] 8013014: 681b ldr r3, [r3, #0] 8013016: 68da ldr r2, [r3, #12] 8013018: 687b ldr r3, [r7, #4] 801301a: 681b ldr r3, [r3, #0] 801301c: f422 7280 bic.w r2, r2, #256 @ 0x100 8013020: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8013022: 687b ldr r3, [r7, #4] 8013024: 681b ldr r3, [r3, #0] 8013026: 695a ldr r2, [r3, #20] 8013028: 687b ldr r3, [r7, #4] 801302a: 681b ldr r3, [r3, #0] 801302c: f022 0201 bic.w r2, r2, #1 8013030: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013032: 687b ldr r3, [r7, #4] 8013034: 2220 movs r2, #32 8013036: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 801303a: 687b ldr r3, [r7, #4] 801303c: 2200 movs r2, #0 801303e: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013040: 687b ldr r3, [r7, #4] 8013042: 6b1b ldr r3, [r3, #48] @ 0x30 8013044: 2b01 cmp r3, #1 8013046: d135 bne.n 80130b4 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013048: 687b ldr r3, [r7, #4] 801304a: 2200 movs r2, #0 801304c: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801304e: 687b ldr r3, [r7, #4] 8013050: 681b ldr r3, [r3, #0] 8013052: 330c adds r3, #12 8013054: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013056: 697b ldr r3, [r7, #20] 8013058: e853 3f00 ldrex r3, [r3] 801305c: 613b str r3, [r7, #16] return(result); 801305e: 693b ldr r3, [r7, #16] 8013060: f023 0310 bic.w r3, r3, #16 8013064: 627b str r3, [r7, #36] @ 0x24 8013066: 687b ldr r3, [r7, #4] 8013068: 681b ldr r3, [r3, #0] 801306a: 330c adds r3, #12 801306c: 6a7a ldr r2, [r7, #36] @ 0x24 801306e: 623a str r2, [r7, #32] 8013070: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013072: 69f9 ldr r1, [r7, #28] 8013074: 6a3a ldr r2, [r7, #32] 8013076: e841 2300 strex r3, r2, [r1] 801307a: 61bb str r3, [r7, #24] return(result); 801307c: 69bb ldr r3, [r7, #24] 801307e: 2b00 cmp r3, #0 8013080: d1e5 bne.n 801304e /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 8013082: 687b ldr r3, [r7, #4] 8013084: 681b ldr r3, [r3, #0] 8013086: 681b ldr r3, [r3, #0] 8013088: f003 0310 and.w r3, r3, #16 801308c: 2b10 cmp r3, #16 801308e: d10a bne.n 80130a6 { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 8013090: 2300 movs r3, #0 8013092: 60fb str r3, [r7, #12] 8013094: 687b ldr r3, [r7, #4] 8013096: 681b ldr r3, [r3, #0] 8013098: 681b ldr r3, [r3, #0] 801309a: 60fb str r3, [r7, #12] 801309c: 687b ldr r3, [r7, #4] 801309e: 681b ldr r3, [r3, #0] 80130a0: 685b ldr r3, [r3, #4] 80130a2: 60fb str r3, [r7, #12] 80130a4: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 80130a6: 687b ldr r3, [r7, #4] 80130a8: 8d9b ldrh r3, [r3, #44] @ 0x2c 80130aa: 4619 mov r1, r3 80130ac: 6878 ldr r0, [r7, #4] 80130ae: f7f9 fb5d bl 800c76c 80130b2: e002 b.n 80130ba #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 80130b4: 6878 ldr r0, [r7, #4] 80130b6: f7ff fd5f bl 8012b78 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 80130ba: 2300 movs r3, #0 80130bc: e002 b.n 80130c4 } return HAL_OK; 80130be: 2300 movs r3, #0 80130c0: e000 b.n 80130c4 } else { return HAL_BUSY; 80130c2: 2302 movs r3, #2 } } 80130c4: 4618 mov r0, r3 80130c6: 3730 adds r7, #48 @ 0x30 80130c8: 46bd mov sp, r7 80130ca: bd80 pop {r7, pc} 080130cc : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 80130cc: b580 push {r7, lr} 80130ce: b084 sub sp, #16 80130d0: af00 add r7, sp, #0 80130d2: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 80130d4: 687b ldr r3, [r7, #4] 80130d6: 681b ldr r3, [r3, #0] 80130d8: 691b ldr r3, [r3, #16] 80130da: f423 5140 bic.w r1, r3, #12288 @ 0x3000 80130de: 687b ldr r3, [r7, #4] 80130e0: 68da ldr r2, [r3, #12] 80130e2: 687b ldr r3, [r7, #4] 80130e4: 681b ldr r3, [r3, #0] 80130e6: 430a orrs r2, r1 80130e8: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 80130ea: 687b ldr r3, [r7, #4] 80130ec: 689a ldr r2, [r3, #8] 80130ee: 687b ldr r3, [r7, #4] 80130f0: 691b ldr r3, [r3, #16] 80130f2: 431a orrs r2, r3 80130f4: 687b ldr r3, [r7, #4] 80130f6: 695b ldr r3, [r3, #20] 80130f8: 4313 orrs r3, r2 80130fa: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 80130fc: 687b ldr r3, [r7, #4] 80130fe: 681b ldr r3, [r3, #0] 8013100: 68db ldr r3, [r3, #12] 8013102: f423 53b0 bic.w r3, r3, #5632 @ 0x1600 8013106: f023 030c bic.w r3, r3, #12 801310a: 687a ldr r2, [r7, #4] 801310c: 6812 ldr r2, [r2, #0] 801310e: 68b9 ldr r1, [r7, #8] 8013110: 430b orrs r3, r1 8013112: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8013114: 687b ldr r3, [r7, #4] 8013116: 681b ldr r3, [r3, #0] 8013118: 695b ldr r3, [r3, #20] 801311a: f423 7140 bic.w r1, r3, #768 @ 0x300 801311e: 687b ldr r3, [r7, #4] 8013120: 699a ldr r2, [r3, #24] 8013122: 687b ldr r3, [r7, #4] 8013124: 681b ldr r3, [r3, #0] 8013126: 430a orrs r2, r1 8013128: 615a str r2, [r3, #20] if(huart->Instance == USART1) 801312a: 687b ldr r3, [r7, #4] 801312c: 681b ldr r3, [r3, #0] 801312e: 4a2c ldr r2, [pc, #176] @ (80131e0 ) 8013130: 4293 cmp r3, r2 8013132: d103 bne.n 801313c { pclk = HAL_RCC_GetPCLK2Freq(); 8013134: f7fd fb82 bl 801083c 8013138: 60f8 str r0, [r7, #12] 801313a: e002 b.n 8013142 } else { pclk = HAL_RCC_GetPCLK1Freq(); 801313c: f7fd fb6a bl 8010814 8013140: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8013142: 68fa ldr r2, [r7, #12] 8013144: 4613 mov r3, r2 8013146: 009b lsls r3, r3, #2 8013148: 4413 add r3, r2 801314a: 009a lsls r2, r3, #2 801314c: 441a add r2, r3 801314e: 687b ldr r3, [r7, #4] 8013150: 685b ldr r3, [r3, #4] 8013152: 009b lsls r3, r3, #2 8013154: fbb2 f3f3 udiv r3, r2, r3 8013158: 4a22 ldr r2, [pc, #136] @ (80131e4 ) 801315a: fba2 2303 umull r2, r3, r2, r3 801315e: 095b lsrs r3, r3, #5 8013160: 0119 lsls r1, r3, #4 8013162: 68fa ldr r2, [r7, #12] 8013164: 4613 mov r3, r2 8013166: 009b lsls r3, r3, #2 8013168: 4413 add r3, r2 801316a: 009a lsls r2, r3, #2 801316c: 441a add r2, r3 801316e: 687b ldr r3, [r7, #4] 8013170: 685b ldr r3, [r3, #4] 8013172: 009b lsls r3, r3, #2 8013174: fbb2 f2f3 udiv r2, r2, r3 8013178: 4b1a ldr r3, [pc, #104] @ (80131e4 ) 801317a: fba3 0302 umull r0, r3, r3, r2 801317e: 095b lsrs r3, r3, #5 8013180: 2064 movs r0, #100 @ 0x64 8013182: fb00 f303 mul.w r3, r0, r3 8013186: 1ad3 subs r3, r2, r3 8013188: 011b lsls r3, r3, #4 801318a: 3332 adds r3, #50 @ 0x32 801318c: 4a15 ldr r2, [pc, #84] @ (80131e4 ) 801318e: fba2 2303 umull r2, r3, r2, r3 8013192: 095b lsrs r3, r3, #5 8013194: f003 03f0 and.w r3, r3, #240 @ 0xf0 8013198: 4419 add r1, r3 801319a: 68fa ldr r2, [r7, #12] 801319c: 4613 mov r3, r2 801319e: 009b lsls r3, r3, #2 80131a0: 4413 add r3, r2 80131a2: 009a lsls r2, r3, #2 80131a4: 441a add r2, r3 80131a6: 687b ldr r3, [r7, #4] 80131a8: 685b ldr r3, [r3, #4] 80131aa: 009b lsls r3, r3, #2 80131ac: fbb2 f2f3 udiv r2, r2, r3 80131b0: 4b0c ldr r3, [pc, #48] @ (80131e4 ) 80131b2: fba3 0302 umull r0, r3, r3, r2 80131b6: 095b lsrs r3, r3, #5 80131b8: 2064 movs r0, #100 @ 0x64 80131ba: fb00 f303 mul.w r3, r0, r3 80131be: 1ad3 subs r3, r2, r3 80131c0: 011b lsls r3, r3, #4 80131c2: 3332 adds r3, #50 @ 0x32 80131c4: 4a07 ldr r2, [pc, #28] @ (80131e4 ) 80131c6: fba2 2303 umull r2, r3, r2, r3 80131ca: 095b lsrs r3, r3, #5 80131cc: f003 020f and.w r2, r3, #15 80131d0: 687b ldr r3, [r7, #4] 80131d2: 681b ldr r3, [r3, #0] 80131d4: 440a add r2, r1 80131d6: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 80131d8: bf00 nop 80131da: 3710 adds r7, #16 80131dc: 46bd mov sp, r7 80131de: bd80 pop {r7, pc} 80131e0: 40013800 .word 0x40013800 80131e4: 51eb851f .word 0x51eb851f 080131e8 <__cvt>: 80131e8: 2b00 cmp r3, #0 80131ea: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80131ee: 461d mov r5, r3 80131f0: bfbb ittet lt 80131f2: f103 4300 addlt.w r3, r3, #2147483648 @ 0x80000000 80131f6: 461d movlt r5, r3 80131f8: 2300 movge r3, #0 80131fa: 232d movlt r3, #45 @ 0x2d 80131fc: b088 sub sp, #32 80131fe: 4614 mov r4, r2 8013200: bfb8 it lt 8013202: 4614 movlt r4, r2 8013204: 9a12 ldr r2, [sp, #72] @ 0x48 8013206: 9e10 ldr r6, [sp, #64] @ 0x40 8013208: 7013 strb r3, [r2, #0] 801320a: 9b14 ldr r3, [sp, #80] @ 0x50 801320c: f8dd a04c ldr.w sl, [sp, #76] @ 0x4c 8013210: f023 0820 bic.w r8, r3, #32 8013214: f1b8 0f46 cmp.w r8, #70 @ 0x46 8013218: d005 beq.n 8013226 <__cvt+0x3e> 801321a: f1b8 0f45 cmp.w r8, #69 @ 0x45 801321e: d100 bne.n 8013222 <__cvt+0x3a> 8013220: 3601 adds r6, #1 8013222: 2302 movs r3, #2 8013224: e000 b.n 8013228 <__cvt+0x40> 8013226: 2303 movs r3, #3 8013228: aa07 add r2, sp, #28 801322a: 9204 str r2, [sp, #16] 801322c: aa06 add r2, sp, #24 801322e: e9cd a202 strd sl, r2, [sp, #8] 8013232: e9cd 3600 strd r3, r6, [sp] 8013236: 4622 mov r2, r4 8013238: 462b mov r3, r5 801323a: f000 fe3d bl 8013eb8 <_dtoa_r> 801323e: f1b8 0f47 cmp.w r8, #71 @ 0x47 8013242: 4607 mov r7, r0 8013244: d119 bne.n 801327a <__cvt+0x92> 8013246: 9b11 ldr r3, [sp, #68] @ 0x44 8013248: 07db lsls r3, r3, #31 801324a: d50e bpl.n 801326a <__cvt+0x82> 801324c: eb00 0906 add.w r9, r0, r6 8013250: 2200 movs r2, #0 8013252: 2300 movs r3, #0 8013254: 4620 mov r0, r4 8013256: 4629 mov r1, r5 8013258: f7f5 fc12 bl 8008a80 <__aeabi_dcmpeq> 801325c: b108 cbz r0, 8013262 <__cvt+0x7a> 801325e: f8cd 901c str.w r9, [sp, #28] 8013262: 2230 movs r2, #48 @ 0x30 8013264: 9b07 ldr r3, [sp, #28] 8013266: 454b cmp r3, r9 8013268: d31e bcc.n 80132a8 <__cvt+0xc0> 801326a: 4638 mov r0, r7 801326c: 9b07 ldr r3, [sp, #28] 801326e: 9a15 ldr r2, [sp, #84] @ 0x54 8013270: 1bdb subs r3, r3, r7 8013272: 6013 str r3, [r2, #0] 8013274: b008 add sp, #32 8013276: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801327a: f1b8 0f46 cmp.w r8, #70 @ 0x46 801327e: eb00 0906 add.w r9, r0, r6 8013282: d1e5 bne.n 8013250 <__cvt+0x68> 8013284: 7803 ldrb r3, [r0, #0] 8013286: 2b30 cmp r3, #48 @ 0x30 8013288: d10a bne.n 80132a0 <__cvt+0xb8> 801328a: 2200 movs r2, #0 801328c: 2300 movs r3, #0 801328e: 4620 mov r0, r4 8013290: 4629 mov r1, r5 8013292: f7f5 fbf5 bl 8008a80 <__aeabi_dcmpeq> 8013296: b918 cbnz r0, 80132a0 <__cvt+0xb8> 8013298: f1c6 0601 rsb r6, r6, #1 801329c: f8ca 6000 str.w r6, [sl] 80132a0: f8da 3000 ldr.w r3, [sl] 80132a4: 4499 add r9, r3 80132a6: e7d3 b.n 8013250 <__cvt+0x68> 80132a8: 1c59 adds r1, r3, #1 80132aa: 9107 str r1, [sp, #28] 80132ac: 701a strb r2, [r3, #0] 80132ae: e7d9 b.n 8013264 <__cvt+0x7c> 080132b0 <__exponent>: 80132b0: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 80132b2: 2900 cmp r1, #0 80132b4: bfb6 itet lt 80132b6: 232d movlt r3, #45 @ 0x2d 80132b8: 232b movge r3, #43 @ 0x2b 80132ba: 4249 neglt r1, r1 80132bc: 2909 cmp r1, #9 80132be: 7002 strb r2, [r0, #0] 80132c0: 7043 strb r3, [r0, #1] 80132c2: dd29 ble.n 8013318 <__exponent+0x68> 80132c4: f10d 0307 add.w r3, sp, #7 80132c8: 461d mov r5, r3 80132ca: 270a movs r7, #10 80132cc: fbb1 f6f7 udiv r6, r1, r7 80132d0: 461a mov r2, r3 80132d2: fb07 1416 mls r4, r7, r6, r1 80132d6: 3430 adds r4, #48 @ 0x30 80132d8: f802 4c01 strb.w r4, [r2, #-1] 80132dc: 460c mov r4, r1 80132de: 2c63 cmp r4, #99 @ 0x63 80132e0: 4631 mov r1, r6 80132e2: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff 80132e6: dcf1 bgt.n 80132cc <__exponent+0x1c> 80132e8: 3130 adds r1, #48 @ 0x30 80132ea: 1e94 subs r4, r2, #2 80132ec: f803 1c01 strb.w r1, [r3, #-1] 80132f0: 4623 mov r3, r4 80132f2: 1c41 adds r1, r0, #1 80132f4: 42ab cmp r3, r5 80132f6: d30a bcc.n 801330e <__exponent+0x5e> 80132f8: f10d 0309 add.w r3, sp, #9 80132fc: 1a9b subs r3, r3, r2 80132fe: 42ac cmp r4, r5 8013300: bf88 it hi 8013302: 2300 movhi r3, #0 8013304: 3302 adds r3, #2 8013306: 4403 add r3, r0 8013308: 1a18 subs r0, r3, r0 801330a: b003 add sp, #12 801330c: bdf0 pop {r4, r5, r6, r7, pc} 801330e: f813 6b01 ldrb.w r6, [r3], #1 8013312: f801 6f01 strb.w r6, [r1, #1]! 8013316: e7ed b.n 80132f4 <__exponent+0x44> 8013318: 2330 movs r3, #48 @ 0x30 801331a: 3130 adds r1, #48 @ 0x30 801331c: 7083 strb r3, [r0, #2] 801331e: 70c1 strb r1, [r0, #3] 8013320: 1d03 adds r3, r0, #4 8013322: e7f1 b.n 8013308 <__exponent+0x58> 08013324 <_printf_float>: 8013324: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8013328: b091 sub sp, #68 @ 0x44 801332a: 460c mov r4, r1 801332c: f8dd 8068 ldr.w r8, [sp, #104] @ 0x68 8013330: 4616 mov r6, r2 8013332: 461f mov r7, r3 8013334: 4605 mov r5, r0 8013336: f000 fcf7 bl 8013d28 <_localeconv_r> 801333a: 6803 ldr r3, [r0, #0] 801333c: 4618 mov r0, r3 801333e: 9308 str r3, [sp, #32] 8013340: f7f4 ff72 bl 8008228 8013344: 2300 movs r3, #0 8013346: 930e str r3, [sp, #56] @ 0x38 8013348: f8d8 3000 ldr.w r3, [r8] 801334c: 9009 str r0, [sp, #36] @ 0x24 801334e: 3307 adds r3, #7 8013350: f023 0307 bic.w r3, r3, #7 8013354: f103 0208 add.w r2, r3, #8 8013358: f894 a018 ldrb.w sl, [r4, #24] 801335c: f8d4 b000 ldr.w fp, [r4] 8013360: f8c8 2000 str.w r2, [r8] 8013364: e9d3 8900 ldrd r8, r9, [r3] 8013368: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000 801336c: 930b str r3, [sp, #44] @ 0x2c 801336e: f8cd 8028 str.w r8, [sp, #40] @ 0x28 8013372: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8013376: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 801337a: e9c4 8912 strd r8, r9, [r4, #72] @ 0x48 801337e: 4b9c ldr r3, [pc, #624] @ (80135f0 <_printf_float+0x2cc>) 8013380: f7f5 fbb0 bl 8008ae4 <__aeabi_dcmpun> 8013384: bb70 cbnz r0, 80133e4 <_printf_float+0xc0> 8013386: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 801338a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801338e: 4b98 ldr r3, [pc, #608] @ (80135f0 <_printf_float+0x2cc>) 8013390: f7f5 fb8a bl 8008aa8 <__aeabi_dcmple> 8013394: bb30 cbnz r0, 80133e4 <_printf_float+0xc0> 8013396: 2200 movs r2, #0 8013398: 2300 movs r3, #0 801339a: 4640 mov r0, r8 801339c: 4649 mov r1, r9 801339e: f7f5 fb79 bl 8008a94 <__aeabi_dcmplt> 80133a2: b110 cbz r0, 80133aa <_printf_float+0x86> 80133a4: 232d movs r3, #45 @ 0x2d 80133a6: f884 3043 strb.w r3, [r4, #67] @ 0x43 80133aa: 4a92 ldr r2, [pc, #584] @ (80135f4 <_printf_float+0x2d0>) 80133ac: 4b92 ldr r3, [pc, #584] @ (80135f8 <_printf_float+0x2d4>) 80133ae: f1ba 0f47 cmp.w sl, #71 @ 0x47 80133b2: bf8c ite hi 80133b4: 4690 movhi r8, r2 80133b6: 4698 movls r8, r3 80133b8: 2303 movs r3, #3 80133ba: f04f 0900 mov.w r9, #0 80133be: 6123 str r3, [r4, #16] 80133c0: f02b 0304 bic.w r3, fp, #4 80133c4: 6023 str r3, [r4, #0] 80133c6: 4633 mov r3, r6 80133c8: 4621 mov r1, r4 80133ca: 4628 mov r0, r5 80133cc: 9700 str r7, [sp, #0] 80133ce: aa0f add r2, sp, #60 @ 0x3c 80133d0: f000 f9d4 bl 801377c <_printf_common> 80133d4: 3001 adds r0, #1 80133d6: f040 8090 bne.w 80134fa <_printf_float+0x1d6> 80133da: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80133de: b011 add sp, #68 @ 0x44 80133e0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80133e4: 4642 mov r2, r8 80133e6: 464b mov r3, r9 80133e8: 4640 mov r0, r8 80133ea: 4649 mov r1, r9 80133ec: f7f5 fb7a bl 8008ae4 <__aeabi_dcmpun> 80133f0: b148 cbz r0, 8013406 <_printf_float+0xe2> 80133f2: 464b mov r3, r9 80133f4: 2b00 cmp r3, #0 80133f6: bfb8 it lt 80133f8: 232d movlt r3, #45 @ 0x2d 80133fa: 4a80 ldr r2, [pc, #512] @ (80135fc <_printf_float+0x2d8>) 80133fc: bfb8 it lt 80133fe: f884 3043 strblt.w r3, [r4, #67] @ 0x43 8013402: 4b7f ldr r3, [pc, #508] @ (8013600 <_printf_float+0x2dc>) 8013404: e7d3 b.n 80133ae <_printf_float+0x8a> 8013406: 6863 ldr r3, [r4, #4] 8013408: f00a 01df and.w r1, sl, #223 @ 0xdf 801340c: 1c5a adds r2, r3, #1 801340e: d13f bne.n 8013490 <_printf_float+0x16c> 8013410: 2306 movs r3, #6 8013412: 6063 str r3, [r4, #4] 8013414: 2200 movs r2, #0 8013416: f44b 6380 orr.w r3, fp, #1024 @ 0x400 801341a: 6023 str r3, [r4, #0] 801341c: 9206 str r2, [sp, #24] 801341e: aa0e add r2, sp, #56 @ 0x38 8013420: e9cd a204 strd sl, r2, [sp, #16] 8013424: aa0d add r2, sp, #52 @ 0x34 8013426: 9203 str r2, [sp, #12] 8013428: f10d 0233 add.w r2, sp, #51 @ 0x33 801342c: e9cd 3201 strd r3, r2, [sp, #4] 8013430: 6863 ldr r3, [r4, #4] 8013432: 4642 mov r2, r8 8013434: 9300 str r3, [sp, #0] 8013436: 4628 mov r0, r5 8013438: 464b mov r3, r9 801343a: 910a str r1, [sp, #40] @ 0x28 801343c: f7ff fed4 bl 80131e8 <__cvt> 8013440: 990a ldr r1, [sp, #40] @ 0x28 8013442: 4680 mov r8, r0 8013444: 2947 cmp r1, #71 @ 0x47 8013446: 990d ldr r1, [sp, #52] @ 0x34 8013448: d128 bne.n 801349c <_printf_float+0x178> 801344a: 1cc8 adds r0, r1, #3 801344c: db02 blt.n 8013454 <_printf_float+0x130> 801344e: 6863 ldr r3, [r4, #4] 8013450: 4299 cmp r1, r3 8013452: dd40 ble.n 80134d6 <_printf_float+0x1b2> 8013454: f1aa 0a02 sub.w sl, sl, #2 8013458: fa5f fa8a uxtb.w sl, sl 801345c: 4652 mov r2, sl 801345e: 3901 subs r1, #1 8013460: f104 0050 add.w r0, r4, #80 @ 0x50 8013464: 910d str r1, [sp, #52] @ 0x34 8013466: f7ff ff23 bl 80132b0 <__exponent> 801346a: 9a0e ldr r2, [sp, #56] @ 0x38 801346c: 4681 mov r9, r0 801346e: 1813 adds r3, r2, r0 8013470: 2a01 cmp r2, #1 8013472: 6123 str r3, [r4, #16] 8013474: dc02 bgt.n 801347c <_printf_float+0x158> 8013476: 6822 ldr r2, [r4, #0] 8013478: 07d2 lsls r2, r2, #31 801347a: d501 bpl.n 8013480 <_printf_float+0x15c> 801347c: 3301 adds r3, #1 801347e: 6123 str r3, [r4, #16] 8013480: f89d 3033 ldrb.w r3, [sp, #51] @ 0x33 8013484: 2b00 cmp r3, #0 8013486: d09e beq.n 80133c6 <_printf_float+0xa2> 8013488: 232d movs r3, #45 @ 0x2d 801348a: f884 3043 strb.w r3, [r4, #67] @ 0x43 801348e: e79a b.n 80133c6 <_printf_float+0xa2> 8013490: 2947 cmp r1, #71 @ 0x47 8013492: d1bf bne.n 8013414 <_printf_float+0xf0> 8013494: 2b00 cmp r3, #0 8013496: d1bd bne.n 8013414 <_printf_float+0xf0> 8013498: 2301 movs r3, #1 801349a: e7ba b.n 8013412 <_printf_float+0xee> 801349c: f1ba 0f65 cmp.w sl, #101 @ 0x65 80134a0: d9dc bls.n 801345c <_printf_float+0x138> 80134a2: f1ba 0f66 cmp.w sl, #102 @ 0x66 80134a6: d118 bne.n 80134da <_printf_float+0x1b6> 80134a8: 2900 cmp r1, #0 80134aa: 6863 ldr r3, [r4, #4] 80134ac: dd0b ble.n 80134c6 <_printf_float+0x1a2> 80134ae: 6121 str r1, [r4, #16] 80134b0: b913 cbnz r3, 80134b8 <_printf_float+0x194> 80134b2: 6822 ldr r2, [r4, #0] 80134b4: 07d0 lsls r0, r2, #31 80134b6: d502 bpl.n 80134be <_printf_float+0x19a> 80134b8: 3301 adds r3, #1 80134ba: 440b add r3, r1 80134bc: 6123 str r3, [r4, #16] 80134be: f04f 0900 mov.w r9, #0 80134c2: 65a1 str r1, [r4, #88] @ 0x58 80134c4: e7dc b.n 8013480 <_printf_float+0x15c> 80134c6: b913 cbnz r3, 80134ce <_printf_float+0x1aa> 80134c8: 6822 ldr r2, [r4, #0] 80134ca: 07d2 lsls r2, r2, #31 80134cc: d501 bpl.n 80134d2 <_printf_float+0x1ae> 80134ce: 3302 adds r3, #2 80134d0: e7f4 b.n 80134bc <_printf_float+0x198> 80134d2: 2301 movs r3, #1 80134d4: e7f2 b.n 80134bc <_printf_float+0x198> 80134d6: f04f 0a67 mov.w sl, #103 @ 0x67 80134da: 9b0e ldr r3, [sp, #56] @ 0x38 80134dc: 4299 cmp r1, r3 80134de: db05 blt.n 80134ec <_printf_float+0x1c8> 80134e0: 6823 ldr r3, [r4, #0] 80134e2: 6121 str r1, [r4, #16] 80134e4: 07d8 lsls r0, r3, #31 80134e6: d5ea bpl.n 80134be <_printf_float+0x19a> 80134e8: 1c4b adds r3, r1, #1 80134ea: e7e7 b.n 80134bc <_printf_float+0x198> 80134ec: 2900 cmp r1, #0 80134ee: bfcc ite gt 80134f0: 2201 movgt r2, #1 80134f2: f1c1 0202 rsble r2, r1, #2 80134f6: 4413 add r3, r2 80134f8: e7e0 b.n 80134bc <_printf_float+0x198> 80134fa: 6823 ldr r3, [r4, #0] 80134fc: 055a lsls r2, r3, #21 80134fe: d407 bmi.n 8013510 <_printf_float+0x1ec> 8013500: 6923 ldr r3, [r4, #16] 8013502: 4642 mov r2, r8 8013504: 4631 mov r1, r6 8013506: 4628 mov r0, r5 8013508: 47b8 blx r7 801350a: 3001 adds r0, #1 801350c: d12b bne.n 8013566 <_printf_float+0x242> 801350e: e764 b.n 80133da <_printf_float+0xb6> 8013510: f1ba 0f65 cmp.w sl, #101 @ 0x65 8013514: f240 80dc bls.w 80136d0 <_printf_float+0x3ac> 8013518: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 801351c: 2200 movs r2, #0 801351e: 2300 movs r3, #0 8013520: f7f5 faae bl 8008a80 <__aeabi_dcmpeq> 8013524: 2800 cmp r0, #0 8013526: d033 beq.n 8013590 <_printf_float+0x26c> 8013528: 2301 movs r3, #1 801352a: 4631 mov r1, r6 801352c: 4628 mov r0, r5 801352e: 4a35 ldr r2, [pc, #212] @ (8013604 <_printf_float+0x2e0>) 8013530: 47b8 blx r7 8013532: 3001 adds r0, #1 8013534: f43f af51 beq.w 80133da <_printf_float+0xb6> 8013538: e9dd 380d ldrd r3, r8, [sp, #52] @ 0x34 801353c: 4543 cmp r3, r8 801353e: db02 blt.n 8013546 <_printf_float+0x222> 8013540: 6823 ldr r3, [r4, #0] 8013542: 07d8 lsls r0, r3, #31 8013544: d50f bpl.n 8013566 <_printf_float+0x242> 8013546: e9dd 2308 ldrd r2, r3, [sp, #32] 801354a: 4631 mov r1, r6 801354c: 4628 mov r0, r5 801354e: 47b8 blx r7 8013550: 3001 adds r0, #1 8013552: f43f af42 beq.w 80133da <_printf_float+0xb6> 8013556: f04f 0900 mov.w r9, #0 801355a: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 801355e: f104 0a1a add.w sl, r4, #26 8013562: 45c8 cmp r8, r9 8013564: dc09 bgt.n 801357a <_printf_float+0x256> 8013566: 6823 ldr r3, [r4, #0] 8013568: 079b lsls r3, r3, #30 801356a: f100 8102 bmi.w 8013772 <_printf_float+0x44e> 801356e: 68e0 ldr r0, [r4, #12] 8013570: 9b0f ldr r3, [sp, #60] @ 0x3c 8013572: 4298 cmp r0, r3 8013574: bfb8 it lt 8013576: 4618 movlt r0, r3 8013578: e731 b.n 80133de <_printf_float+0xba> 801357a: 2301 movs r3, #1 801357c: 4652 mov r2, sl 801357e: 4631 mov r1, r6 8013580: 4628 mov r0, r5 8013582: 47b8 blx r7 8013584: 3001 adds r0, #1 8013586: f43f af28 beq.w 80133da <_printf_float+0xb6> 801358a: f109 0901 add.w r9, r9, #1 801358e: e7e8 b.n 8013562 <_printf_float+0x23e> 8013590: 9b0d ldr r3, [sp, #52] @ 0x34 8013592: 2b00 cmp r3, #0 8013594: dc38 bgt.n 8013608 <_printf_float+0x2e4> 8013596: 2301 movs r3, #1 8013598: 4631 mov r1, r6 801359a: 4628 mov r0, r5 801359c: 4a19 ldr r2, [pc, #100] @ (8013604 <_printf_float+0x2e0>) 801359e: 47b8 blx r7 80135a0: 3001 adds r0, #1 80135a2: f43f af1a beq.w 80133da <_printf_float+0xb6> 80135a6: e9dd 390d ldrd r3, r9, [sp, #52] @ 0x34 80135aa: ea59 0303 orrs.w r3, r9, r3 80135ae: d102 bne.n 80135b6 <_printf_float+0x292> 80135b0: 6823 ldr r3, [r4, #0] 80135b2: 07d9 lsls r1, r3, #31 80135b4: d5d7 bpl.n 8013566 <_printf_float+0x242> 80135b6: e9dd 2308 ldrd r2, r3, [sp, #32] 80135ba: 4631 mov r1, r6 80135bc: 4628 mov r0, r5 80135be: 47b8 blx r7 80135c0: 3001 adds r0, #1 80135c2: f43f af0a beq.w 80133da <_printf_float+0xb6> 80135c6: f04f 0a00 mov.w sl, #0 80135ca: f104 0b1a add.w fp, r4, #26 80135ce: 9b0d ldr r3, [sp, #52] @ 0x34 80135d0: 425b negs r3, r3 80135d2: 4553 cmp r3, sl 80135d4: dc01 bgt.n 80135da <_printf_float+0x2b6> 80135d6: 464b mov r3, r9 80135d8: e793 b.n 8013502 <_printf_float+0x1de> 80135da: 2301 movs r3, #1 80135dc: 465a mov r2, fp 80135de: 4631 mov r1, r6 80135e0: 4628 mov r0, r5 80135e2: 47b8 blx r7 80135e4: 3001 adds r0, #1 80135e6: f43f aef8 beq.w 80133da <_printf_float+0xb6> 80135ea: f10a 0a01 add.w sl, sl, #1 80135ee: e7ee b.n 80135ce <_printf_float+0x2aa> 80135f0: 7fefffff .word 0x7fefffff 80135f4: 080163e0 .word 0x080163e0 80135f8: 080163dc .word 0x080163dc 80135fc: 080163e8 .word 0x080163e8 8013600: 080163e4 .word 0x080163e4 8013604: 080163ec .word 0x080163ec 8013608: 6da3 ldr r3, [r4, #88] @ 0x58 801360a: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 801360e: 4553 cmp r3, sl 8013610: bfa8 it ge 8013612: 4653 movge r3, sl 8013614: 2b00 cmp r3, #0 8013616: 4699 mov r9, r3 8013618: dc36 bgt.n 8013688 <_printf_float+0x364> 801361a: f04f 0b00 mov.w fp, #0 801361e: ea29 79e9 bic.w r9, r9, r9, asr #31 8013622: f104 021a add.w r2, r4, #26 8013626: 6da3 ldr r3, [r4, #88] @ 0x58 8013628: 930a str r3, [sp, #40] @ 0x28 801362a: eba3 0309 sub.w r3, r3, r9 801362e: 455b cmp r3, fp 8013630: dc31 bgt.n 8013696 <_printf_float+0x372> 8013632: 9b0d ldr r3, [sp, #52] @ 0x34 8013634: 459a cmp sl, r3 8013636: dc3a bgt.n 80136ae <_printf_float+0x38a> 8013638: 6823 ldr r3, [r4, #0] 801363a: 07da lsls r2, r3, #31 801363c: d437 bmi.n 80136ae <_printf_float+0x38a> 801363e: 9b0d ldr r3, [sp, #52] @ 0x34 8013640: ebaa 0903 sub.w r9, sl, r3 8013644: 9b0a ldr r3, [sp, #40] @ 0x28 8013646: ebaa 0303 sub.w r3, sl, r3 801364a: 4599 cmp r9, r3 801364c: bfa8 it ge 801364e: 4699 movge r9, r3 8013650: f1b9 0f00 cmp.w r9, #0 8013654: dc33 bgt.n 80136be <_printf_float+0x39a> 8013656: f04f 0800 mov.w r8, #0 801365a: ea29 79e9 bic.w r9, r9, r9, asr #31 801365e: f104 0b1a add.w fp, r4, #26 8013662: 9b0d ldr r3, [sp, #52] @ 0x34 8013664: ebaa 0303 sub.w r3, sl, r3 8013668: eba3 0309 sub.w r3, r3, r9 801366c: 4543 cmp r3, r8 801366e: f77f af7a ble.w 8013566 <_printf_float+0x242> 8013672: 2301 movs r3, #1 8013674: 465a mov r2, fp 8013676: 4631 mov r1, r6 8013678: 4628 mov r0, r5 801367a: 47b8 blx r7 801367c: 3001 adds r0, #1 801367e: f43f aeac beq.w 80133da <_printf_float+0xb6> 8013682: f108 0801 add.w r8, r8, #1 8013686: e7ec b.n 8013662 <_printf_float+0x33e> 8013688: 4642 mov r2, r8 801368a: 4631 mov r1, r6 801368c: 4628 mov r0, r5 801368e: 47b8 blx r7 8013690: 3001 adds r0, #1 8013692: d1c2 bne.n 801361a <_printf_float+0x2f6> 8013694: e6a1 b.n 80133da <_printf_float+0xb6> 8013696: 2301 movs r3, #1 8013698: 4631 mov r1, r6 801369a: 4628 mov r0, r5 801369c: 920a str r2, [sp, #40] @ 0x28 801369e: 47b8 blx r7 80136a0: 3001 adds r0, #1 80136a2: f43f ae9a beq.w 80133da <_printf_float+0xb6> 80136a6: 9a0a ldr r2, [sp, #40] @ 0x28 80136a8: f10b 0b01 add.w fp, fp, #1 80136ac: e7bb b.n 8013626 <_printf_float+0x302> 80136ae: 4631 mov r1, r6 80136b0: e9dd 2308 ldrd r2, r3, [sp, #32] 80136b4: 4628 mov r0, r5 80136b6: 47b8 blx r7 80136b8: 3001 adds r0, #1 80136ba: d1c0 bne.n 801363e <_printf_float+0x31a> 80136bc: e68d b.n 80133da <_printf_float+0xb6> 80136be: 9a0a ldr r2, [sp, #40] @ 0x28 80136c0: 464b mov r3, r9 80136c2: 4631 mov r1, r6 80136c4: 4628 mov r0, r5 80136c6: 4442 add r2, r8 80136c8: 47b8 blx r7 80136ca: 3001 adds r0, #1 80136cc: d1c3 bne.n 8013656 <_printf_float+0x332> 80136ce: e684 b.n 80133da <_printf_float+0xb6> 80136d0: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 80136d4: f1ba 0f01 cmp.w sl, #1 80136d8: dc01 bgt.n 80136de <_printf_float+0x3ba> 80136da: 07db lsls r3, r3, #31 80136dc: d536 bpl.n 801374c <_printf_float+0x428> 80136de: 2301 movs r3, #1 80136e0: 4642 mov r2, r8 80136e2: 4631 mov r1, r6 80136e4: 4628 mov r0, r5 80136e6: 47b8 blx r7 80136e8: 3001 adds r0, #1 80136ea: f43f ae76 beq.w 80133da <_printf_float+0xb6> 80136ee: e9dd 2308 ldrd r2, r3, [sp, #32] 80136f2: 4631 mov r1, r6 80136f4: 4628 mov r0, r5 80136f6: 47b8 blx r7 80136f8: 3001 adds r0, #1 80136fa: f43f ae6e beq.w 80133da <_printf_float+0xb6> 80136fe: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 8013702: 2200 movs r2, #0 8013704: 2300 movs r3, #0 8013706: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff 801370a: f7f5 f9b9 bl 8008a80 <__aeabi_dcmpeq> 801370e: b9c0 cbnz r0, 8013742 <_printf_float+0x41e> 8013710: 4653 mov r3, sl 8013712: f108 0201 add.w r2, r8, #1 8013716: 4631 mov r1, r6 8013718: 4628 mov r0, r5 801371a: 47b8 blx r7 801371c: 3001 adds r0, #1 801371e: d10c bne.n 801373a <_printf_float+0x416> 8013720: e65b b.n 80133da <_printf_float+0xb6> 8013722: 2301 movs r3, #1 8013724: 465a mov r2, fp 8013726: 4631 mov r1, r6 8013728: 4628 mov r0, r5 801372a: 47b8 blx r7 801372c: 3001 adds r0, #1 801372e: f43f ae54 beq.w 80133da <_printf_float+0xb6> 8013732: f108 0801 add.w r8, r8, #1 8013736: 45d0 cmp r8, sl 8013738: dbf3 blt.n 8013722 <_printf_float+0x3fe> 801373a: 464b mov r3, r9 801373c: f104 0250 add.w r2, r4, #80 @ 0x50 8013740: e6e0 b.n 8013504 <_printf_float+0x1e0> 8013742: f04f 0800 mov.w r8, #0 8013746: f104 0b1a add.w fp, r4, #26 801374a: e7f4 b.n 8013736 <_printf_float+0x412> 801374c: 2301 movs r3, #1 801374e: 4642 mov r2, r8 8013750: e7e1 b.n 8013716 <_printf_float+0x3f2> 8013752: 2301 movs r3, #1 8013754: 464a mov r2, r9 8013756: 4631 mov r1, r6 8013758: 4628 mov r0, r5 801375a: 47b8 blx r7 801375c: 3001 adds r0, #1 801375e: f43f ae3c beq.w 80133da <_printf_float+0xb6> 8013762: f108 0801 add.w r8, r8, #1 8013766: 68e3 ldr r3, [r4, #12] 8013768: 990f ldr r1, [sp, #60] @ 0x3c 801376a: 1a5b subs r3, r3, r1 801376c: 4543 cmp r3, r8 801376e: dcf0 bgt.n 8013752 <_printf_float+0x42e> 8013770: e6fd b.n 801356e <_printf_float+0x24a> 8013772: f04f 0800 mov.w r8, #0 8013776: f104 0919 add.w r9, r4, #25 801377a: e7f4 b.n 8013766 <_printf_float+0x442> 0801377c <_printf_common>: 801377c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8013780: 4616 mov r6, r2 8013782: 4698 mov r8, r3 8013784: 688a ldr r2, [r1, #8] 8013786: 690b ldr r3, [r1, #16] 8013788: 4607 mov r7, r0 801378a: 4293 cmp r3, r2 801378c: bfb8 it lt 801378e: 4613 movlt r3, r2 8013790: 6033 str r3, [r6, #0] 8013792: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 8013796: 460c mov r4, r1 8013798: f8dd 9020 ldr.w r9, [sp, #32] 801379c: b10a cbz r2, 80137a2 <_printf_common+0x26> 801379e: 3301 adds r3, #1 80137a0: 6033 str r3, [r6, #0] 80137a2: 6823 ldr r3, [r4, #0] 80137a4: 0699 lsls r1, r3, #26 80137a6: bf42 ittt mi 80137a8: 6833 ldrmi r3, [r6, #0] 80137aa: 3302 addmi r3, #2 80137ac: 6033 strmi r3, [r6, #0] 80137ae: 6825 ldr r5, [r4, #0] 80137b0: f015 0506 ands.w r5, r5, #6 80137b4: d106 bne.n 80137c4 <_printf_common+0x48> 80137b6: f104 0a19 add.w sl, r4, #25 80137ba: 68e3 ldr r3, [r4, #12] 80137bc: 6832 ldr r2, [r6, #0] 80137be: 1a9b subs r3, r3, r2 80137c0: 42ab cmp r3, r5 80137c2: dc2b bgt.n 801381c <_printf_common+0xa0> 80137c4: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 80137c8: 6822 ldr r2, [r4, #0] 80137ca: 3b00 subs r3, #0 80137cc: bf18 it ne 80137ce: 2301 movne r3, #1 80137d0: 0692 lsls r2, r2, #26 80137d2: d430 bmi.n 8013836 <_printf_common+0xba> 80137d4: 4641 mov r1, r8 80137d6: 4638 mov r0, r7 80137d8: f104 0243 add.w r2, r4, #67 @ 0x43 80137dc: 47c8 blx r9 80137de: 3001 adds r0, #1 80137e0: d023 beq.n 801382a <_printf_common+0xae> 80137e2: 6823 ldr r3, [r4, #0] 80137e4: 6922 ldr r2, [r4, #16] 80137e6: f003 0306 and.w r3, r3, #6 80137ea: 2b04 cmp r3, #4 80137ec: bf14 ite ne 80137ee: 2500 movne r5, #0 80137f0: 6833 ldreq r3, [r6, #0] 80137f2: f04f 0600 mov.w r6, #0 80137f6: bf08 it eq 80137f8: 68e5 ldreq r5, [r4, #12] 80137fa: f104 041a add.w r4, r4, #26 80137fe: bf08 it eq 8013800: 1aed subeq r5, r5, r3 8013802: f854 3c12 ldr.w r3, [r4, #-18] 8013806: bf08 it eq 8013808: ea25 75e5 biceq.w r5, r5, r5, asr #31 801380c: 4293 cmp r3, r2 801380e: bfc4 itt gt 8013810: 1a9b subgt r3, r3, r2 8013812: 18ed addgt r5, r5, r3 8013814: 42b5 cmp r5, r6 8013816: d11a bne.n 801384e <_printf_common+0xd2> 8013818: 2000 movs r0, #0 801381a: e008 b.n 801382e <_printf_common+0xb2> 801381c: 2301 movs r3, #1 801381e: 4652 mov r2, sl 8013820: 4641 mov r1, r8 8013822: 4638 mov r0, r7 8013824: 47c8 blx r9 8013826: 3001 adds r0, #1 8013828: d103 bne.n 8013832 <_printf_common+0xb6> 801382a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801382e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8013832: 3501 adds r5, #1 8013834: e7c1 b.n 80137ba <_printf_common+0x3e> 8013836: 2030 movs r0, #48 @ 0x30 8013838: 18e1 adds r1, r4, r3 801383a: f881 0043 strb.w r0, [r1, #67] @ 0x43 801383e: 1c5a adds r2, r3, #1 8013840: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 8013844: 4422 add r2, r4 8013846: 3302 adds r3, #2 8013848: f882 1043 strb.w r1, [r2, #67] @ 0x43 801384c: e7c2 b.n 80137d4 <_printf_common+0x58> 801384e: 2301 movs r3, #1 8013850: 4622 mov r2, r4 8013852: 4641 mov r1, r8 8013854: 4638 mov r0, r7 8013856: 47c8 blx r9 8013858: 3001 adds r0, #1 801385a: d0e6 beq.n 801382a <_printf_common+0xae> 801385c: 3601 adds r6, #1 801385e: e7d9 b.n 8013814 <_printf_common+0x98> 08013860 <_printf_i>: 8013860: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 8013864: 7e0f ldrb r7, [r1, #24] 8013866: 4691 mov r9, r2 8013868: 2f78 cmp r7, #120 @ 0x78 801386a: 4680 mov r8, r0 801386c: 460c mov r4, r1 801386e: 469a mov sl, r3 8013870: 9e0c ldr r6, [sp, #48] @ 0x30 8013872: f101 0243 add.w r2, r1, #67 @ 0x43 8013876: d807 bhi.n 8013888 <_printf_i+0x28> 8013878: 2f62 cmp r7, #98 @ 0x62 801387a: d80a bhi.n 8013892 <_printf_i+0x32> 801387c: 2f00 cmp r7, #0 801387e: f000 80d1 beq.w 8013a24 <_printf_i+0x1c4> 8013882: 2f58 cmp r7, #88 @ 0x58 8013884: f000 80b8 beq.w 80139f8 <_printf_i+0x198> 8013888: f104 0642 add.w r6, r4, #66 @ 0x42 801388c: f884 7042 strb.w r7, [r4, #66] @ 0x42 8013890: e03a b.n 8013908 <_printf_i+0xa8> 8013892: f1a7 0363 sub.w r3, r7, #99 @ 0x63 8013896: 2b15 cmp r3, #21 8013898: d8f6 bhi.n 8013888 <_printf_i+0x28> 801389a: a101 add r1, pc, #4 @ (adr r1, 80138a0 <_printf_i+0x40>) 801389c: f851 f023 ldr.w pc, [r1, r3, lsl #2] 80138a0: 080138f9 .word 0x080138f9 80138a4: 0801390d .word 0x0801390d 80138a8: 08013889 .word 0x08013889 80138ac: 08013889 .word 0x08013889 80138b0: 08013889 .word 0x08013889 80138b4: 08013889 .word 0x08013889 80138b8: 0801390d .word 0x0801390d 80138bc: 08013889 .word 0x08013889 80138c0: 08013889 .word 0x08013889 80138c4: 08013889 .word 0x08013889 80138c8: 08013889 .word 0x08013889 80138cc: 08013a0b .word 0x08013a0b 80138d0: 08013937 .word 0x08013937 80138d4: 080139c5 .word 0x080139c5 80138d8: 08013889 .word 0x08013889 80138dc: 08013889 .word 0x08013889 80138e0: 08013a2d .word 0x08013a2d 80138e4: 08013889 .word 0x08013889 80138e8: 08013937 .word 0x08013937 80138ec: 08013889 .word 0x08013889 80138f0: 08013889 .word 0x08013889 80138f4: 080139cd .word 0x080139cd 80138f8: 6833 ldr r3, [r6, #0] 80138fa: 1d1a adds r2, r3, #4 80138fc: 681b ldr r3, [r3, #0] 80138fe: 6032 str r2, [r6, #0] 8013900: f104 0642 add.w r6, r4, #66 @ 0x42 8013904: f884 3042 strb.w r3, [r4, #66] @ 0x42 8013908: 2301 movs r3, #1 801390a: e09c b.n 8013a46 <_printf_i+0x1e6> 801390c: 6833 ldr r3, [r6, #0] 801390e: 6820 ldr r0, [r4, #0] 8013910: 1d19 adds r1, r3, #4 8013912: 6031 str r1, [r6, #0] 8013914: 0606 lsls r6, r0, #24 8013916: d501 bpl.n 801391c <_printf_i+0xbc> 8013918: 681d ldr r5, [r3, #0] 801391a: e003 b.n 8013924 <_printf_i+0xc4> 801391c: 0645 lsls r5, r0, #25 801391e: d5fb bpl.n 8013918 <_printf_i+0xb8> 8013920: f9b3 5000 ldrsh.w r5, [r3] 8013924: 2d00 cmp r5, #0 8013926: da03 bge.n 8013930 <_printf_i+0xd0> 8013928: 232d movs r3, #45 @ 0x2d 801392a: 426d negs r5, r5 801392c: f884 3043 strb.w r3, [r4, #67] @ 0x43 8013930: 230a movs r3, #10 8013932: 4858 ldr r0, [pc, #352] @ (8013a94 <_printf_i+0x234>) 8013934: e011 b.n 801395a <_printf_i+0xfa> 8013936: 6821 ldr r1, [r4, #0] 8013938: 6833 ldr r3, [r6, #0] 801393a: 0608 lsls r0, r1, #24 801393c: f853 5b04 ldr.w r5, [r3], #4 8013940: d402 bmi.n 8013948 <_printf_i+0xe8> 8013942: 0649 lsls r1, r1, #25 8013944: bf48 it mi 8013946: b2ad uxthmi r5, r5 8013948: 2f6f cmp r7, #111 @ 0x6f 801394a: 6033 str r3, [r6, #0] 801394c: bf14 ite ne 801394e: 230a movne r3, #10 8013950: 2308 moveq r3, #8 8013952: 4850 ldr r0, [pc, #320] @ (8013a94 <_printf_i+0x234>) 8013954: 2100 movs r1, #0 8013956: f884 1043 strb.w r1, [r4, #67] @ 0x43 801395a: 6866 ldr r6, [r4, #4] 801395c: 2e00 cmp r6, #0 801395e: 60a6 str r6, [r4, #8] 8013960: db05 blt.n 801396e <_printf_i+0x10e> 8013962: 6821 ldr r1, [r4, #0] 8013964: 432e orrs r6, r5 8013966: f021 0104 bic.w r1, r1, #4 801396a: 6021 str r1, [r4, #0] 801396c: d04b beq.n 8013a06 <_printf_i+0x1a6> 801396e: 4616 mov r6, r2 8013970: fbb5 f1f3 udiv r1, r5, r3 8013974: fb03 5711 mls r7, r3, r1, r5 8013978: 5dc7 ldrb r7, [r0, r7] 801397a: f806 7d01 strb.w r7, [r6, #-1]! 801397e: 462f mov r7, r5 8013980: 42bb cmp r3, r7 8013982: 460d mov r5, r1 8013984: d9f4 bls.n 8013970 <_printf_i+0x110> 8013986: 2b08 cmp r3, #8 8013988: d10b bne.n 80139a2 <_printf_i+0x142> 801398a: 6823 ldr r3, [r4, #0] 801398c: 07df lsls r7, r3, #31 801398e: d508 bpl.n 80139a2 <_printf_i+0x142> 8013990: 6923 ldr r3, [r4, #16] 8013992: 6861 ldr r1, [r4, #4] 8013994: 4299 cmp r1, r3 8013996: bfde ittt le 8013998: 2330 movle r3, #48 @ 0x30 801399a: f806 3c01 strble.w r3, [r6, #-1] 801399e: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff 80139a2: 1b92 subs r2, r2, r6 80139a4: 6122 str r2, [r4, #16] 80139a6: 464b mov r3, r9 80139a8: 4621 mov r1, r4 80139aa: 4640 mov r0, r8 80139ac: f8cd a000 str.w sl, [sp] 80139b0: aa03 add r2, sp, #12 80139b2: f7ff fee3 bl 801377c <_printf_common> 80139b6: 3001 adds r0, #1 80139b8: d14a bne.n 8013a50 <_printf_i+0x1f0> 80139ba: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80139be: b004 add sp, #16 80139c0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80139c4: 6823 ldr r3, [r4, #0] 80139c6: f043 0320 orr.w r3, r3, #32 80139ca: 6023 str r3, [r4, #0] 80139cc: 2778 movs r7, #120 @ 0x78 80139ce: 4832 ldr r0, [pc, #200] @ (8013a98 <_printf_i+0x238>) 80139d0: f884 7045 strb.w r7, [r4, #69] @ 0x45 80139d4: 6823 ldr r3, [r4, #0] 80139d6: 6831 ldr r1, [r6, #0] 80139d8: 061f lsls r7, r3, #24 80139da: f851 5b04 ldr.w r5, [r1], #4 80139de: d402 bmi.n 80139e6 <_printf_i+0x186> 80139e0: 065f lsls r7, r3, #25 80139e2: bf48 it mi 80139e4: b2ad uxthmi r5, r5 80139e6: 6031 str r1, [r6, #0] 80139e8: 07d9 lsls r1, r3, #31 80139ea: bf44 itt mi 80139ec: f043 0320 orrmi.w r3, r3, #32 80139f0: 6023 strmi r3, [r4, #0] 80139f2: b11d cbz r5, 80139fc <_printf_i+0x19c> 80139f4: 2310 movs r3, #16 80139f6: e7ad b.n 8013954 <_printf_i+0xf4> 80139f8: 4826 ldr r0, [pc, #152] @ (8013a94 <_printf_i+0x234>) 80139fa: e7e9 b.n 80139d0 <_printf_i+0x170> 80139fc: 6823 ldr r3, [r4, #0] 80139fe: f023 0320 bic.w r3, r3, #32 8013a02: 6023 str r3, [r4, #0] 8013a04: e7f6 b.n 80139f4 <_printf_i+0x194> 8013a06: 4616 mov r6, r2 8013a08: e7bd b.n 8013986 <_printf_i+0x126> 8013a0a: 6833 ldr r3, [r6, #0] 8013a0c: 6825 ldr r5, [r4, #0] 8013a0e: 1d18 adds r0, r3, #4 8013a10: 6961 ldr r1, [r4, #20] 8013a12: 6030 str r0, [r6, #0] 8013a14: 062e lsls r6, r5, #24 8013a16: 681b ldr r3, [r3, #0] 8013a18: d501 bpl.n 8013a1e <_printf_i+0x1be> 8013a1a: 6019 str r1, [r3, #0] 8013a1c: e002 b.n 8013a24 <_printf_i+0x1c4> 8013a1e: 0668 lsls r0, r5, #25 8013a20: d5fb bpl.n 8013a1a <_printf_i+0x1ba> 8013a22: 8019 strh r1, [r3, #0] 8013a24: 2300 movs r3, #0 8013a26: 4616 mov r6, r2 8013a28: 6123 str r3, [r4, #16] 8013a2a: e7bc b.n 80139a6 <_printf_i+0x146> 8013a2c: 6833 ldr r3, [r6, #0] 8013a2e: 2100 movs r1, #0 8013a30: 1d1a adds r2, r3, #4 8013a32: 6032 str r2, [r6, #0] 8013a34: 681e ldr r6, [r3, #0] 8013a36: 6862 ldr r2, [r4, #4] 8013a38: 4630 mov r0, r6 8013a3a: f000 f979 bl 8013d30 8013a3e: b108 cbz r0, 8013a44 <_printf_i+0x1e4> 8013a40: 1b80 subs r0, r0, r6 8013a42: 6060 str r0, [r4, #4] 8013a44: 6863 ldr r3, [r4, #4] 8013a46: 6123 str r3, [r4, #16] 8013a48: 2300 movs r3, #0 8013a4a: f884 3043 strb.w r3, [r4, #67] @ 0x43 8013a4e: e7aa b.n 80139a6 <_printf_i+0x146> 8013a50: 4632 mov r2, r6 8013a52: 4649 mov r1, r9 8013a54: 4640 mov r0, r8 8013a56: 6923 ldr r3, [r4, #16] 8013a58: 47d0 blx sl 8013a5a: 3001 adds r0, #1 8013a5c: d0ad beq.n 80139ba <_printf_i+0x15a> 8013a5e: 6823 ldr r3, [r4, #0] 8013a60: 079b lsls r3, r3, #30 8013a62: d413 bmi.n 8013a8c <_printf_i+0x22c> 8013a64: 68e0 ldr r0, [r4, #12] 8013a66: 9b03 ldr r3, [sp, #12] 8013a68: 4298 cmp r0, r3 8013a6a: bfb8 it lt 8013a6c: 4618 movlt r0, r3 8013a6e: e7a6 b.n 80139be <_printf_i+0x15e> 8013a70: 2301 movs r3, #1 8013a72: 4632 mov r2, r6 8013a74: 4649 mov r1, r9 8013a76: 4640 mov r0, r8 8013a78: 47d0 blx sl 8013a7a: 3001 adds r0, #1 8013a7c: d09d beq.n 80139ba <_printf_i+0x15a> 8013a7e: 3501 adds r5, #1 8013a80: 68e3 ldr r3, [r4, #12] 8013a82: 9903 ldr r1, [sp, #12] 8013a84: 1a5b subs r3, r3, r1 8013a86: 42ab cmp r3, r5 8013a88: dcf2 bgt.n 8013a70 <_printf_i+0x210> 8013a8a: e7eb b.n 8013a64 <_printf_i+0x204> 8013a8c: 2500 movs r5, #0 8013a8e: f104 0619 add.w r6, r4, #25 8013a92: e7f5 b.n 8013a80 <_printf_i+0x220> 8013a94: 080163ee .word 0x080163ee 8013a98: 080163ff .word 0x080163ff 08013a9c : 8013a9c: 2300 movs r3, #0 8013a9e: b510 push {r4, lr} 8013aa0: 4604 mov r4, r0 8013aa2: e9c0 3300 strd r3, r3, [r0] 8013aa6: e9c0 3304 strd r3, r3, [r0, #16] 8013aaa: 6083 str r3, [r0, #8] 8013aac: 8181 strh r1, [r0, #12] 8013aae: 6643 str r3, [r0, #100] @ 0x64 8013ab0: 81c2 strh r2, [r0, #14] 8013ab2: 6183 str r3, [r0, #24] 8013ab4: 4619 mov r1, r3 8013ab6: 2208 movs r2, #8 8013ab8: 305c adds r0, #92 @ 0x5c 8013aba: f000 f8ff bl 8013cbc 8013abe: 4b0d ldr r3, [pc, #52] @ (8013af4 ) 8013ac0: 6224 str r4, [r4, #32] 8013ac2: 6263 str r3, [r4, #36] @ 0x24 8013ac4: 4b0c ldr r3, [pc, #48] @ (8013af8 ) 8013ac6: 62a3 str r3, [r4, #40] @ 0x28 8013ac8: 4b0c ldr r3, [pc, #48] @ (8013afc ) 8013aca: 62e3 str r3, [r4, #44] @ 0x2c 8013acc: 4b0c ldr r3, [pc, #48] @ (8013b00 ) 8013ace: 6323 str r3, [r4, #48] @ 0x30 8013ad0: 4b0c ldr r3, [pc, #48] @ (8013b04 ) 8013ad2: 429c cmp r4, r3 8013ad4: d006 beq.n 8013ae4 8013ad6: f103 0268 add.w r2, r3, #104 @ 0x68 8013ada: 4294 cmp r4, r2 8013adc: d002 beq.n 8013ae4 8013ade: 33d0 adds r3, #208 @ 0xd0 8013ae0: 429c cmp r4, r3 8013ae2: d105 bne.n 8013af0 8013ae4: f104 0058 add.w r0, r4, #88 @ 0x58 8013ae8: e8bd 4010 ldmia.w sp!, {r4, lr} 8013aec: f000 b918 b.w 8013d20 <__retarget_lock_init_recursive> 8013af0: bd10 pop {r4, pc} 8013af2: bf00 nop 8013af4: 08015941 .word 0x08015941 8013af8: 08015963 .word 0x08015963 8013afc: 0801599b .word 0x0801599b 8013b00: 080159bf .word 0x080159bf 8013b04: 20001208 .word 0x20001208 08013b08 : 8013b08: 4a02 ldr r2, [pc, #8] @ (8013b14 ) 8013b0a: 4903 ldr r1, [pc, #12] @ (8013b18 ) 8013b0c: 4803 ldr r0, [pc, #12] @ (8013b1c ) 8013b0e: f000 b8a5 b.w 8013c5c <_fwalk_sglue> 8013b12: bf00 nop 8013b14: 2000008c .word 0x2000008c 8013b18: 080151e5 .word 0x080151e5 8013b1c: 2000009c .word 0x2000009c 08013b20 : 8013b20: 6841 ldr r1, [r0, #4] 8013b22: 4b0c ldr r3, [pc, #48] @ (8013b54 ) 8013b24: b510 push {r4, lr} 8013b26: 4299 cmp r1, r3 8013b28: 4604 mov r4, r0 8013b2a: d001 beq.n 8013b30 8013b2c: f001 fb5a bl 80151e4 <_fflush_r> 8013b30: 68a1 ldr r1, [r4, #8] 8013b32: 4b09 ldr r3, [pc, #36] @ (8013b58 ) 8013b34: 4299 cmp r1, r3 8013b36: d002 beq.n 8013b3e 8013b38: 4620 mov r0, r4 8013b3a: f001 fb53 bl 80151e4 <_fflush_r> 8013b3e: 68e1 ldr r1, [r4, #12] 8013b40: 4b06 ldr r3, [pc, #24] @ (8013b5c ) 8013b42: 4299 cmp r1, r3 8013b44: d004 beq.n 8013b50 8013b46: 4620 mov r0, r4 8013b48: e8bd 4010 ldmia.w sp!, {r4, lr} 8013b4c: f001 bb4a b.w 80151e4 <_fflush_r> 8013b50: bd10 pop {r4, pc} 8013b52: bf00 nop 8013b54: 20001208 .word 0x20001208 8013b58: 20001270 .word 0x20001270 8013b5c: 200012d8 .word 0x200012d8 08013b60 : 8013b60: b510 push {r4, lr} 8013b62: 4b0b ldr r3, [pc, #44] @ (8013b90 ) 8013b64: 4c0b ldr r4, [pc, #44] @ (8013b94 ) 8013b66: 4a0c ldr r2, [pc, #48] @ (8013b98 ) 8013b68: 4620 mov r0, r4 8013b6a: 601a str r2, [r3, #0] 8013b6c: 2104 movs r1, #4 8013b6e: 2200 movs r2, #0 8013b70: f7ff ff94 bl 8013a9c 8013b74: f104 0068 add.w r0, r4, #104 @ 0x68 8013b78: 2201 movs r2, #1 8013b7a: 2109 movs r1, #9 8013b7c: f7ff ff8e bl 8013a9c 8013b80: f104 00d0 add.w r0, r4, #208 @ 0xd0 8013b84: 2202 movs r2, #2 8013b86: e8bd 4010 ldmia.w sp!, {r4, lr} 8013b8a: 2112 movs r1, #18 8013b8c: f7ff bf86 b.w 8013a9c 8013b90: 20001340 .word 0x20001340 8013b94: 20001208 .word 0x20001208 8013b98: 08013b09 .word 0x08013b09 08013b9c <__sfp_lock_acquire>: 8013b9c: 4801 ldr r0, [pc, #4] @ (8013ba4 <__sfp_lock_acquire+0x8>) 8013b9e: f000 b8c0 b.w 8013d22 <__retarget_lock_acquire_recursive> 8013ba2: bf00 nop 8013ba4: 20001345 .word 0x20001345 08013ba8 <__sfp_lock_release>: 8013ba8: 4801 ldr r0, [pc, #4] @ (8013bb0 <__sfp_lock_release+0x8>) 8013baa: f000 b8bb b.w 8013d24 <__retarget_lock_release_recursive> 8013bae: bf00 nop 8013bb0: 20001345 .word 0x20001345 08013bb4 <__sinit>: 8013bb4: b510 push {r4, lr} 8013bb6: 4604 mov r4, r0 8013bb8: f7ff fff0 bl 8013b9c <__sfp_lock_acquire> 8013bbc: 6a23 ldr r3, [r4, #32] 8013bbe: b11b cbz r3, 8013bc8 <__sinit+0x14> 8013bc0: e8bd 4010 ldmia.w sp!, {r4, lr} 8013bc4: f7ff bff0 b.w 8013ba8 <__sfp_lock_release> 8013bc8: 4b04 ldr r3, [pc, #16] @ (8013bdc <__sinit+0x28>) 8013bca: 6223 str r3, [r4, #32] 8013bcc: 4b04 ldr r3, [pc, #16] @ (8013be0 <__sinit+0x2c>) 8013bce: 681b ldr r3, [r3, #0] 8013bd0: 2b00 cmp r3, #0 8013bd2: d1f5 bne.n 8013bc0 <__sinit+0xc> 8013bd4: f7ff ffc4 bl 8013b60 8013bd8: e7f2 b.n 8013bc0 <__sinit+0xc> 8013bda: bf00 nop 8013bdc: 08013b21 .word 0x08013b21 8013be0: 20001340 .word 0x20001340 08013be4 <_vsniprintf_r>: 8013be4: b530 push {r4, r5, lr} 8013be6: 4614 mov r4, r2 8013be8: 2c00 cmp r4, #0 8013bea: 4605 mov r5, r0 8013bec: 461a mov r2, r3 8013bee: b09b sub sp, #108 @ 0x6c 8013bf0: da05 bge.n 8013bfe <_vsniprintf_r+0x1a> 8013bf2: 238b movs r3, #139 @ 0x8b 8013bf4: 6003 str r3, [r0, #0] 8013bf6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8013bfa: b01b add sp, #108 @ 0x6c 8013bfc: bd30 pop {r4, r5, pc} 8013bfe: f44f 7302 mov.w r3, #520 @ 0x208 8013c02: f8ad 300c strh.w r3, [sp, #12] 8013c06: f04f 0300 mov.w r3, #0 8013c0a: 9319 str r3, [sp, #100] @ 0x64 8013c0c: bf0c ite eq 8013c0e: 4623 moveq r3, r4 8013c10: f104 33ff addne.w r3, r4, #4294967295 @ 0xffffffff 8013c14: 9302 str r3, [sp, #8] 8013c16: 9305 str r3, [sp, #20] 8013c18: f64f 73ff movw r3, #65535 @ 0xffff 8013c1c: 9100 str r1, [sp, #0] 8013c1e: 9104 str r1, [sp, #16] 8013c20: f8ad 300e strh.w r3, [sp, #14] 8013c24: 4669 mov r1, sp 8013c26: 9b1e ldr r3, [sp, #120] @ 0x78 8013c28: f000 ff76 bl 8014b18 <_svfiprintf_r> 8013c2c: 1c43 adds r3, r0, #1 8013c2e: bfbc itt lt 8013c30: 238b movlt r3, #139 @ 0x8b 8013c32: 602b strlt r3, [r5, #0] 8013c34: 2c00 cmp r4, #0 8013c36: d0e0 beq.n 8013bfa <_vsniprintf_r+0x16> 8013c38: 2200 movs r2, #0 8013c3a: 9b00 ldr r3, [sp, #0] 8013c3c: 701a strb r2, [r3, #0] 8013c3e: e7dc b.n 8013bfa <_vsniprintf_r+0x16> 08013c40 : 8013c40: b507 push {r0, r1, r2, lr} 8013c42: 9300 str r3, [sp, #0] 8013c44: 4613 mov r3, r2 8013c46: 460a mov r2, r1 8013c48: 4601 mov r1, r0 8013c4a: 4803 ldr r0, [pc, #12] @ (8013c58 ) 8013c4c: 6800 ldr r0, [r0, #0] 8013c4e: f7ff ffc9 bl 8013be4 <_vsniprintf_r> 8013c52: b003 add sp, #12 8013c54: f85d fb04 ldr.w pc, [sp], #4 8013c58: 20000098 .word 0x20000098 08013c5c <_fwalk_sglue>: 8013c5c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8013c60: 4607 mov r7, r0 8013c62: 4688 mov r8, r1 8013c64: 4614 mov r4, r2 8013c66: 2600 movs r6, #0 8013c68: e9d4 9501 ldrd r9, r5, [r4, #4] 8013c6c: f1b9 0901 subs.w r9, r9, #1 8013c70: d505 bpl.n 8013c7e <_fwalk_sglue+0x22> 8013c72: 6824 ldr r4, [r4, #0] 8013c74: 2c00 cmp r4, #0 8013c76: d1f7 bne.n 8013c68 <_fwalk_sglue+0xc> 8013c78: 4630 mov r0, r6 8013c7a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8013c7e: 89ab ldrh r3, [r5, #12] 8013c80: 2b01 cmp r3, #1 8013c82: d907 bls.n 8013c94 <_fwalk_sglue+0x38> 8013c84: f9b5 300e ldrsh.w r3, [r5, #14] 8013c88: 3301 adds r3, #1 8013c8a: d003 beq.n 8013c94 <_fwalk_sglue+0x38> 8013c8c: 4629 mov r1, r5 8013c8e: 4638 mov r0, r7 8013c90: 47c0 blx r8 8013c92: 4306 orrs r6, r0 8013c94: 3568 adds r5, #104 @ 0x68 8013c96: e7e9 b.n 8013c6c <_fwalk_sglue+0x10> 08013c98 : 8013c98: b40f push {r0, r1, r2, r3} 8013c9a: b507 push {r0, r1, r2, lr} 8013c9c: 4906 ldr r1, [pc, #24] @ (8013cb8 ) 8013c9e: ab04 add r3, sp, #16 8013ca0: 6808 ldr r0, [r1, #0] 8013ca2: f853 2b04 ldr.w r2, [r3], #4 8013ca6: 6881 ldr r1, [r0, #8] 8013ca8: 9301 str r3, [sp, #4] 8013caa: f001 f859 bl 8014d60 <_vfiprintf_r> 8013cae: b003 add sp, #12 8013cb0: f85d eb04 ldr.w lr, [sp], #4 8013cb4: b004 add sp, #16 8013cb6: 4770 bx lr 8013cb8: 20000098 .word 0x20000098 08013cbc : 8013cbc: 4603 mov r3, r0 8013cbe: 4402 add r2, r0 8013cc0: 4293 cmp r3, r2 8013cc2: d100 bne.n 8013cc6 8013cc4: 4770 bx lr 8013cc6: f803 1b01 strb.w r1, [r3], #1 8013cca: e7f9 b.n 8013cc0 08013ccc <__errno>: 8013ccc: 4b01 ldr r3, [pc, #4] @ (8013cd4 <__errno+0x8>) 8013cce: 6818 ldr r0, [r3, #0] 8013cd0: 4770 bx lr 8013cd2: bf00 nop 8013cd4: 20000098 .word 0x20000098 08013cd8 <__libc_init_array>: 8013cd8: b570 push {r4, r5, r6, lr} 8013cda: 2600 movs r6, #0 8013cdc: 4d0c ldr r5, [pc, #48] @ (8013d10 <__libc_init_array+0x38>) 8013cde: 4c0d ldr r4, [pc, #52] @ (8013d14 <__libc_init_array+0x3c>) 8013ce0: 1b64 subs r4, r4, r5 8013ce2: 10a4 asrs r4, r4, #2 8013ce4: 42a6 cmp r6, r4 8013ce6: d109 bne.n 8013cfc <__libc_init_array+0x24> 8013ce8: f002 f906 bl 8015ef8 <_init> 8013cec: 2600 movs r6, #0 8013cee: 4d0a ldr r5, [pc, #40] @ (8013d18 <__libc_init_array+0x40>) 8013cf0: 4c0a ldr r4, [pc, #40] @ (8013d1c <__libc_init_array+0x44>) 8013cf2: 1b64 subs r4, r4, r5 8013cf4: 10a4 asrs r4, r4, #2 8013cf6: 42a6 cmp r6, r4 8013cf8: d105 bne.n 8013d06 <__libc_init_array+0x2e> 8013cfa: bd70 pop {r4, r5, r6, pc} 8013cfc: f855 3b04 ldr.w r3, [r5], #4 8013d00: 4798 blx r3 8013d02: 3601 adds r6, #1 8013d04: e7ee b.n 8013ce4 <__libc_init_array+0xc> 8013d06: f855 3b04 ldr.w r3, [r5], #4 8013d0a: 4798 blx r3 8013d0c: 3601 adds r6, #1 8013d0e: e7f2 b.n 8013cf6 <__libc_init_array+0x1e> 8013d10: 0801675c .word 0x0801675c 8013d14: 0801675c .word 0x0801675c 8013d18: 0801675c .word 0x0801675c 8013d1c: 08016760 .word 0x08016760 08013d20 <__retarget_lock_init_recursive>: 8013d20: 4770 bx lr 08013d22 <__retarget_lock_acquire_recursive>: 8013d22: 4770 bx lr 08013d24 <__retarget_lock_release_recursive>: 8013d24: 4770 bx lr ... 08013d28 <_localeconv_r>: 8013d28: 4800 ldr r0, [pc, #0] @ (8013d2c <_localeconv_r+0x4>) 8013d2a: 4770 bx lr 8013d2c: 200001d8 .word 0x200001d8 08013d30 : 8013d30: 4603 mov r3, r0 8013d32: b510 push {r4, lr} 8013d34: b2c9 uxtb r1, r1 8013d36: 4402 add r2, r0 8013d38: 4293 cmp r3, r2 8013d3a: 4618 mov r0, r3 8013d3c: d101 bne.n 8013d42 8013d3e: 2000 movs r0, #0 8013d40: e003 b.n 8013d4a 8013d42: 7804 ldrb r4, [r0, #0] 8013d44: 3301 adds r3, #1 8013d46: 428c cmp r4, r1 8013d48: d1f6 bne.n 8013d38 8013d4a: bd10 pop {r4, pc} 08013d4c : 8013d4c: 440a add r2, r1 8013d4e: 4291 cmp r1, r2 8013d50: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 8013d54: d100 bne.n 8013d58 8013d56: 4770 bx lr 8013d58: b510 push {r4, lr} 8013d5a: f811 4b01 ldrb.w r4, [r1], #1 8013d5e: 4291 cmp r1, r2 8013d60: f803 4f01 strb.w r4, [r3, #1]! 8013d64: d1f9 bne.n 8013d5a 8013d66: bd10 pop {r4, pc} 08013d68 <__assert_func>: 8013d68: b51f push {r0, r1, r2, r3, r4, lr} 8013d6a: 4614 mov r4, r2 8013d6c: 461a mov r2, r3 8013d6e: 4b09 ldr r3, [pc, #36] @ (8013d94 <__assert_func+0x2c>) 8013d70: 4605 mov r5, r0 8013d72: 681b ldr r3, [r3, #0] 8013d74: 68d8 ldr r0, [r3, #12] 8013d76: b14c cbz r4, 8013d8c <__assert_func+0x24> 8013d78: 4b07 ldr r3, [pc, #28] @ (8013d98 <__assert_func+0x30>) 8013d7a: e9cd 3401 strd r3, r4, [sp, #4] 8013d7e: 9100 str r1, [sp, #0] 8013d80: 462b mov r3, r5 8013d82: 4906 ldr r1, [pc, #24] @ (8013d9c <__assert_func+0x34>) 8013d84: f001 fe20 bl 80159c8 8013d88: f001 ffe6 bl 8015d58 8013d8c: 4b04 ldr r3, [pc, #16] @ (8013da0 <__assert_func+0x38>) 8013d8e: 461c mov r4, r3 8013d90: e7f3 b.n 8013d7a <__assert_func+0x12> 8013d92: bf00 nop 8013d94: 20000098 .word 0x20000098 8013d98: 08016410 .word 0x08016410 8013d9c: 0801641d .word 0x0801641d 8013da0: 0801644b .word 0x0801644b 08013da4 : 8013da4: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8013da8: 6903 ldr r3, [r0, #16] 8013daa: 690c ldr r4, [r1, #16] 8013dac: 4607 mov r7, r0 8013dae: 42a3 cmp r3, r4 8013db0: db7e blt.n 8013eb0 8013db2: 3c01 subs r4, #1 8013db4: 00a3 lsls r3, r4, #2 8013db6: f100 0514 add.w r5, r0, #20 8013dba: f101 0814 add.w r8, r1, #20 8013dbe: 9300 str r3, [sp, #0] 8013dc0: eb05 0384 add.w r3, r5, r4, lsl #2 8013dc4: 9301 str r3, [sp, #4] 8013dc6: f858 3024 ldr.w r3, [r8, r4, lsl #2] 8013dca: f855 2024 ldr.w r2, [r5, r4, lsl #2] 8013dce: 3301 adds r3, #1 8013dd0: 429a cmp r2, r3 8013dd2: fbb2 f6f3 udiv r6, r2, r3 8013dd6: eb08 0984 add.w r9, r8, r4, lsl #2 8013dda: d32e bcc.n 8013e3a 8013ddc: f04f 0a00 mov.w sl, #0 8013de0: 46c4 mov ip, r8 8013de2: 46ae mov lr, r5 8013de4: 46d3 mov fp, sl 8013de6: f85c 3b04 ldr.w r3, [ip], #4 8013dea: b298 uxth r0, r3 8013dec: fb06 a000 mla r0, r6, r0, sl 8013df0: 0c1b lsrs r3, r3, #16 8013df2: 0c02 lsrs r2, r0, #16 8013df4: fb06 2303 mla r3, r6, r3, r2 8013df8: f8de 2000 ldr.w r2, [lr] 8013dfc: b280 uxth r0, r0 8013dfe: b292 uxth r2, r2 8013e00: 1a12 subs r2, r2, r0 8013e02: 445a add r2, fp 8013e04: f8de 0000 ldr.w r0, [lr] 8013e08: ea4f 4a13 mov.w sl, r3, lsr #16 8013e0c: b29b uxth r3, r3 8013e0e: ebc3 4322 rsb r3, r3, r2, asr #16 8013e12: eb03 4310 add.w r3, r3, r0, lsr #16 8013e16: b292 uxth r2, r2 8013e18: ea42 4203 orr.w r2, r2, r3, lsl #16 8013e1c: 45e1 cmp r9, ip 8013e1e: ea4f 4b23 mov.w fp, r3, asr #16 8013e22: f84e 2b04 str.w r2, [lr], #4 8013e26: d2de bcs.n 8013de6 8013e28: 9b00 ldr r3, [sp, #0] 8013e2a: 58eb ldr r3, [r5, r3] 8013e2c: b92b cbnz r3, 8013e3a 8013e2e: 9b01 ldr r3, [sp, #4] 8013e30: 3b04 subs r3, #4 8013e32: 429d cmp r5, r3 8013e34: 461a mov r2, r3 8013e36: d32f bcc.n 8013e98 8013e38: 613c str r4, [r7, #16] 8013e3a: 4638 mov r0, r7 8013e3c: f001 fc78 bl 8015730 <__mcmp> 8013e40: 2800 cmp r0, #0 8013e42: db25 blt.n 8013e90 8013e44: 4629 mov r1, r5 8013e46: 2000 movs r0, #0 8013e48: f858 2b04 ldr.w r2, [r8], #4 8013e4c: f8d1 c000 ldr.w ip, [r1] 8013e50: fa1f fe82 uxth.w lr, r2 8013e54: fa1f f38c uxth.w r3, ip 8013e58: eba3 030e sub.w r3, r3, lr 8013e5c: 4403 add r3, r0 8013e5e: 0c12 lsrs r2, r2, #16 8013e60: ebc2 4223 rsb r2, r2, r3, asr #16 8013e64: eb02 421c add.w r2, r2, ip, lsr #16 8013e68: b29b uxth r3, r3 8013e6a: ea43 4302 orr.w r3, r3, r2, lsl #16 8013e6e: 45c1 cmp r9, r8 8013e70: ea4f 4022 mov.w r0, r2, asr #16 8013e74: f841 3b04 str.w r3, [r1], #4 8013e78: d2e6 bcs.n 8013e48 8013e7a: f855 2024 ldr.w r2, [r5, r4, lsl #2] 8013e7e: eb05 0384 add.w r3, r5, r4, lsl #2 8013e82: b922 cbnz r2, 8013e8e 8013e84: 3b04 subs r3, #4 8013e86: 429d cmp r5, r3 8013e88: 461a mov r2, r3 8013e8a: d30b bcc.n 8013ea4 8013e8c: 613c str r4, [r7, #16] 8013e8e: 3601 adds r6, #1 8013e90: 4630 mov r0, r6 8013e92: b003 add sp, #12 8013e94: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8013e98: 6812 ldr r2, [r2, #0] 8013e9a: 3b04 subs r3, #4 8013e9c: 2a00 cmp r2, #0 8013e9e: d1cb bne.n 8013e38 8013ea0: 3c01 subs r4, #1 8013ea2: e7c6 b.n 8013e32 8013ea4: 6812 ldr r2, [r2, #0] 8013ea6: 3b04 subs r3, #4 8013ea8: 2a00 cmp r2, #0 8013eaa: d1ef bne.n 8013e8c 8013eac: 3c01 subs r4, #1 8013eae: e7ea b.n 8013e86 8013eb0: 2000 movs r0, #0 8013eb2: e7ee b.n 8013e92 8013eb4: 0000 movs r0, r0 ... 08013eb8 <_dtoa_r>: 8013eb8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8013ebc: 4614 mov r4, r2 8013ebe: 461d mov r5, r3 8013ec0: 69c7 ldr r7, [r0, #28] 8013ec2: b097 sub sp, #92 @ 0x5c 8013ec4: 4681 mov r9, r0 8013ec6: e9cd 4506 strd r4, r5, [sp, #24] 8013eca: 9e23 ldr r6, [sp, #140] @ 0x8c 8013ecc: b97f cbnz r7, 8013eee <_dtoa_r+0x36> 8013ece: 2010 movs r0, #16 8013ed0: f001 f85e bl 8014f90 8013ed4: 4602 mov r2, r0 8013ed6: f8c9 001c str.w r0, [r9, #28] 8013eda: b920 cbnz r0, 8013ee6 <_dtoa_r+0x2e> 8013edc: 21ef movs r1, #239 @ 0xef 8013ede: 4bac ldr r3, [pc, #688] @ (8014190 <_dtoa_r+0x2d8>) 8013ee0: 48ac ldr r0, [pc, #688] @ (8014194 <_dtoa_r+0x2dc>) 8013ee2: f7ff ff41 bl 8013d68 <__assert_func> 8013ee6: e9c0 7701 strd r7, r7, [r0, #4] 8013eea: 6007 str r7, [r0, #0] 8013eec: 60c7 str r7, [r0, #12] 8013eee: f8d9 301c ldr.w r3, [r9, #28] 8013ef2: 6819 ldr r1, [r3, #0] 8013ef4: b159 cbz r1, 8013f0e <_dtoa_r+0x56> 8013ef6: 685a ldr r2, [r3, #4] 8013ef8: 2301 movs r3, #1 8013efa: 4093 lsls r3, r2 8013efc: 604a str r2, [r1, #4] 8013efe: 608b str r3, [r1, #8] 8013f00: 4648 mov r0, r9 8013f02: f001 f9e3 bl 80152cc <_Bfree> 8013f06: 2200 movs r2, #0 8013f08: f8d9 301c ldr.w r3, [r9, #28] 8013f0c: 601a str r2, [r3, #0] 8013f0e: 1e2b subs r3, r5, #0 8013f10: bfaf iteee ge 8013f12: 2300 movge r3, #0 8013f14: 2201 movlt r2, #1 8013f16: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000 8013f1a: 9307 strlt r3, [sp, #28] 8013f1c: bfa8 it ge 8013f1e: 6033 strge r3, [r6, #0] 8013f20: f8dd 801c ldr.w r8, [sp, #28] 8013f24: 4b9c ldr r3, [pc, #624] @ (8014198 <_dtoa_r+0x2e0>) 8013f26: bfb8 it lt 8013f28: 6032 strlt r2, [r6, #0] 8013f2a: ea33 0308 bics.w r3, r3, r8 8013f2e: d112 bne.n 8013f56 <_dtoa_r+0x9e> 8013f30: f242 730f movw r3, #9999 @ 0x270f 8013f34: 9a22 ldr r2, [sp, #136] @ 0x88 8013f36: 6013 str r3, [r2, #0] 8013f38: f3c8 0313 ubfx r3, r8, #0, #20 8013f3c: 4323 orrs r3, r4 8013f3e: f000 855e beq.w 80149fe <_dtoa_r+0xb46> 8013f42: 9b24 ldr r3, [sp, #144] @ 0x90 8013f44: f8df a254 ldr.w sl, [pc, #596] @ 801419c <_dtoa_r+0x2e4> 8013f48: 2b00 cmp r3, #0 8013f4a: f000 8560 beq.w 8014a0e <_dtoa_r+0xb56> 8013f4e: f10a 0303 add.w r3, sl, #3 8013f52: f000 bd5a b.w 8014a0a <_dtoa_r+0xb52> 8013f56: e9dd 2306 ldrd r2, r3, [sp, #24] 8013f5a: e9cd 230c strd r2, r3, [sp, #48] @ 0x30 8013f5e: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8013f62: 2200 movs r2, #0 8013f64: 2300 movs r3, #0 8013f66: f7f4 fd8b bl 8008a80 <__aeabi_dcmpeq> 8013f6a: 4607 mov r7, r0 8013f6c: b158 cbz r0, 8013f86 <_dtoa_r+0xce> 8013f6e: 2301 movs r3, #1 8013f70: 9a22 ldr r2, [sp, #136] @ 0x88 8013f72: 6013 str r3, [r2, #0] 8013f74: 9b24 ldr r3, [sp, #144] @ 0x90 8013f76: b113 cbz r3, 8013f7e <_dtoa_r+0xc6> 8013f78: 4b89 ldr r3, [pc, #548] @ (80141a0 <_dtoa_r+0x2e8>) 8013f7a: 9a24 ldr r2, [sp, #144] @ 0x90 8013f7c: 6013 str r3, [r2, #0] 8013f7e: f8df a224 ldr.w sl, [pc, #548] @ 80141a4 <_dtoa_r+0x2ec> 8013f82: f000 bd44 b.w 8014a0e <_dtoa_r+0xb56> 8013f86: ab14 add r3, sp, #80 @ 0x50 8013f88: 9301 str r3, [sp, #4] 8013f8a: ab15 add r3, sp, #84 @ 0x54 8013f8c: 9300 str r3, [sp, #0] 8013f8e: 4648 mov r0, r9 8013f90: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30 8013f94: f001 fc7c bl 8015890 <__d2b> 8013f98: f3c8 560a ubfx r6, r8, #20, #11 8013f9c: 9003 str r0, [sp, #12] 8013f9e: 2e00 cmp r6, #0 8013fa0: d078 beq.n 8014094 <_dtoa_r+0x1dc> 8013fa2: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8013fa6: 9b0d ldr r3, [sp, #52] @ 0x34 8013fa8: f2a6 36ff subw r6, r6, #1023 @ 0x3ff 8013fac: f3c3 0313 ubfx r3, r3, #0, #20 8013fb0: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000 8013fb4: f443 1340 orr.w r3, r3, #3145728 @ 0x300000 8013fb8: 9712 str r7, [sp, #72] @ 0x48 8013fba: 4619 mov r1, r3 8013fbc: 2200 movs r2, #0 8013fbe: 4b7a ldr r3, [pc, #488] @ (80141a8 <_dtoa_r+0x2f0>) 8013fc0: f7f4 f93e bl 8008240 <__aeabi_dsub> 8013fc4: a36c add r3, pc, #432 @ (adr r3, 8014178 <_dtoa_r+0x2c0>) 8013fc6: e9d3 2300 ldrd r2, r3, [r3] 8013fca: f7f4 faf1 bl 80085b0 <__aeabi_dmul> 8013fce: a36c add r3, pc, #432 @ (adr r3, 8014180 <_dtoa_r+0x2c8>) 8013fd0: e9d3 2300 ldrd r2, r3, [r3] 8013fd4: f7f4 f936 bl 8008244 <__adddf3> 8013fd8: 4604 mov r4, r0 8013fda: 4630 mov r0, r6 8013fdc: 460d mov r5, r1 8013fde: f7f4 fa7d bl 80084dc <__aeabi_i2d> 8013fe2: a369 add r3, pc, #420 @ (adr r3, 8014188 <_dtoa_r+0x2d0>) 8013fe4: e9d3 2300 ldrd r2, r3, [r3] 8013fe8: f7f4 fae2 bl 80085b0 <__aeabi_dmul> 8013fec: 4602 mov r2, r0 8013fee: 460b mov r3, r1 8013ff0: 4620 mov r0, r4 8013ff2: 4629 mov r1, r5 8013ff4: f7f4 f926 bl 8008244 <__adddf3> 8013ff8: 4604 mov r4, r0 8013ffa: 460d mov r5, r1 8013ffc: f7f4 fd88 bl 8008b10 <__aeabi_d2iz> 8014000: 2200 movs r2, #0 8014002: 4607 mov r7, r0 8014004: 2300 movs r3, #0 8014006: 4620 mov r0, r4 8014008: 4629 mov r1, r5 801400a: f7f4 fd43 bl 8008a94 <__aeabi_dcmplt> 801400e: b140 cbz r0, 8014022 <_dtoa_r+0x16a> 8014010: 4638 mov r0, r7 8014012: f7f4 fa63 bl 80084dc <__aeabi_i2d> 8014016: 4622 mov r2, r4 8014018: 462b mov r3, r5 801401a: f7f4 fd31 bl 8008a80 <__aeabi_dcmpeq> 801401e: b900 cbnz r0, 8014022 <_dtoa_r+0x16a> 8014020: 3f01 subs r7, #1 8014022: 2f16 cmp r7, #22 8014024: d854 bhi.n 80140d0 <_dtoa_r+0x218> 8014026: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 801402a: 4b60 ldr r3, [pc, #384] @ (80141ac <_dtoa_r+0x2f4>) 801402c: eb03 03c7 add.w r3, r3, r7, lsl #3 8014030: e9d3 2300 ldrd r2, r3, [r3] 8014034: f7f4 fd2e bl 8008a94 <__aeabi_dcmplt> 8014038: 2800 cmp r0, #0 801403a: d04b beq.n 80140d4 <_dtoa_r+0x21c> 801403c: 2300 movs r3, #0 801403e: 3f01 subs r7, #1 8014040: 930f str r3, [sp, #60] @ 0x3c 8014042: 9b14 ldr r3, [sp, #80] @ 0x50 8014044: 1b9b subs r3, r3, r6 8014046: 1e5a subs r2, r3, #1 8014048: bf49 itett mi 801404a: f1c3 0301 rsbmi r3, r3, #1 801404e: 2300 movpl r3, #0 8014050: 9304 strmi r3, [sp, #16] 8014052: 2300 movmi r3, #0 8014054: 9209 str r2, [sp, #36] @ 0x24 8014056: bf54 ite pl 8014058: 9304 strpl r3, [sp, #16] 801405a: 9309 strmi r3, [sp, #36] @ 0x24 801405c: 2f00 cmp r7, #0 801405e: db3b blt.n 80140d8 <_dtoa_r+0x220> 8014060: 9b09 ldr r3, [sp, #36] @ 0x24 8014062: 970e str r7, [sp, #56] @ 0x38 8014064: 443b add r3, r7 8014066: 9309 str r3, [sp, #36] @ 0x24 8014068: 2300 movs r3, #0 801406a: 930a str r3, [sp, #40] @ 0x28 801406c: 9b20 ldr r3, [sp, #128] @ 0x80 801406e: 2b09 cmp r3, #9 8014070: d865 bhi.n 801413e <_dtoa_r+0x286> 8014072: 2b05 cmp r3, #5 8014074: bfc4 itt gt 8014076: 3b04 subgt r3, #4 8014078: 9320 strgt r3, [sp, #128] @ 0x80 801407a: 9b20 ldr r3, [sp, #128] @ 0x80 801407c: bfc8 it gt 801407e: 2400 movgt r4, #0 8014080: f1a3 0302 sub.w r3, r3, #2 8014084: bfd8 it le 8014086: 2401 movle r4, #1 8014088: 2b03 cmp r3, #3 801408a: d864 bhi.n 8014156 <_dtoa_r+0x29e> 801408c: e8df f003 tbb [pc, r3] 8014090: 2c385553 .word 0x2c385553 8014094: e9dd 6314 ldrd r6, r3, [sp, #80] @ 0x50 8014098: 441e add r6, r3 801409a: f206 4332 addw r3, r6, #1074 @ 0x432 801409e: 2b20 cmp r3, #32 80140a0: bfc1 itttt gt 80140a2: f1c3 0340 rsbgt r3, r3, #64 @ 0x40 80140a6: fa08 f803 lslgt.w r8, r8, r3 80140aa: f206 4312 addwgt r3, r6, #1042 @ 0x412 80140ae: fa24 f303 lsrgt.w r3, r4, r3 80140b2: bfd6 itet le 80140b4: f1c3 0320 rsble r3, r3, #32 80140b8: ea48 0003 orrgt.w r0, r8, r3 80140bc: fa04 f003 lslle.w r0, r4, r3 80140c0: f7f4 f9fc bl 80084bc <__aeabi_ui2d> 80140c4: 2201 movs r2, #1 80140c6: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000 80140ca: 3e01 subs r6, #1 80140cc: 9212 str r2, [sp, #72] @ 0x48 80140ce: e774 b.n 8013fba <_dtoa_r+0x102> 80140d0: 2301 movs r3, #1 80140d2: e7b5 b.n 8014040 <_dtoa_r+0x188> 80140d4: 900f str r0, [sp, #60] @ 0x3c 80140d6: e7b4 b.n 8014042 <_dtoa_r+0x18a> 80140d8: 9b04 ldr r3, [sp, #16] 80140da: 1bdb subs r3, r3, r7 80140dc: 9304 str r3, [sp, #16] 80140de: 427b negs r3, r7 80140e0: 930a str r3, [sp, #40] @ 0x28 80140e2: 2300 movs r3, #0 80140e4: 930e str r3, [sp, #56] @ 0x38 80140e6: e7c1 b.n 801406c <_dtoa_r+0x1b4> 80140e8: 2301 movs r3, #1 80140ea: 930b str r3, [sp, #44] @ 0x2c 80140ec: 9b21 ldr r3, [sp, #132] @ 0x84 80140ee: eb07 0b03 add.w fp, r7, r3 80140f2: f10b 0301 add.w r3, fp, #1 80140f6: 2b01 cmp r3, #1 80140f8: 9308 str r3, [sp, #32] 80140fa: bfb8 it lt 80140fc: 2301 movlt r3, #1 80140fe: e006 b.n 801410e <_dtoa_r+0x256> 8014100: 2301 movs r3, #1 8014102: 930b str r3, [sp, #44] @ 0x2c 8014104: 9b21 ldr r3, [sp, #132] @ 0x84 8014106: 2b00 cmp r3, #0 8014108: dd28 ble.n 801415c <_dtoa_r+0x2a4> 801410a: 469b mov fp, r3 801410c: 9308 str r3, [sp, #32] 801410e: 2100 movs r1, #0 8014110: 2204 movs r2, #4 8014112: f8d9 001c ldr.w r0, [r9, #28] 8014116: f102 0514 add.w r5, r2, #20 801411a: 429d cmp r5, r3 801411c: d926 bls.n 801416c <_dtoa_r+0x2b4> 801411e: 6041 str r1, [r0, #4] 8014120: 4648 mov r0, r9 8014122: f001 f893 bl 801524c <_Balloc> 8014126: 4682 mov sl, r0 8014128: 2800 cmp r0, #0 801412a: d143 bne.n 80141b4 <_dtoa_r+0x2fc> 801412c: 4602 mov r2, r0 801412e: f240 11af movw r1, #431 @ 0x1af 8014132: 4b1f ldr r3, [pc, #124] @ (80141b0 <_dtoa_r+0x2f8>) 8014134: e6d4 b.n 8013ee0 <_dtoa_r+0x28> 8014136: 2300 movs r3, #0 8014138: e7e3 b.n 8014102 <_dtoa_r+0x24a> 801413a: 2300 movs r3, #0 801413c: e7d5 b.n 80140ea <_dtoa_r+0x232> 801413e: 2401 movs r4, #1 8014140: 2300 movs r3, #0 8014142: 940b str r4, [sp, #44] @ 0x2c 8014144: 9320 str r3, [sp, #128] @ 0x80 8014146: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff 801414a: 2200 movs r2, #0 801414c: 2312 movs r3, #18 801414e: f8cd b020 str.w fp, [sp, #32] 8014152: 9221 str r2, [sp, #132] @ 0x84 8014154: e7db b.n 801410e <_dtoa_r+0x256> 8014156: 2301 movs r3, #1 8014158: 930b str r3, [sp, #44] @ 0x2c 801415a: e7f4 b.n 8014146 <_dtoa_r+0x28e> 801415c: f04f 0b01 mov.w fp, #1 8014160: 465b mov r3, fp 8014162: f8cd b020 str.w fp, [sp, #32] 8014166: f8cd b084 str.w fp, [sp, #132] @ 0x84 801416a: e7d0 b.n 801410e <_dtoa_r+0x256> 801416c: 3101 adds r1, #1 801416e: 0052 lsls r2, r2, #1 8014170: e7d1 b.n 8014116 <_dtoa_r+0x25e> 8014172: bf00 nop 8014174: f3af 8000 nop.w 8014178: 636f4361 .word 0x636f4361 801417c: 3fd287a7 .word 0x3fd287a7 8014180: 8b60c8b3 .word 0x8b60c8b3 8014184: 3fc68a28 .word 0x3fc68a28 8014188: 509f79fb .word 0x509f79fb 801418c: 3fd34413 .word 0x3fd34413 8014190: 08016459 .word 0x08016459 8014194: 08016470 .word 0x08016470 8014198: 7ff00000 .word 0x7ff00000 801419c: 08016455 .word 0x08016455 80141a0: 080163ed .word 0x080163ed 80141a4: 080163ec .word 0x080163ec 80141a8: 3ff80000 .word 0x3ff80000 80141ac: 08016588 .word 0x08016588 80141b0: 080164c8 .word 0x080164c8 80141b4: f8d9 301c ldr.w r3, [r9, #28] 80141b8: 6018 str r0, [r3, #0] 80141ba: 9b08 ldr r3, [sp, #32] 80141bc: 2b0e cmp r3, #14 80141be: f200 80a1 bhi.w 8014304 <_dtoa_r+0x44c> 80141c2: 2c00 cmp r4, #0 80141c4: f000 809e beq.w 8014304 <_dtoa_r+0x44c> 80141c8: 2f00 cmp r7, #0 80141ca: dd33 ble.n 8014234 <_dtoa_r+0x37c> 80141cc: 4b9c ldr r3, [pc, #624] @ (8014440 <_dtoa_r+0x588>) 80141ce: f007 020f and.w r2, r7, #15 80141d2: eb03 03c2 add.w r3, r3, r2, lsl #3 80141d6: 05f8 lsls r0, r7, #23 80141d8: e9d3 3400 ldrd r3, r4, [r3] 80141dc: e9cd 3410 strd r3, r4, [sp, #64] @ 0x40 80141e0: ea4f 1427 mov.w r4, r7, asr #4 80141e4: d516 bpl.n 8014214 <_dtoa_r+0x35c> 80141e6: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 80141ea: 4b96 ldr r3, [pc, #600] @ (8014444 <_dtoa_r+0x58c>) 80141ec: 2603 movs r6, #3 80141ee: e9d3 2308 ldrd r2, r3, [r3, #32] 80141f2: f7f4 fb07 bl 8008804 <__aeabi_ddiv> 80141f6: e9cd 0106 strd r0, r1, [sp, #24] 80141fa: f004 040f and.w r4, r4, #15 80141fe: 4d91 ldr r5, [pc, #580] @ (8014444 <_dtoa_r+0x58c>) 8014200: b954 cbnz r4, 8014218 <_dtoa_r+0x360> 8014202: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 8014206: e9dd 0106 ldrd r0, r1, [sp, #24] 801420a: f7f4 fafb bl 8008804 <__aeabi_ddiv> 801420e: e9cd 0106 strd r0, r1, [sp, #24] 8014212: e028 b.n 8014266 <_dtoa_r+0x3ae> 8014214: 2602 movs r6, #2 8014216: e7f2 b.n 80141fe <_dtoa_r+0x346> 8014218: 07e1 lsls r1, r4, #31 801421a: d508 bpl.n 801422e <_dtoa_r+0x376> 801421c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 8014220: e9d5 2300 ldrd r2, r3, [r5] 8014224: f7f4 f9c4 bl 80085b0 <__aeabi_dmul> 8014228: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 801422c: 3601 adds r6, #1 801422e: 1064 asrs r4, r4, #1 8014230: 3508 adds r5, #8 8014232: e7e5 b.n 8014200 <_dtoa_r+0x348> 8014234: f000 80af beq.w 8014396 <_dtoa_r+0x4de> 8014238: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 801423c: 427c negs r4, r7 801423e: 4b80 ldr r3, [pc, #512] @ (8014440 <_dtoa_r+0x588>) 8014240: f004 020f and.w r2, r4, #15 8014244: eb03 03c2 add.w r3, r3, r2, lsl #3 8014248: e9d3 2300 ldrd r2, r3, [r3] 801424c: f7f4 f9b0 bl 80085b0 <__aeabi_dmul> 8014250: 2602 movs r6, #2 8014252: 2300 movs r3, #0 8014254: e9cd 0106 strd r0, r1, [sp, #24] 8014258: 4d7a ldr r5, [pc, #488] @ (8014444 <_dtoa_r+0x58c>) 801425a: 1124 asrs r4, r4, #4 801425c: 2c00 cmp r4, #0 801425e: f040 808f bne.w 8014380 <_dtoa_r+0x4c8> 8014262: 2b00 cmp r3, #0 8014264: d1d3 bne.n 801420e <_dtoa_r+0x356> 8014266: e9dd 4506 ldrd r4, r5, [sp, #24] 801426a: 9b0f ldr r3, [sp, #60] @ 0x3c 801426c: 2b00 cmp r3, #0 801426e: f000 8094 beq.w 801439a <_dtoa_r+0x4e2> 8014272: 2200 movs r2, #0 8014274: 4620 mov r0, r4 8014276: 4629 mov r1, r5 8014278: 4b73 ldr r3, [pc, #460] @ (8014448 <_dtoa_r+0x590>) 801427a: f7f4 fc0b bl 8008a94 <__aeabi_dcmplt> 801427e: 2800 cmp r0, #0 8014280: f000 808b beq.w 801439a <_dtoa_r+0x4e2> 8014284: 9b08 ldr r3, [sp, #32] 8014286: 2b00 cmp r3, #0 8014288: f000 8087 beq.w 801439a <_dtoa_r+0x4e2> 801428c: f1bb 0f00 cmp.w fp, #0 8014290: dd34 ble.n 80142fc <_dtoa_r+0x444> 8014292: 4620 mov r0, r4 8014294: 2200 movs r2, #0 8014296: 4629 mov r1, r5 8014298: 4b6c ldr r3, [pc, #432] @ (801444c <_dtoa_r+0x594>) 801429a: f7f4 f989 bl 80085b0 <__aeabi_dmul> 801429e: 465c mov r4, fp 80142a0: e9cd 0106 strd r0, r1, [sp, #24] 80142a4: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff 80142a8: 3601 adds r6, #1 80142aa: 4630 mov r0, r6 80142ac: f7f4 f916 bl 80084dc <__aeabi_i2d> 80142b0: e9dd 2306 ldrd r2, r3, [sp, #24] 80142b4: f7f4 f97c bl 80085b0 <__aeabi_dmul> 80142b8: 2200 movs r2, #0 80142ba: 4b65 ldr r3, [pc, #404] @ (8014450 <_dtoa_r+0x598>) 80142bc: f7f3 ffc2 bl 8008244 <__adddf3> 80142c0: 4605 mov r5, r0 80142c2: f1a1 7650 sub.w r6, r1, #54525952 @ 0x3400000 80142c6: 2c00 cmp r4, #0 80142c8: d16a bne.n 80143a0 <_dtoa_r+0x4e8> 80142ca: e9dd 0106 ldrd r0, r1, [sp, #24] 80142ce: 2200 movs r2, #0 80142d0: 4b60 ldr r3, [pc, #384] @ (8014454 <_dtoa_r+0x59c>) 80142d2: f7f3 ffb5 bl 8008240 <__aeabi_dsub> 80142d6: 4602 mov r2, r0 80142d8: 460b mov r3, r1 80142da: e9cd 2306 strd r2, r3, [sp, #24] 80142de: 462a mov r2, r5 80142e0: 4633 mov r3, r6 80142e2: f7f4 fbf5 bl 8008ad0 <__aeabi_dcmpgt> 80142e6: 2800 cmp r0, #0 80142e8: f040 8298 bne.w 801481c <_dtoa_r+0x964> 80142ec: e9dd 0106 ldrd r0, r1, [sp, #24] 80142f0: 462a mov r2, r5 80142f2: f106 4300 add.w r3, r6, #2147483648 @ 0x80000000 80142f6: f7f4 fbcd bl 8008a94 <__aeabi_dcmplt> 80142fa: bb38 cbnz r0, 801434c <_dtoa_r+0x494> 80142fc: e9dd 340c ldrd r3, r4, [sp, #48] @ 0x30 8014300: e9cd 3406 strd r3, r4, [sp, #24] 8014304: 9b15 ldr r3, [sp, #84] @ 0x54 8014306: 2b00 cmp r3, #0 8014308: f2c0 8157 blt.w 80145ba <_dtoa_r+0x702> 801430c: 2f0e cmp r7, #14 801430e: f300 8154 bgt.w 80145ba <_dtoa_r+0x702> 8014312: 4b4b ldr r3, [pc, #300] @ (8014440 <_dtoa_r+0x588>) 8014314: eb03 03c7 add.w r3, r3, r7, lsl #3 8014318: e9d3 3400 ldrd r3, r4, [r3] 801431c: e9cd 3404 strd r3, r4, [sp, #16] 8014320: 9b21 ldr r3, [sp, #132] @ 0x84 8014322: 2b00 cmp r3, #0 8014324: f280 80e5 bge.w 80144f2 <_dtoa_r+0x63a> 8014328: 9b08 ldr r3, [sp, #32] 801432a: 2b00 cmp r3, #0 801432c: f300 80e1 bgt.w 80144f2 <_dtoa_r+0x63a> 8014330: d10c bne.n 801434c <_dtoa_r+0x494> 8014332: e9dd 0104 ldrd r0, r1, [sp, #16] 8014336: 2200 movs r2, #0 8014338: 4b46 ldr r3, [pc, #280] @ (8014454 <_dtoa_r+0x59c>) 801433a: f7f4 f939 bl 80085b0 <__aeabi_dmul> 801433e: e9dd 2306 ldrd r2, r3, [sp, #24] 8014342: f7f4 fbbb bl 8008abc <__aeabi_dcmpge> 8014346: 2800 cmp r0, #0 8014348: f000 8266 beq.w 8014818 <_dtoa_r+0x960> 801434c: 2400 movs r4, #0 801434e: 4625 mov r5, r4 8014350: 9b21 ldr r3, [sp, #132] @ 0x84 8014352: 4656 mov r6, sl 8014354: ea6f 0803 mvn.w r8, r3 8014358: 2700 movs r7, #0 801435a: 4621 mov r1, r4 801435c: 4648 mov r0, r9 801435e: f000 ffb5 bl 80152cc <_Bfree> 8014362: 2d00 cmp r5, #0 8014364: f000 80bd beq.w 80144e2 <_dtoa_r+0x62a> 8014368: b12f cbz r7, 8014376 <_dtoa_r+0x4be> 801436a: 42af cmp r7, r5 801436c: d003 beq.n 8014376 <_dtoa_r+0x4be> 801436e: 4639 mov r1, r7 8014370: 4648 mov r0, r9 8014372: f000 ffab bl 80152cc <_Bfree> 8014376: 4629 mov r1, r5 8014378: 4648 mov r0, r9 801437a: f000 ffa7 bl 80152cc <_Bfree> 801437e: e0b0 b.n 80144e2 <_dtoa_r+0x62a> 8014380: 07e2 lsls r2, r4, #31 8014382: d505 bpl.n 8014390 <_dtoa_r+0x4d8> 8014384: e9d5 2300 ldrd r2, r3, [r5] 8014388: f7f4 f912 bl 80085b0 <__aeabi_dmul> 801438c: 2301 movs r3, #1 801438e: 3601 adds r6, #1 8014390: 1064 asrs r4, r4, #1 8014392: 3508 adds r5, #8 8014394: e762 b.n 801425c <_dtoa_r+0x3a4> 8014396: 2602 movs r6, #2 8014398: e765 b.n 8014266 <_dtoa_r+0x3ae> 801439a: 46b8 mov r8, r7 801439c: 9c08 ldr r4, [sp, #32] 801439e: e784 b.n 80142aa <_dtoa_r+0x3f2> 80143a0: 4b27 ldr r3, [pc, #156] @ (8014440 <_dtoa_r+0x588>) 80143a2: 990b ldr r1, [sp, #44] @ 0x2c 80143a4: eb03 03c4 add.w r3, r3, r4, lsl #3 80143a8: e953 2302 ldrd r2, r3, [r3, #-8] 80143ac: 4454 add r4, sl 80143ae: 2900 cmp r1, #0 80143b0: d054 beq.n 801445c <_dtoa_r+0x5a4> 80143b2: 2000 movs r0, #0 80143b4: 4928 ldr r1, [pc, #160] @ (8014458 <_dtoa_r+0x5a0>) 80143b6: f7f4 fa25 bl 8008804 <__aeabi_ddiv> 80143ba: 4633 mov r3, r6 80143bc: 462a mov r2, r5 80143be: f7f3 ff3f bl 8008240 <__aeabi_dsub> 80143c2: 4656 mov r6, sl 80143c4: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 80143c8: e9dd 0106 ldrd r0, r1, [sp, #24] 80143cc: f7f4 fba0 bl 8008b10 <__aeabi_d2iz> 80143d0: 4605 mov r5, r0 80143d2: f7f4 f883 bl 80084dc <__aeabi_i2d> 80143d6: 4602 mov r2, r0 80143d8: 460b mov r3, r1 80143da: e9dd 0106 ldrd r0, r1, [sp, #24] 80143de: f7f3 ff2f bl 8008240 <__aeabi_dsub> 80143e2: 4602 mov r2, r0 80143e4: 460b mov r3, r1 80143e6: 3530 adds r5, #48 @ 0x30 80143e8: e9cd 2306 strd r2, r3, [sp, #24] 80143ec: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 80143f0: f806 5b01 strb.w r5, [r6], #1 80143f4: f7f4 fb4e bl 8008a94 <__aeabi_dcmplt> 80143f8: 2800 cmp r0, #0 80143fa: d172 bne.n 80144e2 <_dtoa_r+0x62a> 80143fc: e9dd 2306 ldrd r2, r3, [sp, #24] 8014400: 2000 movs r0, #0 8014402: 4911 ldr r1, [pc, #68] @ (8014448 <_dtoa_r+0x590>) 8014404: f7f3 ff1c bl 8008240 <__aeabi_dsub> 8014408: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 801440c: f7f4 fb42 bl 8008a94 <__aeabi_dcmplt> 8014410: 2800 cmp r0, #0 8014412: f040 80b4 bne.w 801457e <_dtoa_r+0x6c6> 8014416: 42a6 cmp r6, r4 8014418: f43f af70 beq.w 80142fc <_dtoa_r+0x444> 801441c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 8014420: 2200 movs r2, #0 8014422: 4b0a ldr r3, [pc, #40] @ (801444c <_dtoa_r+0x594>) 8014424: f7f4 f8c4 bl 80085b0 <__aeabi_dmul> 8014428: 2200 movs r2, #0 801442a: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 801442e: e9dd 0106 ldrd r0, r1, [sp, #24] 8014432: 4b06 ldr r3, [pc, #24] @ (801444c <_dtoa_r+0x594>) 8014434: f7f4 f8bc bl 80085b0 <__aeabi_dmul> 8014438: e9cd 0106 strd r0, r1, [sp, #24] 801443c: e7c4 b.n 80143c8 <_dtoa_r+0x510> 801443e: bf00 nop 8014440: 08016588 .word 0x08016588 8014444: 08016560 .word 0x08016560 8014448: 3ff00000 .word 0x3ff00000 801444c: 40240000 .word 0x40240000 8014450: 401c0000 .word 0x401c0000 8014454: 40140000 .word 0x40140000 8014458: 3fe00000 .word 0x3fe00000 801445c: 4631 mov r1, r6 801445e: 4628 mov r0, r5 8014460: f7f4 f8a6 bl 80085b0 <__aeabi_dmul> 8014464: 4656 mov r6, sl 8014466: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 801446a: 9413 str r4, [sp, #76] @ 0x4c 801446c: e9dd 0106 ldrd r0, r1, [sp, #24] 8014470: f7f4 fb4e bl 8008b10 <__aeabi_d2iz> 8014474: 4605 mov r5, r0 8014476: f7f4 f831 bl 80084dc <__aeabi_i2d> 801447a: 4602 mov r2, r0 801447c: 460b mov r3, r1 801447e: e9dd 0106 ldrd r0, r1, [sp, #24] 8014482: f7f3 fedd bl 8008240 <__aeabi_dsub> 8014486: 4602 mov r2, r0 8014488: 460b mov r3, r1 801448a: 3530 adds r5, #48 @ 0x30 801448c: f806 5b01 strb.w r5, [r6], #1 8014490: 42a6 cmp r6, r4 8014492: e9cd 2306 strd r2, r3, [sp, #24] 8014496: f04f 0200 mov.w r2, #0 801449a: d124 bne.n 80144e6 <_dtoa_r+0x62e> 801449c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 80144a0: 4bae ldr r3, [pc, #696] @ (801475c <_dtoa_r+0x8a4>) 80144a2: f7f3 fecf bl 8008244 <__adddf3> 80144a6: 4602 mov r2, r0 80144a8: 460b mov r3, r1 80144aa: e9dd 0106 ldrd r0, r1, [sp, #24] 80144ae: f7f4 fb0f bl 8008ad0 <__aeabi_dcmpgt> 80144b2: 2800 cmp r0, #0 80144b4: d163 bne.n 801457e <_dtoa_r+0x6c6> 80144b6: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 80144ba: 2000 movs r0, #0 80144bc: 49a7 ldr r1, [pc, #668] @ (801475c <_dtoa_r+0x8a4>) 80144be: f7f3 febf bl 8008240 <__aeabi_dsub> 80144c2: 4602 mov r2, r0 80144c4: 460b mov r3, r1 80144c6: e9dd 0106 ldrd r0, r1, [sp, #24] 80144ca: f7f4 fae3 bl 8008a94 <__aeabi_dcmplt> 80144ce: 2800 cmp r0, #0 80144d0: f43f af14 beq.w 80142fc <_dtoa_r+0x444> 80144d4: 9e13 ldr r6, [sp, #76] @ 0x4c 80144d6: 1e73 subs r3, r6, #1 80144d8: 9313 str r3, [sp, #76] @ 0x4c 80144da: f816 3c01 ldrb.w r3, [r6, #-1] 80144de: 2b30 cmp r3, #48 @ 0x30 80144e0: d0f8 beq.n 80144d4 <_dtoa_r+0x61c> 80144e2: 4647 mov r7, r8 80144e4: e03b b.n 801455e <_dtoa_r+0x6a6> 80144e6: 4b9e ldr r3, [pc, #632] @ (8014760 <_dtoa_r+0x8a8>) 80144e8: f7f4 f862 bl 80085b0 <__aeabi_dmul> 80144ec: e9cd 0106 strd r0, r1, [sp, #24] 80144f0: e7bc b.n 801446c <_dtoa_r+0x5b4> 80144f2: 4656 mov r6, sl 80144f4: e9dd 4506 ldrd r4, r5, [sp, #24] 80144f8: e9dd 2304 ldrd r2, r3, [sp, #16] 80144fc: 4620 mov r0, r4 80144fe: 4629 mov r1, r5 8014500: f7f4 f980 bl 8008804 <__aeabi_ddiv> 8014504: f7f4 fb04 bl 8008b10 <__aeabi_d2iz> 8014508: 4680 mov r8, r0 801450a: f7f3 ffe7 bl 80084dc <__aeabi_i2d> 801450e: e9dd 2304 ldrd r2, r3, [sp, #16] 8014512: f7f4 f84d bl 80085b0 <__aeabi_dmul> 8014516: 4602 mov r2, r0 8014518: 460b mov r3, r1 801451a: 4620 mov r0, r4 801451c: 4629 mov r1, r5 801451e: f7f3 fe8f bl 8008240 <__aeabi_dsub> 8014522: f108 0430 add.w r4, r8, #48 @ 0x30 8014526: 9d08 ldr r5, [sp, #32] 8014528: f806 4b01 strb.w r4, [r6], #1 801452c: eba6 040a sub.w r4, r6, sl 8014530: 42a5 cmp r5, r4 8014532: 4602 mov r2, r0 8014534: 460b mov r3, r1 8014536: d133 bne.n 80145a0 <_dtoa_r+0x6e8> 8014538: f7f3 fe84 bl 8008244 <__adddf3> 801453c: e9dd 2304 ldrd r2, r3, [sp, #16] 8014540: 4604 mov r4, r0 8014542: 460d mov r5, r1 8014544: f7f4 fac4 bl 8008ad0 <__aeabi_dcmpgt> 8014548: b9c0 cbnz r0, 801457c <_dtoa_r+0x6c4> 801454a: e9dd 2304 ldrd r2, r3, [sp, #16] 801454e: 4620 mov r0, r4 8014550: 4629 mov r1, r5 8014552: f7f4 fa95 bl 8008a80 <__aeabi_dcmpeq> 8014556: b110 cbz r0, 801455e <_dtoa_r+0x6a6> 8014558: f018 0f01 tst.w r8, #1 801455c: d10e bne.n 801457c <_dtoa_r+0x6c4> 801455e: 4648 mov r0, r9 8014560: 9903 ldr r1, [sp, #12] 8014562: f000 feb3 bl 80152cc <_Bfree> 8014566: 2300 movs r3, #0 8014568: 7033 strb r3, [r6, #0] 801456a: 9b22 ldr r3, [sp, #136] @ 0x88 801456c: 3701 adds r7, #1 801456e: 601f str r7, [r3, #0] 8014570: 9b24 ldr r3, [sp, #144] @ 0x90 8014572: 2b00 cmp r3, #0 8014574: f000 824b beq.w 8014a0e <_dtoa_r+0xb56> 8014578: 601e str r6, [r3, #0] 801457a: e248 b.n 8014a0e <_dtoa_r+0xb56> 801457c: 46b8 mov r8, r7 801457e: 4633 mov r3, r6 8014580: 461e mov r6, r3 8014582: f813 2d01 ldrb.w r2, [r3, #-1]! 8014586: 2a39 cmp r2, #57 @ 0x39 8014588: d106 bne.n 8014598 <_dtoa_r+0x6e0> 801458a: 459a cmp sl, r3 801458c: d1f8 bne.n 8014580 <_dtoa_r+0x6c8> 801458e: 2230 movs r2, #48 @ 0x30 8014590: f108 0801 add.w r8, r8, #1 8014594: f88a 2000 strb.w r2, [sl] 8014598: 781a ldrb r2, [r3, #0] 801459a: 3201 adds r2, #1 801459c: 701a strb r2, [r3, #0] 801459e: e7a0 b.n 80144e2 <_dtoa_r+0x62a> 80145a0: 2200 movs r2, #0 80145a2: 4b6f ldr r3, [pc, #444] @ (8014760 <_dtoa_r+0x8a8>) 80145a4: f7f4 f804 bl 80085b0 <__aeabi_dmul> 80145a8: 2200 movs r2, #0 80145aa: 2300 movs r3, #0 80145ac: 4604 mov r4, r0 80145ae: 460d mov r5, r1 80145b0: f7f4 fa66 bl 8008a80 <__aeabi_dcmpeq> 80145b4: 2800 cmp r0, #0 80145b6: d09f beq.n 80144f8 <_dtoa_r+0x640> 80145b8: e7d1 b.n 801455e <_dtoa_r+0x6a6> 80145ba: 9a0b ldr r2, [sp, #44] @ 0x2c 80145bc: 2a00 cmp r2, #0 80145be: f000 80ea beq.w 8014796 <_dtoa_r+0x8de> 80145c2: 9a20 ldr r2, [sp, #128] @ 0x80 80145c4: 2a01 cmp r2, #1 80145c6: f300 80cd bgt.w 8014764 <_dtoa_r+0x8ac> 80145ca: 9a12 ldr r2, [sp, #72] @ 0x48 80145cc: 2a00 cmp r2, #0 80145ce: f000 80c1 beq.w 8014754 <_dtoa_r+0x89c> 80145d2: f203 4333 addw r3, r3, #1075 @ 0x433 80145d6: 9c0a ldr r4, [sp, #40] @ 0x28 80145d8: 9e04 ldr r6, [sp, #16] 80145da: 9a04 ldr r2, [sp, #16] 80145dc: 2101 movs r1, #1 80145de: 441a add r2, r3 80145e0: 9204 str r2, [sp, #16] 80145e2: 9a09 ldr r2, [sp, #36] @ 0x24 80145e4: 4648 mov r0, r9 80145e6: 441a add r2, r3 80145e8: 9209 str r2, [sp, #36] @ 0x24 80145ea: f000 ff23 bl 8015434 <__i2b> 80145ee: 4605 mov r5, r0 80145f0: b166 cbz r6, 801460c <_dtoa_r+0x754> 80145f2: 9b09 ldr r3, [sp, #36] @ 0x24 80145f4: 2b00 cmp r3, #0 80145f6: dd09 ble.n 801460c <_dtoa_r+0x754> 80145f8: 42b3 cmp r3, r6 80145fa: bfa8 it ge 80145fc: 4633 movge r3, r6 80145fe: 9a04 ldr r2, [sp, #16] 8014600: 1af6 subs r6, r6, r3 8014602: 1ad2 subs r2, r2, r3 8014604: 9204 str r2, [sp, #16] 8014606: 9a09 ldr r2, [sp, #36] @ 0x24 8014608: 1ad3 subs r3, r2, r3 801460a: 9309 str r3, [sp, #36] @ 0x24 801460c: 9b0a ldr r3, [sp, #40] @ 0x28 801460e: b30b cbz r3, 8014654 <_dtoa_r+0x79c> 8014610: 9b0b ldr r3, [sp, #44] @ 0x2c 8014612: 2b00 cmp r3, #0 8014614: f000 80c6 beq.w 80147a4 <_dtoa_r+0x8ec> 8014618: 2c00 cmp r4, #0 801461a: f000 80c0 beq.w 801479e <_dtoa_r+0x8e6> 801461e: 4629 mov r1, r5 8014620: 4622 mov r2, r4 8014622: 4648 mov r0, r9 8014624: f000 ffbe bl 80155a4 <__pow5mult> 8014628: 9a03 ldr r2, [sp, #12] 801462a: 4601 mov r1, r0 801462c: 4605 mov r5, r0 801462e: 4648 mov r0, r9 8014630: f000 ff16 bl 8015460 <__multiply> 8014634: 9903 ldr r1, [sp, #12] 8014636: 4680 mov r8, r0 8014638: 4648 mov r0, r9 801463a: f000 fe47 bl 80152cc <_Bfree> 801463e: 9b0a ldr r3, [sp, #40] @ 0x28 8014640: 1b1b subs r3, r3, r4 8014642: 930a str r3, [sp, #40] @ 0x28 8014644: f000 80b1 beq.w 80147aa <_dtoa_r+0x8f2> 8014648: 4641 mov r1, r8 801464a: 9a0a ldr r2, [sp, #40] @ 0x28 801464c: 4648 mov r0, r9 801464e: f000 ffa9 bl 80155a4 <__pow5mult> 8014652: 9003 str r0, [sp, #12] 8014654: 2101 movs r1, #1 8014656: 4648 mov r0, r9 8014658: f000 feec bl 8015434 <__i2b> 801465c: 9b0e ldr r3, [sp, #56] @ 0x38 801465e: 4604 mov r4, r0 8014660: 2b00 cmp r3, #0 8014662: f000 81d8 beq.w 8014a16 <_dtoa_r+0xb5e> 8014666: 461a mov r2, r3 8014668: 4601 mov r1, r0 801466a: 4648 mov r0, r9 801466c: f000 ff9a bl 80155a4 <__pow5mult> 8014670: 9b20 ldr r3, [sp, #128] @ 0x80 8014672: 4604 mov r4, r0 8014674: 2b01 cmp r3, #1 8014676: f300 809f bgt.w 80147b8 <_dtoa_r+0x900> 801467a: 9b06 ldr r3, [sp, #24] 801467c: 2b00 cmp r3, #0 801467e: f040 8097 bne.w 80147b0 <_dtoa_r+0x8f8> 8014682: 9b07 ldr r3, [sp, #28] 8014684: f3c3 0313 ubfx r3, r3, #0, #20 8014688: 2b00 cmp r3, #0 801468a: f040 8093 bne.w 80147b4 <_dtoa_r+0x8fc> 801468e: 9b07 ldr r3, [sp, #28] 8014690: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8014694: 0d1b lsrs r3, r3, #20 8014696: 051b lsls r3, r3, #20 8014698: b133 cbz r3, 80146a8 <_dtoa_r+0x7f0> 801469a: 9b04 ldr r3, [sp, #16] 801469c: 3301 adds r3, #1 801469e: 9304 str r3, [sp, #16] 80146a0: 9b09 ldr r3, [sp, #36] @ 0x24 80146a2: 3301 adds r3, #1 80146a4: 9309 str r3, [sp, #36] @ 0x24 80146a6: 2301 movs r3, #1 80146a8: 930a str r3, [sp, #40] @ 0x28 80146aa: 9b0e ldr r3, [sp, #56] @ 0x38 80146ac: 2b00 cmp r3, #0 80146ae: f000 81b8 beq.w 8014a22 <_dtoa_r+0xb6a> 80146b2: 6923 ldr r3, [r4, #16] 80146b4: eb04 0383 add.w r3, r4, r3, lsl #2 80146b8: 6918 ldr r0, [r3, #16] 80146ba: f000 fe6f bl 801539c <__hi0bits> 80146be: f1c0 0020 rsb r0, r0, #32 80146c2: 9b09 ldr r3, [sp, #36] @ 0x24 80146c4: 4418 add r0, r3 80146c6: f010 001f ands.w r0, r0, #31 80146ca: f000 8082 beq.w 80147d2 <_dtoa_r+0x91a> 80146ce: f1c0 0320 rsb r3, r0, #32 80146d2: 2b04 cmp r3, #4 80146d4: dd73 ble.n 80147be <_dtoa_r+0x906> 80146d6: 9b04 ldr r3, [sp, #16] 80146d8: f1c0 001c rsb r0, r0, #28 80146dc: 4403 add r3, r0 80146de: 9304 str r3, [sp, #16] 80146e0: 9b09 ldr r3, [sp, #36] @ 0x24 80146e2: 4406 add r6, r0 80146e4: 4403 add r3, r0 80146e6: 9309 str r3, [sp, #36] @ 0x24 80146e8: 9b04 ldr r3, [sp, #16] 80146ea: 2b00 cmp r3, #0 80146ec: dd05 ble.n 80146fa <_dtoa_r+0x842> 80146ee: 461a mov r2, r3 80146f0: 4648 mov r0, r9 80146f2: 9903 ldr r1, [sp, #12] 80146f4: f000 ffb0 bl 8015658 <__lshift> 80146f8: 9003 str r0, [sp, #12] 80146fa: 9b09 ldr r3, [sp, #36] @ 0x24 80146fc: 2b00 cmp r3, #0 80146fe: dd05 ble.n 801470c <_dtoa_r+0x854> 8014700: 4621 mov r1, r4 8014702: 461a mov r2, r3 8014704: 4648 mov r0, r9 8014706: f000 ffa7 bl 8015658 <__lshift> 801470a: 4604 mov r4, r0 801470c: 9b0f ldr r3, [sp, #60] @ 0x3c 801470e: 2b00 cmp r3, #0 8014710: d061 beq.n 80147d6 <_dtoa_r+0x91e> 8014712: 4621 mov r1, r4 8014714: 9803 ldr r0, [sp, #12] 8014716: f001 f80b bl 8015730 <__mcmp> 801471a: 2800 cmp r0, #0 801471c: da5b bge.n 80147d6 <_dtoa_r+0x91e> 801471e: 2300 movs r3, #0 8014720: 220a movs r2, #10 8014722: 4648 mov r0, r9 8014724: 9903 ldr r1, [sp, #12] 8014726: f000 fdf3 bl 8015310 <__multadd> 801472a: 9b0b ldr r3, [sp, #44] @ 0x2c 801472c: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff 8014730: 9003 str r0, [sp, #12] 8014732: 2b00 cmp r3, #0 8014734: f000 8177 beq.w 8014a26 <_dtoa_r+0xb6e> 8014738: 4629 mov r1, r5 801473a: 2300 movs r3, #0 801473c: 220a movs r2, #10 801473e: 4648 mov r0, r9 8014740: f000 fde6 bl 8015310 <__multadd> 8014744: f1bb 0f00 cmp.w fp, #0 8014748: 4605 mov r5, r0 801474a: dc6f bgt.n 801482c <_dtoa_r+0x974> 801474c: 9b20 ldr r3, [sp, #128] @ 0x80 801474e: 2b02 cmp r3, #2 8014750: dc49 bgt.n 80147e6 <_dtoa_r+0x92e> 8014752: e06b b.n 801482c <_dtoa_r+0x974> 8014754: 9b14 ldr r3, [sp, #80] @ 0x50 8014756: f1c3 0336 rsb r3, r3, #54 @ 0x36 801475a: e73c b.n 80145d6 <_dtoa_r+0x71e> 801475c: 3fe00000 .word 0x3fe00000 8014760: 40240000 .word 0x40240000 8014764: 9b08 ldr r3, [sp, #32] 8014766: 1e5c subs r4, r3, #1 8014768: 9b0a ldr r3, [sp, #40] @ 0x28 801476a: 42a3 cmp r3, r4 801476c: db09 blt.n 8014782 <_dtoa_r+0x8ca> 801476e: 1b1c subs r4, r3, r4 8014770: 9b08 ldr r3, [sp, #32] 8014772: 2b00 cmp r3, #0 8014774: f6bf af30 bge.w 80145d8 <_dtoa_r+0x720> 8014778: 9b04 ldr r3, [sp, #16] 801477a: 9a08 ldr r2, [sp, #32] 801477c: 1a9e subs r6, r3, r2 801477e: 2300 movs r3, #0 8014780: e72b b.n 80145da <_dtoa_r+0x722> 8014782: 9b0a ldr r3, [sp, #40] @ 0x28 8014784: 9a0e ldr r2, [sp, #56] @ 0x38 8014786: 1ae3 subs r3, r4, r3 8014788: 441a add r2, r3 801478a: 940a str r4, [sp, #40] @ 0x28 801478c: 9e04 ldr r6, [sp, #16] 801478e: 2400 movs r4, #0 8014790: 9b08 ldr r3, [sp, #32] 8014792: 920e str r2, [sp, #56] @ 0x38 8014794: e721 b.n 80145da <_dtoa_r+0x722> 8014796: 9c0a ldr r4, [sp, #40] @ 0x28 8014798: 9e04 ldr r6, [sp, #16] 801479a: 9d0b ldr r5, [sp, #44] @ 0x2c 801479c: e728 b.n 80145f0 <_dtoa_r+0x738> 801479e: f8dd 800c ldr.w r8, [sp, #12] 80147a2: e751 b.n 8014648 <_dtoa_r+0x790> 80147a4: 9a0a ldr r2, [sp, #40] @ 0x28 80147a6: 9903 ldr r1, [sp, #12] 80147a8: e750 b.n 801464c <_dtoa_r+0x794> 80147aa: f8cd 800c str.w r8, [sp, #12] 80147ae: e751 b.n 8014654 <_dtoa_r+0x79c> 80147b0: 2300 movs r3, #0 80147b2: e779 b.n 80146a8 <_dtoa_r+0x7f0> 80147b4: 9b06 ldr r3, [sp, #24] 80147b6: e777 b.n 80146a8 <_dtoa_r+0x7f0> 80147b8: 2300 movs r3, #0 80147ba: 930a str r3, [sp, #40] @ 0x28 80147bc: e779 b.n 80146b2 <_dtoa_r+0x7fa> 80147be: d093 beq.n 80146e8 <_dtoa_r+0x830> 80147c0: 9a04 ldr r2, [sp, #16] 80147c2: 331c adds r3, #28 80147c4: 441a add r2, r3 80147c6: 9204 str r2, [sp, #16] 80147c8: 9a09 ldr r2, [sp, #36] @ 0x24 80147ca: 441e add r6, r3 80147cc: 441a add r2, r3 80147ce: 9209 str r2, [sp, #36] @ 0x24 80147d0: e78a b.n 80146e8 <_dtoa_r+0x830> 80147d2: 4603 mov r3, r0 80147d4: e7f4 b.n 80147c0 <_dtoa_r+0x908> 80147d6: 9b08 ldr r3, [sp, #32] 80147d8: 46b8 mov r8, r7 80147da: 2b00 cmp r3, #0 80147dc: dc20 bgt.n 8014820 <_dtoa_r+0x968> 80147de: 469b mov fp, r3 80147e0: 9b20 ldr r3, [sp, #128] @ 0x80 80147e2: 2b02 cmp r3, #2 80147e4: dd1e ble.n 8014824 <_dtoa_r+0x96c> 80147e6: f1bb 0f00 cmp.w fp, #0 80147ea: f47f adb1 bne.w 8014350 <_dtoa_r+0x498> 80147ee: 4621 mov r1, r4 80147f0: 465b mov r3, fp 80147f2: 2205 movs r2, #5 80147f4: 4648 mov r0, r9 80147f6: f000 fd8b bl 8015310 <__multadd> 80147fa: 4601 mov r1, r0 80147fc: 4604 mov r4, r0 80147fe: 9803 ldr r0, [sp, #12] 8014800: f000 ff96 bl 8015730 <__mcmp> 8014804: 2800 cmp r0, #0 8014806: f77f ada3 ble.w 8014350 <_dtoa_r+0x498> 801480a: 4656 mov r6, sl 801480c: 2331 movs r3, #49 @ 0x31 801480e: f108 0801 add.w r8, r8, #1 8014812: f806 3b01 strb.w r3, [r6], #1 8014816: e59f b.n 8014358 <_dtoa_r+0x4a0> 8014818: 46b8 mov r8, r7 801481a: 9c08 ldr r4, [sp, #32] 801481c: 4625 mov r5, r4 801481e: e7f4 b.n 801480a <_dtoa_r+0x952> 8014820: f8dd b020 ldr.w fp, [sp, #32] 8014824: 9b0b ldr r3, [sp, #44] @ 0x2c 8014826: 2b00 cmp r3, #0 8014828: f000 8101 beq.w 8014a2e <_dtoa_r+0xb76> 801482c: 2e00 cmp r6, #0 801482e: dd05 ble.n 801483c <_dtoa_r+0x984> 8014830: 4629 mov r1, r5 8014832: 4632 mov r2, r6 8014834: 4648 mov r0, r9 8014836: f000 ff0f bl 8015658 <__lshift> 801483a: 4605 mov r5, r0 801483c: 9b0a ldr r3, [sp, #40] @ 0x28 801483e: 2b00 cmp r3, #0 8014840: d05c beq.n 80148fc <_dtoa_r+0xa44> 8014842: 4648 mov r0, r9 8014844: 6869 ldr r1, [r5, #4] 8014846: f000 fd01 bl 801524c <_Balloc> 801484a: 4606 mov r6, r0 801484c: b928 cbnz r0, 801485a <_dtoa_r+0x9a2> 801484e: 4602 mov r2, r0 8014850: f240 21ef movw r1, #751 @ 0x2ef 8014854: 4b80 ldr r3, [pc, #512] @ (8014a58 <_dtoa_r+0xba0>) 8014856: f7ff bb43 b.w 8013ee0 <_dtoa_r+0x28> 801485a: 692a ldr r2, [r5, #16] 801485c: f105 010c add.w r1, r5, #12 8014860: 3202 adds r2, #2 8014862: 0092 lsls r2, r2, #2 8014864: 300c adds r0, #12 8014866: f7ff fa71 bl 8013d4c 801486a: 2201 movs r2, #1 801486c: 4631 mov r1, r6 801486e: 4648 mov r0, r9 8014870: f000 fef2 bl 8015658 <__lshift> 8014874: 462f mov r7, r5 8014876: 4605 mov r5, r0 8014878: f10a 0301 add.w r3, sl, #1 801487c: 9304 str r3, [sp, #16] 801487e: eb0a 030b add.w r3, sl, fp 8014882: 930a str r3, [sp, #40] @ 0x28 8014884: 9b06 ldr r3, [sp, #24] 8014886: f003 0301 and.w r3, r3, #1 801488a: 9309 str r3, [sp, #36] @ 0x24 801488c: 9b04 ldr r3, [sp, #16] 801488e: 4621 mov r1, r4 8014890: 9803 ldr r0, [sp, #12] 8014892: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff 8014896: f7ff fa85 bl 8013da4 801489a: 4603 mov r3, r0 801489c: 4639 mov r1, r7 801489e: 3330 adds r3, #48 @ 0x30 80148a0: 9006 str r0, [sp, #24] 80148a2: 9803 ldr r0, [sp, #12] 80148a4: 930b str r3, [sp, #44] @ 0x2c 80148a6: f000 ff43 bl 8015730 <__mcmp> 80148aa: 462a mov r2, r5 80148ac: 9008 str r0, [sp, #32] 80148ae: 4621 mov r1, r4 80148b0: 4648 mov r0, r9 80148b2: f000 ff59 bl 8015768 <__mdiff> 80148b6: 68c2 ldr r2, [r0, #12] 80148b8: 4606 mov r6, r0 80148ba: 9b0b ldr r3, [sp, #44] @ 0x2c 80148bc: bb02 cbnz r2, 8014900 <_dtoa_r+0xa48> 80148be: 4601 mov r1, r0 80148c0: 9803 ldr r0, [sp, #12] 80148c2: f000 ff35 bl 8015730 <__mcmp> 80148c6: 4602 mov r2, r0 80148c8: 9b0b ldr r3, [sp, #44] @ 0x2c 80148ca: 4631 mov r1, r6 80148cc: 4648 mov r0, r9 80148ce: e9cd 320b strd r3, r2, [sp, #44] @ 0x2c 80148d2: f000 fcfb bl 80152cc <_Bfree> 80148d6: 9b20 ldr r3, [sp, #128] @ 0x80 80148d8: 9a0c ldr r2, [sp, #48] @ 0x30 80148da: 9e04 ldr r6, [sp, #16] 80148dc: ea42 0103 orr.w r1, r2, r3 80148e0: 9b09 ldr r3, [sp, #36] @ 0x24 80148e2: 4319 orrs r1, r3 80148e4: 9b0b ldr r3, [sp, #44] @ 0x2c 80148e6: d10d bne.n 8014904 <_dtoa_r+0xa4c> 80148e8: 2b39 cmp r3, #57 @ 0x39 80148ea: d027 beq.n 801493c <_dtoa_r+0xa84> 80148ec: 9a08 ldr r2, [sp, #32] 80148ee: 2a00 cmp r2, #0 80148f0: dd01 ble.n 80148f6 <_dtoa_r+0xa3e> 80148f2: 9b06 ldr r3, [sp, #24] 80148f4: 3331 adds r3, #49 @ 0x31 80148f6: f88b 3000 strb.w r3, [fp] 80148fa: e52e b.n 801435a <_dtoa_r+0x4a2> 80148fc: 4628 mov r0, r5 80148fe: e7b9 b.n 8014874 <_dtoa_r+0x9bc> 8014900: 2201 movs r2, #1 8014902: e7e2 b.n 80148ca <_dtoa_r+0xa12> 8014904: 9908 ldr r1, [sp, #32] 8014906: 2900 cmp r1, #0 8014908: db04 blt.n 8014914 <_dtoa_r+0xa5c> 801490a: 9820 ldr r0, [sp, #128] @ 0x80 801490c: 4301 orrs r1, r0 801490e: 9809 ldr r0, [sp, #36] @ 0x24 8014910: 4301 orrs r1, r0 8014912: d120 bne.n 8014956 <_dtoa_r+0xa9e> 8014914: 2a00 cmp r2, #0 8014916: ddee ble.n 80148f6 <_dtoa_r+0xa3e> 8014918: 2201 movs r2, #1 801491a: 9903 ldr r1, [sp, #12] 801491c: 4648 mov r0, r9 801491e: 9304 str r3, [sp, #16] 8014920: f000 fe9a bl 8015658 <__lshift> 8014924: 4621 mov r1, r4 8014926: 9003 str r0, [sp, #12] 8014928: f000 ff02 bl 8015730 <__mcmp> 801492c: 2800 cmp r0, #0 801492e: 9b04 ldr r3, [sp, #16] 8014930: dc02 bgt.n 8014938 <_dtoa_r+0xa80> 8014932: d1e0 bne.n 80148f6 <_dtoa_r+0xa3e> 8014934: 07da lsls r2, r3, #31 8014936: d5de bpl.n 80148f6 <_dtoa_r+0xa3e> 8014938: 2b39 cmp r3, #57 @ 0x39 801493a: d1da bne.n 80148f2 <_dtoa_r+0xa3a> 801493c: 2339 movs r3, #57 @ 0x39 801493e: f88b 3000 strb.w r3, [fp] 8014942: 4633 mov r3, r6 8014944: 461e mov r6, r3 8014946: f816 2c01 ldrb.w r2, [r6, #-1] 801494a: 3b01 subs r3, #1 801494c: 2a39 cmp r2, #57 @ 0x39 801494e: d04e beq.n 80149ee <_dtoa_r+0xb36> 8014950: 3201 adds r2, #1 8014952: 701a strb r2, [r3, #0] 8014954: e501 b.n 801435a <_dtoa_r+0x4a2> 8014956: 2a00 cmp r2, #0 8014958: dd03 ble.n 8014962 <_dtoa_r+0xaaa> 801495a: 2b39 cmp r3, #57 @ 0x39 801495c: d0ee beq.n 801493c <_dtoa_r+0xa84> 801495e: 3301 adds r3, #1 8014960: e7c9 b.n 80148f6 <_dtoa_r+0xa3e> 8014962: 9a04 ldr r2, [sp, #16] 8014964: 990a ldr r1, [sp, #40] @ 0x28 8014966: f802 3c01 strb.w r3, [r2, #-1] 801496a: 428a cmp r2, r1 801496c: d028 beq.n 80149c0 <_dtoa_r+0xb08> 801496e: 2300 movs r3, #0 8014970: 220a movs r2, #10 8014972: 9903 ldr r1, [sp, #12] 8014974: 4648 mov r0, r9 8014976: f000 fccb bl 8015310 <__multadd> 801497a: 42af cmp r7, r5 801497c: 9003 str r0, [sp, #12] 801497e: f04f 0300 mov.w r3, #0 8014982: f04f 020a mov.w r2, #10 8014986: 4639 mov r1, r7 8014988: 4648 mov r0, r9 801498a: d107 bne.n 801499c <_dtoa_r+0xae4> 801498c: f000 fcc0 bl 8015310 <__multadd> 8014990: 4607 mov r7, r0 8014992: 4605 mov r5, r0 8014994: 9b04 ldr r3, [sp, #16] 8014996: 3301 adds r3, #1 8014998: 9304 str r3, [sp, #16] 801499a: e777 b.n 801488c <_dtoa_r+0x9d4> 801499c: f000 fcb8 bl 8015310 <__multadd> 80149a0: 4629 mov r1, r5 80149a2: 4607 mov r7, r0 80149a4: 2300 movs r3, #0 80149a6: 220a movs r2, #10 80149a8: 4648 mov r0, r9 80149aa: f000 fcb1 bl 8015310 <__multadd> 80149ae: 4605 mov r5, r0 80149b0: e7f0 b.n 8014994 <_dtoa_r+0xadc> 80149b2: f1bb 0f00 cmp.w fp, #0 80149b6: bfcc ite gt 80149b8: 465e movgt r6, fp 80149ba: 2601 movle r6, #1 80149bc: 2700 movs r7, #0 80149be: 4456 add r6, sl 80149c0: 2201 movs r2, #1 80149c2: 9903 ldr r1, [sp, #12] 80149c4: 4648 mov r0, r9 80149c6: 9304 str r3, [sp, #16] 80149c8: f000 fe46 bl 8015658 <__lshift> 80149cc: 4621 mov r1, r4 80149ce: 9003 str r0, [sp, #12] 80149d0: f000 feae bl 8015730 <__mcmp> 80149d4: 2800 cmp r0, #0 80149d6: dcb4 bgt.n 8014942 <_dtoa_r+0xa8a> 80149d8: d102 bne.n 80149e0 <_dtoa_r+0xb28> 80149da: 9b04 ldr r3, [sp, #16] 80149dc: 07db lsls r3, r3, #31 80149de: d4b0 bmi.n 8014942 <_dtoa_r+0xa8a> 80149e0: 4633 mov r3, r6 80149e2: 461e mov r6, r3 80149e4: f813 2d01 ldrb.w r2, [r3, #-1]! 80149e8: 2a30 cmp r2, #48 @ 0x30 80149ea: d0fa beq.n 80149e2 <_dtoa_r+0xb2a> 80149ec: e4b5 b.n 801435a <_dtoa_r+0x4a2> 80149ee: 459a cmp sl, r3 80149f0: d1a8 bne.n 8014944 <_dtoa_r+0xa8c> 80149f2: 2331 movs r3, #49 @ 0x31 80149f4: f108 0801 add.w r8, r8, #1 80149f8: f88a 3000 strb.w r3, [sl] 80149fc: e4ad b.n 801435a <_dtoa_r+0x4a2> 80149fe: 9b24 ldr r3, [sp, #144] @ 0x90 8014a00: f8df a058 ldr.w sl, [pc, #88] @ 8014a5c <_dtoa_r+0xba4> 8014a04: b11b cbz r3, 8014a0e <_dtoa_r+0xb56> 8014a06: f10a 0308 add.w r3, sl, #8 8014a0a: 9a24 ldr r2, [sp, #144] @ 0x90 8014a0c: 6013 str r3, [r2, #0] 8014a0e: 4650 mov r0, sl 8014a10: b017 add sp, #92 @ 0x5c 8014a12: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8014a16: 9b20 ldr r3, [sp, #128] @ 0x80 8014a18: 2b01 cmp r3, #1 8014a1a: f77f ae2e ble.w 801467a <_dtoa_r+0x7c2> 8014a1e: 9b0e ldr r3, [sp, #56] @ 0x38 8014a20: 930a str r3, [sp, #40] @ 0x28 8014a22: 2001 movs r0, #1 8014a24: e64d b.n 80146c2 <_dtoa_r+0x80a> 8014a26: f1bb 0f00 cmp.w fp, #0 8014a2a: f77f aed9 ble.w 80147e0 <_dtoa_r+0x928> 8014a2e: 4656 mov r6, sl 8014a30: 4621 mov r1, r4 8014a32: 9803 ldr r0, [sp, #12] 8014a34: f7ff f9b6 bl 8013da4 8014a38: f100 0330 add.w r3, r0, #48 @ 0x30 8014a3c: f806 3b01 strb.w r3, [r6], #1 8014a40: eba6 020a sub.w r2, r6, sl 8014a44: 4593 cmp fp, r2 8014a46: ddb4 ble.n 80149b2 <_dtoa_r+0xafa> 8014a48: 2300 movs r3, #0 8014a4a: 220a movs r2, #10 8014a4c: 4648 mov r0, r9 8014a4e: 9903 ldr r1, [sp, #12] 8014a50: f000 fc5e bl 8015310 <__multadd> 8014a54: 9003 str r0, [sp, #12] 8014a56: e7eb b.n 8014a30 <_dtoa_r+0xb78> 8014a58: 080164c8 .word 0x080164c8 8014a5c: 0801644c .word 0x0801644c 08014a60 <__ssputs_r>: 8014a60: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8014a64: 461f mov r7, r3 8014a66: 688e ldr r6, [r1, #8] 8014a68: 4682 mov sl, r0 8014a6a: 42be cmp r6, r7 8014a6c: 460c mov r4, r1 8014a6e: 4690 mov r8, r2 8014a70: 680b ldr r3, [r1, #0] 8014a72: d82d bhi.n 8014ad0 <__ssputs_r+0x70> 8014a74: f9b1 200c ldrsh.w r2, [r1, #12] 8014a78: f412 6f90 tst.w r2, #1152 @ 0x480 8014a7c: d026 beq.n 8014acc <__ssputs_r+0x6c> 8014a7e: 6965 ldr r5, [r4, #20] 8014a80: 6909 ldr r1, [r1, #16] 8014a82: eb05 0545 add.w r5, r5, r5, lsl #1 8014a86: eba3 0901 sub.w r9, r3, r1 8014a8a: eb05 75d5 add.w r5, r5, r5, lsr #31 8014a8e: 1c7b adds r3, r7, #1 8014a90: 444b add r3, r9 8014a92: 106d asrs r5, r5, #1 8014a94: 429d cmp r5, r3 8014a96: bf38 it cc 8014a98: 461d movcc r5, r3 8014a9a: 0553 lsls r3, r2, #21 8014a9c: d527 bpl.n 8014aee <__ssputs_r+0x8e> 8014a9e: 4629 mov r1, r5 8014aa0: f000 faa0 bl 8014fe4 <_malloc_r> 8014aa4: 4606 mov r6, r0 8014aa6: b360 cbz r0, 8014b02 <__ssputs_r+0xa2> 8014aa8: 464a mov r2, r9 8014aaa: 6921 ldr r1, [r4, #16] 8014aac: f7ff f94e bl 8013d4c 8014ab0: 89a3 ldrh r3, [r4, #12] 8014ab2: f423 6390 bic.w r3, r3, #1152 @ 0x480 8014ab6: f043 0380 orr.w r3, r3, #128 @ 0x80 8014aba: 81a3 strh r3, [r4, #12] 8014abc: 6126 str r6, [r4, #16] 8014abe: 444e add r6, r9 8014ac0: 6026 str r6, [r4, #0] 8014ac2: 463e mov r6, r7 8014ac4: 6165 str r5, [r4, #20] 8014ac6: eba5 0509 sub.w r5, r5, r9 8014aca: 60a5 str r5, [r4, #8] 8014acc: 42be cmp r6, r7 8014ace: d900 bls.n 8014ad2 <__ssputs_r+0x72> 8014ad0: 463e mov r6, r7 8014ad2: 4632 mov r2, r6 8014ad4: 4641 mov r1, r8 8014ad6: 6820 ldr r0, [r4, #0] 8014ad8: f001 f8ab bl 8015c32 8014adc: 2000 movs r0, #0 8014ade: 68a3 ldr r3, [r4, #8] 8014ae0: 1b9b subs r3, r3, r6 8014ae2: 60a3 str r3, [r4, #8] 8014ae4: 6823 ldr r3, [r4, #0] 8014ae6: 4433 add r3, r6 8014ae8: 6023 str r3, [r4, #0] 8014aea: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8014aee: 462a mov r2, r5 8014af0: f000 ff7c bl 80159ec <_realloc_r> 8014af4: 4606 mov r6, r0 8014af6: 2800 cmp r0, #0 8014af8: d1e0 bne.n 8014abc <__ssputs_r+0x5c> 8014afa: 4650 mov r0, sl 8014afc: 6921 ldr r1, [r4, #16] 8014afe: f001 f947 bl 8015d90 <_free_r> 8014b02: 230c movs r3, #12 8014b04: f8ca 3000 str.w r3, [sl] 8014b08: 89a3 ldrh r3, [r4, #12] 8014b0a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8014b0e: f043 0340 orr.w r3, r3, #64 @ 0x40 8014b12: 81a3 strh r3, [r4, #12] 8014b14: e7e9 b.n 8014aea <__ssputs_r+0x8a> ... 08014b18 <_svfiprintf_r>: 8014b18: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8014b1c: 4698 mov r8, r3 8014b1e: 898b ldrh r3, [r1, #12] 8014b20: 4607 mov r7, r0 8014b22: 061b lsls r3, r3, #24 8014b24: 460d mov r5, r1 8014b26: 4614 mov r4, r2 8014b28: b09d sub sp, #116 @ 0x74 8014b2a: d510 bpl.n 8014b4e <_svfiprintf_r+0x36> 8014b2c: 690b ldr r3, [r1, #16] 8014b2e: b973 cbnz r3, 8014b4e <_svfiprintf_r+0x36> 8014b30: 2140 movs r1, #64 @ 0x40 8014b32: f000 fa57 bl 8014fe4 <_malloc_r> 8014b36: 6028 str r0, [r5, #0] 8014b38: 6128 str r0, [r5, #16] 8014b3a: b930 cbnz r0, 8014b4a <_svfiprintf_r+0x32> 8014b3c: 230c movs r3, #12 8014b3e: 603b str r3, [r7, #0] 8014b40: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8014b44: b01d add sp, #116 @ 0x74 8014b46: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8014b4a: 2340 movs r3, #64 @ 0x40 8014b4c: 616b str r3, [r5, #20] 8014b4e: 2300 movs r3, #0 8014b50: 9309 str r3, [sp, #36] @ 0x24 8014b52: 2320 movs r3, #32 8014b54: f88d 3029 strb.w r3, [sp, #41] @ 0x29 8014b58: 2330 movs r3, #48 @ 0x30 8014b5a: f04f 0901 mov.w r9, #1 8014b5e: f8cd 800c str.w r8, [sp, #12] 8014b62: f8df 8198 ldr.w r8, [pc, #408] @ 8014cfc <_svfiprintf_r+0x1e4> 8014b66: f88d 302a strb.w r3, [sp, #42] @ 0x2a 8014b6a: 4623 mov r3, r4 8014b6c: 469a mov sl, r3 8014b6e: f813 2b01 ldrb.w r2, [r3], #1 8014b72: b10a cbz r2, 8014b78 <_svfiprintf_r+0x60> 8014b74: 2a25 cmp r2, #37 @ 0x25 8014b76: d1f9 bne.n 8014b6c <_svfiprintf_r+0x54> 8014b78: ebba 0b04 subs.w fp, sl, r4 8014b7c: d00b beq.n 8014b96 <_svfiprintf_r+0x7e> 8014b7e: 465b mov r3, fp 8014b80: 4622 mov r2, r4 8014b82: 4629 mov r1, r5 8014b84: 4638 mov r0, r7 8014b86: f7ff ff6b bl 8014a60 <__ssputs_r> 8014b8a: 3001 adds r0, #1 8014b8c: f000 80a7 beq.w 8014cde <_svfiprintf_r+0x1c6> 8014b90: 9a09 ldr r2, [sp, #36] @ 0x24 8014b92: 445a add r2, fp 8014b94: 9209 str r2, [sp, #36] @ 0x24 8014b96: f89a 3000 ldrb.w r3, [sl] 8014b9a: 2b00 cmp r3, #0 8014b9c: f000 809f beq.w 8014cde <_svfiprintf_r+0x1c6> 8014ba0: 2300 movs r3, #0 8014ba2: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8014ba6: e9cd 2305 strd r2, r3, [sp, #20] 8014baa: f10a 0a01 add.w sl, sl, #1 8014bae: 9304 str r3, [sp, #16] 8014bb0: 9307 str r3, [sp, #28] 8014bb2: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8014bb6: 931a str r3, [sp, #104] @ 0x68 8014bb8: 4654 mov r4, sl 8014bba: 2205 movs r2, #5 8014bbc: f814 1b01 ldrb.w r1, [r4], #1 8014bc0: 484e ldr r0, [pc, #312] @ (8014cfc <_svfiprintf_r+0x1e4>) 8014bc2: f7ff f8b5 bl 8013d30 8014bc6: 9a04 ldr r2, [sp, #16] 8014bc8: b9d8 cbnz r0, 8014c02 <_svfiprintf_r+0xea> 8014bca: 06d0 lsls r0, r2, #27 8014bcc: bf44 itt mi 8014bce: 2320 movmi r3, #32 8014bd0: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8014bd4: 0711 lsls r1, r2, #28 8014bd6: bf44 itt mi 8014bd8: 232b movmi r3, #43 @ 0x2b 8014bda: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8014bde: f89a 3000 ldrb.w r3, [sl] 8014be2: 2b2a cmp r3, #42 @ 0x2a 8014be4: d015 beq.n 8014c12 <_svfiprintf_r+0xfa> 8014be6: 4654 mov r4, sl 8014be8: 2000 movs r0, #0 8014bea: f04f 0c0a mov.w ip, #10 8014bee: 9a07 ldr r2, [sp, #28] 8014bf0: 4621 mov r1, r4 8014bf2: f811 3b01 ldrb.w r3, [r1], #1 8014bf6: 3b30 subs r3, #48 @ 0x30 8014bf8: 2b09 cmp r3, #9 8014bfa: d94b bls.n 8014c94 <_svfiprintf_r+0x17c> 8014bfc: b1b0 cbz r0, 8014c2c <_svfiprintf_r+0x114> 8014bfe: 9207 str r2, [sp, #28] 8014c00: e014 b.n 8014c2c <_svfiprintf_r+0x114> 8014c02: eba0 0308 sub.w r3, r0, r8 8014c06: fa09 f303 lsl.w r3, r9, r3 8014c0a: 4313 orrs r3, r2 8014c0c: 46a2 mov sl, r4 8014c0e: 9304 str r3, [sp, #16] 8014c10: e7d2 b.n 8014bb8 <_svfiprintf_r+0xa0> 8014c12: 9b03 ldr r3, [sp, #12] 8014c14: 1d19 adds r1, r3, #4 8014c16: 681b ldr r3, [r3, #0] 8014c18: 9103 str r1, [sp, #12] 8014c1a: 2b00 cmp r3, #0 8014c1c: bfbb ittet lt 8014c1e: 425b neglt r3, r3 8014c20: f042 0202 orrlt.w r2, r2, #2 8014c24: 9307 strge r3, [sp, #28] 8014c26: 9307 strlt r3, [sp, #28] 8014c28: bfb8 it lt 8014c2a: 9204 strlt r2, [sp, #16] 8014c2c: 7823 ldrb r3, [r4, #0] 8014c2e: 2b2e cmp r3, #46 @ 0x2e 8014c30: d10a bne.n 8014c48 <_svfiprintf_r+0x130> 8014c32: 7863 ldrb r3, [r4, #1] 8014c34: 2b2a cmp r3, #42 @ 0x2a 8014c36: d132 bne.n 8014c9e <_svfiprintf_r+0x186> 8014c38: 9b03 ldr r3, [sp, #12] 8014c3a: 3402 adds r4, #2 8014c3c: 1d1a adds r2, r3, #4 8014c3e: 681b ldr r3, [r3, #0] 8014c40: 9203 str r2, [sp, #12] 8014c42: ea43 73e3 orr.w r3, r3, r3, asr #31 8014c46: 9305 str r3, [sp, #20] 8014c48: f8df a0b4 ldr.w sl, [pc, #180] @ 8014d00 <_svfiprintf_r+0x1e8> 8014c4c: 2203 movs r2, #3 8014c4e: 4650 mov r0, sl 8014c50: 7821 ldrb r1, [r4, #0] 8014c52: f7ff f86d bl 8013d30 8014c56: b138 cbz r0, 8014c68 <_svfiprintf_r+0x150> 8014c58: 2240 movs r2, #64 @ 0x40 8014c5a: 9b04 ldr r3, [sp, #16] 8014c5c: eba0 000a sub.w r0, r0, sl 8014c60: 4082 lsls r2, r0 8014c62: 4313 orrs r3, r2 8014c64: 3401 adds r4, #1 8014c66: 9304 str r3, [sp, #16] 8014c68: f814 1b01 ldrb.w r1, [r4], #1 8014c6c: 2206 movs r2, #6 8014c6e: 4825 ldr r0, [pc, #148] @ (8014d04 <_svfiprintf_r+0x1ec>) 8014c70: f88d 1028 strb.w r1, [sp, #40] @ 0x28 8014c74: f7ff f85c bl 8013d30 8014c78: 2800 cmp r0, #0 8014c7a: d036 beq.n 8014cea <_svfiprintf_r+0x1d2> 8014c7c: 4b22 ldr r3, [pc, #136] @ (8014d08 <_svfiprintf_r+0x1f0>) 8014c7e: bb1b cbnz r3, 8014cc8 <_svfiprintf_r+0x1b0> 8014c80: 9b03 ldr r3, [sp, #12] 8014c82: 3307 adds r3, #7 8014c84: f023 0307 bic.w r3, r3, #7 8014c88: 3308 adds r3, #8 8014c8a: 9303 str r3, [sp, #12] 8014c8c: 9b09 ldr r3, [sp, #36] @ 0x24 8014c8e: 4433 add r3, r6 8014c90: 9309 str r3, [sp, #36] @ 0x24 8014c92: e76a b.n 8014b6a <_svfiprintf_r+0x52> 8014c94: 460c mov r4, r1 8014c96: 2001 movs r0, #1 8014c98: fb0c 3202 mla r2, ip, r2, r3 8014c9c: e7a8 b.n 8014bf0 <_svfiprintf_r+0xd8> 8014c9e: 2300 movs r3, #0 8014ca0: f04f 0c0a mov.w ip, #10 8014ca4: 4619 mov r1, r3 8014ca6: 3401 adds r4, #1 8014ca8: 9305 str r3, [sp, #20] 8014caa: 4620 mov r0, r4 8014cac: f810 2b01 ldrb.w r2, [r0], #1 8014cb0: 3a30 subs r2, #48 @ 0x30 8014cb2: 2a09 cmp r2, #9 8014cb4: d903 bls.n 8014cbe <_svfiprintf_r+0x1a6> 8014cb6: 2b00 cmp r3, #0 8014cb8: d0c6 beq.n 8014c48 <_svfiprintf_r+0x130> 8014cba: 9105 str r1, [sp, #20] 8014cbc: e7c4 b.n 8014c48 <_svfiprintf_r+0x130> 8014cbe: 4604 mov r4, r0 8014cc0: 2301 movs r3, #1 8014cc2: fb0c 2101 mla r1, ip, r1, r2 8014cc6: e7f0 b.n 8014caa <_svfiprintf_r+0x192> 8014cc8: ab03 add r3, sp, #12 8014cca: 9300 str r3, [sp, #0] 8014ccc: 462a mov r2, r5 8014cce: 4638 mov r0, r7 8014cd0: 4b0e ldr r3, [pc, #56] @ (8014d0c <_svfiprintf_r+0x1f4>) 8014cd2: a904 add r1, sp, #16 8014cd4: f7fe fb26 bl 8013324 <_printf_float> 8014cd8: 1c42 adds r2, r0, #1 8014cda: 4606 mov r6, r0 8014cdc: d1d6 bne.n 8014c8c <_svfiprintf_r+0x174> 8014cde: 89ab ldrh r3, [r5, #12] 8014ce0: 065b lsls r3, r3, #25 8014ce2: f53f af2d bmi.w 8014b40 <_svfiprintf_r+0x28> 8014ce6: 9809 ldr r0, [sp, #36] @ 0x24 8014ce8: e72c b.n 8014b44 <_svfiprintf_r+0x2c> 8014cea: ab03 add r3, sp, #12 8014cec: 9300 str r3, [sp, #0] 8014cee: 462a mov r2, r5 8014cf0: 4638 mov r0, r7 8014cf2: 4b06 ldr r3, [pc, #24] @ (8014d0c <_svfiprintf_r+0x1f4>) 8014cf4: a904 add r1, sp, #16 8014cf6: f7fe fdb3 bl 8013860 <_printf_i> 8014cfa: e7ed b.n 8014cd8 <_svfiprintf_r+0x1c0> 8014cfc: 080164d9 .word 0x080164d9 8014d00: 080164df .word 0x080164df 8014d04: 080164e3 .word 0x080164e3 8014d08: 08013325 .word 0x08013325 8014d0c: 08014a61 .word 0x08014a61 08014d10 <__sfputc_r>: 8014d10: 6893 ldr r3, [r2, #8] 8014d12: b410 push {r4} 8014d14: 3b01 subs r3, #1 8014d16: 2b00 cmp r3, #0 8014d18: 6093 str r3, [r2, #8] 8014d1a: da07 bge.n 8014d2c <__sfputc_r+0x1c> 8014d1c: 6994 ldr r4, [r2, #24] 8014d1e: 42a3 cmp r3, r4 8014d20: db01 blt.n 8014d26 <__sfputc_r+0x16> 8014d22: 290a cmp r1, #10 8014d24: d102 bne.n 8014d2c <__sfputc_r+0x1c> 8014d26: bc10 pop {r4} 8014d28: f000 be8e b.w 8015a48 <__swbuf_r> 8014d2c: 6813 ldr r3, [r2, #0] 8014d2e: 1c58 adds r0, r3, #1 8014d30: 6010 str r0, [r2, #0] 8014d32: 7019 strb r1, [r3, #0] 8014d34: 4608 mov r0, r1 8014d36: bc10 pop {r4} 8014d38: 4770 bx lr 08014d3a <__sfputs_r>: 8014d3a: b5f8 push {r3, r4, r5, r6, r7, lr} 8014d3c: 4606 mov r6, r0 8014d3e: 460f mov r7, r1 8014d40: 4614 mov r4, r2 8014d42: 18d5 adds r5, r2, r3 8014d44: 42ac cmp r4, r5 8014d46: d101 bne.n 8014d4c <__sfputs_r+0x12> 8014d48: 2000 movs r0, #0 8014d4a: e007 b.n 8014d5c <__sfputs_r+0x22> 8014d4c: 463a mov r2, r7 8014d4e: 4630 mov r0, r6 8014d50: f814 1b01 ldrb.w r1, [r4], #1 8014d54: f7ff ffdc bl 8014d10 <__sfputc_r> 8014d58: 1c43 adds r3, r0, #1 8014d5a: d1f3 bne.n 8014d44 <__sfputs_r+0xa> 8014d5c: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 08014d60 <_vfiprintf_r>: 8014d60: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8014d64: 460d mov r5, r1 8014d66: 4614 mov r4, r2 8014d68: 4698 mov r8, r3 8014d6a: 4606 mov r6, r0 8014d6c: b09d sub sp, #116 @ 0x74 8014d6e: b118 cbz r0, 8014d78 <_vfiprintf_r+0x18> 8014d70: 6a03 ldr r3, [r0, #32] 8014d72: b90b cbnz r3, 8014d78 <_vfiprintf_r+0x18> 8014d74: f7fe ff1e bl 8013bb4 <__sinit> 8014d78: 6e6b ldr r3, [r5, #100] @ 0x64 8014d7a: 07d9 lsls r1, r3, #31 8014d7c: d405 bmi.n 8014d8a <_vfiprintf_r+0x2a> 8014d7e: 89ab ldrh r3, [r5, #12] 8014d80: 059a lsls r2, r3, #22 8014d82: d402 bmi.n 8014d8a <_vfiprintf_r+0x2a> 8014d84: 6da8 ldr r0, [r5, #88] @ 0x58 8014d86: f7fe ffcc bl 8013d22 <__retarget_lock_acquire_recursive> 8014d8a: 89ab ldrh r3, [r5, #12] 8014d8c: 071b lsls r3, r3, #28 8014d8e: d501 bpl.n 8014d94 <_vfiprintf_r+0x34> 8014d90: 692b ldr r3, [r5, #16] 8014d92: b99b cbnz r3, 8014dbc <_vfiprintf_r+0x5c> 8014d94: 4629 mov r1, r5 8014d96: 4630 mov r0, r6 8014d98: f000 fe94 bl 8015ac4 <__swsetup_r> 8014d9c: b170 cbz r0, 8014dbc <_vfiprintf_r+0x5c> 8014d9e: 6e6b ldr r3, [r5, #100] @ 0x64 8014da0: 07dc lsls r4, r3, #31 8014da2: d504 bpl.n 8014dae <_vfiprintf_r+0x4e> 8014da4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8014da8: b01d add sp, #116 @ 0x74 8014daa: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8014dae: 89ab ldrh r3, [r5, #12] 8014db0: 0598 lsls r0, r3, #22 8014db2: d4f7 bmi.n 8014da4 <_vfiprintf_r+0x44> 8014db4: 6da8 ldr r0, [r5, #88] @ 0x58 8014db6: f7fe ffb5 bl 8013d24 <__retarget_lock_release_recursive> 8014dba: e7f3 b.n 8014da4 <_vfiprintf_r+0x44> 8014dbc: 2300 movs r3, #0 8014dbe: 9309 str r3, [sp, #36] @ 0x24 8014dc0: 2320 movs r3, #32 8014dc2: f88d 3029 strb.w r3, [sp, #41] @ 0x29 8014dc6: 2330 movs r3, #48 @ 0x30 8014dc8: f04f 0901 mov.w r9, #1 8014dcc: f8cd 800c str.w r8, [sp, #12] 8014dd0: f8df 81a8 ldr.w r8, [pc, #424] @ 8014f7c <_vfiprintf_r+0x21c> 8014dd4: f88d 302a strb.w r3, [sp, #42] @ 0x2a 8014dd8: 4623 mov r3, r4 8014dda: 469a mov sl, r3 8014ddc: f813 2b01 ldrb.w r2, [r3], #1 8014de0: b10a cbz r2, 8014de6 <_vfiprintf_r+0x86> 8014de2: 2a25 cmp r2, #37 @ 0x25 8014de4: d1f9 bne.n 8014dda <_vfiprintf_r+0x7a> 8014de6: ebba 0b04 subs.w fp, sl, r4 8014dea: d00b beq.n 8014e04 <_vfiprintf_r+0xa4> 8014dec: 465b mov r3, fp 8014dee: 4622 mov r2, r4 8014df0: 4629 mov r1, r5 8014df2: 4630 mov r0, r6 8014df4: f7ff ffa1 bl 8014d3a <__sfputs_r> 8014df8: 3001 adds r0, #1 8014dfa: f000 80a7 beq.w 8014f4c <_vfiprintf_r+0x1ec> 8014dfe: 9a09 ldr r2, [sp, #36] @ 0x24 8014e00: 445a add r2, fp 8014e02: 9209 str r2, [sp, #36] @ 0x24 8014e04: f89a 3000 ldrb.w r3, [sl] 8014e08: 2b00 cmp r3, #0 8014e0a: f000 809f beq.w 8014f4c <_vfiprintf_r+0x1ec> 8014e0e: 2300 movs r3, #0 8014e10: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8014e14: e9cd 2305 strd r2, r3, [sp, #20] 8014e18: f10a 0a01 add.w sl, sl, #1 8014e1c: 9304 str r3, [sp, #16] 8014e1e: 9307 str r3, [sp, #28] 8014e20: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8014e24: 931a str r3, [sp, #104] @ 0x68 8014e26: 4654 mov r4, sl 8014e28: 2205 movs r2, #5 8014e2a: f814 1b01 ldrb.w r1, [r4], #1 8014e2e: 4853 ldr r0, [pc, #332] @ (8014f7c <_vfiprintf_r+0x21c>) 8014e30: f7fe ff7e bl 8013d30 8014e34: 9a04 ldr r2, [sp, #16] 8014e36: b9d8 cbnz r0, 8014e70 <_vfiprintf_r+0x110> 8014e38: 06d1 lsls r1, r2, #27 8014e3a: bf44 itt mi 8014e3c: 2320 movmi r3, #32 8014e3e: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8014e42: 0713 lsls r3, r2, #28 8014e44: bf44 itt mi 8014e46: 232b movmi r3, #43 @ 0x2b 8014e48: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8014e4c: f89a 3000 ldrb.w r3, [sl] 8014e50: 2b2a cmp r3, #42 @ 0x2a 8014e52: d015 beq.n 8014e80 <_vfiprintf_r+0x120> 8014e54: 4654 mov r4, sl 8014e56: 2000 movs r0, #0 8014e58: f04f 0c0a mov.w ip, #10 8014e5c: 9a07 ldr r2, [sp, #28] 8014e5e: 4621 mov r1, r4 8014e60: f811 3b01 ldrb.w r3, [r1], #1 8014e64: 3b30 subs r3, #48 @ 0x30 8014e66: 2b09 cmp r3, #9 8014e68: d94b bls.n 8014f02 <_vfiprintf_r+0x1a2> 8014e6a: b1b0 cbz r0, 8014e9a <_vfiprintf_r+0x13a> 8014e6c: 9207 str r2, [sp, #28] 8014e6e: e014 b.n 8014e9a <_vfiprintf_r+0x13a> 8014e70: eba0 0308 sub.w r3, r0, r8 8014e74: fa09 f303 lsl.w r3, r9, r3 8014e78: 4313 orrs r3, r2 8014e7a: 46a2 mov sl, r4 8014e7c: 9304 str r3, [sp, #16] 8014e7e: e7d2 b.n 8014e26 <_vfiprintf_r+0xc6> 8014e80: 9b03 ldr r3, [sp, #12] 8014e82: 1d19 adds r1, r3, #4 8014e84: 681b ldr r3, [r3, #0] 8014e86: 9103 str r1, [sp, #12] 8014e88: 2b00 cmp r3, #0 8014e8a: bfbb ittet lt 8014e8c: 425b neglt r3, r3 8014e8e: f042 0202 orrlt.w r2, r2, #2 8014e92: 9307 strge r3, [sp, #28] 8014e94: 9307 strlt r3, [sp, #28] 8014e96: bfb8 it lt 8014e98: 9204 strlt r2, [sp, #16] 8014e9a: 7823 ldrb r3, [r4, #0] 8014e9c: 2b2e cmp r3, #46 @ 0x2e 8014e9e: d10a bne.n 8014eb6 <_vfiprintf_r+0x156> 8014ea0: 7863 ldrb r3, [r4, #1] 8014ea2: 2b2a cmp r3, #42 @ 0x2a 8014ea4: d132 bne.n 8014f0c <_vfiprintf_r+0x1ac> 8014ea6: 9b03 ldr r3, [sp, #12] 8014ea8: 3402 adds r4, #2 8014eaa: 1d1a adds r2, r3, #4 8014eac: 681b ldr r3, [r3, #0] 8014eae: 9203 str r2, [sp, #12] 8014eb0: ea43 73e3 orr.w r3, r3, r3, asr #31 8014eb4: 9305 str r3, [sp, #20] 8014eb6: f8df a0c8 ldr.w sl, [pc, #200] @ 8014f80 <_vfiprintf_r+0x220> 8014eba: 2203 movs r2, #3 8014ebc: 4650 mov r0, sl 8014ebe: 7821 ldrb r1, [r4, #0] 8014ec0: f7fe ff36 bl 8013d30 8014ec4: b138 cbz r0, 8014ed6 <_vfiprintf_r+0x176> 8014ec6: 2240 movs r2, #64 @ 0x40 8014ec8: 9b04 ldr r3, [sp, #16] 8014eca: eba0 000a sub.w r0, r0, sl 8014ece: 4082 lsls r2, r0 8014ed0: 4313 orrs r3, r2 8014ed2: 3401 adds r4, #1 8014ed4: 9304 str r3, [sp, #16] 8014ed6: f814 1b01 ldrb.w r1, [r4], #1 8014eda: 2206 movs r2, #6 8014edc: 4829 ldr r0, [pc, #164] @ (8014f84 <_vfiprintf_r+0x224>) 8014ede: f88d 1028 strb.w r1, [sp, #40] @ 0x28 8014ee2: f7fe ff25 bl 8013d30 8014ee6: 2800 cmp r0, #0 8014ee8: d03f beq.n 8014f6a <_vfiprintf_r+0x20a> 8014eea: 4b27 ldr r3, [pc, #156] @ (8014f88 <_vfiprintf_r+0x228>) 8014eec: bb1b cbnz r3, 8014f36 <_vfiprintf_r+0x1d6> 8014eee: 9b03 ldr r3, [sp, #12] 8014ef0: 3307 adds r3, #7 8014ef2: f023 0307 bic.w r3, r3, #7 8014ef6: 3308 adds r3, #8 8014ef8: 9303 str r3, [sp, #12] 8014efa: 9b09 ldr r3, [sp, #36] @ 0x24 8014efc: 443b add r3, r7 8014efe: 9309 str r3, [sp, #36] @ 0x24 8014f00: e76a b.n 8014dd8 <_vfiprintf_r+0x78> 8014f02: 460c mov r4, r1 8014f04: 2001 movs r0, #1 8014f06: fb0c 3202 mla r2, ip, r2, r3 8014f0a: e7a8 b.n 8014e5e <_vfiprintf_r+0xfe> 8014f0c: 2300 movs r3, #0 8014f0e: f04f 0c0a mov.w ip, #10 8014f12: 4619 mov r1, r3 8014f14: 3401 adds r4, #1 8014f16: 9305 str r3, [sp, #20] 8014f18: 4620 mov r0, r4 8014f1a: f810 2b01 ldrb.w r2, [r0], #1 8014f1e: 3a30 subs r2, #48 @ 0x30 8014f20: 2a09 cmp r2, #9 8014f22: d903 bls.n 8014f2c <_vfiprintf_r+0x1cc> 8014f24: 2b00 cmp r3, #0 8014f26: d0c6 beq.n 8014eb6 <_vfiprintf_r+0x156> 8014f28: 9105 str r1, [sp, #20] 8014f2a: e7c4 b.n 8014eb6 <_vfiprintf_r+0x156> 8014f2c: 4604 mov r4, r0 8014f2e: 2301 movs r3, #1 8014f30: fb0c 2101 mla r1, ip, r1, r2 8014f34: e7f0 b.n 8014f18 <_vfiprintf_r+0x1b8> 8014f36: ab03 add r3, sp, #12 8014f38: 9300 str r3, [sp, #0] 8014f3a: 462a mov r2, r5 8014f3c: 4630 mov r0, r6 8014f3e: 4b13 ldr r3, [pc, #76] @ (8014f8c <_vfiprintf_r+0x22c>) 8014f40: a904 add r1, sp, #16 8014f42: f7fe f9ef bl 8013324 <_printf_float> 8014f46: 4607 mov r7, r0 8014f48: 1c78 adds r0, r7, #1 8014f4a: d1d6 bne.n 8014efa <_vfiprintf_r+0x19a> 8014f4c: 6e6b ldr r3, [r5, #100] @ 0x64 8014f4e: 07d9 lsls r1, r3, #31 8014f50: d405 bmi.n 8014f5e <_vfiprintf_r+0x1fe> 8014f52: 89ab ldrh r3, [r5, #12] 8014f54: 059a lsls r2, r3, #22 8014f56: d402 bmi.n 8014f5e <_vfiprintf_r+0x1fe> 8014f58: 6da8 ldr r0, [r5, #88] @ 0x58 8014f5a: f7fe fee3 bl 8013d24 <__retarget_lock_release_recursive> 8014f5e: 89ab ldrh r3, [r5, #12] 8014f60: 065b lsls r3, r3, #25 8014f62: f53f af1f bmi.w 8014da4 <_vfiprintf_r+0x44> 8014f66: 9809 ldr r0, [sp, #36] @ 0x24 8014f68: e71e b.n 8014da8 <_vfiprintf_r+0x48> 8014f6a: ab03 add r3, sp, #12 8014f6c: 9300 str r3, [sp, #0] 8014f6e: 462a mov r2, r5 8014f70: 4630 mov r0, r6 8014f72: 4b06 ldr r3, [pc, #24] @ (8014f8c <_vfiprintf_r+0x22c>) 8014f74: a904 add r1, sp, #16 8014f76: f7fe fc73 bl 8013860 <_printf_i> 8014f7a: e7e4 b.n 8014f46 <_vfiprintf_r+0x1e6> 8014f7c: 080164d9 .word 0x080164d9 8014f80: 080164df .word 0x080164df 8014f84: 080164e3 .word 0x080164e3 8014f88: 08013325 .word 0x08013325 8014f8c: 08014d3b .word 0x08014d3b 08014f90 : 8014f90: 4b02 ldr r3, [pc, #8] @ (8014f9c ) 8014f92: 4601 mov r1, r0 8014f94: 6818 ldr r0, [r3, #0] 8014f96: f000 b825 b.w 8014fe4 <_malloc_r> 8014f9a: bf00 nop 8014f9c: 20000098 .word 0x20000098 08014fa0 : 8014fa0: b570 push {r4, r5, r6, lr} 8014fa2: 4e0f ldr r6, [pc, #60] @ (8014fe0 ) 8014fa4: 460c mov r4, r1 8014fa6: 6831 ldr r1, [r6, #0] 8014fa8: 4605 mov r5, r0 8014faa: b911 cbnz r1, 8014fb2 8014fac: f000 fe90 bl 8015cd0 <_sbrk_r> 8014fb0: 6030 str r0, [r6, #0] 8014fb2: 4621 mov r1, r4 8014fb4: 4628 mov r0, r5 8014fb6: f000 fe8b bl 8015cd0 <_sbrk_r> 8014fba: 1c43 adds r3, r0, #1 8014fbc: d103 bne.n 8014fc6 8014fbe: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff 8014fc2: 4620 mov r0, r4 8014fc4: bd70 pop {r4, r5, r6, pc} 8014fc6: 1cc4 adds r4, r0, #3 8014fc8: f024 0403 bic.w r4, r4, #3 8014fcc: 42a0 cmp r0, r4 8014fce: d0f8 beq.n 8014fc2 8014fd0: 1a21 subs r1, r4, r0 8014fd2: 4628 mov r0, r5 8014fd4: f000 fe7c bl 8015cd0 <_sbrk_r> 8014fd8: 3001 adds r0, #1 8014fda: d1f2 bne.n 8014fc2 8014fdc: e7ef b.n 8014fbe 8014fde: bf00 nop 8014fe0: 20001348 .word 0x20001348 08014fe4 <_malloc_r>: 8014fe4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8014fe8: 1ccd adds r5, r1, #3 8014fea: f025 0503 bic.w r5, r5, #3 8014fee: 3508 adds r5, #8 8014ff0: 2d0c cmp r5, #12 8014ff2: bf38 it cc 8014ff4: 250c movcc r5, #12 8014ff6: 2d00 cmp r5, #0 8014ff8: 4606 mov r6, r0 8014ffa: db01 blt.n 8015000 <_malloc_r+0x1c> 8014ffc: 42a9 cmp r1, r5 8014ffe: d904 bls.n 801500a <_malloc_r+0x26> 8015000: 230c movs r3, #12 8015002: 6033 str r3, [r6, #0] 8015004: 2000 movs r0, #0 8015006: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 801500a: f8df 80d4 ldr.w r8, [pc, #212] @ 80150e0 <_malloc_r+0xfc> 801500e: f000 f911 bl 8015234 <__malloc_lock> 8015012: f8d8 3000 ldr.w r3, [r8] 8015016: 461c mov r4, r3 8015018: bb44 cbnz r4, 801506c <_malloc_r+0x88> 801501a: 4629 mov r1, r5 801501c: 4630 mov r0, r6 801501e: f7ff ffbf bl 8014fa0 8015022: 1c43 adds r3, r0, #1 8015024: 4604 mov r4, r0 8015026: d158 bne.n 80150da <_malloc_r+0xf6> 8015028: f8d8 4000 ldr.w r4, [r8] 801502c: 4627 mov r7, r4 801502e: 2f00 cmp r7, #0 8015030: d143 bne.n 80150ba <_malloc_r+0xd6> 8015032: 2c00 cmp r4, #0 8015034: d04b beq.n 80150ce <_malloc_r+0xea> 8015036: 6823 ldr r3, [r4, #0] 8015038: 4639 mov r1, r7 801503a: 4630 mov r0, r6 801503c: eb04 0903 add.w r9, r4, r3 8015040: f000 fe46 bl 8015cd0 <_sbrk_r> 8015044: 4581 cmp r9, r0 8015046: d142 bne.n 80150ce <_malloc_r+0xea> 8015048: 6821 ldr r1, [r4, #0] 801504a: 4630 mov r0, r6 801504c: 1a6d subs r5, r5, r1 801504e: 4629 mov r1, r5 8015050: f7ff ffa6 bl 8014fa0 8015054: 3001 adds r0, #1 8015056: d03a beq.n 80150ce <_malloc_r+0xea> 8015058: 6823 ldr r3, [r4, #0] 801505a: 442b add r3, r5 801505c: 6023 str r3, [r4, #0] 801505e: f8d8 3000 ldr.w r3, [r8] 8015062: 685a ldr r2, [r3, #4] 8015064: bb62 cbnz r2, 80150c0 <_malloc_r+0xdc> 8015066: f8c8 7000 str.w r7, [r8] 801506a: e00f b.n 801508c <_malloc_r+0xa8> 801506c: 6822 ldr r2, [r4, #0] 801506e: 1b52 subs r2, r2, r5 8015070: d420 bmi.n 80150b4 <_malloc_r+0xd0> 8015072: 2a0b cmp r2, #11 8015074: d917 bls.n 80150a6 <_malloc_r+0xc2> 8015076: 1961 adds r1, r4, r5 8015078: 42a3 cmp r3, r4 801507a: 6025 str r5, [r4, #0] 801507c: bf18 it ne 801507e: 6059 strne r1, [r3, #4] 8015080: 6863 ldr r3, [r4, #4] 8015082: bf08 it eq 8015084: f8c8 1000 streq.w r1, [r8] 8015088: 5162 str r2, [r4, r5] 801508a: 604b str r3, [r1, #4] 801508c: 4630 mov r0, r6 801508e: f000 f8d7 bl 8015240 <__malloc_unlock> 8015092: f104 000b add.w r0, r4, #11 8015096: 1d23 adds r3, r4, #4 8015098: f020 0007 bic.w r0, r0, #7 801509c: 1ac2 subs r2, r0, r3 801509e: bf1c itt ne 80150a0: 1a1b subne r3, r3, r0 80150a2: 50a3 strne r3, [r4, r2] 80150a4: e7af b.n 8015006 <_malloc_r+0x22> 80150a6: 6862 ldr r2, [r4, #4] 80150a8: 42a3 cmp r3, r4 80150aa: bf0c ite eq 80150ac: f8c8 2000 streq.w r2, [r8] 80150b0: 605a strne r2, [r3, #4] 80150b2: e7eb b.n 801508c <_malloc_r+0xa8> 80150b4: 4623 mov r3, r4 80150b6: 6864 ldr r4, [r4, #4] 80150b8: e7ae b.n 8015018 <_malloc_r+0x34> 80150ba: 463c mov r4, r7 80150bc: 687f ldr r7, [r7, #4] 80150be: e7b6 b.n 801502e <_malloc_r+0x4a> 80150c0: 461a mov r2, r3 80150c2: 685b ldr r3, [r3, #4] 80150c4: 42a3 cmp r3, r4 80150c6: d1fb bne.n 80150c0 <_malloc_r+0xdc> 80150c8: 2300 movs r3, #0 80150ca: 6053 str r3, [r2, #4] 80150cc: e7de b.n 801508c <_malloc_r+0xa8> 80150ce: 230c movs r3, #12 80150d0: 4630 mov r0, r6 80150d2: 6033 str r3, [r6, #0] 80150d4: f000 f8b4 bl 8015240 <__malloc_unlock> 80150d8: e794 b.n 8015004 <_malloc_r+0x20> 80150da: 6005 str r5, [r0, #0] 80150dc: e7d6 b.n 801508c <_malloc_r+0xa8> 80150de: bf00 nop 80150e0: 2000134c .word 0x2000134c 080150e4 <__sflush_r>: 80150e4: f9b1 200c ldrsh.w r2, [r1, #12] 80150e8: b5f8 push {r3, r4, r5, r6, r7, lr} 80150ea: 0716 lsls r6, r2, #28 80150ec: 4605 mov r5, r0 80150ee: 460c mov r4, r1 80150f0: d454 bmi.n 801519c <__sflush_r+0xb8> 80150f2: 684b ldr r3, [r1, #4] 80150f4: 2b00 cmp r3, #0 80150f6: dc02 bgt.n 80150fe <__sflush_r+0x1a> 80150f8: 6c0b ldr r3, [r1, #64] @ 0x40 80150fa: 2b00 cmp r3, #0 80150fc: dd48 ble.n 8015190 <__sflush_r+0xac> 80150fe: 6ae6 ldr r6, [r4, #44] @ 0x2c 8015100: 2e00 cmp r6, #0 8015102: d045 beq.n 8015190 <__sflush_r+0xac> 8015104: 2300 movs r3, #0 8015106: f412 5280 ands.w r2, r2, #4096 @ 0x1000 801510a: 682f ldr r7, [r5, #0] 801510c: 6a21 ldr r1, [r4, #32] 801510e: 602b str r3, [r5, #0] 8015110: d030 beq.n 8015174 <__sflush_r+0x90> 8015112: 6d62 ldr r2, [r4, #84] @ 0x54 8015114: 89a3 ldrh r3, [r4, #12] 8015116: 0759 lsls r1, r3, #29 8015118: d505 bpl.n 8015126 <__sflush_r+0x42> 801511a: 6863 ldr r3, [r4, #4] 801511c: 1ad2 subs r2, r2, r3 801511e: 6b63 ldr r3, [r4, #52] @ 0x34 8015120: b10b cbz r3, 8015126 <__sflush_r+0x42> 8015122: 6c23 ldr r3, [r4, #64] @ 0x40 8015124: 1ad2 subs r2, r2, r3 8015126: 2300 movs r3, #0 8015128: 4628 mov r0, r5 801512a: 6ae6 ldr r6, [r4, #44] @ 0x2c 801512c: 6a21 ldr r1, [r4, #32] 801512e: 47b0 blx r6 8015130: 1c43 adds r3, r0, #1 8015132: 89a3 ldrh r3, [r4, #12] 8015134: d106 bne.n 8015144 <__sflush_r+0x60> 8015136: 6829 ldr r1, [r5, #0] 8015138: 291d cmp r1, #29 801513a: d82b bhi.n 8015194 <__sflush_r+0xb0> 801513c: 4a28 ldr r2, [pc, #160] @ (80151e0 <__sflush_r+0xfc>) 801513e: 40ca lsrs r2, r1 8015140: 07d6 lsls r6, r2, #31 8015142: d527 bpl.n 8015194 <__sflush_r+0xb0> 8015144: 2200 movs r2, #0 8015146: 6062 str r2, [r4, #4] 8015148: 6922 ldr r2, [r4, #16] 801514a: 04d9 lsls r1, r3, #19 801514c: 6022 str r2, [r4, #0] 801514e: d504 bpl.n 801515a <__sflush_r+0x76> 8015150: 1c42 adds r2, r0, #1 8015152: d101 bne.n 8015158 <__sflush_r+0x74> 8015154: 682b ldr r3, [r5, #0] 8015156: b903 cbnz r3, 801515a <__sflush_r+0x76> 8015158: 6560 str r0, [r4, #84] @ 0x54 801515a: 6b61 ldr r1, [r4, #52] @ 0x34 801515c: 602f str r7, [r5, #0] 801515e: b1b9 cbz r1, 8015190 <__sflush_r+0xac> 8015160: f104 0344 add.w r3, r4, #68 @ 0x44 8015164: 4299 cmp r1, r3 8015166: d002 beq.n 801516e <__sflush_r+0x8a> 8015168: 4628 mov r0, r5 801516a: f000 fe11 bl 8015d90 <_free_r> 801516e: 2300 movs r3, #0 8015170: 6363 str r3, [r4, #52] @ 0x34 8015172: e00d b.n 8015190 <__sflush_r+0xac> 8015174: 2301 movs r3, #1 8015176: 4628 mov r0, r5 8015178: 47b0 blx r6 801517a: 4602 mov r2, r0 801517c: 1c50 adds r0, r2, #1 801517e: d1c9 bne.n 8015114 <__sflush_r+0x30> 8015180: 682b ldr r3, [r5, #0] 8015182: 2b00 cmp r3, #0 8015184: d0c6 beq.n 8015114 <__sflush_r+0x30> 8015186: 2b1d cmp r3, #29 8015188: d001 beq.n 801518e <__sflush_r+0xaa> 801518a: 2b16 cmp r3, #22 801518c: d11d bne.n 80151ca <__sflush_r+0xe6> 801518e: 602f str r7, [r5, #0] 8015190: 2000 movs r0, #0 8015192: e021 b.n 80151d8 <__sflush_r+0xf4> 8015194: f043 0340 orr.w r3, r3, #64 @ 0x40 8015198: b21b sxth r3, r3 801519a: e01a b.n 80151d2 <__sflush_r+0xee> 801519c: 690f ldr r7, [r1, #16] 801519e: 2f00 cmp r7, #0 80151a0: d0f6 beq.n 8015190 <__sflush_r+0xac> 80151a2: 0793 lsls r3, r2, #30 80151a4: bf18 it ne 80151a6: 2300 movne r3, #0 80151a8: 680e ldr r6, [r1, #0] 80151aa: bf08 it eq 80151ac: 694b ldreq r3, [r1, #20] 80151ae: 1bf6 subs r6, r6, r7 80151b0: 600f str r7, [r1, #0] 80151b2: 608b str r3, [r1, #8] 80151b4: 2e00 cmp r6, #0 80151b6: ddeb ble.n 8015190 <__sflush_r+0xac> 80151b8: 4633 mov r3, r6 80151ba: 463a mov r2, r7 80151bc: 4628 mov r0, r5 80151be: 6a21 ldr r1, [r4, #32] 80151c0: f8d4 c028 ldr.w ip, [r4, #40] @ 0x28 80151c4: 47e0 blx ip 80151c6: 2800 cmp r0, #0 80151c8: dc07 bgt.n 80151da <__sflush_r+0xf6> 80151ca: f9b4 300c ldrsh.w r3, [r4, #12] 80151ce: f043 0340 orr.w r3, r3, #64 @ 0x40 80151d2: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80151d6: 81a3 strh r3, [r4, #12] 80151d8: bdf8 pop {r3, r4, r5, r6, r7, pc} 80151da: 4407 add r7, r0 80151dc: 1a36 subs r6, r6, r0 80151de: e7e9 b.n 80151b4 <__sflush_r+0xd0> 80151e0: 20400001 .word 0x20400001 080151e4 <_fflush_r>: 80151e4: b538 push {r3, r4, r5, lr} 80151e6: 690b ldr r3, [r1, #16] 80151e8: 4605 mov r5, r0 80151ea: 460c mov r4, r1 80151ec: b913 cbnz r3, 80151f4 <_fflush_r+0x10> 80151ee: 2500 movs r5, #0 80151f0: 4628 mov r0, r5 80151f2: bd38 pop {r3, r4, r5, pc} 80151f4: b118 cbz r0, 80151fe <_fflush_r+0x1a> 80151f6: 6a03 ldr r3, [r0, #32] 80151f8: b90b cbnz r3, 80151fe <_fflush_r+0x1a> 80151fa: f7fe fcdb bl 8013bb4 <__sinit> 80151fe: f9b4 300c ldrsh.w r3, [r4, #12] 8015202: 2b00 cmp r3, #0 8015204: d0f3 beq.n 80151ee <_fflush_r+0xa> 8015206: 6e62 ldr r2, [r4, #100] @ 0x64 8015208: 07d0 lsls r0, r2, #31 801520a: d404 bmi.n 8015216 <_fflush_r+0x32> 801520c: 0599 lsls r1, r3, #22 801520e: d402 bmi.n 8015216 <_fflush_r+0x32> 8015210: 6da0 ldr r0, [r4, #88] @ 0x58 8015212: f7fe fd86 bl 8013d22 <__retarget_lock_acquire_recursive> 8015216: 4628 mov r0, r5 8015218: 4621 mov r1, r4 801521a: f7ff ff63 bl 80150e4 <__sflush_r> 801521e: 6e63 ldr r3, [r4, #100] @ 0x64 8015220: 4605 mov r5, r0 8015222: 07da lsls r2, r3, #31 8015224: d4e4 bmi.n 80151f0 <_fflush_r+0xc> 8015226: 89a3 ldrh r3, [r4, #12] 8015228: 059b lsls r3, r3, #22 801522a: d4e1 bmi.n 80151f0 <_fflush_r+0xc> 801522c: 6da0 ldr r0, [r4, #88] @ 0x58 801522e: f7fe fd79 bl 8013d24 <__retarget_lock_release_recursive> 8015232: e7dd b.n 80151f0 <_fflush_r+0xc> 08015234 <__malloc_lock>: 8015234: 4801 ldr r0, [pc, #4] @ (801523c <__malloc_lock+0x8>) 8015236: f7fe bd74 b.w 8013d22 <__retarget_lock_acquire_recursive> 801523a: bf00 nop 801523c: 20001344 .word 0x20001344 08015240 <__malloc_unlock>: 8015240: 4801 ldr r0, [pc, #4] @ (8015248 <__malloc_unlock+0x8>) 8015242: f7fe bd6f b.w 8013d24 <__retarget_lock_release_recursive> 8015246: bf00 nop 8015248: 20001344 .word 0x20001344 0801524c <_Balloc>: 801524c: b570 push {r4, r5, r6, lr} 801524e: 69c6 ldr r6, [r0, #28] 8015250: 4604 mov r4, r0 8015252: 460d mov r5, r1 8015254: b976 cbnz r6, 8015274 <_Balloc+0x28> 8015256: 2010 movs r0, #16 8015258: f7ff fe9a bl 8014f90 801525c: 4602 mov r2, r0 801525e: 61e0 str r0, [r4, #28] 8015260: b920 cbnz r0, 801526c <_Balloc+0x20> 8015262: 216b movs r1, #107 @ 0x6b 8015264: 4b17 ldr r3, [pc, #92] @ (80152c4 <_Balloc+0x78>) 8015266: 4818 ldr r0, [pc, #96] @ (80152c8 <_Balloc+0x7c>) 8015268: f7fe fd7e bl 8013d68 <__assert_func> 801526c: e9c0 6601 strd r6, r6, [r0, #4] 8015270: 6006 str r6, [r0, #0] 8015272: 60c6 str r6, [r0, #12] 8015274: 69e6 ldr r6, [r4, #28] 8015276: 68f3 ldr r3, [r6, #12] 8015278: b183 cbz r3, 801529c <_Balloc+0x50> 801527a: 69e3 ldr r3, [r4, #28] 801527c: 68db ldr r3, [r3, #12] 801527e: f853 0025 ldr.w r0, [r3, r5, lsl #2] 8015282: b9b8 cbnz r0, 80152b4 <_Balloc+0x68> 8015284: 2101 movs r1, #1 8015286: fa01 f605 lsl.w r6, r1, r5 801528a: 1d72 adds r2, r6, #5 801528c: 4620 mov r0, r4 801528e: 0092 lsls r2, r2, #2 8015290: f000 fd69 bl 8015d66 <_calloc_r> 8015294: b160 cbz r0, 80152b0 <_Balloc+0x64> 8015296: e9c0 5601 strd r5, r6, [r0, #4] 801529a: e00e b.n 80152ba <_Balloc+0x6e> 801529c: 2221 movs r2, #33 @ 0x21 801529e: 2104 movs r1, #4 80152a0: 4620 mov r0, r4 80152a2: f000 fd60 bl 8015d66 <_calloc_r> 80152a6: 69e3 ldr r3, [r4, #28] 80152a8: 60f0 str r0, [r6, #12] 80152aa: 68db ldr r3, [r3, #12] 80152ac: 2b00 cmp r3, #0 80152ae: d1e4 bne.n 801527a <_Balloc+0x2e> 80152b0: 2000 movs r0, #0 80152b2: bd70 pop {r4, r5, r6, pc} 80152b4: 6802 ldr r2, [r0, #0] 80152b6: f843 2025 str.w r2, [r3, r5, lsl #2] 80152ba: 2300 movs r3, #0 80152bc: e9c0 3303 strd r3, r3, [r0, #12] 80152c0: e7f7 b.n 80152b2 <_Balloc+0x66> 80152c2: bf00 nop 80152c4: 08016459 .word 0x08016459 80152c8: 080164ea .word 0x080164ea 080152cc <_Bfree>: 80152cc: b570 push {r4, r5, r6, lr} 80152ce: 69c6 ldr r6, [r0, #28] 80152d0: 4605 mov r5, r0 80152d2: 460c mov r4, r1 80152d4: b976 cbnz r6, 80152f4 <_Bfree+0x28> 80152d6: 2010 movs r0, #16 80152d8: f7ff fe5a bl 8014f90 80152dc: 4602 mov r2, r0 80152de: 61e8 str r0, [r5, #28] 80152e0: b920 cbnz r0, 80152ec <_Bfree+0x20> 80152e2: 218f movs r1, #143 @ 0x8f 80152e4: 4b08 ldr r3, [pc, #32] @ (8015308 <_Bfree+0x3c>) 80152e6: 4809 ldr r0, [pc, #36] @ (801530c <_Bfree+0x40>) 80152e8: f7fe fd3e bl 8013d68 <__assert_func> 80152ec: e9c0 6601 strd r6, r6, [r0, #4] 80152f0: 6006 str r6, [r0, #0] 80152f2: 60c6 str r6, [r0, #12] 80152f4: b13c cbz r4, 8015306 <_Bfree+0x3a> 80152f6: 69eb ldr r3, [r5, #28] 80152f8: 6862 ldr r2, [r4, #4] 80152fa: 68db ldr r3, [r3, #12] 80152fc: f853 1022 ldr.w r1, [r3, r2, lsl #2] 8015300: 6021 str r1, [r4, #0] 8015302: f843 4022 str.w r4, [r3, r2, lsl #2] 8015306: bd70 pop {r4, r5, r6, pc} 8015308: 08016459 .word 0x08016459 801530c: 080164ea .word 0x080164ea 08015310 <__multadd>: 8015310: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8015314: 4607 mov r7, r0 8015316: 460c mov r4, r1 8015318: 461e mov r6, r3 801531a: 2000 movs r0, #0 801531c: 690d ldr r5, [r1, #16] 801531e: f101 0c14 add.w ip, r1, #20 8015322: f8dc 3000 ldr.w r3, [ip] 8015326: 3001 adds r0, #1 8015328: b299 uxth r1, r3 801532a: fb02 6101 mla r1, r2, r1, r6 801532e: 0c1e lsrs r6, r3, #16 8015330: 0c0b lsrs r3, r1, #16 8015332: fb02 3306 mla r3, r2, r6, r3 8015336: b289 uxth r1, r1 8015338: eb01 4103 add.w r1, r1, r3, lsl #16 801533c: 4285 cmp r5, r0 801533e: ea4f 4613 mov.w r6, r3, lsr #16 8015342: f84c 1b04 str.w r1, [ip], #4 8015346: dcec bgt.n 8015322 <__multadd+0x12> 8015348: b30e cbz r6, 801538e <__multadd+0x7e> 801534a: 68a3 ldr r3, [r4, #8] 801534c: 42ab cmp r3, r5 801534e: dc19 bgt.n 8015384 <__multadd+0x74> 8015350: 6861 ldr r1, [r4, #4] 8015352: 4638 mov r0, r7 8015354: 3101 adds r1, #1 8015356: f7ff ff79 bl 801524c <_Balloc> 801535a: 4680 mov r8, r0 801535c: b928 cbnz r0, 801536a <__multadd+0x5a> 801535e: 4602 mov r2, r0 8015360: 21ba movs r1, #186 @ 0xba 8015362: 4b0c ldr r3, [pc, #48] @ (8015394 <__multadd+0x84>) 8015364: 480c ldr r0, [pc, #48] @ (8015398 <__multadd+0x88>) 8015366: f7fe fcff bl 8013d68 <__assert_func> 801536a: 6922 ldr r2, [r4, #16] 801536c: f104 010c add.w r1, r4, #12 8015370: 3202 adds r2, #2 8015372: 0092 lsls r2, r2, #2 8015374: 300c adds r0, #12 8015376: f7fe fce9 bl 8013d4c 801537a: 4621 mov r1, r4 801537c: 4638 mov r0, r7 801537e: f7ff ffa5 bl 80152cc <_Bfree> 8015382: 4644 mov r4, r8 8015384: eb04 0385 add.w r3, r4, r5, lsl #2 8015388: 3501 adds r5, #1 801538a: 615e str r6, [r3, #20] 801538c: 6125 str r5, [r4, #16] 801538e: 4620 mov r0, r4 8015390: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8015394: 080164c8 .word 0x080164c8 8015398: 080164ea .word 0x080164ea 0801539c <__hi0bits>: 801539c: 4603 mov r3, r0 801539e: f5b0 3f80 cmp.w r0, #65536 @ 0x10000 80153a2: bf3a itte cc 80153a4: 0403 lslcc r3, r0, #16 80153a6: 2010 movcc r0, #16 80153a8: 2000 movcs r0, #0 80153aa: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 80153ae: bf3c itt cc 80153b0: 021b lslcc r3, r3, #8 80153b2: 3008 addcc r0, #8 80153b4: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80153b8: bf3c itt cc 80153ba: 011b lslcc r3, r3, #4 80153bc: 3004 addcc r0, #4 80153be: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80153c2: bf3c itt cc 80153c4: 009b lslcc r3, r3, #2 80153c6: 3002 addcc r0, #2 80153c8: 2b00 cmp r3, #0 80153ca: db05 blt.n 80153d8 <__hi0bits+0x3c> 80153cc: f013 4f80 tst.w r3, #1073741824 @ 0x40000000 80153d0: f100 0001 add.w r0, r0, #1 80153d4: bf08 it eq 80153d6: 2020 moveq r0, #32 80153d8: 4770 bx lr 080153da <__lo0bits>: 80153da: 6803 ldr r3, [r0, #0] 80153dc: 4602 mov r2, r0 80153de: f013 0007 ands.w r0, r3, #7 80153e2: d00b beq.n 80153fc <__lo0bits+0x22> 80153e4: 07d9 lsls r1, r3, #31 80153e6: d421 bmi.n 801542c <__lo0bits+0x52> 80153e8: 0798 lsls r0, r3, #30 80153ea: bf49 itett mi 80153ec: 085b lsrmi r3, r3, #1 80153ee: 089b lsrpl r3, r3, #2 80153f0: 2001 movmi r0, #1 80153f2: 6013 strmi r3, [r2, #0] 80153f4: bf5c itt pl 80153f6: 2002 movpl r0, #2 80153f8: 6013 strpl r3, [r2, #0] 80153fa: 4770 bx lr 80153fc: b299 uxth r1, r3 80153fe: b909 cbnz r1, 8015404 <__lo0bits+0x2a> 8015400: 2010 movs r0, #16 8015402: 0c1b lsrs r3, r3, #16 8015404: b2d9 uxtb r1, r3 8015406: b909 cbnz r1, 801540c <__lo0bits+0x32> 8015408: 3008 adds r0, #8 801540a: 0a1b lsrs r3, r3, #8 801540c: 0719 lsls r1, r3, #28 801540e: bf04 itt eq 8015410: 091b lsreq r3, r3, #4 8015412: 3004 addeq r0, #4 8015414: 0799 lsls r1, r3, #30 8015416: bf04 itt eq 8015418: 089b lsreq r3, r3, #2 801541a: 3002 addeq r0, #2 801541c: 07d9 lsls r1, r3, #31 801541e: d403 bmi.n 8015428 <__lo0bits+0x4e> 8015420: 085b lsrs r3, r3, #1 8015422: f100 0001 add.w r0, r0, #1 8015426: d003 beq.n 8015430 <__lo0bits+0x56> 8015428: 6013 str r3, [r2, #0] 801542a: 4770 bx lr 801542c: 2000 movs r0, #0 801542e: 4770 bx lr 8015430: 2020 movs r0, #32 8015432: 4770 bx lr 08015434 <__i2b>: 8015434: b510 push {r4, lr} 8015436: 460c mov r4, r1 8015438: 2101 movs r1, #1 801543a: f7ff ff07 bl 801524c <_Balloc> 801543e: 4602 mov r2, r0 8015440: b928 cbnz r0, 801544e <__i2b+0x1a> 8015442: f240 1145 movw r1, #325 @ 0x145 8015446: 4b04 ldr r3, [pc, #16] @ (8015458 <__i2b+0x24>) 8015448: 4804 ldr r0, [pc, #16] @ (801545c <__i2b+0x28>) 801544a: f7fe fc8d bl 8013d68 <__assert_func> 801544e: 2301 movs r3, #1 8015450: 6144 str r4, [r0, #20] 8015452: 6103 str r3, [r0, #16] 8015454: bd10 pop {r4, pc} 8015456: bf00 nop 8015458: 080164c8 .word 0x080164c8 801545c: 080164ea .word 0x080164ea 08015460 <__multiply>: 8015460: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8015464: 4617 mov r7, r2 8015466: 690a ldr r2, [r1, #16] 8015468: 693b ldr r3, [r7, #16] 801546a: 4689 mov r9, r1 801546c: 429a cmp r2, r3 801546e: bfa2 ittt ge 8015470: 463b movge r3, r7 8015472: 460f movge r7, r1 8015474: 4699 movge r9, r3 8015476: 693d ldr r5, [r7, #16] 8015478: f8d9 a010 ldr.w sl, [r9, #16] 801547c: 68bb ldr r3, [r7, #8] 801547e: 6879 ldr r1, [r7, #4] 8015480: eb05 060a add.w r6, r5, sl 8015484: 42b3 cmp r3, r6 8015486: b085 sub sp, #20 8015488: bfb8 it lt 801548a: 3101 addlt r1, #1 801548c: f7ff fede bl 801524c <_Balloc> 8015490: b930 cbnz r0, 80154a0 <__multiply+0x40> 8015492: 4602 mov r2, r0 8015494: f44f 71b1 mov.w r1, #354 @ 0x162 8015498: 4b40 ldr r3, [pc, #256] @ (801559c <__multiply+0x13c>) 801549a: 4841 ldr r0, [pc, #260] @ (80155a0 <__multiply+0x140>) 801549c: f7fe fc64 bl 8013d68 <__assert_func> 80154a0: f100 0414 add.w r4, r0, #20 80154a4: 4623 mov r3, r4 80154a6: 2200 movs r2, #0 80154a8: eb04 0e86 add.w lr, r4, r6, lsl #2 80154ac: 4573 cmp r3, lr 80154ae: d320 bcc.n 80154f2 <__multiply+0x92> 80154b0: f107 0814 add.w r8, r7, #20 80154b4: f109 0114 add.w r1, r9, #20 80154b8: eb08 0585 add.w r5, r8, r5, lsl #2 80154bc: eb01 038a add.w r3, r1, sl, lsl #2 80154c0: 9302 str r3, [sp, #8] 80154c2: 1beb subs r3, r5, r7 80154c4: 3b15 subs r3, #21 80154c6: f023 0303 bic.w r3, r3, #3 80154ca: 3304 adds r3, #4 80154cc: 3715 adds r7, #21 80154ce: 42bd cmp r5, r7 80154d0: bf38 it cc 80154d2: 2304 movcc r3, #4 80154d4: 9301 str r3, [sp, #4] 80154d6: 9b02 ldr r3, [sp, #8] 80154d8: 9103 str r1, [sp, #12] 80154da: 428b cmp r3, r1 80154dc: d80c bhi.n 80154f8 <__multiply+0x98> 80154de: 2e00 cmp r6, #0 80154e0: dd03 ble.n 80154ea <__multiply+0x8a> 80154e2: f85e 3d04 ldr.w r3, [lr, #-4]! 80154e6: 2b00 cmp r3, #0 80154e8: d055 beq.n 8015596 <__multiply+0x136> 80154ea: 6106 str r6, [r0, #16] 80154ec: b005 add sp, #20 80154ee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80154f2: f843 2b04 str.w r2, [r3], #4 80154f6: e7d9 b.n 80154ac <__multiply+0x4c> 80154f8: f8b1 a000 ldrh.w sl, [r1] 80154fc: f1ba 0f00 cmp.w sl, #0 8015500: d01f beq.n 8015542 <__multiply+0xe2> 8015502: 46c4 mov ip, r8 8015504: 46a1 mov r9, r4 8015506: 2700 movs r7, #0 8015508: f85c 2b04 ldr.w r2, [ip], #4 801550c: f8d9 3000 ldr.w r3, [r9] 8015510: fa1f fb82 uxth.w fp, r2 8015514: b29b uxth r3, r3 8015516: fb0a 330b mla r3, sl, fp, r3 801551a: 443b add r3, r7 801551c: f8d9 7000 ldr.w r7, [r9] 8015520: 0c12 lsrs r2, r2, #16 8015522: 0c3f lsrs r7, r7, #16 8015524: fb0a 7202 mla r2, sl, r2, r7 8015528: eb02 4213 add.w r2, r2, r3, lsr #16 801552c: b29b uxth r3, r3 801552e: ea43 4302 orr.w r3, r3, r2, lsl #16 8015532: 4565 cmp r5, ip 8015534: ea4f 4712 mov.w r7, r2, lsr #16 8015538: f849 3b04 str.w r3, [r9], #4 801553c: d8e4 bhi.n 8015508 <__multiply+0xa8> 801553e: 9b01 ldr r3, [sp, #4] 8015540: 50e7 str r7, [r4, r3] 8015542: 9b03 ldr r3, [sp, #12] 8015544: 3104 adds r1, #4 8015546: f8b3 9002 ldrh.w r9, [r3, #2] 801554a: f1b9 0f00 cmp.w r9, #0 801554e: d020 beq.n 8015592 <__multiply+0x132> 8015550: 4647 mov r7, r8 8015552: 46a4 mov ip, r4 8015554: f04f 0a00 mov.w sl, #0 8015558: 6823 ldr r3, [r4, #0] 801555a: f8b7 b000 ldrh.w fp, [r7] 801555e: f8bc 2002 ldrh.w r2, [ip, #2] 8015562: b29b uxth r3, r3 8015564: fb09 220b mla r2, r9, fp, r2 8015568: 4452 add r2, sl 801556a: ea43 4302 orr.w r3, r3, r2, lsl #16 801556e: f84c 3b04 str.w r3, [ip], #4 8015572: f857 3b04 ldr.w r3, [r7], #4 8015576: ea4f 4a13 mov.w sl, r3, lsr #16 801557a: f8bc 3000 ldrh.w r3, [ip] 801557e: 42bd cmp r5, r7 8015580: fb09 330a mla r3, r9, sl, r3 8015584: eb03 4312 add.w r3, r3, r2, lsr #16 8015588: ea4f 4a13 mov.w sl, r3, lsr #16 801558c: d8e5 bhi.n 801555a <__multiply+0xfa> 801558e: 9a01 ldr r2, [sp, #4] 8015590: 50a3 str r3, [r4, r2] 8015592: 3404 adds r4, #4 8015594: e79f b.n 80154d6 <__multiply+0x76> 8015596: 3e01 subs r6, #1 8015598: e7a1 b.n 80154de <__multiply+0x7e> 801559a: bf00 nop 801559c: 080164c8 .word 0x080164c8 80155a0: 080164ea .word 0x080164ea 080155a4 <__pow5mult>: 80155a4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 80155a8: 4615 mov r5, r2 80155aa: f012 0203 ands.w r2, r2, #3 80155ae: 4607 mov r7, r0 80155b0: 460e mov r6, r1 80155b2: d007 beq.n 80155c4 <__pow5mult+0x20> 80155b4: 4c25 ldr r4, [pc, #148] @ (801564c <__pow5mult+0xa8>) 80155b6: 3a01 subs r2, #1 80155b8: 2300 movs r3, #0 80155ba: f854 2022 ldr.w r2, [r4, r2, lsl #2] 80155be: f7ff fea7 bl 8015310 <__multadd> 80155c2: 4606 mov r6, r0 80155c4: 10ad asrs r5, r5, #2 80155c6: d03d beq.n 8015644 <__pow5mult+0xa0> 80155c8: 69fc ldr r4, [r7, #28] 80155ca: b97c cbnz r4, 80155ec <__pow5mult+0x48> 80155cc: 2010 movs r0, #16 80155ce: f7ff fcdf bl 8014f90 80155d2: 4602 mov r2, r0 80155d4: 61f8 str r0, [r7, #28] 80155d6: b928 cbnz r0, 80155e4 <__pow5mult+0x40> 80155d8: f240 11b3 movw r1, #435 @ 0x1b3 80155dc: 4b1c ldr r3, [pc, #112] @ (8015650 <__pow5mult+0xac>) 80155de: 481d ldr r0, [pc, #116] @ (8015654 <__pow5mult+0xb0>) 80155e0: f7fe fbc2 bl 8013d68 <__assert_func> 80155e4: e9c0 4401 strd r4, r4, [r0, #4] 80155e8: 6004 str r4, [r0, #0] 80155ea: 60c4 str r4, [r0, #12] 80155ec: f8d7 801c ldr.w r8, [r7, #28] 80155f0: f8d8 4008 ldr.w r4, [r8, #8] 80155f4: b94c cbnz r4, 801560a <__pow5mult+0x66> 80155f6: f240 2171 movw r1, #625 @ 0x271 80155fa: 4638 mov r0, r7 80155fc: f7ff ff1a bl 8015434 <__i2b> 8015600: 2300 movs r3, #0 8015602: 4604 mov r4, r0 8015604: f8c8 0008 str.w r0, [r8, #8] 8015608: 6003 str r3, [r0, #0] 801560a: f04f 0900 mov.w r9, #0 801560e: 07eb lsls r3, r5, #31 8015610: d50a bpl.n 8015628 <__pow5mult+0x84> 8015612: 4631 mov r1, r6 8015614: 4622 mov r2, r4 8015616: 4638 mov r0, r7 8015618: f7ff ff22 bl 8015460 <__multiply> 801561c: 4680 mov r8, r0 801561e: 4631 mov r1, r6 8015620: 4638 mov r0, r7 8015622: f7ff fe53 bl 80152cc <_Bfree> 8015626: 4646 mov r6, r8 8015628: 106d asrs r5, r5, #1 801562a: d00b beq.n 8015644 <__pow5mult+0xa0> 801562c: 6820 ldr r0, [r4, #0] 801562e: b938 cbnz r0, 8015640 <__pow5mult+0x9c> 8015630: 4622 mov r2, r4 8015632: 4621 mov r1, r4 8015634: 4638 mov r0, r7 8015636: f7ff ff13 bl 8015460 <__multiply> 801563a: 6020 str r0, [r4, #0] 801563c: f8c0 9000 str.w r9, [r0] 8015640: 4604 mov r4, r0 8015642: e7e4 b.n 801560e <__pow5mult+0x6a> 8015644: 4630 mov r0, r6 8015646: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 801564a: bf00 nop 801564c: 08016550 .word 0x08016550 8015650: 08016459 .word 0x08016459 8015654: 080164ea .word 0x080164ea 08015658 <__lshift>: 8015658: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 801565c: 460c mov r4, r1 801565e: 4607 mov r7, r0 8015660: 4691 mov r9, r2 8015662: 6923 ldr r3, [r4, #16] 8015664: 6849 ldr r1, [r1, #4] 8015666: eb03 1862 add.w r8, r3, r2, asr #5 801566a: 68a3 ldr r3, [r4, #8] 801566c: ea4f 1a62 mov.w sl, r2, asr #5 8015670: f108 0601 add.w r6, r8, #1 8015674: 42b3 cmp r3, r6 8015676: db0b blt.n 8015690 <__lshift+0x38> 8015678: 4638 mov r0, r7 801567a: f7ff fde7 bl 801524c <_Balloc> 801567e: 4605 mov r5, r0 8015680: b948 cbnz r0, 8015696 <__lshift+0x3e> 8015682: 4602 mov r2, r0 8015684: f44f 71ef mov.w r1, #478 @ 0x1de 8015688: 4b27 ldr r3, [pc, #156] @ (8015728 <__lshift+0xd0>) 801568a: 4828 ldr r0, [pc, #160] @ (801572c <__lshift+0xd4>) 801568c: f7fe fb6c bl 8013d68 <__assert_func> 8015690: 3101 adds r1, #1 8015692: 005b lsls r3, r3, #1 8015694: e7ee b.n 8015674 <__lshift+0x1c> 8015696: 2300 movs r3, #0 8015698: f100 0114 add.w r1, r0, #20 801569c: f100 0210 add.w r2, r0, #16 80156a0: 4618 mov r0, r3 80156a2: 4553 cmp r3, sl 80156a4: db33 blt.n 801570e <__lshift+0xb6> 80156a6: 6920 ldr r0, [r4, #16] 80156a8: ea2a 7aea bic.w sl, sl, sl, asr #31 80156ac: f104 0314 add.w r3, r4, #20 80156b0: f019 091f ands.w r9, r9, #31 80156b4: eb01 018a add.w r1, r1, sl, lsl #2 80156b8: eb03 0c80 add.w ip, r3, r0, lsl #2 80156bc: d02b beq.n 8015716 <__lshift+0xbe> 80156be: 468a mov sl, r1 80156c0: 2200 movs r2, #0 80156c2: f1c9 0e20 rsb lr, r9, #32 80156c6: 6818 ldr r0, [r3, #0] 80156c8: fa00 f009 lsl.w r0, r0, r9 80156cc: 4310 orrs r0, r2 80156ce: f84a 0b04 str.w r0, [sl], #4 80156d2: f853 2b04 ldr.w r2, [r3], #4 80156d6: 459c cmp ip, r3 80156d8: fa22 f20e lsr.w r2, r2, lr 80156dc: d8f3 bhi.n 80156c6 <__lshift+0x6e> 80156de: ebac 0304 sub.w r3, ip, r4 80156e2: 3b15 subs r3, #21 80156e4: f023 0303 bic.w r3, r3, #3 80156e8: 3304 adds r3, #4 80156ea: f104 0015 add.w r0, r4, #21 80156ee: 4560 cmp r0, ip 80156f0: bf88 it hi 80156f2: 2304 movhi r3, #4 80156f4: 50ca str r2, [r1, r3] 80156f6: b10a cbz r2, 80156fc <__lshift+0xa4> 80156f8: f108 0602 add.w r6, r8, #2 80156fc: 3e01 subs r6, #1 80156fe: 4638 mov r0, r7 8015700: 4621 mov r1, r4 8015702: 612e str r6, [r5, #16] 8015704: f7ff fde2 bl 80152cc <_Bfree> 8015708: 4628 mov r0, r5 801570a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801570e: f842 0f04 str.w r0, [r2, #4]! 8015712: 3301 adds r3, #1 8015714: e7c5 b.n 80156a2 <__lshift+0x4a> 8015716: 3904 subs r1, #4 8015718: f853 2b04 ldr.w r2, [r3], #4 801571c: 459c cmp ip, r3 801571e: f841 2f04 str.w r2, [r1, #4]! 8015722: d8f9 bhi.n 8015718 <__lshift+0xc0> 8015724: e7ea b.n 80156fc <__lshift+0xa4> 8015726: bf00 nop 8015728: 080164c8 .word 0x080164c8 801572c: 080164ea .word 0x080164ea 08015730 <__mcmp>: 8015730: 4603 mov r3, r0 8015732: 690a ldr r2, [r1, #16] 8015734: 6900 ldr r0, [r0, #16] 8015736: b530 push {r4, r5, lr} 8015738: 1a80 subs r0, r0, r2 801573a: d10e bne.n 801575a <__mcmp+0x2a> 801573c: 3314 adds r3, #20 801573e: 3114 adds r1, #20 8015740: eb03 0482 add.w r4, r3, r2, lsl #2 8015744: eb01 0182 add.w r1, r1, r2, lsl #2 8015748: f854 5d04 ldr.w r5, [r4, #-4]! 801574c: f851 2d04 ldr.w r2, [r1, #-4]! 8015750: 4295 cmp r5, r2 8015752: d003 beq.n 801575c <__mcmp+0x2c> 8015754: d205 bcs.n 8015762 <__mcmp+0x32> 8015756: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801575a: bd30 pop {r4, r5, pc} 801575c: 42a3 cmp r3, r4 801575e: d3f3 bcc.n 8015748 <__mcmp+0x18> 8015760: e7fb b.n 801575a <__mcmp+0x2a> 8015762: 2001 movs r0, #1 8015764: e7f9 b.n 801575a <__mcmp+0x2a> ... 08015768 <__mdiff>: 8015768: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 801576c: 4689 mov r9, r1 801576e: 4606 mov r6, r0 8015770: 4611 mov r1, r2 8015772: 4648 mov r0, r9 8015774: 4614 mov r4, r2 8015776: f7ff ffdb bl 8015730 <__mcmp> 801577a: 1e05 subs r5, r0, #0 801577c: d112 bne.n 80157a4 <__mdiff+0x3c> 801577e: 4629 mov r1, r5 8015780: 4630 mov r0, r6 8015782: f7ff fd63 bl 801524c <_Balloc> 8015786: 4602 mov r2, r0 8015788: b928 cbnz r0, 8015796 <__mdiff+0x2e> 801578a: f240 2137 movw r1, #567 @ 0x237 801578e: 4b3e ldr r3, [pc, #248] @ (8015888 <__mdiff+0x120>) 8015790: 483e ldr r0, [pc, #248] @ (801588c <__mdiff+0x124>) 8015792: f7fe fae9 bl 8013d68 <__assert_func> 8015796: 2301 movs r3, #1 8015798: e9c0 3504 strd r3, r5, [r0, #16] 801579c: 4610 mov r0, r2 801579e: b003 add sp, #12 80157a0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80157a4: bfbc itt lt 80157a6: 464b movlt r3, r9 80157a8: 46a1 movlt r9, r4 80157aa: 4630 mov r0, r6 80157ac: f8d9 1004 ldr.w r1, [r9, #4] 80157b0: bfba itte lt 80157b2: 461c movlt r4, r3 80157b4: 2501 movlt r5, #1 80157b6: 2500 movge r5, #0 80157b8: f7ff fd48 bl 801524c <_Balloc> 80157bc: 4602 mov r2, r0 80157be: b918 cbnz r0, 80157c8 <__mdiff+0x60> 80157c0: f240 2145 movw r1, #581 @ 0x245 80157c4: 4b30 ldr r3, [pc, #192] @ (8015888 <__mdiff+0x120>) 80157c6: e7e3 b.n 8015790 <__mdiff+0x28> 80157c8: f100 0b14 add.w fp, r0, #20 80157cc: f8d9 7010 ldr.w r7, [r9, #16] 80157d0: f109 0310 add.w r3, r9, #16 80157d4: 60c5 str r5, [r0, #12] 80157d6: f04f 0c00 mov.w ip, #0 80157da: f109 0514 add.w r5, r9, #20 80157de: 46d9 mov r9, fp 80157e0: 6926 ldr r6, [r4, #16] 80157e2: f104 0e14 add.w lr, r4, #20 80157e6: eb05 0887 add.w r8, r5, r7, lsl #2 80157ea: eb0e 0686 add.w r6, lr, r6, lsl #2 80157ee: 9301 str r3, [sp, #4] 80157f0: 9b01 ldr r3, [sp, #4] 80157f2: f85e 0b04 ldr.w r0, [lr], #4 80157f6: f853 af04 ldr.w sl, [r3, #4]! 80157fa: b281 uxth r1, r0 80157fc: 9301 str r3, [sp, #4] 80157fe: fa1f f38a uxth.w r3, sl 8015802: 1a5b subs r3, r3, r1 8015804: 0c00 lsrs r0, r0, #16 8015806: 4463 add r3, ip 8015808: ebc0 401a rsb r0, r0, sl, lsr #16 801580c: eb00 4023 add.w r0, r0, r3, asr #16 8015810: b29b uxth r3, r3 8015812: ea43 4300 orr.w r3, r3, r0, lsl #16 8015816: 4576 cmp r6, lr 8015818: ea4f 4c20 mov.w ip, r0, asr #16 801581c: f849 3b04 str.w r3, [r9], #4 8015820: d8e6 bhi.n 80157f0 <__mdiff+0x88> 8015822: 1b33 subs r3, r6, r4 8015824: 3b15 subs r3, #21 8015826: f023 0303 bic.w r3, r3, #3 801582a: 3415 adds r4, #21 801582c: 3304 adds r3, #4 801582e: 42a6 cmp r6, r4 8015830: bf38 it cc 8015832: 2304 movcc r3, #4 8015834: 441d add r5, r3 8015836: 445b add r3, fp 8015838: 461e mov r6, r3 801583a: 462c mov r4, r5 801583c: 4544 cmp r4, r8 801583e: d30e bcc.n 801585e <__mdiff+0xf6> 8015840: f108 0103 add.w r1, r8, #3 8015844: 1b49 subs r1, r1, r5 8015846: f021 0103 bic.w r1, r1, #3 801584a: 3d03 subs r5, #3 801584c: 45a8 cmp r8, r5 801584e: bf38 it cc 8015850: 2100 movcc r1, #0 8015852: 440b add r3, r1 8015854: f853 1d04 ldr.w r1, [r3, #-4]! 8015858: b199 cbz r1, 8015882 <__mdiff+0x11a> 801585a: 6117 str r7, [r2, #16] 801585c: e79e b.n 801579c <__mdiff+0x34> 801585e: 46e6 mov lr, ip 8015860: f854 1b04 ldr.w r1, [r4], #4 8015864: fa1f fc81 uxth.w ip, r1 8015868: 44f4 add ip, lr 801586a: 0c08 lsrs r0, r1, #16 801586c: 4471 add r1, lr 801586e: eb00 402c add.w r0, r0, ip, asr #16 8015872: b289 uxth r1, r1 8015874: ea41 4100 orr.w r1, r1, r0, lsl #16 8015878: ea4f 4c20 mov.w ip, r0, asr #16 801587c: f846 1b04 str.w r1, [r6], #4 8015880: e7dc b.n 801583c <__mdiff+0xd4> 8015882: 3f01 subs r7, #1 8015884: e7e6 b.n 8015854 <__mdiff+0xec> 8015886: bf00 nop 8015888: 080164c8 .word 0x080164c8 801588c: 080164ea .word 0x080164ea 08015890 <__d2b>: 8015890: e92d 4373 stmdb sp!, {r0, r1, r4, r5, r6, r8, r9, lr} 8015894: 2101 movs r1, #1 8015896: 4690 mov r8, r2 8015898: 4699 mov r9, r3 801589a: 9e08 ldr r6, [sp, #32] 801589c: f7ff fcd6 bl 801524c <_Balloc> 80158a0: 4604 mov r4, r0 80158a2: b930 cbnz r0, 80158b2 <__d2b+0x22> 80158a4: 4602 mov r2, r0 80158a6: f240 310f movw r1, #783 @ 0x30f 80158aa: 4b23 ldr r3, [pc, #140] @ (8015938 <__d2b+0xa8>) 80158ac: 4823 ldr r0, [pc, #140] @ (801593c <__d2b+0xac>) 80158ae: f7fe fa5b bl 8013d68 <__assert_func> 80158b2: f3c9 550a ubfx r5, r9, #20, #11 80158b6: f3c9 0313 ubfx r3, r9, #0, #20 80158ba: b10d cbz r5, 80158c0 <__d2b+0x30> 80158bc: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80158c0: 9301 str r3, [sp, #4] 80158c2: f1b8 0300 subs.w r3, r8, #0 80158c6: d024 beq.n 8015912 <__d2b+0x82> 80158c8: 4668 mov r0, sp 80158ca: 9300 str r3, [sp, #0] 80158cc: f7ff fd85 bl 80153da <__lo0bits> 80158d0: e9dd 1200 ldrd r1, r2, [sp] 80158d4: b1d8 cbz r0, 801590e <__d2b+0x7e> 80158d6: f1c0 0320 rsb r3, r0, #32 80158da: fa02 f303 lsl.w r3, r2, r3 80158de: 430b orrs r3, r1 80158e0: 40c2 lsrs r2, r0 80158e2: 6163 str r3, [r4, #20] 80158e4: 9201 str r2, [sp, #4] 80158e6: 9b01 ldr r3, [sp, #4] 80158e8: 2b00 cmp r3, #0 80158ea: bf0c ite eq 80158ec: 2201 moveq r2, #1 80158ee: 2202 movne r2, #2 80158f0: 61a3 str r3, [r4, #24] 80158f2: 6122 str r2, [r4, #16] 80158f4: b1ad cbz r5, 8015922 <__d2b+0x92> 80158f6: f2a5 4533 subw r5, r5, #1075 @ 0x433 80158fa: 4405 add r5, r0 80158fc: 6035 str r5, [r6, #0] 80158fe: f1c0 0035 rsb r0, r0, #53 @ 0x35 8015902: 9b09 ldr r3, [sp, #36] @ 0x24 8015904: 6018 str r0, [r3, #0] 8015906: 4620 mov r0, r4 8015908: b002 add sp, #8 801590a: e8bd 8370 ldmia.w sp!, {r4, r5, r6, r8, r9, pc} 801590e: 6161 str r1, [r4, #20] 8015910: e7e9 b.n 80158e6 <__d2b+0x56> 8015912: a801 add r0, sp, #4 8015914: f7ff fd61 bl 80153da <__lo0bits> 8015918: 9b01 ldr r3, [sp, #4] 801591a: 2201 movs r2, #1 801591c: 6163 str r3, [r4, #20] 801591e: 3020 adds r0, #32 8015920: e7e7 b.n 80158f2 <__d2b+0x62> 8015922: f2a0 4032 subw r0, r0, #1074 @ 0x432 8015926: eb04 0382 add.w r3, r4, r2, lsl #2 801592a: 6030 str r0, [r6, #0] 801592c: 6918 ldr r0, [r3, #16] 801592e: f7ff fd35 bl 801539c <__hi0bits> 8015932: ebc0 1042 rsb r0, r0, r2, lsl #5 8015936: e7e4 b.n 8015902 <__d2b+0x72> 8015938: 080164c8 .word 0x080164c8 801593c: 080164ea .word 0x080164ea 08015940 <__sread>: 8015940: b510 push {r4, lr} 8015942: 460c mov r4, r1 8015944: f9b1 100e ldrsh.w r1, [r1, #14] 8015948: f000 f9b0 bl 8015cac <_read_r> 801594c: 2800 cmp r0, #0 801594e: bfab itete ge 8015950: 6d63 ldrge r3, [r4, #84] @ 0x54 8015952: 89a3 ldrhlt r3, [r4, #12] 8015954: 181b addge r3, r3, r0 8015956: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 801595a: bfac ite ge 801595c: 6563 strge r3, [r4, #84] @ 0x54 801595e: 81a3 strhlt r3, [r4, #12] 8015960: bd10 pop {r4, pc} 08015962 <__swrite>: 8015962: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8015966: 461f mov r7, r3 8015968: 898b ldrh r3, [r1, #12] 801596a: 4605 mov r5, r0 801596c: 05db lsls r3, r3, #23 801596e: 460c mov r4, r1 8015970: 4616 mov r6, r2 8015972: d505 bpl.n 8015980 <__swrite+0x1e> 8015974: 2302 movs r3, #2 8015976: 2200 movs r2, #0 8015978: f9b1 100e ldrsh.w r1, [r1, #14] 801597c: f000 f984 bl 8015c88 <_lseek_r> 8015980: 89a3 ldrh r3, [r4, #12] 8015982: 4632 mov r2, r6 8015984: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8015988: 81a3 strh r3, [r4, #12] 801598a: 4628 mov r0, r5 801598c: 463b mov r3, r7 801598e: f9b4 100e ldrsh.w r1, [r4, #14] 8015992: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8015996: f000 b9ab b.w 8015cf0 <_write_r> 0801599a <__sseek>: 801599a: b510 push {r4, lr} 801599c: 460c mov r4, r1 801599e: f9b1 100e ldrsh.w r1, [r1, #14] 80159a2: f000 f971 bl 8015c88 <_lseek_r> 80159a6: 1c43 adds r3, r0, #1 80159a8: 89a3 ldrh r3, [r4, #12] 80159aa: bf15 itete ne 80159ac: 6560 strne r0, [r4, #84] @ 0x54 80159ae: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 80159b2: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 80159b6: 81a3 strheq r3, [r4, #12] 80159b8: bf18 it ne 80159ba: 81a3 strhne r3, [r4, #12] 80159bc: bd10 pop {r4, pc} 080159be <__sclose>: 80159be: f9b1 100e ldrsh.w r1, [r1, #14] 80159c2: f000 b9a7 b.w 8015d14 <_close_r> ... 080159c8 : 80159c8: b40e push {r1, r2, r3} 80159ca: b503 push {r0, r1, lr} 80159cc: 4601 mov r1, r0 80159ce: ab03 add r3, sp, #12 80159d0: 4805 ldr r0, [pc, #20] @ (80159e8 ) 80159d2: f853 2b04 ldr.w r2, [r3], #4 80159d6: 6800 ldr r0, [r0, #0] 80159d8: 9301 str r3, [sp, #4] 80159da: f7ff f9c1 bl 8014d60 <_vfiprintf_r> 80159de: b002 add sp, #8 80159e0: f85d eb04 ldr.w lr, [sp], #4 80159e4: b003 add sp, #12 80159e6: 4770 bx lr 80159e8: 20000098 .word 0x20000098 080159ec <_realloc_r>: 80159ec: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80159f0: 4607 mov r7, r0 80159f2: 4614 mov r4, r2 80159f4: 460d mov r5, r1 80159f6: b921 cbnz r1, 8015a02 <_realloc_r+0x16> 80159f8: 4611 mov r1, r2 80159fa: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 80159fe: f7ff baf1 b.w 8014fe4 <_malloc_r> 8015a02: b92a cbnz r2, 8015a10 <_realloc_r+0x24> 8015a04: f000 f9c4 bl 8015d90 <_free_r> 8015a08: 4625 mov r5, r4 8015a0a: 4628 mov r0, r5 8015a0c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8015a10: f000 fa18 bl 8015e44 <_malloc_usable_size_r> 8015a14: 4284 cmp r4, r0 8015a16: 4606 mov r6, r0 8015a18: d802 bhi.n 8015a20 <_realloc_r+0x34> 8015a1a: ebb4 0f50 cmp.w r4, r0, lsr #1 8015a1e: d8f4 bhi.n 8015a0a <_realloc_r+0x1e> 8015a20: 4621 mov r1, r4 8015a22: 4638 mov r0, r7 8015a24: f7ff fade bl 8014fe4 <_malloc_r> 8015a28: 4680 mov r8, r0 8015a2a: b908 cbnz r0, 8015a30 <_realloc_r+0x44> 8015a2c: 4645 mov r5, r8 8015a2e: e7ec b.n 8015a0a <_realloc_r+0x1e> 8015a30: 42b4 cmp r4, r6 8015a32: 4622 mov r2, r4 8015a34: 4629 mov r1, r5 8015a36: bf28 it cs 8015a38: 4632 movcs r2, r6 8015a3a: f7fe f987 bl 8013d4c 8015a3e: 4629 mov r1, r5 8015a40: 4638 mov r0, r7 8015a42: f000 f9a5 bl 8015d90 <_free_r> 8015a46: e7f1 b.n 8015a2c <_realloc_r+0x40> 08015a48 <__swbuf_r>: 8015a48: b5f8 push {r3, r4, r5, r6, r7, lr} 8015a4a: 460e mov r6, r1 8015a4c: 4614 mov r4, r2 8015a4e: 4605 mov r5, r0 8015a50: b118 cbz r0, 8015a5a <__swbuf_r+0x12> 8015a52: 6a03 ldr r3, [r0, #32] 8015a54: b90b cbnz r3, 8015a5a <__swbuf_r+0x12> 8015a56: f7fe f8ad bl 8013bb4 <__sinit> 8015a5a: 69a3 ldr r3, [r4, #24] 8015a5c: 60a3 str r3, [r4, #8] 8015a5e: 89a3 ldrh r3, [r4, #12] 8015a60: 071a lsls r2, r3, #28 8015a62: d501 bpl.n 8015a68 <__swbuf_r+0x20> 8015a64: 6923 ldr r3, [r4, #16] 8015a66: b943 cbnz r3, 8015a7a <__swbuf_r+0x32> 8015a68: 4621 mov r1, r4 8015a6a: 4628 mov r0, r5 8015a6c: f000 f82a bl 8015ac4 <__swsetup_r> 8015a70: b118 cbz r0, 8015a7a <__swbuf_r+0x32> 8015a72: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff 8015a76: 4638 mov r0, r7 8015a78: bdf8 pop {r3, r4, r5, r6, r7, pc} 8015a7a: 6823 ldr r3, [r4, #0] 8015a7c: 6922 ldr r2, [r4, #16] 8015a7e: b2f6 uxtb r6, r6 8015a80: 1a98 subs r0, r3, r2 8015a82: 6963 ldr r3, [r4, #20] 8015a84: 4637 mov r7, r6 8015a86: 4283 cmp r3, r0 8015a88: dc05 bgt.n 8015a96 <__swbuf_r+0x4e> 8015a8a: 4621 mov r1, r4 8015a8c: 4628 mov r0, r5 8015a8e: f7ff fba9 bl 80151e4 <_fflush_r> 8015a92: 2800 cmp r0, #0 8015a94: d1ed bne.n 8015a72 <__swbuf_r+0x2a> 8015a96: 68a3 ldr r3, [r4, #8] 8015a98: 3b01 subs r3, #1 8015a9a: 60a3 str r3, [r4, #8] 8015a9c: 6823 ldr r3, [r4, #0] 8015a9e: 1c5a adds r2, r3, #1 8015aa0: 6022 str r2, [r4, #0] 8015aa2: 701e strb r6, [r3, #0] 8015aa4: 6962 ldr r2, [r4, #20] 8015aa6: 1c43 adds r3, r0, #1 8015aa8: 429a cmp r2, r3 8015aaa: d004 beq.n 8015ab6 <__swbuf_r+0x6e> 8015aac: 89a3 ldrh r3, [r4, #12] 8015aae: 07db lsls r3, r3, #31 8015ab0: d5e1 bpl.n 8015a76 <__swbuf_r+0x2e> 8015ab2: 2e0a cmp r6, #10 8015ab4: d1df bne.n 8015a76 <__swbuf_r+0x2e> 8015ab6: 4621 mov r1, r4 8015ab8: 4628 mov r0, r5 8015aba: f7ff fb93 bl 80151e4 <_fflush_r> 8015abe: 2800 cmp r0, #0 8015ac0: d0d9 beq.n 8015a76 <__swbuf_r+0x2e> 8015ac2: e7d6 b.n 8015a72 <__swbuf_r+0x2a> 08015ac4 <__swsetup_r>: 8015ac4: b538 push {r3, r4, r5, lr} 8015ac6: 4b29 ldr r3, [pc, #164] @ (8015b6c <__swsetup_r+0xa8>) 8015ac8: 4605 mov r5, r0 8015aca: 6818 ldr r0, [r3, #0] 8015acc: 460c mov r4, r1 8015ace: b118 cbz r0, 8015ad8 <__swsetup_r+0x14> 8015ad0: 6a03 ldr r3, [r0, #32] 8015ad2: b90b cbnz r3, 8015ad8 <__swsetup_r+0x14> 8015ad4: f7fe f86e bl 8013bb4 <__sinit> 8015ad8: f9b4 300c ldrsh.w r3, [r4, #12] 8015adc: 0719 lsls r1, r3, #28 8015ade: d422 bmi.n 8015b26 <__swsetup_r+0x62> 8015ae0: 06da lsls r2, r3, #27 8015ae2: d407 bmi.n 8015af4 <__swsetup_r+0x30> 8015ae4: 2209 movs r2, #9 8015ae6: 602a str r2, [r5, #0] 8015ae8: f043 0340 orr.w r3, r3, #64 @ 0x40 8015aec: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015af0: 81a3 strh r3, [r4, #12] 8015af2: e033 b.n 8015b5c <__swsetup_r+0x98> 8015af4: 0758 lsls r0, r3, #29 8015af6: d512 bpl.n 8015b1e <__swsetup_r+0x5a> 8015af8: 6b61 ldr r1, [r4, #52] @ 0x34 8015afa: b141 cbz r1, 8015b0e <__swsetup_r+0x4a> 8015afc: f104 0344 add.w r3, r4, #68 @ 0x44 8015b00: 4299 cmp r1, r3 8015b02: d002 beq.n 8015b0a <__swsetup_r+0x46> 8015b04: 4628 mov r0, r5 8015b06: f000 f943 bl 8015d90 <_free_r> 8015b0a: 2300 movs r3, #0 8015b0c: 6363 str r3, [r4, #52] @ 0x34 8015b0e: 89a3 ldrh r3, [r4, #12] 8015b10: f023 0324 bic.w r3, r3, #36 @ 0x24 8015b14: 81a3 strh r3, [r4, #12] 8015b16: 2300 movs r3, #0 8015b18: 6063 str r3, [r4, #4] 8015b1a: 6923 ldr r3, [r4, #16] 8015b1c: 6023 str r3, [r4, #0] 8015b1e: 89a3 ldrh r3, [r4, #12] 8015b20: f043 0308 orr.w r3, r3, #8 8015b24: 81a3 strh r3, [r4, #12] 8015b26: 6923 ldr r3, [r4, #16] 8015b28: b94b cbnz r3, 8015b3e <__swsetup_r+0x7a> 8015b2a: 89a3 ldrh r3, [r4, #12] 8015b2c: f403 7320 and.w r3, r3, #640 @ 0x280 8015b30: f5b3 7f00 cmp.w r3, #512 @ 0x200 8015b34: d003 beq.n 8015b3e <__swsetup_r+0x7a> 8015b36: 4621 mov r1, r4 8015b38: 4628 mov r0, r5 8015b3a: f000 f83e bl 8015bba <__smakebuf_r> 8015b3e: f9b4 300c ldrsh.w r3, [r4, #12] 8015b42: f013 0201 ands.w r2, r3, #1 8015b46: d00a beq.n 8015b5e <__swsetup_r+0x9a> 8015b48: 2200 movs r2, #0 8015b4a: 60a2 str r2, [r4, #8] 8015b4c: 6962 ldr r2, [r4, #20] 8015b4e: 4252 negs r2, r2 8015b50: 61a2 str r2, [r4, #24] 8015b52: 6922 ldr r2, [r4, #16] 8015b54: b942 cbnz r2, 8015b68 <__swsetup_r+0xa4> 8015b56: f013 0080 ands.w r0, r3, #128 @ 0x80 8015b5a: d1c5 bne.n 8015ae8 <__swsetup_r+0x24> 8015b5c: bd38 pop {r3, r4, r5, pc} 8015b5e: 0799 lsls r1, r3, #30 8015b60: bf58 it pl 8015b62: 6962 ldrpl r2, [r4, #20] 8015b64: 60a2 str r2, [r4, #8] 8015b66: e7f4 b.n 8015b52 <__swsetup_r+0x8e> 8015b68: 2000 movs r0, #0 8015b6a: e7f7 b.n 8015b5c <__swsetup_r+0x98> 8015b6c: 20000098 .word 0x20000098 08015b70 <__swhatbuf_r>: 8015b70: b570 push {r4, r5, r6, lr} 8015b72: 460c mov r4, r1 8015b74: f9b1 100e ldrsh.w r1, [r1, #14] 8015b78: 4615 mov r5, r2 8015b7a: 2900 cmp r1, #0 8015b7c: 461e mov r6, r3 8015b7e: b096 sub sp, #88 @ 0x58 8015b80: da0c bge.n 8015b9c <__swhatbuf_r+0x2c> 8015b82: 89a3 ldrh r3, [r4, #12] 8015b84: 2100 movs r1, #0 8015b86: f013 0f80 tst.w r3, #128 @ 0x80 8015b8a: bf14 ite ne 8015b8c: 2340 movne r3, #64 @ 0x40 8015b8e: f44f 6380 moveq.w r3, #1024 @ 0x400 8015b92: 2000 movs r0, #0 8015b94: 6031 str r1, [r6, #0] 8015b96: 602b str r3, [r5, #0] 8015b98: b016 add sp, #88 @ 0x58 8015b9a: bd70 pop {r4, r5, r6, pc} 8015b9c: 466a mov r2, sp 8015b9e: f000 f8c9 bl 8015d34 <_fstat_r> 8015ba2: 2800 cmp r0, #0 8015ba4: dbed blt.n 8015b82 <__swhatbuf_r+0x12> 8015ba6: 9901 ldr r1, [sp, #4] 8015ba8: f401 4170 and.w r1, r1, #61440 @ 0xf000 8015bac: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 8015bb0: 4259 negs r1, r3 8015bb2: 4159 adcs r1, r3 8015bb4: f44f 6380 mov.w r3, #1024 @ 0x400 8015bb8: e7eb b.n 8015b92 <__swhatbuf_r+0x22> 08015bba <__smakebuf_r>: 8015bba: 898b ldrh r3, [r1, #12] 8015bbc: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8015bbe: 079d lsls r5, r3, #30 8015bc0: 4606 mov r6, r0 8015bc2: 460c mov r4, r1 8015bc4: d507 bpl.n 8015bd6 <__smakebuf_r+0x1c> 8015bc6: f104 0347 add.w r3, r4, #71 @ 0x47 8015bca: 6023 str r3, [r4, #0] 8015bcc: 6123 str r3, [r4, #16] 8015bce: 2301 movs r3, #1 8015bd0: 6163 str r3, [r4, #20] 8015bd2: b003 add sp, #12 8015bd4: bdf0 pop {r4, r5, r6, r7, pc} 8015bd6: 466a mov r2, sp 8015bd8: ab01 add r3, sp, #4 8015bda: f7ff ffc9 bl 8015b70 <__swhatbuf_r> 8015bde: 9f00 ldr r7, [sp, #0] 8015be0: 4605 mov r5, r0 8015be2: 4639 mov r1, r7 8015be4: 4630 mov r0, r6 8015be6: f7ff f9fd bl 8014fe4 <_malloc_r> 8015bea: b948 cbnz r0, 8015c00 <__smakebuf_r+0x46> 8015bec: f9b4 300c ldrsh.w r3, [r4, #12] 8015bf0: 059a lsls r2, r3, #22 8015bf2: d4ee bmi.n 8015bd2 <__smakebuf_r+0x18> 8015bf4: f023 0303 bic.w r3, r3, #3 8015bf8: f043 0302 orr.w r3, r3, #2 8015bfc: 81a3 strh r3, [r4, #12] 8015bfe: e7e2 b.n 8015bc6 <__smakebuf_r+0xc> 8015c00: 89a3 ldrh r3, [r4, #12] 8015c02: e9c4 0704 strd r0, r7, [r4, #16] 8015c06: f043 0380 orr.w r3, r3, #128 @ 0x80 8015c0a: 81a3 strh r3, [r4, #12] 8015c0c: 9b01 ldr r3, [sp, #4] 8015c0e: 6020 str r0, [r4, #0] 8015c10: b15b cbz r3, 8015c2a <__smakebuf_r+0x70> 8015c12: 4630 mov r0, r6 8015c14: f9b4 100e ldrsh.w r1, [r4, #14] 8015c18: f000 f826 bl 8015c68 <_isatty_r> 8015c1c: b128 cbz r0, 8015c2a <__smakebuf_r+0x70> 8015c1e: 89a3 ldrh r3, [r4, #12] 8015c20: f023 0303 bic.w r3, r3, #3 8015c24: f043 0301 orr.w r3, r3, #1 8015c28: 81a3 strh r3, [r4, #12] 8015c2a: 89a3 ldrh r3, [r4, #12] 8015c2c: 431d orrs r5, r3 8015c2e: 81a5 strh r5, [r4, #12] 8015c30: e7cf b.n 8015bd2 <__smakebuf_r+0x18> 08015c32 : 8015c32: 4288 cmp r0, r1 8015c34: b510 push {r4, lr} 8015c36: eb01 0402 add.w r4, r1, r2 8015c3a: d902 bls.n 8015c42 8015c3c: 4284 cmp r4, r0 8015c3e: 4623 mov r3, r4 8015c40: d807 bhi.n 8015c52 8015c42: 1e43 subs r3, r0, #1 8015c44: 42a1 cmp r1, r4 8015c46: d008 beq.n 8015c5a 8015c48: f811 2b01 ldrb.w r2, [r1], #1 8015c4c: f803 2f01 strb.w r2, [r3, #1]! 8015c50: e7f8 b.n 8015c44 8015c52: 4601 mov r1, r0 8015c54: 4402 add r2, r0 8015c56: 428a cmp r2, r1 8015c58: d100 bne.n 8015c5c 8015c5a: bd10 pop {r4, pc} 8015c5c: f813 4d01 ldrb.w r4, [r3, #-1]! 8015c60: f802 4d01 strb.w r4, [r2, #-1]! 8015c64: e7f7 b.n 8015c56 ... 08015c68 <_isatty_r>: 8015c68: b538 push {r3, r4, r5, lr} 8015c6a: 2300 movs r3, #0 8015c6c: 4d05 ldr r5, [pc, #20] @ (8015c84 <_isatty_r+0x1c>) 8015c6e: 4604 mov r4, r0 8015c70: 4608 mov r0, r1 8015c72: 602b str r3, [r5, #0] 8015c74: f7f7 fb81 bl 800d37a <_isatty> 8015c78: 1c43 adds r3, r0, #1 8015c7a: d102 bne.n 8015c82 <_isatty_r+0x1a> 8015c7c: 682b ldr r3, [r5, #0] 8015c7e: b103 cbz r3, 8015c82 <_isatty_r+0x1a> 8015c80: 6023 str r3, [r4, #0] 8015c82: bd38 pop {r3, r4, r5, pc} 8015c84: 20001350 .word 0x20001350 08015c88 <_lseek_r>: 8015c88: b538 push {r3, r4, r5, lr} 8015c8a: 4604 mov r4, r0 8015c8c: 4608 mov r0, r1 8015c8e: 4611 mov r1, r2 8015c90: 2200 movs r2, #0 8015c92: 4d05 ldr r5, [pc, #20] @ (8015ca8 <_lseek_r+0x20>) 8015c94: 602a str r2, [r5, #0] 8015c96: 461a mov r2, r3 8015c98: f7f7 fb79 bl 800d38e <_lseek> 8015c9c: 1c43 adds r3, r0, #1 8015c9e: d102 bne.n 8015ca6 <_lseek_r+0x1e> 8015ca0: 682b ldr r3, [r5, #0] 8015ca2: b103 cbz r3, 8015ca6 <_lseek_r+0x1e> 8015ca4: 6023 str r3, [r4, #0] 8015ca6: bd38 pop {r3, r4, r5, pc} 8015ca8: 20001350 .word 0x20001350 08015cac <_read_r>: 8015cac: b538 push {r3, r4, r5, lr} 8015cae: 4604 mov r4, r0 8015cb0: 4608 mov r0, r1 8015cb2: 4611 mov r1, r2 8015cb4: 2200 movs r2, #0 8015cb6: 4d05 ldr r5, [pc, #20] @ (8015ccc <_read_r+0x20>) 8015cb8: 602a str r2, [r5, #0] 8015cba: 461a mov r2, r3 8015cbc: f7f7 fb26 bl 800d30c <_read> 8015cc0: 1c43 adds r3, r0, #1 8015cc2: d102 bne.n 8015cca <_read_r+0x1e> 8015cc4: 682b ldr r3, [r5, #0] 8015cc6: b103 cbz r3, 8015cca <_read_r+0x1e> 8015cc8: 6023 str r3, [r4, #0] 8015cca: bd38 pop {r3, r4, r5, pc} 8015ccc: 20001350 .word 0x20001350 08015cd0 <_sbrk_r>: 8015cd0: b538 push {r3, r4, r5, lr} 8015cd2: 2300 movs r3, #0 8015cd4: 4d05 ldr r5, [pc, #20] @ (8015cec <_sbrk_r+0x1c>) 8015cd6: 4604 mov r4, r0 8015cd8: 4608 mov r0, r1 8015cda: 602b str r3, [r5, #0] 8015cdc: f7f7 fb64 bl 800d3a8 <_sbrk> 8015ce0: 1c43 adds r3, r0, #1 8015ce2: d102 bne.n 8015cea <_sbrk_r+0x1a> 8015ce4: 682b ldr r3, [r5, #0] 8015ce6: b103 cbz r3, 8015cea <_sbrk_r+0x1a> 8015ce8: 6023 str r3, [r4, #0] 8015cea: bd38 pop {r3, r4, r5, pc} 8015cec: 20001350 .word 0x20001350 08015cf0 <_write_r>: 8015cf0: b538 push {r3, r4, r5, lr} 8015cf2: 4604 mov r4, r0 8015cf4: 4608 mov r0, r1 8015cf6: 4611 mov r1, r2 8015cf8: 2200 movs r2, #0 8015cfa: 4d05 ldr r5, [pc, #20] @ (8015d10 <_write_r+0x20>) 8015cfc: 602a str r2, [r5, #0] 8015cfe: 461a mov r2, r3 8015d00: f7f4 fa78 bl 800a1f4 <_write> 8015d04: 1c43 adds r3, r0, #1 8015d06: d102 bne.n 8015d0e <_write_r+0x1e> 8015d08: 682b ldr r3, [r5, #0] 8015d0a: b103 cbz r3, 8015d0e <_write_r+0x1e> 8015d0c: 6023 str r3, [r4, #0] 8015d0e: bd38 pop {r3, r4, r5, pc} 8015d10: 20001350 .word 0x20001350 08015d14 <_close_r>: 8015d14: b538 push {r3, r4, r5, lr} 8015d16: 2300 movs r3, #0 8015d18: 4d05 ldr r5, [pc, #20] @ (8015d30 <_close_r+0x1c>) 8015d1a: 4604 mov r4, r0 8015d1c: 4608 mov r0, r1 8015d1e: 602b str r3, [r5, #0] 8015d20: f7f7 fb11 bl 800d346 <_close> 8015d24: 1c43 adds r3, r0, #1 8015d26: d102 bne.n 8015d2e <_close_r+0x1a> 8015d28: 682b ldr r3, [r5, #0] 8015d2a: b103 cbz r3, 8015d2e <_close_r+0x1a> 8015d2c: 6023 str r3, [r4, #0] 8015d2e: bd38 pop {r3, r4, r5, pc} 8015d30: 20001350 .word 0x20001350 08015d34 <_fstat_r>: 8015d34: b538 push {r3, r4, r5, lr} 8015d36: 2300 movs r3, #0 8015d38: 4d06 ldr r5, [pc, #24] @ (8015d54 <_fstat_r+0x20>) 8015d3a: 4604 mov r4, r0 8015d3c: 4608 mov r0, r1 8015d3e: 4611 mov r1, r2 8015d40: 602b str r3, [r5, #0] 8015d42: f7f7 fb0b bl 800d35c <_fstat> 8015d46: 1c43 adds r3, r0, #1 8015d48: d102 bne.n 8015d50 <_fstat_r+0x1c> 8015d4a: 682b ldr r3, [r5, #0] 8015d4c: b103 cbz r3, 8015d50 <_fstat_r+0x1c> 8015d4e: 6023 str r3, [r4, #0] 8015d50: bd38 pop {r3, r4, r5, pc} 8015d52: bf00 nop 8015d54: 20001350 .word 0x20001350 08015d58 : 8015d58: 2006 movs r0, #6 8015d5a: b508 push {r3, lr} 8015d5c: f000 f8b0 bl 8015ec0 8015d60: 2001 movs r0, #1 8015d62: f7f7 fac8 bl 800d2f6 <_exit> 08015d66 <_calloc_r>: 8015d66: b570 push {r4, r5, r6, lr} 8015d68: fba1 5402 umull r5, r4, r1, r2 8015d6c: b934 cbnz r4, 8015d7c <_calloc_r+0x16> 8015d6e: 4629 mov r1, r5 8015d70: f7ff f938 bl 8014fe4 <_malloc_r> 8015d74: 4606 mov r6, r0 8015d76: b928 cbnz r0, 8015d84 <_calloc_r+0x1e> 8015d78: 4630 mov r0, r6 8015d7a: bd70 pop {r4, r5, r6, pc} 8015d7c: 220c movs r2, #12 8015d7e: 2600 movs r6, #0 8015d80: 6002 str r2, [r0, #0] 8015d82: e7f9 b.n 8015d78 <_calloc_r+0x12> 8015d84: 462a mov r2, r5 8015d86: 4621 mov r1, r4 8015d88: f7fd ff98 bl 8013cbc 8015d8c: e7f4 b.n 8015d78 <_calloc_r+0x12> ... 08015d90 <_free_r>: 8015d90: b538 push {r3, r4, r5, lr} 8015d92: 4605 mov r5, r0 8015d94: 2900 cmp r1, #0 8015d96: d040 beq.n 8015e1a <_free_r+0x8a> 8015d98: f851 3c04 ldr.w r3, [r1, #-4] 8015d9c: 1f0c subs r4, r1, #4 8015d9e: 2b00 cmp r3, #0 8015da0: bfb8 it lt 8015da2: 18e4 addlt r4, r4, r3 8015da4: f7ff fa46 bl 8015234 <__malloc_lock> 8015da8: 4a1c ldr r2, [pc, #112] @ (8015e1c <_free_r+0x8c>) 8015daa: 6813 ldr r3, [r2, #0] 8015dac: b933 cbnz r3, 8015dbc <_free_r+0x2c> 8015dae: 6063 str r3, [r4, #4] 8015db0: 6014 str r4, [r2, #0] 8015db2: 4628 mov r0, r5 8015db4: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8015db8: f7ff ba42 b.w 8015240 <__malloc_unlock> 8015dbc: 42a3 cmp r3, r4 8015dbe: d908 bls.n 8015dd2 <_free_r+0x42> 8015dc0: 6820 ldr r0, [r4, #0] 8015dc2: 1821 adds r1, r4, r0 8015dc4: 428b cmp r3, r1 8015dc6: bf01 itttt eq 8015dc8: 6819 ldreq r1, [r3, #0] 8015dca: 685b ldreq r3, [r3, #4] 8015dcc: 1809 addeq r1, r1, r0 8015dce: 6021 streq r1, [r4, #0] 8015dd0: e7ed b.n 8015dae <_free_r+0x1e> 8015dd2: 461a mov r2, r3 8015dd4: 685b ldr r3, [r3, #4] 8015dd6: b10b cbz r3, 8015ddc <_free_r+0x4c> 8015dd8: 42a3 cmp r3, r4 8015dda: d9fa bls.n 8015dd2 <_free_r+0x42> 8015ddc: 6811 ldr r1, [r2, #0] 8015dde: 1850 adds r0, r2, r1 8015de0: 42a0 cmp r0, r4 8015de2: d10b bne.n 8015dfc <_free_r+0x6c> 8015de4: 6820 ldr r0, [r4, #0] 8015de6: 4401 add r1, r0 8015de8: 1850 adds r0, r2, r1 8015dea: 4283 cmp r3, r0 8015dec: 6011 str r1, [r2, #0] 8015dee: d1e0 bne.n 8015db2 <_free_r+0x22> 8015df0: 6818 ldr r0, [r3, #0] 8015df2: 685b ldr r3, [r3, #4] 8015df4: 4408 add r0, r1 8015df6: 6010 str r0, [r2, #0] 8015df8: 6053 str r3, [r2, #4] 8015dfa: e7da b.n 8015db2 <_free_r+0x22> 8015dfc: d902 bls.n 8015e04 <_free_r+0x74> 8015dfe: 230c movs r3, #12 8015e00: 602b str r3, [r5, #0] 8015e02: e7d6 b.n 8015db2 <_free_r+0x22> 8015e04: 6820 ldr r0, [r4, #0] 8015e06: 1821 adds r1, r4, r0 8015e08: 428b cmp r3, r1 8015e0a: bf01 itttt eq 8015e0c: 6819 ldreq r1, [r3, #0] 8015e0e: 685b ldreq r3, [r3, #4] 8015e10: 1809 addeq r1, r1, r0 8015e12: 6021 streq r1, [r4, #0] 8015e14: 6063 str r3, [r4, #4] 8015e16: 6054 str r4, [r2, #4] 8015e18: e7cb b.n 8015db2 <_free_r+0x22> 8015e1a: bd38 pop {r3, r4, r5, pc} 8015e1c: 2000134c .word 0x2000134c 08015e20 <__ascii_mbtowc>: 8015e20: b082 sub sp, #8 8015e22: b901 cbnz r1, 8015e26 <__ascii_mbtowc+0x6> 8015e24: a901 add r1, sp, #4 8015e26: b142 cbz r2, 8015e3a <__ascii_mbtowc+0x1a> 8015e28: b14b cbz r3, 8015e3e <__ascii_mbtowc+0x1e> 8015e2a: 7813 ldrb r3, [r2, #0] 8015e2c: 600b str r3, [r1, #0] 8015e2e: 7812 ldrb r2, [r2, #0] 8015e30: 1e10 subs r0, r2, #0 8015e32: bf18 it ne 8015e34: 2001 movne r0, #1 8015e36: b002 add sp, #8 8015e38: 4770 bx lr 8015e3a: 4610 mov r0, r2 8015e3c: e7fb b.n 8015e36 <__ascii_mbtowc+0x16> 8015e3e: f06f 0001 mvn.w r0, #1 8015e42: e7f8 b.n 8015e36 <__ascii_mbtowc+0x16> 08015e44 <_malloc_usable_size_r>: 8015e44: f851 3c04 ldr.w r3, [r1, #-4] 8015e48: 1f18 subs r0, r3, #4 8015e4a: 2b00 cmp r3, #0 8015e4c: bfbc itt lt 8015e4e: 580b ldrlt r3, [r1, r0] 8015e50: 18c0 addlt r0, r0, r3 8015e52: 4770 bx lr 08015e54 <__ascii_wctomb>: 8015e54: 4603 mov r3, r0 8015e56: 4608 mov r0, r1 8015e58: b141 cbz r1, 8015e6c <__ascii_wctomb+0x18> 8015e5a: 2aff cmp r2, #255 @ 0xff 8015e5c: d904 bls.n 8015e68 <__ascii_wctomb+0x14> 8015e5e: 228a movs r2, #138 @ 0x8a 8015e60: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015e64: 601a str r2, [r3, #0] 8015e66: 4770 bx lr 8015e68: 2001 movs r0, #1 8015e6a: 700a strb r2, [r1, #0] 8015e6c: 4770 bx lr 08015e6e <_raise_r>: 8015e6e: 291f cmp r1, #31 8015e70: b538 push {r3, r4, r5, lr} 8015e72: 4605 mov r5, r0 8015e74: 460c mov r4, r1 8015e76: d904 bls.n 8015e82 <_raise_r+0x14> 8015e78: 2316 movs r3, #22 8015e7a: 6003 str r3, [r0, #0] 8015e7c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015e80: bd38 pop {r3, r4, r5, pc} 8015e82: 6bc2 ldr r2, [r0, #60] @ 0x3c 8015e84: b112 cbz r2, 8015e8c <_raise_r+0x1e> 8015e86: f852 3021 ldr.w r3, [r2, r1, lsl #2] 8015e8a: b94b cbnz r3, 8015ea0 <_raise_r+0x32> 8015e8c: 4628 mov r0, r5 8015e8e: f000 f831 bl 8015ef4 <_getpid_r> 8015e92: 4622 mov r2, r4 8015e94: 4601 mov r1, r0 8015e96: 4628 mov r0, r5 8015e98: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8015e9c: f000 b818 b.w 8015ed0 <_kill_r> 8015ea0: 2b01 cmp r3, #1 8015ea2: d00a beq.n 8015eba <_raise_r+0x4c> 8015ea4: 1c59 adds r1, r3, #1 8015ea6: d103 bne.n 8015eb0 <_raise_r+0x42> 8015ea8: 2316 movs r3, #22 8015eaa: 6003 str r3, [r0, #0] 8015eac: 2001 movs r0, #1 8015eae: e7e7 b.n 8015e80 <_raise_r+0x12> 8015eb0: 2100 movs r1, #0 8015eb2: 4620 mov r0, r4 8015eb4: f842 1024 str.w r1, [r2, r4, lsl #2] 8015eb8: 4798 blx r3 8015eba: 2000 movs r0, #0 8015ebc: e7e0 b.n 8015e80 <_raise_r+0x12> ... 08015ec0 : 8015ec0: 4b02 ldr r3, [pc, #8] @ (8015ecc ) 8015ec2: 4601 mov r1, r0 8015ec4: 6818 ldr r0, [r3, #0] 8015ec6: f7ff bfd2 b.w 8015e6e <_raise_r> 8015eca: bf00 nop 8015ecc: 20000098 .word 0x20000098 08015ed0 <_kill_r>: 8015ed0: b538 push {r3, r4, r5, lr} 8015ed2: 2300 movs r3, #0 8015ed4: 4d06 ldr r5, [pc, #24] @ (8015ef0 <_kill_r+0x20>) 8015ed6: 4604 mov r4, r0 8015ed8: 4608 mov r0, r1 8015eda: 4611 mov r1, r2 8015edc: 602b str r3, [r5, #0] 8015ede: f7f7 f9fa bl 800d2d6 <_kill> 8015ee2: 1c43 adds r3, r0, #1 8015ee4: d102 bne.n 8015eec <_kill_r+0x1c> 8015ee6: 682b ldr r3, [r5, #0] 8015ee8: b103 cbz r3, 8015eec <_kill_r+0x1c> 8015eea: 6023 str r3, [r4, #0] 8015eec: bd38 pop {r3, r4, r5, pc} 8015eee: bf00 nop 8015ef0: 20001350 .word 0x20001350 08015ef4 <_getpid_r>: 8015ef4: f7f7 b9e8 b.w 800d2c8 <_getpid> 08015ef8 <_init>: 8015ef8: b5f8 push {r3, r4, r5, r6, r7, lr} 8015efa: bf00 nop 8015efc: bcf8 pop {r3, r4, r5, r6, r7} 8015efe: bc08 pop {r3} 8015f00: 469e mov lr, r3 8015f02: 4770 bx lr 08015f04 <_fini>: 8015f04: b5f8 push {r3, r4, r5, r6, r7, lr} 8015f06: bf00 nop 8015f08: bcf8 pop {r3, r4, r5, r6, r7} 8015f0a: bc08 pop {r3} 8015f0c: 469e mov lr, r3 8015f0e: 4770 bx lr