CCSModuleSW30Web.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001e8 08008000 08008000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000ed6c 080081e8 080081e8 000011e8 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000de4 08016f58 08016f58 0000ff58 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08017d3c 08017d3c 00011258 2**0 CONTENTS 4 .ARM 00000008 08017d3c 08017d3c 00010d3c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 08017d44 08017d44 00011258 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08017d44 08017d44 00010d44 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08017d48 08017d48 00010d48 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000258 20000000 08017d4c 00011000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00001380 20000258 08017fa4 00011258 2**3 ALLOC 10 ._user_heap_stack 00000600 200015d8 08017fa4 000115d8 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 00011258 2**0 CONTENTS, READONLY 12 .debug_info 0001d76a 00000000 00000000 00011281 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 000057ef 00000000 00000000 0002e9eb 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_loclists 00000f96 00000000 00000000 000341da 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_aranges 00001770 00000000 00000000 00035170 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_rnglists 00001245 00000000 00000000 000368e0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_macro 00026728 00000000 00000000 00037b25 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_line 000206f5 00000000 00000000 0005e24d 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_str 000c9ab5 00000000 00000000 0007e942 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .comment 00000043 00000000 00000000 001483f7 2**0 CONTENTS, READONLY 21 .debug_frame 00006e4c 00000000 00000000 0014843c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 22 .debug_line_str 0000006e 00000000 00000000 0014f288 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080081e8 <__do_global_dtors_aux>: 80081e8: b510 push {r4, lr} 80081ea: 4c05 ldr r4, [pc, #20] @ (8008200 <__do_global_dtors_aux+0x18>) 80081ec: 7823 ldrb r3, [r4, #0] 80081ee: b933 cbnz r3, 80081fe <__do_global_dtors_aux+0x16> 80081f0: 4b04 ldr r3, [pc, #16] @ (8008204 <__do_global_dtors_aux+0x1c>) 80081f2: b113 cbz r3, 80081fa <__do_global_dtors_aux+0x12> 80081f4: 4804 ldr r0, [pc, #16] @ (8008208 <__do_global_dtors_aux+0x20>) 80081f6: f3af 8000 nop.w 80081fa: 2301 movs r3, #1 80081fc: 7023 strb r3, [r4, #0] 80081fe: bd10 pop {r4, pc} 8008200: 20000258 .word 0x20000258 8008204: 00000000 .word 0x00000000 8008208: 08016f3c .word 0x08016f3c 0800820c : 800820c: b508 push {r3, lr} 800820e: 4b03 ldr r3, [pc, #12] @ (800821c ) 8008210: b11b cbz r3, 800821a 8008212: 4903 ldr r1, [pc, #12] @ (8008220 ) 8008214: 4803 ldr r0, [pc, #12] @ (8008224 ) 8008216: f3af 8000 nop.w 800821a: bd08 pop {r3, pc} 800821c: 00000000 .word 0x00000000 8008220: 2000025c .word 0x2000025c 8008224: 08016f3c .word 0x08016f3c 08008228 : 8008228: 4603 mov r3, r0 800822a: f813 2b01 ldrb.w r2, [r3], #1 800822e: 2a00 cmp r2, #0 8008230: d1fb bne.n 800822a 8008232: 1a18 subs r0, r3, r0 8008234: 3801 subs r0, #1 8008236: 4770 bx lr 08008238 <__aeabi_drsub>: 8008238: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 800823c: e002 b.n 8008244 <__adddf3> 800823e: bf00 nop 08008240 <__aeabi_dsub>: 8008240: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 08008244 <__adddf3>: 8008244: b530 push {r4, r5, lr} 8008246: ea4f 0441 mov.w r4, r1, lsl #1 800824a: ea4f 0543 mov.w r5, r3, lsl #1 800824e: ea94 0f05 teq r4, r5 8008252: bf08 it eq 8008254: ea90 0f02 teqeq r0, r2 8008258: bf1f itttt ne 800825a: ea54 0c00 orrsne.w ip, r4, r0 800825e: ea55 0c02 orrsne.w ip, r5, r2 8008262: ea7f 5c64 mvnsne.w ip, r4, asr #21 8008266: ea7f 5c65 mvnsne.w ip, r5, asr #21 800826a: f000 80e2 beq.w 8008432 <__adddf3+0x1ee> 800826e: ea4f 5454 mov.w r4, r4, lsr #21 8008272: ebd4 5555 rsbs r5, r4, r5, lsr #21 8008276: bfb8 it lt 8008278: 426d neglt r5, r5 800827a: dd0c ble.n 8008296 <__adddf3+0x52> 800827c: 442c add r4, r5 800827e: ea80 0202 eor.w r2, r0, r2 8008282: ea81 0303 eor.w r3, r1, r3 8008286: ea82 0000 eor.w r0, r2, r0 800828a: ea83 0101 eor.w r1, r3, r1 800828e: ea80 0202 eor.w r2, r0, r2 8008292: ea81 0303 eor.w r3, r1, r3 8008296: 2d36 cmp r5, #54 @ 0x36 8008298: bf88 it hi 800829a: bd30 pophi {r4, r5, pc} 800829c: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 80082a0: ea4f 3101 mov.w r1, r1, lsl #12 80082a4: f44f 1c80 mov.w ip, #1048576 @ 0x100000 80082a8: ea4c 3111 orr.w r1, ip, r1, lsr #12 80082ac: d002 beq.n 80082b4 <__adddf3+0x70> 80082ae: 4240 negs r0, r0 80082b0: eb61 0141 sbc.w r1, r1, r1, lsl #1 80082b4: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 80082b8: ea4f 3303 mov.w r3, r3, lsl #12 80082bc: ea4c 3313 orr.w r3, ip, r3, lsr #12 80082c0: d002 beq.n 80082c8 <__adddf3+0x84> 80082c2: 4252 negs r2, r2 80082c4: eb63 0343 sbc.w r3, r3, r3, lsl #1 80082c8: ea94 0f05 teq r4, r5 80082cc: f000 80a7 beq.w 800841e <__adddf3+0x1da> 80082d0: f1a4 0401 sub.w r4, r4, #1 80082d4: f1d5 0e20 rsbs lr, r5, #32 80082d8: db0d blt.n 80082f6 <__adddf3+0xb2> 80082da: fa02 fc0e lsl.w ip, r2, lr 80082de: fa22 f205 lsr.w r2, r2, r5 80082e2: 1880 adds r0, r0, r2 80082e4: f141 0100 adc.w r1, r1, #0 80082e8: fa03 f20e lsl.w r2, r3, lr 80082ec: 1880 adds r0, r0, r2 80082ee: fa43 f305 asr.w r3, r3, r5 80082f2: 4159 adcs r1, r3 80082f4: e00e b.n 8008314 <__adddf3+0xd0> 80082f6: f1a5 0520 sub.w r5, r5, #32 80082fa: f10e 0e20 add.w lr, lr, #32 80082fe: 2a01 cmp r2, #1 8008300: fa03 fc0e lsl.w ip, r3, lr 8008304: bf28 it cs 8008306: f04c 0c02 orrcs.w ip, ip, #2 800830a: fa43 f305 asr.w r3, r3, r5 800830e: 18c0 adds r0, r0, r3 8008310: eb51 71e3 adcs.w r1, r1, r3, asr #31 8008314: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008318: d507 bpl.n 800832a <__adddf3+0xe6> 800831a: f04f 0e00 mov.w lr, #0 800831e: f1dc 0c00 rsbs ip, ip, #0 8008322: eb7e 0000 sbcs.w r0, lr, r0 8008326: eb6e 0101 sbc.w r1, lr, r1 800832a: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 800832e: d31b bcc.n 8008368 <__adddf3+0x124> 8008330: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 8008334: d30c bcc.n 8008350 <__adddf3+0x10c> 8008336: 0849 lsrs r1, r1, #1 8008338: ea5f 0030 movs.w r0, r0, rrx 800833c: ea4f 0c3c mov.w ip, ip, rrx 8008340: f104 0401 add.w r4, r4, #1 8008344: ea4f 5244 mov.w r2, r4, lsl #21 8008348: f512 0f80 cmn.w r2, #4194304 @ 0x400000 800834c: f080 809a bcs.w 8008484 <__adddf3+0x240> 8008350: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008354: bf08 it eq 8008356: ea5f 0c50 movseq.w ip, r0, lsr #1 800835a: f150 0000 adcs.w r0, r0, #0 800835e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008362: ea41 0105 orr.w r1, r1, r5 8008366: bd30 pop {r4, r5, pc} 8008368: ea5f 0c4c movs.w ip, ip, lsl #1 800836c: 4140 adcs r0, r0 800836e: eb41 0101 adc.w r1, r1, r1 8008372: 3c01 subs r4, #1 8008374: bf28 it cs 8008376: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 800837a: d2e9 bcs.n 8008350 <__adddf3+0x10c> 800837c: f091 0f00 teq r1, #0 8008380: bf04 itt eq 8008382: 4601 moveq r1, r0 8008384: 2000 moveq r0, #0 8008386: fab1 f381 clz r3, r1 800838a: bf08 it eq 800838c: 3320 addeq r3, #32 800838e: f1a3 030b sub.w r3, r3, #11 8008392: f1b3 0220 subs.w r2, r3, #32 8008396: da0c bge.n 80083b2 <__adddf3+0x16e> 8008398: 320c adds r2, #12 800839a: dd08 ble.n 80083ae <__adddf3+0x16a> 800839c: f102 0c14 add.w ip, r2, #20 80083a0: f1c2 020c rsb r2, r2, #12 80083a4: fa01 f00c lsl.w r0, r1, ip 80083a8: fa21 f102 lsr.w r1, r1, r2 80083ac: e00c b.n 80083c8 <__adddf3+0x184> 80083ae: f102 0214 add.w r2, r2, #20 80083b2: bfd8 it le 80083b4: f1c2 0c20 rsble ip, r2, #32 80083b8: fa01 f102 lsl.w r1, r1, r2 80083bc: fa20 fc0c lsr.w ip, r0, ip 80083c0: bfdc itt le 80083c2: ea41 010c orrle.w r1, r1, ip 80083c6: 4090 lslle r0, r2 80083c8: 1ae4 subs r4, r4, r3 80083ca: bfa2 ittt ge 80083cc: eb01 5104 addge.w r1, r1, r4, lsl #20 80083d0: 4329 orrge r1, r5 80083d2: bd30 popge {r4, r5, pc} 80083d4: ea6f 0404 mvn.w r4, r4 80083d8: 3c1f subs r4, #31 80083da: da1c bge.n 8008416 <__adddf3+0x1d2> 80083dc: 340c adds r4, #12 80083de: dc0e bgt.n 80083fe <__adddf3+0x1ba> 80083e0: f104 0414 add.w r4, r4, #20 80083e4: f1c4 0220 rsb r2, r4, #32 80083e8: fa20 f004 lsr.w r0, r0, r4 80083ec: fa01 f302 lsl.w r3, r1, r2 80083f0: ea40 0003 orr.w r0, r0, r3 80083f4: fa21 f304 lsr.w r3, r1, r4 80083f8: ea45 0103 orr.w r1, r5, r3 80083fc: bd30 pop {r4, r5, pc} 80083fe: f1c4 040c rsb r4, r4, #12 8008402: f1c4 0220 rsb r2, r4, #32 8008406: fa20 f002 lsr.w r0, r0, r2 800840a: fa01 f304 lsl.w r3, r1, r4 800840e: ea40 0003 orr.w r0, r0, r3 8008412: 4629 mov r1, r5 8008414: bd30 pop {r4, r5, pc} 8008416: fa21 f004 lsr.w r0, r1, r4 800841a: 4629 mov r1, r5 800841c: bd30 pop {r4, r5, pc} 800841e: f094 0f00 teq r4, #0 8008422: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 8008426: bf06 itte eq 8008428: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 800842c: 3401 addeq r4, #1 800842e: 3d01 subne r5, #1 8008430: e74e b.n 80082d0 <__adddf3+0x8c> 8008432: ea7f 5c64 mvns.w ip, r4, asr #21 8008436: bf18 it ne 8008438: ea7f 5c65 mvnsne.w ip, r5, asr #21 800843c: d029 beq.n 8008492 <__adddf3+0x24e> 800843e: ea94 0f05 teq r4, r5 8008442: bf08 it eq 8008444: ea90 0f02 teqeq r0, r2 8008448: d005 beq.n 8008456 <__adddf3+0x212> 800844a: ea54 0c00 orrs.w ip, r4, r0 800844e: bf04 itt eq 8008450: 4619 moveq r1, r3 8008452: 4610 moveq r0, r2 8008454: bd30 pop {r4, r5, pc} 8008456: ea91 0f03 teq r1, r3 800845a: bf1e ittt ne 800845c: 2100 movne r1, #0 800845e: 2000 movne r0, #0 8008460: bd30 popne {r4, r5, pc} 8008462: ea5f 5c54 movs.w ip, r4, lsr #21 8008466: d105 bne.n 8008474 <__adddf3+0x230> 8008468: 0040 lsls r0, r0, #1 800846a: 4149 adcs r1, r1 800846c: bf28 it cs 800846e: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 8008472: bd30 pop {r4, r5, pc} 8008474: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 8008478: bf3c itt cc 800847a: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 800847e: bd30 popcc {r4, r5, pc} 8008480: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8008484: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 8008488: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 800848c: f04f 0000 mov.w r0, #0 8008490: bd30 pop {r4, r5, pc} 8008492: ea7f 5c64 mvns.w ip, r4, asr #21 8008496: bf1a itte ne 8008498: 4619 movne r1, r3 800849a: 4610 movne r0, r2 800849c: ea7f 5c65 mvnseq.w ip, r5, asr #21 80084a0: bf1c itt ne 80084a2: 460b movne r3, r1 80084a4: 4602 movne r2, r0 80084a6: ea50 3401 orrs.w r4, r0, r1, lsl #12 80084aa: bf06 itte eq 80084ac: ea52 3503 orrseq.w r5, r2, r3, lsl #12 80084b0: ea91 0f03 teqeq r1, r3 80084b4: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 80084b8: bd30 pop {r4, r5, pc} 80084ba: bf00 nop 080084bc <__aeabi_ui2d>: 80084bc: f090 0f00 teq r0, #0 80084c0: bf04 itt eq 80084c2: 2100 moveq r1, #0 80084c4: 4770 bxeq lr 80084c6: b530 push {r4, r5, lr} 80084c8: f44f 6480 mov.w r4, #1024 @ 0x400 80084cc: f104 0432 add.w r4, r4, #50 @ 0x32 80084d0: f04f 0500 mov.w r5, #0 80084d4: f04f 0100 mov.w r1, #0 80084d8: e750 b.n 800837c <__adddf3+0x138> 80084da: bf00 nop 080084dc <__aeabi_i2d>: 80084dc: f090 0f00 teq r0, #0 80084e0: bf04 itt eq 80084e2: 2100 moveq r1, #0 80084e4: 4770 bxeq lr 80084e6: b530 push {r4, r5, lr} 80084e8: f44f 6480 mov.w r4, #1024 @ 0x400 80084ec: f104 0432 add.w r4, r4, #50 @ 0x32 80084f0: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 80084f4: bf48 it mi 80084f6: 4240 negmi r0, r0 80084f8: f04f 0100 mov.w r1, #0 80084fc: e73e b.n 800837c <__adddf3+0x138> 80084fe: bf00 nop 08008500 <__aeabi_f2d>: 8008500: 0042 lsls r2, r0, #1 8008502: ea4f 01e2 mov.w r1, r2, asr #3 8008506: ea4f 0131 mov.w r1, r1, rrx 800850a: ea4f 7002 mov.w r0, r2, lsl #28 800850e: bf1f itttt ne 8008510: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 8008514: f093 4f7f teqne r3, #4278190080 @ 0xff000000 8008518: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 800851c: 4770 bxne lr 800851e: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 8008522: bf08 it eq 8008524: 4770 bxeq lr 8008526: f093 4f7f teq r3, #4278190080 @ 0xff000000 800852a: bf04 itt eq 800852c: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 8008530: 4770 bxeq lr 8008532: b530 push {r4, r5, lr} 8008534: f44f 7460 mov.w r4, #896 @ 0x380 8008538: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 800853c: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 8008540: e71c b.n 800837c <__adddf3+0x138> 8008542: bf00 nop 08008544 <__aeabi_ul2d>: 8008544: ea50 0201 orrs.w r2, r0, r1 8008548: bf08 it eq 800854a: 4770 bxeq lr 800854c: b530 push {r4, r5, lr} 800854e: f04f 0500 mov.w r5, #0 8008552: e00a b.n 800856a <__aeabi_l2d+0x16> 08008554 <__aeabi_l2d>: 8008554: ea50 0201 orrs.w r2, r0, r1 8008558: bf08 it eq 800855a: 4770 bxeq lr 800855c: b530 push {r4, r5, lr} 800855e: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 8008562: d502 bpl.n 800856a <__aeabi_l2d+0x16> 8008564: 4240 negs r0, r0 8008566: eb61 0141 sbc.w r1, r1, r1, lsl #1 800856a: f44f 6480 mov.w r4, #1024 @ 0x400 800856e: f104 0432 add.w r4, r4, #50 @ 0x32 8008572: ea5f 5c91 movs.w ip, r1, lsr #22 8008576: f43f aed8 beq.w 800832a <__adddf3+0xe6> 800857a: f04f 0203 mov.w r2, #3 800857e: ea5f 0cdc movs.w ip, ip, lsr #3 8008582: bf18 it ne 8008584: 3203 addne r2, #3 8008586: ea5f 0cdc movs.w ip, ip, lsr #3 800858a: bf18 it ne 800858c: 3203 addne r2, #3 800858e: eb02 02dc add.w r2, r2, ip, lsr #3 8008592: f1c2 0320 rsb r3, r2, #32 8008596: fa00 fc03 lsl.w ip, r0, r3 800859a: fa20 f002 lsr.w r0, r0, r2 800859e: fa01 fe03 lsl.w lr, r1, r3 80085a2: ea40 000e orr.w r0, r0, lr 80085a6: fa21 f102 lsr.w r1, r1, r2 80085aa: 4414 add r4, r2 80085ac: e6bd b.n 800832a <__adddf3+0xe6> 80085ae: bf00 nop 080085b0 <__aeabi_dmul>: 80085b0: b570 push {r4, r5, r6, lr} 80085b2: f04f 0cff mov.w ip, #255 @ 0xff 80085b6: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 80085ba: ea1c 5411 ands.w r4, ip, r1, lsr #20 80085be: bf1d ittte ne 80085c0: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80085c4: ea94 0f0c teqne r4, ip 80085c8: ea95 0f0c teqne r5, ip 80085cc: f000 f8de bleq 800878c <__aeabi_dmul+0x1dc> 80085d0: 442c add r4, r5 80085d2: ea81 0603 eor.w r6, r1, r3 80085d6: ea21 514c bic.w r1, r1, ip, lsl #21 80085da: ea23 534c bic.w r3, r3, ip, lsl #21 80085de: ea50 3501 orrs.w r5, r0, r1, lsl #12 80085e2: bf18 it ne 80085e4: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80085e8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 80085ec: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80085f0: d038 beq.n 8008664 <__aeabi_dmul+0xb4> 80085f2: fba0 ce02 umull ip, lr, r0, r2 80085f6: f04f 0500 mov.w r5, #0 80085fa: fbe1 e502 umlal lr, r5, r1, r2 80085fe: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000 8008602: fbe0 e503 umlal lr, r5, r0, r3 8008606: f04f 0600 mov.w r6, #0 800860a: fbe1 5603 umlal r5, r6, r1, r3 800860e: f09c 0f00 teq ip, #0 8008612: bf18 it ne 8008614: f04e 0e01 orrne.w lr, lr, #1 8008618: f1a4 04ff sub.w r4, r4, #255 @ 0xff 800861c: f5b6 7f00 cmp.w r6, #512 @ 0x200 8008620: f564 7440 sbc.w r4, r4, #768 @ 0x300 8008624: d204 bcs.n 8008630 <__aeabi_dmul+0x80> 8008626: ea5f 0e4e movs.w lr, lr, lsl #1 800862a: 416d adcs r5, r5 800862c: eb46 0606 adc.w r6, r6, r6 8008630: ea42 21c6 orr.w r1, r2, r6, lsl #11 8008634: ea41 5155 orr.w r1, r1, r5, lsr #21 8008638: ea4f 20c5 mov.w r0, r5, lsl #11 800863c: ea40 505e orr.w r0, r0, lr, lsr #21 8008640: ea4f 2ece mov.w lr, lr, lsl #11 8008644: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008648: bf88 it hi 800864a: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800864e: d81e bhi.n 800868e <__aeabi_dmul+0xde> 8008650: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000 8008654: bf08 it eq 8008656: ea5f 0e50 movseq.w lr, r0, lsr #1 800865a: f150 0000 adcs.w r0, r0, #0 800865e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008662: bd70 pop {r4, r5, r6, pc} 8008664: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000 8008668: ea46 0101 orr.w r1, r6, r1 800866c: ea40 0002 orr.w r0, r0, r2 8008670: ea81 0103 eor.w r1, r1, r3 8008674: ebb4 045c subs.w r4, r4, ip, lsr #1 8008678: bfc2 ittt gt 800867a: ebd4 050c rsbsgt r5, r4, ip 800867e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8008682: bd70 popgt {r4, r5, r6, pc} 8008684: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008688: f04f 0e00 mov.w lr, #0 800868c: 3c01 subs r4, #1 800868e: f300 80ab bgt.w 80087e8 <__aeabi_dmul+0x238> 8008692: f114 0f36 cmn.w r4, #54 @ 0x36 8008696: bfde ittt le 8008698: 2000 movle r0, #0 800869a: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000 800869e: bd70 pople {r4, r5, r6, pc} 80086a0: f1c4 0400 rsb r4, r4, #0 80086a4: 3c20 subs r4, #32 80086a6: da35 bge.n 8008714 <__aeabi_dmul+0x164> 80086a8: 340c adds r4, #12 80086aa: dc1b bgt.n 80086e4 <__aeabi_dmul+0x134> 80086ac: f104 0414 add.w r4, r4, #20 80086b0: f1c4 0520 rsb r5, r4, #32 80086b4: fa00 f305 lsl.w r3, r0, r5 80086b8: fa20 f004 lsr.w r0, r0, r4 80086bc: fa01 f205 lsl.w r2, r1, r5 80086c0: ea40 0002 orr.w r0, r0, r2 80086c4: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000 80086c8: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 80086cc: eb10 70d3 adds.w r0, r0, r3, lsr #31 80086d0: fa21 f604 lsr.w r6, r1, r4 80086d4: eb42 0106 adc.w r1, r2, r6 80086d8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80086dc: bf08 it eq 80086de: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80086e2: bd70 pop {r4, r5, r6, pc} 80086e4: f1c4 040c rsb r4, r4, #12 80086e8: f1c4 0520 rsb r5, r4, #32 80086ec: fa00 f304 lsl.w r3, r0, r4 80086f0: fa20 f005 lsr.w r0, r0, r5 80086f4: fa01 f204 lsl.w r2, r1, r4 80086f8: ea40 0002 orr.w r0, r0, r2 80086fc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8008700: eb10 70d3 adds.w r0, r0, r3, lsr #31 8008704: f141 0100 adc.w r1, r1, #0 8008708: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 800870c: bf08 it eq 800870e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8008712: bd70 pop {r4, r5, r6, pc} 8008714: f1c4 0520 rsb r5, r4, #32 8008718: fa00 f205 lsl.w r2, r0, r5 800871c: ea4e 0e02 orr.w lr, lr, r2 8008720: fa20 f304 lsr.w r3, r0, r4 8008724: fa01 f205 lsl.w r2, r1, r5 8008728: ea43 0302 orr.w r3, r3, r2 800872c: fa21 f004 lsr.w r0, r1, r4 8008730: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8008734: fa21 f204 lsr.w r2, r1, r4 8008738: ea20 0002 bic.w r0, r0, r2 800873c: eb00 70d3 add.w r0, r0, r3, lsr #31 8008740: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8008744: bf08 it eq 8008746: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800874a: bd70 pop {r4, r5, r6, pc} 800874c: f094 0f00 teq r4, #0 8008750: d10f bne.n 8008772 <__aeabi_dmul+0x1c2> 8008752: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000 8008756: 0040 lsls r0, r0, #1 8008758: eb41 0101 adc.w r1, r1, r1 800875c: f411 1f80 tst.w r1, #1048576 @ 0x100000 8008760: bf08 it eq 8008762: 3c01 subeq r4, #1 8008764: d0f7 beq.n 8008756 <__aeabi_dmul+0x1a6> 8008766: ea41 0106 orr.w r1, r1, r6 800876a: f095 0f00 teq r5, #0 800876e: bf18 it ne 8008770: 4770 bxne lr 8008772: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000 8008776: 0052 lsls r2, r2, #1 8008778: eb43 0303 adc.w r3, r3, r3 800877c: f413 1f80 tst.w r3, #1048576 @ 0x100000 8008780: bf08 it eq 8008782: 3d01 subeq r5, #1 8008784: d0f7 beq.n 8008776 <__aeabi_dmul+0x1c6> 8008786: ea43 0306 orr.w r3, r3, r6 800878a: 4770 bx lr 800878c: ea94 0f0c teq r4, ip 8008790: ea0c 5513 and.w r5, ip, r3, lsr #20 8008794: bf18 it ne 8008796: ea95 0f0c teqne r5, ip 800879a: d00c beq.n 80087b6 <__aeabi_dmul+0x206> 800879c: ea50 0641 orrs.w r6, r0, r1, lsl #1 80087a0: bf18 it ne 80087a2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80087a6: d1d1 bne.n 800874c <__aeabi_dmul+0x19c> 80087a8: ea81 0103 eor.w r1, r1, r3 80087ac: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087b0: f04f 0000 mov.w r0, #0 80087b4: bd70 pop {r4, r5, r6, pc} 80087b6: ea50 0641 orrs.w r6, r0, r1, lsl #1 80087ba: bf06 itte eq 80087bc: 4610 moveq r0, r2 80087be: 4619 moveq r1, r3 80087c0: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80087c4: d019 beq.n 80087fa <__aeabi_dmul+0x24a> 80087c6: ea94 0f0c teq r4, ip 80087ca: d102 bne.n 80087d2 <__aeabi_dmul+0x222> 80087cc: ea50 3601 orrs.w r6, r0, r1, lsl #12 80087d0: d113 bne.n 80087fa <__aeabi_dmul+0x24a> 80087d2: ea95 0f0c teq r5, ip 80087d6: d105 bne.n 80087e4 <__aeabi_dmul+0x234> 80087d8: ea52 3603 orrs.w r6, r2, r3, lsl #12 80087dc: bf1c itt ne 80087de: 4610 movne r0, r2 80087e0: 4619 movne r1, r3 80087e2: d10a bne.n 80087fa <__aeabi_dmul+0x24a> 80087e4: ea81 0103 eor.w r1, r1, r3 80087e8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80087ec: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087f0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 80087f4: f04f 0000 mov.w r0, #0 80087f8: bd70 pop {r4, r5, r6, pc} 80087fa: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80087fe: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000 8008802: bd70 pop {r4, r5, r6, pc} 08008804 <__aeabi_ddiv>: 8008804: b570 push {r4, r5, r6, lr} 8008806: f04f 0cff mov.w ip, #255 @ 0xff 800880a: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 800880e: ea1c 5411 ands.w r4, ip, r1, lsr #20 8008812: bf1d ittte ne 8008814: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8008818: ea94 0f0c teqne r4, ip 800881c: ea95 0f0c teqne r5, ip 8008820: f000 f8a7 bleq 8008972 <__aeabi_ddiv+0x16e> 8008824: eba4 0405 sub.w r4, r4, r5 8008828: ea81 0e03 eor.w lr, r1, r3 800882c: ea52 3503 orrs.w r5, r2, r3, lsl #12 8008830: ea4f 3101 mov.w r1, r1, lsl #12 8008834: f000 8088 beq.w 8008948 <__aeabi_ddiv+0x144> 8008838: ea4f 3303 mov.w r3, r3, lsl #12 800883c: f04f 5580 mov.w r5, #268435456 @ 0x10000000 8008840: ea45 1313 orr.w r3, r5, r3, lsr #4 8008844: ea43 6312 orr.w r3, r3, r2, lsr #24 8008848: ea4f 2202 mov.w r2, r2, lsl #8 800884c: ea45 1511 orr.w r5, r5, r1, lsr #4 8008850: ea45 6510 orr.w r5, r5, r0, lsr #24 8008854: ea4f 2600 mov.w r6, r0, lsl #8 8008858: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000 800885c: 429d cmp r5, r3 800885e: bf08 it eq 8008860: 4296 cmpeq r6, r2 8008862: f144 04fd adc.w r4, r4, #253 @ 0xfd 8008866: f504 7440 add.w r4, r4, #768 @ 0x300 800886a: d202 bcs.n 8008872 <__aeabi_ddiv+0x6e> 800886c: 085b lsrs r3, r3, #1 800886e: ea4f 0232 mov.w r2, r2, rrx 8008872: 1ab6 subs r6, r6, r2 8008874: eb65 0503 sbc.w r5, r5, r3 8008878: 085b lsrs r3, r3, #1 800887a: ea4f 0232 mov.w r2, r2, rrx 800887e: f44f 1080 mov.w r0, #1048576 @ 0x100000 8008882: f44f 2c00 mov.w ip, #524288 @ 0x80000 8008886: ebb6 0e02 subs.w lr, r6, r2 800888a: eb75 0e03 sbcs.w lr, r5, r3 800888e: bf22 ittt cs 8008890: 1ab6 subcs r6, r6, r2 8008892: 4675 movcs r5, lr 8008894: ea40 000c orrcs.w r0, r0, ip 8008898: 085b lsrs r3, r3, #1 800889a: ea4f 0232 mov.w r2, r2, rrx 800889e: ebb6 0e02 subs.w lr, r6, r2 80088a2: eb75 0e03 sbcs.w lr, r5, r3 80088a6: bf22 ittt cs 80088a8: 1ab6 subcs r6, r6, r2 80088aa: 4675 movcs r5, lr 80088ac: ea40 005c orrcs.w r0, r0, ip, lsr #1 80088b0: 085b lsrs r3, r3, #1 80088b2: ea4f 0232 mov.w r2, r2, rrx 80088b6: ebb6 0e02 subs.w lr, r6, r2 80088ba: eb75 0e03 sbcs.w lr, r5, r3 80088be: bf22 ittt cs 80088c0: 1ab6 subcs r6, r6, r2 80088c2: 4675 movcs r5, lr 80088c4: ea40 009c orrcs.w r0, r0, ip, lsr #2 80088c8: 085b lsrs r3, r3, #1 80088ca: ea4f 0232 mov.w r2, r2, rrx 80088ce: ebb6 0e02 subs.w lr, r6, r2 80088d2: eb75 0e03 sbcs.w lr, r5, r3 80088d6: bf22 ittt cs 80088d8: 1ab6 subcs r6, r6, r2 80088da: 4675 movcs r5, lr 80088dc: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80088e0: ea55 0e06 orrs.w lr, r5, r6 80088e4: d018 beq.n 8008918 <__aeabi_ddiv+0x114> 80088e6: ea4f 1505 mov.w r5, r5, lsl #4 80088ea: ea45 7516 orr.w r5, r5, r6, lsr #28 80088ee: ea4f 1606 mov.w r6, r6, lsl #4 80088f2: ea4f 03c3 mov.w r3, r3, lsl #3 80088f6: ea43 7352 orr.w r3, r3, r2, lsr #29 80088fa: ea4f 02c2 mov.w r2, r2, lsl #3 80088fe: ea5f 1c1c movs.w ip, ip, lsr #4 8008902: d1c0 bne.n 8008886 <__aeabi_ddiv+0x82> 8008904: f411 1f80 tst.w r1, #1048576 @ 0x100000 8008908: d10b bne.n 8008922 <__aeabi_ddiv+0x11e> 800890a: ea41 0100 orr.w r1, r1, r0 800890e: f04f 0000 mov.w r0, #0 8008912: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000 8008916: e7b6 b.n 8008886 <__aeabi_ddiv+0x82> 8008918: f411 1f80 tst.w r1, #1048576 @ 0x100000 800891c: bf04 itt eq 800891e: 4301 orreq r1, r0 8008920: 2000 moveq r0, #0 8008922: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8008926: bf88 it hi 8008928: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 800892c: f63f aeaf bhi.w 800868e <__aeabi_dmul+0xde> 8008930: ebb5 0c03 subs.w ip, r5, r3 8008934: bf04 itt eq 8008936: ebb6 0c02 subseq.w ip, r6, r2 800893a: ea5f 0c50 movseq.w ip, r0, lsr #1 800893e: f150 0000 adcs.w r0, r0, #0 8008942: eb41 5104 adc.w r1, r1, r4, lsl #20 8008946: bd70 pop {r4, r5, r6, pc} 8008948: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000 800894c: ea4e 3111 orr.w r1, lr, r1, lsr #12 8008950: eb14 045c adds.w r4, r4, ip, lsr #1 8008954: bfc2 ittt gt 8008956: ebd4 050c rsbsgt r5, r4, ip 800895a: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800895e: bd70 popgt {r4, r5, r6, pc} 8008960: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008964: f04f 0e00 mov.w lr, #0 8008968: 3c01 subs r4, #1 800896a: e690 b.n 800868e <__aeabi_dmul+0xde> 800896c: ea45 0e06 orr.w lr, r5, r6 8008970: e68d b.n 800868e <__aeabi_dmul+0xde> 8008972: ea0c 5513 and.w r5, ip, r3, lsr #20 8008976: ea94 0f0c teq r4, ip 800897a: bf08 it eq 800897c: ea95 0f0c teqeq r5, ip 8008980: f43f af3b beq.w 80087fa <__aeabi_dmul+0x24a> 8008984: ea94 0f0c teq r4, ip 8008988: d10a bne.n 80089a0 <__aeabi_ddiv+0x19c> 800898a: ea50 3401 orrs.w r4, r0, r1, lsl #12 800898e: f47f af34 bne.w 80087fa <__aeabi_dmul+0x24a> 8008992: ea95 0f0c teq r5, ip 8008996: f47f af25 bne.w 80087e4 <__aeabi_dmul+0x234> 800899a: 4610 mov r0, r2 800899c: 4619 mov r1, r3 800899e: e72c b.n 80087fa <__aeabi_dmul+0x24a> 80089a0: ea95 0f0c teq r5, ip 80089a4: d106 bne.n 80089b4 <__aeabi_ddiv+0x1b0> 80089a6: ea52 3503 orrs.w r5, r2, r3, lsl #12 80089aa: f43f aefd beq.w 80087a8 <__aeabi_dmul+0x1f8> 80089ae: 4610 mov r0, r2 80089b0: 4619 mov r1, r3 80089b2: e722 b.n 80087fa <__aeabi_dmul+0x24a> 80089b4: ea50 0641 orrs.w r6, r0, r1, lsl #1 80089b8: bf18 it ne 80089ba: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80089be: f47f aec5 bne.w 800874c <__aeabi_dmul+0x19c> 80089c2: ea50 0441 orrs.w r4, r0, r1, lsl #1 80089c6: f47f af0d bne.w 80087e4 <__aeabi_dmul+0x234> 80089ca: ea52 0543 orrs.w r5, r2, r3, lsl #1 80089ce: f47f aeeb bne.w 80087a8 <__aeabi_dmul+0x1f8> 80089d2: e712 b.n 80087fa <__aeabi_dmul+0x24a> 080089d4 <__gedf2>: 80089d4: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80089d8: e006 b.n 80089e8 <__cmpdf2+0x4> 80089da: bf00 nop 080089dc <__ledf2>: 80089dc: f04f 0c01 mov.w ip, #1 80089e0: e002 b.n 80089e8 <__cmpdf2+0x4> 80089e2: bf00 nop 080089e4 <__cmpdf2>: 80089e4: f04f 0c01 mov.w ip, #1 80089e8: f84d cd04 str.w ip, [sp, #-4]! 80089ec: ea4f 0c41 mov.w ip, r1, lsl #1 80089f0: ea7f 5c6c mvns.w ip, ip, asr #21 80089f4: ea4f 0c43 mov.w ip, r3, lsl #1 80089f8: bf18 it ne 80089fa: ea7f 5c6c mvnsne.w ip, ip, asr #21 80089fe: d01b beq.n 8008a38 <__cmpdf2+0x54> 8008a00: b001 add sp, #4 8008a02: ea50 0c41 orrs.w ip, r0, r1, lsl #1 8008a06: bf0c ite eq 8008a08: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 8008a0c: ea91 0f03 teqne r1, r3 8008a10: bf02 ittt eq 8008a12: ea90 0f02 teqeq r0, r2 8008a16: 2000 moveq r0, #0 8008a18: 4770 bxeq lr 8008a1a: f110 0f00 cmn.w r0, #0 8008a1e: ea91 0f03 teq r1, r3 8008a22: bf58 it pl 8008a24: 4299 cmppl r1, r3 8008a26: bf08 it eq 8008a28: 4290 cmpeq r0, r2 8008a2a: bf2c ite cs 8008a2c: 17d8 asrcs r0, r3, #31 8008a2e: ea6f 70e3 mvncc.w r0, r3, asr #31 8008a32: f040 0001 orr.w r0, r0, #1 8008a36: 4770 bx lr 8008a38: ea4f 0c41 mov.w ip, r1, lsl #1 8008a3c: ea7f 5c6c mvns.w ip, ip, asr #21 8008a40: d102 bne.n 8008a48 <__cmpdf2+0x64> 8008a42: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8008a46: d107 bne.n 8008a58 <__cmpdf2+0x74> 8008a48: ea4f 0c43 mov.w ip, r3, lsl #1 8008a4c: ea7f 5c6c mvns.w ip, ip, asr #21 8008a50: d1d6 bne.n 8008a00 <__cmpdf2+0x1c> 8008a52: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8008a56: d0d3 beq.n 8008a00 <__cmpdf2+0x1c> 8008a58: f85d 0b04 ldr.w r0, [sp], #4 8008a5c: 4770 bx lr 8008a5e: bf00 nop 08008a60 <__aeabi_cdrcmple>: 8008a60: 4684 mov ip, r0 8008a62: 4610 mov r0, r2 8008a64: 4662 mov r2, ip 8008a66: 468c mov ip, r1 8008a68: 4619 mov r1, r3 8008a6a: 4663 mov r3, ip 8008a6c: e000 b.n 8008a70 <__aeabi_cdcmpeq> 8008a6e: bf00 nop 08008a70 <__aeabi_cdcmpeq>: 8008a70: b501 push {r0, lr} 8008a72: f7ff ffb7 bl 80089e4 <__cmpdf2> 8008a76: 2800 cmp r0, #0 8008a78: bf48 it mi 8008a7a: f110 0f00 cmnmi.w r0, #0 8008a7e: bd01 pop {r0, pc} 08008a80 <__aeabi_dcmpeq>: 8008a80: f84d ed08 str.w lr, [sp, #-8]! 8008a84: f7ff fff4 bl 8008a70 <__aeabi_cdcmpeq> 8008a88: bf0c ite eq 8008a8a: 2001 moveq r0, #1 8008a8c: 2000 movne r0, #0 8008a8e: f85d fb08 ldr.w pc, [sp], #8 8008a92: bf00 nop 08008a94 <__aeabi_dcmplt>: 8008a94: f84d ed08 str.w lr, [sp, #-8]! 8008a98: f7ff ffea bl 8008a70 <__aeabi_cdcmpeq> 8008a9c: bf34 ite cc 8008a9e: 2001 movcc r0, #1 8008aa0: 2000 movcs r0, #0 8008aa2: f85d fb08 ldr.w pc, [sp], #8 8008aa6: bf00 nop 08008aa8 <__aeabi_dcmple>: 8008aa8: f84d ed08 str.w lr, [sp, #-8]! 8008aac: f7ff ffe0 bl 8008a70 <__aeabi_cdcmpeq> 8008ab0: bf94 ite ls 8008ab2: 2001 movls r0, #1 8008ab4: 2000 movhi r0, #0 8008ab6: f85d fb08 ldr.w pc, [sp], #8 8008aba: bf00 nop 08008abc <__aeabi_dcmpge>: 8008abc: f84d ed08 str.w lr, [sp, #-8]! 8008ac0: f7ff ffce bl 8008a60 <__aeabi_cdrcmple> 8008ac4: bf94 ite ls 8008ac6: 2001 movls r0, #1 8008ac8: 2000 movhi r0, #0 8008aca: f85d fb08 ldr.w pc, [sp], #8 8008ace: bf00 nop 08008ad0 <__aeabi_dcmpgt>: 8008ad0: f84d ed08 str.w lr, [sp, #-8]! 8008ad4: f7ff ffc4 bl 8008a60 <__aeabi_cdrcmple> 8008ad8: bf34 ite cc 8008ada: 2001 movcc r0, #1 8008adc: 2000 movcs r0, #0 8008ade: f85d fb08 ldr.w pc, [sp], #8 8008ae2: bf00 nop 08008ae4 <__aeabi_dcmpun>: 8008ae4: ea4f 0c41 mov.w ip, r1, lsl #1 8008ae8: ea7f 5c6c mvns.w ip, ip, asr #21 8008aec: d102 bne.n 8008af4 <__aeabi_dcmpun+0x10> 8008aee: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8008af2: d10a bne.n 8008b0a <__aeabi_dcmpun+0x26> 8008af4: ea4f 0c43 mov.w ip, r3, lsl #1 8008af8: ea7f 5c6c mvns.w ip, ip, asr #21 8008afc: d102 bne.n 8008b04 <__aeabi_dcmpun+0x20> 8008afe: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8008b02: d102 bne.n 8008b0a <__aeabi_dcmpun+0x26> 8008b04: f04f 0000 mov.w r0, #0 8008b08: 4770 bx lr 8008b0a: f04f 0001 mov.w r0, #1 8008b0e: 4770 bx lr 08008b10 <__aeabi_d2iz>: 8008b10: ea4f 0241 mov.w r2, r1, lsl #1 8008b14: f512 1200 adds.w r2, r2, #2097152 @ 0x200000 8008b18: d215 bcs.n 8008b46 <__aeabi_d2iz+0x36> 8008b1a: d511 bpl.n 8008b40 <__aeabi_d2iz+0x30> 8008b1c: f46f 7378 mvn.w r3, #992 @ 0x3e0 8008b20: ebb3 5262 subs.w r2, r3, r2, asr #21 8008b24: d912 bls.n 8008b4c <__aeabi_d2iz+0x3c> 8008b26: ea4f 23c1 mov.w r3, r1, lsl #11 8008b2a: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8008b2e: ea43 5350 orr.w r3, r3, r0, lsr #21 8008b32: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008b36: fa23 f002 lsr.w r0, r3, r2 8008b3a: bf18 it ne 8008b3c: 4240 negne r0, r0 8008b3e: 4770 bx lr 8008b40: f04f 0000 mov.w r0, #0 8008b44: 4770 bx lr 8008b46: ea50 3001 orrs.w r0, r0, r1, lsl #12 8008b4a: d105 bne.n 8008b58 <__aeabi_d2iz+0x48> 8008b4c: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000 8008b50: bf08 it eq 8008b52: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 8008b56: 4770 bx lr 8008b58: f04f 0000 mov.w r0, #0 8008b5c: 4770 bx lr 8008b5e: bf00 nop 08008b60 <__aeabi_d2f>: 8008b60: ea4f 0241 mov.w r2, r1, lsl #1 8008b64: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000 8008b68: bf24 itt cs 8008b6a: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000 8008b6e: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000 8008b72: d90d bls.n 8008b90 <__aeabi_d2f+0x30> 8008b74: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008b78: ea4f 02c0 mov.w r2, r0, lsl #3 8008b7c: ea4c 7050 orr.w r0, ip, r0, lsr #29 8008b80: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000 8008b84: eb40 0083 adc.w r0, r0, r3, lsl #2 8008b88: bf08 it eq 8008b8a: f020 0001 biceq.w r0, r0, #1 8008b8e: 4770 bx lr 8008b90: f011 4f80 tst.w r1, #1073741824 @ 0x40000000 8008b94: d121 bne.n 8008bda <__aeabi_d2f+0x7a> 8008b96: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000 8008b9a: bfbc itt lt 8008b9c: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000 8008ba0: 4770 bxlt lr 8008ba2: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8008ba6: ea4f 5252 mov.w r2, r2, lsr #21 8008baa: f1c2 0218 rsb r2, r2, #24 8008bae: f1c2 0c20 rsb ip, r2, #32 8008bb2: fa10 f30c lsls.w r3, r0, ip 8008bb6: fa20 f002 lsr.w r0, r0, r2 8008bba: bf18 it ne 8008bbc: f040 0001 orrne.w r0, r0, #1 8008bc0: ea4f 23c1 mov.w r3, r1, lsl #11 8008bc4: ea4f 23d3 mov.w r3, r3, lsr #11 8008bc8: fa03 fc0c lsl.w ip, r3, ip 8008bcc: ea40 000c orr.w r0, r0, ip 8008bd0: fa23 f302 lsr.w r3, r3, r2 8008bd4: ea4f 0343 mov.w r3, r3, lsl #1 8008bd8: e7cc b.n 8008b74 <__aeabi_d2f+0x14> 8008bda: ea7f 5362 mvns.w r3, r2, asr #21 8008bde: d107 bne.n 8008bf0 <__aeabi_d2f+0x90> 8008be0: ea50 3301 orrs.w r3, r0, r1, lsl #12 8008be4: bf1e ittt ne 8008be6: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000 8008bea: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000 8008bee: 4770 bxne lr 8008bf0: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000 8008bf4: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008bf8: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008bfc: 4770 bx lr 8008bfe: bf00 nop 08008c00 <__aeabi_frsub>: 8008c00: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000 8008c04: e002 b.n 8008c0c <__addsf3> 8008c06: bf00 nop 08008c08 <__aeabi_fsub>: 8008c08: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 08008c0c <__addsf3>: 8008c0c: 0042 lsls r2, r0, #1 8008c0e: bf1f itttt ne 8008c10: ea5f 0341 movsne.w r3, r1, lsl #1 8008c14: ea92 0f03 teqne r2, r3 8008c18: ea7f 6c22 mvnsne.w ip, r2, asr #24 8008c1c: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008c20: d06a beq.n 8008cf8 <__addsf3+0xec> 8008c22: ea4f 6212 mov.w r2, r2, lsr #24 8008c26: ebd2 6313 rsbs r3, r2, r3, lsr #24 8008c2a: bfc1 itttt gt 8008c2c: 18d2 addgt r2, r2, r3 8008c2e: 4041 eorgt r1, r0 8008c30: 4048 eorgt r0, r1 8008c32: 4041 eorgt r1, r0 8008c34: bfb8 it lt 8008c36: 425b neglt r3, r3 8008c38: 2b19 cmp r3, #25 8008c3a: bf88 it hi 8008c3c: 4770 bxhi lr 8008c3e: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 8008c42: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008c46: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000 8008c4a: bf18 it ne 8008c4c: 4240 negne r0, r0 8008c4e: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8008c52: f441 0100 orr.w r1, r1, #8388608 @ 0x800000 8008c56: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000 8008c5a: bf18 it ne 8008c5c: 4249 negne r1, r1 8008c5e: ea92 0f03 teq r2, r3 8008c62: d03f beq.n 8008ce4 <__addsf3+0xd8> 8008c64: f1a2 0201 sub.w r2, r2, #1 8008c68: fa41 fc03 asr.w ip, r1, r3 8008c6c: eb10 000c adds.w r0, r0, ip 8008c70: f1c3 0320 rsb r3, r3, #32 8008c74: fa01 f103 lsl.w r1, r1, r3 8008c78: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008c7c: d502 bpl.n 8008c84 <__addsf3+0x78> 8008c7e: 4249 negs r1, r1 8008c80: eb60 0040 sbc.w r0, r0, r0, lsl #1 8008c84: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000 8008c88: d313 bcc.n 8008cb2 <__addsf3+0xa6> 8008c8a: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000 8008c8e: d306 bcc.n 8008c9e <__addsf3+0x92> 8008c90: 0840 lsrs r0, r0, #1 8008c92: ea4f 0131 mov.w r1, r1, rrx 8008c96: f102 0201 add.w r2, r2, #1 8008c9a: 2afe cmp r2, #254 @ 0xfe 8008c9c: d251 bcs.n 8008d42 <__addsf3+0x136> 8008c9e: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000 8008ca2: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008ca6: bf08 it eq 8008ca8: f020 0001 biceq.w r0, r0, #1 8008cac: ea40 0003 orr.w r0, r0, r3 8008cb0: 4770 bx lr 8008cb2: 0049 lsls r1, r1, #1 8008cb4: eb40 0000 adc.w r0, r0, r0 8008cb8: 3a01 subs r2, #1 8008cba: bf28 it cs 8008cbc: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000 8008cc0: d2ed bcs.n 8008c9e <__addsf3+0x92> 8008cc2: fab0 fc80 clz ip, r0 8008cc6: f1ac 0c08 sub.w ip, ip, #8 8008cca: ebb2 020c subs.w r2, r2, ip 8008cce: fa00 f00c lsl.w r0, r0, ip 8008cd2: bfaa itet ge 8008cd4: eb00 50c2 addge.w r0, r0, r2, lsl #23 8008cd8: 4252 neglt r2, r2 8008cda: 4318 orrge r0, r3 8008cdc: bfbc itt lt 8008cde: 40d0 lsrlt r0, r2 8008ce0: 4318 orrlt r0, r3 8008ce2: 4770 bx lr 8008ce4: f092 0f00 teq r2, #0 8008ce8: f481 0100 eor.w r1, r1, #8388608 @ 0x800000 8008cec: bf06 itte eq 8008cee: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000 8008cf2: 3201 addeq r2, #1 8008cf4: 3b01 subne r3, #1 8008cf6: e7b5 b.n 8008c64 <__addsf3+0x58> 8008cf8: ea4f 0341 mov.w r3, r1, lsl #1 8008cfc: ea7f 6c22 mvns.w ip, r2, asr #24 8008d00: bf18 it ne 8008d02: ea7f 6c23 mvnsne.w ip, r3, asr #24 8008d06: d021 beq.n 8008d4c <__addsf3+0x140> 8008d08: ea92 0f03 teq r2, r3 8008d0c: d004 beq.n 8008d18 <__addsf3+0x10c> 8008d0e: f092 0f00 teq r2, #0 8008d12: bf08 it eq 8008d14: 4608 moveq r0, r1 8008d16: 4770 bx lr 8008d18: ea90 0f01 teq r0, r1 8008d1c: bf1c itt ne 8008d1e: 2000 movne r0, #0 8008d20: 4770 bxne lr 8008d22: f012 4f7f tst.w r2, #4278190080 @ 0xff000000 8008d26: d104 bne.n 8008d32 <__addsf3+0x126> 8008d28: 0040 lsls r0, r0, #1 8008d2a: bf28 it cs 8008d2c: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000 8008d30: 4770 bx lr 8008d32: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000 8008d36: bf3c itt cc 8008d38: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000 8008d3c: 4770 bxcc lr 8008d3e: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000 8008d42: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000 8008d46: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008d4a: 4770 bx lr 8008d4c: ea7f 6222 mvns.w r2, r2, asr #24 8008d50: bf16 itet ne 8008d52: 4608 movne r0, r1 8008d54: ea7f 6323 mvnseq.w r3, r3, asr #24 8008d58: 4601 movne r1, r0 8008d5a: 0242 lsls r2, r0, #9 8008d5c: bf06 itte eq 8008d5e: ea5f 2341 movseq.w r3, r1, lsl #9 8008d62: ea90 0f01 teqeq r0, r1 8008d66: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000 8008d6a: 4770 bx lr 08008d6c <__aeabi_ui2f>: 8008d6c: f04f 0300 mov.w r3, #0 8008d70: e004 b.n 8008d7c <__aeabi_i2f+0x8> 8008d72: bf00 nop 08008d74 <__aeabi_i2f>: 8008d74: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000 8008d78: bf48 it mi 8008d7a: 4240 negmi r0, r0 8008d7c: ea5f 0c00 movs.w ip, r0 8008d80: bf08 it eq 8008d82: 4770 bxeq lr 8008d84: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000 8008d88: 4601 mov r1, r0 8008d8a: f04f 0000 mov.w r0, #0 8008d8e: e01c b.n 8008dca <__aeabi_l2f+0x2a> 08008d90 <__aeabi_ul2f>: 8008d90: ea50 0201 orrs.w r2, r0, r1 8008d94: bf08 it eq 8008d96: 4770 bxeq lr 8008d98: f04f 0300 mov.w r3, #0 8008d9c: e00a b.n 8008db4 <__aeabi_l2f+0x14> 8008d9e: bf00 nop 08008da0 <__aeabi_l2f>: 8008da0: ea50 0201 orrs.w r2, r0, r1 8008da4: bf08 it eq 8008da6: 4770 bxeq lr 8008da8: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000 8008dac: d502 bpl.n 8008db4 <__aeabi_l2f+0x14> 8008dae: 4240 negs r0, r0 8008db0: eb61 0141 sbc.w r1, r1, r1, lsl #1 8008db4: ea5f 0c01 movs.w ip, r1 8008db8: bf02 ittt eq 8008dba: 4684 moveq ip, r0 8008dbc: 4601 moveq r1, r0 8008dbe: 2000 moveq r0, #0 8008dc0: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000 8008dc4: bf08 it eq 8008dc6: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000 8008dca: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 8008dce: fabc f28c clz r2, ip 8008dd2: 3a08 subs r2, #8 8008dd4: eba3 53c2 sub.w r3, r3, r2, lsl #23 8008dd8: db10 blt.n 8008dfc <__aeabi_l2f+0x5c> 8008dda: fa01 fc02 lsl.w ip, r1, r2 8008dde: 4463 add r3, ip 8008de0: fa00 fc02 lsl.w ip, r0, r2 8008de4: f1c2 0220 rsb r2, r2, #32 8008de8: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 8008dec: fa20 f202 lsr.w r2, r0, r2 8008df0: eb43 0002 adc.w r0, r3, r2 8008df4: bf08 it eq 8008df6: f020 0001 biceq.w r0, r0, #1 8008dfa: 4770 bx lr 8008dfc: f102 0220 add.w r2, r2, #32 8008e00: fa01 fc02 lsl.w ip, r1, r2 8008e04: f1c2 0220 rsb r2, r2, #32 8008e08: ea50 004c orrs.w r0, r0, ip, lsl #1 8008e0c: fa21 f202 lsr.w r2, r1, r2 8008e10: eb43 0002 adc.w r0, r3, r2 8008e14: bf08 it eq 8008e16: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008e1a: 4770 bx lr 08008e1c <__aeabi_fmul>: 8008e1c: f04f 0cff mov.w ip, #255 @ 0xff 8008e20: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008e24: bf1e ittt ne 8008e26: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008e2a: ea92 0f0c teqne r2, ip 8008e2e: ea93 0f0c teqne r3, ip 8008e32: d06f beq.n 8008f14 <__aeabi_fmul+0xf8> 8008e34: 441a add r2, r3 8008e36: ea80 0c01 eor.w ip, r0, r1 8008e3a: 0240 lsls r0, r0, #9 8008e3c: bf18 it ne 8008e3e: ea5f 2141 movsne.w r1, r1, lsl #9 8008e42: d01e beq.n 8008e82 <__aeabi_fmul+0x66> 8008e44: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8008e48: ea43 1050 orr.w r0, r3, r0, lsr #5 8008e4c: ea43 1151 orr.w r1, r3, r1, lsr #5 8008e50: fba0 3101 umull r3, r1, r0, r1 8008e54: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008e58: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000 8008e5c: bf3e ittt cc 8008e5e: 0049 lslcc r1, r1, #1 8008e60: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 8008e64: 005b lslcc r3, r3, #1 8008e66: ea40 0001 orr.w r0, r0, r1 8008e6a: f162 027f sbc.w r2, r2, #127 @ 0x7f 8008e6e: 2afd cmp r2, #253 @ 0xfd 8008e70: d81d bhi.n 8008eae <__aeabi_fmul+0x92> 8008e72: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008e76: eb40 50c2 adc.w r0, r0, r2, lsl #23 8008e7a: bf08 it eq 8008e7c: f020 0001 biceq.w r0, r0, #1 8008e80: 4770 bx lr 8008e82: f090 0f00 teq r0, #0 8008e86: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8008e8a: bf08 it eq 8008e8c: 0249 lsleq r1, r1, #9 8008e8e: ea4c 2050 orr.w r0, ip, r0, lsr #9 8008e92: ea40 2051 orr.w r0, r0, r1, lsr #9 8008e96: 3a7f subs r2, #127 @ 0x7f 8008e98: bfc2 ittt gt 8008e9a: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 8008e9e: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8008ea2: 4770 bxgt lr 8008ea4: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008ea8: f04f 0300 mov.w r3, #0 8008eac: 3a01 subs r2, #1 8008eae: dc5d bgt.n 8008f6c <__aeabi_fmul+0x150> 8008eb0: f112 0f19 cmn.w r2, #25 8008eb4: bfdc itt le 8008eb6: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000 8008eba: 4770 bxle lr 8008ebc: f1c2 0200 rsb r2, r2, #0 8008ec0: 0041 lsls r1, r0, #1 8008ec2: fa21 f102 lsr.w r1, r1, r2 8008ec6: f1c2 0220 rsb r2, r2, #32 8008eca: fa00 fc02 lsl.w ip, r0, r2 8008ece: ea5f 0031 movs.w r0, r1, rrx 8008ed2: f140 0000 adc.w r0, r0, #0 8008ed6: ea53 034c orrs.w r3, r3, ip, lsl #1 8008eda: bf08 it eq 8008edc: ea20 70dc biceq.w r0, r0, ip, lsr #31 8008ee0: 4770 bx lr 8008ee2: f092 0f00 teq r2, #0 8008ee6: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8008eea: bf02 ittt eq 8008eec: 0040 lsleq r0, r0, #1 8008eee: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 8008ef2: 3a01 subeq r2, #1 8008ef4: d0f9 beq.n 8008eea <__aeabi_fmul+0xce> 8008ef6: ea40 000c orr.w r0, r0, ip 8008efa: f093 0f00 teq r3, #0 8008efe: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8008f02: bf02 ittt eq 8008f04: 0049 lsleq r1, r1, #1 8008f06: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8008f0a: 3b01 subeq r3, #1 8008f0c: d0f9 beq.n 8008f02 <__aeabi_fmul+0xe6> 8008f0e: ea41 010c orr.w r1, r1, ip 8008f12: e78f b.n 8008e34 <__aeabi_fmul+0x18> 8008f14: ea0c 53d1 and.w r3, ip, r1, lsr #23 8008f18: ea92 0f0c teq r2, ip 8008f1c: bf18 it ne 8008f1e: ea93 0f0c teqne r3, ip 8008f22: d00a beq.n 8008f3a <__aeabi_fmul+0x11e> 8008f24: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 8008f28: bf18 it ne 8008f2a: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 8008f2e: d1d8 bne.n 8008ee2 <__aeabi_fmul+0xc6> 8008f30: ea80 0001 eor.w r0, r0, r1 8008f34: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008f38: 4770 bx lr 8008f3a: f090 0f00 teq r0, #0 8008f3e: bf17 itett ne 8008f40: f090 4f00 teqne r0, #2147483648 @ 0x80000000 8008f44: 4608 moveq r0, r1 8008f46: f091 0f00 teqne r1, #0 8008f4a: f091 4f00 teqne r1, #2147483648 @ 0x80000000 8008f4e: d014 beq.n 8008f7a <__aeabi_fmul+0x15e> 8008f50: ea92 0f0c teq r2, ip 8008f54: d101 bne.n 8008f5a <__aeabi_fmul+0x13e> 8008f56: 0242 lsls r2, r0, #9 8008f58: d10f bne.n 8008f7a <__aeabi_fmul+0x15e> 8008f5a: ea93 0f0c teq r3, ip 8008f5e: d103 bne.n 8008f68 <__aeabi_fmul+0x14c> 8008f60: 024b lsls r3, r1, #9 8008f62: bf18 it ne 8008f64: 4608 movne r0, r1 8008f66: d108 bne.n 8008f7a <__aeabi_fmul+0x15e> 8008f68: ea80 0001 eor.w r0, r0, r1 8008f6c: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 8008f70: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008f74: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8008f78: 4770 bx lr 8008f7a: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8008f7e: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000 8008f82: 4770 bx lr 08008f84 <__aeabi_fdiv>: 8008f84: f04f 0cff mov.w ip, #255 @ 0xff 8008f88: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8008f8c: bf1e ittt ne 8008f8e: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8008f92: ea92 0f0c teqne r2, ip 8008f96: ea93 0f0c teqne r3, ip 8008f9a: d069 beq.n 8009070 <__aeabi_fdiv+0xec> 8008f9c: eba2 0203 sub.w r2, r2, r3 8008fa0: ea80 0c01 eor.w ip, r0, r1 8008fa4: 0249 lsls r1, r1, #9 8008fa6: ea4f 2040 mov.w r0, r0, lsl #9 8008faa: d037 beq.n 800901c <__aeabi_fdiv+0x98> 8008fac: f04f 5380 mov.w r3, #268435456 @ 0x10000000 8008fb0: ea43 1111 orr.w r1, r3, r1, lsr #4 8008fb4: ea43 1310 orr.w r3, r3, r0, lsr #4 8008fb8: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000 8008fbc: 428b cmp r3, r1 8008fbe: bf38 it cc 8008fc0: 005b lslcc r3, r3, #1 8008fc2: f142 027d adc.w r2, r2, #125 @ 0x7d 8008fc6: f44f 0c00 mov.w ip, #8388608 @ 0x800000 8008fca: 428b cmp r3, r1 8008fcc: bf24 itt cs 8008fce: 1a5b subcs r3, r3, r1 8008fd0: ea40 000c orrcs.w r0, r0, ip 8008fd4: ebb3 0f51 cmp.w r3, r1, lsr #1 8008fd8: bf24 itt cs 8008fda: eba3 0351 subcs.w r3, r3, r1, lsr #1 8008fde: ea40 005c orrcs.w r0, r0, ip, lsr #1 8008fe2: ebb3 0f91 cmp.w r3, r1, lsr #2 8008fe6: bf24 itt cs 8008fe8: eba3 0391 subcs.w r3, r3, r1, lsr #2 8008fec: ea40 009c orrcs.w r0, r0, ip, lsr #2 8008ff0: ebb3 0fd1 cmp.w r3, r1, lsr #3 8008ff4: bf24 itt cs 8008ff6: eba3 03d1 subcs.w r3, r3, r1, lsr #3 8008ffa: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8008ffe: 011b lsls r3, r3, #4 8009000: bf18 it ne 8009002: ea5f 1c1c movsne.w ip, ip, lsr #4 8009006: d1e0 bne.n 8008fca <__aeabi_fdiv+0x46> 8009008: 2afd cmp r2, #253 @ 0xfd 800900a: f63f af50 bhi.w 8008eae <__aeabi_fmul+0x92> 800900e: 428b cmp r3, r1 8009010: eb40 50c2 adc.w r0, r0, r2, lsl #23 8009014: bf08 it eq 8009016: f020 0001 biceq.w r0, r0, #1 800901a: 4770 bx lr 800901c: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000 8009020: ea4c 2050 orr.w r0, ip, r0, lsr #9 8009024: 327f adds r2, #127 @ 0x7f 8009026: bfc2 ittt gt 8009028: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff 800902c: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8009030: 4770 bxgt lr 8009032: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8009036: f04f 0300 mov.w r3, #0 800903a: 3a01 subs r2, #1 800903c: e737 b.n 8008eae <__aeabi_fmul+0x92> 800903e: f092 0f00 teq r2, #0 8009042: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000 8009046: bf02 ittt eq 8009048: 0040 lsleq r0, r0, #1 800904a: f410 0f00 tsteq.w r0, #8388608 @ 0x800000 800904e: 3a01 subeq r2, #1 8009050: d0f9 beq.n 8009046 <__aeabi_fdiv+0xc2> 8009052: ea40 000c orr.w r0, r0, ip 8009056: f093 0f00 teq r3, #0 800905a: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 800905e: bf02 ittt eq 8009060: 0049 lsleq r1, r1, #1 8009062: f411 0f00 tsteq.w r1, #8388608 @ 0x800000 8009066: 3b01 subeq r3, #1 8009068: d0f9 beq.n 800905e <__aeabi_fdiv+0xda> 800906a: ea41 010c orr.w r1, r1, ip 800906e: e795 b.n 8008f9c <__aeabi_fdiv+0x18> 8009070: ea0c 53d1 and.w r3, ip, r1, lsr #23 8009074: ea92 0f0c teq r2, ip 8009078: d108 bne.n 800908c <__aeabi_fdiv+0x108> 800907a: 0242 lsls r2, r0, #9 800907c: f47f af7d bne.w 8008f7a <__aeabi_fmul+0x15e> 8009080: ea93 0f0c teq r3, ip 8009084: f47f af70 bne.w 8008f68 <__aeabi_fmul+0x14c> 8009088: 4608 mov r0, r1 800908a: e776 b.n 8008f7a <__aeabi_fmul+0x15e> 800908c: ea93 0f0c teq r3, ip 8009090: d104 bne.n 800909c <__aeabi_fdiv+0x118> 8009092: 024b lsls r3, r1, #9 8009094: f43f af4c beq.w 8008f30 <__aeabi_fmul+0x114> 8009098: 4608 mov r0, r1 800909a: e76e b.n 8008f7a <__aeabi_fmul+0x15e> 800909c: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000 80090a0: bf18 it ne 80090a2: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000 80090a6: d1ca bne.n 800903e <__aeabi_fdiv+0xba> 80090a8: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000 80090ac: f47f af5c bne.w 8008f68 <__aeabi_fmul+0x14c> 80090b0: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000 80090b4: f47f af3c bne.w 8008f30 <__aeabi_fmul+0x114> 80090b8: e75f b.n 8008f7a <__aeabi_fmul+0x15e> 80090ba: bf00 nop 080090bc <__gesf2>: 80090bc: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80090c0: e006 b.n 80090d0 <__cmpsf2+0x4> 80090c2: bf00 nop 080090c4 <__lesf2>: 80090c4: f04f 0c01 mov.w ip, #1 80090c8: e002 b.n 80090d0 <__cmpsf2+0x4> 80090ca: bf00 nop 080090cc <__cmpsf2>: 80090cc: f04f 0c01 mov.w ip, #1 80090d0: f84d cd04 str.w ip, [sp, #-4]! 80090d4: ea4f 0240 mov.w r2, r0, lsl #1 80090d8: ea4f 0341 mov.w r3, r1, lsl #1 80090dc: ea7f 6c22 mvns.w ip, r2, asr #24 80090e0: bf18 it ne 80090e2: ea7f 6c23 mvnsne.w ip, r3, asr #24 80090e6: d011 beq.n 800910c <__cmpsf2+0x40> 80090e8: b001 add sp, #4 80090ea: ea52 0c53 orrs.w ip, r2, r3, lsr #1 80090ee: bf18 it ne 80090f0: ea90 0f01 teqne r0, r1 80090f4: bf58 it pl 80090f6: ebb2 0003 subspl.w r0, r2, r3 80090fa: bf88 it hi 80090fc: 17c8 asrhi r0, r1, #31 80090fe: bf38 it cc 8009100: ea6f 70e1 mvncc.w r0, r1, asr #31 8009104: bf18 it ne 8009106: f040 0001 orrne.w r0, r0, #1 800910a: 4770 bx lr 800910c: ea7f 6c22 mvns.w ip, r2, asr #24 8009110: d102 bne.n 8009118 <__cmpsf2+0x4c> 8009112: ea5f 2c40 movs.w ip, r0, lsl #9 8009116: d105 bne.n 8009124 <__cmpsf2+0x58> 8009118: ea7f 6c23 mvns.w ip, r3, asr #24 800911c: d1e4 bne.n 80090e8 <__cmpsf2+0x1c> 800911e: ea5f 2c41 movs.w ip, r1, lsl #9 8009122: d0e1 beq.n 80090e8 <__cmpsf2+0x1c> 8009124: f85d 0b04 ldr.w r0, [sp], #4 8009128: 4770 bx lr 800912a: bf00 nop 0800912c <__aeabi_cfrcmple>: 800912c: 4684 mov ip, r0 800912e: 4608 mov r0, r1 8009130: 4661 mov r1, ip 8009132: e7ff b.n 8009134 <__aeabi_cfcmpeq> 08009134 <__aeabi_cfcmpeq>: 8009134: b50f push {r0, r1, r2, r3, lr} 8009136: f7ff ffc9 bl 80090cc <__cmpsf2> 800913a: 2800 cmp r0, #0 800913c: bf48 it mi 800913e: f110 0f00 cmnmi.w r0, #0 8009142: bd0f pop {r0, r1, r2, r3, pc} 08009144 <__aeabi_fcmpeq>: 8009144: f84d ed08 str.w lr, [sp, #-8]! 8009148: f7ff fff4 bl 8009134 <__aeabi_cfcmpeq> 800914c: bf0c ite eq 800914e: 2001 moveq r0, #1 8009150: 2000 movne r0, #0 8009152: f85d fb08 ldr.w pc, [sp], #8 8009156: bf00 nop 08009158 <__aeabi_fcmplt>: 8009158: f84d ed08 str.w lr, [sp, #-8]! 800915c: f7ff ffea bl 8009134 <__aeabi_cfcmpeq> 8009160: bf34 ite cc 8009162: 2001 movcc r0, #1 8009164: 2000 movcs r0, #0 8009166: f85d fb08 ldr.w pc, [sp], #8 800916a: bf00 nop 0800916c <__aeabi_fcmple>: 800916c: f84d ed08 str.w lr, [sp, #-8]! 8009170: f7ff ffe0 bl 8009134 <__aeabi_cfcmpeq> 8009174: bf94 ite ls 8009176: 2001 movls r0, #1 8009178: 2000 movhi r0, #0 800917a: f85d fb08 ldr.w pc, [sp], #8 800917e: bf00 nop 08009180 <__aeabi_fcmpge>: 8009180: f84d ed08 str.w lr, [sp, #-8]! 8009184: f7ff ffd2 bl 800912c <__aeabi_cfrcmple> 8009188: bf94 ite ls 800918a: 2001 movls r0, #1 800918c: 2000 movhi r0, #0 800918e: f85d fb08 ldr.w pc, [sp], #8 8009192: bf00 nop 08009194 <__aeabi_fcmpgt>: 8009194: f84d ed08 str.w lr, [sp, #-8]! 8009198: f7ff ffc8 bl 800912c <__aeabi_cfrcmple> 800919c: bf34 ite cc 800919e: 2001 movcc r0, #1 80091a0: 2000 movcs r0, #0 80091a2: f85d fb08 ldr.w pc, [sp], #8 80091a6: bf00 nop 080091a8 <__aeabi_f2iz>: 80091a8: ea4f 0240 mov.w r2, r0, lsl #1 80091ac: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000 80091b0: d30f bcc.n 80091d2 <__aeabi_f2iz+0x2a> 80091b2: f04f 039e mov.w r3, #158 @ 0x9e 80091b6: ebb3 6212 subs.w r2, r3, r2, lsr #24 80091ba: d90d bls.n 80091d8 <__aeabi_f2iz+0x30> 80091bc: ea4f 2300 mov.w r3, r0, lsl #8 80091c0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80091c4: f010 4f00 tst.w r0, #2147483648 @ 0x80000000 80091c8: fa23 f002 lsr.w r0, r3, r2 80091cc: bf18 it ne 80091ce: 4240 negne r0, r0 80091d0: 4770 bx lr 80091d2: f04f 0000 mov.w r0, #0 80091d6: 4770 bx lr 80091d8: f112 0f61 cmn.w r2, #97 @ 0x61 80091dc: d101 bne.n 80091e2 <__aeabi_f2iz+0x3a> 80091de: 0242 lsls r2, r0, #9 80091e0: d105 bne.n 80091ee <__aeabi_f2iz+0x46> 80091e2: f010 4000 ands.w r0, r0, #2147483648 @ 0x80000000 80091e6: bf08 it eq 80091e8: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 80091ec: 4770 bx lr 80091ee: f04f 0000 mov.w r0, #0 80091f2: 4770 bx lr 080091f4 <__aeabi_uldivmod>: 80091f4: b953 cbnz r3, 800920c <__aeabi_uldivmod+0x18> 80091f6: b94a cbnz r2, 800920c <__aeabi_uldivmod+0x18> 80091f8: 2900 cmp r1, #0 80091fa: bf08 it eq 80091fc: 2800 cmpeq r0, #0 80091fe: bf1c itt ne 8009200: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8009204: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8009208: f000 b98c b.w 8009524 <__aeabi_idiv0> 800920c: f1ad 0c08 sub.w ip, sp, #8 8009210: e96d ce04 strd ip, lr, [sp, #-16]! 8009214: f000 f806 bl 8009224 <__udivmoddi4> 8009218: f8dd e004 ldr.w lr, [sp, #4] 800921c: e9dd 2302 ldrd r2, r3, [sp, #8] 8009220: b004 add sp, #16 8009222: 4770 bx lr 08009224 <__udivmoddi4>: 8009224: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8009228: 9d08 ldr r5, [sp, #32] 800922a: 468e mov lr, r1 800922c: 4604 mov r4, r0 800922e: 4688 mov r8, r1 8009230: 2b00 cmp r3, #0 8009232: d14a bne.n 80092ca <__udivmoddi4+0xa6> 8009234: 428a cmp r2, r1 8009236: 4617 mov r7, r2 8009238: d962 bls.n 8009300 <__udivmoddi4+0xdc> 800923a: fab2 f682 clz r6, r2 800923e: b14e cbz r6, 8009254 <__udivmoddi4+0x30> 8009240: f1c6 0320 rsb r3, r6, #32 8009244: fa01 f806 lsl.w r8, r1, r6 8009248: fa20 f303 lsr.w r3, r0, r3 800924c: 40b7 lsls r7, r6 800924e: ea43 0808 orr.w r8, r3, r8 8009252: 40b4 lsls r4, r6 8009254: ea4f 4e17 mov.w lr, r7, lsr #16 8009258: fbb8 f1fe udiv r1, r8, lr 800925c: fa1f fc87 uxth.w ip, r7 8009260: fb0e 8811 mls r8, lr, r1, r8 8009264: fb01 f20c mul.w r2, r1, ip 8009268: 0c23 lsrs r3, r4, #16 800926a: ea43 4308 orr.w r3, r3, r8, lsl #16 800926e: 429a cmp r2, r3 8009270: d909 bls.n 8009286 <__udivmoddi4+0x62> 8009272: 18fb adds r3, r7, r3 8009274: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8009278: f080 80eb bcs.w 8009452 <__udivmoddi4+0x22e> 800927c: 429a cmp r2, r3 800927e: f240 80e8 bls.w 8009452 <__udivmoddi4+0x22e> 8009282: 3902 subs r1, #2 8009284: 443b add r3, r7 8009286: 1a9a subs r2, r3, r2 8009288: fbb2 f0fe udiv r0, r2, lr 800928c: fb0e 2210 mls r2, lr, r0, r2 8009290: fb00 fc0c mul.w ip, r0, ip 8009294: b2a3 uxth r3, r4 8009296: ea43 4302 orr.w r3, r3, r2, lsl #16 800929a: 459c cmp ip, r3 800929c: d909 bls.n 80092b2 <__udivmoddi4+0x8e> 800929e: 18fb adds r3, r7, r3 80092a0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80092a4: f080 80d7 bcs.w 8009456 <__udivmoddi4+0x232> 80092a8: 459c cmp ip, r3 80092aa: f240 80d4 bls.w 8009456 <__udivmoddi4+0x232> 80092ae: 443b add r3, r7 80092b0: 3802 subs r0, #2 80092b2: ea40 4001 orr.w r0, r0, r1, lsl #16 80092b6: 2100 movs r1, #0 80092b8: eba3 030c sub.w r3, r3, ip 80092bc: b11d cbz r5, 80092c6 <__udivmoddi4+0xa2> 80092be: 2200 movs r2, #0 80092c0: 40f3 lsrs r3, r6 80092c2: e9c5 3200 strd r3, r2, [r5] 80092c6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80092ca: 428b cmp r3, r1 80092cc: d905 bls.n 80092da <__udivmoddi4+0xb6> 80092ce: b10d cbz r5, 80092d4 <__udivmoddi4+0xb0> 80092d0: e9c5 0100 strd r0, r1, [r5] 80092d4: 2100 movs r1, #0 80092d6: 4608 mov r0, r1 80092d8: e7f5 b.n 80092c6 <__udivmoddi4+0xa2> 80092da: fab3 f183 clz r1, r3 80092de: 2900 cmp r1, #0 80092e0: d146 bne.n 8009370 <__udivmoddi4+0x14c> 80092e2: 4573 cmp r3, lr 80092e4: d302 bcc.n 80092ec <__udivmoddi4+0xc8> 80092e6: 4282 cmp r2, r0 80092e8: f200 8108 bhi.w 80094fc <__udivmoddi4+0x2d8> 80092ec: 1a84 subs r4, r0, r2 80092ee: eb6e 0203 sbc.w r2, lr, r3 80092f2: 2001 movs r0, #1 80092f4: 4690 mov r8, r2 80092f6: 2d00 cmp r5, #0 80092f8: d0e5 beq.n 80092c6 <__udivmoddi4+0xa2> 80092fa: e9c5 4800 strd r4, r8, [r5] 80092fe: e7e2 b.n 80092c6 <__udivmoddi4+0xa2> 8009300: 2a00 cmp r2, #0 8009302: f000 8091 beq.w 8009428 <__udivmoddi4+0x204> 8009306: fab2 f682 clz r6, r2 800930a: 2e00 cmp r6, #0 800930c: f040 80a5 bne.w 800945a <__udivmoddi4+0x236> 8009310: 1a8a subs r2, r1, r2 8009312: 2101 movs r1, #1 8009314: 0c03 lsrs r3, r0, #16 8009316: ea4f 4e17 mov.w lr, r7, lsr #16 800931a: b280 uxth r0, r0 800931c: b2bc uxth r4, r7 800931e: fbb2 fcfe udiv ip, r2, lr 8009322: fb0e 221c mls r2, lr, ip, r2 8009326: ea43 4302 orr.w r3, r3, r2, lsl #16 800932a: fb04 f20c mul.w r2, r4, ip 800932e: 429a cmp r2, r3 8009330: d907 bls.n 8009342 <__udivmoddi4+0x11e> 8009332: 18fb adds r3, r7, r3 8009334: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8009338: d202 bcs.n 8009340 <__udivmoddi4+0x11c> 800933a: 429a cmp r2, r3 800933c: f200 80e3 bhi.w 8009506 <__udivmoddi4+0x2e2> 8009340: 46c4 mov ip, r8 8009342: 1a9b subs r3, r3, r2 8009344: fbb3 f2fe udiv r2, r3, lr 8009348: fb0e 3312 mls r3, lr, r2, r3 800934c: fb02 f404 mul.w r4, r2, r4 8009350: ea40 4303 orr.w r3, r0, r3, lsl #16 8009354: 429c cmp r4, r3 8009356: d907 bls.n 8009368 <__udivmoddi4+0x144> 8009358: 18fb adds r3, r7, r3 800935a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800935e: d202 bcs.n 8009366 <__udivmoddi4+0x142> 8009360: 429c cmp r4, r3 8009362: f200 80cd bhi.w 8009500 <__udivmoddi4+0x2dc> 8009366: 4602 mov r2, r0 8009368: 1b1b subs r3, r3, r4 800936a: ea42 400c orr.w r0, r2, ip, lsl #16 800936e: e7a5 b.n 80092bc <__udivmoddi4+0x98> 8009370: f1c1 0620 rsb r6, r1, #32 8009374: 408b lsls r3, r1 8009376: fa22 f706 lsr.w r7, r2, r6 800937a: 431f orrs r7, r3 800937c: fa2e fa06 lsr.w sl, lr, r6 8009380: ea4f 4917 mov.w r9, r7, lsr #16 8009384: fbba f8f9 udiv r8, sl, r9 8009388: fa0e fe01 lsl.w lr, lr, r1 800938c: fa20 f306 lsr.w r3, r0, r6 8009390: fb09 aa18 mls sl, r9, r8, sl 8009394: fa1f fc87 uxth.w ip, r7 8009398: ea43 030e orr.w r3, r3, lr 800939c: fa00 fe01 lsl.w lr, r0, r1 80093a0: fb08 f00c mul.w r0, r8, ip 80093a4: 0c1c lsrs r4, r3, #16 80093a6: ea44 440a orr.w r4, r4, sl, lsl #16 80093aa: 42a0 cmp r0, r4 80093ac: fa02 f201 lsl.w r2, r2, r1 80093b0: d90a bls.n 80093c8 <__udivmoddi4+0x1a4> 80093b2: 193c adds r4, r7, r4 80093b4: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff 80093b8: f080 809e bcs.w 80094f8 <__udivmoddi4+0x2d4> 80093bc: 42a0 cmp r0, r4 80093be: f240 809b bls.w 80094f8 <__udivmoddi4+0x2d4> 80093c2: f1a8 0802 sub.w r8, r8, #2 80093c6: 443c add r4, r7 80093c8: 1a24 subs r4, r4, r0 80093ca: b298 uxth r0, r3 80093cc: fbb4 f3f9 udiv r3, r4, r9 80093d0: fb09 4413 mls r4, r9, r3, r4 80093d4: fb03 fc0c mul.w ip, r3, ip 80093d8: ea40 4404 orr.w r4, r0, r4, lsl #16 80093dc: 45a4 cmp ip, r4 80093de: d909 bls.n 80093f4 <__udivmoddi4+0x1d0> 80093e0: 193c adds r4, r7, r4 80093e2: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 80093e6: f080 8085 bcs.w 80094f4 <__udivmoddi4+0x2d0> 80093ea: 45a4 cmp ip, r4 80093ec: f240 8082 bls.w 80094f4 <__udivmoddi4+0x2d0> 80093f0: 3b02 subs r3, #2 80093f2: 443c add r4, r7 80093f4: ea43 4008 orr.w r0, r3, r8, lsl #16 80093f8: eba4 040c sub.w r4, r4, ip 80093fc: fba0 8c02 umull r8, ip, r0, r2 8009400: 4564 cmp r4, ip 8009402: 4643 mov r3, r8 8009404: 46e1 mov r9, ip 8009406: d364 bcc.n 80094d2 <__udivmoddi4+0x2ae> 8009408: d061 beq.n 80094ce <__udivmoddi4+0x2aa> 800940a: b15d cbz r5, 8009424 <__udivmoddi4+0x200> 800940c: ebbe 0203 subs.w r2, lr, r3 8009410: eb64 0409 sbc.w r4, r4, r9 8009414: fa04 f606 lsl.w r6, r4, r6 8009418: fa22 f301 lsr.w r3, r2, r1 800941c: 431e orrs r6, r3 800941e: 40cc lsrs r4, r1 8009420: e9c5 6400 strd r6, r4, [r5] 8009424: 2100 movs r1, #0 8009426: e74e b.n 80092c6 <__udivmoddi4+0xa2> 8009428: fbb1 fcf2 udiv ip, r1, r2 800942c: 0c01 lsrs r1, r0, #16 800942e: ea41 410e orr.w r1, r1, lr, lsl #16 8009432: b280 uxth r0, r0 8009434: ea40 4201 orr.w r2, r0, r1, lsl #16 8009438: 463b mov r3, r7 800943a: fbb1 f1f7 udiv r1, r1, r7 800943e: 4638 mov r0, r7 8009440: 463c mov r4, r7 8009442: 46b8 mov r8, r7 8009444: 46be mov lr, r7 8009446: 2620 movs r6, #32 8009448: eba2 0208 sub.w r2, r2, r8 800944c: ea41 410c orr.w r1, r1, ip, lsl #16 8009450: e765 b.n 800931e <__udivmoddi4+0xfa> 8009452: 4601 mov r1, r0 8009454: e717 b.n 8009286 <__udivmoddi4+0x62> 8009456: 4610 mov r0, r2 8009458: e72b b.n 80092b2 <__udivmoddi4+0x8e> 800945a: f1c6 0120 rsb r1, r6, #32 800945e: fa2e fc01 lsr.w ip, lr, r1 8009462: 40b7 lsls r7, r6 8009464: fa0e fe06 lsl.w lr, lr, r6 8009468: fa20 f101 lsr.w r1, r0, r1 800946c: ea41 010e orr.w r1, r1, lr 8009470: ea4f 4e17 mov.w lr, r7, lsr #16 8009474: fbbc f8fe udiv r8, ip, lr 8009478: b2bc uxth r4, r7 800947a: fb0e cc18 mls ip, lr, r8, ip 800947e: fb08 f904 mul.w r9, r8, r4 8009482: 0c0a lsrs r2, r1, #16 8009484: ea42 420c orr.w r2, r2, ip, lsl #16 8009488: 40b0 lsls r0, r6 800948a: 4591 cmp r9, r2 800948c: ea4f 4310 mov.w r3, r0, lsr #16 8009490: b280 uxth r0, r0 8009492: d93e bls.n 8009512 <__udivmoddi4+0x2ee> 8009494: 18ba adds r2, r7, r2 8009496: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 800949a: d201 bcs.n 80094a0 <__udivmoddi4+0x27c> 800949c: 4591 cmp r9, r2 800949e: d81f bhi.n 80094e0 <__udivmoddi4+0x2bc> 80094a0: eba2 0209 sub.w r2, r2, r9 80094a4: fbb2 f9fe udiv r9, r2, lr 80094a8: fb09 f804 mul.w r8, r9, r4 80094ac: fb0e 2a19 mls sl, lr, r9, r2 80094b0: b28a uxth r2, r1 80094b2: ea42 420a orr.w r2, r2, sl, lsl #16 80094b6: 4542 cmp r2, r8 80094b8: d229 bcs.n 800950e <__udivmoddi4+0x2ea> 80094ba: 18ba adds r2, r7, r2 80094bc: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80094c0: d2c2 bcs.n 8009448 <__udivmoddi4+0x224> 80094c2: 4542 cmp r2, r8 80094c4: d2c0 bcs.n 8009448 <__udivmoddi4+0x224> 80094c6: f1a9 0102 sub.w r1, r9, #2 80094ca: 443a add r2, r7 80094cc: e7bc b.n 8009448 <__udivmoddi4+0x224> 80094ce: 45c6 cmp lr, r8 80094d0: d29b bcs.n 800940a <__udivmoddi4+0x1e6> 80094d2: ebb8 0302 subs.w r3, r8, r2 80094d6: eb6c 0c07 sbc.w ip, ip, r7 80094da: 3801 subs r0, #1 80094dc: 46e1 mov r9, ip 80094de: e794 b.n 800940a <__udivmoddi4+0x1e6> 80094e0: eba7 0909 sub.w r9, r7, r9 80094e4: 444a add r2, r9 80094e6: fbb2 f9fe udiv r9, r2, lr 80094ea: f1a8 0c02 sub.w ip, r8, #2 80094ee: fb09 f804 mul.w r8, r9, r4 80094f2: e7db b.n 80094ac <__udivmoddi4+0x288> 80094f4: 4603 mov r3, r0 80094f6: e77d b.n 80093f4 <__udivmoddi4+0x1d0> 80094f8: 46d0 mov r8, sl 80094fa: e765 b.n 80093c8 <__udivmoddi4+0x1a4> 80094fc: 4608 mov r0, r1 80094fe: e6fa b.n 80092f6 <__udivmoddi4+0xd2> 8009500: 443b add r3, r7 8009502: 3a02 subs r2, #2 8009504: e730 b.n 8009368 <__udivmoddi4+0x144> 8009506: f1ac 0c02 sub.w ip, ip, #2 800950a: 443b add r3, r7 800950c: e719 b.n 8009342 <__udivmoddi4+0x11e> 800950e: 4649 mov r1, r9 8009510: e79a b.n 8009448 <__udivmoddi4+0x224> 8009512: eba2 0209 sub.w r2, r2, r9 8009516: fbb2 f9fe udiv r9, r2, lr 800951a: 46c4 mov ip, r8 800951c: fb09 f804 mul.w r8, r9, r4 8009520: e7c4 b.n 80094ac <__udivmoddi4+0x288> 8009522: bf00 nop 08009524 <__aeabi_idiv0>: 8009524: 4770 bx lr 8009526: bf00 nop 08009528 : static volatile uint16_t adc_dma_raw[6]; volatile ADC_ScanData_t adc_data = {0}; static volatile uint8_t adc_scan_data_ready = 0u; void ADC_ScanStart(void) { 8009528: b580 push {r7, lr} 800952a: af00 add r7, sp, #0 if (HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc_dma_raw, 6u) != HAL_OK) 800952c: 2206 movs r2, #6 800952e: 4905 ldr r1, [pc, #20] @ (8009544 ) 8009530: 4805 ldr r0, [pc, #20] @ (8009548 ) 8009532: f005 f833 bl 800e59c 8009536: 4603 mov r3, r0 8009538: 2b00 cmp r3, #0 800953a: d001 beq.n 8009540 { Error_Handler(); 800953c: f001 fbca bl 800acd4 } } 8009540: bf00 nop 8009542: bd80 pop {r7, pc} 8009544: 20000274 .word 0x20000274 8009548: 20000290 .word 0x20000290 0800954c : ISR_FAST void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { if (hadc->Instance != ADC1) 800954c: 4b0e ldr r3, [pc, #56] @ (8009588 ) 800954e: 6802 ldr r2, [r0, #0] 8009550: 429a cmp r2, r3 8009552: d118 bne.n 8009586 adc_data.cp_raw = adc_dma_raw[1]; adc_data.ntc1_raw = adc_dma_raw[2]; adc_data.ntc2_raw = adc_dma_raw[3]; adc_data.temp_sensor_raw = adc_dma_raw[4]; adc_data.vrefint_raw = adc_dma_raw[5]; adc_scan_data_ready = 1u; 8009554: f04f 0c01 mov.w ip, #1 adc_data.in3_raw = adc_dma_raw[0]; 8009558: 4a0c ldr r2, [pc, #48] @ (800958c ) 800955a: 4b0d ldr r3, [pc, #52] @ (8009590 ) 800955c: 8811 ldrh r1, [r2, #0] adc_scan_data_ready = 1u; 800955e: 480d ldr r0, [pc, #52] @ (8009594 ) adc_data.in3_raw = adc_dma_raw[0]; 8009560: b289 uxth r1, r1 8009562: 8019 strh r1, [r3, #0] adc_data.cp_raw = adc_dma_raw[1]; 8009564: 8851 ldrh r1, [r2, #2] 8009566: b289 uxth r1, r1 8009568: 8059 strh r1, [r3, #2] adc_data.ntc1_raw = adc_dma_raw[2]; 800956a: 8891 ldrh r1, [r2, #4] 800956c: b289 uxth r1, r1 800956e: 8099 strh r1, [r3, #4] adc_data.ntc2_raw = adc_dma_raw[3]; 8009570: 88d1 ldrh r1, [r2, #6] 8009572: b289 uxth r1, r1 8009574: 80d9 strh r1, [r3, #6] adc_data.temp_sensor_raw = adc_dma_raw[4]; 8009576: 8911 ldrh r1, [r2, #8] 8009578: b289 uxth r1, r1 800957a: 8119 strh r1, [r3, #8] adc_data.vrefint_raw = adc_dma_raw[5]; 800957c: 8952 ldrh r2, [r2, #10] 800957e: b292 uxth r2, r2 8009580: 815a strh r2, [r3, #10] adc_scan_data_ready = 1u; 8009582: f880 c000 strb.w ip, [r0] } 8009586: 4770 bx lr 8009588: 40012400 .word 0x40012400 800958c: 20000274 .word 0x20000274 8009590: 20000280 .word 0x20000280 8009594: 2000028c .word 0x2000028c 08009598 : ADC_HandleTypeDef hadc1; DMA_HandleTypeDef hdma_adc1; /* ADC1 init function */ void MX_ADC1_Init(void) { 8009598: b580 push {r7, lr} 800959a: b084 sub sp, #16 800959c: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 800959e: 1d3b adds r3, r7, #4 80095a0: 2200 movs r2, #0 80095a2: 601a str r2, [r3, #0] 80095a4: 605a str r2, [r3, #4] 80095a6: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 80095a8: 4b3c ldr r3, [pc, #240] @ (800969c ) 80095aa: 4a3d ldr r2, [pc, #244] @ (80096a0 ) 80095ac: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 80095ae: 4b3b ldr r3, [pc, #236] @ (800969c ) 80095b0: f44f 7280 mov.w r2, #256 @ 0x100 80095b4: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = DISABLE; 80095b6: 4b39 ldr r3, [pc, #228] @ (800969c ) 80095b8: 2200 movs r2, #0 80095ba: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 80095bc: 4b37 ldr r3, [pc, #220] @ (800969c ) 80095be: 2200 movs r2, #0 80095c0: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T3_TRGO; 80095c2: 4b36 ldr r3, [pc, #216] @ (800969c ) 80095c4: f44f 2200 mov.w r2, #524288 @ 0x80000 80095c8: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80095ca: 4b34 ldr r3, [pc, #208] @ (800969c ) 80095cc: 2200 movs r2, #0 80095ce: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 6; 80095d0: 4b32 ldr r3, [pc, #200] @ (800969c ) 80095d2: 2206 movs r2, #6 80095d4: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 80095d6: 4831 ldr r0, [pc, #196] @ (800969c ) 80095d8: f004 ff08 bl 800e3ec 80095dc: 4603 mov r3, r0 80095de: 2b00 cmp r3, #0 80095e0: d001 beq.n 80095e6 { Error_Handler(); 80095e2: f001 fb77 bl 800acd4 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 80095e6: 2303 movs r3, #3 80095e8: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 80095ea: 2301 movs r3, #1 80095ec: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_41CYCLES_5; 80095ee: 2304 movs r3, #4 80095f0: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80095f2: 1d3b adds r3, r7, #4 80095f4: 4619 mov r1, r3 80095f6: 4829 ldr r0, [pc, #164] @ (800969c ) 80095f8: f005 f988 bl 800e90c 80095fc: 4603 mov r3, r0 80095fe: 2b00 cmp r3, #0 8009600: d001 beq.n 8009606 { Error_Handler(); 8009602: f001 fb67 bl 800acd4 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8009606: 2304 movs r3, #4 8009608: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 800960a: 2302 movs r3, #2 800960c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800960e: 1d3b adds r3, r7, #4 8009610: 4619 mov r1, r3 8009612: 4822 ldr r0, [pc, #136] @ (800969c ) 8009614: f005 f97a bl 800e90c 8009618: 4603 mov r3, r0 800961a: 2b00 cmp r3, #0 800961c: d001 beq.n 8009622 { Error_Handler(); 800961e: f001 fb59 bl 800acd4 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 8009622: 2308 movs r3, #8 8009624: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8009626: 2303 movs r3, #3 8009628: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800962a: 1d3b adds r3, r7, #4 800962c: 4619 mov r1, r3 800962e: 481b ldr r0, [pc, #108] @ (800969c ) 8009630: f005 f96c bl 800e90c 8009634: 4603 mov r3, r0 8009636: 2b00 cmp r3, #0 8009638: d001 beq.n 800963e { Error_Handler(); 800963a: f001 fb4b bl 800acd4 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_9; 800963e: 2309 movs r3, #9 8009640: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_4; 8009642: 2304 movs r3, #4 8009644: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8009646: 1d3b adds r3, r7, #4 8009648: 4619 mov r1, r3 800964a: 4814 ldr r0, [pc, #80] @ (800969c ) 800964c: f005 f95e bl 800e90c 8009650: 4603 mov r3, r0 8009652: 2b00 cmp r3, #0 8009654: d001 beq.n 800965a { Error_Handler(); 8009656: f001 fb3d bl 800acd4 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; 800965a: 2310 movs r3, #16 800965c: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_5; 800965e: 2305 movs r3, #5 8009660: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8009662: 1d3b adds r3, r7, #4 8009664: 4619 mov r1, r3 8009666: 480d ldr r0, [pc, #52] @ (800969c ) 8009668: f005 f950 bl 800e90c 800966c: 4603 mov r3, r0 800966e: 2b00 cmp r3, #0 8009670: d001 beq.n 8009676 { Error_Handler(); 8009672: f001 fb2f bl 800acd4 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; 8009676: 2311 movs r3, #17 8009678: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_6; 800967a: 2306 movs r3, #6 800967c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800967e: 1d3b adds r3, r7, #4 8009680: 4619 mov r1, r3 8009682: 4806 ldr r0, [pc, #24] @ (800969c ) 8009684: f005 f942 bl 800e90c 8009688: 4603 mov r3, r0 800968a: 2b00 cmp r3, #0 800968c: d001 beq.n 8009692 { Error_Handler(); 800968e: f001 fb21 bl 800acd4 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 8009692: bf00 nop 8009694: 3710 adds r7, #16 8009696: 46bd mov sp, r7 8009698: bd80 pop {r7, pc} 800969a: bf00 nop 800969c: 20000290 .word 0x20000290 80096a0: 40012400 .word 0x40012400 080096a4 : void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 80096a4: b580 push {r7, lr} 80096a6: b08a sub sp, #40 @ 0x28 80096a8: af00 add r7, sp, #0 80096aa: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80096ac: f107 0318 add.w r3, r7, #24 80096b0: 2200 movs r2, #0 80096b2: 601a str r2, [r3, #0] 80096b4: 605a str r2, [r3, #4] 80096b6: 609a str r2, [r3, #8] 80096b8: 60da str r2, [r3, #12] if(adcHandle->Instance==ADC1) 80096ba: 687b ldr r3, [r7, #4] 80096bc: 681b ldr r3, [r3, #0] 80096be: 4a38 ldr r2, [pc, #224] @ (80097a0 ) 80096c0: 4293 cmp r3, r2 80096c2: d168 bne.n 8009796 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* ADC1 clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 80096c4: 4b37 ldr r3, [pc, #220] @ (80097a4 ) 80096c6: 699b ldr r3, [r3, #24] 80096c8: 4a36 ldr r2, [pc, #216] @ (80097a4 ) 80096ca: f443 7300 orr.w r3, r3, #512 @ 0x200 80096ce: 6193 str r3, [r2, #24] 80096d0: 4b34 ldr r3, [pc, #208] @ (80097a4 ) 80096d2: 699b ldr r3, [r3, #24] 80096d4: f403 7300 and.w r3, r3, #512 @ 0x200 80096d8: 617b str r3, [r7, #20] 80096da: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 80096dc: 4b31 ldr r3, [pc, #196] @ (80097a4 ) 80096de: 699b ldr r3, [r3, #24] 80096e0: 4a30 ldr r2, [pc, #192] @ (80097a4 ) 80096e2: f043 0304 orr.w r3, r3, #4 80096e6: 6193 str r3, [r2, #24] 80096e8: 4b2e ldr r3, [pc, #184] @ (80097a4 ) 80096ea: 699b ldr r3, [r3, #24] 80096ec: f003 0304 and.w r3, r3, #4 80096f0: 613b str r3, [r7, #16] 80096f2: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 80096f4: 4b2b ldr r3, [pc, #172] @ (80097a4 ) 80096f6: 699b ldr r3, [r3, #24] 80096f8: 4a2a ldr r2, [pc, #168] @ (80097a4 ) 80096fa: f043 0308 orr.w r3, r3, #8 80096fe: 6193 str r3, [r2, #24] 8009700: 4b28 ldr r3, [pc, #160] @ (80097a4 ) 8009702: 699b ldr r3, [r3, #24] 8009704: f003 0308 and.w r3, r3, #8 8009708: 60fb str r3, [r7, #12] 800970a: 68fb ldr r3, [r7, #12] PA3 ------> ADC1_IN3 PA4 ------> ADC1_IN4 PB0 ------> ADC1_IN8 PB1 ------> ADC1_IN9 */ GPIO_InitStruct.Pin = GPIO_PIN_3|CP_ADC_Pin; 800970c: 2318 movs r3, #24 800970e: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009710: 2303 movs r3, #3 8009712: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8009714: f107 0318 add.w r3, r7, #24 8009718: 4619 mov r1, r3 800971a: 4823 ldr r0, [pc, #140] @ (80097a8 ) 800971c: f007 f834 bl 8010788 GPIO_InitStruct.Pin = ADC_NTC1_Pin|ADC_NTC2_Pin; 8009720: 2303 movs r3, #3 8009722: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8009724: 2303 movs r3, #3 8009726: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009728: f107 0318 add.w r3, r7, #24 800972c: 4619 mov r1, r3 800972e: 481f ldr r0, [pc, #124] @ (80097ac ) 8009730: f007 f82a bl 8010788 /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel1; 8009734: 4b1e ldr r3, [pc, #120] @ (80097b0 ) 8009736: 4a1f ldr r2, [pc, #124] @ (80097b4 ) 8009738: 601a str r2, [r3, #0] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 800973a: 4b1d ldr r3, [pc, #116] @ (80097b0 ) 800973c: 2200 movs r2, #0 800973e: 605a str r2, [r3, #4] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8009740: 4b1b ldr r3, [pc, #108] @ (80097b0 ) 8009742: 2200 movs r2, #0 8009744: 609a str r2, [r3, #8] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8009746: 4b1a ldr r3, [pc, #104] @ (80097b0 ) 8009748: 2280 movs r2, #128 @ 0x80 800974a: 60da str r2, [r3, #12] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 800974c: 4b18 ldr r3, [pc, #96] @ (80097b0 ) 800974e: f44f 7280 mov.w r2, #256 @ 0x100 8009752: 611a str r2, [r3, #16] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8009754: 4b16 ldr r3, [pc, #88] @ (80097b0 ) 8009756: f44f 6280 mov.w r2, #1024 @ 0x400 800975a: 615a str r2, [r3, #20] hdma_adc1.Init.Mode = DMA_CIRCULAR; 800975c: 4b14 ldr r3, [pc, #80] @ (80097b0 ) 800975e: 2220 movs r2, #32 8009760: 619a str r2, [r3, #24] hdma_adc1.Init.Priority = DMA_PRIORITY_MEDIUM; 8009762: 4b13 ldr r3, [pc, #76] @ (80097b0 ) 8009764: f44f 5280 mov.w r2, #4096 @ 0x1000 8009768: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 800976a: 4811 ldr r0, [pc, #68] @ (80097b0 ) 800976c: f006 fb7e bl 800fe6c 8009770: 4603 mov r3, r0 8009772: 2b00 cmp r3, #0 8009774: d001 beq.n 800977a { Error_Handler(); 8009776: f001 faad bl 800acd4 } __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1); 800977a: 687b ldr r3, [r7, #4] 800977c: 4a0c ldr r2, [pc, #48] @ (80097b0 ) 800977e: 621a str r2, [r3, #32] 8009780: 4a0b ldr r2, [pc, #44] @ (80097b0 ) 8009782: 687b ldr r3, [r7, #4] 8009784: 6253 str r3, [r2, #36] @ 0x24 /* ADC1 interrupt Init */ HAL_NVIC_SetPriority(ADC1_2_IRQn, 7, 0); 8009786: 2200 movs r2, #0 8009788: 2107 movs r1, #7 800978a: 2012 movs r0, #18 800978c: f006 fb1b bl 800fdc6 HAL_NVIC_EnableIRQ(ADC1_2_IRQn); 8009790: 2012 movs r0, #18 8009792: f006 fb34 bl 800fdfe /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 8009796: bf00 nop 8009798: 3728 adds r7, #40 @ 0x28 800979a: 46bd mov sp, r7 800979c: bd80 pop {r7, pc} 800979e: bf00 nop 80097a0: 40012400 .word 0x40012400 80097a4: 40021000 .word 0x40021000 80097a8: 40010800 .word 0x40010800 80097ac: 40010c00 .word 0x40010c00 80097b0: 200002c0 .word 0x200002c0 80097b4: 40020008 .word 0x40020008 080097b8 : uint8_t RELAY_State[RELAY_COUNT]; static volatile uint8_t adc_lock = 0; static SMAFilter_t conn_temp_adc_filter[2]; void RELAY_Write(relay_t num, uint8_t state){ 80097b8: b580 push {r7, lr} 80097ba: b082 sub sp, #8 80097bc: af00 add r7, sp, #0 80097be: 4603 mov r3, r0 80097c0: 460a mov r2, r1 80097c2: 71fb strb r3, [r7, #7] 80097c4: 4613 mov r3, r2 80097c6: 71bb strb r3, [r7, #6] switch (num) { 80097c8: 79fb ldrb r3, [r7, #7] 80097ca: 2b07 cmp r3, #7 80097cc: d850 bhi.n 8009870 80097ce: a201 add r2, pc, #4 @ (adr r2, 80097d4 ) 80097d0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80097d4: 080097f5 .word 0x080097f5 80097d8: 08009805 .word 0x08009805 80097dc: 08009815 .word 0x08009815 80097e0: 08009825 .word 0x08009825 80097e4: 08009835 .word 0x08009835 80097e8: 08009845 .word 0x08009845 80097ec: 08009853 .word 0x08009853 80097f0: 08009863 .word 0x08009863 case RELAY_AUX0: HAL_GPIO_WritePin(RELAY1_GPIO_Port, RELAY1_Pin, state); 80097f4: 79bb ldrb r3, [r7, #6] 80097f6: 461a mov r2, r3 80097f8: f44f 7180 mov.w r1, #256 @ 0x100 80097fc: 4821 ldr r0, [pc, #132] @ (8009884 ) 80097fe: f007 f95e bl 8010abe break; 8009802: e036 b.n 8009872 case RELAY_AUX1: HAL_GPIO_WritePin(RELAY2_GPIO_Port, RELAY2_Pin, state); 8009804: 79bb ldrb r3, [r7, #6] 8009806: 461a mov r2, r3 8009808: f44f 7100 mov.w r1, #512 @ 0x200 800980c: 481d ldr r0, [pc, #116] @ (8009884 ) 800980e: f007 f956 bl 8010abe break; 8009812: e02e b.n 8009872 case RELAY3: HAL_GPIO_WritePin(RELAY3_GPIO_Port, RELAY3_Pin, state); 8009814: 79bb ldrb r3, [r7, #6] 8009816: 461a mov r2, r3 8009818: f44f 6180 mov.w r1, #1024 @ 0x400 800981c: 4819 ldr r0, [pc, #100] @ (8009884 ) 800981e: f007 f94e bl 8010abe break; 8009822: e026 b.n 8009872 case RELAY_DC: HAL_GPIO_WritePin(RELAY4_GPIO_Port, RELAY4_Pin, state); 8009824: 79bb ldrb r3, [r7, #6] 8009826: 461a mov r2, r3 8009828: f44f 6100 mov.w r1, #2048 @ 0x800 800982c: 4815 ldr r0, [pc, #84] @ (8009884 ) 800982e: f007 f946 bl 8010abe break; 8009832: e01e b.n 8009872 case RELAY_AC: HAL_GPIO_WritePin(RELAY5_GPIO_Port, RELAY5_Pin, state); 8009834: 79bb ldrb r3, [r7, #6] 8009836: 461a mov r2, r3 8009838: f44f 5180 mov.w r1, #4096 @ 0x1000 800983c: 4811 ldr r0, [pc, #68] @ (8009884 ) 800983e: f007 f93e bl 8010abe break; 8009842: e016 b.n 8009872 case RELAY_CP: HAL_GPIO_WritePin(RELAY_CP_GPIO_Port, RELAY_CP_Pin, state); 8009844: 79bb ldrb r3, [r7, #6] 8009846: 461a mov r2, r3 8009848: 2108 movs r1, #8 800984a: 480f ldr r0, [pc, #60] @ (8009888 ) 800984c: f007 f937 bl 8010abe break; 8009850: e00f b.n 8009872 case RELAY_CC: HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, state); 8009852: 79bb ldrb r3, [r7, #6] 8009854: 461a mov r2, r3 8009856: f44f 4100 mov.w r1, #32768 @ 0x8000 800985a: 480c ldr r0, [pc, #48] @ (800988c ) 800985c: f007 f92f bl 8010abe break; 8009860: e007 b.n 8009872 case RELAY_DC1: HAL_GPIO_WritePin(RELAY_DC_GPIO_Port, RELAY_DC_Pin, state); 8009862: 79bb ldrb r3, [r7, #6] 8009864: 461a mov r2, r3 8009866: 2108 movs r1, #8 8009868: 4809 ldr r0, [pc, #36] @ (8009890 ) 800986a: f007 f928 bl 8010abe break; 800986e: e000 b.n 8009872 default: break; 8009870: bf00 nop } RELAY_State[num] = state; 8009872: 79fb ldrb r3, [r7, #7] 8009874: 4907 ldr r1, [pc, #28] @ (8009894 ) 8009876: 79ba ldrb r2, [r7, #6] 8009878: 54ca strb r2, [r1, r3] } 800987a: bf00 nop 800987c: 3708 adds r7, #8 800987e: 46bd mov sp, r7 8009880: bd80 pop {r7, pc} 8009882: bf00 nop 8009884: 40011800 .word 0x40011800 8009888: 40011000 .word 0x40011000 800988c: 40010800 .word 0x40010800 8009890: 40011400 .word 0x40011400 8009894: 20000304 .word 0x20000304 08009898 : uint8_t RELAY_Read(relay_t num){ 8009898: b480 push {r7} 800989a: b083 sub sp, #12 800989c: af00 add r7, sp, #0 800989e: 4603 mov r3, r0 80098a0: 71fb strb r3, [r7, #7] return RELAY_State[num]; 80098a2: 79fb ldrb r3, [r7, #7] 80098a4: 4a03 ldr r2, [pc, #12] @ (80098b4 ) 80098a6: 5cd3 ldrb r3, [r2, r3] } 80098a8: 4618 mov r0, r3 80098aa: 370c adds r7, #12 80098ac: 46bd mov sp, r7 80098ae: bc80 pop {r7} 80098b0: 4770 bx lr 80098b2: bf00 nop 80098b4: 20000304 .word 0x20000304 080098b8 : uint8_t IN_ReadInput(inputNum_t input_n){ 80098b8: b580 push {r7, lr} 80098ba: b082 sub sp, #8 80098bc: af00 add r7, sp, #0 80098be: 4603 mov r3, r0 80098c0: 71fb strb r3, [r7, #7] switch(input_n){ 80098c2: 79fb ldrb r3, [r7, #7] 80098c4: 2b06 cmp r3, #6 80098c6: d83b bhi.n 8009940 80098c8: a201 add r2, pc, #4 @ (adr r2, 80098d0 ) 80098ca: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80098ce: bf00 nop 80098d0: 080098ed .word 0x080098ed 80098d4: 080098f9 .word 0x080098f9 80098d8: 08009905 .word 0x08009905 80098dc: 08009911 .word 0x08009911 80098e0: 0800991d .word 0x0800991d 80098e4: 08009929 .word 0x08009929 80098e8: 08009935 .word 0x08009935 case IN_SW0: return HAL_GPIO_ReadPin(IN_SW0_GPIO_Port, IN_SW0_Pin); 80098ec: 2102 movs r1, #2 80098ee: 4817 ldr r0, [pc, #92] @ (800994c ) 80098f0: f007 f8ce bl 8010a90 80098f4: 4603 mov r3, r0 80098f6: e024 b.n 8009942 case IN_SW1: return HAL_GPIO_ReadPin(IN_SW1_GPIO_Port, IN_SW1_Pin); 80098f8: 2104 movs r1, #4 80098fa: 4814 ldr r0, [pc, #80] @ (800994c ) 80098fc: f007 f8c8 bl 8010a90 8009900: 4603 mov r3, r0 8009902: e01e b.n 8009942 case IN0: return HAL_GPIO_ReadPin(IN0_GPIO_Port, IN0_Pin); 8009904: 2180 movs r1, #128 @ 0x80 8009906: 4812 ldr r0, [pc, #72] @ (8009950 ) 8009908: f007 f8c2 bl 8010a90 800990c: 4603 mov r3, r0 800990e: e018 b.n 8009942 case IN_ESTOP: return HAL_GPIO_ReadPin(IN_ESTOP_GPIO_Port, IN_ESTOP_Pin); 8009910: 2180 movs r1, #128 @ 0x80 8009912: 4810 ldr r0, [pc, #64] @ (8009954 ) 8009914: f007 f8bc bl 8010a90 8009918: 4603 mov r3, r0 800991a: e012 b.n 8009942 case IN_FB1: return HAL_GPIO_ReadPin(IN_FB1_GPIO_Port, IN_FB1_Pin); 800991c: 2110 movs r1, #16 800991e: 480e ldr r0, [pc, #56] @ (8009958 ) 8009920: f007 f8b6 bl 8010a90 8009924: 4603 mov r3, r0 8009926: e00c b.n 8009942 case IN_CONT_FB_DC: return HAL_GPIO_ReadPin(IN_FB2_GPIO_Port, IN_FB2_Pin); 8009928: 2108 movs r1, #8 800992a: 480b ldr r0, [pc, #44] @ (8009958 ) 800992c: f007 f8b0 bl 8010a90 8009930: 4603 mov r3, r0 8009932: e006 b.n 8009942 case ISO_IN: return HAL_GPIO_ReadPin(ISO_IN_GPIO_Port, ISO_IN_Pin); 8009934: 2102 movs r1, #2 8009936: 4806 ldr r0, [pc, #24] @ (8009950 ) 8009938: f007 f8aa bl 8010a90 800993c: 4603 mov r3, r0 800993e: e000 b.n 8009942 default: return 0; 8009940: 2300 movs r3, #0 } } 8009942: 4618 mov r0, r3 8009944: 3708 adds r7, #8 8009946: 46bd mov sp, r7 8009948: bd80 pop {r7, pc} 800994a: bf00 nop 800994c: 40010800 .word 0x40010800 8009950: 40011800 .word 0x40011800 8009954: 40011400 .word 0x40011400 8009958: 40010c00 .word 0x40010c00 0800995c : /** * @brief Force PC12 (HEATER) as GPIO output via CRH/ODR, overriding UART5 MspInit. * CubeMX assigns PC12 to UART5_TX; on the board it drives the heater relay. */ static void Heater_PinForceOutput(void) { 800995c: b480 push {r7} 800995e: b083 sub sp, #12 8009960: af00 add r7, sp, #0 const uint32_t pin_cfg = GPIO_SPEED_FREQ_LOW; /* MODE=10, CNF=00: GP output PP, 2 MHz */ 8009962: 2302 movs r3, #2 8009964: 607b str r3, [r7, #4] __HAL_RCC_GPIOC_CLK_ENABLE(); 8009966: 4b0f ldr r3, [pc, #60] @ (80099a4 ) 8009968: 699b ldr r3, [r3, #24] 800996a: 4a0e ldr r2, [pc, #56] @ (80099a4 ) 800996c: f043 0310 orr.w r3, r3, #16 8009970: 6193 str r3, [r2, #24] 8009972: 4b0c ldr r3, [pc, #48] @ (80099a4 ) 8009974: 699b ldr r3, [r3, #24] 8009976: f003 0310 and.w r3, r3, #16 800997a: 603b str r3, [r7, #0] 800997c: 683b ldr r3, [r7, #0] MODIFY_REG(HEATER_GPIO_Port->CRH, 800997e: 4b0a ldr r3, [pc, #40] @ (80099a8 ) 8009980: 685b ldr r3, [r3, #4] 8009982: f423 2270 bic.w r2, r3, #983040 @ 0xf0000 8009986: 687b ldr r3, [r7, #4] 8009988: 041b lsls r3, r3, #16 800998a: 4907 ldr r1, [pc, #28] @ (80099a8 ) 800998c: 4313 orrs r3, r2 800998e: 604b str r3, [r1, #4] (GPIO_CRH_MODE12 | GPIO_CRH_CNF12), (pin_cfg << GPIO_CRH_MODE12_Pos)); HEATER_GPIO_Port->BSRR = (uint32_t)HEATER_Pin << 16U; 8009990: 4b05 ldr r3, [pc, #20] @ (80099a8 ) 8009992: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8009996: 611a str r2, [r3, #16] } 8009998: bf00 nop 800999a: 370c adds r7, #12 800999c: 46bd mov sp, r7 800999e: bc80 pop {r7} 80099a0: 4770 bx lr 80099a2: bf00 nop 80099a4: 40021000 .word 0x40021000 80099a8: 40011000 .word 0x40011000 080099ac : void Init_Peripheral(){ 80099ac: b580 push {r7, lr} 80099ae: af00 add r7, sp, #0 Heater_PinForceOutput(); 80099b0: f7ff ffd4 bl 800995c HAL_GPIO_WritePin(HEATER_GPIO_Port, HEATER_Pin, GPIO_PIN_RESET); 80099b4: 2200 movs r2, #0 80099b6: f44f 5180 mov.w r1, #4096 @ 0x1000 80099ba: 4818 ldr r0, [pc, #96] @ (8009a1c ) 80099bc: f007 f87f bl 8010abe HAL_ADCEx_Calibration_Start(&hadc1); 80099c0: 4817 ldr r0, [pc, #92] @ (8009a20 ) 80099c2: f005 f99d bl 800ed00 ADC_ScanStart(); 80099c6: f7ff fdaf bl 8009528 RELAY_Write(RELAY_AUX0, 0); 80099ca: 2100 movs r1, #0 80099cc: 2000 movs r0, #0 80099ce: f7ff fef3 bl 80097b8 RELAY_Write(RELAY_AUX1, 0); 80099d2: 2100 movs r1, #0 80099d4: 2001 movs r0, #1 80099d6: f7ff feef bl 80097b8 RELAY_Write(RELAY3, 0); 80099da: 2100 movs r1, #0 80099dc: 2002 movs r0, #2 80099de: f7ff feeb bl 80097b8 RELAY_Write(RELAY_DC, 0); 80099e2: 2100 movs r1, #0 80099e4: 2003 movs r0, #3 80099e6: f7ff fee7 bl 80097b8 RELAY_Write(RELAY_AC, 0); 80099ea: 2100 movs r1, #0 80099ec: 2004 movs r0, #4 80099ee: f7ff fee3 bl 80097b8 RELAY_Write(RELAY_CP, 0); 80099f2: 2100 movs r1, #0 80099f4: 2005 movs r0, #5 80099f6: f7ff fedf bl 80097b8 RELAY_Write(RELAY_CC, 0); 80099fa: 2100 movs r1, #0 80099fc: 2006 movs r0, #6 80099fe: f7ff fedb bl 80097b8 RELAY_Write(RELAY_DC1, 0); 8009a02: 2100 movs r1, #0 8009a04: 2007 movs r0, #7 8009a06: f7ff fed7 bl 80097b8 SMAFilter_Init(&conn_temp_adc_filter[0]); 8009a0a: 4806 ldr r0, [pc, #24] @ (8009a24 ) 8009a0c: f003 fd76 bl 800d4fc SMAFilter_Init(&conn_temp_adc_filter[1]); 8009a10: 4805 ldr r0, [pc, #20] @ (8009a28 ) 8009a12: f003 fd73 bl 800d4fc } 8009a16: bf00 nop 8009a18: bd80 pop {r7, pc} 8009a1a: bf00 nop 8009a1c: 40011000 .word 0x40011000 8009a20: 20000290 .word 0x20000290 8009a24: 2000030c .word 0x2000030c 8009a28: 20000334 .word 0x20000334 08009a2c : float pt1000_to_temperature(float resistance) { 8009a2c: b590 push {r4, r7, lr} 8009a2e: b087 sub sp, #28 8009a30: af00 add r7, sp, #0 8009a32: 6078 str r0, [r7, #4] // Константы для PT1000 const float R0 = 1000.0; // Сопротивление при 0 °C 8009a34: 4b0c ldr r3, [pc, #48] @ (8009a68 ) 8009a36: 617b str r3, [r7, #20] const float C_A = 3.9083E-3f; 8009a38: 4b0c ldr r3, [pc, #48] @ (8009a6c ) 8009a3a: 613b str r3, [r7, #16] float temperature = (resistance-R0) / ( R0 * C_A); 8009a3c: 6979 ldr r1, [r7, #20] 8009a3e: 6878 ldr r0, [r7, #4] 8009a40: f7ff f8e2 bl 8008c08 <__aeabi_fsub> 8009a44: 4603 mov r3, r0 8009a46: 461c mov r4, r3 8009a48: 6939 ldr r1, [r7, #16] 8009a4a: 6978 ldr r0, [r7, #20] 8009a4c: f7ff f9e6 bl 8008e1c <__aeabi_fmul> 8009a50: 4603 mov r3, r0 8009a52: 4619 mov r1, r3 8009a54: 4620 mov r0, r4 8009a56: f7ff fa95 bl 8008f84 <__aeabi_fdiv> 8009a5a: 4603 mov r3, r0 8009a5c: 60fb str r3, [r7, #12] return temperature; 8009a5e: 68fb ldr r3, [r7, #12] } 8009a60: 4618 mov r0, r3 8009a62: 371c adds r7, #28 8009a64: 46bd mov sp, r7 8009a66: bd90 pop {r4, r7, pc} 8009a68: 447a0000 .word 0x447a0000 8009a6c: 3b801132 .word 0x3b801132 08009a70 : float calculate_NTC_resistance(int adc_value, float Vref, float Vin, float R) { 8009a70: b5b0 push {r4, r5, r7, lr} 8009a72: b086 sub sp, #24 8009a74: af00 add r7, sp, #0 8009a76: 60f8 str r0, [r7, #12] 8009a78: 60b9 str r1, [r7, #8] 8009a7a: 607a str r2, [r7, #4] 8009a7c: 603b str r3, [r7, #0] // Преобразуем значение АЦП в выходное напряжение float Vout = (adc_value / 4095.0) * Vref; 8009a7e: 68f8 ldr r0, [r7, #12] 8009a80: f7fe fd2c bl 80084dc <__aeabi_i2d> 8009a84: a31c add r3, pc, #112 @ (adr r3, 8009af8 ) 8009a86: e9d3 2300 ldrd r2, r3, [r3] 8009a8a: f7fe febb bl 8008804 <__aeabi_ddiv> 8009a8e: 4602 mov r2, r0 8009a90: 460b mov r3, r1 8009a92: 4614 mov r4, r2 8009a94: 461d mov r5, r3 8009a96: 68b8 ldr r0, [r7, #8] 8009a98: f7fe fd32 bl 8008500 <__aeabi_f2d> 8009a9c: 4602 mov r2, r0 8009a9e: 460b mov r3, r1 8009aa0: 4620 mov r0, r4 8009aa2: 4629 mov r1, r5 8009aa4: f7fe fd84 bl 80085b0 <__aeabi_dmul> 8009aa8: 4602 mov r2, r0 8009aaa: 460b mov r3, r1 8009aac: 4610 mov r0, r2 8009aae: 4619 mov r1, r3 8009ab0: f7ff f856 bl 8008b60 <__aeabi_d2f> 8009ab4: 4603 mov r3, r0 8009ab6: 617b str r3, [r7, #20] // Проверяем, чтобы Vout не было равно Vin if (Vout >= Vin) { 8009ab8: 6879 ldr r1, [r7, #4] 8009aba: 6978 ldr r0, [r7, #20] 8009abc: f7ff fb60 bl 8009180 <__aeabi_fcmpge> 8009ac0: 4603 mov r3, r0 8009ac2: 2b00 cmp r3, #0 8009ac4: d001 beq.n 8009aca return -1; // Ошибка: Vout не может быть больше или равно Vin 8009ac6: 4b0e ldr r3, [pc, #56] @ (8009b00 ) 8009ac8: e010 b.n 8009aec } // Вычисляем сопротивление термистора float R_NTC = R * (Vout / (Vin - Vout)); 8009aca: 6979 ldr r1, [r7, #20] 8009acc: 6878 ldr r0, [r7, #4] 8009ace: f7ff f89b bl 8008c08 <__aeabi_fsub> 8009ad2: 4603 mov r3, r0 8009ad4: 4619 mov r1, r3 8009ad6: 6978 ldr r0, [r7, #20] 8009ad8: f7ff fa54 bl 8008f84 <__aeabi_fdiv> 8009adc: 4603 mov r3, r0 8009ade: 4619 mov r1, r3 8009ae0: 6838 ldr r0, [r7, #0] 8009ae2: f7ff f99b bl 8008e1c <__aeabi_fmul> 8009ae6: 4603 mov r3, r0 8009ae8: 613b str r3, [r7, #16] return R_NTC; 8009aea: 693b ldr r3, [r7, #16] } 8009aec: 4618 mov r0, r3 8009aee: 3718 adds r7, #24 8009af0: 46bd mov sp, r7 8009af2: bdb0 pop {r4, r5, r7, pc} 8009af4: f3af 8000 nop.w 8009af8: 00000000 .word 0x00000000 8009afc: 40affe00 .word 0x40affe00 8009b00: bf800000 .word 0xbf800000 08009b04 : int16_t CONN_ReadTemp(uint8_t ch){ 8009b04: b580 push {r7, lr} 8009b06: b088 sub sp, #32 8009b08: af00 add r7, sp, #0 8009b0a: 4603 mov r3, r0 8009b0c: 71fb strb r3, [r7, #7] uint32_t adcValue = 0u; 8009b0e: 2300 movs r3, #0 8009b10: 61fb str r3, [r7, #28] adcValue = ch ? adc_data.ntc2_raw : adc_data.ntc1_raw; 8009b12: 79fb ldrb r3, [r7, #7] 8009b14: 2b00 cmp r3, #0 8009b16: d003 beq.n 8009b20 8009b18: 4b1c ldr r3, [pc, #112] @ (8009b8c ) 8009b1a: 88db ldrh r3, [r3, #6] 8009b1c: b29b uxth r3, r3 8009b1e: e002 b.n 8009b26 8009b20: 4b1a ldr r3, [pc, #104] @ (8009b8c ) 8009b22: 889b ldrh r3, [r3, #4] 8009b24: b29b uxth r3, r3 8009b26: 61fb str r3, [r7, #28] int32_t adc_filtered = SMAFilter_Update(&conn_temp_adc_filter[ch ? 1u : 0u], (int32_t)adcValue); 8009b28: 79fb ldrb r3, [r7, #7] 8009b2a: 2b00 cmp r3, #0 8009b2c: d001 beq.n 8009b32 8009b2e: 2201 movs r2, #1 8009b30: e000 b.n 8009b34 8009b32: 2200 movs r2, #0 8009b34: 4613 mov r3, r2 8009b36: 009b lsls r3, r3, #2 8009b38: 4413 add r3, r2 8009b3a: 00db lsls r3, r3, #3 8009b3c: 4a14 ldr r2, [pc, #80] @ (8009b90 ) 8009b3e: 4413 add r3, r2 8009b40: 69fa ldr r2, [r7, #28] 8009b42: 4611 mov r1, r2 8009b44: 4618 mov r0, r3 8009b46: f003 fcfe bl 800d546 8009b4a: 61b8 str r0, [r7, #24] if((uint32_t)adc_filtered > 4000u) { 8009b4c: 69bb ldr r3, [r7, #24] 8009b4e: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 8009b52: d901 bls.n 8009b58 return 20; //Термодатчик не подключен 8009b54: 2314 movs r3, #20 8009b56: e015 b.n 8009b84 } float Vref = 3.3; // Напряжение опорное 8009b58: 4b0e ldr r3, [pc, #56] @ (8009b94 ) 8009b5a: 617b str r3, [r7, #20] float Vin = 5.0; // Входное напряжение 8009b5c: 4b0e ldr r3, [pc, #56] @ (8009b98 ) 8009b5e: 613b str r3, [r7, #16] float R = 1000; // Сопротивление резистора в Омах 8009b60: 4b0e ldr r3, [pc, #56] @ (8009b9c ) 8009b62: 60fb str r3, [r7, #12] float temp = pt1000_to_temperature(calculate_NTC_resistance((int)adc_filtered, Vref, Vin, R)); 8009b64: 68fb ldr r3, [r7, #12] 8009b66: 693a ldr r2, [r7, #16] 8009b68: 6979 ldr r1, [r7, #20] 8009b6a: 69b8 ldr r0, [r7, #24] 8009b6c: f7ff ff80 bl 8009a70 8009b70: 4603 mov r3, r0 8009b72: 4618 mov r0, r3 8009b74: f7ff ff5a bl 8009a2c 8009b78: 60b8 str r0, [r7, #8] return (int16_t)temp; 8009b7a: 68b8 ldr r0, [r7, #8] 8009b7c: f7ff fb14 bl 80091a8 <__aeabi_f2iz> 8009b80: 4603 mov r3, r0 8009b82: b21b sxth r3, r3 } 8009b84: 4618 mov r0, r3 8009b86: 3720 adds r7, #32 8009b88: 46bd mov sp, r7 8009b8a: bd80 pop {r7, pc} 8009b8c: 20000280 .word 0x20000280 8009b90: 2000030c .word 0x2000030c 8009b94: 40533333 .word 0x40533333 8009b98: 40a00000 .word 0x40a00000 8009b9c: 447a0000 .word 0x447a0000 08009ba0 : CAN_HandleTypeDef hcan1; CAN_HandleTypeDef hcan2; /* CAN1 init function */ void MX_CAN1_Init(void) { 8009ba0: b580 push {r7, lr} 8009ba2: af00 add r7, sp, #0 /* USER CODE END CAN1_Init 0 */ /* USER CODE BEGIN CAN1_Init 1 */ /* USER CODE END CAN1_Init 1 */ hcan1.Instance = CAN1; 8009ba4: 4b17 ldr r3, [pc, #92] @ (8009c04 ) 8009ba6: 4a18 ldr r2, [pc, #96] @ (8009c08 ) 8009ba8: 601a str r2, [r3, #0] hcan1.Init.Prescaler = 8; 8009baa: 4b16 ldr r3, [pc, #88] @ (8009c04 ) 8009bac: 2208 movs r2, #8 8009bae: 605a str r2, [r3, #4] hcan1.Init.Mode = CAN_MODE_NORMAL; 8009bb0: 4b14 ldr r3, [pc, #80] @ (8009c04 ) 8009bb2: 2200 movs r2, #0 8009bb4: 609a str r2, [r3, #8] hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; 8009bb6: 4b13 ldr r3, [pc, #76] @ (8009c04 ) 8009bb8: 2200 movs r2, #0 8009bba: 60da str r2, [r3, #12] hcan1.Init.TimeSeg1 = CAN_BS1_15TQ; 8009bbc: 4b11 ldr r3, [pc, #68] @ (8009c04 ) 8009bbe: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009bc2: 611a str r2, [r3, #16] hcan1.Init.TimeSeg2 = CAN_BS2_2TQ; 8009bc4: 4b0f ldr r3, [pc, #60] @ (8009c04 ) 8009bc6: f44f 1280 mov.w r2, #1048576 @ 0x100000 8009bca: 615a str r2, [r3, #20] hcan1.Init.TimeTriggeredMode = DISABLE; 8009bcc: 4b0d ldr r3, [pc, #52] @ (8009c04 ) 8009bce: 2200 movs r2, #0 8009bd0: 761a strb r2, [r3, #24] hcan1.Init.AutoBusOff = ENABLE; 8009bd2: 4b0c ldr r3, [pc, #48] @ (8009c04 ) 8009bd4: 2201 movs r2, #1 8009bd6: 765a strb r2, [r3, #25] hcan1.Init.AutoWakeUp = ENABLE; 8009bd8: 4b0a ldr r3, [pc, #40] @ (8009c04 ) 8009bda: 2201 movs r2, #1 8009bdc: 769a strb r2, [r3, #26] hcan1.Init.AutoRetransmission = ENABLE; 8009bde: 4b09 ldr r3, [pc, #36] @ (8009c04 ) 8009be0: 2201 movs r2, #1 8009be2: 76da strb r2, [r3, #27] hcan1.Init.ReceiveFifoLocked = DISABLE; 8009be4: 4b07 ldr r3, [pc, #28] @ (8009c04 ) 8009be6: 2200 movs r2, #0 8009be8: 771a strb r2, [r3, #28] hcan1.Init.TransmitFifoPriority = ENABLE; 8009bea: 4b06 ldr r3, [pc, #24] @ (8009c04 ) 8009bec: 2201 movs r2, #1 8009bee: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan1) != HAL_OK) 8009bf0: 4804 ldr r0, [pc, #16] @ (8009c04 ) 8009bf2: f005 f93c bl 800ee6e 8009bf6: 4603 mov r3, r0 8009bf8: 2b00 cmp r3, #0 8009bfa: d001 beq.n 8009c00 { Error_Handler(); 8009bfc: f001 f86a bl 800acd4 } /* USER CODE BEGIN CAN1_Init 2 */ /* USER CODE END CAN1_Init 2 */ } 8009c00: bf00 nop 8009c02: bd80 pop {r7, pc} 8009c04: 2000035c .word 0x2000035c 8009c08: 40006400 .word 0x40006400 08009c0c : /* CAN2 init function */ void MX_CAN2_Init(void) { 8009c0c: b580 push {r7, lr} 8009c0e: af00 add r7, sp, #0 /* USER CODE END CAN2_Init 0 */ /* USER CODE BEGIN CAN2_Init 1 */ /* USER CODE END CAN2_Init 1 */ hcan2.Instance = CAN2; 8009c10: 4b17 ldr r3, [pc, #92] @ (8009c70 ) 8009c12: 4a18 ldr r2, [pc, #96] @ (8009c74 ) 8009c14: 601a str r2, [r3, #0] hcan2.Init.Prescaler = 16; 8009c16: 4b16 ldr r3, [pc, #88] @ (8009c70 ) 8009c18: 2210 movs r2, #16 8009c1a: 605a str r2, [r3, #4] hcan2.Init.Mode = CAN_MODE_NORMAL; 8009c1c: 4b14 ldr r3, [pc, #80] @ (8009c70 ) 8009c1e: 2200 movs r2, #0 8009c20: 609a str r2, [r3, #8] hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; 8009c22: 4b13 ldr r3, [pc, #76] @ (8009c70 ) 8009c24: 2200 movs r2, #0 8009c26: 60da str r2, [r3, #12] hcan2.Init.TimeSeg1 = CAN_BS1_15TQ; 8009c28: 4b11 ldr r3, [pc, #68] @ (8009c70 ) 8009c2a: f44f 2260 mov.w r2, #917504 @ 0xe0000 8009c2e: 611a str r2, [r3, #16] hcan2.Init.TimeSeg2 = CAN_BS2_2TQ; 8009c30: 4b0f ldr r3, [pc, #60] @ (8009c70 ) 8009c32: f44f 1280 mov.w r2, #1048576 @ 0x100000 8009c36: 615a str r2, [r3, #20] hcan2.Init.TimeTriggeredMode = DISABLE; 8009c38: 4b0d ldr r3, [pc, #52] @ (8009c70 ) 8009c3a: 2200 movs r2, #0 8009c3c: 761a strb r2, [r3, #24] hcan2.Init.AutoBusOff = ENABLE; 8009c3e: 4b0c ldr r3, [pc, #48] @ (8009c70 ) 8009c40: 2201 movs r2, #1 8009c42: 765a strb r2, [r3, #25] hcan2.Init.AutoWakeUp = ENABLE; 8009c44: 4b0a ldr r3, [pc, #40] @ (8009c70 ) 8009c46: 2201 movs r2, #1 8009c48: 769a strb r2, [r3, #26] hcan2.Init.AutoRetransmission = ENABLE; 8009c4a: 4b09 ldr r3, [pc, #36] @ (8009c70 ) 8009c4c: 2201 movs r2, #1 8009c4e: 76da strb r2, [r3, #27] hcan2.Init.ReceiveFifoLocked = DISABLE; 8009c50: 4b07 ldr r3, [pc, #28] @ (8009c70 ) 8009c52: 2200 movs r2, #0 8009c54: 771a strb r2, [r3, #28] hcan2.Init.TransmitFifoPriority = ENABLE; 8009c56: 4b06 ldr r3, [pc, #24] @ (8009c70 ) 8009c58: 2201 movs r2, #1 8009c5a: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan2) != HAL_OK) 8009c5c: 4804 ldr r0, [pc, #16] @ (8009c70 ) 8009c5e: f005 f906 bl 800ee6e 8009c62: 4603 mov r3, r0 8009c64: 2b00 cmp r3, #0 8009c66: d001 beq.n 8009c6c { Error_Handler(); 8009c68: f001 f834 bl 800acd4 } /* USER CODE BEGIN CAN2_Init 2 */ /* USER CODE END CAN2_Init 2 */ } 8009c6c: bf00 nop 8009c6e: bd80 pop {r7, pc} 8009c70: 20000384 .word 0x20000384 8009c74: 40006800 .word 0x40006800 08009c78 : static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0; void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) { 8009c78: b580 push {r7, lr} 8009c7a: b08e sub sp, #56 @ 0x38 8009c7c: af00 add r7, sp, #0 8009c7e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8009c80: f107 0320 add.w r3, r7, #32 8009c84: 2200 movs r2, #0 8009c86: 601a str r2, [r3, #0] 8009c88: 605a str r2, [r3, #4] 8009c8a: 609a str r2, [r3, #8] 8009c8c: 60da str r2, [r3, #12] if(canHandle->Instance==CAN1) 8009c8e: 687b ldr r3, [r7, #4] 8009c90: 681b ldr r3, [r3, #0] 8009c92: 4a61 ldr r2, [pc, #388] @ (8009e18 ) 8009c94: 4293 cmp r3, r2 8009c96: d153 bne.n 8009d40 { /* USER CODE BEGIN CAN1_MspInit 0 */ /* USER CODE END CAN1_MspInit 0 */ /* CAN1 clock enable */ HAL_RCC_CAN1_CLK_ENABLED++; 8009c98: 4b60 ldr r3, [pc, #384] @ (8009e1c ) 8009c9a: 681b ldr r3, [r3, #0] 8009c9c: 3301 adds r3, #1 8009c9e: 4a5f ldr r2, [pc, #380] @ (8009e1c ) 8009ca0: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009ca2: 4b5e ldr r3, [pc, #376] @ (8009e1c ) 8009ca4: 681b ldr r3, [r3, #0] 8009ca6: 2b01 cmp r3, #1 8009ca8: d10b bne.n 8009cc2 __HAL_RCC_CAN1_CLK_ENABLE(); 8009caa: 4b5d ldr r3, [pc, #372] @ (8009e20 ) 8009cac: 69db ldr r3, [r3, #28] 8009cae: 4a5c ldr r2, [pc, #368] @ (8009e20 ) 8009cb0: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009cb4: 61d3 str r3, [r2, #28] 8009cb6: 4b5a ldr r3, [pc, #360] @ (8009e20 ) 8009cb8: 69db ldr r3, [r3, #28] 8009cba: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009cbe: 61fb str r3, [r7, #28] 8009cc0: 69fb ldr r3, [r7, #28] } __HAL_RCC_GPIOD_CLK_ENABLE(); 8009cc2: 4b57 ldr r3, [pc, #348] @ (8009e20 ) 8009cc4: 699b ldr r3, [r3, #24] 8009cc6: 4a56 ldr r2, [pc, #344] @ (8009e20 ) 8009cc8: f043 0320 orr.w r3, r3, #32 8009ccc: 6193 str r3, [r2, #24] 8009cce: 4b54 ldr r3, [pc, #336] @ (8009e20 ) 8009cd0: 699b ldr r3, [r3, #24] 8009cd2: f003 0320 and.w r3, r3, #32 8009cd6: 61bb str r3, [r7, #24] 8009cd8: 69bb ldr r3, [r7, #24] /**CAN1 GPIO Configuration PD0 ------> CAN1_RX PD1 ------> CAN1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0; 8009cda: 2301 movs r3, #1 8009cdc: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009cde: 2300 movs r3, #0 8009ce0: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009ce2: 2300 movs r3, #0 8009ce4: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009ce6: f107 0320 add.w r3, r7, #32 8009cea: 4619 mov r1, r3 8009cec: 484d ldr r0, [pc, #308] @ (8009e24 ) 8009cee: f006 fd4b bl 8010788 GPIO_InitStruct.Pin = GPIO_PIN_1; 8009cf2: 2302 movs r3, #2 8009cf4: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009cf6: 2302 movs r3, #2 8009cf8: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009cfa: 2303 movs r3, #3 8009cfc: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8009cfe: f107 0320 add.w r3, r7, #32 8009d02: 4619 mov r1, r3 8009d04: 4847 ldr r0, [pc, #284] @ (8009e24 ) 8009d06: f006 fd3f bl 8010788 __HAL_AFIO_REMAP_CAN1_3(); 8009d0a: 4b47 ldr r3, [pc, #284] @ (8009e28 ) 8009d0c: 685b ldr r3, [r3, #4] 8009d0e: 633b str r3, [r7, #48] @ 0x30 8009d10: 6b3b ldr r3, [r7, #48] @ 0x30 8009d12: f423 43c0 bic.w r3, r3, #24576 @ 0x6000 8009d16: 633b str r3, [r7, #48] @ 0x30 8009d18: 6b3b ldr r3, [r7, #48] @ 0x30 8009d1a: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009d1e: 633b str r3, [r7, #48] @ 0x30 8009d20: 6b3b ldr r3, [r7, #48] @ 0x30 8009d22: f443 43c0 orr.w r3, r3, #24576 @ 0x6000 8009d26: 633b str r3, [r7, #48] @ 0x30 8009d28: 4a3f ldr r2, [pc, #252] @ (8009e28 ) 8009d2a: 6b3b ldr r3, [r7, #48] @ 0x30 8009d2c: 6053 str r3, [r2, #4] /* CAN1 interrupt Init */ HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 3, 0); 8009d2e: 2200 movs r2, #0 8009d30: 2103 movs r1, #3 8009d32: 2014 movs r0, #20 8009d34: f006 f847 bl 800fdc6 HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn); 8009d38: 2014 movs r0, #20 8009d3a: f006 f860 bl 800fdfe HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); /* USER CODE BEGIN CAN2_MspInit 1 */ /* USER CODE END CAN2_MspInit 1 */ } } 8009d3e: e067 b.n 8009e10 else if(canHandle->Instance==CAN2) 8009d40: 687b ldr r3, [r7, #4] 8009d42: 681b ldr r3, [r3, #0] 8009d44: 4a39 ldr r2, [pc, #228] @ (8009e2c ) 8009d46: 4293 cmp r3, r2 8009d48: d162 bne.n 8009e10 __HAL_RCC_CAN2_CLK_ENABLE(); 8009d4a: 4b35 ldr r3, [pc, #212] @ (8009e20 ) 8009d4c: 69db ldr r3, [r3, #28] 8009d4e: 4a34 ldr r2, [pc, #208] @ (8009e20 ) 8009d50: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 8009d54: 61d3 str r3, [r2, #28] 8009d56: 4b32 ldr r3, [pc, #200] @ (8009e20 ) 8009d58: 69db ldr r3, [r3, #28] 8009d5a: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8009d5e: 617b str r3, [r7, #20] 8009d60: 697b ldr r3, [r7, #20] HAL_RCC_CAN1_CLK_ENABLED++; 8009d62: 4b2e ldr r3, [pc, #184] @ (8009e1c ) 8009d64: 681b ldr r3, [r3, #0] 8009d66: 3301 adds r3, #1 8009d68: 4a2c ldr r2, [pc, #176] @ (8009e1c ) 8009d6a: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8009d6c: 4b2b ldr r3, [pc, #172] @ (8009e1c ) 8009d6e: 681b ldr r3, [r3, #0] 8009d70: 2b01 cmp r3, #1 8009d72: d10b bne.n 8009d8c __HAL_RCC_CAN1_CLK_ENABLE(); 8009d74: 4b2a ldr r3, [pc, #168] @ (8009e20 ) 8009d76: 69db ldr r3, [r3, #28] 8009d78: 4a29 ldr r2, [pc, #164] @ (8009e20 ) 8009d7a: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8009d7e: 61d3 str r3, [r2, #28] 8009d80: 4b27 ldr r3, [pc, #156] @ (8009e20 ) 8009d82: 69db ldr r3, [r3, #28] 8009d84: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8009d88: 613b str r3, [r7, #16] 8009d8a: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8009d8c: 4b24 ldr r3, [pc, #144] @ (8009e20 ) 8009d8e: 699b ldr r3, [r3, #24] 8009d90: 4a23 ldr r2, [pc, #140] @ (8009e20 ) 8009d92: f043 0308 orr.w r3, r3, #8 8009d96: 6193 str r3, [r2, #24] 8009d98: 4b21 ldr r3, [pc, #132] @ (8009e20 ) 8009d9a: 699b ldr r3, [r3, #24] 8009d9c: f003 0308 and.w r3, r3, #8 8009da0: 60fb str r3, [r7, #12] 8009da2: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_5; 8009da4: 2320 movs r3, #32 8009da6: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8009da8: 2300 movs r3, #0 8009daa: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009dac: 2300 movs r3, #0 8009dae: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009db0: f107 0320 add.w r3, r7, #32 8009db4: 4619 mov r1, r3 8009db6: 481e ldr r0, [pc, #120] @ (8009e30 ) 8009db8: f006 fce6 bl 8010788 GPIO_InitStruct.Pin = GPIO_PIN_6; 8009dbc: 2340 movs r3, #64 @ 0x40 8009dbe: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009dc0: 2302 movs r3, #2 8009dc2: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8009dc4: 2303 movs r3, #3 8009dc6: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8009dc8: f107 0320 add.w r3, r7, #32 8009dcc: 4619 mov r1, r3 8009dce: 4818 ldr r0, [pc, #96] @ (8009e30 ) 8009dd0: f006 fcda bl 8010788 __HAL_AFIO_REMAP_CAN2_ENABLE(); 8009dd4: 4b14 ldr r3, [pc, #80] @ (8009e28 ) 8009dd6: 685b ldr r3, [r3, #4] 8009dd8: 637b str r3, [r7, #52] @ 0x34 8009dda: 6b7b ldr r3, [r7, #52] @ 0x34 8009ddc: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 8009de0: 637b str r3, [r7, #52] @ 0x34 8009de2: 6b7b ldr r3, [r7, #52] @ 0x34 8009de4: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8009de8: 637b str r3, [r7, #52] @ 0x34 8009dea: 4a0f ldr r2, [pc, #60] @ (8009e28 ) 8009dec: 6b7b ldr r3, [r7, #52] @ 0x34 8009dee: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(CAN2_TX_IRQn, 0, 0); 8009df0: 2200 movs r2, #0 8009df2: 2100 movs r1, #0 8009df4: 203f movs r0, #63 @ 0x3f 8009df6: f005 ffe6 bl 800fdc6 HAL_NVIC_EnableIRQ(CAN2_TX_IRQn); 8009dfa: 203f movs r0, #63 @ 0x3f 8009dfc: f005 ffff bl 800fdfe HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 3, 0); 8009e00: 2200 movs r2, #0 8009e02: 2103 movs r1, #3 8009e04: 2041 movs r0, #65 @ 0x41 8009e06: f005 ffde bl 800fdc6 HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); 8009e0a: 2041 movs r0, #65 @ 0x41 8009e0c: f005 fff7 bl 800fdfe } 8009e10: bf00 nop 8009e12: 3738 adds r7, #56 @ 0x38 8009e14: 46bd mov sp, r7 8009e16: bd80 pop {r7, pc} 8009e18: 40006400 .word 0x40006400 8009e1c: 200003ac .word 0x200003ac 8009e20: 40021000 .word 0x40021000 8009e24: 40011400 .word 0x40011400 8009e28: 40010000 .word 0x40010000 8009e2c: 40006800 .word 0x40006800 8009e30: 40010c00 .word 0x40010c00 08009e34 : #include "psu_control.h" ChargingConnector_t CONN; CONN_State_t connectorState; void CONN_Init(){ 8009e34: b480 push {r7} 8009e36: af00 add r7, sp, #0 CONN.connControl = CMD_NONE; 8009e38: 4b08 ldr r3, [pc, #32] @ (8009e5c ) 8009e3a: 2200 movs r2, #0 8009e3c: 701a strb r2, [r3, #0] CONN.connState = Unknown; 8009e3e: 4b07 ldr r3, [pc, #28] @ (8009e5c ) 8009e40: 2200 movs r2, #0 8009e42: 705a strb r2, [r3, #1] CONN.RequestedVoltage = PSU_MIN_VOLTAGE; 8009e44: 4b05 ldr r3, [pc, #20] @ (8009e5c ) 8009e46: 2200 movs r2, #0 8009e48: f062 0269 orn r2, r2, #105 @ 0x69 8009e4c: 73da strb r2, [r3, #15] 8009e4e: 2200 movs r2, #0 8009e50: 741a strb r2, [r3, #16] } 8009e52: bf00 nop 8009e54: 46bd mov sp, r7 8009e56: bc80 pop {r7} 8009e58: 4770 bx lr 8009e5a: bf00 nop 8009e5c: 200003b0 .word 0x200003b0 08009e60 : void CONN_Loop(){ 8009e60: b580 push {r7, lr} 8009e62: af00 add r7, sp, #0 static CONN_State_t last_connState = Unknown; if(last_connState != CONN.connState){ 8009e64: 4b1f ldr r3, [pc, #124] @ (8009ee4 ) 8009e66: 785a ldrb r2, [r3, #1] 8009e68: 4b1f ldr r3, [pc, #124] @ (8009ee8 ) 8009e6a: 781b ldrb r3, [r3, #0] 8009e6c: 429a cmp r2, r3 8009e6e: d006 beq.n 8009e7e last_connState = CONN.connState; 8009e70: 4b1c ldr r3, [pc, #112] @ (8009ee4 ) 8009e72: 785a ldrb r2, [r3, #1] 8009e74: 4b1c ldr r3, [pc, #112] @ (8009ee8 ) 8009e76: 701a strb r2, [r3, #0] CONN.connControl = CMD_NONE; 8009e78: 4b1a ldr r3, [pc, #104] @ (8009ee4 ) 8009e7a: 2200 movs r2, #0 8009e7c: 701a strb r2, [r3, #0] } if (FireAlarm_IsLatched()) { 8009e7e: f000 fbe7 bl 800a650 8009e82: 4603 mov r3, r0 8009e84: 2b00 cmp r3, #0 8009e86: d003 beq.n 8009e90 CONN.chargingError = CONN_ERR_FIRE_ALARM; 8009e88: 4b16 ldr r3, [pc, #88] @ (8009ee4 ) 8009e8a: 220b movs r2, #11 8009e8c: 775a strb r2, [r3, #29] 8009e8e: e016 b.n 8009ebe } else if(PSU0.cont_fault){ 8009e90: 4b16 ldr r3, [pc, #88] @ (8009eec ) 8009e92: 7b1b ldrb r3, [r3, #12] 8009e94: 2b00 cmp r3, #0 8009e96: d003 beq.n 8009ea0 CONN.chargingError = CONN_ERR_CONTACTOR; 8009e98: 4b12 ldr r3, [pc, #72] @ (8009ee4 ) 8009e9a: 2207 movs r2, #7 8009e9c: 775a strb r2, [r3, #29] 8009e9e: e00e b.n 8009ebe } else if(PSU0.psu_fault){ 8009ea0: 4b12 ldr r3, [pc, #72] @ (8009eec ) 8009ea2: 7b5b ldrb r3, [r3, #13] 8009ea4: 2b00 cmp r3, #0 8009ea6: d003 beq.n 8009eb0 CONN.chargingError = CONN_ERR_PSU_FAULT; 8009ea8: 4b0e ldr r3, [pc, #56] @ (8009ee4 ) 8009eaa: 220a movs r2, #10 8009eac: 775a strb r2, [r3, #29] 8009eae: e006 b.n 8009ebe }else if (CONN.EvConnected == 0){ 8009eb0: 4b0c ldr r3, [pc, #48] @ (8009ee4 ) 8009eb2: 7f9b ldrb r3, [r3, #30] 8009eb4: 2b00 cmp r3, #0 8009eb6: d102 bne.n 8009ebe CONN.chargingError = CONN_NO_ERROR; 8009eb8: 4b0a ldr r3, [pc, #40] @ (8009ee4 ) 8009eba: 2200 movs r2, #0 8009ebc: 775a strb r2, [r3, #29] } if(ED_TraceWarning(CONN.chargingError, 0)) { 8009ebe: 4b09 ldr r3, [pc, #36] @ (8009ee4 ) 8009ec0: 7f5b ldrb r3, [r3, #29] 8009ec2: 2100 movs r1, #0 8009ec4: 4618 mov r0, r3 8009ec6: f000 fd47 bl 800a958 8009eca: 4603 mov r3, r0 8009ecc: 2b00 cmp r3, #0 8009ece: d006 beq.n 8009ede log_printf(LOG_WARN, "CONN0 Error: %d\n", (int)CONN.chargingError); 8009ed0: 4b04 ldr r3, [pc, #16] @ (8009ee4 ) 8009ed2: 7f5b ldrb r3, [r3, #29] 8009ed4: 461a mov r2, r3 8009ed6: 4906 ldr r1, [pc, #24] @ (8009ef0 ) 8009ed8: 2005 movs r0, #5 8009eda: f000 fb45 bl 800a568 } } 8009ede: bf00 nop 8009ee0: bd80 pop {r7, pc} 8009ee2: bf00 nop 8009ee4: 200003b0 .word 0x200003b0 8009ee8: 200003d0 .word 0x200003d0 8009eec: 20000904 .word 0x20000904 8009ef0: 08016f58 .word 0x08016f58 08009ef4 : void CONN_SetState(CONN_State_t state){ 8009ef4: b580 push {r7, lr} 8009ef6: b082 sub sp, #8 8009ef8: af00 add r7, sp, #0 8009efa: 4603 mov r3, r0 8009efc: 71fb strb r3, [r7, #7] if (connectorState == state) { 8009efe: 4b41 ldr r3, [pc, #260] @ (800a004 ) 8009f00: 781b ldrb r3, [r3, #0] 8009f02: 79fa ldrb r2, [r7, #7] 8009f04: 429a cmp r2, r3 8009f06: d103 bne.n 8009f10 CONN.connState = state; 8009f08: 4a3f ldr r2, [pc, #252] @ (800a008 ) 8009f0a: 79fb ldrb r3, [r7, #7] 8009f0c: 7053 strb r3, [r2, #1] return; 8009f0e: e075 b.n 8009ffc } connectorState = state; 8009f10: 4a3c ldr r2, [pc, #240] @ (800a004 ) 8009f12: 79fb ldrb r3, [r7, #7] 8009f14: 7013 strb r3, [r2, #0] if(connectorState == Unknown) log_printf(LOG_INFO, "Connector: Unknown\n"); 8009f16: 4b3b ldr r3, [pc, #236] @ (800a004 ) 8009f18: 781b ldrb r3, [r3, #0] 8009f1a: 2b00 cmp r3, #0 8009f1c: d103 bne.n 8009f26 8009f1e: 493b ldr r1, [pc, #236] @ (800a00c ) 8009f20: 2007 movs r0, #7 8009f22: f000 fb21 bl 800a568 if(connectorState == Unplugged) log_printf(LOG_INFO, "Connector: Unplugged\n"); 8009f26: 4b37 ldr r3, [pc, #220] @ (800a004 ) 8009f28: 781b ldrb r3, [r3, #0] 8009f2a: 2b01 cmp r3, #1 8009f2c: d103 bne.n 8009f36 8009f2e: 4938 ldr r1, [pc, #224] @ (800a010 ) 8009f30: 2007 movs r0, #7 8009f32: f000 fb19 bl 800a568 if(connectorState == Disabled) log_printf(LOG_INFO, "Connector: Disabled\n"); 8009f36: 4b33 ldr r3, [pc, #204] @ (800a004 ) 8009f38: 781b ldrb r3, [r3, #0] 8009f3a: 2b02 cmp r3, #2 8009f3c: d103 bne.n 8009f46 8009f3e: 4935 ldr r1, [pc, #212] @ (800a014 ) 8009f40: 2007 movs r0, #7 8009f42: f000 fb11 bl 800a568 if(connectorState == Preparing) log_printf(LOG_INFO, "Connector: Preparing\n"); 8009f46: 4b2f ldr r3, [pc, #188] @ (800a004 ) 8009f48: 781b ldrb r3, [r3, #0] 8009f4a: 2b03 cmp r3, #3 8009f4c: d103 bne.n 8009f56 8009f4e: 4932 ldr r1, [pc, #200] @ (800a018 ) 8009f50: 2007 movs r0, #7 8009f52: f000 fb09 bl 800a568 if(connectorState == AuthRequired) log_printf(LOG_INFO, "Connector: AuthRequired\n"); 8009f56: 4b2b ldr r3, [pc, #172] @ (800a004 ) 8009f58: 781b ldrb r3, [r3, #0] 8009f5a: 2b04 cmp r3, #4 8009f5c: d103 bne.n 8009f66 8009f5e: 492f ldr r1, [pc, #188] @ (800a01c ) 8009f60: 2007 movs r0, #7 8009f62: f000 fb01 bl 800a568 if(connectorState == WaitingForEnergy) log_printf(LOG_INFO, "Connector: WaitingForEnergy\n"); 8009f66: 4b27 ldr r3, [pc, #156] @ (800a004 ) 8009f68: 781b ldrb r3, [r3, #0] 8009f6a: 2b05 cmp r3, #5 8009f6c: d103 bne.n 8009f76 8009f6e: 492c ldr r1, [pc, #176] @ (800a020 ) 8009f70: 2007 movs r0, #7 8009f72: f000 faf9 bl 800a568 if(connectorState == ChargingPausedEV) log_printf(LOG_INFO, "Connector: ChargingPausedEV\n"); 8009f76: 4b23 ldr r3, [pc, #140] @ (800a004 ) 8009f78: 781b ldrb r3, [r3, #0] 8009f7a: 2b06 cmp r3, #6 8009f7c: d103 bne.n 8009f86 8009f7e: 4929 ldr r1, [pc, #164] @ (800a024 ) 8009f80: 2007 movs r0, #7 8009f82: f000 faf1 bl 800a568 if(connectorState == ChargingPausedEVSE) log_printf(LOG_INFO, "Connector: ChargingPausedEVSE\n"); 8009f86: 4b1f ldr r3, [pc, #124] @ (800a004 ) 8009f88: 781b ldrb r3, [r3, #0] 8009f8a: 2b07 cmp r3, #7 8009f8c: d103 bne.n 8009f96 8009f8e: 4926 ldr r1, [pc, #152] @ (800a028 ) 8009f90: 2007 movs r0, #7 8009f92: f000 fae9 bl 800a568 if(connectorState == Charging) log_printf(LOG_INFO, "Connector: Charging\n"); 8009f96: 4b1b ldr r3, [pc, #108] @ (800a004 ) 8009f98: 781b ldrb r3, [r3, #0] 8009f9a: 2b08 cmp r3, #8 8009f9c: d103 bne.n 8009fa6 8009f9e: 4923 ldr r1, [pc, #140] @ (800a02c ) 8009fa0: 2007 movs r0, #7 8009fa2: f000 fae1 bl 800a568 if(connectorState == AuthTimeout) log_printf(LOG_INFO, "Connector: AuthTimeout\n"); 8009fa6: 4b17 ldr r3, [pc, #92] @ (800a004 ) 8009fa8: 781b ldrb r3, [r3, #0] 8009faa: 2b09 cmp r3, #9 8009fac: d103 bne.n 8009fb6 8009fae: 4920 ldr r1, [pc, #128] @ (800a030 ) 8009fb0: 2007 movs r0, #7 8009fb2: f000 fad9 bl 800a568 if(connectorState == Finished) log_printf(LOG_INFO, "Connector: Finished\n"); 8009fb6: 4b13 ldr r3, [pc, #76] @ (800a004 ) 8009fb8: 781b ldrb r3, [r3, #0] 8009fba: 2b0a cmp r3, #10 8009fbc: d103 bne.n 8009fc6 8009fbe: 491d ldr r1, [pc, #116] @ (800a034 ) 8009fc0: 2007 movs r0, #7 8009fc2: f000 fad1 bl 800a568 if(connectorState == FinishedEVSE) log_printf(LOG_INFO, "Connector: FinishedEVSE\n"); 8009fc6: 4b0f ldr r3, [pc, #60] @ (800a004 ) 8009fc8: 781b ldrb r3, [r3, #0] 8009fca: 2b0b cmp r3, #11 8009fcc: d103 bne.n 8009fd6 8009fce: 491a ldr r1, [pc, #104] @ (800a038 ) 8009fd0: 2007 movs r0, #7 8009fd2: f000 fac9 bl 800a568 if(connectorState == FinishedEV) log_printf(LOG_INFO, "Connector: FinishedEV\n"); 8009fd6: 4b0b ldr r3, [pc, #44] @ (800a004 ) 8009fd8: 781b ldrb r3, [r3, #0] 8009fda: 2b0c cmp r3, #12 8009fdc: d103 bne.n 8009fe6 8009fde: 4917 ldr r1, [pc, #92] @ (800a03c ) 8009fe0: 2007 movs r0, #7 8009fe2: f000 fac1 bl 800a568 if(connectorState == Replugging) log_printf(LOG_INFO, "Connector: Replugging\n"); 8009fe6: 4b07 ldr r3, [pc, #28] @ (800a004 ) 8009fe8: 781b ldrb r3, [r3, #0] 8009fea: 2b0d cmp r3, #13 8009fec: d103 bne.n 8009ff6 8009fee: 4914 ldr r1, [pc, #80] @ (800a040 ) 8009ff0: 2007 movs r0, #7 8009ff2: f000 fab9 bl 800a568 CONN.connState = state; 8009ff6: 4a04 ldr r2, [pc, #16] @ (800a008 ) 8009ff8: 79fb ldrb r3, [r7, #7] 8009ffa: 7053 strb r3, [r2, #1] } 8009ffc: 3708 adds r7, #8 8009ffe: 46bd mov sp, r7 800a000: bd80 pop {r7, pc} 800a002: bf00 nop 800a004: 200003cf .word 0x200003cf 800a008: 200003b0 .word 0x200003b0 800a00c: 08016f6c .word 0x08016f6c 800a010: 08016f80 .word 0x08016f80 800a014: 08016f98 .word 0x08016f98 800a018: 08016fb0 .word 0x08016fb0 800a01c: 08016fc8 .word 0x08016fc8 800a020: 08016fe4 .word 0x08016fe4 800a024: 08017004 .word 0x08017004 800a028: 08017024 .word 0x08017024 800a02c: 08017044 .word 0x08017044 800a030: 0801705c .word 0x0801705c 800a034: 08017074 .word 0x08017074 800a038: 0801708c .word 0x0801708c 800a03c: 080170a8 .word 0x080170a8 800a040: 080170c0 .word 0x080170c0 0800a044 : CP_State_t cp_state_buffer = EV_STATE_ACQUIRING; #define VREFINT_CAL_ADDR ((uint16_t*)0x1FFFF7BA) // для STM32F1! static int32_t CP_ReadVoltageMv(void) { 800a044: b480 push {r7} 800a046: b087 sub sp, #28 800a048: af00 add r7, sp, #0 uint32_t adc_cp = adc_data.cp_raw; 800a04a: 4b13 ldr r3, [pc, #76] @ (800a098 ) 800a04c: 885b ldrh r3, [r3, #2] 800a04e: b29b uxth r3, r3 800a050: 617b str r3, [r7, #20] uint32_t adc_vref = adc_data.vrefint_raw; // нужно измерять! 800a052: 4b11 ldr r3, [pc, #68] @ (800a098 ) 800a054: 895b ldrh r3, [r3, #10] 800a056: b29b uxth r3, r3 800a058: 613b str r3, [r7, #16] // VREFINT в мВ (берётся из даташита или калибровки MCU) const int32_t VREFINT_MV = 1210; 800a05a: f240 43ba movw r3, #1210 @ 0x4ba 800a05e: 60fb str r3, [r7, #12] // напряжение на входе АЦП int32_t v_adc_mv = (adc_cp * VREFINT_MV) / adc_vref; 800a060: 68fb ldr r3, [r7, #12] 800a062: 697a ldr r2, [r7, #20] 800a064: fb03 f202 mul.w r2, r3, r2 800a068: 693b ldr r3, [r7, #16] 800a06a: fbb2 f3f3 udiv r3, r2, r3 800a06e: 60bb str r3, [r7, #8] // дальше твоя формула int32_t v_out_mv = ((v_adc_mv - 1723) * 7704) / 1000; 800a070: 68bb ldr r3, [r7, #8] 800a072: f2a3 63bb subw r3, r3, #1723 @ 0x6bb 800a076: f641 6218 movw r2, #7704 @ 0x1e18 800a07a: fb02 f303 mul.w r3, r2, r3 800a07e: 4a07 ldr r2, [pc, #28] @ (800a09c ) 800a080: fb82 1203 smull r1, r2, r2, r3 800a084: 1192 asrs r2, r2, #6 800a086: 17db asrs r3, r3, #31 800a088: 1ad3 subs r3, r2, r3 800a08a: 607b str r3, [r7, #4] return v_out_mv; 800a08c: 687b ldr r3, [r7, #4] } 800a08e: 4618 mov r0, r3 800a090: 371c adds r7, #28 800a092: 46bd mov sp, r7 800a094: bc80 pop {r7} 800a096: 4770 bx lr 800a098: 20000280 .word 0x20000280 800a09c: 10624dd3 .word 0x10624dd3 0800a0a0 : void CP_Init(void) { 800a0a0: b580 push {r7, lr} 800a0a2: af00 add r7, sp, #0 /* TIM3_CH2 (PA7): set 1kHz PWM like original CCS logic. */ htim3.Instance->PSC = 160 - 1; 800a0a4: 4b0e ldr r3, [pc, #56] @ (800a0e0 ) 800a0a6: 681b ldr r3, [r3, #0] 800a0a8: 229f movs r2, #159 @ 0x9f 800a0aa: 629a str r2, [r3, #40] @ 0x28 htim3.Instance->ARR = MAX_DUTY - 1; 800a0ac: 4b0c ldr r3, [pc, #48] @ (800a0e0 ) 800a0ae: 681b ldr r3, [r3, #0] 800a0b0: f240 12c1 movw r2, #449 @ 0x1c1 800a0b4: 62da str r2, [r3, #44] @ 0x2c #if DUTY_INVERT == 0 htim3.Instance->CCR2 = MAX_DUTY; 800a0b6: 4b0a ldr r3, [pc, #40] @ (800a0e0 ) 800a0b8: 681b ldr r3, [r3, #0] 800a0ba: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a0be: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = MAX_DUTY + 5; 800a0c0: 4b07 ldr r3, [pc, #28] @ (800a0e0 ) 800a0c2: 681b ldr r3, [r3, #0] 800a0c4: f240 12c7 movw r2, #455 @ 0x1c7 800a0c8: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = 0; htim3.Instance->CCR1 = 0; #endif HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_2); 800a0ca: 2104 movs r1, #4 800a0cc: 4804 ldr r0, [pc, #16] @ (800a0e0 ) 800a0ce: f008 f82d bl 801212c HAL_TIM_OC_Start(&htim3, TIM_CHANNEL_1); 800a0d2: 2100 movs r1, #0 800a0d4: 4802 ldr r0, [pc, #8] @ (800a0e0 ) 800a0d6: f007 ff27 bl 8011f28 } 800a0da: bf00 nop 800a0dc: bd80 pop {r7, pc} 800a0de: bf00 nop 800a0e0: 200011c8 .word 0x200011c8 0800a0e4 : void CP_SetDuty(uint8_t percentage) { 800a0e4: b480 push {r7} 800a0e6: b085 sub sp, #20 800a0e8: af00 add r7, sp, #0 800a0ea: 4603 mov r3, r0 800a0ec: 71fb strb r3, [r7, #7] uint32_t pwmduty = MAX_DUTY * percentage / 100; 800a0ee: 79fb ldrb r3, [r7, #7] 800a0f0: f44f 72e1 mov.w r2, #450 @ 0x1c2 800a0f4: fb02 f303 mul.w r3, r2, r3 800a0f8: 4a0b ldr r2, [pc, #44] @ (800a128 ) 800a0fa: fb82 1203 smull r1, r2, r2, r3 800a0fe: 1152 asrs r2, r2, #5 800a100: 17db asrs r3, r3, #31 800a102: 1ad3 subs r3, r2, r3 800a104: 60fb str r3, [r7, #12] cp_duty = percentage; 800a106: 4a09 ldr r2, [pc, #36] @ (800a12c ) 800a108: 79fb ldrb r3, [r7, #7] 800a10a: 7013 strb r3, [r2, #0] #if DUTY_INVERT == 0 htim3.Instance->CCR2 = pwmduty; 800a10c: 4b08 ldr r3, [pc, #32] @ (800a130 ) 800a10e: 681b ldr r3, [r3, #0] 800a110: 68fa ldr r2, [r7, #12] 800a112: 639a str r2, [r3, #56] @ 0x38 htim3.Instance->CCR1 = 0 + 1; 800a114: 4b06 ldr r3, [pc, #24] @ (800a130 ) 800a116: 681b ldr r3, [r3, #0] 800a118: 2201 movs r2, #1 800a11a: 635a str r2, [r3, #52] @ 0x34 #else htim3.Instance->CCR2 = MAX_DUTY - pwmduty; htim3.Instance->CCR1 = MAX_DUTY - pwmduty + 5; #endif } 800a11c: bf00 nop 800a11e: 3714 adds r7, #20 800a120: 46bd mov sp, r7 800a122: bc80 pop {r7} 800a124: 4770 bx lr 800a126: bf00 nop 800a128: 51eb851f .word 0x51eb851f 800a12c: 200003d8 .word 0x200003d8 800a130: 200011c8 .word 0x200011c8 0800a134 : uint8_t CP_GetDuty(void) { 800a134: b480 push {r7} 800a136: af00 add r7, sp, #0 return cp_duty; 800a138: 4b02 ldr r3, [pc, #8] @ (800a144 ) 800a13a: 781b ldrb r3, [r3, #0] } 800a13c: 4618 mov r0, r3 800a13e: 46bd mov sp, r7 800a140: bc80 pop {r7} 800a142: 4770 bx lr 800a144: 200003d8 .word 0x200003d8 0800a148 : int32_t CP_GetVoltage(void) { 800a148: b580 push {r7, lr} 800a14a: af00 add r7, sp, #0 cp_voltage_mv = CP_ReadVoltageMv(); 800a14c: f7ff ff7a bl 800a044 800a150: 4603 mov r3, r0 800a152: 4a03 ldr r2, [pc, #12] @ (800a160 ) 800a154: 6013 str r3, [r2, #0] return cp_voltage_mv; 800a156: 4b02 ldr r3, [pc, #8] @ (800a160 ) 800a158: 681b ldr r3, [r3, #0] } 800a15a: 4618 mov r0, r3 800a15c: bd80 pop {r7, pc} 800a15e: bf00 nop 800a160: 200003d4 .word 0x200003d4 0800a164 : CP_State_t CP_GetState(void) { 800a164: b580 push {r7, lr} 800a166: b082 sub sp, #8 800a168: af00 add r7, sp, #0 int32_t voltage_real = CP_GetVoltage(); 800a16a: f7ff ffed bl 800a148 800a16e: 6078 str r0, [r7, #4] if(fake_cp_state != EV_STATE_ACQUIRING) { 800a170: 4b21 ldr r3, [pc, #132] @ (800a1f8 ) 800a172: 781b ldrb r3, [r3, #0] 800a174: 2b06 cmp r3, #6 800a176: d002 beq.n 800a17e return fake_cp_state; 800a178: 4b1f ldr r3, [pc, #124] @ (800a1f8 ) 800a17a: 781b ldrb r3, [r3, #0] 800a17c: e038 b.n 800a1f0 } if (voltage_real >= (12000-1000)) { 800a17e: 687b ldr r3, [r7, #4] 800a180: f642 22f7 movw r2, #10999 @ 0x2af7 800a184: 4293 cmp r3, r2 800a186: dd01 ble.n 800a18c return EV_STATE_A_IDLE; 800a188: 2300 movs r3, #0 800a18a: e031 b.n 800a1f0 } else if (voltage_real >= (9000-1000) && voltage_real <= (9000+1000)) { 800a18c: 687b ldr r3, [r7, #4] 800a18e: f5b3 5ffa cmp.w r3, #8000 @ 0x1f40 800a192: db06 blt.n 800a1a2 800a194: 687b ldr r3, [r7, #4] 800a196: f242 7210 movw r2, #10000 @ 0x2710 800a19a: 4293 cmp r3, r2 800a19c: dc01 bgt.n 800a1a2 return EV_STATE_B_CONN_PREP; 800a19e: 2301 movs r3, #1 800a1a0: e026 b.n 800a1f0 } else if (voltage_real >= (6000-1000) && voltage_real <= (6000+1000)) { 800a1a2: 687b ldr r3, [r7, #4] 800a1a4: f241 3287 movw r2, #4999 @ 0x1387 800a1a8: 4293 cmp r3, r2 800a1aa: dd06 ble.n 800a1ba 800a1ac: 687b ldr r3, [r7, #4] 800a1ae: f641 3258 movw r2, #7000 @ 0x1b58 800a1b2: 4293 cmp r3, r2 800a1b4: dc01 bgt.n 800a1ba return EV_STATE_C_CONN_ACTIVE; 800a1b6: 2302 movs r3, #2 800a1b8: e01a b.n 800a1f0 } else if (voltage_real >= (3000-1000) && voltage_real <= (3000 + 1000)) { 800a1ba: 687b ldr r3, [r7, #4] 800a1bc: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800a1c0: db05 blt.n 800a1ce 800a1c2: 687b ldr r3, [r7, #4] 800a1c4: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800a1c8: dc01 bgt.n 800a1ce return EV_STATE_D_CONN_ACT_VENT; 800a1ca: 2303 movs r3, #3 800a1cc: e010 b.n 800a1f0 } else if (voltage_real >= (0-1000) && voltage_real <= (0+2000)){ 800a1ce: 687b ldr r3, [r7, #4] 800a1d0: f513 7f7a cmn.w r3, #1000 @ 0x3e8 800a1d4: db05 blt.n 800a1e2 800a1d6: 687b ldr r3, [r7, #4] 800a1d8: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 800a1dc: dc01 bgt.n 800a1e2 return EV_STATE_E_NO_POWER; 800a1de: 2304 movs r3, #4 800a1e0: e006 b.n 800a1f0 } else if (voltage_real <= (-12000+1000)) { 800a1e2: 687b ldr r3, [r7, #4] 800a1e4: 4a05 ldr r2, [pc, #20] @ (800a1fc ) 800a1e6: 4293 cmp r3, r2 800a1e8: da01 bge.n 800a1ee return EV_STATE_F_ERROR; 800a1ea: 2305 movs r3, #5 800a1ec: e000 b.n 800a1f0 } else { return EV_STATE_ACQUIRING; 800a1ee: 2306 movs r3, #6 } } 800a1f0: 4618 mov r0, r3 800a1f2: 3708 adds r7, #8 800a1f4: 46bd mov sp, r7 800a1f6: bd80 pop {r7, pc} 800a1f8: 20000004 .word 0x20000004 800a1fc: ffffd509 .word 0xffffd509 0800a200 : CP_State_t CP_GetFilteredState(void) { 800a200: b480 push {r7} 800a202: af00 add r7, sp, #0 return cp_state_buffer; 800a204: 4b02 ldr r3, [pc, #8] @ (800a210 ) 800a206: 781b ldrb r3, [r3, #0] } 800a208: 4618 mov r0, r3 800a20a: 46bd mov sp, r7 800a20c: bc80 pop {r7} 800a20e: 4770 bx lr 800a210: 20000005 .word 0x20000005 0800a214 : void CP_FilterState(void) { 800a214: b580 push {r7, lr} 800a216: b082 sub sp, #8 800a218: af00 add r7, sp, #0 static CP_State_t pending_state = EV_STATE_ACQUIRING; static uint8_t stable_count = 0u; CP_State_t current_state = CP_GetState(); 800a21a: f7ff ffa3 bl 800a164 800a21e: 4603 mov r3, r0 800a220: 71fb strb r3, [r7, #7] /* Keep last accepted state while CP is still acquiring. */ if (current_state == EV_STATE_ACQUIRING) { 800a222: 79fb ldrb r3, [r7, #7] 800a224: 2b06 cmp r3, #6 800a226: d106 bne.n 800a236 pending_state = EV_STATE_ACQUIRING; 800a228: 4b13 ldr r3, [pc, #76] @ (800a278 ) 800a22a: 2206 movs r2, #6 800a22c: 701a strb r2, [r3, #0] stable_count = 0u; 800a22e: 4b13 ldr r3, [pc, #76] @ (800a27c ) 800a230: 2200 movs r2, #0 800a232: 701a strb r2, [r3, #0] return; 800a234: e01d b.n 800a272 } if (current_state != pending_state) { 800a236: 4b10 ldr r3, [pc, #64] @ (800a278 ) 800a238: 781b ldrb r3, [r3, #0] 800a23a: 79fa ldrb r2, [r7, #7] 800a23c: 429a cmp r2, r3 800a23e: d006 beq.n 800a24e pending_state = current_state; 800a240: 4a0d ldr r2, [pc, #52] @ (800a278 ) 800a242: 79fb ldrb r3, [r7, #7] 800a244: 7013 strb r3, [r2, #0] stable_count = 1u; 800a246: 4b0d ldr r3, [pc, #52] @ (800a27c ) 800a248: 2201 movs r2, #1 800a24a: 701a strb r2, [r3, #0] return; 800a24c: e011 b.n 800a272 } if (stable_count < FILTER_ORDER) { 800a24e: 4b0b ldr r3, [pc, #44] @ (800a27c ) 800a250: 781b ldrb r3, [r3, #0] 800a252: 2b63 cmp r3, #99 @ 0x63 800a254: d805 bhi.n 800a262 stable_count++; 800a256: 4b09 ldr r3, [pc, #36] @ (800a27c ) 800a258: 781b ldrb r3, [r3, #0] 800a25a: 3301 adds r3, #1 800a25c: b2da uxtb r2, r3 800a25e: 4b07 ldr r3, [pc, #28] @ (800a27c ) 800a260: 701a strb r2, [r3, #0] } if (stable_count >= FILTER_ORDER) { 800a262: 4b06 ldr r3, [pc, #24] @ (800a27c ) 800a264: 781b ldrb r3, [r3, #0] 800a266: 2b63 cmp r3, #99 @ 0x63 800a268: d903 bls.n 800a272 cp_state_buffer = pending_state; 800a26a: 4b03 ldr r3, [pc, #12] @ (800a278 ) 800a26c: 781a ldrb r2, [r3, #0] 800a26e: 4b04 ldr r3, [pc, #16] @ (800a280 ) 800a270: 701a strb r2, [r3, #0] } } 800a272: 3708 adds r7, #8 800a274: 46bd mov sp, r7 800a276: bd80 pop {r7, pc} 800a278: 20000006 .word 0x20000006 800a27c: 200003d9 .word 0x200003d9 800a280: 20000005 .word 0x20000005 0800a284 : void CP_Loop(void) { 800a284: b580 push {r7, lr} 800a286: b082 sub sp, #8 800a288: af00 add r7, sp, #0 static uint32_t tick; if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800a28a: f004 f881 bl 800e390 800a28e: 4602 mov r2, r0 800a290: 4b22 ldr r3, [pc, #136] @ (800a31c ) 800a292: 681b ldr r3, [r3, #0] 800a294: 1ad3 subs r3, r2, r3 800a296: 2b00 cmp r3, #0 800a298: dd3c ble.n 800a314 tick = HAL_GetTick(); 800a29a: f004 f879 bl 800e390 800a29e: 4603 mov r3, r0 800a2a0: 4a1e ldr r2, [pc, #120] @ (800a31c ) 800a2a2: 6013 str r3, [r2, #0] static uint8_t initialized = 0; static CP_State_t prev_state = EV_STATE_ACQUIRING; static uint8_t prev_duty = 0; CP_FilterState(); 800a2a4: f7ff ffb6 bl 800a214 CP_State_t current_state = CP_GetFilteredState(); 800a2a8: f7ff ffaa bl 800a200 800a2ac: 4603 mov r3, r0 800a2ae: 71fb strb r3, [r7, #7] uint8_t current_duty = cp_duty; 800a2b0: 4b1b ldr r3, [pc, #108] @ (800a320 ) 800a2b2: 781b ldrb r3, [r3, #0] 800a2b4: 71bb strb r3, [r7, #6] if (!initialized) { 800a2b6: 4b1b ldr r3, [pc, #108] @ (800a324 ) 800a2b8: 781b ldrb r3, [r3, #0] 800a2ba: 2b00 cmp r3, #0 800a2bc: d109 bne.n 800a2d2 prev_state = current_state; 800a2be: 4a1a ldr r2, [pc, #104] @ (800a328 ) 800a2c0: 79fb ldrb r3, [r7, #7] 800a2c2: 7013 strb r3, [r2, #0] prev_duty = current_duty; 800a2c4: 4a19 ldr r2, [pc, #100] @ (800a32c ) 800a2c6: 79bb ldrb r3, [r7, #6] 800a2c8: 7013 strb r3, [r2, #0] initialized = 1; 800a2ca: 4b16 ldr r3, [pc, #88] @ (800a324 ) 800a2cc: 2201 movs r2, #1 800a2ce: 701a strb r2, [r3, #0] return; 800a2d0: e021 b.n 800a316 } if (current_state != prev_state) { 800a2d2: 4b15 ldr r3, [pc, #84] @ (800a328 ) 800a2d4: 781b ldrb r3, [r3, #0] 800a2d6: 79fa ldrb r2, [r7, #7] 800a2d8: 429a cmp r2, r3 800a2da: d00a beq.n 800a2f2 log_printf(LOG_INFO, "CP state changed: %d -> %d\n", prev_state, current_state); 800a2dc: 4b12 ldr r3, [pc, #72] @ (800a328 ) 800a2de: 781b ldrb r3, [r3, #0] 800a2e0: 461a mov r2, r3 800a2e2: 79fb ldrb r3, [r7, #7] 800a2e4: 4912 ldr r1, [pc, #72] @ (800a330 ) 800a2e6: 2007 movs r0, #7 800a2e8: f000 f93e bl 800a568 prev_state = current_state; 800a2ec: 4a0e ldr r2, [pc, #56] @ (800a328 ) 800a2ee: 79fb ldrb r3, [r7, #7] 800a2f0: 7013 strb r3, [r2, #0] } if (current_duty != prev_duty) { 800a2f2: 4b0e ldr r3, [pc, #56] @ (800a32c ) 800a2f4: 781b ldrb r3, [r3, #0] 800a2f6: 79ba ldrb r2, [r7, #6] 800a2f8: 429a cmp r2, r3 800a2fa: d00c beq.n 800a316 log_printf(LOG_INFO, "CP duty changed: %u -> %u\n", prev_duty, current_duty); 800a2fc: 4b0b ldr r3, [pc, #44] @ (800a32c ) 800a2fe: 781b ldrb r3, [r3, #0] 800a300: 461a mov r2, r3 800a302: 79bb ldrb r3, [r7, #6] 800a304: 490b ldr r1, [pc, #44] @ (800a334 ) 800a306: 2007 movs r0, #7 800a308: f000 f92e bl 800a568 prev_duty = current_duty; 800a30c: 4a07 ldr r2, [pc, #28] @ (800a32c ) 800a30e: 79bb ldrb r3, [r7, #6] 800a310: 7013 strb r3, [r2, #0] 800a312: e000 b.n 800a316 if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800a314: bf00 nop } } 800a316: 3708 adds r7, #8 800a318: 46bd mov sp, r7 800a31a: bd80 pop {r7, pc} 800a31c: 200003dc .word 0x200003dc 800a320: 200003d8 .word 0x200003d8 800a324: 200003e0 .word 0x200003e0 800a328: 20000007 .word 0x20000007 800a32c: 200003e1 .word 0x200003e1 800a330: 080170d8 .word 0x080170d8 800a334: 080170f4 .word 0x080170f4 0800a338 : CRC_HandleTypeDef hcrc; /* CRC init function */ void MX_CRC_Init(void) { 800a338: b580 push {r7, lr} 800a33a: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 800a33c: 4b06 ldr r3, [pc, #24] @ (800a358 ) 800a33e: 4a07 ldr r2, [pc, #28] @ (800a35c ) 800a340: 601a str r2, [r3, #0] if (HAL_CRC_Init(&hcrc) != HAL_OK) 800a342: 4805 ldr r0, [pc, #20] @ (800a358 ) 800a344: f005 fd75 bl 800fe32 800a348: 4603 mov r3, r0 800a34a: 2b00 cmp r3, #0 800a34c: d001 beq.n 800a352 { Error_Handler(); 800a34e: f000 fcc1 bl 800acd4 } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 800a352: bf00 nop 800a354: bd80 pop {r7, pc} 800a356: bf00 nop 800a358: 200003e4 .word 0x200003e4 800a35c: 40023000 .word 0x40023000 0800a360 : void HAL_CRC_MspInit(CRC_HandleTypeDef* crcHandle) { 800a360: b480 push {r7} 800a362: b085 sub sp, #20 800a364: af00 add r7, sp, #0 800a366: 6078 str r0, [r7, #4] if(crcHandle->Instance==CRC) 800a368: 687b ldr r3, [r7, #4] 800a36a: 681b ldr r3, [r3, #0] 800a36c: 4a09 ldr r2, [pc, #36] @ (800a394 ) 800a36e: 4293 cmp r3, r2 800a370: d10b bne.n 800a38a { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* CRC clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 800a372: 4b09 ldr r3, [pc, #36] @ (800a398 ) 800a374: 695b ldr r3, [r3, #20] 800a376: 4a08 ldr r2, [pc, #32] @ (800a398 ) 800a378: f043 0340 orr.w r3, r3, #64 @ 0x40 800a37c: 6153 str r3, [r2, #20] 800a37e: 4b06 ldr r3, [pc, #24] @ (800a398 ) 800a380: 695b ldr r3, [r3, #20] 800a382: f003 0340 and.w r3, r3, #64 @ 0x40 800a386: 60fb str r3, [r7, #12] 800a388: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 800a38a: bf00 nop 800a38c: 3714 adds r7, #20 800a38e: 46bd mov sp, r7 800a390: bc80 pop {r7} 800a392: 4770 bx lr 800a394: 40023000 .word 0x40023000 800a398: 40021000 .word 0x40021000 0800a39c <_write>: #if defined(__GNUC__) int _write(int fd, char * ptr, int len) { 800a39c: b580 push {r7, lr} 800a39e: b084 sub sp, #16 800a3a0: af00 add r7, sp, #0 800a3a2: 60f8 str r0, [r7, #12] 800a3a4: 60b9 str r1, [r7, #8] 800a3a6: 607a str r2, [r7, #4] debug_buffer_add((const uint8_t*)ptr, len); 800a3a8: 687b ldr r3, [r7, #4] 800a3aa: b29b uxth r3, r3 800a3ac: 4619 mov r1, r3 800a3ae: 68b8 ldr r0, [r7, #8] 800a3b0: f000 f806 bl 800a3c0 return len; 800a3b4: 687b ldr r3, [r7, #4] } 800a3b6: 4618 mov r0, r3 800a3b8: 3710 adds r7, #16 800a3ba: 46bd mov sp, r7 800a3bc: bd80 pop {r7, pc} ... 0800a3c0 : #endif // Добавляет данные в кольцевой буфер void debug_buffer_add(const uint8_t* data, uint16_t len) { 800a3c0: b480 push {r7} 800a3c2: b085 sub sp, #20 800a3c4: af00 add r7, sp, #0 800a3c6: 6078 str r0, [r7, #4] 800a3c8: 460b mov r3, r1 800a3ca: 807b strh r3, [r7, #2] \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 800a3cc: b672 cpsid i } 800a3ce: bf00 nop __disable_irq(); for (uint16_t i = 0; i < len; i++) { 800a3d0: 2300 movs r3, #0 800a3d2: 81fb strh r3, [r7, #14] 800a3d4: e045 b.n 800a462 // Если буфер полон, перезаписываем старые данные if (debug_buffer.count >= DEBUG_BUFFER_SIZE) { 800a3d6: 4b28 ldr r3, [pc, #160] @ (800a478 ) 800a3d8: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a3dc: b29b uxth r3, r3 800a3de: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800a3e2: d318 bcc.n 800a416 debug_buffer.read_index = (debug_buffer.read_index + 1) % DEBUG_BUFFER_SIZE; 800a3e4: 4b24 ldr r3, [pc, #144] @ (800a478 ) 800a3e6: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a3ea: b29b uxth r3, r3 800a3ec: 3301 adds r3, #1 800a3ee: 425a negs r2, r3 800a3f0: f3c3 0309 ubfx r3, r3, #0, #10 800a3f4: f3c2 0209 ubfx r2, r2, #0, #10 800a3f8: bf58 it pl 800a3fa: 4253 negpl r3, r2 800a3fc: b29a uxth r2, r3 800a3fe: 4b1e ldr r3, [pc, #120] @ (800a478 ) 800a400: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count--; 800a404: 4b1c ldr r3, [pc, #112] @ (800a478 ) 800a406: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a40a: b29b uxth r3, r3 800a40c: 3b01 subs r3, #1 800a40e: b29a uxth r2, r3 800a410: 4b19 ldr r3, [pc, #100] @ (800a478 ) 800a412: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 } debug_buffer.buffer[debug_buffer.write_index] = data[i]; 800a416: 89fb ldrh r3, [r7, #14] 800a418: 687a ldr r2, [r7, #4] 800a41a: 4413 add r3, r2 800a41c: 4a16 ldr r2, [pc, #88] @ (800a478 ) 800a41e: f8b2 2400 ldrh.w r2, [r2, #1024] @ 0x400 800a422: b292 uxth r2, r2 800a424: 7819 ldrb r1, [r3, #0] 800a426: 4b14 ldr r3, [pc, #80] @ (800a478 ) 800a428: 5499 strb r1, [r3, r2] debug_buffer.write_index = (debug_buffer.write_index + 1) % DEBUG_BUFFER_SIZE; 800a42a: 4b13 ldr r3, [pc, #76] @ (800a478 ) 800a42c: f8b3 3400 ldrh.w r3, [r3, #1024] @ 0x400 800a430: b29b uxth r3, r3 800a432: 3301 adds r3, #1 800a434: 425a negs r2, r3 800a436: f3c3 0309 ubfx r3, r3, #0, #10 800a43a: f3c2 0209 ubfx r2, r2, #0, #10 800a43e: bf58 it pl 800a440: 4253 negpl r3, r2 800a442: b29a uxth r2, r3 800a444: 4b0c ldr r3, [pc, #48] @ (800a478 ) 800a446: f8a3 2400 strh.w r2, [r3, #1024] @ 0x400 debug_buffer.count++; 800a44a: 4b0b ldr r3, [pc, #44] @ (800a478 ) 800a44c: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a450: b29b uxth r3, r3 800a452: 3301 adds r3, #1 800a454: b29a uxth r2, r3 800a456: 4b08 ldr r3, [pc, #32] @ (800a478 ) 800a458: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 for (uint16_t i = 0; i < len; i++) { 800a45c: 89fb ldrh r3, [r7, #14] 800a45e: 3301 adds r3, #1 800a460: 81fb strh r3, [r7, #14] 800a462: 89fa ldrh r2, [r7, #14] 800a464: 887b ldrh r3, [r7, #2] 800a466: 429a cmp r2, r3 800a468: d3b5 bcc.n 800a3d6 __ASM volatile ("cpsie i" : : : "memory"); 800a46a: b662 cpsie i } 800a46c: bf00 nop } __enable_irq(); } 800a46e: bf00 nop 800a470: 3714 adds r7, #20 800a472: 46bd mov sp, r7 800a474: bc80 pop {r7} 800a476: 4770 bx lr 800a478: 200003ec .word 0x200003ec 0800a47c : // Возвращает количество доступных данных в буфере uint16_t debug_buffer_available(void) { 800a47c: b480 push {r7} 800a47e: b083 sub sp, #12 800a480: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a482: b672 cpsid i } 800a484: bf00 nop __disable_irq(); uint16_t count = debug_buffer.count; 800a486: 4b06 ldr r3, [pc, #24] @ (800a4a0 ) 800a488: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a48c: 80fb strh r3, [r7, #6] __ASM volatile ("cpsie i" : : : "memory"); 800a48e: b662 cpsie i } 800a490: bf00 nop __enable_irq(); return count; 800a492: 88fb ldrh r3, [r7, #6] } 800a494: 4618 mov r0, r3 800a496: 370c adds r7, #12 800a498: 46bd mov sp, r7 800a49a: bc80 pop {r7} 800a49c: 4770 bx lr 800a49e: bf00 nop 800a4a0: 200003ec .word 0x200003ec 0800a4a4 : // Отправляет один пакет данных из буфера через SC_SendPacket (не более 250 байт) void debug_buffer_send(void) { 800a4a4: b580 push {r7, lr} 800a4a6: b082 sub sp, #8 800a4a8: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800a4aa: b672 cpsid i } 800a4ac: bf00 nop __disable_irq(); // Если буфер пуст, ничего не делаем if (debug_buffer.count == 0) { 800a4ae: 4b2d ldr r3, [pc, #180] @ (800a564 ) 800a4b0: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a4b4: b29b uxth r3, r3 800a4b6: 2b00 cmp r3, #0 800a4b8: d102 bne.n 800a4c0 __ASM volatile ("cpsie i" : : : "memory"); 800a4ba: b662 cpsie i } 800a4bc: bf00 nop __enable_irq(); return; 800a4be: e04e b.n 800a55e } // Определяем сколько байт можно отправить (не более 250) uint16_t bytes_to_send = debug_buffer.count; 800a4c0: 4b28 ldr r3, [pc, #160] @ (800a564 ) 800a4c2: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a4c6: 80fb strh r3, [r7, #6] if (bytes_to_send > DEBUG_BUFFER_MAX_COUNT) { 800a4c8: 88fb ldrh r3, [r7, #6] 800a4ca: 2b80 cmp r3, #128 @ 0x80 800a4cc: d901 bls.n 800a4d2 bytes_to_send = DEBUG_BUFFER_MAX_COUNT; 800a4ce: 2380 movs r3, #128 @ 0x80 800a4d0: 80fb strh r3, [r7, #6] } // Вычисляем сколько байт до конца буфера uint16_t bytes_to_end = DEBUG_BUFFER_SIZE - debug_buffer.read_index; 800a4d2: 4b24 ldr r3, [pc, #144] @ (800a564 ) 800a4d4: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a4d8: b29b uxth r3, r3 800a4da: f5c3 6380 rsb r3, r3, #1024 @ 0x400 800a4de: 80bb strh r3, [r7, #4] // Отправляем только непрерывный блок (до конца буфера или до bytes_to_send) if (bytes_to_send > bytes_to_end) { 800a4e0: 88fa ldrh r2, [r7, #6] 800a4e2: 88bb ldrh r3, [r7, #4] 800a4e4: 429a cmp r2, r3 800a4e6: d901 bls.n 800a4ec bytes_to_send = bytes_to_end; 800a4e8: 88bb ldrh r3, [r7, #4] 800a4ea: 80fb strh r3, [r7, #6] } // Отправляем данные напрямую из буфера if(bytes_to_send == debug_buffer.count){ 800a4ec: 4b1d ldr r3, [pc, #116] @ (800a564 ) 800a4ee: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a4f2: b29b uxth r3, r3 800a4f4: 88fa ldrh r2, [r7, #6] 800a4f6: 429a cmp r2, r3 800a4f8: d10c bne.n 800a514 SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG); 800a4fa: 4b1a ldr r3, [pc, #104] @ (800a564 ) 800a4fc: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a500: b29b uxth r3, r3 800a502: 461a mov r2, r3 800a504: 4b17 ldr r3, [pc, #92] @ (800a564 ) 800a506: 4413 add r3, r2 800a508: 88f9 ldrh r1, [r7, #6] 800a50a: 2250 movs r2, #80 @ 0x50 800a50c: 4618 mov r0, r3 800a50e: f002 fc57 bl 800cdc0 800a512: e00b b.n 800a52c }else{ SC_SendPacket(&debug_buffer.buffer[debug_buffer.read_index], bytes_to_send, CMD_GET_LOG_CONTINUE); 800a514: 4b13 ldr r3, [pc, #76] @ (800a564 ) 800a516: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a51a: b29b uxth r3, r3 800a51c: 461a mov r2, r3 800a51e: 4b11 ldr r3, [pc, #68] @ (800a564 ) 800a520: 4413 add r3, r2 800a522: 88f9 ldrh r1, [r7, #6] 800a524: 2251 movs r2, #81 @ 0x51 800a526: 4618 mov r0, r3 800a528: f002 fc4a bl 800cdc0 } debug_buffer.read_index = (debug_buffer.read_index + bytes_to_send) % DEBUG_BUFFER_SIZE; 800a52c: 4b0d ldr r3, [pc, #52] @ (800a564 ) 800a52e: f8b3 3402 ldrh.w r3, [r3, #1026] @ 0x402 800a532: b29a uxth r2, r3 800a534: 88fb ldrh r3, [r7, #6] 800a536: 4413 add r3, r2 800a538: b29b uxth r3, r3 800a53a: f3c3 0309 ubfx r3, r3, #0, #10 800a53e: b29a uxth r2, r3 800a540: 4b08 ldr r3, [pc, #32] @ (800a564 ) 800a542: f8a3 2402 strh.w r2, [r3, #1026] @ 0x402 debug_buffer.count -= bytes_to_send; 800a546: 4b07 ldr r3, [pc, #28] @ (800a564 ) 800a548: f8b3 3404 ldrh.w r3, [r3, #1028] @ 0x404 800a54c: b29a uxth r2, r3 800a54e: 88fb ldrh r3, [r7, #6] 800a550: 1ad3 subs r3, r2, r3 800a552: b29a uxth r2, r3 800a554: 4b03 ldr r3, [pc, #12] @ (800a564 ) 800a556: f8a3 2404 strh.w r2, [r3, #1028] @ 0x404 __ASM volatile ("cpsie i" : : : "memory"); 800a55a: b662 cpsie i } 800a55c: bf00 nop __enable_irq(); } 800a55e: 3708 adds r7, #8 800a560: 46bd mov sp, r7 800a562: bd80 pop {r7, pc} 800a564: 200003ec .word 0x200003ec 0800a568 : #define LOG_BUFFER_SIZE 128 uint8_t log_buffer[LOG_BUFFER_SIZE]; // Кастомный printf с приоритетом лога int log_printf(LogLevel_t level, const char *format, ...) { 800a568: b40e push {r1, r2, r3} 800a56a: b580 push {r7, lr} 800a56c: b085 sub sp, #20 800a56e: af00 add r7, sp, #0 800a570: 4603 mov r3, r0 800a572: 71fb strb r3, [r7, #7] va_list args; int result; // Добавляем приоритет первым байтом log_buffer[0] = (uint8_t)level; 800a574: 4a15 ldr r2, [pc, #84] @ (800a5cc ) 800a576: 79fb ldrb r3, [r7, #7] 800a578: 7013 strb r3, [r2, #0] // Форматируем строку начиная со второго байта va_start(args, format); 800a57a: f107 0320 add.w r3, r7, #32 800a57e: 60bb str r3, [r7, #8] result = vsnprintf((char*)&log_buffer[1], LOG_BUFFER_SIZE - 2, format, args); 800a580: 68bb ldr r3, [r7, #8] 800a582: 69fa ldr r2, [r7, #28] 800a584: 217e movs r1, #126 @ 0x7e 800a586: 4812 ldr r0, [pc, #72] @ (800a5d0 ) 800a588: f00a fb90 bl 8014cac 800a58c: 60f8 str r0, [r7, #12] va_end(args); // Проверяем, не переполнился ли буфер if (result < 0) { 800a58e: 68fb ldr r3, [r7, #12] 800a590: 2b00 cmp r3, #0 800a592: da01 bge.n 800a598 return result; 800a594: 68fb ldr r3, [r7, #12] 800a596: e012 b.n 800a5be } // Ограничиваем размер, чтобы оставить место для нуль-терминатора if (result >= (LOG_BUFFER_SIZE - 2)) { 800a598: 68fb ldr r3, [r7, #12] 800a59a: 2b7d cmp r3, #125 @ 0x7d 800a59c: dd01 ble.n 800a5a2 result = LOG_BUFFER_SIZE - 2; 800a59e: 237e movs r3, #126 @ 0x7e 800a5a0: 60fb str r3, [r7, #12] } // Добавляем нуль-терминатор в конец log_buffer[result + 1] = '\0'; 800a5a2: 68fb ldr r3, [r7, #12] 800a5a4: 3301 adds r3, #1 800a5a6: 4a09 ldr r2, [pc, #36] @ (800a5cc ) 800a5a8: 2100 movs r1, #0 800a5aa: 54d1 strb r1, [r2, r3] // Отправляем в буфер (приоритет + строка + нуль-терминатор) debug_buffer_add(log_buffer, result + 2); 800a5ac: 68fb ldr r3, [r7, #12] 800a5ae: b29b uxth r3, r3 800a5b0: 3302 adds r3, #2 800a5b2: b29b uxth r3, r3 800a5b4: 4619 mov r1, r3 800a5b6: 4805 ldr r0, [pc, #20] @ (800a5cc ) 800a5b8: f7ff ff02 bl 800a3c0 return result; 800a5bc: 68fb ldr r3, [r7, #12] } 800a5be: 4618 mov r0, r3 800a5c0: 3714 adds r7, #20 800a5c2: 46bd mov sp, r7 800a5c4: e8bd 4080 ldmia.w sp!, {r7, lr} 800a5c8: b003 add sp, #12 800a5ca: 4770 bx lr 800a5cc: 200007f4 .word 0x200007f4 800a5d0: 200007f5 .word 0x200007f5 0800a5d4 : /** * Enable DMA controller clock */ void MX_DMA_Init(void) { 800a5d4: b580 push {r7, lr} 800a5d6: b082 sub sp, #8 800a5d8: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 800a5da: 4b1c ldr r3, [pc, #112] @ (800a64c ) 800a5dc: 695b ldr r3, [r3, #20] 800a5de: 4a1b ldr r2, [pc, #108] @ (800a64c ) 800a5e0: f043 0301 orr.w r3, r3, #1 800a5e4: 6153 str r3, [r2, #20] 800a5e6: 4b19 ldr r3, [pc, #100] @ (800a64c ) 800a5e8: 695b ldr r3, [r3, #20] 800a5ea: f003 0301 and.w r3, r3, #1 800a5ee: 607b str r3, [r7, #4] 800a5f0: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 1, 0); 800a5f2: 2200 movs r2, #0 800a5f4: 2101 movs r1, #1 800a5f6: 200b movs r0, #11 800a5f8: f005 fbe5 bl 800fdc6 HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 800a5fc: 200b movs r0, #11 800a5fe: f005 fbfe bl 800fdfe /* DMA1_Channel2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 4, 0); 800a602: 2200 movs r2, #0 800a604: 2104 movs r1, #4 800a606: 200c movs r0, #12 800a608: f005 fbdd bl 800fdc6 HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); 800a60c: 200c movs r0, #12 800a60e: f005 fbf6 bl 800fdfe /* DMA1_Channel3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 1, 0); 800a612: 2200 movs r2, #0 800a614: 2101 movs r1, #1 800a616: 200d movs r0, #13 800a618: f005 fbd5 bl 800fdc6 HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn); 800a61c: 200d movs r0, #13 800a61e: f005 fbee bl 800fdfe /* DMA1_Channel6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel6_IRQn, 1, 0); 800a622: 2200 movs r2, #0 800a624: 2101 movs r1, #1 800a626: 2010 movs r0, #16 800a628: f005 fbcd bl 800fdc6 HAL_NVIC_EnableIRQ(DMA1_Channel6_IRQn); 800a62c: 2010 movs r0, #16 800a62e: f005 fbe6 bl 800fdfe /* DMA1_Channel7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 4, 0); 800a632: 2200 movs r2, #0 800a634: 2104 movs r1, #4 800a636: 2011 movs r0, #17 800a638: f005 fbc5 bl 800fdc6 HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn); 800a63c: 2011 movs r0, #17 800a63e: f005 fbde bl 800fdfe } 800a642: bf00 nop 800a644: 3708 adds r7, #8 800a646: 46bd mov sp, r7 800a648: bd80 pop {r7, pc} 800a64a: bf00 nop 800a64c: 40021000 .word 0x40021000 0800a650 : #include "debug.h" #include "serial.h" static uint8_t fire_alarm_latched = 0; uint8_t FireAlarm_IsLatched(void) { 800a650: b480 push {r7} 800a652: af00 add r7, sp, #0 return fire_alarm_latched; 800a654: 4b02 ldr r3, [pc, #8] @ (800a660 ) 800a656: 781b ldrb r3, [r3, #0] } 800a658: 4618 mov r0, r3 800a65a: 46bd mov sp, r7 800a65c: bc80 pop {r7} 800a65e: 4770 bx lr 800a660: 20000874 .word 0x20000874 0800a664 : void FireAlarm_Activate(void) { 800a664: b580 push {r7, lr} 800a666: af00 add r7, sp, #0 if (fire_alarm_latched) { 800a668: 4b06 ldr r3, [pc, #24] @ (800a684 ) 800a66a: 781b ldrb r3, [r3, #0] 800a66c: 2b00 cmp r3, #0 800a66e: d107 bne.n 800a680 return; } fire_alarm_latched = 1; 800a670: 4b04 ldr r3, [pc, #16] @ (800a684 ) 800a672: 2201 movs r2, #1 800a674: 701a strb r2, [r3, #0] log_printf(LOG_ERR, "FIRE ALARM activated\n"); 800a676: 4904 ldr r1, [pc, #16] @ (800a688 ) 800a678: 2004 movs r0, #4 800a67a: f7ff ff75 bl 800a568 800a67e: e000 b.n 800a682 return; 800a680: bf00 nop } 800a682: bd80 pop {r7, pc} 800a684: 20000874 .word 0x20000874 800a688: 08017110 .word 0x08017110 0800a68c : * EXTI PB8 ------> I2C1_SCL PB9 ------> I2C1_SDA */ void MX_GPIO_Init(void) { 800a68c: b580 push {r7, lr} 800a68e: b08a sub sp, #40 @ 0x28 800a690: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800a692: f107 0314 add.w r3, r7, #20 800a696: 2200 movs r2, #0 800a698: 601a str r2, [r3, #0] 800a69a: 605a str r2, [r3, #4] 800a69c: 609a str r2, [r3, #8] 800a69e: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 800a6a0: 4b94 ldr r3, [pc, #592] @ (800a8f4 ) 800a6a2: 699b ldr r3, [r3, #24] 800a6a4: 4a93 ldr r2, [pc, #588] @ (800a8f4 ) 800a6a6: f043 0310 orr.w r3, r3, #16 800a6aa: 6193 str r3, [r2, #24] 800a6ac: 4b91 ldr r3, [pc, #580] @ (800a8f4 ) 800a6ae: 699b ldr r3, [r3, #24] 800a6b0: f003 0310 and.w r3, r3, #16 800a6b4: 613b str r3, [r7, #16] 800a6b6: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800a6b8: 4b8e ldr r3, [pc, #568] @ (800a8f4 ) 800a6ba: 699b ldr r3, [r3, #24] 800a6bc: 4a8d ldr r2, [pc, #564] @ (800a8f4 ) 800a6be: f043 0304 orr.w r3, r3, #4 800a6c2: 6193 str r3, [r2, #24] 800a6c4: 4b8b ldr r3, [pc, #556] @ (800a8f4 ) 800a6c6: 699b ldr r3, [r3, #24] 800a6c8: f003 0304 and.w r3, r3, #4 800a6cc: 60fb str r3, [r7, #12] 800a6ce: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 800a6d0: 4b88 ldr r3, [pc, #544] @ (800a8f4 ) 800a6d2: 699b ldr r3, [r3, #24] 800a6d4: 4a87 ldr r2, [pc, #540] @ (800a8f4 ) 800a6d6: f043 0308 orr.w r3, r3, #8 800a6da: 6193 str r3, [r2, #24] 800a6dc: 4b85 ldr r3, [pc, #532] @ (800a8f4 ) 800a6de: 699b ldr r3, [r3, #24] 800a6e0: f003 0308 and.w r3, r3, #8 800a6e4: 60bb str r3, [r7, #8] 800a6e6: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOE_CLK_ENABLE(); 800a6e8: 4b82 ldr r3, [pc, #520] @ (800a8f4 ) 800a6ea: 699b ldr r3, [r3, #24] 800a6ec: 4a81 ldr r2, [pc, #516] @ (800a8f4 ) 800a6ee: f043 0340 orr.w r3, r3, #64 @ 0x40 800a6f2: 6193 str r3, [r2, #24] 800a6f4: 4b7f ldr r3, [pc, #508] @ (800a8f4 ) 800a6f6: 699b ldr r3, [r3, #24] 800a6f8: f003 0340 and.w r3, r3, #64 @ 0x40 800a6fc: 607b str r3, [r7, #4] 800a6fe: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 800a700: 4b7c ldr r3, [pc, #496] @ (800a8f4 ) 800a702: 699b ldr r3, [r3, #24] 800a704: 4a7b ldr r2, [pc, #492] @ (800a8f4 ) 800a706: f043 0320 orr.w r3, r3, #32 800a70a: 6193 str r3, [r2, #24] 800a70c: 4b79 ldr r3, [pc, #484] @ (800a8f4 ) 800a70e: 699b ldr r3, [r3, #24] 800a710: f003 0320 and.w r3, r3, #32 800a714: 603b str r3, [r7, #0] 800a716: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, DBG1_Pin|RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin 800a718: 2200 movs r2, #0 800a71a: f44f 710f mov.w r1, #572 @ 0x23c 800a71e: 4876 ldr r0, [pc, #472] @ (800a8f8 ) 800a720: f006 f9cd bl 8010abe |LED_DATA_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, DBG2_Pin|DBG3_Pin|RELAY_CC_Pin, GPIO_PIN_RESET); 800a724: 2200 movs r2, #0 800a726: f248 0160 movw r1, #32864 @ 0x8060 800a72a: 4874 ldr r0, [pc, #464] @ (800a8fc ) 800a72c: f006 f9c7 bl 8010abe /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a730: 2200 movs r2, #0 800a732: f44f 51f8 mov.w r1, #7936 @ 0x1f00 800a736: 4872 ldr r0, [pc, #456] @ (800a900 ) 800a738: f006 f9c1 bl 8010abe |RELAY5_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, DBG5_Pin|DBG4_Pin|EE_WP_Pin, GPIO_PIN_RESET); 800a73c: 2200 movs r2, #0 800a73e: f44f 6148 mov.w r1, #3200 @ 0xc80 800a742: 4870 ldr r0, [pc, #448] @ (800a904 ) 800a744: f006 f9bb bl 8010abe /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, RELAY_DC_Pin|USART2_DIR_Pin, GPIO_PIN_RESET); 800a748: 2200 movs r2, #0 800a74a: 2118 movs r1, #24 800a74c: 486e ldr r0, [pc, #440] @ (800a908 ) 800a74e: f006 f9b6 bl 8010abe /*Configure GPIO pin : DBG1_Pin */ GPIO_InitStruct.Pin = DBG1_Pin; 800a752: 2304 movs r3, #4 800a754: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a756: 2301 movs r3, #1 800a758: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a75a: 2300 movs r3, #0 800a75c: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a75e: 2303 movs r3, #3 800a760: 623b str r3, [r7, #32] HAL_GPIO_Init(DBG1_GPIO_Port, &GPIO_InitStruct); 800a762: f107 0314 add.w r3, r7, #20 800a766: 4619 mov r1, r3 800a768: 4863 ldr r0, [pc, #396] @ (800a8f8 ) 800a76a: f006 f80d bl 8010788 /*Configure GPIO pins : RELAY_CP_Pin LOCK_A_Pin LOCK_B_Pin LED_DATA_Pin */ GPIO_InitStruct.Pin = RELAY_CP_Pin|LOCK_A_Pin|LOCK_B_Pin|LED_DATA_Pin; 800a76e: f44f 730e mov.w r3, #568 @ 0x238 800a772: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a774: 2301 movs r3, #1 800a776: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a778: 2300 movs r3, #0 800a77a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a77c: 2302 movs r3, #2 800a77e: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800a780: f107 0314 add.w r3, r7, #20 800a784: 4619 mov r1, r3 800a786: 485c ldr r0, [pc, #368] @ (800a8f8 ) 800a788: f005 fffe bl 8010788 /*Configure GPIO pin : IN_SW0_Pin */ GPIO_InitStruct.Pin = IN_SW0_Pin; 800a78c: 2302 movs r3, #2 800a78e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a790: 2300 movs r3, #0 800a792: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a794: 2300 movs r3, #0 800a796: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW0_GPIO_Port, &GPIO_InitStruct); 800a798: f107 0314 add.w r3, r7, #20 800a79c: 4619 mov r1, r3 800a79e: 4857 ldr r0, [pc, #348] @ (800a8fc ) 800a7a0: f005 fff2 bl 8010788 /*Configure GPIO pin : IN_SW1_Pin */ GPIO_InitStruct.Pin = IN_SW1_Pin; 800a7a4: 2304 movs r3, #4 800a7a6: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a7a8: 2300 movs r3, #0 800a7aa: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 800a7ac: 2302 movs r3, #2 800a7ae: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_SW1_GPIO_Port, &GPIO_InitStruct); 800a7b0: f107 0314 add.w r3, r7, #20 800a7b4: 4619 mov r1, r3 800a7b6: 4851 ldr r0, [pc, #324] @ (800a8fc ) 800a7b8: f005 ffe6 bl 8010788 /*Configure GPIO pins : DBG2_Pin DBG3_Pin */ GPIO_InitStruct.Pin = DBG2_Pin|DBG3_Pin; 800a7bc: 2360 movs r3, #96 @ 0x60 800a7be: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a7c0: 2301 movs r3, #1 800a7c2: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a7c4: 2300 movs r3, #0 800a7c6: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a7c8: 2303 movs r3, #3 800a7ca: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800a7cc: f107 0314 add.w r3, r7, #20 800a7d0: 4619 mov r1, r3 800a7d2: 484a ldr r0, [pc, #296] @ (800a8fc ) 800a7d4: f005 ffd8 bl 8010788 /*Configure GPIO pins : IN0_Pin AC_OK_Pin ISO_IN_Pin */ GPIO_InitStruct.Pin = IN0_Pin|AC_OK_Pin|ISO_IN_Pin; 800a7d8: f244 0382 movw r3, #16514 @ 0x4082 800a7dc: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a7de: 2300 movs r3, #0 800a7e0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a7e2: 2300 movs r3, #0 800a7e4: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a7e6: f107 0314 add.w r3, r7, #20 800a7ea: 4619 mov r1, r3 800a7ec: 4844 ldr r0, [pc, #272] @ (800a900 ) 800a7ee: f005 ffcb bl 8010788 /*Configure GPIO pins : RELAY1_Pin RELAY2_Pin RELAY3_Pin RELAY4_Pin RELAY5_Pin */ GPIO_InitStruct.Pin = RELAY1_Pin|RELAY2_Pin|RELAY3_Pin|RELAY4_Pin 800a7f2: f44f 53f8 mov.w r3, #7936 @ 0x1f00 800a7f6: 617b str r3, [r7, #20] |RELAY5_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a7f8: 2301 movs r3, #1 800a7fa: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a7fc: 2300 movs r3, #0 800a7fe: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a800: 2302 movs r3, #2 800a802: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800a804: f107 0314 add.w r3, r7, #20 800a808: 4619 mov r1, r3 800a80a: 483d ldr r0, [pc, #244] @ (800a900 ) 800a80c: f005 ffbc bl 8010788 /*Configure GPIO pins : DBG5_Pin DBG4_Pin */ GPIO_InitStruct.Pin = DBG5_Pin|DBG4_Pin; 800a810: f44f 6340 mov.w r3, #3072 @ 0xc00 800a814: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a816: 2301 movs r3, #1 800a818: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a81a: 2300 movs r3, #0 800a81c: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a81e: 2303 movs r3, #3 800a820: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a822: f107 0314 add.w r3, r7, #20 800a826: 4619 mov r1, r3 800a828: 4836 ldr r0, [pc, #216] @ (800a904 ) 800a82a: f005 ffad bl 8010788 /*Configure GPIO pin : RELAY_CC_Pin */ GPIO_InitStruct.Pin = RELAY_CC_Pin; 800a82e: f44f 4300 mov.w r3, #32768 @ 0x8000 800a832: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a834: 2301 movs r3, #1 800a836: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a838: 2300 movs r3, #0 800a83a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a83c: 2302 movs r3, #2 800a83e: 623b str r3, [r7, #32] HAL_GPIO_Init(RELAY_CC_GPIO_Port, &GPIO_InitStruct); 800a840: f107 0314 add.w r3, r7, #20 800a844: 4619 mov r1, r3 800a846: 482d ldr r0, [pc, #180] @ (800a8fc ) 800a848: f005 ff9e bl 8010788 /*Configure GPIO pins : RELAY_DC_Pin USART2_DIR_Pin */ GPIO_InitStruct.Pin = RELAY_DC_Pin|USART2_DIR_Pin; 800a84c: 2318 movs r3, #24 800a84e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a850: 2301 movs r3, #1 800a852: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a854: 2300 movs r3, #0 800a856: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a858: 2302 movs r3, #2 800a85a: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800a85c: f107 0314 add.w r3, r7, #20 800a860: 4619 mov r1, r3 800a862: 4829 ldr r0, [pc, #164] @ (800a908 ) 800a864: f005 ff90 bl 8010788 /*Configure GPIO pin : IN_ESTOP_Pin */ GPIO_InitStruct.Pin = IN_ESTOP_Pin; 800a868: 2380 movs r3, #128 @ 0x80 800a86a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a86c: 2300 movs r3, #0 800a86e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a870: 2300 movs r3, #0 800a872: 61fb str r3, [r7, #28] HAL_GPIO_Init(IN_ESTOP_GPIO_Port, &GPIO_InitStruct); 800a874: f107 0314 add.w r3, r7, #20 800a878: 4619 mov r1, r3 800a87a: 4823 ldr r0, [pc, #140] @ (800a908 ) 800a87c: f005 ff84 bl 8010788 /*Configure GPIO pins : IN_FB2_Pin IN_FB1_Pin */ GPIO_InitStruct.Pin = IN_FB2_Pin|IN_FB1_Pin; 800a880: 2318 movs r3, #24 800a882: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800a884: 2300 movs r3, #0 800a886: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a888: 2300 movs r3, #0 800a88a: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a88c: f107 0314 add.w r3, r7, #20 800a890: 4619 mov r1, r3 800a892: 481c ldr r0, [pc, #112] @ (800a904 ) 800a894: f005 ff78 bl 8010788 /*Configure GPIO pin : EE_WP_Pin */ GPIO_InitStruct.Pin = EE_WP_Pin; 800a898: 2380 movs r3, #128 @ 0x80 800a89a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800a89c: 2301 movs r3, #1 800a89e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800a8a0: 2300 movs r3, #0 800a8a2: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800a8a4: 2302 movs r3, #2 800a8a6: 623b str r3, [r7, #32] HAL_GPIO_Init(EE_WP_GPIO_Port, &GPIO_InitStruct); 800a8a8: f107 0314 add.w r3, r7, #20 800a8ac: 4619 mov r1, r3 800a8ae: 4815 ldr r0, [pc, #84] @ (800a904 ) 800a8b0: f005 ff6a bl 8010788 /*Configure GPIO pins : PB8 PB9 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 800a8b4: f44f 7340 mov.w r3, #768 @ 0x300 800a8b8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 800a8ba: 2312 movs r3, #18 800a8bc: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800a8be: 2303 movs r3, #3 800a8c0: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800a8c2: f107 0314 add.w r3, r7, #20 800a8c6: 4619 mov r1, r3 800a8c8: 480e ldr r0, [pc, #56] @ (800a904 ) 800a8ca: f005 ff5d bl 8010788 /*Configure peripheral I/O remapping */ __HAL_AFIO_REMAP_I2C1_ENABLE(); 800a8ce: 4b0f ldr r3, [pc, #60] @ (800a90c ) 800a8d0: 685b ldr r3, [r3, #4] 800a8d2: 627b str r3, [r7, #36] @ 0x24 800a8d4: 6a7b ldr r3, [r7, #36] @ 0x24 800a8d6: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800a8da: 627b str r3, [r7, #36] @ 0x24 800a8dc: 6a7b ldr r3, [r7, #36] @ 0x24 800a8de: f043 0302 orr.w r3, r3, #2 800a8e2: 627b str r3, [r7, #36] @ 0x24 800a8e4: 4a09 ldr r2, [pc, #36] @ (800a90c ) 800a8e6: 6a7b ldr r3, [r7, #36] @ 0x24 800a8e8: 6053 str r3, [r2, #4] } 800a8ea: bf00 nop 800a8ec: 3728 adds r7, #40 @ 0x28 800a8ee: 46bd mov sp, r7 800a8f0: bd80 pop {r7, pc} 800a8f2: bf00 nop 800a8f4: 40021000 .word 0x40021000 800a8f8: 40011000 .word 0x40011000 800a8fc: 40010800 .word 0x40010800 800a900: 40011800 .word 0x40011800 800a904: 40010c00 .word 0x40010c00 800a908: 40011400 .word 0x40011400 800a90c: 40010000 .word 0x40010000 0800a910 <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 800a910: b480 push {r7} 800a912: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 800a914: f3bf 8f4f dsb sy } 800a918: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800a91a: 4b06 ldr r3, [pc, #24] @ (800a934 <__NVIC_SystemReset+0x24>) 800a91c: 68db ldr r3, [r3, #12] 800a91e: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800a922: 4904 ldr r1, [pc, #16] @ (800a934 <__NVIC_SystemReset+0x24>) 800a924: 4b04 ldr r3, [pc, #16] @ (800a938 <__NVIC_SystemReset+0x28>) 800a926: 4313 orrs r3, r2 800a928: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800a92a: f3bf 8f4f dsb sy } 800a92e: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 800a930: bf00 nop 800a932: e7fd b.n 800a930 <__NVIC_SystemReset+0x20> 800a934: e000ed00 .word 0xe000ed00 800a938: 05fa0004 .word 0x05fa0004 0800a93c : * bootloader before starting this program. Unfortunately, function * SystemInit() overwrites this change again. * @return none. */ static void VectorBase_Config(void) { 800a93c: b480 push {r7} 800a93e: af00 add r7, sp, #0 * c-startup code. */ extern const unsigned long g_pfnVectors[]; /* Remap the vector table to where the vector table is located for this program. */ SCB->VTOR = (unsigned long)&g_pfnVectors[0]; 800a940: 4b03 ldr r3, [pc, #12] @ (800a950 ) 800a942: 4a04 ldr r2, [pc, #16] @ (800a954 ) 800a944: 609a str r2, [r3, #8] } 800a946: bf00 nop 800a948: 46bd mov sp, r7 800a94a: bc80 pop {r7} 800a94c: 4770 bx lr 800a94e: bf00 nop 800a950: e000ed00 .word 0xe000ed00 800a954: 08008000 .word 0x08008000 0800a958 : uint8_t ED_TraceWarning(uint8_t flag, uint8_t id){ 800a958: b480 push {r7} 800a95a: b085 sub sp, #20 800a95c: af00 add r7, sp, #0 800a95e: 4603 mov r3, r0 800a960: 460a mov r2, r1 800a962: 71fb strb r3, [r7, #7] 800a964: 4613 mov r3, r2 800a966: 71bb strb r3, [r7, #6] static uint8_t memory[32]; if(id > 31) return 0; 800a968: 79bb ldrb r3, [r7, #6] 800a96a: 2b1f cmp r3, #31 800a96c: d901 bls.n 800a972 800a96e: 2300 movs r3, #0 800a970: e00e b.n 800a990 uint8_t result = 0; 800a972: 2300 movs r3, #0 800a974: 73fb strb r3, [r7, #15] if(memory[id] != flag){ 800a976: 79bb ldrb r3, [r7, #6] 800a978: 4a08 ldr r2, [pc, #32] @ (800a99c ) 800a97a: 5cd3 ldrb r3, [r2, r3] 800a97c: 79fa ldrb r2, [r7, #7] 800a97e: 429a cmp r2, r3 800a980: d001 beq.n 800a986 result = 1; 800a982: 2301 movs r3, #1 800a984: 73fb strb r3, [r7, #15] } memory[id] = flag; 800a986: 79bb ldrb r3, [r7, #6] 800a988: 4904 ldr r1, [pc, #16] @ (800a99c ) 800a98a: 79fa ldrb r2, [r7, #7] 800a98c: 54ca strb r2, [r1, r3] return result; 800a98e: 7bfb ldrb r3, [r7, #15] } 800a990: 4618 mov r0, r3 800a992: 3714 adds r7, #20 800a994: 46bd mov sp, r7 800a996: bc80 pop {r7} 800a998: 4770 bx lr 800a99a: bf00 nop 800a99c: 20000878 .word 0x20000878 0800a9a0 : void ED_Delay(uint32_t Delay) { 800a9a0: b580 push {r7, lr} 800a9a2: b084 sub sp, #16 800a9a4: af00 add r7, sp, #0 800a9a6: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800a9a8: f003 fcf2 bl 800e390 800a9ac: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800a9ae: 687b ldr r3, [r7, #4] 800a9b0: 60fb str r3, [r7, #12] if (wait < HAL_MAX_DELAY) 800a9b2: 68fb ldr r3, [r7, #12] 800a9b4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800a9b8: d010 beq.n 800a9dc { wait += (uint32_t)(uwTickFreq); 800a9ba: 4b0f ldr r3, [pc, #60] @ (800a9f8 ) 800a9bc: 781b ldrb r3, [r3, #0] 800a9be: 461a mov r2, r3 800a9c0: 68fb ldr r3, [r7, #12] 800a9c2: 4413 add r3, r2 800a9c4: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait){ 800a9c6: e009 b.n 800a9dc CCS_SerialLoop(); 800a9c8: f001 fa48 bl 800be5c StopButtonControl(); 800a9cc: f000 f816 bl 800a9fc CP_Loop(); 800a9d0: f7ff fc58 bl 800a284 LED_Task(); 800a9d4: f001 f80a bl 800b9ec SC_Task(); 800a9d8: f002 f898 bl 800cb0c while ((HAL_GetTick() - tickstart) < wait){ 800a9dc: f003 fcd8 bl 800e390 800a9e0: 4602 mov r2, r0 800a9e2: 68bb ldr r3, [r7, #8] 800a9e4: 1ad3 subs r3, r2, r3 800a9e6: 68fa ldr r2, [r7, #12] 800a9e8: 429a cmp r2, r3 800a9ea: d8ed bhi.n 800a9c8 } } 800a9ec: bf00 nop 800a9ee: bf00 nop 800a9f0: 3710 adds r7, #16 800a9f2: 46bd mov sp, r7 800a9f4: bd80 pop {r7, pc} 800a9f6: bf00 nop 800a9f8: 2000008c .word 0x2000008c 0800a9fc : static void StopButtonControl(void){ 800a9fc: b580 push {r7, lr} 800a9fe: b082 sub sp, #8 800aa00: af00 add r7, sp, #0 static uint32_t tick; static uint32_t hold_time; static uint8_t stop_btn_fault = 1; uint32_t now = HAL_GetTick(); 800aa02: f003 fcc5 bl 800e390 800aa06: 6078 str r0, [r7, #4] /* Run no faster than once per 10 ms. */ if((now - tick) < 10){ 800aa08: 4b2a ldr r3, [pc, #168] @ (800aab4 ) 800aa0a: 681b ldr r3, [r3, #0] 800aa0c: 687a ldr r2, [r7, #4] 800aa0e: 1ad3 subs r3, r2, r3 800aa10: 2b09 cmp r3, #9 800aa12: d949 bls.n 800aaa8 return; } tick = now; 800aa14: 4a27 ldr r2, [pc, #156] @ (800aab4 ) 800aa16: 687b ldr r3, [r7, #4] 800aa18: 6013 str r3, [r2, #0] uint8_t pressed = !IN_ReadInput(IN_ESTOP); 800aa1a: 2003 movs r0, #3 800aa1c: f7fe ff4c bl 80098b8 800aa20: 4603 mov r3, r0 800aa22: 2b00 cmp r3, #0 800aa24: bf0c ite eq 800aa26: 2301 moveq r3, #1 800aa28: 2300 movne r3, #0 800aa2a: b2db uxtb r3, r3 800aa2c: 70fb strb r3, [r7, #3] if(!pressed){ 800aa2e: 78fb ldrb r3, [r7, #3] 800aa30: 2b00 cmp r3, #0 800aa32: d102 bne.n 800aa3a stop_btn_fault = 0; 800aa34: 4b20 ldr r3, [pc, #128] @ (800aab8 ) 800aa36: 2200 movs r2, #0 800aa38: 701a strb r2, [r3, #0] } if(stop_btn_fault){ 800aa3a: 4b1f ldr r3, [pc, #124] @ (800aab8 ) 800aa3c: 781b ldrb r3, [r3, #0] 800aa3e: 2b00 cmp r3, #0 800aa40: d134 bne.n 800aaac return; } if(pressed){ 800aa42: 78fb ldrb r3, [r7, #3] 800aa44: 2b00 cmp r3, #0 800aa46: d02b beq.n 800aaa0 if(hold_time == 0){ 800aa48: 4b1c ldr r3, [pc, #112] @ (800aabc ) 800aa4a: 681b ldr r3, [r3, #0] 800aa4c: 2b00 cmp r3, #0 800aa4e: d102 bne.n 800aa56 CONN.connControl = CMD_STOP; 800aa50: 4b1b ldr r3, [pc, #108] @ (800aac0 ) 800aa52: 2201 movs r2, #1 800aa54: 701a strb r2, [r3, #0] } hold_time += 10; 800aa56: 4b19 ldr r3, [pc, #100] @ (800aabc ) 800aa58: 681b ldr r3, [r3, #0] 800aa5a: 330a adds r3, #10 800aa5c: 4a17 ldr r2, [pc, #92] @ (800aabc ) 800aa5e: 6013 str r3, [r2, #0] if(hold_time == 5000){ 800aa60: 4b16 ldr r3, [pc, #88] @ (800aabc ) 800aa62: 681b ldr r3, [r3, #0] 800aa64: f241 3288 movw r2, #5000 @ 0x1388 800aa68: 4293 cmp r3, r2 800aa6a: d102 bne.n 800aa72 CONN.connControl = CMD_FORCE_UNLOCK; 800aa6c: 4b14 ldr r3, [pc, #80] @ (800aac0 ) 800aa6e: 2203 movs r2, #3 800aa70: 701a strb r2, [r3, #0] } if(hold_time > 40000){ 800aa72: 4b12 ldr r3, [pc, #72] @ (800aabc ) 800aa74: 681b ldr r3, [r3, #0] 800aa76: f649 4240 movw r2, #40000 @ 0x9c40 800aa7a: 4293 cmp r3, r2 800aa7c: d917 bls.n 800aaae SC_SendPacket(NULL, 0, RESP_SUCCESS); 800aa7e: 2212 movs r2, #18 800aa80: 2100 movs r1, #0 800aa82: 2000 movs r0, #0 800aa84: f002 f99c bl 800cdc0 while(huart2.gState == HAL_UART_STATE_BUSY_TX); 800aa88: bf00 nop 800aa8a: 4b0e ldr r3, [pc, #56] @ (800aac4 ) 800aa8c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800aa90: b2db uxtb r3, r3 800aa92: 2b21 cmp r3, #33 @ 0x21 800aa94: d0f9 beq.n 800aa8a HAL_Delay(10); 800aa96: 200a movs r0, #10 800aa98: f003 fc84 bl 800e3a4 NVIC_SystemReset(); 800aa9c: f7ff ff38 bl 800a910 <__NVIC_SystemReset> } } else{ hold_time = 0; 800aaa0: 4b06 ldr r3, [pc, #24] @ (800aabc ) 800aaa2: 2200 movs r2, #0 800aaa4: 601a str r2, [r3, #0] 800aaa6: e002 b.n 800aaae return; 800aaa8: bf00 nop 800aaaa: e000 b.n 800aaae return; 800aaac: bf00 nop } } 800aaae: 3708 adds r7, #8 800aab0: 46bd mov sp, r7 800aab2: bd80 pop {r7, pc} 800aab4: 20000898 .word 0x20000898 800aab8: 20000008 .word 0x20000008 800aabc: 2000089c .word 0x2000089c 800aac0: 200003b0 .word 0x200003b0 800aac4: 200012e8 .word 0x200012e8 0800aac8 : static void CAN1_MinimalReInit(void) { 800aac8: b580 push {r7, lr} 800aaca: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan1); 800aacc: 480b ldr r0, [pc, #44] @ (800aafc ) 800aace: f004 fbed bl 800f2ac MX_CAN1_Init(); 800aad2: f7ff f865 bl 8009ba0 if (HAL_CAN_Start(&hcan1) != HAL_OK) { 800aad6: 4809 ldr r0, [pc, #36] @ (800aafc ) 800aad8: f004 fba4 bl 800f224 800aadc: 4603 mov r3, r0 800aade: 2b00 cmp r3, #0 800aae0: d001 beq.n 800aae6 Error_Handler(); 800aae2: f000 f8f7 bl 800acd4 } if (HAL_CAN_ActivateNotification(&hcan1, CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) { 800aae6: 2102 movs r1, #2 800aae8: 4804 ldr r0, [pc, #16] @ (800aafc ) 800aaea: f004 fe4c bl 800f786 800aaee: 4603 mov r3, r0 800aaf0: 2b00 cmp r3, #0 800aaf2: d001 beq.n 800aaf8 Error_Handler(); 800aaf4: f000 f8ee bl 800acd4 } } 800aaf8: bf00 nop 800aafa: bd80 pop {r7, pc} 800aafc: 2000035c .word 0x2000035c 0800ab00
: /** * @brief The application entry point. * @retval int */ int main(void) { 800ab00: b580 push {r7, lr} 800ab02: b082 sub sp, #8 800ab04: af02 add r7, sp, #8 /* USER CODE BEGIN 1 */ VectorBase_Config(); 800ab06: f7ff ff19 bl 800a93c /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800ab0a: f003 fbe9 bl 800e2e0 /* USER CODE BEGIN Init */ HAL_RCC_DeInit(); 800ab0e: f005 fffb bl 8010b08 /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800ab12: f000 f86f bl 800abf4 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800ab16: f7ff fdb9 bl 800a68c MX_DMA_Init(); 800ab1a: f7ff fd5b bl 800a5d4 MX_ADC1_Init(); 800ab1e: f7fe fd3b bl 8009598 MX_CAN1_Init(); 800ab22: f7ff f83d bl 8009ba0 MX_CAN2_Init(); 800ab26: f7ff f871 bl 8009c0c MX_RTC_Init(); 800ab2a: f000 fffd bl 800bb28 MX_TIM4_Init(); 800ab2e: f002 ffdf bl 800daf0 MX_USART2_UART_Init(); 800ab32: f003 f95d bl 800ddf0 MX_CRC_Init(); 800ab36: f7ff fbff bl 800a338 MX_UART5_Init(); 800ab3a: f003 f905 bl 800dd48 MX_USART1_UART_Init(); 800ab3e: f003 f92d bl 800dd9c MX_USART3_UART_Init(); 800ab42: f003 f97f bl 800de44 MX_TIM3_Init(); 800ab46: f002 ff45 bl 800d9d4 /* USER CODE BEGIN 2 */ Init_Peripheral(); 800ab4a: f7fe ff2f bl 80099ac LED_Init(); 800ab4e: f000 ff2d bl 800b9ac HAL_Delay(300); 800ab52: f44f 7096 mov.w r0, #300 @ 0x12c 800ab56: f003 fc25 bl 800e3a4 CCS_Init(); 800ab5a: f001 fc17 bl 800c38c SC_Init(); 800ab5e: f001 ffab bl 800cab8 log_printf(LOG_INFO, "CCS module start\n"); 800ab62: 491f ldr r1, [pc, #124] @ (800abe0 ) 800ab64: 2007 movs r0, #7 800ab66: f7ff fcff bl 800a568 ReadVersion(); 800ab6a: f001 ff81 bl 800ca70 log_printf(LOG_INFO, "Serial number: %d\n", infoPacket.serialNumber); 800ab6e: 4b1d ldr r3, [pc, #116] @ (800abe4 ) 800ab70: 881b ldrh r3, [r3, #0] 800ab72: b29b uxth r3, r3 800ab74: 461a mov r2, r3 800ab76: 491c ldr r1, [pc, #112] @ (800abe8 ) 800ab78: 2007 movs r0, #7 800ab7a: f7ff fcf5 bl 800a568 log_printf(LOG_INFO, "Board revision: %d\n", infoPacket.boardVersion); 800ab7e: 4b19 ldr r3, [pc, #100] @ (800abe4 ) 800ab80: 789b ldrb r3, [r3, #2] 800ab82: 461a mov r2, r3 800ab84: 4919 ldr r1, [pc, #100] @ (800abec ) 800ab86: 2007 movs r0, #7 800ab88: f7ff fcee bl 800a568 log_printf(LOG_INFO, "FW version: %d.%d.%d\n", infoPacket.fw_version_major, infoPacket.fw_version_minor, infoPacket.fw_version_patch); 800ab8c: 4b15 ldr r3, [pc, #84] @ (800abe4 ) 800ab8e: 889b ldrh r3, [r3, #4] 800ab90: b29b uxth r3, r3 800ab92: 461a mov r2, r3 800ab94: 4b13 ldr r3, [pc, #76] @ (800abe4 ) 800ab96: 88db ldrh r3, [r3, #6] 800ab98: b29b uxth r3, r3 800ab9a: 4619 mov r1, r3 800ab9c: 4b11 ldr r3, [pc, #68] @ (800abe4 ) 800ab9e: 891b ldrh r3, [r3, #8] 800aba0: b29b uxth r3, r3 800aba2: 9300 str r3, [sp, #0] 800aba4: 460b mov r3, r1 800aba6: 4912 ldr r1, [pc, #72] @ (800abf0 ) 800aba8: 2007 movs r0, #7 800abaa: f7ff fcdd bl 800a568 CAN1_MinimalReInit(); 800abae: f7ff ff8b bl 800aac8 PSU_Init(); 800abb2: f000 f9e5 bl 800af80 CONN_Init(); 800abb6: f7ff f93d bl 8009e34 /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ PSU_ReadWrite(); 800abba: f000 faf3 bl 800b1a4 PSU_Task(); 800abbe: f000 fbb7 bl 800b330 ED_Delay(10); 800abc2: 200a movs r0, #10 800abc4: f7ff feec bl 800a9a0 METER_CalculateEnergy(); 800abc8: f000 f88a bl 800ace0 CONN_Loop(); 800abcc: f7ff f948 bl 8009e60 LED_Write(); 800abd0: f000 fd9e bl 800b710 ED_Delay(10); 800abd4: 200a movs r0, #10 800abd6: f7ff fee3 bl 800a9a0 PSU_ReadWrite(); 800abda: bf00 nop 800abdc: e7ed b.n 800abba 800abde: bf00 nop 800abe0: 08017128 .word 0x08017128 800abe4: 200011b0 .word 0x200011b0 800abe8: 0801713c .word 0x0801713c 800abec: 08017150 .word 0x08017150 800abf0: 08017164 .word 0x08017164 0800abf4 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800abf4: b580 push {r7, lr} 800abf6: b09c sub sp, #112 @ 0x70 800abf8: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800abfa: f107 0338 add.w r3, r7, #56 @ 0x38 800abfe: 2238 movs r2, #56 @ 0x38 800ac00: 2100 movs r1, #0 800ac02: 4618 mov r0, r3 800ac04: f00a f87e bl 8014d04 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800ac08: f107 0324 add.w r3, r7, #36 @ 0x24 800ac0c: 2200 movs r2, #0 800ac0e: 601a str r2, [r3, #0] 800ac10: 605a str r2, [r3, #4] 800ac12: 609a str r2, [r3, #8] 800ac14: 60da str r2, [r3, #12] 800ac16: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 800ac18: 1d3b adds r3, r7, #4 800ac1a: 2220 movs r2, #32 800ac1c: 2100 movs r1, #0 800ac1e: 4618 mov r0, r3 800ac20: f00a f870 bl 8014d04 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; 800ac24: 2305 movs r3, #5 800ac26: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 800ac28: f44f 3380 mov.w r3, #65536 @ 0x10000 800ac2c: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV5; 800ac2e: 2304 movs r3, #4 800ac30: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 800ac32: 2301 movs r3, #1 800ac34: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800ac36: 2301 movs r3, #1 800ac38: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.Prediv1Source = RCC_PREDIV1_SOURCE_PLL2; 800ac3a: f44f 3380 mov.w r3, #65536 @ 0x10000 800ac3e: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800ac40: 2302 movs r3, #2 800ac42: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800ac44: f44f 3380 mov.w r3, #65536 @ 0x10000 800ac48: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 800ac4a: f44f 13e0 mov.w r3, #1835008 @ 0x1c0000 800ac4e: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL2.PLL2State = RCC_PLL2_ON; 800ac50: 2302 movs r3, #2 800ac52: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL2.PLL2MUL = RCC_PLL2_MUL8; 800ac54: f44f 63c0 mov.w r3, #1536 @ 0x600 800ac58: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL2.HSEPrediv2Value = RCC_HSE_PREDIV2_DIV5; 800ac5a: 2340 movs r3, #64 @ 0x40 800ac5c: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800ac5e: f107 0338 add.w r3, r7, #56 @ 0x38 800ac62: 4618 mov r0, r3 800ac64: f006 f820 bl 8010ca8 800ac68: 4603 mov r3, r0 800ac6a: 2b00 cmp r3, #0 800ac6c: d001 beq.n 800ac72 { Error_Handler(); 800ac6e: f000 f831 bl 800acd4 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800ac72: 230f movs r3, #15 800ac74: 627b str r3, [r7, #36] @ 0x24 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800ac76: 2302 movs r3, #2 800ac78: 62bb str r3, [r7, #40] @ 0x28 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800ac7a: 2300 movs r3, #0 800ac7c: 62fb str r3, [r7, #44] @ 0x2c RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 800ac7e: f44f 6380 mov.w r3, #1024 @ 0x400 800ac82: 633b str r3, [r7, #48] @ 0x30 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 800ac84: 2300 movs r3, #0 800ac86: 637b str r3, [r7, #52] @ 0x34 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800ac88: f107 0324 add.w r3, r7, #36 @ 0x24 800ac8c: 2102 movs r1, #2 800ac8e: 4618 mov r0, r3 800ac90: f006 fb20 bl 80112d4 800ac94: 4603 mov r3, r0 800ac96: 2b00 cmp r3, #0 800ac98: d001 beq.n 800ac9e { Error_Handler(); 800ac9a: f000 f81b bl 800acd4 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC; 800ac9e: 2303 movs r3, #3 800aca0: 607b str r3, [r7, #4] PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 800aca2: f44f 7380 mov.w r3, #256 @ 0x100 800aca6: 60bb str r3, [r7, #8] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 800aca8: f44f 4300 mov.w r3, #32768 @ 0x8000 800acac: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 800acae: 1d3b adds r3, r7, #4 800acb0: 4618 mov r0, r3 800acb2: f006 fd05 bl 80116c0 800acb6: 4603 mov r3, r0 800acb8: 2b00 cmp r3, #0 800acba: d001 beq.n 800acc0 { Error_Handler(); 800acbc: f000 f80a bl 800acd4 } /** Configure the Systick interrupt time */ __HAL_RCC_PLLI2S_ENABLE(); 800acc0: 4b03 ldr r3, [pc, #12] @ (800acd0 ) 800acc2: 2201 movs r2, #1 800acc4: 601a str r2, [r3, #0] } 800acc6: bf00 nop 800acc8: 3770 adds r7, #112 @ 0x70 800acca: 46bd mov sp, r7 800accc: bd80 pop {r7, pc} 800acce: bf00 nop 800acd0: 42420070 .word 0x42420070 0800acd4 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 800acd4: b480 push {r7} 800acd6: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 800acd8: b672 cpsid i } 800acda: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 800acdc: bf00 nop 800acde: e7fd b.n 800acdc 0800ace0 : METER_t METER; // Функция для расчета и накопления энергии c дробной частью без счетчиков void METER_CalculateEnergy() { 800ace0: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} 800ace4: b084 sub sp, #16 800ace6: af00 add r7, sp, #0 // Проверяем, что индекс находится в пределах массива METER.online = 0; 800ace8: 4b2c ldr r3, [pc, #176] @ (800ad9c ) 800acea: 2200 movs r2, #0 800acec: 701a strb r2, [r3, #0] if(CONN.connState == Charging){ 800acee: 4b2c ldr r3, [pc, #176] @ (800ada0 ) 800acf0: 785b ldrb r3, [r3, #1] 800acf2: 2b08 cmp r3, #8 800acf4: d103 bne.n 800acfe METER.enable = 1; 800acf6: 4b29 ldr r3, [pc, #164] @ (800ad9c ) 800acf8: 2201 movs r2, #1 800acfa: 761a strb r2, [r3, #24] 800acfc: e002 b.n 800ad04 }else{ METER.enable = 0; 800acfe: 4b27 ldr r3, [pc, #156] @ (800ad9c ) 800ad00: 2200 movs r2, #0 800ad02: 761a strb r2, [r3, #24] } uint32_t currentTick = HAL_GetTick(); // Получаем текущее время в миллисекундах 800ad04: f003 fb44 bl 800e390 800ad08: 60f8 str r0, [r7, #12] uint32_t elapsedTimeMs = currentTick - METER.lastTick; // Вычисляем время, прошедшее с последнего вызова в секундах 800ad0a: 4b24 ldr r3, [pc, #144] @ (800ad9c ) 800ad0c: 685b ldr r3, [r3, #4] 800ad0e: 68fa ldr r2, [r7, #12] 800ad10: 1ad3 subs r3, r2, r3 800ad12: 60bb str r3, [r7, #8] METER.lastTick = currentTick; // Обновляем время последнего вызова для текущего коннектора 800ad14: 4a21 ldr r2, [pc, #132] @ (800ad9c ) 800ad16: 68fb ldr r3, [r7, #12] 800ad18: 6053 str r3, [r2, #4] uint32_t energyWs = CONN.Power * elapsedTimeMs / 1000; // Рассчитываем энергию в ватт-секундах за прошедший промежуток времени 800ad1a: 4b21 ldr r3, [pc, #132] @ (800ada0 ) 800ad1c: f8d3 3003 ldr.w r3, [r3, #3] 800ad20: 68ba ldr r2, [r7, #8] 800ad22: fb02 f303 mul.w r3, r2, r3 800ad26: 4a1f ldr r2, [pc, #124] @ (800ada4 ) 800ad28: fba2 2303 umull r2, r3, r2, r3 800ad2c: 099b lsrs r3, r3, #6 800ad2e: 607b str r3, [r7, #4] //Расчет энергии теперь идет всегда, смещение берем суммарное METER.EnergyPSU_Ws += energyWs; 800ad30: 4b1a ldr r3, [pc, #104] @ (800ad9c ) 800ad32: e9d3 2302 ldrd r2, r3, [r3, #8] 800ad36: 6879 ldr r1, [r7, #4] 800ad38: 2000 movs r0, #0 800ad3a: 460c mov r4, r1 800ad3c: 4605 mov r5, r0 800ad3e: eb12 0804 adds.w r8, r2, r4 800ad42: eb43 0905 adc.w r9, r3, r5 800ad46: 4b15 ldr r3, [pc, #84] @ (800ad9c ) 800ad48: e9c3 8902 strd r8, r9, [r3, #8] // Абсолютное значение энергии разъема складывается из накопленной дробной части и значения со счетчиков METER.AbsoluteEnergy = (uint32_t)METER.EnergyPSU_Ws/3600; //переводим в Вт*час 800ad4c: 4b13 ldr r3, [pc, #76] @ (800ad9c ) 800ad4e: e9d3 2302 ldrd r2, r3, [r3, #8] 800ad52: 4b15 ldr r3, [pc, #84] @ (800ada8 ) 800ad54: fba3 2302 umull r2, r3, r3, r2 800ad58: 0adb lsrs r3, r3, #11 800ad5a: 4a10 ldr r2, [pc, #64] @ (800ad9c ) 800ad5c: 6113 str r3, [r2, #16] if(METER.enable) { 800ad5e: 4b0f ldr r3, [pc, #60] @ (800ad9c ) 800ad60: 7e1b ldrb r3, [r3, #24] 800ad62: 2b00 cmp r3, #0 800ad64: d008 beq.n 800ad78 //enabled state CONN.Energy = METER.AbsoluteEnergy - METER.EnergyOffset;//переводим в Вт*час 800ad66: 4b0d ldr r3, [pc, #52] @ (800ad9c ) 800ad68: 691a ldr r2, [r3, #16] 800ad6a: 4b0c ldr r3, [pc, #48] @ (800ad9c ) 800ad6c: 695b ldr r3, [r3, #20] 800ad6e: 1ad3 subs r3, r2, r3 800ad70: 4a0b ldr r2, [pc, #44] @ (800ada0 ) 800ad72: f8c2 3007 str.w r3, [r2, #7] METER.EnergyOffset = METER.AbsoluteEnergy; } } 800ad76: e00c b.n 800ad92 CONN.Energy = 0; 800ad78: 4b09 ldr r3, [pc, #36] @ (800ada0 ) 800ad7a: 2200 movs r2, #0 800ad7c: 71da strb r2, [r3, #7] 800ad7e: 2200 movs r2, #0 800ad80: 721a strb r2, [r3, #8] 800ad82: 2200 movs r2, #0 800ad84: 725a strb r2, [r3, #9] 800ad86: 2200 movs r2, #0 800ad88: 729a strb r2, [r3, #10] METER.EnergyOffset = METER.AbsoluteEnergy; 800ad8a: 4b04 ldr r3, [pc, #16] @ (800ad9c ) 800ad8c: 691b ldr r3, [r3, #16] 800ad8e: 4a03 ldr r2, [pc, #12] @ (800ad9c ) 800ad90: 6153 str r3, [r2, #20] } 800ad92: bf00 nop 800ad94: 3710 adds r7, #16 800ad96: 46bd mov sp, r7 800ad98: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} 800ad9c: 200008a0 .word 0x200008a0 800ada0: 200003b0 .word 0x200003b0 800ada4: 10624dd3 .word 0x10624dd3 800ada8: 91a2b3c5 .word 0x91a2b3c5 0800adac : extern CAN_HandleTypeDef hcan2; static void PSU_SendCmd(uint8_t source, uint8_t destination, uint8_t cmd, void *data); static void PSU_SwitchState(PSU_State_t state){ 800adac: b580 push {r7, lr} 800adae: b082 sub sp, #8 800adb0: af00 add r7, sp, #0 800adb2: 4603 mov r3, r0 800adb4: 71fb strb r3, [r7, #7] PSU0.state = state; 800adb6: 4a06 ldr r2, [pc, #24] @ (800add0 ) 800adb8: 79fb ldrb r3, [r7, #7] 800adba: 71d3 strb r3, [r2, #7] PSU0.statetick = HAL_GetTick(); 800adbc: f003 fae8 bl 800e390 800adc0: 4603 mov r3, r0 800adc2: 4a03 ldr r2, [pc, #12] @ (800add0 ) 800adc4: 6113 str r3, [r2, #16] } 800adc6: bf00 nop 800adc8: 3708 adds r7, #8 800adca: 46bd mov sp, r7 800adcc: bd80 pop {r7, pc} 800adce: bf00 nop 800add0: 20000904 .word 0x20000904 0800add4 : static uint32_t PSU_StateTime(void){ 800add4: b580 push {r7, lr} 800add6: af00 add r7, sp, #0 return HAL_GetTick() - PSU0.statetick; 800add8: f003 fada bl 800e390 800addc: 4602 mov r2, r0 800adde: 4b02 ldr r3, [pc, #8] @ (800ade8 ) 800ade0: 691b ldr r3, [r3, #16] 800ade2: 1ad3 subs r3, r2, r3 } 800ade4: 4618 mov r0, r3 800ade6: bd80 pop {r7, pc} 800ade8: 20000904 .word 0x20000904 0800adec : ISR_FAST void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan){ 800adec: b538 push {r3, r4, r5, lr} static CAN_RxHeaderTypeDef RxHeader; static uint8_t RxData[8] = {0,}; CanId_t CanId; if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO1, &RxHeader, RxData) == HAL_OK) 800adee: 4c42 ldr r4, [pc, #264] @ (800aef8 ) 800adf0: 4d42 ldr r5, [pc, #264] @ (800aefc ) 800adf2: 4623 mov r3, r4 800adf4: 462a mov r2, r5 800adf6: 2101 movs r1, #1 800adf8: f004 fba4 bl 800f544 800adfc: b910 cbnz r0, 800ae04 { memcpy(&CanId, &RxHeader.ExtId, sizeof(CanId_t)); 800adfe: 686d ldr r5, [r5, #4] /* Для DC30 поддерживается только один силовой модуль (source == 0) */ if(CanId.source != 0) return; 800ae00: b2eb uxtb r3, r5 800ae02: b103 cbz r3, 800ae06 CONN.outputEnabled = PSU0.PSU_enabled; } } } } } 800ae04: bd38 pop {r3, r4, r5, pc} can_lastpacket = HAL_GetTick(); 800ae06: f003 fac3 bl 800e390 if(CanId.command==0x02){ 800ae0a: f3c5 4505 ubfx r5, r5, #16, #6 can_lastpacket = HAL_GetTick(); 800ae0e: 4b3c ldr r3, [pc, #240] @ (800af00 ) if(CanId.command==0x02){ 800ae10: 2d02 cmp r5, #2 can_lastpacket = HAL_GetTick(); 800ae12: 6018 str r0, [r3, #0] if(CanId.command==0x02){ 800ae14: d013 beq.n 800ae3e if(CanId.command==0x04){ 800ae16: 2d04 cmp r5, #4 800ae18: d117 bne.n 800ae4a memcpy(&PSU_04, RxData, 8); 800ae1a: e894 0003 ldmia.w r4, {r0, r1} 800ae1e: 4b39 ldr r3, [pc, #228] @ (800af04 ) PSU0.tempAmbient = PSU_04.moduleTemperature; 800ae20: 4a39 ldr r2, [pc, #228] @ (800af08 ) memcpy(&PSU_04, RxData, 8); 800ae22: e883 0003 stmia.w r3, {r0, r1} PSU0.status0.raw = PSU_04.modularForm0; 800ae26: 7a18 ldrb r0, [r3, #8] PSU0.tempAmbient = PSU_04.moduleTemperature; 800ae28: 791c ldrb r4, [r3, #4] PSU0.status1.raw = PSU_04.modularForm1; 800ae2a: 79d9 ldrb r1, [r3, #7] PSU0.status2.raw = PSU_04.modularForm2; 800ae2c: 799b ldrb r3, [r3, #6] PSU0.tempAmbient = PSU_04.moduleTemperature; 800ae2e: 6214 str r4, [r2, #32] PSU0.status0.raw = PSU_04.modularForm0; 800ae30: f882 0024 strb.w r0, [r2, #36] @ 0x24 PSU0.status1.raw = PSU_04.modularForm1; 800ae34: f882 1025 strb.w r1, [r2, #37] @ 0x25 PSU0.status2.raw = PSU_04.modularForm2; 800ae38: f882 3026 strb.w r3, [r2, #38] @ 0x26 } 800ae3c: bd38 pop {r3, r4, r5, pc} memcpy(&PSU_02, RxData, 8); 800ae3e: 4b33 ldr r3, [pc, #204] @ (800af0c ) 800ae40: e894 0003 ldmia.w r4, {r0, r1} 800ae44: e883 0003 stmia.w r3, {r0, r1} } 800ae48: bd38 pop {r3, r4, r5, pc} if(CanId.command==0x06){ 800ae4a: 2d06 cmp r5, #6 800ae4c: d111 bne.n 800ae72 memcpy(&PSU_06, RxData, 8); 800ae4e: e894 0003 ldmia.w r4, {r0, r1} 800ae52: 4b2f ldr r3, [pc, #188] @ (800af10 ) 800ae54: e883 0003 stmia.w r3, {r0, r1} PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800ae58: 8818 ldrh r0, [r3, #0] PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800ae5a: 8859 ldrh r1, [r3, #2] PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ae5c: 889a ldrh r2, [r3, #4] PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800ae5e: ba40 rev16 r0, r0 PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800ae60: ba49 rev16 r1, r1 PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ae62: ba52 rev16 r2, r2 PSU_06.VAB = PSU_06.VABLo+(PSU_06.VABHi<<8); 800ae64: b280 uxth r0, r0 PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800ae66: b289 uxth r1, r1 PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ae68: b292 uxth r2, r2 PSU_06.VBC = PSU_06.VBCLo+(PSU_06.VBCHi<<8); 800ae6a: e9c3 0102 strd r0, r1, [r3, #8] PSU_06.VCA = PSU_06.VCALo+(PSU_06.VCAHi<<8); 800ae6e: 611a str r2, [r3, #16] } 800ae70: bd38 pop {r3, r4, r5, pc} if(CanId.command==0x08){ 800ae72: 2d08 cmp r5, #8 800ae74: d03a beq.n 800aeec if(CanId.command==0x09){ 800ae76: 2d09 cmp r5, #9 800ae78: d1c4 bne.n 800ae04 memcpy(&PSU_09, RxData, 8); 800ae7a: e894 0003 ldmia.w r4, {r0, r1} PSU0.temperature = PSU_04.moduleTemperature; 800ae7e: 4b21 ldr r3, [pc, #132] @ (800af04 ) memcpy(&PSU_09, RxData, 8); 800ae80: 4d24 ldr r5, [pc, #144] @ (800af14 ) PSU0.outputVoltage = v; 800ae82: 4c21 ldr r4, [pc, #132] @ (800af08 ) PSU0.temperature = PSU_04.moduleTemperature; 800ae84: f893 c004 ldrb.w ip, [r3, #4] uint16_t v = PSU_09.moduleNVoltage / 1000; 800ae88: 4a23 ldr r2, [pc, #140] @ (800af18 ) memcpy(&PSU_09, RxData, 8); 800ae8a: e885 0003 stmia.w r5, {r0, r1} PSU_09.moduleNCurrent = PSU_09.moduleNCurrent_[3]; 800ae8e: ba00 rev r0, r0 PSU0.temperature = PSU_04.moduleTemperature; 800ae90: f884 c006 strb.w ip, [r4, #6] uint16_t v = PSU_09.moduleNVoltage / 1000; 800ae94: fba2 c200 umull ip, r2, r2, r0 800ae98: ba09 rev r1, r1 PSU_09.moduleNVoltage |= PSU_09.moduleNVoltage_[0]<<24; 800ae9a: e9c5 0102 strd r0, r1, [r5, #8] uint16_t v = PSU_09.moduleNVoltage / 1000; 800ae9e: f3c2 108f ubfx r0, r2, #6, #16 PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800aea2: 2813 cmp r0, #19 PSU0.online = 1; 800aea4: f04f 0e01 mov.w lr, #1 PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800aea8: bf94 ite ls 800aeaa: 2500 movls r5, #0 800aeac: 2501 movhi r5, #1 int16_t i = PSU_09.moduleNCurrent / 100; 800aeae: 4b1b ldr r3, [pc, #108] @ (800af1c ) PSU0.online = 1; 800aeb0: f884 e008 strb.w lr, [r4, #8] int16_t i = PSU_09.moduleNCurrent / 100; 800aeb4: fba3 c301 umull ip, r3, r3, r1 if(PSU0.state >= PSU_READY){ 800aeb8: 79e1 ldrb r1, [r4, #7] int16_t i = PSU_09.moduleNCurrent / 100; 800aeba: 095b lsrs r3, r3, #5 if(PSU0.state >= PSU_READY){ 800aebc: 4571 cmp r1, lr PSU0.outputVoltage = v; 800aebe: 8060 strh r0, [r4, #2] int16_t i = PSU_09.moduleNCurrent / 100; 800aec0: 80a3 strh r3, [r4, #4] uint16_t v = PSU_09.moduleNVoltage / 1000; 800aec2: ea4f 1292 mov.w r2, r2, lsr #6 PSU0.PSU_enabled = (v >= PSU_VOLTAGE_THRESHOLD); 800aec6: 72a5 strb r5, [r4, #10] if(PSU0.state >= PSU_READY){ 800aec8: d99c bls.n 800ae04 CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800aeca: b299 uxth r1, r3 800aecc: b292 uxth r2, r2 800aece: fb01 f202 mul.w r2, r1, r2 800aed2: 4c13 ldr r4, [pc, #76] @ (800af20 ) CONN.MeasuredVoltage = PSU0.outputVoltage; 800aed4: 4913 ldr r1, [pc, #76] @ (800af24 ) CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800aed6: fba4 4202 umull r4, r2, r4, r2 CONN.MeasuredCurrent = PSU0.outputCurrent; 800aeda: f8a1 3015 strh.w r3, [r1, #21] CONN.outputEnabled = PSU0.PSU_enabled; 800aede: 760d strb r5, [r1, #24] CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800aee0: 08d3 lsrs r3, r2, #3 CONN.MeasuredVoltage = PSU0.outputVoltage; 800aee2: f8a1 0013 strh.w r0, [r1, #19] CONN.Power = CONN.MeasuredCurrent * CONN.MeasuredVoltage / 10; 800aee6: f8c1 3003 str.w r3, [r1, #3] } 800aeea: bd38 pop {r3, r4, r5, pc} memcpy(&PSU_08, RxData, 8); 800aeec: 4b0e ldr r3, [pc, #56] @ (800af28 ) 800aeee: e894 0003 ldmia.w r4, {r0, r1} 800aef2: e883 0003 stmia.w r3, {r0, r1} } 800aef6: bd38 pop {r3, r4, r5, pc} 800aef8: 2000094c .word 0x2000094c 800aefc: 20000930 .word 0x20000930 800af00: 2000092c .word 0x2000092c 800af04: 200008cc .word 0x200008cc 800af08: 20000904 .word 0x20000904 800af0c: 200008c0 .word 0x200008c0 800af10: 200008d8 .word 0x200008d8 800af14: 200008f4 .word 0x200008f4 800af18: 10624dd3 .word 0x10624dd3 800af1c: 51eb851f .word 0x51eb851f 800af20: cccccccd .word 0xcccccccd 800af24: 200003b0 .word 0x200003b0 800af28: 200008ec .word 0x200008ec 0800af2c : void PSU_CAN_FilterInit(){ 800af2c: b580 push {r7, lr} 800af2e: b08a sub sp, #40 @ 0x28 800af30: af00 add r7, sp, #0 CAN_FilterTypeDef sFilterConfig; sFilterConfig.FilterBank = 14; 800af32: 230e movs r3, #14 800af34: 617b str r3, [r7, #20] sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; 800af36: 2300 movs r3, #0 800af38: 61bb str r3, [r7, #24] sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; 800af3a: 2301 movs r3, #1 800af3c: 61fb str r3, [r7, #28] sFilterConfig.FilterIdHigh = 0x0000; 800af3e: 2300 movs r3, #0 800af40: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = 0x0000; 800af42: 2300 movs r3, #0 800af44: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 800af46: 2300 movs r3, #0 800af48: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = 0x0000; 800af4a: 2300 movs r3, #0 800af4c: 60fb str r3, [r7, #12] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; 800af4e: 2300 movs r3, #0 800af50: 613b str r3, [r7, #16] sFilterConfig.FilterActivation = ENABLE; 800af52: 2301 movs r3, #1 800af54: 623b str r3, [r7, #32] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; 800af56: 2301 movs r3, #1 800af58: 613b str r3, [r7, #16] sFilterConfig.SlaveStartFilterBank = 14; 800af5a: 230e movs r3, #14 800af5c: 627b str r3, [r7, #36] @ 0x24 if(HAL_CAN_ConfigFilter(&hcan2, &sFilterConfig) != HAL_OK) 800af5e: 463b mov r3, r7 800af60: 4619 mov r1, r3 800af62: 4806 ldr r0, [pc, #24] @ (800af7c ) 800af64: f004 f87e bl 800f064 800af68: 4603 mov r3, r0 800af6a: 2b00 cmp r3, #0 800af6c: d001 beq.n 800af72 { Error_Handler(); 800af6e: f7ff feb1 bl 800acd4 } } 800af72: bf00 nop 800af74: 3728 adds r7, #40 @ 0x28 800af76: 46bd mov sp, r7 800af78: bd80 pop {r7, pc} 800af7a: bf00 nop 800af7c: 20000384 .word 0x20000384 0800af80 : void PSU_Init(){ 800af80: b580 push {r7, lr} 800af82: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan2); 800af84: 4815 ldr r0, [pc, #84] @ (800afdc ) 800af86: f004 f991 bl 800f2ac MX_CAN2_Init(); 800af8a: f7fe fe3f bl 8009c0c PSU_CAN_FilterInit(); 800af8e: f7ff ffcd bl 800af2c HAL_CAN_Start(&hcan2); 800af92: 4812 ldr r0, [pc, #72] @ (800afdc ) 800af94: f004 f946 bl 800f224 HAL_CAN_ActivateNotification(&hcan2, CAN_IT_RX_FIFO1_MSG_PENDING /* | CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | CAN_IT_TX_MAILBOX_EMPTY*/); 800af98: 2110 movs r1, #16 800af9a: 4810 ldr r0, [pc, #64] @ (800afdc ) 800af9c: f004 fbf3 bl 800f786 memset(&PSU0, 0, sizeof(PSU0)); 800afa0: 2228 movs r2, #40 @ 0x28 800afa2: 2100 movs r1, #0 800afa4: 480e ldr r0, [pc, #56] @ (800afe0 ) 800afa6: f009 fead bl 8014d04 PSU0.state = PSU_UNREADY; 800afaa: 4b0d ldr r3, [pc, #52] @ (800afe0 ) 800afac: 2200 movs r2, #0 800afae: 71da strb r2, [r3, #7] PSU0.statetick = HAL_GetTick(); 800afb0: f003 f9ee bl 800e390 800afb4: 4603 mov r3, r0 800afb6: 4a0a ldr r2, [pc, #40] @ (800afe0 ) 800afb8: 6113 str r3, [r2, #16] PSU0.power_limit = PSU_MAX_POWER; // kW 800afba: 4b09 ldr r3, [pc, #36] @ (800afe0 ) 800afbc: f649 4240 movw r2, #40000 @ 0x9c40 800afc0: 615a str r2, [r3, #20] PSU0.hv_mode = 0; 800afc2: 4b07 ldr r3, [pc, #28] @ (800afe0 ) 800afc4: 2200 movs r2, #0 800afc6: 761a strb r2, [r3, #24] PSU0.hv_tick = 0; 800afc8: 4b05 ldr r3, [pc, #20] @ (800afe0 ) 800afca: 2200 movs r2, #0 800afcc: 61da str r2, [r3, #28] PSU_Enable(0, 0); 800afce: 2100 movs r1, #0 800afd0: 2000 movs r0, #0 800afd2: f000 f807 bl 800afe4 } 800afd6: bf00 nop 800afd8: bd80 pop {r7, pc} 800afda: bf00 nop 800afdc: 20000384 .word 0x20000384 800afe0: 20000904 .word 0x20000904 0800afe4 : void PSU_Enable(uint8_t addr, uint8_t enable){ 800afe4: b580 push {r7, lr} 800afe6: b084 sub sp, #16 800afe8: af00 add r7, sp, #0 800afea: 4603 mov r3, r0 800afec: 460a mov r2, r1 800afee: 71fb strb r3, [r7, #7] 800aff0: 4613 mov r3, r2 800aff2: 71bb strb r3, [r7, #6] PSU_1A_t data; memset(&data, 0, sizeof(data)); 800aff4: f107 0308 add.w r3, r7, #8 800aff8: 2208 movs r2, #8 800affa: 2100 movs r1, #0 800affc: 4618 mov r0, r3 800affe: f009 fe81 bl 8014d04 /* Для DC30 поддерживается только один модуль с адресом 0 */ if(addr != 0) return; 800b002: 79fb ldrb r3, [r7, #7] 800b004: 2b00 cmp r3, #0 800b006: d115 bne.n 800b034 if(PSU0.online == 0) return; 800b008: 4b0d ldr r3, [pc, #52] @ (800b040 ) 800b00a: 7a1b ldrb r3, [r3, #8] 800b00c: 2b00 cmp r3, #0 800b00e: d013 beq.n 800b038 data.enable = !enable; 800b010: 79bb ldrb r3, [r7, #6] 800b012: 2b00 cmp r3, #0 800b014: bf0c ite eq 800b016: 2301 moveq r3, #1 800b018: 2300 movne r3, #0 800b01a: b2db uxtb r3, r3 800b01c: 723b strb r3, [r7, #8] PSU_SendCmd(0xF0, addr, 0x1A, &data); 800b01e: f107 0308 add.w r3, r7, #8 800b022: 79f9 ldrb r1, [r7, #7] 800b024: 221a movs r2, #26 800b026: 20f0 movs r0, #240 @ 0xf0 800b028: f000 f866 bl 800b0f8 ED_Delay(CAN_DELAY); 800b02c: 2014 movs r0, #20 800b02e: f7ff fcb7 bl 800a9a0 800b032: e002 b.n 800b03a if(addr != 0) return; 800b034: bf00 nop 800b036: e000 b.n 800b03a if(PSU0.online == 0) return; 800b038: bf00 nop } 800b03a: 3710 adds r7, #16 800b03c: 46bd mov sp, r7 800b03e: bd80 pop {r7, pc} 800b040: 20000904 .word 0x20000904 0800b044 : memset(&data, 0, sizeof(data)); data.enable = !enable; if(addr != 0) return; PSU_SendCmd(0xF0, addr, 0x1D, &data); } void PSU_SetVoltageCurrent(uint8_t addr, uint16_t voltage, uint16_t current){ 800b044: b580 push {r7, lr} 800b046: b086 sub sp, #24 800b048: af00 add r7, sp, #0 800b04a: 4603 mov r3, r0 800b04c: 71fb strb r3, [r7, #7] 800b04e: 460b mov r3, r1 800b050: 80bb strh r3, [r7, #4] 800b052: 4613 mov r3, r2 800b054: 807b strh r3, [r7, #2] PSU_1C_t data; memset(&data, 0, sizeof(data)); 800b056: f107 0308 add.w r3, r7, #8 800b05a: 2208 movs r2, #8 800b05c: 2100 movs r1, #0 800b05e: 4618 mov r0, r3 800b060: f009 fe50 bl 8014d04 if(addr != 0) return; 800b064: 79fb ldrb r3, [r7, #7] 800b066: 2b00 cmp r3, #0 800b068: d140 bne.n 800b0ec if(voltage 800b070: 2396 movs r3, #150 @ 0x96 800b072: 80bb strh r3, [r7, #4] if((PSU0.hv_mode==0) && voltage>499) voltage = 499; 800b074: 4b1f ldr r3, [pc, #124] @ (800b0f4 ) 800b076: 7e1b ldrb r3, [r3, #24] 800b078: 2b00 cmp r3, #0 800b07a: d106 bne.n 800b08a 800b07c: 88bb ldrh r3, [r7, #4] 800b07e: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b082: d302 bcc.n 800b08a 800b084: f240 13f3 movw r3, #499 @ 0x1f3 800b088: 80bb strh r3, [r7, #4] uint32_t current_ma = current * 100; 800b08a: 887b ldrh r3, [r7, #2] 800b08c: 2264 movs r2, #100 @ 0x64 800b08e: fb02 f303 mul.w r3, r2, r3 800b092: 617b str r3, [r7, #20] uint32_t voltage_mv = voltage * 1000; 800b094: 88bb ldrh r3, [r7, #4] 800b096: f44f 727a mov.w r2, #1000 @ 0x3e8 800b09a: fb02 f303 mul.w r3, r2, r3 800b09e: 613b str r3, [r7, #16] data.moduleCurrentTotal[0] = (current_ma >> 24) & 0xFF; 800b0a0: 697b ldr r3, [r7, #20] 800b0a2: 0e1b lsrs r3, r3, #24 800b0a4: b2db uxtb r3, r3 800b0a6: 733b strb r3, [r7, #12] data.moduleCurrentTotal[1] = (current_ma >> 16) & 0xFF; 800b0a8: 697b ldr r3, [r7, #20] 800b0aa: 0c1b lsrs r3, r3, #16 800b0ac: b2db uxtb r3, r3 800b0ae: 737b strb r3, [r7, #13] data.moduleCurrentTotal[2] = (current_ma >> 8) & 0xFF; 800b0b0: 697b ldr r3, [r7, #20] 800b0b2: 0a1b lsrs r3, r3, #8 800b0b4: b2db uxtb r3, r3 800b0b6: 73bb strb r3, [r7, #14] data.moduleCurrentTotal[3] = (current_ma >> 0) & 0xFF; 800b0b8: 697b ldr r3, [r7, #20] 800b0ba: b2db uxtb r3, r3 800b0bc: 73fb strb r3, [r7, #15] data.moduleVoltage[0] = (voltage_mv >> 24) & 0xFF; 800b0be: 693b ldr r3, [r7, #16] 800b0c0: 0e1b lsrs r3, r3, #24 800b0c2: b2db uxtb r3, r3 800b0c4: 723b strb r3, [r7, #8] data.moduleVoltage[1] = (voltage_mv >> 16) & 0xFF; 800b0c6: 693b ldr r3, [r7, #16] 800b0c8: 0c1b lsrs r3, r3, #16 800b0ca: b2db uxtb r3, r3 800b0cc: 727b strb r3, [r7, #9] data.moduleVoltage[2] = (voltage_mv >> 8) & 0xFF; 800b0ce: 693b ldr r3, [r7, #16] 800b0d0: 0a1b lsrs r3, r3, #8 800b0d2: b2db uxtb r3, r3 800b0d4: 72bb strb r3, [r7, #10] data.moduleVoltage[3] = (voltage_mv >> 0) & 0xFF; 800b0d6: 693b ldr r3, [r7, #16] 800b0d8: b2db uxtb r3, r3 800b0da: 72fb strb r3, [r7, #11] PSU_SendCmd(0xF0, addr, 0x1C, &data); 800b0dc: f107 0308 add.w r3, r7, #8 800b0e0: 79f9 ldrb r1, [r7, #7] 800b0e2: 221c movs r2, #28 800b0e4: 20f0 movs r0, #240 @ 0xf0 800b0e6: f000 f807 bl 800b0f8 800b0ea: e000 b.n 800b0ee if(addr != 0) return; 800b0ec: bf00 nop } 800b0ee: 3718 adds r7, #24 800b0f0: 46bd mov sp, r7 800b0f2: bd80 pop {r7, pc} 800b0f4: 20000904 .word 0x20000904 0800b0f8 : void PSU_SendCmd(uint8_t source, uint8_t destination, uint8_t cmd, void *data){ 800b0f8: b580 push {r7, lr} 800b0fa: b08c sub sp, #48 @ 0x30 800b0fc: af00 add r7, sp, #0 800b0fe: 603b str r3, [r7, #0] 800b100: 4603 mov r3, r0 800b102: 71fb strb r3, [r7, #7] 800b104: 460b mov r3, r1 800b106: 71bb strb r3, [r7, #6] 800b108: 4613 mov r3, r2 800b10a: 717b strb r3, [r7, #5] CanId_t CanId; CanId.source = source; 800b10c: 79fb ldrb r3, [r7, #7] 800b10e: f887 3028 strb.w r3, [r7, #40] @ 0x28 CanId.destination = destination; 800b112: 79bb ldrb r3, [r7, #6] 800b114: f887 3029 strb.w r3, [r7, #41] @ 0x29 CanId.command = cmd; 800b118: 797b ldrb r3, [r7, #5] 800b11a: f003 033f and.w r3, r3, #63 @ 0x3f 800b11e: b2da uxtb r2, r3 800b120: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 800b124: f362 0305 bfi r3, r2, #0, #6 800b128: f887 302a strb.w r3, [r7, #42] @ 0x2a CanId.device = 0x0A; 800b12c: 8d7b ldrh r3, [r7, #42] @ 0x2a 800b12e: 220a movs r2, #10 800b130: f362 1389 bfi r3, r2, #6, #4 800b134: 857b strh r3, [r7, #42] @ 0x2a int8_t retry_counter = 10; 800b136: 230a movs r3, #10 800b138: f887 302f strb.w r3, [r7, #47] @ 0x2f CAN_TxHeaderTypeDef tx_header; uint32_t tx_mailbox; HAL_StatusTypeDef CAN_result; memcpy(&tx_header.ExtId, &CanId, sizeof(CanId_t)); 800b13c: 6abb ldr r3, [r7, #40] @ 0x28 800b13e: 617b str r3, [r7, #20] tx_header.RTR = CAN_RTR_DATA; 800b140: 2300 movs r3, #0 800b142: 61fb str r3, [r7, #28] tx_header.IDE = CAN_ID_EXT; 800b144: 2304 movs r3, #4 800b146: 61bb str r3, [r7, #24] tx_header.DLC = 8; 800b148: 2308 movs r3, #8 800b14a: 623b str r3, [r7, #32] while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800b14c: e01e b.n 800b18c if (HAL_CAN_GetTxMailboxesFreeLevel(&hcan2) > 0){ 800b14e: 4814 ldr r0, [pc, #80] @ (800b1a0 ) 800b150: f004 f9c4 bl 800f4dc 800b154: 4603 mov r3, r0 800b156: 2b00 cmp r3, #0 800b158: d00e beq.n 800b178 /* отправка сообщения */ CAN_result = HAL_CAN_AddTxMessage(&hcan2, &tx_header, (uint8_t*)data, &tx_mailbox); 800b15a: f107 030c add.w r3, r7, #12 800b15e: f107 0110 add.w r1, r7, #16 800b162: 683a ldr r2, [r7, #0] 800b164: 480e ldr r0, [pc, #56] @ (800b1a0 ) 800b166: f004 f8ea bl 800f33e 800b16a: 4603 mov r3, r0 800b16c: f887 302e strb.w r3, [r7, #46] @ 0x2e /* если отправка удалась, выход */ if(CAN_result == HAL_OK) { 800b170: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 800b174: 2b00 cmp r3, #0 800b176: d00e beq.n 800b196 return; } } ED_Delay(1); 800b178: 2001 movs r0, #1 800b17a: f7ff fc11 bl 800a9a0 retry_counter--; 800b17e: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800b182: b2db uxtb r3, r3 800b184: 3b01 subs r3, #1 800b186: b2db uxtb r3, r3 800b188: f887 302f strb.w r3, [r7, #47] @ 0x2f while(retry_counter>0){ //если буфер полон, ждем пока он освободится 800b18c: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 800b190: 2b00 cmp r3, #0 800b192: dcdc bgt.n 800b14e 800b194: e000 b.n 800b198 return; 800b196: bf00 nop } } 800b198: 3730 adds r7, #48 @ 0x30 800b19a: 46bd mov sp, r7 800b19c: bd80 pop {r7, pc} 800b19e: bf00 nop 800b1a0: 20000384 .word 0x20000384 0800b1a4 : void PSU_ReadWrite(){ 800b1a4: b580 push {r7, lr} 800b1a6: b082 sub sp, #8 800b1a8: af00 add r7, sp, #0 uint8_t zero_data[8] = {0,0,0,0,0,0,0,0}; 800b1aa: 463b mov r3, r7 800b1ac: 2200 movs r2, #0 800b1ae: 601a str r2, [r3, #0] 800b1b0: 605a str r2, [r3, #4] PSU_SendCmd(0xF0, 0, 0x04, zero_data);ED_Delay(CAN_DELAY); 800b1b2: 463b mov r3, r7 800b1b4: 2204 movs r2, #4 800b1b6: 2100 movs r1, #0 800b1b8: 20f0 movs r0, #240 @ 0xf0 800b1ba: f7ff ff9d bl 800b0f8 800b1be: 2014 movs r0, #20 800b1c0: f7ff fbee bl 800a9a0 PSU_SendCmd(0xF0, 0, 0x06, zero_data);ED_Delay(CAN_DELAY); 800b1c4: 463b mov r3, r7 800b1c6: 2206 movs r2, #6 800b1c8: 2100 movs r1, #0 800b1ca: 20f0 movs r0, #240 @ 0xf0 800b1cc: f7ff ff94 bl 800b0f8 800b1d0: 2014 movs r0, #20 800b1d2: f7ff fbe5 bl 800a9a0 // PSU_SendCmd(0xF0, 0, 0x08, zero_data);ED_Delay(CAN_DELAY); PSU_SendCmd(0xF0, 0, 0x09, zero_data);ED_Delay(CAN_DELAY); 800b1d6: 463b mov r3, r7 800b1d8: 2209 movs r2, #9 800b1da: 2100 movs r1, #0 800b1dc: 20f0 movs r0, #240 @ 0xf0 800b1de: f7ff ff8b bl 800b0f8 800b1e2: 2014 movs r0, #20 800b1e4: f7ff fbdc bl 800a9a0 // Power Limit if ((CONN.WantedCurrent/10) * CONN.MeasuredVoltage > PSU0.power_limit){ 800b1e8: 4b4d ldr r3, [pc, #308] @ (800b320 ) 800b1ea: f8b3 301b ldrh.w r3, [r3, #27] 800b1ee: b29b uxth r3, r3 800b1f0: 4a4c ldr r2, [pc, #304] @ (800b324 ) 800b1f2: fba2 2303 umull r2, r3, r2, r3 800b1f6: 08db lsrs r3, r3, #3 800b1f8: b29b uxth r3, r3 800b1fa: 461a mov r2, r3 800b1fc: 4b48 ldr r3, [pc, #288] @ (800b320 ) 800b1fe: f8b3 3013 ldrh.w r3, [r3, #19] 800b202: b29b uxth r3, r3 800b204: fb02 f303 mul.w r3, r2, r3 800b208: 461a mov r2, r3 800b20a: 4b47 ldr r3, [pc, #284] @ (800b328 ) 800b20c: 695b ldr r3, [r3, #20] 800b20e: 429a cmp r2, r3 800b210: d911 bls.n 800b236 CONN.RequestedCurrent = PSU0.power_limit * 10 / CONN.MeasuredVoltage; 800b212: 4b45 ldr r3, [pc, #276] @ (800b328 ) 800b214: 695a ldr r2, [r3, #20] 800b216: 4613 mov r3, r2 800b218: 009b lsls r3, r3, #2 800b21a: 4413 add r3, r2 800b21c: 005b lsls r3, r3, #1 800b21e: 461a mov r2, r3 800b220: 4b3f ldr r3, [pc, #252] @ (800b320 ) 800b222: f8b3 3013 ldrh.w r3, [r3, #19] 800b226: b29b uxth r3, r3 800b228: fbb2 f3f3 udiv r3, r2, r3 800b22c: b29a uxth r2, r3 800b22e: 4b3c ldr r3, [pc, #240] @ (800b320 ) 800b230: f8a3 2011 strh.w r2, [r3, #17] 800b234: e006 b.n 800b244 }else{ CONN.RequestedCurrent = CONN.WantedCurrent; 800b236: 4b3a ldr r3, [pc, #232] @ (800b320 ) 800b238: f8b3 301b ldrh.w r3, [r3, #27] 800b23c: b29a uxth r2, r3 800b23e: 4b38 ldr r3, [pc, #224] @ (800b320 ) 800b240: f8a3 2011 strh.w r2, [r3, #17] } if(CONN.RequestedCurrent > (PSU_MAX_CURRENT*10)){ 800b244: 4b36 ldr r3, [pc, #216] @ (800b320 ) 800b246: f8b3 3011 ldrh.w r3, [r3, #17] 800b24a: b29b uxth r3, r3 800b24c: f240 5232 movw r2, #1330 @ 0x532 800b250: 4293 cmp r3, r2 800b252: d908 bls.n 800b266 CONN.RequestedCurrent = PSU_MAX_CURRENT*10; 800b254: 4b32 ldr r3, [pc, #200] @ (800b320 ) 800b256: 2200 movs r2, #0 800b258: f042 0232 orr.w r2, r2, #50 @ 0x32 800b25c: 745a strb r2, [r3, #17] 800b25e: 2200 movs r2, #0 800b260: f042 0205 orr.w r2, r2, #5 800b264: 749a strb r2, [r3, #18] } CONN.RequestedPower = CONN.RequestedCurrent * CONN.RequestedVoltage / 10; 800b266: 4b2e ldr r3, [pc, #184] @ (800b320 ) 800b268: f8b3 3011 ldrh.w r3, [r3, #17] 800b26c: b29b uxth r3, r3 800b26e: 461a mov r2, r3 800b270: 4b2b ldr r3, [pc, #172] @ (800b320 ) 800b272: f8b3 300f ldrh.w r3, [r3, #15] 800b276: b29b uxth r3, r3 800b278: fb02 f303 mul.w r3, r2, r3 800b27c: 4a2b ldr r2, [pc, #172] @ (800b32c ) 800b27e: fb82 1203 smull r1, r2, r2, r3 800b282: 1092 asrs r2, r2, #2 800b284: 17db asrs r3, r3, #31 800b286: 1ad3 subs r3, r2, r3 800b288: 461a mov r2, r3 800b28a: 4b25 ldr r3, [pc, #148] @ (800b320 ) 800b28c: f8c3 200b str.w r2, [r3, #11] if(PSU0.ready){ 800b290: 4b25 ldr r3, [pc, #148] @ (800b328 ) 800b292: 7a5b ldrb r3, [r3, #9] 800b294: 2b00 cmp r3, #0 800b296: d03e beq.n 800b316 if (CONN.RequestedVoltage == FAKE_EVREQ_VOLTAGE_V) { 800b298: 4b21 ldr r3, [pc, #132] @ (800b320 ) 800b29a: f8b3 300f ldrh.w r3, [r3, #15] 800b29e: b29b uxth r3, r3 800b2a0: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b2a4: d106 bne.n 800b2b4 PSU_SetVoltageCurrent(0, (uint16_t)FAKE_PSU_VOLTAGE_V, (uint16_t)FAKE_PSU_CURRENT_0P1A); 800b2a6: 220a movs r2, #10 800b2a8: f44f 7196 mov.w r1, #300 @ 0x12c 800b2ac: 2000 movs r0, #0 800b2ae: f7ff fec9 bl 800b044 800b2b2: e00b b.n 800b2cc }else{ PSU_SetVoltageCurrent(0, CONN.RequestedVoltage, CONN.RequestedCurrent); // Normal mode 800b2b4: 4b1a ldr r3, [pc, #104] @ (800b320 ) 800b2b6: f8b3 300f ldrh.w r3, [r3, #15] 800b2ba: b29b uxth r3, r3 800b2bc: 4a18 ldr r2, [pc, #96] @ (800b320 ) 800b2be: f8b2 2011 ldrh.w r2, [r2, #17] 800b2c2: b292 uxth r2, r2 800b2c4: 4619 mov r1, r3 800b2c6: 2000 movs r0, #0 800b2c8: f7ff febc bl 800b044 } ED_Delay(CAN_DELAY); 800b2cc: 2014 movs r0, #20 800b2ce: f7ff fb67 bl 800a9a0 if(CONN.MeasuredVoltage > 490){ 800b2d2: 4b13 ldr r3, [pc, #76] @ (800b320 ) 800b2d4: f8b3 3013 ldrh.w r3, [r3, #19] 800b2d8: b29b uxth r3, r3 800b2da: f5b3 7ff5 cmp.w r3, #490 @ 0x1ea 800b2de: d917 bls.n 800b310 if(PSU0.hv_tick == 0){ 800b2e0: 4b11 ldr r3, [pc, #68] @ (800b328 ) 800b2e2: 69db ldr r3, [r3, #28] 800b2e4: 2b00 cmp r3, #0 800b2e6: d105 bne.n 800b2f4 PSU0.hv_tick = HAL_GetTick(); 800b2e8: f003 f852 bl 800e390 800b2ec: 4603 mov r3, r0 800b2ee: 4a0e ldr r2, [pc, #56] @ (800b328 ) 800b2f0: 61d3 str r3, [r2, #28] } // PSU_SetHVMode(0, PSU0.hv_mode); // auto set, no need // ED_Delay(CAN_DELAY); } 800b2f2: e010 b.n 800b316 }else if((HAL_GetTick() - PSU0.hv_tick) >= 10000){ 800b2f4: f003 f84c bl 800e390 800b2f8: 4602 mov r2, r0 800b2fa: 4b0b ldr r3, [pc, #44] @ (800b328 ) 800b2fc: 69db ldr r3, [r3, #28] 800b2fe: 1ad3 subs r3, r2, r3 800b300: f242 720f movw r2, #9999 @ 0x270f 800b304: 4293 cmp r3, r2 800b306: d906 bls.n 800b316 PSU0.hv_mode = 1; 800b308: 4b07 ldr r3, [pc, #28] @ (800b328 ) 800b30a: 2201 movs r2, #1 800b30c: 761a strb r2, [r3, #24] } 800b30e: e002 b.n 800b316 PSU0.hv_tick = 0; 800b310: 4b05 ldr r3, [pc, #20] @ (800b328 ) 800b312: 2200 movs r2, #0 800b314: 61da str r2, [r3, #28] } 800b316: bf00 nop 800b318: 3708 adds r7, #8 800b31a: 46bd mov sp, r7 800b31c: bd80 pop {r7, pc} 800b31e: bf00 nop 800b320: 200003b0 .word 0x200003b0 800b324: cccccccd .word 0xcccccccd 800b328: 20000904 .word 0x20000904 800b32c: 66666667 .word 0x66666667 0800b330 : void PSU_Task(void){ 800b330: b598 push {r3, r4, r7, lr} 800b332: af00 add r7, sp, #0 static uint32_t psu_on_tick = 0; static uint32_t cont_ok_tick = 0; // Обновляем ONLINE/READY по таймауту if((HAL_GetTick() - can_lastpacket) > PSU_ONLINE_TIMEOUT){ 800b334: f003 f82c bl 800e390 800b338: 4602 mov r2, r0 800b33a: 4bb3 ldr r3, [pc, #716] @ (800b608 ) 800b33c: 681b ldr r3, [r3, #0] 800b33e: 1ad3 subs r3, r2, r3 800b340: f5b3 7ffa cmp.w r3, #500 @ 0x1f4 800b344: d920 bls.n 800b388 PSU0.online = 0; 800b346: 4bb1 ldr r3, [pc, #708] @ (800b60c ) 800b348: 2200 movs r2, #0 800b34a: 721a strb r2, [r3, #8] PSU0.PSU_enabled = 0; 800b34c: 4baf ldr r3, [pc, #700] @ (800b60c ) 800b34e: 2200 movs r2, #0 800b350: 729a strb r2, [r3, #10] PSU_04.moduleTemperature = 0; 800b352: 4baf ldr r3, [pc, #700] @ (800b610 ) 800b354: 2200 movs r2, #0 800b356: 711a strb r2, [r3, #4] PSU_04.modularForm0 = 0; 800b358: 4bad ldr r3, [pc, #692] @ (800b610 ) 800b35a: 2200 movs r2, #0 800b35c: 721a strb r2, [r3, #8] PSU_04.modularForm1 = 0; 800b35e: 4bac ldr r3, [pc, #688] @ (800b610 ) 800b360: 2200 movs r2, #0 800b362: 71da strb r2, [r3, #7] PSU_04.modularForm2 = 0; 800b364: 4baa ldr r3, [pc, #680] @ (800b610 ) 800b366: 2200 movs r2, #0 800b368: 719a strb r2, [r3, #6] PSU_06.VAB = 0; 800b36a: 4baa ldr r3, [pc, #680] @ (800b614 ) 800b36c: 2200 movs r2, #0 800b36e: 609a str r2, [r3, #8] PSU_06.VBC = 0; 800b370: 4ba8 ldr r3, [pc, #672] @ (800b614 ) 800b372: 2200 movs r2, #0 800b374: 60da str r2, [r3, #12] PSU_06.VCA = 0; 800b376: 4ba7 ldr r3, [pc, #668] @ (800b614 ) 800b378: 2200 movs r2, #0 800b37a: 611a str r2, [r3, #16] PSU_09.moduleNCurrent = 0; 800b37c: 4ba6 ldr r3, [pc, #664] @ (800b618 ) 800b37e: 2200 movs r2, #0 800b380: 60da str r2, [r3, #12] PSU_09.moduleNVoltage = 0; 800b382: 4ba5 ldr r3, [pc, #660] @ (800b618 ) 800b384: 2200 movs r2, #0 800b386: 609a str r2, [r3, #8] } if(!PSU0.online || !PSU0.enableAC){ 800b388: 4ba0 ldr r3, [pc, #640] @ (800b60c ) 800b38a: 7a1b ldrb r3, [r3, #8] 800b38c: 2b00 cmp r3, #0 800b38e: d003 beq.n 800b398 800b390: 4b9e ldr r3, [pc, #632] @ (800b60c ) 800b392: 781b ldrb r3, [r3, #0] 800b394: 2b00 cmp r3, #0 800b396: d10c bne.n 800b3b2 CONN.MeasuredVoltage = 0; 800b398: 4ba0 ldr r3, [pc, #640] @ (800b61c ) 800b39a: 2200 movs r2, #0 800b39c: 74da strb r2, [r3, #19] 800b39e: 2200 movs r2, #0 800b3a0: 751a strb r2, [r3, #20] CONN.MeasuredCurrent = 0; 800b3a2: 4b9e ldr r3, [pc, #632] @ (800b61c ) 800b3a4: 2200 movs r2, #0 800b3a6: 755a strb r2, [r3, #21] 800b3a8: 2200 movs r2, #0 800b3aa: 759a strb r2, [r3, #22] CONN.outputEnabled = 0; 800b3ac: 4b9b ldr r3, [pc, #620] @ (800b61c ) 800b3ae: 2200 movs r2, #0 800b3b0: 761a strb r2, [r3, #24] } // Управление AC-контактором с задержкой отключения 1 минута if(CONN.EvConnected){ 800b3b2: 4b9a ldr r3, [pc, #616] @ (800b61c ) 800b3b4: 7f9b ldrb r3, [r3, #30] 800b3b6: 2b00 cmp r3, #0 800b3b8: d00c beq.n 800b3d4 RELAY_Write(RELAY_AC, 1); 800b3ba: 2101 movs r1, #1 800b3bc: 2004 movs r0, #4 800b3be: f7fe f9fb bl 80097b8 psu_on_tick = HAL_GetTick(); 800b3c2: f002 ffe5 bl 800e390 800b3c6: 4603 mov r3, r0 800b3c8: 4a95 ldr r2, [pc, #596] @ (800b620 ) 800b3ca: 6013 str r3, [r2, #0] PSU0.enableAC = 1; 800b3cc: 4b8f ldr r3, [pc, #572] @ (800b60c ) 800b3ce: 2201 movs r2, #1 800b3d0: 701a strb r2, [r3, #0] 800b3d2: e010 b.n 800b3f6 }else{ if((HAL_GetTick() - psu_on_tick) > 1 * 60000){ 800b3d4: f002 ffdc bl 800e390 800b3d8: 4602 mov r2, r0 800b3da: 4b91 ldr r3, [pc, #580] @ (800b620 ) 800b3dc: 681b ldr r3, [r3, #0] 800b3de: 1ad3 subs r3, r2, r3 800b3e0: f64e 2260 movw r2, #60000 @ 0xea60 800b3e4: 4293 cmp r3, r2 800b3e6: d906 bls.n 800b3f6 RELAY_Write(RELAY_AC, 0); 800b3e8: 2100 movs r1, #0 800b3ea: 2004 movs r0, #4 800b3ec: f7fe f9e4 bl 80097b8 PSU0.enableAC = 0; 800b3f0: 4b86 ldr r3, [pc, #536] @ (800b60c ) 800b3f2: 2200 movs r2, #0 800b3f4: 701a strb r2, [r3, #0] } } // Текущее состояние DC-контактора по обратной связи PSU0.CONT_enabled = IN_ReadInput(IN_CONT_FB_DC); 800b3f6: 2005 movs r0, #5 800b3f8: f7fe fa5e bl 80098b8 800b3fc: 4603 mov r3, r0 800b3fe: 461a mov r2, r3 800b400: 4b82 ldr r3, [pc, #520] @ (800b60c ) 800b402: 72da strb r2, [r3, #11] // Обновляем ready с учётом ошибок if(PSU0.online && !PSU0.cont_fault && PSU0.enableAC){ 800b404: 4b81 ldr r3, [pc, #516] @ (800b60c ) 800b406: 7a1b ldrb r3, [r3, #8] 800b408: 2b00 cmp r3, #0 800b40a: d007 beq.n 800b41c 800b40c: 4b7f ldr r3, [pc, #508] @ (800b60c ) 800b40e: 7b1b ldrb r3, [r3, #12] 800b410: 2b00 cmp r3, #0 800b412: d103 bne.n 800b41c 800b414: 4b7d ldr r3, [pc, #500] @ (800b60c ) 800b416: 781b ldrb r3, [r3, #0] 800b418: 2b00 cmp r3, #0 800b41a: d102 bne.n 800b422 // PSU0.ready = 1; }else{ PSU0.ready = 0; 800b41c: 4b7b ldr r3, [pc, #492] @ (800b60c ) 800b41e: 2200 movs r2, #0 800b420: 725a strb r2, [r3, #9] } switch(PSU0.state){ 800b422: 4b7a ldr r3, [pc, #488] @ (800b60c ) 800b424: 79db ldrb r3, [r3, #7] 800b426: 2b09 cmp r3, #9 800b428: f200 8151 bhi.w 800b6ce 800b42c: a201 add r2, pc, #4 @ (adr r2, 800b434 ) 800b42e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b432: bf00 nop 800b434: 0800b45d .word 0x0800b45d 800b438: 0800b491 .word 0x0800b491 800b43c: 0800b4ad .word 0x0800b4ad 800b440: 0800b4eb .word 0x0800b4eb 800b444: 0800b52f .word 0x0800b52f 800b448: 0800b571 .word 0x0800b571 800b44c: 0800b5db .word 0x0800b5db 800b450: 0800b681 .word 0x0800b681 800b454: 0800b631 .word 0x0800b631 800b458: 0800b6bb .word 0x0800b6bb case PSU_UNREADY: PSU0.enableOutput = 0; 800b45c: 4b6b ldr r3, [pc, #428] @ (800b60c ) 800b45e: 2200 movs r2, #0 800b460: 705a strb r2, [r3, #1] RELAY_Write(RELAY_DC, 0); 800b462: 2100 movs r1, #0 800b464: 2003 movs r0, #3 800b466: f7fe f9a7 bl 80097b8 if(PSU0.online && PSU0.enableAC && !PSU0.cont_fault){ 800b46a: 4b68 ldr r3, [pc, #416] @ (800b60c ) 800b46c: 7a1b ldrb r3, [r3, #8] 800b46e: 2b00 cmp r3, #0 800b470: f000 8131 beq.w 800b6d6 800b474: 4b65 ldr r3, [pc, #404] @ (800b60c ) 800b476: 781b ldrb r3, [r3, #0] 800b478: 2b00 cmp r3, #0 800b47a: f000 812c beq.w 800b6d6 800b47e: 4b63 ldr r3, [pc, #396] @ (800b60c ) 800b480: 7b1b ldrb r3, [r3, #12] 800b482: 2b00 cmp r3, #0 800b484: f040 8127 bne.w 800b6d6 PSU_SwitchState(PSU_INITIALIZING); 800b488: 2001 movs r0, #1 800b48a: f7ff fc8f bl 800adac } break; 800b48e: e122 b.n 800b6d6 case PSU_INITIALIZING: if(PSU_StateTime() > 4000){ // Wait 4s for PSU to initialize 800b490: f7ff fca0 bl 800add4 800b494: 4603 mov r3, r0 800b496: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b49a: f240 811e bls.w 800b6da PSU0.ready = 1; 800b49e: 4b5b ldr r3, [pc, #364] @ (800b60c ) 800b4a0: 2201 movs r2, #1 800b4a2: 725a strb r2, [r3, #9] PSU_SwitchState(PSU_READY); 800b4a4: 2002 movs r0, #2 800b4a6: f7ff fc81 bl 800adac } break; 800b4aa: e116 b.n 800b6da case PSU_READY: // модуль готов, но выключен PSU0.hv_mode = 0; 800b4ac: 4b57 ldr r3, [pc, #348] @ (800b60c ) 800b4ae: 2200 movs r2, #0 800b4b0: 761a strb r2, [r3, #24] PSU0.hv_tick = 0; 800b4b2: 4b56 ldr r3, [pc, #344] @ (800b60c ) 800b4b4: 2200 movs r2, #0 800b4b6: 61da str r2, [r3, #28] RELAY_Write(RELAY_DC, 0); 800b4b8: 2100 movs r1, #0 800b4ba: 2003 movs r0, #3 800b4bc: f7fe f97c bl 80097b8 if(!PSU0.ready){ 800b4c0: 4b52 ldr r3, [pc, #328] @ (800b60c ) 800b4c2: 7a5b ldrb r3, [r3, #9] 800b4c4: 2b00 cmp r3, #0 800b4c6: d103 bne.n 800b4d0 PSU_SwitchState(PSU_UNREADY); 800b4c8: 2000 movs r0, #0 800b4ca: f7ff fc6f bl 800adac break; 800b4ce: e115 b.n 800b6fc } if(CONN.EnableOutput){ 800b4d0: 4b52 ldr r3, [pc, #328] @ (800b61c ) 800b4d2: 7ddb ldrb r3, [r3, #23] 800b4d4: 2b00 cmp r3, #0 800b4d6: f000 8102 beq.w 800b6de PSU_Enable(0, 1); 800b4da: 2101 movs r1, #1 800b4dc: 2000 movs r0, #0 800b4de: f7ff fd81 bl 800afe4 PSU_SwitchState(PSU_WAIT_ACK_ON); 800b4e2: 2003 movs r0, #3 800b4e4: f7ff fc62 bl 800adac } break; 800b4e8: e0f9 b.n 800b6de case PSU_WAIT_ACK_ON: if(PSU0.PSU_enabled && PSU0.ready){ 800b4ea: 4b48 ldr r3, [pc, #288] @ (800b60c ) 800b4ec: 7a9b ldrb r3, [r3, #10] 800b4ee: 2b00 cmp r3, #0 800b4f0: d007 beq.n 800b502 800b4f2: 4b46 ldr r3, [pc, #280] @ (800b60c ) 800b4f4: 7a5b ldrb r3, [r3, #9] 800b4f6: 2b00 cmp r3, #0 800b4f8: d003 beq.n 800b502 PSU_SwitchState(PSU_CONT_WAIT_ACK_ON); 800b4fa: 2004 movs r0, #4 800b4fc: f7ff fc56 bl 800adac PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU on timeout\n"); } break; 800b500: e0ef b.n 800b6e2 }else if(PSU_StateTime() > 10000){ 800b502: f7ff fc67 bl 800add4 800b506: 4603 mov r3, r0 800b508: f242 7210 movw r2, #10000 @ 0x2710 800b50c: 4293 cmp r3, r2 800b50e: f240 80e8 bls.w 800b6e2 PSU0.psu_fault = 1; 800b512: 4b3e ldr r3, [pc, #248] @ (800b60c ) 800b514: 2201 movs r2, #1 800b516: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b518: 4b40 ldr r3, [pc, #256] @ (800b61c ) 800b51a: 220a movs r2, #10 800b51c: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b51e: 2000 movs r0, #0 800b520: f7ff fc44 bl 800adac log_printf(LOG_ERR, "PSU on timeout\n"); 800b524: 493f ldr r1, [pc, #252] @ (800b624 ) 800b526: 2004 movs r0, #4 800b528: f7ff f81e bl 800a568 break; 800b52c: e0d9 b.n 800b6e2 case PSU_CONT_WAIT_ACK_ON: // замыкаем DC-контактор и ждём подтверждение RELAY_Write(RELAY_DC, 1); 800b52e: 2101 movs r1, #1 800b530: 2003 movs r0, #3 800b532: f7fe f941 bl 80097b8 if(PSU0.CONT_enabled){ 800b536: 4b35 ldr r3, [pc, #212] @ (800b60c ) 800b538: 7adb ldrb r3, [r3, #11] 800b53a: 2b00 cmp r3, #0 800b53c: d003 beq.n 800b546 PSU_SwitchState(PSU_CONNECTED); 800b53e: 2005 movs r0, #5 800b540: f7ff fc34 bl 800adac PSU0.cont_fault = 1; CONN.chargingError = CONN_ERR_CONTACTOR; PSU_SwitchState(PSU_CURRENT_DROP); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b544: e0cf b.n 800b6e6 }else if(PSU_StateTime() > 1000){ 800b546: f7ff fc45 bl 800add4 800b54a: 4603 mov r3, r0 800b54c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b550: f240 80c9 bls.w 800b6e6 PSU0.cont_fault = 1; 800b554: 4b2d ldr r3, [pc, #180] @ (800b60c ) 800b556: 2201 movs r2, #1 800b558: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b55a: 4b30 ldr r3, [pc, #192] @ (800b61c ) 800b55c: 2207 movs r2, #7 800b55e: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_CURRENT_DROP); 800b560: 2006 movs r0, #6 800b562: f7ff fc23 bl 800adac log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b566: 4930 ldr r1, [pc, #192] @ (800b628 ) 800b568: 2004 movs r0, #4 800b56a: f7fe fffd bl 800a568 break; 800b56e: e0ba b.n 800b6e6 case PSU_CONNECTED: // Основное рабочее состояние if(!CONN.EnableOutput || !PSU0.ready){ 800b570: 4b2a ldr r3, [pc, #168] @ (800b61c ) 800b572: 7ddb ldrb r3, [r3, #23] 800b574: 2b00 cmp r3, #0 800b576: d003 beq.n 800b580 800b578: 4b24 ldr r3, [pc, #144] @ (800b60c ) 800b57a: 7a5b ldrb r3, [r3, #9] 800b57c: 2b00 cmp r3, #0 800b57e: d103 bne.n 800b588 PSU_SwitchState(PSU_CURRENT_DROP); 800b580: 2006 movs r0, #6 800b582: f7ff fc13 bl 800adac break; 800b586: e0b9 b.n 800b6fc } // контроль контактора: 1 c таймаут if (IN_ReadInput(IN_CONT_FB_DC) != RELAY_Read(RELAY_DC)){ 800b588: 2005 movs r0, #5 800b58a: f7fe f995 bl 80098b8 800b58e: 4603 mov r3, r0 800b590: 461c mov r4, r3 800b592: 2003 movs r0, #3 800b594: f7fe f980 bl 8009898 800b598: 4603 mov r3, r0 800b59a: 429c cmp r4, r3 800b59c: d017 beq.n 800b5ce if((HAL_GetTick() - cont_ok_tick) > 1000){ 800b59e: f002 fef7 bl 800e390 800b5a2: 4602 mov r2, r0 800b5a4: 4b21 ldr r3, [pc, #132] @ (800b62c ) 800b5a6: 681b ldr r3, [r3, #0] 800b5a8: 1ad3 subs r3, r2, r3 800b5aa: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b5ae: f240 809c bls.w 800b6ea CONN.chargingError = CONN_ERR_CONTACTOR; 800b5b2: 4b1a ldr r3, [pc, #104] @ (800b61c ) 800b5b4: 2207 movs r2, #7 800b5b6: 775a strb r2, [r3, #29] PSU0.cont_fault = 1; 800b5b8: 4b14 ldr r3, [pc, #80] @ (800b60c ) 800b5ba: 2201 movs r2, #1 800b5bc: 731a strb r2, [r3, #12] PSU_SwitchState(PSU_CURRENT_DROP); 800b5be: 2006 movs r0, #6 800b5c0: f7ff fbf4 bl 800adac log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b5c4: 4918 ldr r1, [pc, #96] @ (800b628 ) 800b5c6: 2004 movs r0, #4 800b5c8: f7fe ffce bl 800a568 } }else{ cont_ok_tick = HAL_GetTick(); } break; 800b5cc: e08d b.n 800b6ea cont_ok_tick = HAL_GetTick(); 800b5ce: f002 fedf bl 800e390 800b5d2: 4603 mov r3, r0 800b5d4: 4a15 ldr r2, [pc, #84] @ (800b62c ) 800b5d6: 6013 str r3, [r2, #0] break; 800b5d8: e087 b.n 800b6ea case PSU_CURRENT_DROP: // снижаем ток до нуля перед отключением DC CONN.RequestedCurrent = 0; 800b5da: 4b10 ldr r3, [pc, #64] @ (800b61c ) 800b5dc: 2200 movs r2, #0 800b5de: 745a strb r2, [r3, #17] 800b5e0: 2200 movs r2, #0 800b5e2: 749a strb r2, [r3, #18] // если ток действительно упал или вышло время, отключаем DC if((CONN.MeasuredCurrent < 30) || (PSU_StateTime() > 5000)){ 800b5e4: 4b0d ldr r3, [pc, #52] @ (800b61c ) 800b5e6: f8b3 3015 ldrh.w r3, [r3, #21] 800b5ea: b29b uxth r3, r3 800b5ec: 2b1d cmp r3, #29 800b5ee: d906 bls.n 800b5fe 800b5f0: f7ff fbf0 bl 800add4 800b5f4: 4603 mov r3, r0 800b5f6: f241 3288 movw r2, #5000 @ 0x1388 800b5fa: 4293 cmp r3, r2 800b5fc: d977 bls.n 800b6ee PSU_SwitchState(PSU_CONT_WAIT_ACK_OFF); 800b5fe: 2008 movs r0, #8 800b600: f7ff fbd4 bl 800adac } break; 800b604: e073 b.n 800b6ee 800b606: bf00 nop 800b608: 2000092c .word 0x2000092c 800b60c: 20000904 .word 0x20000904 800b610: 200008cc .word 0x200008cc 800b614: 200008d8 .word 0x200008d8 800b618: 200008f4 .word 0x200008f4 800b61c: 200003b0 .word 0x200003b0 800b620: 20000954 .word 0x20000954 800b624: 0801717c .word 0x0801717c 800b628: 0801718c .word 0x0801718c 800b62c: 20000958 .word 0x20000958 case PSU_CONT_WAIT_ACK_OFF: RELAY_Write(RELAY_DC, 0); 800b630: 2100 movs r1, #0 800b632: 2003 movs r0, #3 800b634: f7fe f8c0 bl 80097b8 if(!PSU0.CONT_enabled){ 800b638: 4b31 ldr r3, [pc, #196] @ (800b700 ) 800b63a: 7adb ldrb r3, [r3, #11] 800b63c: 2b00 cmp r3, #0 800b63e: d107 bne.n 800b650 PSU_Enable(0, 0); 800b640: 2100 movs r1, #0 800b642: 2000 movs r0, #0 800b644: f7ff fcce bl 800afe4 PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b648: 2007 movs r0, #7 800b64a: f7ff fbaf bl 800adac CONN.chargingError = CONN_ERR_CONTACTOR; PSU_Enable(0, 0); PSU_SwitchState(PSU_WAIT_ACK_OFF); log_printf(LOG_ERR, "Contactor error, stopping...\n"); } break; 800b64e: e050 b.n 800b6f2 }else if(PSU_StateTime() > 1000){ 800b650: f7ff fbc0 bl 800add4 800b654: 4603 mov r3, r0 800b656: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b65a: d94a bls.n 800b6f2 PSU0.cont_fault = 1; 800b65c: 4b28 ldr r3, [pc, #160] @ (800b700 ) 800b65e: 2201 movs r2, #1 800b660: 731a strb r2, [r3, #12] CONN.chargingError = CONN_ERR_CONTACTOR; 800b662: 4b28 ldr r3, [pc, #160] @ (800b704 ) 800b664: 2207 movs r2, #7 800b666: 775a strb r2, [r3, #29] PSU_Enable(0, 0); 800b668: 2100 movs r1, #0 800b66a: 2000 movs r0, #0 800b66c: f7ff fcba bl 800afe4 PSU_SwitchState(PSU_WAIT_ACK_OFF); 800b670: 2007 movs r0, #7 800b672: f7ff fb9b bl 800adac log_printf(LOG_ERR, "Contactor error, stopping...\n"); 800b676: 4924 ldr r1, [pc, #144] @ (800b708 ) 800b678: 2004 movs r0, #4 800b67a: f7fe ff75 bl 800a568 break; 800b67e: e038 b.n 800b6f2 case PSU_WAIT_ACK_OFF: if(!PSU0.PSU_enabled){ 800b680: 4b1f ldr r3, [pc, #124] @ (800b700 ) 800b682: 7a9b ldrb r3, [r3, #10] 800b684: 2b00 cmp r3, #0 800b686: d103 bne.n 800b690 PSU_SwitchState(PSU_OFF_PAUSE); 800b688: 2009 movs r0, #9 800b68a: f7ff fb8f bl 800adac PSU0.psu_fault = 1; CONN.chargingError = CONN_ERR_PSU_FAULT; PSU_SwitchState(PSU_UNREADY); log_printf(LOG_ERR, "PSU off timeout\n"); } break; 800b68e: e032 b.n 800b6f6 }else if(PSU_StateTime() > 10000){ 800b690: f7ff fba0 bl 800add4 800b694: 4603 mov r3, r0 800b696: f242 7210 movw r2, #10000 @ 0x2710 800b69a: 4293 cmp r3, r2 800b69c: d92b bls.n 800b6f6 PSU0.psu_fault = 1; 800b69e: 4b18 ldr r3, [pc, #96] @ (800b700 ) 800b6a0: 2201 movs r2, #1 800b6a2: 735a strb r2, [r3, #13] CONN.chargingError = CONN_ERR_PSU_FAULT; 800b6a4: 4b17 ldr r3, [pc, #92] @ (800b704 ) 800b6a6: 220a movs r2, #10 800b6a8: 775a strb r2, [r3, #29] PSU_SwitchState(PSU_UNREADY); 800b6aa: 2000 movs r0, #0 800b6ac: f7ff fb7e bl 800adac log_printf(LOG_ERR, "PSU off timeout\n"); 800b6b0: 4916 ldr r1, [pc, #88] @ (800b70c ) 800b6b2: 2004 movs r0, #4 800b6b4: f7fe ff58 bl 800a568 break; 800b6b8: e01d b.n 800b6f6 case PSU_OFF_PAUSE: if(PSU_StateTime() > 4000){ 800b6ba: f7ff fb8b bl 800add4 800b6be: 4603 mov r3, r0 800b6c0: f5b3 6f7a cmp.w r3, #4000 @ 0xfa0 800b6c4: d919 bls.n 800b6fa PSU_SwitchState(PSU_READY); 800b6c6: 2002 movs r0, #2 800b6c8: f7ff fb70 bl 800adac } break; 800b6cc: e015 b.n 800b6fa default: PSU_SwitchState(PSU_UNREADY); 800b6ce: 2000 movs r0, #0 800b6d0: f7ff fb6c bl 800adac break; 800b6d4: e012 b.n 800b6fc break; 800b6d6: bf00 nop 800b6d8: e010 b.n 800b6fc break; 800b6da: bf00 nop 800b6dc: e00e b.n 800b6fc break; 800b6de: bf00 nop 800b6e0: e00c b.n 800b6fc break; 800b6e2: bf00 nop 800b6e4: e00a b.n 800b6fc break; 800b6e6: bf00 nop 800b6e8: e008 b.n 800b6fc break; 800b6ea: bf00 nop 800b6ec: e006 b.n 800b6fc break; 800b6ee: bf00 nop 800b6f0: e004 b.n 800b6fc break; 800b6f2: bf00 nop 800b6f4: e002 b.n 800b6fc break; 800b6f6: bf00 nop 800b6f8: e000 b.n 800b6fc break; 800b6fa: bf00 nop } } 800b6fc: bf00 nop 800b6fe: bd98 pop {r3, r4, r7, pc} 800b700: 20000904 .word 0x20000904 800b704: 200003b0 .word 0x200003b0 800b708: 0801718c .word 0x0801718c 800b70c: 080171ac .word 0x080171ac 0800b710 : .Th = 10, .Tf = 50, .Tl = 0, }; void LED_Write(){ 800b710: b580 push {r7, lr} 800b712: af00 add r7, sp, #0 if(CONN.chargingError != CONN_NO_ERROR){ 800b714: 4b3c ldr r3, [pc, #240] @ (800b808 ) 800b716: 7f5b ldrb r3, [r3, #29] 800b718: 2b00 cmp r3, #0 800b71a: d003 beq.n 800b724 LED_SetColor(&color_error); 800b71c: 483b ldr r0, [pc, #236] @ (800b80c ) 800b71e: f000 f933 bl 800b988 return; 800b722: e06f b.n 800b804 } if(CONN.connControl == CMD_FORCE_UNLOCK){ 800b724: 4b38 ldr r3, [pc, #224] @ (800b808 ) 800b726: 781b ldrb r3, [r3, #0] 800b728: 2b03 cmp r3, #3 800b72a: d103 bne.n 800b734 LED_SetColor(&color_unlock); 800b72c: 4838 ldr r0, [pc, #224] @ (800b810 ) 800b72e: f000 f92b bl 800b988 return; 800b732: e067 b.n 800b804 } if(CONN.connControl == CMD_STOP){ 800b734: 4b34 ldr r3, [pc, #208] @ (800b808 ) 800b736: 781b ldrb r3, [r3, #0] 800b738: 2b01 cmp r3, #1 800b73a: d103 bne.n 800b744 LED_SetColor(&color_estop); 800b73c: 4835 ldr r0, [pc, #212] @ (800b814 ) 800b73e: f000 f923 bl 800b988 return; 800b742: e05f b.n 800b804 } switch(CONN.connState){ 800b744: 4b30 ldr r3, [pc, #192] @ (800b808 ) 800b746: 785b ldrb r3, [r3, #1] 800b748: 2b0d cmp r3, #13 800b74a: d857 bhi.n 800b7fc 800b74c: a201 add r2, pc, #4 @ (adr r2, 800b754 ) 800b74e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b752: bf00 nop 800b754: 0800b78d .word 0x0800b78d 800b758: 0800b795 .word 0x0800b795 800b75c: 0800b79d .word 0x0800b79d 800b760: 0800b7a5 .word 0x0800b7a5 800b764: 0800b7ad .word 0x0800b7ad 800b768: 0800b7b5 .word 0x0800b7b5 800b76c: 0800b7bd .word 0x0800b7bd 800b770: 0800b7c5 .word 0x0800b7c5 800b774: 0800b7cd .word 0x0800b7cd 800b778: 0800b7d5 .word 0x0800b7d5 800b77c: 0800b7dd .word 0x0800b7dd 800b780: 0800b7e5 .word 0x0800b7e5 800b784: 0800b7ed .word 0x0800b7ed 800b788: 0800b7f5 .word 0x0800b7f5 case Unknown: LED_SetColor(&color_unknown); 800b78c: 4822 ldr r0, [pc, #136] @ (800b818 ) 800b78e: f000 f8fb bl 800b988 break; 800b792: e037 b.n 800b804 case Unplugged: LED_SetColor(&color_unplugged); 800b794: 4821 ldr r0, [pc, #132] @ (800b81c ) 800b796: f000 f8f7 bl 800b988 break; 800b79a: e033 b.n 800b804 case Disabled: LED_SetColor(&color_error); 800b79c: 481b ldr r0, [pc, #108] @ (800b80c ) 800b79e: f000 f8f3 bl 800b988 break; 800b7a2: e02f b.n 800b804 case Preparing: LED_SetColor(&color_preparing); 800b7a4: 481e ldr r0, [pc, #120] @ (800b820 ) 800b7a6: f000 f8ef bl 800b988 break; 800b7aa: e02b b.n 800b804 case AuthRequired: LED_SetColor(&color_preparing); 800b7ac: 481c ldr r0, [pc, #112] @ (800b820 ) 800b7ae: f000 f8eb bl 800b988 break; 800b7b2: e027 b.n 800b804 case WaitingForEnergy: LED_SetColor(&color_charging); 800b7b4: 481b ldr r0, [pc, #108] @ (800b824 ) 800b7b6: f000 f8e7 bl 800b988 break; 800b7ba: e023 b.n 800b804 case ChargingPausedEV: LED_SetColor(&color_charging); 800b7bc: 4819 ldr r0, [pc, #100] @ (800b824 ) 800b7be: f000 f8e3 bl 800b988 break; 800b7c2: e01f b.n 800b804 case ChargingPausedEVSE: LED_SetColor(&color_charging); 800b7c4: 4817 ldr r0, [pc, #92] @ (800b824 ) 800b7c6: f000 f8df bl 800b988 break; 800b7ca: e01b b.n 800b804 case Charging: LED_SetColor(&color_charging); 800b7cc: 4815 ldr r0, [pc, #84] @ (800b824 ) 800b7ce: f000 f8db bl 800b988 break; 800b7d2: e017 b.n 800b804 case AuthTimeout: LED_SetColor(&color_finished); 800b7d4: 4814 ldr r0, [pc, #80] @ (800b828 ) 800b7d6: f000 f8d7 bl 800b988 break; 800b7da: e013 b.n 800b804 case Finished: LED_SetColor(&color_finished); 800b7dc: 4812 ldr r0, [pc, #72] @ (800b828 ) 800b7de: f000 f8d3 bl 800b988 break; 800b7e2: e00f b.n 800b804 case FinishedEVSE: LED_SetColor(&color_finished); 800b7e4: 4810 ldr r0, [pc, #64] @ (800b828 ) 800b7e6: f000 f8cf bl 800b988 break; 800b7ea: e00b b.n 800b804 case FinishedEV: LED_SetColor(&color_finished); 800b7ec: 480e ldr r0, [pc, #56] @ (800b828 ) 800b7ee: f000 f8cb bl 800b988 break; 800b7f2: e007 b.n 800b804 case Replugging: LED_SetColor(&color_preparing); 800b7f4: 480a ldr r0, [pc, #40] @ (800b820 ) 800b7f6: f000 f8c7 bl 800b988 break; 800b7fa: e003 b.n 800b804 default: LED_SetColor(&color_unknown); 800b7fc: 4806 ldr r0, [pc, #24] @ (800b818 ) 800b7fe: f000 f8c3 bl 800b988 break; 800b802: bf00 nop } } 800b804: bd80 pop {r7, pc} 800b806: bf00 nop 800b808: 200003b0 .word 0x200003b0 800b80c: 20000060 .word 0x20000060 800b810: 20000018 .word 0x20000018 800b814: 2000000c .word 0x2000000c 800b818: 20000024 .word 0x20000024 800b81c: 20000030 .word 0x20000030 800b820: 2000003c .word 0x2000003c 800b824: 20000048 .word 0x20000048 800b828: 20000054 .word 0x20000054 0800b82c : void interpolateColors(RGB_t* color1, RGB_t* color2, uint16_t a, uint16_t b, RGB_t *result) { 800b82c: b480 push {r7} 800b82e: b087 sub sp, #28 800b830: af00 add r7, sp, #0 800b832: 60f8 str r0, [r7, #12] 800b834: 60b9 str r1, [r7, #8] 800b836: 4611 mov r1, r2 800b838: 461a mov r2, r3 800b83a: 460b mov r3, r1 800b83c: 80fb strh r3, [r7, #6] 800b83e: 4613 mov r3, r2 800b840: 80bb strh r3, [r7, #4] // Проверяем, чтобы a не выходила за пределы диапазона if (a > b) a = b; 800b842: 88fa ldrh r2, [r7, #6] 800b844: 88bb ldrh r3, [r7, #4] 800b846: 429a cmp r2, r3 800b848: d901 bls.n 800b84e 800b84a: 88bb ldrh r3, [r7, #4] 800b84c: 80fb strh r3, [r7, #6] if(b==0) b = 1; 800b84e: 88bb ldrh r3, [r7, #4] 800b850: 2b00 cmp r3, #0 800b852: d101 bne.n 800b858 800b854: 2301 movs r3, #1 800b856: 80bb strh r3, [r7, #4] // Вычисляем коэффициент смешивания в виде целого числа uint16_t t = (a * 255) / b; // t будет от 0 до 255 800b858: 88fa ldrh r2, [r7, #6] 800b85a: 4613 mov r3, r2 800b85c: 021b lsls r3, r3, #8 800b85e: 1a9a subs r2, r3, r2 800b860: 88bb ldrh r3, [r7, #4] 800b862: fb92 f3f3 sdiv r3, r2, r3 800b866: 82fb strh r3, [r7, #22] // Линейная интерполяция с использованием целых чисел result->R = (color1->R * (255 - t) + color2->R * t) / 255; 800b868: 68fb ldr r3, [r7, #12] 800b86a: 781b ldrb r3, [r3, #0] 800b86c: 461a mov r2, r3 800b86e: 8afb ldrh r3, [r7, #22] 800b870: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b874: fb03 f202 mul.w r2, r3, r2 800b878: 68bb ldr r3, [r7, #8] 800b87a: 781b ldrb r3, [r3, #0] 800b87c: 4619 mov r1, r3 800b87e: 8afb ldrh r3, [r7, #22] 800b880: fb01 f303 mul.w r3, r1, r3 800b884: 4413 add r3, r2 800b886: 4a20 ldr r2, [pc, #128] @ (800b908 ) 800b888: fb82 1203 smull r1, r2, r2, r3 800b88c: 441a add r2, r3 800b88e: 11d2 asrs r2, r2, #7 800b890: 17db asrs r3, r3, #31 800b892: 1ad3 subs r3, r2, r3 800b894: b2da uxtb r2, r3 800b896: 6a3b ldr r3, [r7, #32] 800b898: 701a strb r2, [r3, #0] result->G = (color1->G * (255 - t) + color2->G * t) / 255; 800b89a: 68fb ldr r3, [r7, #12] 800b89c: 785b ldrb r3, [r3, #1] 800b89e: 461a mov r2, r3 800b8a0: 8afb ldrh r3, [r7, #22] 800b8a2: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b8a6: fb03 f202 mul.w r2, r3, r2 800b8aa: 68bb ldr r3, [r7, #8] 800b8ac: 785b ldrb r3, [r3, #1] 800b8ae: 4619 mov r1, r3 800b8b0: 8afb ldrh r3, [r7, #22] 800b8b2: fb01 f303 mul.w r3, r1, r3 800b8b6: 4413 add r3, r2 800b8b8: 4a13 ldr r2, [pc, #76] @ (800b908 ) 800b8ba: fb82 1203 smull r1, r2, r2, r3 800b8be: 441a add r2, r3 800b8c0: 11d2 asrs r2, r2, #7 800b8c2: 17db asrs r3, r3, #31 800b8c4: 1ad3 subs r3, r2, r3 800b8c6: b2da uxtb r2, r3 800b8c8: 6a3b ldr r3, [r7, #32] 800b8ca: 705a strb r2, [r3, #1] result->B = (color1->B * (255 - t) + color2->B * t) / 255; 800b8cc: 68fb ldr r3, [r7, #12] 800b8ce: 789b ldrb r3, [r3, #2] 800b8d0: 461a mov r2, r3 800b8d2: 8afb ldrh r3, [r7, #22] 800b8d4: f1c3 03ff rsb r3, r3, #255 @ 0xff 800b8d8: fb03 f202 mul.w r2, r3, r2 800b8dc: 68bb ldr r3, [r7, #8] 800b8de: 789b ldrb r3, [r3, #2] 800b8e0: 4619 mov r1, r3 800b8e2: 8afb ldrh r3, [r7, #22] 800b8e4: fb01 f303 mul.w r3, r1, r3 800b8e8: 4413 add r3, r2 800b8ea: 4a07 ldr r2, [pc, #28] @ (800b908 ) 800b8ec: fb82 1203 smull r1, r2, r2, r3 800b8f0: 441a add r2, r3 800b8f2: 11d2 asrs r2, r2, #7 800b8f4: 17db asrs r3, r3, #31 800b8f6: 1ad3 subs r3, r2, r3 800b8f8: b2da uxtb r2, r3 800b8fa: 6a3b ldr r3, [r7, #32] 800b8fc: 709a strb r2, [r3, #2] } 800b8fe: bf00 nop 800b900: 371c adds r7, #28 800b902: 46bd mov sp, r7 800b904: bc80 pop {r7} 800b906: 4770 bx lr 800b908: 80808081 .word 0x80808081 0800b90c : void RGB_SetColor(RGB_t *color){ 800b90c: b480 push {r7} 800b90e: b083 sub sp, #12 800b910: af00 add r7, sp, #0 800b912: 6078 str r0, [r7, #4] htim4.Instance->CCR2 = color->R * 100 / 255; 800b914: 687b ldr r3, [r7, #4] 800b916: 781b ldrb r3, [r3, #0] 800b918: 461a mov r2, r3 800b91a: 2364 movs r3, #100 @ 0x64 800b91c: fb02 f303 mul.w r3, r2, r3 800b920: 4a17 ldr r2, [pc, #92] @ (800b980 ) 800b922: fb82 1203 smull r1, r2, r2, r3 800b926: 441a add r2, r3 800b928: 11d2 asrs r2, r2, #7 800b92a: 17db asrs r3, r3, #31 800b92c: 1ad2 subs r2, r2, r3 800b92e: 4b15 ldr r3, [pc, #84] @ (800b984 ) 800b930: 681b ldr r3, [r3, #0] 800b932: 639a str r2, [r3, #56] @ 0x38 htim4.Instance->CCR3 = color->G * 100 / 255; 800b934: 687b ldr r3, [r7, #4] 800b936: 785b ldrb r3, [r3, #1] 800b938: 461a mov r2, r3 800b93a: 2364 movs r3, #100 @ 0x64 800b93c: fb02 f303 mul.w r3, r2, r3 800b940: 4a0f ldr r2, [pc, #60] @ (800b980 ) 800b942: fb82 1203 smull r1, r2, r2, r3 800b946: 441a add r2, r3 800b948: 11d2 asrs r2, r2, #7 800b94a: 17db asrs r3, r3, #31 800b94c: 1ad2 subs r2, r2, r3 800b94e: 4b0d ldr r3, [pc, #52] @ (800b984 ) 800b950: 681b ldr r3, [r3, #0] 800b952: 63da str r2, [r3, #60] @ 0x3c htim4.Instance->CCR4 = color->B * 100 / 255; 800b954: 687b ldr r3, [r7, #4] 800b956: 789b ldrb r3, [r3, #2] 800b958: 461a mov r2, r3 800b95a: 2364 movs r3, #100 @ 0x64 800b95c: fb02 f303 mul.w r3, r2, r3 800b960: 4a07 ldr r2, [pc, #28] @ (800b980 ) 800b962: fb82 1203 smull r1, r2, r2, r3 800b966: 441a add r2, r3 800b968: 11d2 asrs r2, r2, #7 800b96a: 17db asrs r3, r3, #31 800b96c: 1ad2 subs r2, r2, r3 800b96e: 4b05 ldr r3, [pc, #20] @ (800b984 ) 800b970: 681b ldr r3, [r3, #0] 800b972: 641a str r2, [r3, #64] @ 0x40 } 800b974: bf00 nop 800b976: 370c adds r7, #12 800b978: 46bd mov sp, r7 800b97a: bc80 pop {r7} 800b97c: 4770 bx lr 800b97e: bf00 nop 800b980: 80808081 .word 0x80808081 800b984: 20001210 .word 0x20001210 0800b988 : void LED_SetColor(RGB_Cycle_t *color){ 800b988: b480 push {r7} 800b98a: b083 sub sp, #12 800b98c: af00 add r7, sp, #0 800b98e: 6078 str r0, [r7, #4] memcpy(&LED_Cycle, color, sizeof(RGB_Cycle_t)); 800b990: 4b05 ldr r3, [pc, #20] @ (800b9a8 ) 800b992: 687a ldr r2, [r7, #4] 800b994: 6810 ldr r0, [r2, #0] 800b996: 6851 ldr r1, [r2, #4] 800b998: c303 stmia r3!, {r0, r1} 800b99a: 8912 ldrh r2, [r2, #8] 800b99c: 801a strh r2, [r3, #0] } 800b99e: bf00 nop 800b9a0: 370c adds r7, #12 800b9a2: 46bd mov sp, r7 800b9a4: bc80 pop {r7} 800b9a6: 4770 bx lr 800b9a8: 20000964 .word 0x20000964 0800b9ac : void LED_Init(){ 800b9ac: b580 push {r7, lr} 800b9ae: b082 sub sp, #8 800b9b0: af00 add r7, sp, #0 RGB_t color = {.R=0, .G=0, .B=0}; 800b9b2: 2300 movs r3, #0 800b9b4: 713b strb r3, [r7, #4] 800b9b6: 2300 movs r3, #0 800b9b8: 717b strb r3, [r7, #5] 800b9ba: 2300 movs r3, #0 800b9bc: 71bb strb r3, [r7, #6] HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_2); 800b9be: 2104 movs r1, #4 800b9c0: 4809 ldr r0, [pc, #36] @ (800b9e8 ) 800b9c2: f006 fbb3 bl 801212c HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); 800b9c6: 2108 movs r1, #8 800b9c8: 4807 ldr r0, [pc, #28] @ (800b9e8 ) 800b9ca: f006 fbaf bl 801212c HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_4); 800b9ce: 210c movs r1, #12 800b9d0: 4805 ldr r0, [pc, #20] @ (800b9e8 ) 800b9d2: f006 fbab bl 801212c RGB_SetColor(&color); 800b9d6: 1d3b adds r3, r7, #4 800b9d8: 4618 mov r0, r3 800b9da: f7ff ff97 bl 800b90c } 800b9de: bf00 nop 800b9e0: 3708 adds r7, #8 800b9e2: 46bd mov sp, r7 800b9e4: bd80 pop {r7, pc} 800b9e6: bf00 nop 800b9e8: 20001210 .word 0x20001210 0800b9ec : void LED_Task(){ 800b9ec: b580 push {r7, lr} 800b9ee: b082 sub sp, #8 800b9f0: af02 add r7, sp, #8 static uint32_t led_tick; if((HAL_GetTick() - led_tick) > 20){ 800b9f2: f002 fccd bl 800e390 800b9f6: 4602 mov r2, r0 800b9f8: 4b46 ldr r3, [pc, #280] @ (800bb14 ) 800b9fa: 681b ldr r3, [r3, #0] 800b9fc: 1ad3 subs r3, r2, r3 800b9fe: 2b14 cmp r3, #20 800ba00: f240 8085 bls.w 800bb0e led_tick = HAL_GetTick(); 800ba04: f002 fcc4 bl 800e390 800ba08: 4603 mov r3, r0 800ba0a: 4a42 ldr r2, [pc, #264] @ (800bb14 ) 800ba0c: 6013 str r3, [r2, #0] LED_State.tick++; 800ba0e: 4b42 ldr r3, [pc, #264] @ (800bb18 ) 800ba10: 885b ldrh r3, [r3, #2] 800ba12: 3301 adds r3, #1 800ba14: b29a uxth r2, r3 800ba16: 4b40 ldr r3, [pc, #256] @ (800bb18 ) 800ba18: 805a strh r2, [r3, #2] switch(LED_State.state){ 800ba1a: 4b3f ldr r3, [pc, #252] @ (800bb18 ) 800ba1c: 781b ldrb r3, [r3, #0] 800ba1e: 2b03 cmp r3, #3 800ba20: d867 bhi.n 800baf2 800ba22: a201 add r2, pc, #4 @ (adr r2, 800ba28 ) 800ba24: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ba28: 0800ba39 .word 0x0800ba39 800ba2c: 0800ba6b .word 0x0800ba6b 800ba30: 0800ba97 .word 0x0800ba97 800ba34: 0800bac9 .word 0x0800bac9 case LED_RISING: interpolateColors(&LED_Cycle.Color2, &LED_Cycle.Color1, LED_State.tick, LED_Cycle.Tr, &LED_State.color); 800ba38: 4b37 ldr r3, [pc, #220] @ (800bb18 ) 800ba3a: 885a ldrh r2, [r3, #2] 800ba3c: 4b37 ldr r3, [pc, #220] @ (800bb1c ) 800ba3e: 78db ldrb r3, [r3, #3] 800ba40: 4619 mov r1, r3 800ba42: 4b37 ldr r3, [pc, #220] @ (800bb20 ) 800ba44: 9300 str r3, [sp, #0] 800ba46: 460b mov r3, r1 800ba48: 4934 ldr r1, [pc, #208] @ (800bb1c ) 800ba4a: 4836 ldr r0, [pc, #216] @ (800bb24 ) 800ba4c: f7ff feee bl 800b82c if(LED_State.tick>LED_Cycle.Tr){ 800ba50: 4b31 ldr r3, [pc, #196] @ (800bb18 ) 800ba52: 885b ldrh r3, [r3, #2] 800ba54: 4a31 ldr r2, [pc, #196] @ (800bb1c ) 800ba56: 78d2 ldrb r2, [r2, #3] 800ba58: 4293 cmp r3, r2 800ba5a: d94e bls.n 800bafa LED_State.state = LED_HIGH; 800ba5c: 4b2e ldr r3, [pc, #184] @ (800bb18 ) 800ba5e: 2201 movs r2, #1 800ba60: 701a strb r2, [r3, #0] LED_State.tick = 0; 800ba62: 4b2d ldr r3, [pc, #180] @ (800bb18 ) 800ba64: 2200 movs r2, #0 800ba66: 805a strh r2, [r3, #2] } break; 800ba68: e047 b.n 800bafa case LED_HIGH: memcpy(&LED_State.color, &LED_Cycle.Color1, sizeof(RGB_t)); 800ba6a: 4b2b ldr r3, [pc, #172] @ (800bb18 ) 800ba6c: 4a2b ldr r2, [pc, #172] @ (800bb1c ) 800ba6e: 3304 adds r3, #4 800ba70: 6812 ldr r2, [r2, #0] 800ba72: 4611 mov r1, r2 800ba74: 8019 strh r1, [r3, #0] 800ba76: 3302 adds r3, #2 800ba78: 0c12 lsrs r2, r2, #16 800ba7a: 701a strb r2, [r3, #0] if(LED_State.tick>LED_Cycle.Th){ 800ba7c: 4b26 ldr r3, [pc, #152] @ (800bb18 ) 800ba7e: 885b ldrh r3, [r3, #2] 800ba80: 4a26 ldr r2, [pc, #152] @ (800bb1c ) 800ba82: 7912 ldrb r2, [r2, #4] 800ba84: 4293 cmp r3, r2 800ba86: d93a bls.n 800bafe LED_State.state = LED_FALLING; 800ba88: 4b23 ldr r3, [pc, #140] @ (800bb18 ) 800ba8a: 2202 movs r2, #2 800ba8c: 701a strb r2, [r3, #0] LED_State.tick = 0; 800ba8e: 4b22 ldr r3, [pc, #136] @ (800bb18 ) 800ba90: 2200 movs r2, #0 800ba92: 805a strh r2, [r3, #2] } break; 800ba94: e033 b.n 800bafe case LED_FALLING: interpolateColors(&LED_Cycle.Color1, &LED_Cycle.Color2, LED_State.tick, LED_Cycle.Tf, &LED_State.color); 800ba96: 4b20 ldr r3, [pc, #128] @ (800bb18 ) 800ba98: 885a ldrh r2, [r3, #2] 800ba9a: 4b20 ldr r3, [pc, #128] @ (800bb1c ) 800ba9c: 795b ldrb r3, [r3, #5] 800ba9e: 4619 mov r1, r3 800baa0: 4b1f ldr r3, [pc, #124] @ (800bb20 ) 800baa2: 9300 str r3, [sp, #0] 800baa4: 460b mov r3, r1 800baa6: 491f ldr r1, [pc, #124] @ (800bb24 ) 800baa8: 481c ldr r0, [pc, #112] @ (800bb1c ) 800baaa: f7ff febf bl 800b82c if(LED_State.tick>LED_Cycle.Tf){ 800baae: 4b1a ldr r3, [pc, #104] @ (800bb18 ) 800bab0: 885b ldrh r3, [r3, #2] 800bab2: 4a1a ldr r2, [pc, #104] @ (800bb1c ) 800bab4: 7952 ldrb r2, [r2, #5] 800bab6: 4293 cmp r3, r2 800bab8: d923 bls.n 800bb02 LED_State.state = LED_LOW; 800baba: 4b17 ldr r3, [pc, #92] @ (800bb18 ) 800babc: 2203 movs r2, #3 800babe: 701a strb r2, [r3, #0] LED_State.tick = 0; 800bac0: 4b15 ldr r3, [pc, #84] @ (800bb18 ) 800bac2: 2200 movs r2, #0 800bac4: 805a strh r2, [r3, #2] } break; 800bac6: e01c b.n 800bb02 case LED_LOW: memcpy(&LED_State.color, &LED_Cycle.Color2, sizeof(RGB_t)); 800bac8: 4b13 ldr r3, [pc, #76] @ (800bb18 ) 800baca: 4a14 ldr r2, [pc, #80] @ (800bb1c ) 800bacc: 3304 adds r3, #4 800bace: 3207 adds r2, #7 800bad0: 8811 ldrh r1, [r2, #0] 800bad2: 7892 ldrb r2, [r2, #2] 800bad4: 8019 strh r1, [r3, #0] 800bad6: 709a strb r2, [r3, #2] if(LED_State.tick>LED_Cycle.Tl){ 800bad8: 4b0f ldr r3, [pc, #60] @ (800bb18 ) 800bada: 885b ldrh r3, [r3, #2] 800badc: 4a0f ldr r2, [pc, #60] @ (800bb1c ) 800bade: 7992 ldrb r2, [r2, #6] 800bae0: 4293 cmp r3, r2 800bae2: d910 bls.n 800bb06 LED_State.state = LED_RISING; 800bae4: 4b0c ldr r3, [pc, #48] @ (800bb18 ) 800bae6: 2200 movs r2, #0 800bae8: 701a strb r2, [r3, #0] LED_State.tick = 0; 800baea: 4b0b ldr r3, [pc, #44] @ (800bb18 ) 800baec: 2200 movs r2, #0 800baee: 805a strh r2, [r3, #2] } break; 800baf0: e009 b.n 800bb06 default: LED_State.state = LED_RISING; 800baf2: 4b09 ldr r3, [pc, #36] @ (800bb18 ) 800baf4: 2200 movs r2, #0 800baf6: 701a strb r2, [r3, #0] 800baf8: e006 b.n 800bb08 break; 800bafa: bf00 nop 800bafc: e004 b.n 800bb08 break; 800bafe: bf00 nop 800bb00: e002 b.n 800bb08 break; 800bb02: bf00 nop 800bb04: e000 b.n 800bb08 break; 800bb06: bf00 nop } RGB_SetColor(&LED_State.color); 800bb08: 4805 ldr r0, [pc, #20] @ (800bb20 ) 800bb0a: f7ff feff bl 800b90c } } 800bb0e: bf00 nop 800bb10: 46bd mov sp, r7 800bb12: bd80 pop {r7, pc} 800bb14: 20000970 .word 0x20000970 800bb18: 2000095c .word 0x2000095c 800bb1c: 20000964 .word 0x20000964 800bb20: 20000960 .word 0x20000960 800bb24: 2000096b .word 0x2000096b 0800bb28 : RTC_HandleTypeDef hrtc; /* RTC init function */ void MX_RTC_Init(void) { 800bb28: b580 push {r7, lr} 800bb2a: af00 add r7, sp, #0 /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; 800bb2c: 4b0a ldr r3, [pc, #40] @ (800bb58 ) 800bb2e: 4a0b ldr r2, [pc, #44] @ (800bb5c ) 800bb30: 601a str r2, [r3, #0] hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; 800bb32: 4b09 ldr r3, [pc, #36] @ (800bb58 ) 800bb34: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800bb38: 605a str r2, [r3, #4] hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM; 800bb3a: 4b07 ldr r3, [pc, #28] @ (800bb58 ) 800bb3c: f44f 7280 mov.w r2, #256 @ 0x100 800bb40: 609a str r2, [r3, #8] if (HAL_RTC_Init(&hrtc) != HAL_OK) 800bb42: 4805 ldr r0, [pc, #20] @ (800bb58 ) 800bb44: f006 f840 bl 8011bc8 800bb48: 4603 mov r3, r0 800bb4a: 2b00 cmp r3, #0 800bb4c: d001 beq.n 800bb52 { Error_Handler(); 800bb4e: f7ff f8c1 bl 800acd4 } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } 800bb52: bf00 nop 800bb54: bd80 pop {r7, pc} 800bb56: bf00 nop 800bb58: 20000974 .word 0x20000974 800bb5c: 40002800 .word 0x40002800 0800bb60 : void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) { 800bb60: b580 push {r7, lr} 800bb62: b084 sub sp, #16 800bb64: af00 add r7, sp, #0 800bb66: 6078 str r0, [r7, #4] if(rtcHandle->Instance==RTC) 800bb68: 687b ldr r3, [r7, #4] 800bb6a: 681b ldr r3, [r3, #0] 800bb6c: 4a0b ldr r2, [pc, #44] @ (800bb9c ) 800bb6e: 4293 cmp r3, r2 800bb70: d110 bne.n 800bb94 { /* USER CODE BEGIN RTC_MspInit 0 */ /* USER CODE END RTC_MspInit 0 */ HAL_PWR_EnableBkUpAccess(); 800bb72: f004 ffbd bl 8010af0 /* Enable BKP CLK enable for backup registers */ __HAL_RCC_BKP_CLK_ENABLE(); 800bb76: 4b0a ldr r3, [pc, #40] @ (800bba0 ) 800bb78: 69db ldr r3, [r3, #28] 800bb7a: 4a09 ldr r2, [pc, #36] @ (800bba0 ) 800bb7c: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800bb80: 61d3 str r3, [r2, #28] 800bb82: 4b07 ldr r3, [pc, #28] @ (800bba0 ) 800bb84: 69db ldr r3, [r3, #28] 800bb86: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800bb8a: 60fb str r3, [r7, #12] 800bb8c: 68fb ldr r3, [r7, #12] /* RTC clock enable */ __HAL_RCC_RTC_ENABLE(); 800bb8e: 4b05 ldr r3, [pc, #20] @ (800bba4 ) 800bb90: 2201 movs r2, #1 800bb92: 601a str r2, [r3, #0] /* USER CODE BEGIN RTC_MspInit 1 */ /* USER CODE END RTC_MspInit 1 */ } } 800bb94: bf00 nop 800bb96: 3710 adds r7, #16 800bb98: 46bd mov sp, r7 800bb9a: bd80 pop {r7, pc} 800bb9c: 40002800 .word 0x40002800 800bba0: 40021000 .word 0x40021000 800bba4: 4242043c .word 0x4242043c 0800bba8 : ISR_FAST static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len); static void CCS_UART3_Watchdog(void); static void CCS_LogUart3Error(const char *tag); ISR_FAST static void uart3_log_hal_error(uint8_t uart_num, uint32_t err) { 800bba8: 4602 mov r2, r0 if (err == HAL_UART_ERROR_NONE) { 800bbaa: b359 cbz r1, 800bc04 ISR_FAST static void uart3_log_hal_error(uint8_t uart_num, uint32_t err) { 800bbac: b570 push {r4, r5, r6, lr} 800bbae: 460c mov r4, r1 log_printf(LOG_ERR, "UART%u HAL error decode: NONE\n", uart_num); return; } log_printf(LOG_ERR, "UART%u HAL error decode: %s%s%s%s%s%s raw=0x%08lx\n", 800bbb0: 07cb lsls r3, r1, #31 800bbb2: bf58 it pl 800bbb4: 4915 ldrpl r1, [pc, #84] @ (800bc0c ) 800bbb6: 4d15 ldr r5, [pc, #84] @ (800bc0c ) 800bbb8: bf48 it mi 800bbba: 4914 ldrmi r1, [pc, #80] @ (800bc0c ) ISR_FAST static void uart3_log_hal_error(uint8_t uart_num, uint32_t err) { 800bbbc: b086 sub sp, #24 log_printf(LOG_ERR, "UART%u HAL error decode: %s%s%s%s%s%s raw=0x%08lx\n", 800bbbe: bf54 ite pl 800bbc0: 460b movpl r3, r1 800bbc2: 4b13 ldrmi r3, [pc, #76] @ (800bc10 ) 800bbc4: f014 0f02 tst.w r4, #2 800bbc8: 9104 str r1, [sp, #16] 800bbca: 4912 ldr r1, [pc, #72] @ (800bc14 ) 800bbcc: bf08 it eq 800bbce: 4629 moveq r1, r5 800bbd0: f014 0f04 tst.w r4, #4 800bbd4: 4810 ldr r0, [pc, #64] @ (800bc18 ) 800bbd6: bf08 it eq 800bbd8: 4628 moveq r0, r5 800bbda: f014 0f08 tst.w r4, #8 800bbde: 9001 str r0, [sp, #4] 800bbe0: 480e ldr r0, [pc, #56] @ (800bc1c ) 800bbe2: 4e0f ldr r6, [pc, #60] @ (800bc20 ) 800bbe4: bf08 it eq 800bbe6: 462e moveq r6, r5 800bbe8: f014 0f10 tst.w r4, #16 800bbec: bf18 it ne 800bbee: 4605 movne r5, r0 800bbf0: 9100 str r1, [sp, #0] 800bbf2: e9cd 6502 strd r6, r5, [sp, #8] 800bbf6: 490b ldr r1, [pc, #44] @ (800bc24 ) 800bbf8: 9405 str r4, [sp, #20] 800bbfa: 2004 movs r0, #4 800bbfc: f7fe fcb4 bl 800a568 (err & HAL_UART_ERROR_INVALID_CALLBACK) ? "INV_CB " : "", #else "", #endif (unsigned long)err); } 800bc00: b006 add sp, #24 800bc02: bd70 pop {r4, r5, r6, pc} log_printf(LOG_ERR, "UART%u HAL error decode: NONE\n", uart_num); 800bc04: 2004 movs r0, #4 800bc06: 4908 ldr r1, [pc, #32] @ (800bc28 ) 800bc08: f7fe bcae b.w 800a568 800bc0c: 080175b8 .word 0x080175b8 800bc10: 080171c0 .word 0x080171c0 800bc14: 080171c4 .word 0x080171c4 800bc18: 080171c8 .word 0x080171c8 800bc1c: 080171d4 .word 0x080171d4 800bc20: 080171cc .word 0x080171cc 800bc24: 080171fc .word 0x080171fc 800bc28: 080171dc .word 0x080171dc 0800bc2c : ISR_FAST static void uart3_arm_rx_or_log(const char *where) { 800bc2c: b530 push {r4, r5, lr} HAL_StatusTypeDef st = HAL_UARTEx_ReceiveToIdle_DMA(&huart3, rx_buffer, sizeof(rx_buffer)); 800bc2e: f44f 7280 mov.w r2, #256 @ 0x100 ISR_FAST static void uart3_arm_rx_or_log(const char *where) { 800bc32: 4605 mov r5, r0 800bc34: b083 sub sp, #12 HAL_StatusTypeDef st = HAL_UARTEx_ReceiveToIdle_DMA(&huart3, rx_buffer, sizeof(rx_buffer)); 800bc36: 4911 ldr r1, [pc, #68] @ (800bc7c ) 800bc38: 4811 ldr r0, [pc, #68] @ (800bc80 ) 800bc3a: f007 fa72 bl 8013122 if (st == HAL_OK) { 800bc3e: b908 cbnz r0, 800bc44 uart3_log_hal_error(3u, err_after); CCS_LogUart3Error("UART3 RX arm failed details"); if (err_after != HAL_UART_ERROR_NONE) { (void)HAL_UART_AbortReceive(&huart3); } } 800bc40: b003 add sp, #12 800bc42: bd30 pop {r4, r5, pc} uint32_t err_after = HAL_UART_GetError(&huart3); 800bc44: 4604 mov r4, r0 800bc46: 480e ldr r0, [pc, #56] @ (800bc80 ) 800bc48: f007 fe7d bl 8013946 800bc4c: 4602 mov r2, r0 log_printf(LOG_ERR, 800bc4e: 4623 mov r3, r4 uint32_t err_after = HAL_UART_GetError(&huart3); 800bc50: 4614 mov r4, r2 log_printf(LOG_ERR, 800bc52: 490c ldr r1, [pc, #48] @ (800bc84 ) 800bc54: 462a mov r2, r5 800bc56: 2004 movs r0, #4 800bc58: 9400 str r4, [sp, #0] 800bc5a: f7fe fc85 bl 800a568 uart3_log_hal_error(3u, err_after); 800bc5e: 2003 movs r0, #3 800bc60: 4621 mov r1, r4 800bc62: f7ff ffa1 bl 800bba8 CCS_LogUart3Error("UART3 RX arm failed details"); 800bc66: 4808 ldr r0, [pc, #32] @ (800bc88 ) 800bc68: f000 fedc bl 800ca24 if (err_after != HAL_UART_ERROR_NONE) { 800bc6c: 2c00 cmp r4, #0 800bc6e: d0e7 beq.n 800bc40 (void)HAL_UART_AbortReceive(&huart3); 800bc70: 4803 ldr r0, [pc, #12] @ (800bc80 ) } 800bc72: b003 add sp, #12 800bc74: e8bd 4030 ldmia.w sp!, {r4, r5, lr} (void)HAL_UART_AbortReceive(&huart3); 800bc78: f007 bb14 b.w 80132a4 800bc7c: 200009ac .word 0x200009ac 800bc80: 20001330 .word 0x20001330 800bc84: 08017230 .word 0x08017230 800bc88: 0801726c .word 0x0801726c 0800bc8c : ISR_FAST void CCS_RxEventCallback(UART_HandleTypeDef *huart, uint16_t size) { 800bc8c: b538 push {r3, r4, r5, lr} if (huart != &huart3) { 800bc8e: 4b1a ldr r3, [pc, #104] @ (800bcf8 ) ISR_FAST void CCS_RxEventCallback(UART_HandleTypeDef *huart, uint16_t size) { 800bc90: 460c mov r4, r1 if (huart != &huart3) { 800bc92: 4283 cmp r3, r0 800bc94: d113 bne.n 800bcbe log_printf(LOG_WARN, "UART3 RX drop: wrong huart in RxEventCallback (size=%u)\n", (unsigned)size); return; } if (size == 0u) { 800bc96: b329 cbz r1, 800bce4 log_printf(LOG_WARN, "UART3 RX drop: RxEvent size=0 (idle, no payload)\n"); uart3_arm_rx_or_log("RxEventCallback"); return; } if (size > sizeof(rx_buffer)) { 800bc98: f5b1 7f80 cmp.w r1, #256 @ 0x100 800bc9c: d816 bhi.n 800bccc log_printf(LOG_ERR, "UART3 RX drop: size=%u > rx_buffer %u (overflow, not parsed)\n", (unsigned)size, (unsigned)sizeof(rx_buffer)); uart3_arm_rx_or_log("RxEventCallback"); return; } uart3_last_packet_tick = HAL_GetTick(); 800bc9e: f002 fb77 bl 800e390 800bca2: 4603 mov r3, r0 800bca4: 4d15 ldr r5, [pc, #84] @ (800bcfc ) uart3_last_reinit_tick = uart3_last_packet_tick; 800bca6: 4a16 ldr r2, [pc, #88] @ (800bd00 ) process_received_packet(rx_buffer, size); 800bca8: 4621 mov r1, r4 800bcaa: 4816 ldr r0, [pc, #88] @ (800bd04 ) uart3_last_packet_tick = HAL_GetTick(); 800bcac: 602b str r3, [r5, #0] uart3_last_reinit_tick = uart3_last_packet_tick; 800bcae: 6013 str r3, [r2, #0] process_received_packet(rx_buffer, size); 800bcb0: f000 fe10 bl 800c8d4 uart3_arm_rx_or_log("RxEventCallback"); } 800bcb4: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} uart3_arm_rx_or_log("RxEventCallback"); 800bcb8: 4813 ldr r0, [pc, #76] @ (800bd08 ) 800bcba: f7ff bfb7 b.w 800bc2c log_printf(LOG_WARN, "UART3 RX drop: wrong huart in RxEventCallback (size=%u)\n", 800bcbe: 460a mov r2, r1 } 800bcc0: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} log_printf(LOG_WARN, "UART3 RX drop: wrong huart in RxEventCallback (size=%u)\n", 800bcc4: 2005 movs r0, #5 800bcc6: 4911 ldr r1, [pc, #68] @ (800bd0c ) 800bcc8: f7fe bc4e b.w 800a568 log_printf(LOG_ERR, "UART3 RX drop: size=%u > rx_buffer %u (overflow, not parsed)\n", 800bccc: f44f 7380 mov.w r3, #256 @ 0x100 800bcd0: 460a mov r2, r1 800bcd2: 2004 movs r0, #4 800bcd4: 490e ldr r1, [pc, #56] @ (800bd10 ) 800bcd6: f7fe fc47 bl 800a568 } 800bcda: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} uart3_arm_rx_or_log("RxEventCallback"); 800bcde: 480a ldr r0, [pc, #40] @ (800bd08 ) 800bce0: f7ff bfa4 b.w 800bc2c log_printf(LOG_WARN, "UART3 RX drop: RxEvent size=0 (idle, no payload)\n"); 800bce4: 2005 movs r0, #5 800bce6: 490b ldr r1, [pc, #44] @ (800bd14 ) 800bce8: f7fe fc3e bl 800a568 } 800bcec: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} uart3_arm_rx_or_log("RxEventCallback"); 800bcf0: 4805 ldr r0, [pc, #20] @ (800bd08 ) 800bcf2: f7ff bf9b b.w 800bc2c 800bcf6: bf00 nop 800bcf8: 20001330 .word 0x20001330 800bcfc: 20000cbc .word 0x20000cbc 800bd00: 20000cc0 .word 0x20000cc0 800bd04: 200009ac .word 0x200009ac 800bd08: 080172f8 .word 0x080172f8 800bd0c: 08017288 .word 0x08017288 800bd10: 08017308 .word 0x08017308 800bd14: 080172c4 .word 0x080172c4 0800bd18 : ISR_FAST void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 800bd18: b5f8 push {r3, r4, r5, r6, r7, lr} 800bd1a: 4604 mov r4, r0 uint32_t error = HAL_UART_GetError(huart); 800bd1c: f007 fe13 bl 8013946 uint8_t uart_num = 800bd20: 4b29 ldr r3, [pc, #164] @ (800bdc8 ) uint32_t error = HAL_UART_GetError(huart); 800bd22: 4605 mov r5, r0 uint8_t uart_num = 800bd24: 429c cmp r4, r3 800bd26: d032 beq.n 800bd8e 800bd28: 4e28 ldr r6, [pc, #160] @ (800bdcc ) 800bd2a: 42b4 cmp r4, r6 800bd2c: d017 beq.n 800bd5e 800bd2e: 4b28 ldr r3, [pc, #160] @ (800bdd0 ) 800bd30: 429c cmp r4, r3 800bd32: d045 beq.n 800bdc0 (huart == &huart2) ? 2 : (huart == &huart3) ? 3 : (huart == &huart5) ? 5 : 0; log_printf(LOG_ERR, 800bd34: 4603 mov r3, r0 800bd36: 2200 movs r2, #0 800bd38: 4926 ldr r1, [pc, #152] @ (800bdd4 ) 800bd3a: 2004 movs r0, #4 800bd3c: f7fe fc14 bl 800a568 "UART%u HAL error (ISR): raw=0x%08lx — RX may be corrupted until re-arm\n", uart_num, (unsigned long)error); uart3_log_hal_error(uart_num, error); 800bd40: 4629 mov r1, r5 800bd42: 2000 movs r0, #0 800bd44: f7ff ff30 bl 800bba8 (void)HAL_UART_AbortReceive(huart); 800bd48: 4620 mov r0, r4 800bd4a: f007 faab bl 80132a4 (void)HAL_UART_AbortTransmit(huart); 800bd4e: 4620 mov r0, r4 800bd50: f007 fa40 bl 80131d4 if (huart == &huart3) { uart3_tx_busy = 0; uart3_arm_rx_or_log("ErrorCallback"); } else { SC_RecoverUartDma(huart); 800bd54: 4620 mov r0, r4 } } 800bd56: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} SC_RecoverUartDma(huart); 800bd5a: f001 b91f b.w 800cf9c log_printf(LOG_ERR, 800bd5e: 4603 mov r3, r0 800bd60: 2203 movs r2, #3 800bd62: 491c ldr r1, [pc, #112] @ (800bdd4 ) 800bd64: 2004 movs r0, #4 800bd66: f7fe fbff bl 800a568 uart3_log_hal_error(uart_num, error); 800bd6a: 4629 mov r1, r5 800bd6c: 2003 movs r0, #3 800bd6e: f7ff ff1b bl 800bba8 (void)HAL_UART_AbortReceive(huart); 800bd72: 4620 mov r0, r4 800bd74: f007 fa96 bl 80132a4 (void)HAL_UART_AbortTransmit(huart); 800bd78: 4620 mov r0, r4 800bd7a: f007 fa2b bl 80131d4 uart3_tx_busy = 0; 800bd7e: 2200 movs r2, #0 800bd80: 4b15 ldr r3, [pc, #84] @ (800bdd8 ) uart3_arm_rx_or_log("ErrorCallback"); 800bd82: 4816 ldr r0, [pc, #88] @ (800bddc ) uart3_tx_busy = 0; 800bd84: 701a strb r2, [r3, #0] } 800bd86: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} uart3_arm_rx_or_log("ErrorCallback"); 800bd8a: f7ff bf4f b.w 800bc2c 800bd8e: 2202 movs r2, #2 uint8_t uart_num = 800bd90: 4617 mov r7, r2 800bd92: 4e0e ldr r6, [pc, #56] @ (800bdcc ) log_printf(LOG_ERR, 800bd94: 462b mov r3, r5 800bd96: 490f ldr r1, [pc, #60] @ (800bdd4 ) 800bd98: 2004 movs r0, #4 800bd9a: f7fe fbe5 bl 800a568 uart3_log_hal_error(uart_num, error); 800bd9e: 4629 mov r1, r5 800bda0: 4638 mov r0, r7 800bda2: f7ff ff01 bl 800bba8 (void)HAL_UART_AbortReceive(huart); 800bda6: 4620 mov r0, r4 800bda8: f007 fa7c bl 80132a4 (void)HAL_UART_AbortTransmit(huart); 800bdac: 4620 mov r0, r4 800bdae: f007 fa11 bl 80131d4 if (huart == &huart3) { 800bdb2: 42b4 cmp r4, r6 800bdb4: d0e3 beq.n 800bd7e SC_RecoverUartDma(huart); 800bdb6: 4620 mov r0, r4 } 800bdb8: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} SC_RecoverUartDma(huart); 800bdbc: f001 b8ee b.w 800cf9c 800bdc0: 2205 movs r2, #5 uint8_t uart_num = 800bdc2: 4617 mov r7, r2 800bdc4: e7e6 b.n 800bd94 800bdc6: bf00 nop 800bdc8: 200012e8 .word 0x200012e8 800bdcc: 20001330 .word 0x20001330 800bdd0: 20001258 .word 0x20001258 800bdd4: 08017348 .word 0x08017348 800bdd8: 20000cae .word 0x20000cae 800bddc: 08017394 .word 0x08017394 0800bde0 : void CCS_TxCpltCallback(UART_HandleTypeDef *huart) { 800bde0: b580 push {r7, lr} 800bde2: b082 sub sp, #8 800bde4: af00 add r7, sp, #0 800bde6: 6078 str r0, [r7, #4] if (huart != &huart3) { 800bde8: 687b ldr r3, [r7, #4] 800bdea: 4a16 ldr r2, [pc, #88] @ (800be44 ) 800bdec: 4293 cmp r3, r2 800bdee: d124 bne.n 800be3a return; } uart3_tx_busy = 0; 800bdf0: 4b15 ldr r3, [pc, #84] @ (800be48 ) 800bdf2: 2200 movs r2, #0 800bdf4: 701a strb r2, [r3, #0] if (tx_pending_len > 0) { 800bdf6: 4b15 ldr r3, [pc, #84] @ (800be4c ) 800bdf8: 881b ldrh r3, [r3, #0] 800bdfa: 2b00 cmp r3, #0 800bdfc: d01e beq.n 800be3c memcpy(tx_buffer, tx_pending_buffer, tx_pending_len); 800bdfe: 4b13 ldr r3, [pc, #76] @ (800be4c ) 800be00: 881b ldrh r3, [r3, #0] 800be02: 461a mov r2, r3 800be04: 4912 ldr r1, [pc, #72] @ (800be50 ) 800be06: 4813 ldr r0, [pc, #76] @ (800be54 ) 800be08: f008 ffc4 bl 8014d94 uart3_tx_busy = 1; 800be0c: 4b0e ldr r3, [pc, #56] @ (800be48 ) 800be0e: 2201 movs r2, #1 800be10: 701a strb r2, [r3, #0] if (HAL_UART_Transmit_DMA(&huart3, tx_buffer, tx_pending_len) != HAL_OK) { 800be12: 4b0e ldr r3, [pc, #56] @ (800be4c ) 800be14: 881b ldrh r3, [r3, #0] 800be16: 461a mov r2, r3 800be18: 490e ldr r1, [pc, #56] @ (800be54 ) 800be1a: 480a ldr r0, [pc, #40] @ (800be44 ) 800be1c: f007 f8b4 bl 8012f88 800be20: 4603 mov r3, r0 800be22: 2b00 cmp r3, #0 800be24: d005 beq.n 800be32 uart3_tx_busy = 0; 800be26: 4b08 ldr r3, [pc, #32] @ (800be48 ) 800be28: 2200 movs r2, #0 800be2a: 701a strb r2, [r3, #0] CCS_LogUart3Error("UART3 TX DMA resend failed"); 800be2c: 480a ldr r0, [pc, #40] @ (800be58 ) 800be2e: f000 fdf9 bl 800ca24 } tx_pending_len = 0; 800be32: 4b06 ldr r3, [pc, #24] @ (800be4c ) 800be34: 2200 movs r2, #0 800be36: 801a strh r2, [r3, #0] 800be38: e000 b.n 800be3c return; 800be3a: bf00 nop } } 800be3c: 3708 adds r7, #8 800be3e: 46bd mov sp, r7 800be40: bd80 pop {r7, pc} 800be42: bf00 nop 800be44: 20001330 .word 0x20001330 800be48: 20000cae .word 0x20000cae 800be4c: 20000cac .word 0x20000cac 800be50: 20000bac .word 0x20000bac 800be54: 20000aac .word 0x20000aac 800be58: 080173a4 .word 0x080173a4 0800be5c : void CCS_SerialLoop(void) { 800be5c: b580 push {r7, lr} 800be5e: b082 sub sp, #8 800be60: af00 add r7, sp, #0 static uint32_t tick; if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800be62: f002 fa95 bl 800e390 800be66: 4602 mov r2, r0 800be68: 4ba5 ldr r3, [pc, #660] @ (800c100 ) 800be6a: 681b ldr r3, [r3, #0] 800be6c: 1ad3 subs r3, r2, r3 800be6e: 2b00 cmp r3, #0 800be70: f340 826b ble.w 800c34a tick = HAL_GetTick(); 800be74: f002 fa8c bl 800e390 800be78: 4603 mov r3, r0 800be7a: 4aa1 ldr r2, [pc, #644] @ (800c100 ) 800be7c: 6013 str r3, [r2, #0] static uint32_t replug_watchdog1_tick = 0; static uint32_t last_state_sent = 0; static uint32_t force_unlock_tick = 0; static uint32_t stop_tick = 0; CCS_UART3_Watchdog(); 800be7e: f000 fd97 bl 800c9b0 if (CONN.connControl != CMD_NONE) { 800be82: 4ba0 ldr r3, [pc, #640] @ (800c104 ) 800be84: 781b ldrb r3, [r3, #0] 800be86: 2b00 cmp r3, #0 800be88: d003 beq.n 800be92 last_cmd = CONN.connControl; 800be8a: 4b9e ldr r3, [pc, #632] @ (800c104 ) 800be8c: 781a ldrb r2, [r3, #0] 800be8e: 4b9e ldr r3, [pc, #632] @ (800c108 ) 800be90: 701a strb r2, [r3, #0] } if (CONN.connControl == CMD_FORCE_UNLOCK) { 800be92: 4b9c ldr r3, [pc, #624] @ (800c104 ) 800be94: 781b ldrb r3, [r3, #0] 800be96: 2b03 cmp r3, #3 800be98: d11b bne.n 800bed2 if (force_unlock_tick == 0) { 800be9a: 4b9c ldr r3, [pc, #624] @ (800c10c ) 800be9c: 681b ldr r3, [r3, #0] 800be9e: 2b00 cmp r3, #0 800bea0: d105 bne.n 800beae force_unlock_tick = HAL_GetTick(); 800bea2: f002 fa75 bl 800e390 800bea6: 4603 mov r3, r0 800bea8: 4a98 ldr r2, [pc, #608] @ (800c10c ) 800beaa: 6013 str r3, [r2, #0] 800beac: e014 b.n 800bed8 } else if ((int32_t)(HAL_GetTick() - force_unlock_tick) >= 10000) { 800beae: f002 fa6f bl 800e390 800beb2: 4602 mov r2, r0 800beb4: 4b95 ldr r3, [pc, #596] @ (800c10c ) 800beb6: 681b ldr r3, [r3, #0] 800beb8: 1ad3 subs r3, r2, r3 800beba: 461a mov r2, r3 800bebc: f242 730f movw r3, #9999 @ 0x270f 800bec0: 429a cmp r2, r3 800bec2: dd09 ble.n 800bed8 CONN.connControl = CMD_NONE; 800bec4: 4b8f ldr r3, [pc, #572] @ (800c104 ) 800bec6: 2200 movs r2, #0 800bec8: 701a strb r2, [r3, #0] force_unlock_tick = 0; 800beca: 4b90 ldr r3, [pc, #576] @ (800c10c ) 800becc: 2200 movs r2, #0 800bece: 601a str r2, [r3, #0] 800bed0: e002 b.n 800bed8 } } else { force_unlock_tick = 0; 800bed2: 4b8e ldr r3, [pc, #568] @ (800c10c ) 800bed4: 2200 movs r2, #0 800bed6: 601a str r2, [r3, #0] } if (CONN.connControl == CMD_STOP) { 800bed8: 4b8a ldr r3, [pc, #552] @ (800c104 ) 800beda: 781b ldrb r3, [r3, #0] 800bedc: 2b01 cmp r3, #1 800bede: d119 bne.n 800bf14 if (stop_tick == 0) { 800bee0: 4b8b ldr r3, [pc, #556] @ (800c110 ) 800bee2: 681b ldr r3, [r3, #0] 800bee4: 2b00 cmp r3, #0 800bee6: d105 bne.n 800bef4 stop_tick = HAL_GetTick(); 800bee8: f002 fa52 bl 800e390 800beec: 4603 mov r3, r0 800beee: 4a88 ldr r2, [pc, #544] @ (800c110 ) 800bef0: 6013 str r3, [r2, #0] 800bef2: e012 b.n 800bf1a } else if ((int32_t)(HAL_GetTick() - stop_tick) >= 1000) { 800bef4: f002 fa4c bl 800e390 800bef8: 4602 mov r2, r0 800befa: 4b85 ldr r3, [pc, #532] @ (800c110 ) 800befc: 681b ldr r3, [r3, #0] 800befe: 1ad3 subs r3, r2, r3 800bf00: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bf04: db09 blt.n 800bf1a CONN.connControl = CMD_NONE; 800bf06: 4b7f ldr r3, [pc, #508] @ (800c104 ) 800bf08: 2200 movs r2, #0 800bf0a: 701a strb r2, [r3, #0] stop_tick = 0; 800bf0c: 4b80 ldr r3, [pc, #512] @ (800c110 ) 800bf0e: 2200 movs r2, #0 800bf10: 601a str r2, [r3, #0] 800bf12: e002 b.n 800bf1a } } else { stop_tick = 0; 800bf14: 4b7e ldr r3, [pc, #504] @ (800c110 ) 800bf16: 2200 movs r2, #0 800bf18: 601a str r2, [r3, #0] } if((int32_t)(HAL_GetTick() - last_cmd_sent) > (int32_t)CMD_INTERVAL){ 800bf1a: f002 fa39 bl 800e390 800bf1e: 4602 mov r2, r0 800bf20: 4b7c ldr r3, [pc, #496] @ (800c114 ) 800bf22: 681b ldr r3, [r3, #0] 800bf24: 1ad3 subs r3, r2, r3 800bf26: 2b0a cmp r3, #10 800bf28: dd5e ble.n 800bfe8 if ((int32_t)(HAL_GetTick() - last_state_sent) >= 200) { 800bf2a: f002 fa31 bl 800e390 800bf2e: 4602 mov r2, r0 800bf30: 4b79 ldr r3, [pc, #484] @ (800c118 ) 800bf32: 681b ldr r3, [r3, #0] 800bf34: 1ad3 subs r3, r2, r3 800bf36: 2bc7 cmp r3, #199 @ 0xc7 800bf38: dd06 ble.n 800bf48 send_state(); 800bf3a: f000 fb9b bl 800c674 last_state_sent = HAL_GetTick(); 800bf3e: f002 fa27 bl 800e390 800bf42: 4603 mov r3, r0 800bf44: 4a74 ldr r2, [pc, #464] @ (800c118 ) 800bf46: 6013 str r3, [r2, #0] } if (ESTOP) { 800bf48: 4b74 ldr r3, [pc, #464] @ (800c11c ) 800bf4a: 781b ldrb r3, [r3, #0] 800bf4c: 2b00 cmp r3, #0 800bf4e: d008 beq.n 800bf62 log_printf(LOG_ERR, "ESTOP triggered\n"); 800bf50: 4973 ldr r1, [pc, #460] @ (800c120 ) 800bf52: 2004 movs r0, #4 800bf54: f7fe fb08 bl 800a568 CCS_SendEmergencyStop(); 800bf58: f000 fb2c bl 800c5b4 ESTOP = 0; 800bf5c: 4b6f ldr r3, [pc, #444] @ (800c11c ) 800bf5e: 2200 movs r2, #0 800bf60: 701a strb r2, [r3, #0] } if (((CONN.connControl == CMD_STOP) || 800bf62: 4b68 ldr r3, [pc, #416] @ (800c104 ) 800bf64: 781b ldrb r3, [r3, #0] 800bf66: 2b01 cmp r3, #1 800bf68: d007 beq.n 800bf7a (CONN.connControl == CMD_FORCE_UNLOCK) || 800bf6a: 4b66 ldr r3, [pc, #408] @ (800c104 ) 800bf6c: 781b ldrb r3, [r3, #0] if (((CONN.connControl == CMD_STOP) || 800bf6e: 2b03 cmp r3, #3 800bf70: d003 beq.n 800bf7a (CONN.chargingError != CONN_NO_ERROR)) && 800bf72: 4b64 ldr r3, [pc, #400] @ (800c104 ) 800bf74: 7f5b ldrb r3, [r3, #29] (CONN.connControl == CMD_FORCE_UNLOCK) || 800bf76: 2b00 cmp r3, #0 800bf78: d01a beq.n 800bfb0 ((int32_t)(HAL_GetTick() - last_stop_sent) > 1000)) { 800bf7a: f002 fa09 bl 800e390 800bf7e: 4602 mov r2, r0 800bf80: 4b68 ldr r3, [pc, #416] @ (800c124 ) 800bf82: 681b ldr r3, [r3, #0] 800bf84: 1ad3 subs r3, r2, r3 (CONN.chargingError != CONN_NO_ERROR)) && 800bf86: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bf8a: dd11 ble.n 800bfb0 last_stop_sent = HAL_GetTick(); 800bf8c: f002 fa00 bl 800e390 800bf90: 4603 mov r3, r0 800bf92: 4a64 ldr r2, [pc, #400] @ (800c124 ) 800bf94: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "Stopping charging...\n"); 800bf96: 4964 ldr r1, [pc, #400] @ (800c128 ) 800bf98: 2005 movs r0, #5 800bf9a: f7fe fae5 bl 800a568 if (CONN.connControl == CMD_FORCE_UNLOCK) { 800bf9e: 4b59 ldr r3, [pc, #356] @ (800c104 ) 800bfa0: 781b ldrb r3, [r3, #0] 800bfa2: 2b03 cmp r3, #3 800bfa4: d102 bne.n 800bfac CP_SetDuty(100); 800bfa6: 2064 movs r0, #100 @ 0x64 800bfa8: f7fe f89c bl 800a0e4 } CCS_SendEmergencyStop(); 800bfac: f000 fb02 bl 800c5b4 } if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800bfb0: 4b5e ldr r3, [pc, #376] @ (800c12c ) 800bfb2: 781b ldrb r3, [r3, #0] 800bfb4: 2b0c cmp r3, #12 800bfb6: d003 beq.n 800bfc0 800bfb8: 4b5c ldr r3, [pc, #368] @ (800c12c ) 800bfba: 781b ldrb r3, [r3, #0] 800bfbc: 2b0b cmp r3, #11 800bfbe: d113 bne.n 800bfe8 ((int32_t)(HAL_GetTick() - last_stop_sent) > 1000)) { 800bfc0: f002 f9e6 bl 800e390 800bfc4: 4602 mov r2, r0 800bfc6: 4b57 ldr r3, [pc, #348] @ (800c124 ) 800bfc8: 681b ldr r3, [r3, #0] 800bfca: 1ad3 subs r3, r2, r3 if (((CCS_EvseState == FinishedEV) || (CCS_EvseState == FinishedEVSE)) && 800bfcc: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800bfd0: dd0a ble.n 800bfe8 last_stop_sent = HAL_GetTick(); 800bfd2: f002 f9dd bl 800e390 800bfd6: 4603 mov r3, r0 800bfd8: 4a52 ldr r2, [pc, #328] @ (800c124 ) 800bfda: 6013 str r3, [r2, #0] log_printf(LOG_WARN, "FinishedEV, stopping...\n"); 800bfdc: 4954 ldr r1, [pc, #336] @ (800c130 ) 800bfde: 2005 movs r0, #5 800bfe0: f7fe fac2 bl 800a568 CCS_SendEmergencyStop(); 800bfe4: f000 fae6 bl 800c5b4 } (void)replug_watchdog_tick; (void)replug_watchdog1_tick; uint8_t host_timeout_warn = (last_host_seen > 0u) && ((int32_t)(HAL_GetTick() - last_host_seen) > (int32_t)EVEREST_TIMEOUT_WARN_MS); 800bfe8: 4b52 ldr r3, [pc, #328] @ (800c134 ) 800bfea: 681b ldr r3, [r3, #0] 800bfec: 2b00 cmp r3, #0 800bfee: d00c beq.n 800c00a 800bff0: f002 f9ce bl 800e390 800bff4: 4602 mov r2, r0 800bff6: 4b4f ldr r3, [pc, #316] @ (800c134 ) 800bff8: 681b ldr r3, [r3, #0] 800bffa: 1ad3 subs r3, r2, r3 800bffc: 461a mov r2, r3 800bffe: f241 3388 movw r3, #5000 @ 0x1388 800c002: 429a cmp r2, r3 800c004: dd01 ble.n 800c00a 800c006: 2301 movs r3, #1 800c008: e000 b.n 800c00c 800c00a: 2300 movs r3, #0 800c00c: 71fb strb r3, [r7, #7] uint8_t host_timeout_stop = (last_host_seen > 0u) && ((int32_t)(HAL_GetTick() - last_host_seen) > (int32_t)EVEREST_TIMEOUT_STOP_MS); 800c00e: 4b49 ldr r3, [pc, #292] @ (800c134 ) 800c010: 681b ldr r3, [r3, #0] 800c012: 2b00 cmp r3, #0 800c014: d00c beq.n 800c030 800c016: f002 f9bb bl 800e390 800c01a: 4602 mov r2, r0 800c01c: 4b45 ldr r3, [pc, #276] @ (800c134 ) 800c01e: 681b ldr r3, [r3, #0] 800c020: 1ad3 subs r3, r2, r3 800c022: 461a mov r2, r3 800c024: f242 7310 movw r3, #10000 @ 0x2710 800c028: 429a cmp r2, r3 800c02a: dd01 ble.n 800c030 800c02c: 2301 movs r3, #1 800c02e: e000 b.n 800c032 800c030: 2300 movs r3, #0 800c032: 71bb strb r3, [r7, #6] uint8_t host_timed_out = host_timeout_stop; 800c034: 79bb ldrb r3, [r7, #6] 800c036: 717b strb r3, [r7, #5] if (host_timeout_warn && !everest_timeout_warn_latched) { 800c038: 79fb ldrb r3, [r7, #7] 800c03a: 2b00 cmp r3, #0 800c03c: d00a beq.n 800c054 800c03e: 4b3e ldr r3, [pc, #248] @ (800c138 ) 800c040: 781b ldrb r3, [r3, #0] 800c042: 2b00 cmp r3, #0 800c044: d106 bne.n 800c054 log_printf(LOG_ERR, "Everest timeout\n"); 800c046: 493d ldr r1, [pc, #244] @ (800c13c ) 800c048: 2004 movs r0, #4 800c04a: f7fe fa8d bl 800a568 everest_timeout_warn_latched = 1; 800c04e: 4b3a ldr r3, [pc, #232] @ (800c138 ) 800c050: 2201 movs r2, #1 800c052: 701a strb r2, [r3, #0] } if (host_timeout_stop && !everest_timeout_stop_latched) { 800c054: 79bb ldrb r3, [r7, #6] 800c056: 2b00 cmp r3, #0 800c058: d00a beq.n 800c070 800c05a: 4b39 ldr r3, [pc, #228] @ (800c140 ) 800c05c: 781b ldrb r3, [r3, #0] 800c05e: 2b00 cmp r3, #0 800c060: d106 bne.n 800c070 log_printf(LOG_ERR, "Everest timeout, stopping charging...\n"); 800c062: 4938 ldr r1, [pc, #224] @ (800c144 ) 800c064: 2004 movs r0, #4 800c066: f7fe fa7f bl 800a568 everest_timeout_stop_latched = 1; 800c06a: 4b35 ldr r3, [pc, #212] @ (800c140 ) 800c06c: 2201 movs r2, #1 800c06e: 701a strb r2, [r3, #0] } if (!host_timeout_warn) { 800c070: 79fb ldrb r3, [r7, #7] 800c072: 2b00 cmp r3, #0 800c074: d105 bne.n 800c082 everest_timeout_warn_latched = 0; 800c076: 4b30 ldr r3, [pc, #192] @ (800c138 ) 800c078: 2200 movs r2, #0 800c07a: 701a strb r2, [r3, #0] everest_timeout_stop_latched = 0; 800c07c: 4b30 ldr r3, [pc, #192] @ (800c140 ) 800c07e: 2200 movs r2, #0 800c080: 701a strb r2, [r3, #0] } everest_timed_out = host_timeout_stop; 800c082: 4a31 ldr r2, [pc, #196] @ (800c148 ) 800c084: 79bb ldrb r3, [r7, #6] 800c086: 7013 strb r3, [r2, #0] switch(CCS_ConnectorState){ 800c088: 4b30 ldr r3, [pc, #192] @ (800c14c ) 800c08a: 781b ldrb r3, [r3, #0] 800c08c: 2b05 cmp r3, #5 800c08e: f200 8113 bhi.w 800c2b8 800c092: a201 add r2, pc, #4 @ (adr r2, 800c098 ) 800c094: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c098: 0800c0b1 .word 0x0800c0b1 800c09c: 0800c0d9 .word 0x0800c0d9 800c0a0: 0800c155 .word 0x0800c155 800c0a4: 0800c199 .word 0x0800c199 800c0a8: 0800c1d5 .word 0x0800c1d5 800c0ac: 0800c22d .word 0x0800c22d case CCS_UNKNOWN: RELAY_Write(RELAY_CP, 0); 800c0b0: 2100 movs r1, #0 800c0b2: 2005 movs r0, #5 800c0b4: f7fd fb80 bl 80097b8 CONN_SetState(Unknown); 800c0b8: 2000 movs r0, #0 800c0ba: f7fd ff1b bl 8009ef4 if (config_initialized && !host_timed_out) { 800c0be: 4b24 ldr r3, [pc, #144] @ (800c150 ) 800c0c0: 781b ldrb r3, [r3, #0] 800c0c2: 2b00 cmp r3, #0 800c0c4: f000 80ed beq.w 800c2a2 800c0c8: 797b ldrb r3, [r7, #5] 800c0ca: 2b00 cmp r3, #0 800c0cc: f040 80e9 bne.w 800c2a2 CCS_ConnectorState = CCS_UNPLUGGED; 800c0d0: 4b1e ldr r3, [pc, #120] @ (800c14c ) 800c0d2: 2202 movs r2, #2 800c0d4: 701a strb r2, [r3, #0] } break; 800c0d6: e0e4 b.n 800c2a2 case CCS_DISABLED: RELAY_Write(RELAY_CP, 0); 800c0d8: 2100 movs r1, #0 800c0da: 2005 movs r0, #5 800c0dc: f7fd fb6c bl 80097b8 CONN_SetState(Disabled); 800c0e0: 2002 movs r0, #2 800c0e2: f7fd ff07 bl 8009ef4 if ((CONN.chargingError == CONN_NO_ERROR) && !host_timed_out){ 800c0e6: 4b07 ldr r3, [pc, #28] @ (800c104 ) 800c0e8: 7f5b ldrb r3, [r3, #29] 800c0ea: 2b00 cmp r3, #0 800c0ec: f040 80db bne.w 800c2a6 800c0f0: 797b ldrb r3, [r7, #5] 800c0f2: 2b00 cmp r3, #0 800c0f4: f040 80d7 bne.w 800c2a6 CCS_ConnectorState = CCS_UNPLUGGED; 800c0f8: 4b14 ldr r3, [pc, #80] @ (800c14c ) 800c0fa: 2202 movs r2, #2 800c0fc: 701a strb r2, [r3, #0] } break; 800c0fe: e0d2 b.n 800c2a6 800c100: 20000d14 .word 0x20000d14 800c104: 200003b0 .word 0x200003b0 800c108: 200009a8 .word 0x200009a8 800c10c: 20000d18 .word 0x20000d18 800c110: 20000d1c .word 0x20000d1c 800c114: 200009a0 .word 0x200009a0 800c118: 20000d20 .word 0x20000d20 800c11c: 20000caf .word 0x20000caf 800c120: 080173c0 .word 0x080173c0 800c124: 200009a4 .word 0x200009a4 800c128: 080173d4 .word 0x080173d4 800c12c: 20000d10 .word 0x20000d10 800c130: 080173ec .word 0x080173ec 800c134: 20000cb4 .word 0x20000cb4 800c138: 20000cba .word 0x20000cba 800c13c: 08017408 .word 0x08017408 800c140: 20000cbb .word 0x20000cbb 800c144: 0801741c .word 0x0801741c 800c148: 20000cb9 .word 0x20000cb9 800c14c: 20000d11 .word 0x20000d11 800c150: 200011c0 .word 0x200011c0 case CCS_UNPLUGGED: RELAY_Write(RELAY_CP, 1); 800c154: 2101 movs r1, #1 800c156: 2005 movs r0, #5 800c158: f7fd fb2e bl 80097b8 CONN_SetState(Unplugged); 800c15c: 2001 movs r0, #1 800c15e: f7fd fec9 bl 8009ef4 if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || (cp_state_buffer == EV_STATE_C_CONN_ACTIVE)){ 800c162: 4b7c ldr r3, [pc, #496] @ (800c354 ) 800c164: 781b ldrb r3, [r3, #0] 800c166: 2b01 cmp r3, #1 800c168: d003 beq.n 800c172 800c16a: 4b7a ldr r3, [pc, #488] @ (800c354 ) 800c16c: 781b ldrb r3, [r3, #0] 800c16e: 2b02 cmp r3, #2 800c170: d102 bne.n 800c178 CCS_ConnectorState = CCS_AUTH_REQUIRED; 800c172: 4b79 ldr r3, [pc, #484] @ (800c358 ) 800c174: 2203 movs r2, #3 800c176: 701a strb r2, [r3, #0] } if (CONN.chargingError != CONN_NO_ERROR){ 800c178: 4b78 ldr r3, [pc, #480] @ (800c35c ) 800c17a: 7f5b ldrb r3, [r3, #29] 800c17c: 2b00 cmp r3, #0 800c17e: f000 8094 beq.w 800c2aa log_printf(LOG_ERR, "Charging error %d, state -> disabled\n", CONN.chargingError); 800c182: 4b76 ldr r3, [pc, #472] @ (800c35c ) 800c184: 7f5b ldrb r3, [r3, #29] 800c186: 461a mov r2, r3 800c188: 4975 ldr r1, [pc, #468] @ (800c360 ) 800c18a: 2004 movs r0, #4 800c18c: f7fe f9ec bl 800a568 CCS_ConnectorState = CCS_DISABLED; 800c190: 4b71 ldr r3, [pc, #452] @ (800c358 ) 800c192: 2201 movs r2, #1 800c194: 701a strb r2, [r3, #0] } break; 800c196: e088 b.n 800c2aa case CCS_AUTH_REQUIRED: RELAY_Write(RELAY_CP, 1); 800c198: 2101 movs r1, #1 800c19a: 2005 movs r0, #5 800c19c: f7fd fb0c bl 80097b8 CONN_SetState(AuthRequired); 800c1a0: 2004 movs r0, #4 800c1a2: f7fd fea7 bl 8009ef4 if(CONN.connControl == CMD_START){ 800c1a6: 4b6d ldr r3, [pc, #436] @ (800c35c ) 800c1a8: 781b ldrb r3, [r3, #0] 800c1aa: 2b02 cmp r3, #2 800c1ac: d106 bne.n 800c1bc log_printf(LOG_INFO, "Charging permitted, start charging\n"); 800c1ae: 496d ldr r1, [pc, #436] @ (800c364 ) 800c1b0: 2007 movs r0, #7 800c1b2: f7fe f9d9 bl 800a568 CCS_ConnectorState = CCS_CONNECTED; 800c1b6: 4b68 ldr r3, [pc, #416] @ (800c358 ) 800c1b8: 2204 movs r2, #4 800c1ba: 701a strb r2, [r3, #0] } if (cp_state_buffer == EV_STATE_A_IDLE){ 800c1bc: 4b65 ldr r3, [pc, #404] @ (800c354 ) 800c1be: 781b ldrb r3, [r3, #0] 800c1c0: 2b00 cmp r3, #0 800c1c2: d174 bne.n 800c2ae log_printf(LOG_INFO, "Car unplugged\n"); 800c1c4: 4968 ldr r1, [pc, #416] @ (800c368 ) 800c1c6: 2007 movs r0, #7 800c1c8: f7fe f9ce bl 800a568 CCS_ConnectorState = CCS_UNPLUGGED; 800c1cc: 4b62 ldr r3, [pc, #392] @ (800c358 ) 800c1ce: 2202 movs r2, #2 800c1d0: 701a strb r2, [r3, #0] } break; 800c1d2: e06c b.n 800c2ae case CCS_CONNECTED: RELAY_Write(RELAY_CP, 1); 800c1d4: 2101 movs r1, #1 800c1d6: 2005 movs r0, #5 800c1d8: f7fd faee bl 80097b8 if((CCS_EvseState < Preparing) || (CCS_EvseState == AuthRequired)) { 800c1dc: 4b63 ldr r3, [pc, #396] @ (800c36c ) 800c1de: 781b ldrb r3, [r3, #0] 800c1e0: 2b02 cmp r3, #2 800c1e2: d903 bls.n 800c1ec 800c1e4: 4b61 ldr r3, [pc, #388] @ (800c36c ) 800c1e6: 781b ldrb r3, [r3, #0] 800c1e8: 2b04 cmp r3, #4 800c1ea: d103 bne.n 800c1f4 CONN_SetState(Preparing); 800c1ec: 2003 movs r0, #3 800c1ee: f7fd fe81 bl 8009ef4 800c1f2: e004 b.n 800c1fe } else { CONN_SetState(CCS_EvseState); 800c1f4: 4b5d ldr r3, [pc, #372] @ (800c36c ) 800c1f6: 781b ldrb r3, [r3, #0] 800c1f8: 4618 mov r0, r3 800c1fa: f7fd fe7b bl 8009ef4 } if (cp_state_buffer == EV_STATE_A_IDLE){ 800c1fe: 4b55 ldr r3, [pc, #340] @ (800c354 ) 800c200: 781b ldrb r3, [r3, #0] 800c202: 2b00 cmp r3, #0 800c204: d106 bne.n 800c214 log_printf(LOG_INFO, "Car unplugged\n"); 800c206: 4958 ldr r1, [pc, #352] @ (800c368 ) 800c208: 2007 movs r0, #7 800c20a: f7fe f9ad bl 800a568 CCS_ConnectorState = CCS_UNPLUGGED; 800c20e: 4b52 ldr r3, [pc, #328] @ (800c358 ) 800c210: 2202 movs r2, #2 800c212: 701a strb r2, [r3, #0] } if(REPLUG > 0){ 800c214: 4b56 ldr r3, [pc, #344] @ (800c370 ) 800c216: 781b ldrb r3, [r3, #0] 800c218: 2b00 cmp r3, #0 800c21a: d04a beq.n 800c2b2 log_printf(LOG_INFO, "Replugging...\n"); 800c21c: 4955 ldr r1, [pc, #340] @ (800c374 ) 800c21e: 2007 movs r0, #7 800c220: f7fe f9a2 bl 800a568 CCS_ConnectorState = CCS_REPLUGGING; 800c224: 4b4c ldr r3, [pc, #304] @ (800c358 ) 800c226: 2205 movs r2, #5 800c228: 701a strb r2, [r3, #0] } break; 800c22a: e042 b.n 800c2b2 case CCS_REPLUGGING: RELAY_Write(RELAY_CP, 0); 800c22c: 2100 movs r1, #0 800c22e: 2005 movs r0, #5 800c230: f7fd fac2 bl 80097b8 CONN_SetState(Replugging); 800c234: 200d movs r0, #13 800c236: f7fd fe5d bl 8009ef4 if((int32_t)(HAL_GetTick() - replug_tick) > 1000){ 800c23a: f002 f8a9 bl 800e390 800c23e: 4602 mov r2, r0 800c240: 4b4d ldr r3, [pc, #308] @ (800c378 ) 800c242: 681b ldr r3, [r3, #0] 800c244: 1ad3 subs r3, r2, r3 800c246: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800c24a: dd1a ble.n 800c282 replug_tick = HAL_GetTick(); 800c24c: f002 f8a0 bl 800e390 800c250: 4603 mov r3, r0 800c252: 4a49 ldr r2, [pc, #292] @ (800c378 ) 800c254: 6013 str r3, [r2, #0] if(REPLUG > 0){ 800c256: 4b46 ldr r3, [pc, #280] @ (800c370 ) 800c258: 781b ldrb r3, [r3, #0] 800c25a: 2b00 cmp r3, #0 800c25c: d00a beq.n 800c274 if (REPLUG != 0xFF) REPLUG--; 800c25e: 4b44 ldr r3, [pc, #272] @ (800c370 ) 800c260: 781b ldrb r3, [r3, #0] 800c262: 2bff cmp r3, #255 @ 0xff 800c264: d00d beq.n 800c282 800c266: 4b42 ldr r3, [pc, #264] @ (800c370 ) 800c268: 781b ldrb r3, [r3, #0] 800c26a: 3b01 subs r3, #1 800c26c: b2da uxtb r2, r3 800c26e: 4b40 ldr r3, [pc, #256] @ (800c370 ) 800c270: 701a strb r2, [r3, #0] 800c272: e006 b.n 800c282 } else { log_printf(LOG_INFO, "Replugging finished, but car unplugged\n"); 800c274: 4941 ldr r1, [pc, #260] @ (800c37c ) 800c276: 2007 movs r0, #7 800c278: f7fe f976 bl 800a568 CCS_ConnectorState = CCS_UNPLUGGED; 800c27c: 4b36 ldr r3, [pc, #216] @ (800c358 ) 800c27e: 2202 movs r2, #2 800c280: 701a strb r2, [r3, #0] } } if(REPLUG == 0){ 800c282: 4b3b ldr r3, [pc, #236] @ (800c370 ) 800c284: 781b ldrb r3, [r3, #0] 800c286: 2b00 cmp r3, #0 800c288: d115 bne.n 800c2b6 if(cp_state_buffer == EV_STATE_B_CONN_PREP){ 800c28a: 4b32 ldr r3, [pc, #200] @ (800c354 ) 800c28c: 781b ldrb r3, [r3, #0] 800c28e: 2b01 cmp r3, #1 800c290: d111 bne.n 800c2b6 log_printf(LOG_INFO, "Replugging finished, car plugged, state -> auth required\n"); 800c292: 493b ldr r1, [pc, #236] @ (800c380 ) 800c294: 2007 movs r0, #7 800c296: f7fe f967 bl 800a568 CCS_ConnectorState = CCS_AUTH_REQUIRED; 800c29a: 4b2f ldr r3, [pc, #188] @ (800c358 ) 800c29c: 2203 movs r2, #3 800c29e: 701a strb r2, [r3, #0] } } break; 800c2a0: e009 b.n 800c2b6 break; 800c2a2: bf00 nop 800c2a4: e008 b.n 800c2b8 break; 800c2a6: bf00 nop 800c2a8: e006 b.n 800c2b8 break; 800c2aa: bf00 nop 800c2ac: e004 b.n 800c2b8 break; 800c2ae: bf00 nop 800c2b0: e002 b.n 800c2b8 break; 800c2b2: bf00 nop 800c2b4: e000 b.n 800c2b8 break; 800c2b6: bf00 nop } // 10s timeout: enforce safe-state until host communication recovers. if (host_timeout_stop) { 800c2b8: 79bb ldrb r3, [r7, #6] 800c2ba: 2b00 cmp r3, #0 800c2bc: d014 beq.n 800c2e8 CONN.EnableOutput = 0; 800c2be: 4b27 ldr r3, [pc, #156] @ (800c35c ) 800c2c0: 2200 movs r2, #0 800c2c2: 75da strb r2, [r3, #23] CCS_EvseState = Unknown; 800c2c4: 4b29 ldr r3, [pc, #164] @ (800c36c ) 800c2c6: 2200 movs r2, #0 800c2c8: 701a strb r2, [r3, #0] CP_SetDuty(100); 800c2ca: 2064 movs r0, #100 @ 0x64 800c2cc: f7fd ff0a bl 800a0e4 if (CCS_ConnectorState != CCS_DISABLED && CCS_ConnectorState != CCS_UNKNOWN) { 800c2d0: 4b21 ldr r3, [pc, #132] @ (800c358 ) 800c2d2: 781b ldrb r3, [r3, #0] 800c2d4: 2b01 cmp r3, #1 800c2d6: d024 beq.n 800c322 800c2d8: 4b1f ldr r3, [pc, #124] @ (800c358 ) 800c2da: 781b ldrb r3, [r3, #0] 800c2dc: 2b00 cmp r3, #0 800c2de: d020 beq.n 800c322 CCS_ConnectorState = CCS_DISABLED; 800c2e0: 4b1d ldr r3, [pc, #116] @ (800c358 ) 800c2e2: 2201 movs r2, #1 800c2e4: 701a strb r2, [r3, #0] 800c2e6: e01c b.n 800c322 } } else { if (last_cmd == CMD_STOP) { 800c2e8: 4b26 ldr r3, [pc, #152] @ (800c384 ) 800c2ea: 781b ldrb r3, [r3, #0] 800c2ec: 2b01 cmp r3, #1 800c2ee: d103 bne.n 800c2f8 CONN.EnableOutput = 0; 800c2f0: 4b1a ldr r3, [pc, #104] @ (800c35c ) 800c2f2: 2200 movs r2, #0 800c2f4: 75da strb r2, [r3, #23] 800c2f6: e014 b.n 800c322 } else { CONN.EnableOutput = ev_enable_output ? 1 : 0; 800c2f8: 4b23 ldr r3, [pc, #140] @ (800c388 ) 800c2fa: 781b ldrb r3, [r3, #0] 800c2fc: 2b00 cmp r3, #0 800c2fe: bf14 ite ne 800c300: 2301 movne r3, #1 800c302: 2300 moveq r3, #0 800c304: b2db uxtb r3, r3 800c306: 461a mov r2, r3 800c308: 4b14 ldr r3, [pc, #80] @ (800c35c ) 800c30a: 75da strb r2, [r3, #23] if((CONN.EnableOutput == 0) && (CONN.connState == Preparing)){ 800c30c: 4b13 ldr r3, [pc, #76] @ (800c35c ) 800c30e: 7ddb ldrb r3, [r3, #23] 800c310: 2b00 cmp r3, #0 800c312: d106 bne.n 800c322 800c314: 4b11 ldr r3, [pc, #68] @ (800c35c ) 800c316: 785b ldrb r3, [r3, #1] 800c318: 2b03 cmp r3, #3 800c31a: d102 bne.n 800c322 CONN.EnableOutput = 0; 800c31c: 4b0f ldr r3, [pc, #60] @ (800c35c ) 800c31e: 2200 movs r2, #0 800c320: 75da strb r2, [r3, #23] } } } if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800c322: 4b0c ldr r3, [pc, #48] @ (800c354 ) 800c324: 781b ldrb r3, [r3, #0] 800c326: 2b01 cmp r3, #1 800c328: d007 beq.n 800c33a (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800c32a: 4b0a ldr r3, [pc, #40] @ (800c354 ) 800c32c: 781b ldrb r3, [r3, #0] if ((cp_state_buffer == EV_STATE_B_CONN_PREP) || 800c32e: 2b02 cmp r3, #2 800c330: d003 beq.n 800c33a (cp_state_buffer == EV_STATE_D_CONN_ACT_VENT)) { 800c332: 4b08 ldr r3, [pc, #32] @ (800c354 ) 800c334: 781b ldrb r3, [r3, #0] (cp_state_buffer == EV_STATE_C_CONN_ACTIVE) || 800c336: 2b03 cmp r3, #3 800c338: d103 bne.n 800c342 CONN.EvConnected = 1; 800c33a: 4b08 ldr r3, [pc, #32] @ (800c35c ) 800c33c: 2201 movs r2, #1 800c33e: 779a strb r2, [r3, #30] 800c340: e004 b.n 800c34c } else { CONN.EvConnected = 0; 800c342: 4b06 ldr r3, [pc, #24] @ (800c35c ) 800c344: 2200 movs r2, #0 800c346: 779a strb r2, [r3, #30] 800c348: e000 b.n 800c34c if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800c34a: bf00 nop } } 800c34c: 3708 adds r7, #8 800c34e: 46bd mov sp, r7 800c350: bd80 pop {r7, pc} 800c352: bf00 nop 800c354: 20000005 .word 0x20000005 800c358: 20000d11 .word 0x20000d11 800c35c: 200003b0 .word 0x200003b0 800c360: 08017444 .word 0x08017444 800c364: 0801746c .word 0x0801746c 800c368: 08017490 .word 0x08017490 800c36c: 20000d10 .word 0x20000d10 800c370: 20000cb0 .word 0x20000cb0 800c374: 080174a0 .word 0x080174a0 800c378: 20000d24 .word 0x20000d24 800c37c: 080174b0 .word 0x080174b0 800c380: 080174d8 .word 0x080174d8 800c384: 200009a8 .word 0x200009a8 800c388: 200009a9 .word 0x200009a9 0800c38c : void CCS_Init(void){ 800c38c: b580 push {r7, lr} 800c38e: af00 add r7, sp, #0 CP_Init(); 800c390: f7fd fe86 bl 800a0a0 CP_SetDuty(100); 800c394: 2064 movs r0, #100 @ 0x64 800c396: f7fd fea5 bl 800a0e4 CCS_MaxLoad.maxVoltage = PSU_MAX_VOLTAGE; // 1000V 800c39a: 4b13 ldr r3, [pc, #76] @ (800c3e8 ) 800c39c: f44f 727a mov.w r2, #1000 @ 0x3e8 800c3a0: 801a strh r2, [r3, #0] CCS_MaxLoad.minVoltage = PSU_MIN_VOLTAGE; //150V 800c3a2: 4b11 ldr r3, [pc, #68] @ (800c3e8 ) 800c3a4: 2296 movs r2, #150 @ 0x96 800c3a6: 805a strh r2, [r3, #2] CCS_MaxLoad.maxCurrent = PSU_MAX_CURRENT*10; //100A 800c3a8: 4b0f ldr r3, [pc, #60] @ (800c3e8 ) 800c3aa: f240 5232 movw r2, #1330 @ 0x532 800c3ae: 809a strh r2, [r3, #4] CCS_MaxLoad.minCurrent = PSU_MIN_CURRENT*10; //1A 800c3b0: 4b0d ldr r3, [pc, #52] @ (800c3e8 ) 800c3b2: 220a movs r2, #10 800c3b4: 80da strh r2, [r3, #6] CCS_MaxLoad.maxPower = PSU_MAX_POWER; //30000W 800c3b6: 4b0c ldr r3, [pc, #48] @ (800c3e8 ) 800c3b8: f649 4240 movw r2, #40000 @ 0x9c40 800c3bc: 609a str r2, [r3, #8] uart3_last_packet_tick = HAL_GetTick(); 800c3be: f001 ffe7 bl 800e390 800c3c2: 4603 mov r3, r0 800c3c4: 4a09 ldr r2, [pc, #36] @ (800c3ec ) 800c3c6: 6013 str r3, [r2, #0] uart3_last_reinit_tick = uart3_last_packet_tick; 800c3c8: 4b08 ldr r3, [pc, #32] @ (800c3ec ) 800c3ca: 681b ldr r3, [r3, #0] 800c3cc: 4a08 ldr r2, [pc, #32] @ (800c3f0 ) 800c3ce: 6013 str r3, [r2, #0] uart3_arm_rx_or_log("Init"); 800c3d0: 4808 ldr r0, [pc, #32] @ (800c3f4 ) 800c3d2: f7ff fc2b bl 800bc2c CCS_SendResetReason(); 800c3d6: f000 f8e3 bl 800c5a0 log_printf(LOG_INFO, "CCS init\n"); 800c3da: 4907 ldr r1, [pc, #28] @ (800c3f8 ) 800c3dc: 2007 movs r0, #7 800c3de: f7fe f8c3 bl 800a568 } 800c3e2: bf00 nop 800c3e4: bd80 pop {r7, pc} 800c3e6: bf00 nop 800c3e8: 20000988 .word 0x20000988 800c3ec: 20000cbc .word 0x20000cbc 800c3f0: 20000cc0 .word 0x20000cc0 800c3f4: 08017514 .word 0x08017514 800c3f8: 0801751c .word 0x0801751c 0800c3fc : ISR_FAST static uint16_t crc16_ibm(const uint8_t* data, uint16_t length) { uint16_t crc = 0xFFFFu; for (uint16_t i = 0; i < length; i++) { 800c3fc: b3e9 cbz r1, 800c47a 800c3fe: 4684 mov ip, r0 ISR_FAST static uint16_t crc16_ibm(const uint8_t* data, uint16_t length) { 800c400: b500 push {lr} 800c402: 468e mov lr, r1 uint16_t crc = 0xFFFFu; 800c404: f64f 70ff movw r0, #65535 @ 0xffff crc ^= data[i]; for (uint8_t j = 0; j < 8; j++) { if (crc & 1u) { 800c408: 491d ldr r1, [pc, #116] @ (800c480 ) 800c40a: 44e6 add lr, ip crc ^= data[i]; 800c40c: f81c 2b01 ldrb.w r2, [ip], #1 800c410: 4042 eors r2, r0 if (crc & 1u) { 800c412: f342 0300 sbfx r3, r2, #0, #1 800c416: 400b ands r3, r1 800c418: ea83 0352 eor.w r3, r3, r2, lsr #1 800c41c: f343 0200 sbfx r2, r3, #0, #1 800c420: 400a ands r2, r1 crc = (crc >> 1) ^ 0xA001u; } else { crc >>= 1; 800c422: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c426: 405a eors r2, r3 800c428: f342 0300 sbfx r3, r2, #0, #1 800c42c: 400b ands r3, r1 crc >>= 1; 800c42e: f3c2 024e ubfx r2, r2, #1, #15 if (crc & 1u) { 800c432: 4053 eors r3, r2 800c434: f343 0200 sbfx r2, r3, #0, #1 800c438: 400a ands r2, r1 crc >>= 1; 800c43a: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c43e: 405a eors r2, r3 800c440: f342 0300 sbfx r3, r2, #0, #1 800c444: 400b ands r3, r1 crc >>= 1; 800c446: f3c2 024e ubfx r2, r2, #1, #15 if (crc & 1u) { 800c44a: 4053 eors r3, r2 800c44c: f343 0200 sbfx r2, r3, #0, #1 800c450: 400a ands r2, r1 crc >>= 1; 800c452: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c456: 405a eors r2, r3 800c458: f342 0300 sbfx r3, r2, #0, #1 800c45c: 400b ands r3, r1 crc >>= 1; 800c45e: f3c2 024e ubfx r2, r2, #1, #15 if (crc & 1u) { 800c462: 4053 eors r3, r2 800c464: f343 0000 sbfx r0, r3, #0, #1 800c468: 4008 ands r0, r1 crc >>= 1; 800c46a: f3c3 034e ubfx r3, r3, #1, #15 if (crc & 1u) { 800c46e: 4058 eors r0, r3 for (uint16_t i = 0; i < length; i++) { 800c470: 45e6 cmp lr, ip if (crc & 1u) { 800c472: b280 uxth r0, r0 for (uint16_t i = 0; i < length; i++) { 800c474: d1ca bne.n 800c40c } } } return crc; } 800c476: f85d fb04 ldr.w pc, [sp], #4 uint16_t crc = 0xFFFFu; 800c47a: f64f 70ff movw r0, #65535 @ 0xffff } 800c47e: 4770 bx lr 800c480: ffffa001 .word 0xffffa001 0800c484 : static uint16_t CCS_BuildPacket(uint8_t cmd, const void* payload, uint16_t payload_len, uint8_t* out, uint16_t out_max) { 800c484: b580 push {r7, lr} 800c486: b086 sub sp, #24 800c488: af00 add r7, sp, #0 800c48a: 60b9 str r1, [r7, #8] 800c48c: 607b str r3, [r7, #4] 800c48e: 4603 mov r3, r0 800c490: 73fb strb r3, [r7, #15] 800c492: 4613 mov r3, r2 800c494: 81bb strh r3, [r7, #12] uint16_t total_len = (uint16_t)(1u + payload_len + 2u); 800c496: 89bb ldrh r3, [r7, #12] 800c498: 3303 adds r3, #3 800c49a: 82fb strh r3, [r7, #22] if (total_len > out_max) return 0; 800c49c: 8afa ldrh r2, [r7, #22] 800c49e: 8c3b ldrh r3, [r7, #32] 800c4a0: 429a cmp r2, r3 800c4a2: d901 bls.n 800c4a8 800c4a4: 2300 movs r3, #0 800c4a6: e029 b.n 800c4fc out[0] = cmd; 800c4a8: 687b ldr r3, [r7, #4] 800c4aa: 7bfa ldrb r2, [r7, #15] 800c4ac: 701a strb r2, [r3, #0] if (payload_len && payload != NULL) { 800c4ae: 89bb ldrh r3, [r7, #12] 800c4b0: 2b00 cmp r3, #0 800c4b2: d009 beq.n 800c4c8 800c4b4: 68bb ldr r3, [r7, #8] 800c4b6: 2b00 cmp r3, #0 800c4b8: d006 beq.n 800c4c8 memcpy(&out[1], payload, payload_len); 800c4ba: 687b ldr r3, [r7, #4] 800c4bc: 3301 adds r3, #1 800c4be: 89ba ldrh r2, [r7, #12] 800c4c0: 68b9 ldr r1, [r7, #8] 800c4c2: 4618 mov r0, r3 800c4c4: f008 fc66 bl 8014d94 } uint16_t crc = crc16_ibm(out, (uint16_t)(1u + payload_len)); 800c4c8: 89bb ldrh r3, [r7, #12] 800c4ca: 3301 adds r3, #1 800c4cc: b29b uxth r3, r3 800c4ce: 4619 mov r1, r3 800c4d0: 6878 ldr r0, [r7, #4] 800c4d2: f7ff ff93 bl 800c3fc 800c4d6: 4603 mov r3, r0 800c4d8: 82bb strh r3, [r7, #20] out[1u + payload_len] = (uint8_t)(crc & 0xFFu); 800c4da: 89bb ldrh r3, [r7, #12] 800c4dc: 3301 adds r3, #1 800c4de: 687a ldr r2, [r7, #4] 800c4e0: 4413 add r3, r2 800c4e2: 8aba ldrh r2, [r7, #20] 800c4e4: b2d2 uxtb r2, r2 800c4e6: 701a strb r2, [r3, #0] out[1u + payload_len + 1u] = (uint8_t)((crc >> 8) & 0xFFu); 800c4e8: 8abb ldrh r3, [r7, #20] 800c4ea: 0a1b lsrs r3, r3, #8 800c4ec: b299 uxth r1, r3 800c4ee: 89bb ldrh r3, [r7, #12] 800c4f0: 3302 adds r3, #2 800c4f2: 687a ldr r2, [r7, #4] 800c4f4: 4413 add r3, r2 800c4f6: b2ca uxtb r2, r1 800c4f8: 701a strb r2, [r3, #0] return total_len; 800c4fa: 8afb ldrh r3, [r7, #22] } 800c4fc: 4618 mov r0, r3 800c4fe: 3718 adds r7, #24 800c500: 46bd mov sp, r7 800c502: bd80 pop {r7, pc} 0800c504 : static void CCS_SendPacket(uint8_t cmd, const void* payload, uint16_t payload_len) { 800c504: b580 push {r7, lr} 800c506: b086 sub sp, #24 800c508: af02 add r7, sp, #8 800c50a: 4603 mov r3, r0 800c50c: 6039 str r1, [r7, #0] 800c50e: 71fb strb r3, [r7, #7] 800c510: 4613 mov r3, r2 800c512: 80bb strh r3, [r7, #4] uint16_t len = CCS_BuildPacket(cmd, payload, payload_len, tx_buffer, sizeof(tx_buffer)); 800c514: 88ba ldrh r2, [r7, #4] 800c516: 79f8 ldrb r0, [r7, #7] 800c518: f44f 7380 mov.w r3, #256 @ 0x100 800c51c: 9300 str r3, [sp, #0] 800c51e: 4b19 ldr r3, [pc, #100] @ (800c584 ) 800c520: 6839 ldr r1, [r7, #0] 800c522: f7ff ffaf bl 800c484 800c526: 4603 mov r3, r0 800c528: 81fb strh r3, [r7, #14] if (len > 0) { 800c52a: 89fb ldrh r3, [r7, #14] 800c52c: 2b00 cmp r3, #0 800c52e: d01f beq.n 800c570 if (uart3_tx_busy) { 800c530: 4b15 ldr r3, [pc, #84] @ (800c588 ) 800c532: 781b ldrb r3, [r3, #0] 800c534: 2b00 cmp r3, #0 800c536: d009 beq.n 800c54c memcpy(tx_pending_buffer, tx_buffer, len); 800c538: 89fb ldrh r3, [r7, #14] 800c53a: 461a mov r2, r3 800c53c: 4911 ldr r1, [pc, #68] @ (800c584 ) 800c53e: 4813 ldr r0, [pc, #76] @ (800c58c ) 800c540: f008 fc28 bl 8014d94 tx_pending_len = len; 800c544: 4a12 ldr r2, [pc, #72] @ (800c590 ) 800c546: 89fb ldrh r3, [r7, #14] 800c548: 8013 strh r3, [r2, #0] 800c54a: e011 b.n 800c570 } else { uart3_tx_busy = 1; 800c54c: 4b0e ldr r3, [pc, #56] @ (800c588 ) 800c54e: 2201 movs r2, #1 800c550: 701a strb r2, [r3, #0] if (HAL_UART_Transmit_DMA(&huart3, tx_buffer, len) != HAL_OK) { 800c552: 89fb ldrh r3, [r7, #14] 800c554: 461a mov r2, r3 800c556: 490b ldr r1, [pc, #44] @ (800c584 ) 800c558: 480e ldr r0, [pc, #56] @ (800c594 ) 800c55a: f006 fd15 bl 8012f88 800c55e: 4603 mov r3, r0 800c560: 2b00 cmp r3, #0 800c562: d005 beq.n 800c570 uart3_tx_busy = 0; 800c564: 4b08 ldr r3, [pc, #32] @ (800c588 ) 800c566: 2200 movs r2, #0 800c568: 701a strb r2, [r3, #0] CCS_LogUart3Error("UART3 TX DMA start failed"); 800c56a: 480b ldr r0, [pc, #44] @ (800c598 ) 800c56c: f000 fa5a bl 800ca24 } } } last_cmd_sent = HAL_GetTick(); 800c570: f001 ff0e bl 800e390 800c574: 4603 mov r3, r0 800c576: 4a09 ldr r2, [pc, #36] @ (800c59c ) 800c578: 6013 str r3, [r2, #0] } 800c57a: bf00 nop 800c57c: 3710 adds r7, #16 800c57e: 46bd mov sp, r7 800c580: bd80 pop {r7, pc} 800c582: bf00 nop 800c584: 20000aac .word 0x20000aac 800c588: 20000cae .word 0x20000cae 800c58c: 20000bac .word 0x20000bac 800c590: 20000cac .word 0x20000cac 800c594: 20001330 .word 0x20001330 800c598: 08017528 .word 0x08017528 800c59c: 200009a0 .word 0x200009a0 0800c5a0 : static void CCS_SendResetReason(void) { 800c5a0: b580 push {r7, lr} 800c5a2: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_RESET, NULL, 0); 800c5a4: 2200 movs r2, #0 800c5a6: 2100 movs r1, #0 800c5a8: 2052 movs r0, #82 @ 0x52 800c5aa: f7ff ffab bl 800c504 } 800c5ae: bf00 nop 800c5b0: bd80 pop {r7, pc} 800c5b2: bf00 nop 0800c5b4 : void CCS_SendEmergencyStop(void) { 800c5b4: b580 push {r7, lr} 800c5b6: af00 add r7, sp, #0 CCS_SendPacket(CMD_M2E_ESTOP, NULL, 0); 800c5b8: 2200 movs r2, #0 800c5ba: 2100 movs r1, #0 800c5bc: 2053 movs r0, #83 @ 0x53 800c5be: f7ff ffa1 bl 800c504 } 800c5c2: bf00 nop 800c5c4: bd80 pop {r7, pc} 800c5c6: bf00 nop 0800c5c8 : void CCS_SendStart(void) { CCS_SendPacket(CMD_M2E_START, NULL, 0); } static void CCS_CalculateEnergy(void) { 800c5c8: b580 push {r7, lr} 800c5ca: b082 sub sp, #8 800c5cc: af00 add r7, sp, #0 static uint32_t lastTick = 0; uint32_t currentTick = HAL_GetTick(); 800c5ce: f001 fedf bl 800e390 800c5d2: 6078 str r0, [r7, #4] uint32_t elapsedTimeMs = currentTick - lastTick; 800c5d4: 4b1e ldr r3, [pc, #120] @ (800c650 ) 800c5d6: 681b ldr r3, [r3, #0] 800c5d8: 687a ldr r2, [r7, #4] 800c5da: 1ad3 subs r3, r2, r3 800c5dc: 603b str r3, [r7, #0] lastTick = currentTick; 800c5de: 4a1c ldr r2, [pc, #112] @ (800c650 ) 800c5e0: 687b ldr r3, [r7, #4] 800c5e2: 6013 str r3, [r2, #0] CCS_Power = CONN.MeasuredVoltage * CONN.MeasuredCurrent / 10; 800c5e4: 4b1b ldr r3, [pc, #108] @ (800c654 ) 800c5e6: f8b3 3013 ldrh.w r3, [r3, #19] 800c5ea: b29b uxth r3, r3 800c5ec: 461a mov r2, r3 800c5ee: 4b19 ldr r3, [pc, #100] @ (800c654 ) 800c5f0: f8b3 3015 ldrh.w r3, [r3, #21] 800c5f4: b29b uxth r3, r3 800c5f6: fb02 f303 mul.w r3, r2, r3 800c5fa: 4a17 ldr r2, [pc, #92] @ (800c658 ) 800c5fc: fb82 1203 smull r1, r2, r2, r3 800c600: 1092 asrs r2, r2, #2 800c602: 17db asrs r3, r3, #31 800c604: 1ad3 subs r3, r2, r3 800c606: 461a mov r2, r3 800c608: 4b14 ldr r3, [pc, #80] @ (800c65c ) 800c60a: 601a str r2, [r3, #0] CCS_EnergyWs += (CCS_Power * elapsedTimeMs) / 1000; 800c60c: 4b13 ldr r3, [pc, #76] @ (800c65c ) 800c60e: 681b ldr r3, [r3, #0] 800c610: 683a ldr r2, [r7, #0] 800c612: fb02 f303 mul.w r3, r2, r3 800c616: 4a12 ldr r2, [pc, #72] @ (800c660 ) 800c618: fba2 2303 umull r2, r3, r2, r3 800c61c: 099a lsrs r2, r3, #6 800c61e: 4b11 ldr r3, [pc, #68] @ (800c664 ) 800c620: 681b ldr r3, [r3, #0] 800c622: 4413 add r3, r2 800c624: 4a0f ldr r2, [pc, #60] @ (800c664 ) 800c626: 6013 str r3, [r2, #0] if(CCS_EvseState == Unplugged) { 800c628: 4b0f ldr r3, [pc, #60] @ (800c668 ) 800c62a: 781b ldrb r3, [r3, #0] 800c62c: 2b01 cmp r3, #1 800c62e: d102 bne.n 800c636 CCS_EnergyWs = 0; 800c630: 4b0c ldr r3, [pc, #48] @ (800c664 ) 800c632: 2200 movs r2, #0 800c634: 601a str r2, [r3, #0] } CCS_Energy = CCS_EnergyWs / 3600; 800c636: 4b0b ldr r3, [pc, #44] @ (800c664 ) 800c638: 681b ldr r3, [r3, #0] 800c63a: 4a0c ldr r2, [pc, #48] @ (800c66c ) 800c63c: fba2 2303 umull r2, r3, r2, r3 800c640: 0adb lsrs r3, r3, #11 800c642: 4a0b ldr r2, [pc, #44] @ (800c670 ) 800c644: 6013 str r3, [r2, #0] } 800c646: bf00 nop 800c648: 3708 adds r7, #8 800c64a: 46bd mov sp, r7 800c64c: bd80 pop {r7, pc} 800c64e: bf00 nop 800c650: 20000d28 .word 0x20000d28 800c654: 200003b0 .word 0x200003b0 800c658: 66666667 .word 0x66666667 800c65c: 20000994 .word 0x20000994 800c660: 10624dd3 .word 0x10624dd3 800c664: 20000998 .word 0x20000998 800c668: 20000d10 .word 0x20000d10 800c66c: 91a2b3c5 .word 0x91a2b3c5 800c670: 2000099c .word 0x2000099c 0800c674 : static void send_state(void) { 800c674: b580 push {r7, lr} 800c676: af00 add r7, sp, #0 CCS_CalculateEnergy(); 800c678: f7ff ffa6 bl 800c5c8 CCS_State.DutyCycle = CP_GetDuty(); 800c67c: f7fd fd5a bl 800a134 800c680: 4603 mov r3, r0 800c682: 461a mov r2, r3 800c684: 4b2e ldr r3, [pc, #184] @ (800c740 ) 800c686: 701a strb r2, [r3, #0] CCS_State.OutputEnabled = PSU0.CONT_enabled; 800c688: 4b2e ldr r3, [pc, #184] @ (800c744 ) 800c68a: 7ada ldrb r2, [r3, #11] 800c68c: 4b2c ldr r3, [pc, #176] @ (800c740 ) 800c68e: 705a strb r2, [r3, #1] CCS_State.MeasuredVoltage = (uint16_t)CONN.MeasuredVoltage; 800c690: 4b2d ldr r3, [pc, #180] @ (800c748 ) 800c692: f8b3 3013 ldrh.w r3, [r3, #19] 800c696: b29a uxth r2, r3 800c698: 4b29 ldr r3, [pc, #164] @ (800c740 ) 800c69a: 805a strh r2, [r3, #2] if (fake_500_voltage_mode) { 800c69c: 4b2b ldr r3, [pc, #172] @ (800c74c ) 800c69e: 781b ldrb r3, [r3, #0] 800c6a0: 2b00 cmp r3, #0 800c6a2: d003 beq.n 800c6ac CCS_State.MeasuredVoltage = FAKE_EVREQ_VOLTAGE_V; 800c6a4: 4b26 ldr r3, [pc, #152] @ (800c740 ) 800c6a6: f44f 72fa mov.w r2, #500 @ 0x1f4 800c6aa: 805a strh r2, [r3, #2] } CCS_State.MeasuredCurrent = (uint16_t)CONN.MeasuredCurrent; 800c6ac: 4b26 ldr r3, [pc, #152] @ (800c748 ) 800c6ae: f8b3 3015 ldrh.w r3, [r3, #21] 800c6b2: b29a uxth r2, r3 800c6b4: 4b22 ldr r3, [pc, #136] @ (800c740 ) 800c6b6: 809a strh r2, [r3, #4] CCS_State.Power = CCS_Power; 800c6b8: 4b25 ldr r3, [pc, #148] @ (800c750 ) 800c6ba: 681b ldr r3, [r3, #0] 800c6bc: 4a20 ldr r2, [pc, #128] @ (800c740 ) 800c6be: f8c2 3006 str.w r3, [r2, #6] CCS_State.Energy = CCS_Energy; 800c6c2: 4b24 ldr r3, [pc, #144] @ (800c754 ) 800c6c4: 681b ldr r3, [r3, #0] 800c6c6: 4a1e ldr r2, [pc, #120] @ (800c740 ) 800c6c8: f8c2 300a str.w r3, [r2, #10] if(CCS_ConnectorState == CCS_CONNECTED){ 800c6cc: 4b22 ldr r3, [pc, #136] @ (800c758 ) 800c6ce: 781b ldrb r3, [r3, #0] 800c6d0: 2b04 cmp r3, #4 800c6d2: d104 bne.n 800c6de CCS_State.CpState = cp_state_buffer; 800c6d4: 4b21 ldr r3, [pc, #132] @ (800c75c ) 800c6d6: 781a ldrb r2, [r3, #0] 800c6d8: 4b19 ldr r3, [pc, #100] @ (800c740 ) 800c6da: 74da strb r2, [r3, #19] 800c6dc: e002 b.n 800c6e4 } else { CCS_State.CpState = EV_STATE_A_IDLE; 800c6de: 4b18 ldr r3, [pc, #96] @ (800c740 ) 800c6e0: 2200 movs r2, #0 800c6e2: 74da strb r2, [r3, #19] } CCS_State.MaxVoltage = CCS_MaxLoad.maxVoltage; 800c6e4: 4b1e ldr r3, [pc, #120] @ (800c760 ) 800c6e6: 881a ldrh r2, [r3, #0] 800c6e8: 4b15 ldr r3, [pc, #84] @ (800c740 ) 800c6ea: 829a strh r2, [r3, #20] CCS_State.MinVoltage = CCS_MaxLoad.minVoltage; 800c6ec: 4b1c ldr r3, [pc, #112] @ (800c760 ) 800c6ee: 885a ldrh r2, [r3, #2] 800c6f0: 4b13 ldr r3, [pc, #76] @ (800c740 ) 800c6f2: 82da strh r2, [r3, #22] CCS_State.MaxCurrent = CCS_MaxLoad.maxCurrent; 800c6f4: 4b1a ldr r3, [pc, #104] @ (800c760 ) 800c6f6: 889a ldrh r2, [r3, #4] 800c6f8: 4b11 ldr r3, [pc, #68] @ (800c740 ) 800c6fa: 831a strh r2, [r3, #24] CCS_State.MinCurrent = CCS_MaxLoad.minCurrent; 800c6fc: 4b18 ldr r3, [pc, #96] @ (800c760 ) 800c6fe: 88da ldrh r2, [r3, #6] 800c700: 4b0f ldr r3, [pc, #60] @ (800c740 ) 800c702: 835a strh r2, [r3, #26] CCS_State.MaxPower = CCS_MaxLoad.maxPower; 800c704: 4b16 ldr r3, [pc, #88] @ (800c760 ) 800c706: 689b ldr r3, [r3, #8] 800c708: 4a0d ldr r2, [pc, #52] @ (800c740 ) 800c70a: 61d3 str r3, [r2, #28] CCS_State.IsolationValid = isolation_enable; 800c70c: 4b15 ldr r3, [pc, #84] @ (800c764 ) 800c70e: 781a ldrb r2, [r3, #0] 800c710: 4b0b ldr r3, [pc, #44] @ (800c740 ) 800c712: 749a strb r2, [r3, #18] CCS_State.IsolationResistance = 900000; 800c714: 4a0a ldr r2, [pc, #40] @ (800c740 ) 800c716: 2300 movs r3, #0 800c718: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800c71c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800c720: f443 433b orr.w r3, r3, #47872 @ 0xbb00 800c724: f043 03a0 orr.w r3, r3, #160 @ 0xa0 800c728: 81d3 strh r3, [r2, #14] 800c72a: 2300 movs r3, #0 800c72c: f043 030d orr.w r3, r3, #13 800c730: 8213 strh r3, [r2, #16] CCS_SendPacket(CMD_M2E_STATE, &CCS_State, sizeof(CCS_State)); 800c732: 2220 movs r2, #32 800c734: 4902 ldr r1, [pc, #8] @ (800c740 ) 800c736: 2050 movs r0, #80 @ 0x50 800c738: f7ff fee4 bl 800c504 } 800c73c: bf00 nop 800c73e: bd80 pop {r7, pc} 800c740: 20000cc4 .word 0x20000cc4 800c744: 20000904 .word 0x20000904 800c748: 200003b0 .word 0x200003b0 800c74c: 20000cb8 .word 0x20000cb8 800c750: 20000994 .word 0x20000994 800c754: 2000099c .word 0x2000099c 800c758: 20000d11 .word 0x20000d11 800c75c: 20000005 .word 0x20000005 800c760: 20000988 .word 0x20000988 800c764: 20000cb2 .word 0x20000cb2 0800c768 : ISR_FAST static uint16_t expected_payload_len(uint8_t cmd) { switch (cmd) { 800c768: 3840 subs r0, #64 @ 0x40 800c76a: b2c0 uxtb r0, r0 800c76c: 2809 cmp r0, #9 800c76e: bf9a itte ls 800c770: 4b02 ldrls r3, [pc, #8] @ (800c77c ) 800c772: f833 0010 ldrhls.w r0, [r3, r0, lsl #1] ISR_FAST static uint16_t expected_payload_len(uint8_t cmd) { 800c776: f64f 70ff movwhi r0, #65535 @ 0xffff case CMD_E2M_EV_INFO: return sizeof(CCS_EvInfo_t); case CMD_E2M_EVSE_STATE: return sizeof(CONN_State_t); case CMD_E2M_KEEP_ALIVE: return 0; default: return 0xFFFFu; } } 800c77a: 4770 bx lr 800c77c: 08017958 .word 0x08017958 0800c780 : ISR_FAST static void apply_command(uint8_t cmd, const uint8_t* payload, uint16_t payload_len) { 800c780: b5f8 push {r3, r4, r5, r6, r7, lr} 800c782: 4604 mov r4, r0 800c784: 460d mov r5, r1 (void)payload_len; last_host_seen = HAL_GetTick(); 800c786: f001 fe03 bl 800e390 everest_timed_out = 0; 800c78a: 2300 movs r3, #0 800c78c: 4a42 ldr r2, [pc, #264] @ (800c898 ) last_host_seen = HAL_GetTick(); 800c78e: 4e43 ldr r6, [pc, #268] @ (800c89c ) everest_timed_out = 0; 800c790: 7013 strb r3, [r2, #0] everest_timeout_warn_latched = 0; 800c792: 4a43 ldr r2, [pc, #268] @ (800c8a0 ) last_host_seen = HAL_GetTick(); 800c794: 6030 str r0, [r6, #0] everest_timeout_warn_latched = 0; 800c796: 7013 strb r3, [r2, #0] everest_timeout_stop_latched = 0; 800c798: 4a42 ldr r2, [pc, #264] @ (800c8a4 ) 800c79a: 7013 strb r3, [r2, #0] switch (cmd) { 800c79c: f1a4 0340 sub.w r3, r4, #64 @ 0x40 800c7a0: 2b09 cmp r3, #9 800c7a2: d871 bhi.n 800c888 800c7a4: e8df f003 tbb [pc, r3] 800c7a8: 4e5b1409 .word 0x4e5b1409 800c7ac: 2e2a1b55 .word 0x2e2a1b55 800c7b0: 054a .short 0x054a (void)payload; CP_SetDuty(pwm_duty_percent); break; } case CMD_E2M_KEEP_ALIVE: { last_host_seen = HAL_GetTick(); 800c7b2: f001 fded bl 800e390 800c7b6: 6030 str r0, [r6, #0] log_printf(LOG_WARN, "UART3 RX warn: cmd 0x%02x CRC/len OK but no switch case (expected_payload vs apply_command)\n", cmd); break; } } 800c7b8: bdf8 pop {r3, r4, r5, r6, r7, pc} if (duty > 100) duty = 100; 800c7ba: 7828 ldrb r0, [r5, #0] if (CONN.connControl != CMD_FORCE_UNLOCK) { 800c7bc: 4b3a ldr r3, [pc, #232] @ (800c8a8 ) if (duty > 100) duty = 100; 800c7be: 2864 cmp r0, #100 @ 0x64 800c7c0: bf28 it cs 800c7c2: 2064 movcs r0, #100 @ 0x64 if (CONN.connControl != CMD_FORCE_UNLOCK) { 800c7c4: 781b ldrb r3, [r3, #0] pwm_duty_percent = duty; 800c7c6: 4a39 ldr r2, [pc, #228] @ (800c8ac ) if (CONN.connControl != CMD_FORCE_UNLOCK) { 800c7c8: 2b03 cmp r3, #3 pwm_duty_percent = duty; 800c7ca: 7010 strb r0, [r2, #0] if (CONN.connControl != CMD_FORCE_UNLOCK) { 800c7cc: d143 bne.n 800c856 } 800c7ce: bdf8 pop {r3, r4, r5, r6, r7, pc} ev_enable_output = (p->enable_output != 0); 800c7d0: 782b ldrb r3, [r5, #0] 800c7d2: 4a37 ldr r2, [pc, #220] @ (800c8b0 ) 800c7d4: 3b00 subs r3, #0 800c7d6: bf18 it ne 800c7d8: 2301 movne r3, #1 800c7da: 7013 strb r3, [r2, #0] } 800c7dc: bdf8 pop {r3, r4, r5, r6, r7, pc} if (p->voltage_V == FAKE_EVREQ_VOLTAGE_V) { 800c7de: 882b ldrh r3, [r5, #0] 800c7e0: b29a uxth r2, r3 800c7e2: f5b2 7ffa cmp.w r2, #500 @ 0x1f4 800c7e6: d043 beq.n 800c870 fake_500_voltage_mode = 0u; 800c7e8: 2000 movs r0, #0 CONN.RequestedVoltage = p->voltage_V; 800c7ea: 4a2f ldr r2, [pc, #188] @ (800c8a8 ) fake_500_voltage_mode = 0u; 800c7ec: 4931 ldr r1, [pc, #196] @ (800c8b4 ) CONN.RequestedVoltage = p->voltage_V; 800c7ee: f8a2 300f strh.w r3, [r2, #15] fake_500_voltage_mode = 0u; 800c7f2: 7008 strb r0, [r1, #0] CONN.WantedCurrent = p->current_0p1A; 800c7f4: 886b ldrh r3, [r5, #2] 800c7f6: f8a2 301b strh.w r3, [r2, #27] } 800c7fa: bdf8 pop {r3, r4, r5, r6, r7, pc} isolation_enable = p->command; 800c7fc: 782a ldrb r2, [r5, #0] 800c7fe: 4b2e ldr r3, [pc, #184] @ (800c8b8 ) 800c800: 701a strb r2, [r3, #0] } 800c802: bdf8 pop {r3, r4, r5, r6, r7, pc} memcpy(&CCS_EvInfo, payload, sizeof(CCS_EvInfo_t)); 800c804: 4f2d ldr r7, [pc, #180] @ (800c8bc ) 800c806: 462c mov r4, r5 800c808: 463e mov r6, r7 800c80a: f105 0c20 add.w ip, r5, #32 800c80e: 4635 mov r5, r6 800c810: 6820 ldr r0, [r4, #0] 800c812: 6861 ldr r1, [r4, #4] 800c814: 68a2 ldr r2, [r4, #8] 800c816: 68e3 ldr r3, [r4, #12] 800c818: 3410 adds r4, #16 800c81a: 4564 cmp r4, ip 800c81c: c50f stmia r5!, {r0, r1, r2, r3} 800c81e: f106 0610 add.w r6, r6, #16 800c822: d1f4 bne.n 800c80e 800c824: 6861 ldr r1, [r4, #4] 800c826: 68a2 ldr r2, [r4, #8] 800c828: 6820 ldr r0, [r4, #0] 800c82a: c607 stmia r6!, {r0, r1, r2} CONN.SOC = (uint8_t)(CCS_EvInfo.soc / 10); 800c82c: 4a24 ldr r2, [pc, #144] @ (800c8c0 ) 800c82e: 887b ldrh r3, [r7, #2] 800c830: 491d ldr r1, [pc, #116] @ (800c8a8 ) 800c832: fba2 2303 umull r2, r3, r2, r3 800c836: 08db lsrs r3, r3, #3 800c838: 708b strb r3, [r1, #2] } 800c83a: bdf8 pop {r3, r4, r5, r6, r7, pc} CCS_EvseState = (CONN_State_t)payload[0]; 800c83c: 782a ldrb r2, [r5, #0] 800c83e: 4b21 ldr r3, [pc, #132] @ (800c8c4 ) 800c840: 701a strb r2, [r3, #0] } 800c842: bdf8 pop {r3, r4, r5, r6, r7, pc} enabled = (p->enable != 0); 800c844: 782b ldrb r3, [r5, #0] 800c846: 4a20 ldr r2, [pc, #128] @ (800c8c8 ) 800c848: 3b00 subs r3, #0 800c84a: bf18 it ne 800c84c: 2301 movne r3, #1 800c84e: 7013 strb r3, [r2, #0] } 800c850: bdf8 pop {r3, r4, r5, r6, r7, pc} CP_SetDuty(pwm_duty_percent); 800c852: 4b16 ldr r3, [pc, #88] @ (800c8ac ) 800c854: 7818 ldrb r0, [r3, #0] } 800c856: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} CP_SetDuty(pwm_duty_percent); 800c85a: f7fd bc43 b.w 800a0e4 if (p->reset) { 800c85e: 782b ldrb r3, [r5, #0] 800c860: 2b00 cmp r3, #0 800c862: d0a9 beq.n 800c7b8 } 800c864: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} log_printf(LOG_WARN, "Everest reset command\n"); 800c868: 2005 movs r0, #5 800c86a: 4918 ldr r1, [pc, #96] @ (800c8cc ) 800c86c: f7fd be7c b.w 800a568 fake_500_voltage_mode = 1u; 800c870: 2201 movs r2, #1 CONN.RequestedVoltage = FAKE_PSU_VOLTAGE_V; 800c872: 2100 movs r1, #0 800c874: 242c movs r4, #44 @ 0x2c CONN.WantedCurrent = FAKE_PSU_CURRENT_0P1A; 800c876: 200a movs r0, #10 fake_500_voltage_mode = 1u; 800c878: 4d0e ldr r5, [pc, #56] @ (800c8b4 ) CONN.RequestedVoltage = FAKE_PSU_VOLTAGE_V; 800c87a: 4b0b ldr r3, [pc, #44] @ (800c8a8 ) fake_500_voltage_mode = 1u; 800c87c: 702a strb r2, [r5, #0] CONN.RequestedVoltage = FAKE_PSU_VOLTAGE_V; 800c87e: 741a strb r2, [r3, #16] 800c880: 73dc strb r4, [r3, #15] CONN.WantedCurrent = FAKE_PSU_CURRENT_0P1A; 800c882: 76d8 strb r0, [r3, #27] 800c884: 7719 strb r1, [r3, #28] } 800c886: bdf8 pop {r3, r4, r5, r6, r7, pc} log_printf(LOG_WARN, 800c888: 4622 mov r2, r4 } 800c88a: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} log_printf(LOG_WARN, 800c88e: 2005 movs r0, #5 800c890: 490f ldr r1, [pc, #60] @ (800c8d0 ) 800c892: f7fd be69 b.w 800a568 800c896: bf00 nop 800c898: 20000cb9 .word 0x20000cb9 800c89c: 20000cb4 .word 0x20000cb4 800c8a0: 20000cba .word 0x20000cba 800c8a4: 20000cbb .word 0x20000cbb 800c8a8: 200003b0 .word 0x200003b0 800c8ac: 2000006a .word 0x2000006a 800c8b0: 200009a9 .word 0x200009a9 800c8b4: 20000cb8 .word 0x20000cb8 800c8b8: 20000cb2 .word 0x20000cb2 800c8bc: 20000ce4 .word 0x20000ce4 800c8c0: cccccccd .word 0xcccccccd 800c8c4: 20000d10 .word 0x20000d10 800c8c8: 20000cb1 .word 0x20000cb1 800c8cc: 08017544 .word 0x08017544 800c8d0: 0801755c .word 0x0801755c 0800c8d4 : ISR_FAST static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len) { 800c8d4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} if (packet_len < 3u) { 800c8d8: 2902 cmp r1, #2 ISR_FAST static uint8_t process_received_packet(const uint8_t* packet, uint16_t packet_len) { 800c8da: 460c mov r4, r1 800c8dc: 4605 mov r5, r0 800c8de: b084 sub sp, #16 if (packet_len < 3u) { 800c8e0: d930 bls.n 800c944 uint8_t cmd = packet[0]; uint16_t payload_len = (uint16_t)(packet_len - 3u); uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | (uint16_t)packet[packet_len - 1u] << 8; 800c8e2: 1843 adds r3, r0, r1 uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800c8e4: f813 2c01 ldrb.w r2, [r3, #-1] 800c8e8: f813 7c02 ldrb.w r7, [r3, #-2] uint16_t payload_len = (uint16_t)(packet_len - 3u); 800c8ec: 1ece subs r6, r1, #3 uint16_t calculated_crc = crc16_ibm(packet, (uint16_t)(1u + payload_len)); 800c8ee: 3902 subs r1, #2 800c8f0: b289 uxth r1, r1 uint16_t received_crc = (uint16_t)packet[packet_len - 2u] | 800c8f2: ea47 2702 orr.w r7, r7, r2, lsl #8 uint8_t cmd = packet[0]; 800c8f6: f890 8000 ldrb.w r8, [r0] uint16_t calculated_crc = crc16_ibm(packet, (uint16_t)(1u + payload_len)); 800c8fa: f7ff fd7f bl 800c3fc if (received_crc != calculated_crc) { 800c8fe: 4287 cmp r7, r0 uint16_t payload_len = (uint16_t)(packet_len - 3u); 800c900: b2b6 uxth r6, r6 if (received_crc != calculated_crc) { 800c902: d112 bne.n 800c92a cmd, (unsigned)packet_len, (unsigned)payload_len, (unsigned)received_crc, (unsigned)calculated_crc); return 0; } uint16_t expected_len = expected_payload_len(cmd); 800c904: 4640 mov r0, r8 800c906: f7ff ff2f bl 800c768 if (expected_len == 0xFFFFu) { 800c90a: f64f 72ff movw r2, #65535 @ 0xffff 800c90e: 4290 cmp r0, r2 800c910: d03a beq.n 800c988 log_printf(LOG_WARN, "UART3 RX drop: unknown_cmd cmd=0x%02x total_len=%u payload_len=%u\n", cmd, (unsigned)packet_len, (unsigned)payload_len); return 0; } if (expected_len != payload_len) { 800c912: 4286 cmp r6, r0 800c914: d12a bne.n 800c96c cmd, (unsigned)expected_len, (unsigned)payload_len, (unsigned)packet_len); return 0; } if (payload_len > 0) { apply_command(cmd, &packet[1], payload_len); 800c916: 4632 mov r2, r6 if (payload_len > 0) { 800c918: b9fe cbnz r6, 800c95a } else { apply_command(cmd, NULL, 0); 800c91a: 4631 mov r1, r6 800c91c: 4640 mov r0, r8 800c91e: f7ff ff2f bl 800c780 } return 1; 800c922: 2001 movs r0, #1 } 800c924: b004 add sp, #16 800c926: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} log_printf(LOG_ERR, 800c92a: 9002 str r0, [sp, #8] 800c92c: 4623 mov r3, r4 800c92e: 4642 mov r2, r8 800c930: 2004 movs r0, #4 800c932: e9cd 6700 strd r6, r7, [sp] 800c936: 4918 ldr r1, [pc, #96] @ (800c998 ) 800c938: f7fd fe16 bl 800a568 return 0; 800c93c: 2000 movs r0, #0 } 800c93e: b004 add sp, #16 800c940: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} if (packet_len == 0u) { 800c944: b1d9 cbz r1, 800c97e } else if (packet_len == 1u) { 800c946: 2901 cmp r1, #1 log_printf(LOG_WARN, "UART3 RX drop: too_short len=1 b0=0x%02x\n", packet[0]); 800c948: 7802 ldrb r2, [r0, #0] 800c94a: f04f 0005 mov.w r0, #5 } else if (packet_len == 1u) { 800c94e: d009 beq.n 800c964 log_printf(LOG_WARN, "UART3 RX drop: too_short len=2 b0=0x%02x b1=0x%02x\n", 800c950: 786b ldrb r3, [r5, #1] 800c952: 4912 ldr r1, [pc, #72] @ (800c99c ) 800c954: f7fd fe08 bl 800a568 800c958: e7f0 b.n 800c93c apply_command(cmd, &packet[1], payload_len); 800c95a: 4640 mov r0, r8 800c95c: 1c69 adds r1, r5, #1 800c95e: f7ff ff0f bl 800c780 800c962: e7de b.n 800c922 log_printf(LOG_WARN, "UART3 RX drop: too_short len=1 b0=0x%02x\n", packet[0]); 800c964: 490e ldr r1, [pc, #56] @ (800c9a0 ) 800c966: f7fd fdff bl 800a568 800c96a: e7e7 b.n 800c93c log_printf(LOG_ERR, 800c96c: 4603 mov r3, r0 800c96e: 4642 mov r2, r8 800c970: e9cd 6400 strd r6, r4, [sp] 800c974: 490b ldr r1, [pc, #44] @ (800c9a4 ) 800c976: 2004 movs r0, #4 800c978: f7fd fdf6 bl 800a568 return 0; 800c97c: e7de b.n 800c93c log_printf(LOG_WARN, "UART3 RX drop: too_short len=0 (empty chunk)\n"); 800c97e: 490a ldr r1, [pc, #40] @ (800c9a8 ) 800c980: 2005 movs r0, #5 800c982: f7fd fdf1 bl 800a568 800c986: e7d9 b.n 800c93c log_printf(LOG_WARN, 800c988: 4623 mov r3, r4 800c98a: 4642 mov r2, r8 800c98c: 4907 ldr r1, [pc, #28] @ (800c9ac ) 800c98e: 9600 str r6, [sp, #0] 800c990: 2005 movs r0, #5 800c992: f7fd fde9 bl 800a568 return 0; 800c996: e7d1 b.n 800c93c 800c998: 0801764c .word 0x0801764c 800c99c: 08017618 .word 0x08017618 800c9a0: 080175ec .word 0x080175ec 800c9a4: 080176f4 .word 0x080176f4 800c9a8: 080175bc .word 0x080175bc 800c9ac: 080176b0 .word 0x080176b0 0800c9b0 : static void CCS_UART3_Watchdog(void) { 800c9b0: b580 push {r7, lr} 800c9b2: b082 sub sp, #8 800c9b4: af00 add r7, sp, #0 const int32_t since_last_packet = (int32_t)(HAL_GetTick() - uart3_last_packet_tick); 800c9b6: f001 fceb bl 800e390 800c9ba: 4602 mov r2, r0 800c9bc: 4b14 ldr r3, [pc, #80] @ (800ca10 ) 800c9be: 681b ldr r3, [r3, #0] 800c9c0: 1ad3 subs r3, r2, r3 800c9c2: 607b str r3, [r7, #4] const int32_t since_last_reinit = (int32_t)(HAL_GetTick() - uart3_last_reinit_tick); 800c9c4: f001 fce4 bl 800e390 800c9c8: 4602 mov r2, r0 800c9ca: 4b12 ldr r3, [pc, #72] @ (800ca14 ) 800c9cc: 681b ldr r3, [r3, #0] 800c9ce: 1ad3 subs r3, r2, r3 800c9d0: 603b str r3, [r7, #0] if ((since_last_packet >= (int32_t)UART3_REINIT_TIMEOUT_MS) && 800c9d2: 687b ldr r3, [r7, #4] 800c9d4: f240 52db movw r2, #1499 @ 0x5db 800c9d8: 4293 cmp r3, r2 800c9da: dd15 ble.n 800ca08 800c9dc: 683b ldr r3, [r7, #0] 800c9de: f240 52db movw r2, #1499 @ 0x5db 800c9e2: 4293 cmp r3, r2 800c9e4: dd10 ble.n 800ca08 (since_last_reinit >= (int32_t)UART3_REINIT_TIMEOUT_MS) && (huart3.RxState == HAL_UART_STATE_READY)) { 800c9e6: 4b0c ldr r3, [pc, #48] @ (800ca18 ) 800c9e8: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800c9ec: b2db uxtb r3, r3 (since_last_reinit >= (int32_t)UART3_REINIT_TIMEOUT_MS) && 800c9ee: 2b20 cmp r3, #32 800c9f0: d10a bne.n 800ca08 uart3_arm_rx_or_log("Watchdog"); 800c9f2: 480a ldr r0, [pc, #40] @ (800ca1c ) 800c9f4: f7ff f91a bl 800bc2c CCS_LogUart3Error("UART3 watchdog rearm"); 800c9f8: 4809 ldr r0, [pc, #36] @ (800ca20 ) 800c9fa: f000 f813 bl 800ca24 uart3_last_reinit_tick = HAL_GetTick(); 800c9fe: f001 fcc7 bl 800e390 800ca02: 4603 mov r3, r0 800ca04: 4a03 ldr r2, [pc, #12] @ (800ca14 ) 800ca06: 6013 str r3, [r2, #0] } } 800ca08: bf00 nop 800ca0a: 3708 adds r7, #8 800ca0c: 46bd mov sp, r7 800ca0e: bd80 pop {r7, pc} 800ca10: 20000cbc .word 0x20000cbc 800ca14: 20000cc0 .word 0x20000cc0 800ca18: 20001330 .word 0x20001330 800ca1c: 0801774c .word 0x0801774c 800ca20: 08017758 .word 0x08017758 0800ca24 : static void CCS_LogUart3Error(const char *tag) { 800ca24: b580 push {r7, lr} 800ca26: b086 sub sp, #24 800ca28: af04 add r7, sp, #16 800ca2a: 6078 str r0, [r7, #4] log_printf(LOG_ERR, "%s: err=0x%08lx g=%lu rx=%lu tx_busy=%u\n", tag, (unsigned long)HAL_UART_GetError(&huart3), 800ca2c: 480d ldr r0, [pc, #52] @ (800ca64 ) 800ca2e: f006 ff8a bl 8013946 800ca32: 4603 mov r3, r0 (unsigned long)huart3.gState, 800ca34: 4a0b ldr r2, [pc, #44] @ (800ca64 ) 800ca36: f892 2041 ldrb.w r2, [r2, #65] @ 0x41 800ca3a: b2d2 uxtb r2, r2 log_printf(LOG_ERR, "%s: err=0x%08lx g=%lu rx=%lu tx_busy=%u\n", 800ca3c: 4611 mov r1, r2 (unsigned long)huart3.RxState, 800ca3e: 4a09 ldr r2, [pc, #36] @ (800ca64 ) 800ca40: f892 2042 ldrb.w r2, [r2, #66] @ 0x42 800ca44: b2d2 uxtb r2, r2 log_printf(LOG_ERR, "%s: err=0x%08lx g=%lu rx=%lu tx_busy=%u\n", 800ca46: 4610 mov r0, r2 800ca48: 4a07 ldr r2, [pc, #28] @ (800ca68 ) 800ca4a: 7812 ldrb r2, [r2, #0] 800ca4c: 9202 str r2, [sp, #8] 800ca4e: 9001 str r0, [sp, #4] 800ca50: 9100 str r1, [sp, #0] 800ca52: 687a ldr r2, [r7, #4] 800ca54: 4905 ldr r1, [pc, #20] @ (800ca6c ) 800ca56: 2004 movs r0, #4 800ca58: f7fd fd86 bl 800a568 (unsigned)uart3_tx_busy); } 800ca5c: bf00 nop 800ca5e: 3708 adds r7, #8 800ca60: 46bd mov sp, r7 800ca62: bd80 pop {r7, pc} 800ca64: 20001330 .word 0x20001330 800ca68: 20000cae .word 0x20000cae 800ca6c: 08017770 .word 0x08017770 0800ca70 : .fw_version_major = 0, .fw_version_minor = 0, .fw_version_patch = 0, }; void ReadVersion(){ 800ca70: b480 push {r7} 800ca72: af00 add r7, sp, #0 infoPacket.serialNumber = InfoBlock->serialNumber; 800ca74: 4b0e ldr r3, [pc, #56] @ (800cab0 ) 800ca76: 681b ldr r3, [r3, #0] 800ca78: 681b ldr r3, [r3, #0] 800ca7a: b29a uxth r2, r3 800ca7c: 4b0d ldr r3, [pc, #52] @ (800cab4 ) 800ca7e: 801a strh r2, [r3, #0] infoPacket.boardVersion = InfoBlock->boardVersion; 800ca80: 4b0b ldr r3, [pc, #44] @ (800cab0 ) 800ca82: 681b ldr r3, [r3, #0] 800ca84: 795a ldrb r2, [r3, #5] 800ca86: 4b0b ldr r3, [pc, #44] @ (800cab4 ) 800ca88: 709a strb r2, [r3, #2] infoPacket.stationType = InfoBlock->stationType; 800ca8a: 4b09 ldr r3, [pc, #36] @ (800cab0 ) 800ca8c: 681b ldr r3, [r3, #0] 800ca8e: 791a ldrb r2, [r3, #4] 800ca90: 4b08 ldr r3, [pc, #32] @ (800cab4 ) 800ca92: 70da strb r2, [r3, #3] infoPacket.fw_version_major = FW_VERSION_MAJOR; 800ca94: 4b07 ldr r3, [pc, #28] @ (800cab4 ) 800ca96: 2201 movs r2, #1 800ca98: 809a strh r2, [r3, #4] infoPacket.fw_version_minor = FW_VERSION_MINOR; 800ca9a: 4b06 ldr r3, [pc, #24] @ (800cab4 ) 800ca9c: 2200 movs r2, #0 800ca9e: 80da strh r2, [r3, #6] infoPacket.fw_version_patch = FW_VERSION_PATCH; 800caa0: 4b04 ldr r3, [pc, #16] @ (800cab4 ) 800caa2: 2213 movs r2, #19 800caa4: 811a strh r2, [r3, #8] } 800caa6: bf00 nop 800caa8: 46bd mov sp, r7 800caaa: bc80 pop {r7} 800caac: 4770 bx lr 800caae: bf00 nop 800cab0: 20000000 .word 0x20000000 800cab4: 200011b0 .word 0x200011b0 0800cab8 : // Внешняя функция обработки команд (определена в serial_handler.c) extern void SC_CommandHandler(ReceivedCommand_t* cmd); void SC_Init() { 800cab8: b580 push {r7, lr} 800caba: af00 add r7, sp, #0 // Обнуляем структуру memset(&serial_control, 0, sizeof(SerialControl_t)); 800cabc: f44f 7204 mov.w r2, #528 @ 0x210 800cac0: 2100 movs r1, #0 800cac2: 480d ldr r0, [pc, #52] @ (800caf8 ) 800cac4: f008 f91e bl 8014d04 memset(&serial_iso, 0, sizeof(serial_iso)); 800cac8: f44f 7204 mov.w r2, #528 @ 0x210 800cacc: 2100 movs r1, #0 800cace: 480b ldr r0, [pc, #44] @ (800cafc ) 800cad0: f008 f918 bl 8014d04 sc_uart2_timed_out = 0; 800cad4: 4b0a ldr r3, [pc, #40] @ (800cb00 ) 800cad6: 2200 movs r2, #0 800cad8: 701a strb r2, [r3, #0] sc_uart2_last_packet_tick = HAL_GetTick(); 800cada: f001 fc59 bl 800e390 800cade: 4603 mov r3, r0 800cae0: 4a08 ldr r2, [pc, #32] @ (800cb04 ) 800cae2: 6013 str r3, [r2, #0] sc_uart2_last_recover_tick = sc_uart2_last_packet_tick; 800cae4: 4b07 ldr r3, [pc, #28] @ (800cb04 ) 800cae6: 681b ldr r3, [r3, #0] 800cae8: 4a07 ldr r2, [pc, #28] @ (800cb08 ) 800caea: 6013 str r3, [r2, #0] SC_ArmUart2RxDma(); 800caec: f000 fa14 bl 800cf18 SC_ArmUart5RxDma(); 800caf0: f000 fa36 bl 800cf60 } 800caf4: bf00 nop 800caf6: bd80 pop {r7, pc} 800caf8: 20000d2c .word 0x20000d2c 800cafc: 20000f3c .word 0x20000f3c 800cb00: 2000114d .word 0x2000114d 800cb04: 20001150 .word 0x20001150 800cb08: 20001154 .word 0x20001154 0800cb0c : void SC_Task() { 800cb0c: b580 push {r7, lr} 800cb0e: af00 add r7, sp, #0 static uint32_t tick; if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800cb10: f001 fc3e bl 800e390 800cb14: 4602 mov r2, r0 800cb16: 4b21 ldr r3, [pc, #132] @ (800cb9c ) 800cb18: 681b ldr r3, [r3, #0] 800cb1a: 1ad3 subs r3, r2, r3 800cb1c: 2b00 cmp r3, #0 800cb1e: dd3b ble.n 800cb98 tick = HAL_GetTick(); 800cb20: f001 fc36 bl 800e390 800cb24: 4603 mov r3, r0 800cb26: 4a1d ldr r2, [pc, #116] @ (800cb9c ) 800cb28: 6013 str r3, [r2, #0] SC_UART2_Watchdog(); 800cb2a: f000 f9ad bl 800ce88 // Запуск приема в режиме DMA + idle SC_ArmUart2RxDma(); 800cb2e: f000 f9f3 bl 800cf18 SC_ArmUart5RxDma(); 800cb32: f000 fa15 bl 800cf60 // Проверка таймаута отправки пакета (больше 100 мс) if (huart2.gState == HAL_UART_STATE_BUSY_TX && serial_control.tx_tick != 0) { 800cb36: 4b1a ldr r3, [pc, #104] @ (800cba0 ) 800cb38: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800cb3c: b2db uxtb r3, r3 800cb3e: 2b21 cmp r3, #33 @ 0x21 800cb40: d114 bne.n 800cb6c 800cb42: 4b18 ldr r3, [pc, #96] @ (800cba4 ) 800cb44: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c 800cb48: 2b00 cmp r3, #0 800cb4a: d00f beq.n 800cb6c if ((int32_t)(HAL_GetTick() - serial_control.tx_tick) > 100) { 800cb4c: f001 fc20 bl 800e390 800cb50: 4602 mov r2, r0 800cb52: 4b14 ldr r3, [pc, #80] @ (800cba4 ) 800cb54: f8d3 320c ldr.w r3, [r3, #524] @ 0x20c 800cb58: 1ad3 subs r3, r2, r3 800cb5a: 2b64 cmp r3, #100 @ 0x64 800cb5c: dd06 ble.n 800cb6c // Таймаут: принудительно сбрасываем передачу (void)HAL_UART_AbortTransmit(&huart2); 800cb5e: 4810 ldr r0, [pc, #64] @ (800cba0 ) 800cb60: f006 fb38 bl 80131d4 serial_control.tx_tick = 0; // Сбрасываем tick 800cb64: 4b0f ldr r3, [pc, #60] @ (800cba4 ) 800cb66: 2200 movs r2, #0 800cb68: f8c3 220c str.w r2, [r3, #524] @ 0x20c } } // Проверка наличия принятой команды для обработки if (serial_control.command_ready && (huart2.gState != HAL_UART_STATE_BUSY_TX)) { 800cb6c: 4b0d ldr r3, [pc, #52] @ (800cba4 ) 800cb6e: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800cb72: b2db uxtb r3, r3 800cb74: 2b00 cmp r3, #0 800cb76: d010 beq.n 800cb9a 800cb78: 4b09 ldr r3, [pc, #36] @ (800cba0 ) 800cb7a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800cb7e: b2db uxtb r3, r3 800cb80: 2b21 cmp r3, #33 @ 0x21 800cb82: d00a beq.n 800cb9a // HAL_Delay(2); SC_CommandHandler((ReceivedCommand_t*)&serial_control.received_command); 800cb84: 4808 ldr r0, [pc, #32] @ (800cba8 ) 800cb86: f000 fa87 bl 800d098 serial_control.command_ready = 0; // Сбрасываем флаг 800cb8a: 4b06 ldr r3, [pc, #24] @ (800cba4 ) 800cb8c: 2200 movs r2, #0 800cb8e: f883 2208 strb.w r2, [r3, #520] @ 0x208 SC_ArmUart2RxDma(); 800cb92: f000 f9c1 bl 800cf18 800cb96: e000 b.n 800cb9a if ((int32_t)(HAL_GetTick() - tick) < 1) return; 800cb98: bf00 nop } } 800cb9a: bd80 pop {r7, pc} 800cb9c: 200011bc .word 0x200011bc 800cba0: 200012e8 .word 0x200012e8 800cba4: 20000d2c .word 0x20000d2c 800cba8: 20000f2c .word 0x20000f2c 0800cbac : ISR_FAST void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { if (huart->Instance == huart2.Instance) { 800cbac: 4b2e ldr r3, [pc, #184] @ (800cc68 ) ISR_FAST void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800cbae: b570 push {r4, r5, r6, lr} if (huart->Instance == huart2.Instance) { 800cbb0: 681a ldr r2, [r3, #0] 800cbb2: 6803 ldr r3, [r0, #0] ISR_FAST void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800cbb4: 460c mov r4, r1 if (huart->Instance == huart2.Instance) { 800cbb6: 4293 cmp r3, r2 800cbb8: d019 beq.n 800cbee log_printf(LOG_WARN, "UART2 RX invalid packet len=%u\n", (unsigned)Size); SC_SendPacket(NULL, 0, RESP_INVALID); } g_sc_command_source = SC_SOURCE_UART2; SC_ArmUart2RxDma(); } else if (huart->Instance == huart5.Instance) { 800cbba: 4a2c ldr r2, [pc, #176] @ (800cc6c ) 800cbbc: 6812 ldr r2, [r2, #0] 800cbbe: 4293 cmp r3, r2 800cbc0: d004 beq.n 800cbcc SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); } else { log_printf(LOG_WARN, "UART5 RX invalid packet len=%u\n", (unsigned)Size); } SC_ArmUart5RxDma(); } else if (huart->Instance == huart3.Instance) { 800cbc2: 4a2b ldr r2, [pc, #172] @ (800cc70 ) 800cbc4: 6812 ldr r2, [r2, #0] 800cbc6: 4293 cmp r3, r2 800cbc8: d04a beq.n 800cc60 CCS_RxEventCallback(huart, Size); } } 800cbca: bd70 pop {r4, r5, r6, pc} if (Size == 0u) { 800cbcc: b399 cbz r1, 800cc36 if (process_received_packet(&serial_iso, serial_iso.rx_buffer, Size)) { 800cbce: 4929 ldr r1, [pc, #164] @ (800cc74 ) 800cbd0: 4622 mov r2, r4 800cbd2: f5a1 7080 sub.w r0, r1, #256 @ 0x100 800cbd6: f000 f949 bl 800ce6c 800cbda: bb10 cbnz r0, 800cc22 log_printf(LOG_WARN, "UART5 RX invalid packet len=%u\n", (unsigned)Size); 800cbdc: 4622 mov r2, r4 800cbde: 2005 movs r0, #5 800cbe0: 4925 ldr r1, [pc, #148] @ (800cc78 ) 800cbe2: f7fd fcc1 bl 800a568 } 800cbe6: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} SC_ArmUart5RxDma(); 800cbea: f000 b9b9 b.w 800cf60 if (Size == 0u) { 800cbee: b391 cbz r1, 800cc56 sc_uart2_last_packet_tick = HAL_GetTick(); 800cbf0: f001 fbce bl 800e390 sc_uart2_timed_out = 0; 800cbf4: 2200 movs r2, #0 800cbf6: 4b21 ldr r3, [pc, #132] @ (800cc7c ) if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800cbf8: 4921 ldr r1, [pc, #132] @ (800cc80 ) sc_uart2_timed_out = 0; 800cbfa: 701a strb r2, [r3, #0] sc_uart2_last_packet_tick = HAL_GetTick(); 800cbfc: 4603 mov r3, r0 sc_uart2_last_recover_tick = sc_uart2_last_packet_tick; 800cbfe: 4d21 ldr r5, [pc, #132] @ (800cc84 ) sc_uart2_last_packet_tick = HAL_GetTick(); 800cc00: 4e21 ldr r6, [pc, #132] @ (800cc88 ) if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800cc02: 4622 mov r2, r4 800cc04: f5a1 7080 sub.w r0, r1, #256 @ 0x100 sc_uart2_last_recover_tick = sc_uart2_last_packet_tick; 800cc08: 602b str r3, [r5, #0] sc_uart2_last_packet_tick = HAL_GetTick(); 800cc0a: 6033 str r3, [r6, #0] if(!process_received_packet(&serial_control, serial_control.rx_buffer, Size)){ 800cc0c: f000 f92e bl 800ce6c 800cc10: 4605 mov r5, r0 800cc12: b1a8 cbz r0, 800cc40 g_sc_command_source = SC_SOURCE_UART2; 800cc14: 2200 movs r2, #0 800cc16: 4b1d ldr r3, [pc, #116] @ (800cc8c ) 800cc18: 701a strb r2, [r3, #0] } 800cc1a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} SC_ArmUart2RxDma(); 800cc1e: f000 b97b b.w 800cf18 g_sc_command_source = SC_SOURCE_UART5; 800cc22: 2201 movs r2, #1 800cc24: 4b19 ldr r3, [pc, #100] @ (800cc8c ) SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); 800cc26: 481a ldr r0, [pc, #104] @ (800cc90 ) g_sc_command_source = SC_SOURCE_UART5; 800cc28: 701a strb r2, [r3, #0] SC_CommandHandler((ReceivedCommand_t*)&serial_iso.received_command); 800cc2a: f000 fa35 bl 800d098 } 800cc2e: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} SC_ArmUart5RxDma(); 800cc32: f000 b995 b.w 800cf60 log_printf(LOG_WARN, "UART5 RX idle event with zero size\n"); 800cc36: 4917 ldr r1, [pc, #92] @ (800cc94 ) 800cc38: 2005 movs r0, #5 800cc3a: f7fd fc95 bl 800a568 800cc3e: e7c6 b.n 800cbce log_printf(LOG_WARN, "UART2 RX invalid packet len=%u\n", (unsigned)Size); 800cc40: 4622 mov r2, r4 800cc42: 4915 ldr r1, [pc, #84] @ (800cc98 ) 800cc44: 2005 movs r0, #5 800cc46: f7fd fc8f bl 800a568 SC_SendPacket(NULL, 0, RESP_INVALID); 800cc4a: 2214 movs r2, #20 800cc4c: 4629 mov r1, r5 800cc4e: 4628 mov r0, r5 800cc50: f000 f8b6 bl 800cdc0 800cc54: e7de b.n 800cc14 log_printf(LOG_WARN, "UART2 RX idle event with zero size\n"); 800cc56: 4911 ldr r1, [pc, #68] @ (800cc9c ) 800cc58: 2005 movs r0, #5 800cc5a: f7fd fc85 bl 800a568 800cc5e: e7c7 b.n 800cbf0 } 800cc60: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} CCS_RxEventCallback(huart, Size); 800cc64: f7ff b812 b.w 800bc8c 800cc68: 200012e8 .word 0x200012e8 800cc6c: 20001258 .word 0x20001258 800cc70: 20001330 .word 0x20001330 800cc74: 2000103c .word 0x2000103c 800cc78: 08017804 .word 0x08017804 800cc7c: 2000114d .word 0x2000114d 800cc80: 20000e2c .word 0x20000e2c 800cc84: 20001154 .word 0x20001154 800cc88: 20001150 .word 0x20001150 800cc8c: 2000114c .word 0x2000114c 800cc90: 2000113c .word 0x2000113c 800cc94: 080177e0 .word 0x080177e0 800cc98: 080177c0 .word 0x080177c0 800cc9c: 0801779c .word 0x0801779c 0800cca0 : ISR_FAST void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { if (huart->Instance == huart2.Instance) { 800cca0: 4b08 ldr r3, [pc, #32] @ (800ccc4 ) 800cca2: 681a ldr r2, [r3, #0] 800cca4: 6803 ldr r3, [r0, #0] 800cca6: 4293 cmp r3, r2 800cca8: d004 beq.n 800ccb4 serial_control.tx_tick = 0; } else if (huart->Instance == huart3.Instance) { 800ccaa: 4a07 ldr r2, [pc, #28] @ (800ccc8 ) 800ccac: 6812 ldr r2, [r2, #0] 800ccae: 4293 cmp r3, r2 800ccb0: d005 beq.n 800ccbe CCS_TxCpltCallback(huart); } } 800ccb2: 4770 bx lr serial_control.tx_tick = 0; 800ccb4: 2200 movs r2, #0 800ccb6: 4b05 ldr r3, [pc, #20] @ (800cccc ) 800ccb8: f8c3 220c str.w r2, [r3, #524] @ 0x20c 800ccbc: 4770 bx lr CCS_TxCpltCallback(huart); 800ccbe: f7ff b88f b.w 800bde0 800ccc2: bf00 nop 800ccc4: 200012e8 .word 0x200012e8 800ccc8: 20001330 .word 0x20001330 800cccc: 20000d2c .word 0x20000d2c 0800ccd0 : // Полностью программная реализация CRC-32 (полином CRC32_POLYNOMIAL, порядок little-endian) ISR_FAST static uint32_t calculate_crc32(const uint8_t* data, uint16_t length) { uint32_t crc = 0xFFFFFFFFu; for (uint16_t i = 0; i < length; i++) { 800ccd0: b3c9 cbz r1, 800cd46 uint32_t crc = 0xFFFFFFFFu; 800ccd2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff ISR_FAST static uint32_t calculate_crc32(const uint8_t* data, uint16_t length) { 800ccd6: b500 push {lr} crc ^= data[i]; for (uint8_t bit = 0; bit < 8; bit++) { if (crc & 0x1u) { 800ccd8: 4a1c ldr r2, [pc, #112] @ (800cd4c ) 800ccda: 4401 add r1, r0 crc ^= data[i]; 800ccdc: f810 eb01 ldrb.w lr, [r0], #1 800cce0: ea8e 0e03 eor.w lr, lr, r3 if (crc & 0x1u) { 800cce4: f34e 0300 sbfx r3, lr, #0, #1 800cce8: f34e 0c40 sbfx ip, lr, #1, #1 800ccec: 4013 ands r3, r2 800ccee: ea83 035e eor.w r3, r3, lr, lsr #1 800ccf2: ea0c 0c02 and.w ip, ip, r2 800ccf6: ea8c 0c53 eor.w ip, ip, r3, lsr #1 800ccfa: f343 0340 sbfx r3, r3, #1, #1 800ccfe: f34c 0e40 sbfx lr, ip, #1, #1 800cd02: 4013 ands r3, r2 800cd04: ea83 035c eor.w r3, r3, ip, lsr #1 800cd08: ea0e 0e02 and.w lr, lr, r2 800cd0c: ea8e 0e53 eor.w lr, lr, r3, lsr #1 800cd10: f343 0340 sbfx r3, r3, #1, #1 800cd14: f34e 0c40 sbfx ip, lr, #1, #1 800cd18: 4013 ands r3, r2 800cd1a: ea83 035e eor.w r3, r3, lr, lsr #1 800cd1e: ea0c 0c02 and.w ip, ip, r2 800cd22: ea8c 0c53 eor.w ip, ip, r3, lsr #1 800cd26: f343 0340 sbfx r3, r3, #1, #1 800cd2a: 4013 ands r3, r2 800cd2c: f34c 0e40 sbfx lr, ip, #1, #1 800cd30: ea83 035c eor.w r3, r3, ip, lsr #1 for (uint16_t i = 0; i < length; i++) { 800cd34: 4281 cmp r1, r0 if (crc & 0x1u) { 800cd36: ea0e 0c02 and.w ip, lr, r2 800cd3a: ea8c 0353 eor.w r3, ip, r3, lsr #1 for (uint16_t i = 0; i < length; i++) { 800cd3e: d1cd bne.n 800ccdc crc >>= 1; } } } return crc ^ 0xFFFFFFFFu; 800cd40: 43d8 mvns r0, r3 } 800cd42: f85d fb04 ldr.w pc, [sp], #4 for (uint16_t i = 0; i < length; i++) { 800cd46: 4608 mov r0, r1 } 800cd48: 4770 bx lr 800cd4a: bf00 nop 800cd4c: edb88320 .word 0xedb88320 0800cd50 : ISR_FAST static uint16_t encode_packet(const uint8_t* payload, uint16_t payload_len, uint8_t* output, uint8_t response_code) { 800cd50: b570 push {r4, r5, r6, lr} 800cd52: 4615 mov r5, r2 uint16_t out_index = 0; output[out_index++] = response_code; 800cd54: 7013 strb r3, [r2, #0] if (payload != NULL) { 800cd56: b360 cbz r0, 800cdb2 // Просто копируем полезную нагрузку без какого‑либо экранирования for (uint16_t i = 0; i < payload_len; i++) { 800cd58: b359 cbz r1, 800cdb2 output[out_index++] = payload[i]; 800cd5a: 4694 mov ip, r2 800cd5c: 2302 movs r3, #2 800cd5e: 7802 ldrb r2, [r0, #0] 800cd60: 1e4c subs r4, r1, #1 800cd62: b2a4 uxth r4, r4 800cd64: 441c add r4, r3 800cd66: f80c 2f01 strb.w r2, [ip, #1]! // Проверка переполнения if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800cd6a: e005 b.n 800cd78 output[out_index++] = payload[i]; 800cd6c: f810 1f01 ldrb.w r1, [r0, #1]! if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800cd70: 2bfb cmp r3, #251 @ 0xfb output[out_index++] = payload[i]; 800cd72: f80c 1f01 strb.w r1, [ip, #1]! if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800cd76: d020 beq.n 800cdba for (uint16_t i = 0; i < payload_len; i++) { 800cd78: 42a3 cmp r3, r4 if (out_index >= MAX_TX_BUFFER_SIZE - 5) { // 4 байта CRC + END_BYTE 800cd7a: f103 0301 add.w r3, r3, #1 for (uint16_t i = 0; i < payload_len; i++) { 800cd7e: d1f5 bne.n 800cd6c 800cd80: b2a1 uxth r1, r4 output[out_index++] = payload[i]; 800cd82: 1c4e adds r6, r1, #1 800cd84: b2b6 uxth r6, r6 } } } // Вычисляем CRC для всего содержимого (код ответа + полезная нагрузка) uint32_t crc = calculate_crc32(output, out_index); 800cd86: 4628 mov r0, r5 800cd88: f7ff ffa2 bl 800ccd0 800cd8c: 4603 mov r3, r0 uint8_t* crc_bytes = (uint8_t*)&crc; // Добавляем CRC без экранирования for (int i = 0; i < 4; i++) { output[out_index++] = crc_bytes[i]; 800cd8e: 1c71 adds r1, r6, #1 800cd90: 1cb2 adds r2, r6, #2 800cd92: 552b strb r3, [r5, r4] 800cd94: f3c3 2c07 ubfx ip, r3, #8, #8 800cd98: f3c3 4407 ubfx r4, r3, #16, #8 800cd9c: b289 uxth r1, r1 800cd9e: b292 uxth r2, r2 800cda0: f3c3 6307 ubfx r3, r3, #24, #8 800cda4: f805 c006 strb.w ip, [r5, r6] 800cda8: 1cf0 adds r0, r6, #3 800cdaa: 546c strb r4, [r5, r1] 800cdac: 54ab strb r3, [r5, r2] 800cdae: b280 uxth r0, r0 return 0; } } return out_index; } 800cdb0: bd70 pop {r4, r5, r6, pc} for (uint16_t i = 0; i < payload_len; i++) { 800cdb2: 2401 movs r4, #1 800cdb4: 2602 movs r6, #2 output[out_index++] = response_code; 800cdb6: 4621 mov r1, r4 800cdb8: e7e5 b.n 800cd86 return 0; 800cdba: 2000 movs r0, #0 } 800cdbc: bd70 pop {r4, r5, r6, pc} 800cdbe: bf00 nop 0800cdc0 : ISR_FAST void SC_SendPacket(const uint8_t* payload, uint16_t payload_len, uint8_t response_code) { 800cdc0: b538 push {r3, r4, r5, lr} 800cdc2: 4613 mov r3, r2 uint16_t packet_len = encode_packet(payload, payload_len, serial_control.tx_buffer, response_code); 800cdc4: 4a11 ldr r2, [pc, #68] @ (800ce0c ) 800cdc6: f7ff ffc3 bl 800cd50 if (packet_len > 0) { 800cdca: b180 cbz r0, 800cdee if (huart2.gState != HAL_UART_STATE_READY) { 800cdcc: 4604 mov r4, r0 800cdce: 4810 ldr r0, [pc, #64] @ (800ce10 ) 800cdd0: f890 3041 ldrb.w r3, [r0, #65] @ 0x41 800cdd4: 2b20 cmp r3, #32 800cdd6: d10b bne.n 800cdf0 (void)HAL_UART_AbortTransmit(&huart2); log_printf(LOG_WARN, "UART2 TX busy, abort transmit before resend\n"); } if (HAL_UART_Transmit_DMA(&huart2, serial_control.tx_buffer, packet_len) != HAL_OK) { 800cdd8: 4d0c ldr r5, [pc, #48] @ (800ce0c ) 800cdda: 4622 mov r2, r4 800cddc: 4629 mov r1, r5 800cdde: 480c ldr r0, [pc, #48] @ (800ce10 ) 800cde0: f006 f8d2 bl 8012f88 800cde4: b958 cbnz r0, 800cdfe SC_LogUartError("UART2 TX DMA start failed", &huart2); return; } serial_control.tx_tick = HAL_GetTick(); 800cde6: f001 fad3 bl 800e390 800cdea: f8c5 020c str.w r0, [r5, #524] @ 0x20c } } 800cdee: bd38 pop {r3, r4, r5, pc} (void)HAL_UART_AbortTransmit(&huart2); 800cdf0: f006 f9f0 bl 80131d4 log_printf(LOG_WARN, "UART2 TX busy, abort transmit before resend\n"); 800cdf4: 4907 ldr r1, [pc, #28] @ (800ce14 ) 800cdf6: 2005 movs r0, #5 800cdf8: f7fd fbb6 bl 800a568 800cdfc: e7ec b.n 800cdd8 SC_LogUartError("UART2 TX DMA start failed", &huart2); 800cdfe: 4904 ldr r1, [pc, #16] @ (800ce10 ) 800ce00: 4805 ldr r0, [pc, #20] @ (800ce18 ) } 800ce02: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} SC_LogUartError("UART2 TX DMA start failed", &huart2); 800ce06: f000 b905 b.w 800d014 800ce0a: bf00 nop 800ce0c: 20000d2c .word 0x20000d2c 800ce10: 200012e8 .word 0x200012e8 800ce14: 08017824 .word 0x08017824 800ce18: 08017854 .word 0x08017854 0800ce1c : ISR_FAST static uint8_t parse_packet(const uint8_t* packet_data, uint16_t packet_len, ReceivedCommand_t* out_cmd) { 800ce1c: e92d 4178 stmdb sp!, {r3, r4, r5, r6, r8, lr} // }else{ // test_crc_invalid = 5; // } // Минимальный размер: 1 байт команды + 4 байта CRC if (packet_len < 5) return 0; 800ce20: 1f4b subs r3, r1, #5 800ce22: 2bfb cmp r3, #251 @ 0xfb 800ce24: d813 bhi.n 800ce4e if (packet_len > MAX_RX_BUFFER_SIZE) return 0; uint16_t payload_length = packet_len - 4; 800ce26: 3904 subs r1, #4 800ce28: b28c uxth r4, r1 // Извлекаем принятую CRC (последние 4 байта, little-endian) uint32_t received_checksum = ((uint32_t)packet_data[payload_length] << 0) | ((uint32_t)packet_data[payload_length + 1] << 8) | 800ce2a: 1903 adds r3, r0, r4 ((uint32_t)packet_data[payload_length + 2] << 16) | 800ce2c: 789d ldrb r5, [r3, #2] 800ce2e: 4690 mov r8, r2 ((uint32_t)packet_data[payload_length + 1] << 8) | 800ce30: 785a ldrb r2, [r3, #1] ((uint32_t)packet_data[payload_length + 2] << 16) | 800ce32: 042d lsls r5, r5, #16 ((uint32_t)packet_data[payload_length + 1] << 8) | 800ce34: ea45 2502 orr.w r5, r5, r2, lsl #8 ((uint32_t)packet_data[payload_length] << 0) | 800ce38: 5d02 ldrb r2, [r0, r4] ((uint32_t)packet_data[payload_length + 3] << 24); 800ce3a: 78db ldrb r3, [r3, #3] ((uint32_t)packet_data[payload_length + 1] << 8) | 800ce3c: 4315 orrs r5, r2 // Вычисляем CRC для полезной нагрузки uint32_t calculated_checksum = calculate_crc32(packet_data, payload_length); 800ce3e: 4621 mov r1, r4 uint32_t received_checksum = 800ce40: ea45 6503 orr.w r5, r5, r3, lsl #24 uint32_t calculated_checksum = calculate_crc32(packet_data, payload_length); 800ce44: 4606 mov r6, r0 800ce46: f7ff ff43 bl 800ccd0 if (received_checksum != calculated_checksum) return 0; // CRC не совпадает 800ce4a: 4285 cmp r5, r0 800ce4c: d002 beq.n 800ce54 if (packet_len < 5) return 0; 800ce4e: 2000 movs r0, #0 out_cmd->argument = (void *)&packet_data[1]; out_cmd->command = packet_data[0]; out_cmd->argument_length = (uint8_t)(payload_length - 1); return 1; } 800ce50: e8bd 8178 ldmia.w sp!, {r3, r4, r5, r6, r8, pc} out_cmd->argument = (void *)&packet_data[1]; 800ce54: 1c73 adds r3, r6, #1 800ce56: f8c8 3004 str.w r3, [r8, #4] out_cmd->command = packet_data[0]; 800ce5a: 7833 ldrb r3, [r6, #0] out_cmd->argument_length = (uint8_t)(payload_length - 1); 800ce5c: 3c01 subs r4, #1 out_cmd->command = packet_data[0]; 800ce5e: f888 3000 strb.w r3, [r8] out_cmd->argument_length = (uint8_t)(payload_length - 1); 800ce62: f888 4001 strb.w r4, [r8, #1] return 1; 800ce66: 2001 movs r0, #1 } 800ce68: e8bd 8178 ldmia.w sp!, {r3, r4, r5, r6, r8, pc} 0800ce6c : ISR_FAST static uint8_t process_received_packet(SerialControl_t *ctx, const uint8_t* packet_data, uint16_t packet_len) { 800ce6c: b510 push {r4, lr} 800ce6e: 4604 mov r4, r0 if (!parse_packet(packet_data, packet_len, (ReceivedCommand_t *)&ctx->received_command)) { 800ce70: 4608 mov r0, r1 800ce72: 4611 mov r1, r2 800ce74: f504 7200 add.w r2, r4, #512 @ 0x200 800ce78: f7ff ffd0 bl 800ce1c 800ce7c: b118 cbz r0, 800ce86 return 0; } ctx->command_ready = 1; 800ce7e: 2301 movs r3, #1 return 1; 800ce80: 4618 mov r0, r3 ctx->command_ready = 1; 800ce82: f884 3208 strb.w r3, [r4, #520] @ 0x208 } 800ce86: bd10 pop {r4, pc} 0800ce88 : static void SC_UART2_Watchdog(void) { 800ce88: b580 push {r7, lr} 800ce8a: b082 sub sp, #8 800ce8c: af00 add r7, sp, #0 const uint32_t now = HAL_GetTick(); 800ce8e: f001 fa7f bl 800e390 800ce92: 6078 str r0, [r7, #4] const int32_t since_last_packet = (int32_t)(now - sc_uart2_last_packet_tick); 800ce94: 4b1a ldr r3, [pc, #104] @ (800cf00 ) 800ce96: 681b ldr r3, [r3, #0] 800ce98: 687a ldr r2, [r7, #4] 800ce9a: 1ad3 subs r3, r2, r3 800ce9c: 603b str r3, [r7, #0] if (since_last_packet >= (int32_t)SC_UART2_PACKET_TIMEOUT_MS) { 800ce9e: 683b ldr r3, [r7, #0] 800cea0: f241 3287 movw r2, #4999 @ 0x1387 800cea4: 4293 cmp r3, r2 800cea6: dd12 ble.n 800cece if (sc_uart2_timed_out == 0u) { 800cea8: 4b16 ldr r3, [pc, #88] @ (800cf04 ) 800ceaa: 781b ldrb r3, [r3, #0] 800ceac: b2db uxtb r3, r3 800ceae: 2b00 cmp r3, #0 800ceb0: d109 bne.n 800cec6 serial_control.command_ready = 0; 800ceb2: 4b15 ldr r3, [pc, #84] @ (800cf08 ) 800ceb4: 2200 movs r2, #0 800ceb6: f883 2208 strb.w r2, [r3, #520] @ 0x208 log_printf(LOG_WARN, "UART2 RX packet timeout (%u ms)\n", (unsigned)SC_UART2_PACKET_TIMEOUT_MS); 800ceba: f241 3288 movw r2, #5000 @ 0x1388 800cebe: 4913 ldr r1, [pc, #76] @ (800cf0c ) 800cec0: 2005 movs r0, #5 800cec2: f7fd fb51 bl 800a568 } sc_uart2_timed_out = 1; 800cec6: 4b0f ldr r3, [pc, #60] @ (800cf04 ) 800cec8: 2201 movs r2, #1 800ceca: 701a strb r2, [r3, #0] 800cecc: e002 b.n 800ced4 } else { sc_uart2_timed_out = 0; 800cece: 4b0d ldr r3, [pc, #52] @ (800cf04 ) 800ced0: 2200 movs r2, #0 800ced2: 701a strb r2, [r3, #0] } if ((huart2.RxState == HAL_UART_STATE_READY) && 800ced4: 4b0e ldr r3, [pc, #56] @ (800cf10 ) 800ced6: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800ceda: b2db uxtb r3, r3 800cedc: 2b20 cmp r3, #32 800cede: d10a bne.n 800cef6 ((int32_t)(now - sc_uart2_last_recover_tick) >= (int32_t)SC_UART2_RECOVER_GUARD_MS)) { 800cee0: 4b0c ldr r3, [pc, #48] @ (800cf14 ) 800cee2: 681b ldr r3, [r3, #0] 800cee4: 687a ldr r2, [r7, #4] 800cee6: 1ad3 subs r3, r2, r3 if ((huart2.RxState == HAL_UART_STATE_READY) && 800cee8: 2bc7 cmp r3, #199 @ 0xc7 800ceea: dd04 ble.n 800cef6 SC_ArmUart2RxDma(); 800ceec: f000 f814 bl 800cf18 sc_uart2_last_recover_tick = now; 800cef0: 4a08 ldr r2, [pc, #32] @ (800cf14 ) 800cef2: 687b ldr r3, [r7, #4] 800cef4: 6013 str r3, [r2, #0] } } 800cef6: bf00 nop 800cef8: 3708 adds r7, #8 800cefa: 46bd mov sp, r7 800cefc: bd80 pop {r7, pc} 800cefe: bf00 nop 800cf00: 20001150 .word 0x20001150 800cf04: 2000114d .word 0x2000114d 800cf08: 20000d2c .word 0x20000d2c 800cf0c: 08017870 .word 0x08017870 800cf10: 200012e8 .word 0x200012e8 800cf14: 20001154 .word 0x20001154 0800cf18 : static void SC_ArmUart2RxDma(void) { 800cf18: b580 push {r7, lr} 800cf1a: af00 add r7, sp, #0 if ((huart2.RxState == HAL_UART_STATE_READY) && (serial_control.command_ready == 0)) { 800cf1c: 4b0c ldr r3, [pc, #48] @ (800cf50 ) 800cf1e: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800cf22: b2db uxtb r3, r3 800cf24: 2b20 cmp r3, #32 800cf26: d111 bne.n 800cf4c 800cf28: 4b0a ldr r3, [pc, #40] @ (800cf54 ) 800cf2a: f893 3208 ldrb.w r3, [r3, #520] @ 0x208 800cf2e: b2db uxtb r3, r3 800cf30: 2b00 cmp r3, #0 800cf32: d10b bne.n 800cf4c if (HAL_UARTEx_ReceiveToIdle_DMA(&huart2, serial_control.rx_buffer, MAX_RX_BUFFER_SIZE - 1) != HAL_OK) { 800cf34: 22ff movs r2, #255 @ 0xff 800cf36: 4908 ldr r1, [pc, #32] @ (800cf58 ) 800cf38: 4805 ldr r0, [pc, #20] @ (800cf50 ) 800cf3a: f006 f8f2 bl 8013122 800cf3e: 4603 mov r3, r0 800cf40: 2b00 cmp r3, #0 800cf42: d003 beq.n 800cf4c SC_LogUartError("UART2 RX DMA arm failed", &huart2); 800cf44: 4902 ldr r1, [pc, #8] @ (800cf50 ) 800cf46: 4805 ldr r0, [pc, #20] @ (800cf5c ) 800cf48: f000 f864 bl 800d014 } } } 800cf4c: bf00 nop 800cf4e: bd80 pop {r7, pc} 800cf50: 200012e8 .word 0x200012e8 800cf54: 20000d2c .word 0x20000d2c 800cf58: 20000e2c .word 0x20000e2c 800cf5c: 08017894 .word 0x08017894 0800cf60 : static void SC_ArmUart5RxDma(void) { 800cf60: b580 push {r7, lr} 800cf62: af00 add r7, sp, #0 if (huart5.RxState == HAL_UART_STATE_READY) { 800cf64: 4b0a ldr r3, [pc, #40] @ (800cf90 ) 800cf66: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800cf6a: b2db uxtb r3, r3 800cf6c: 2b20 cmp r3, #32 800cf6e: d10d bne.n 800cf8c if (HAL_UARTEx_ReceiveToIdle_IT(&huart5, serial_iso.rx_buffer, MAX_RX_BUFFER_SIZE - 1) == HAL_OK) { 800cf70: 22ff movs r2, #255 @ 0xff 800cf72: 4908 ldr r1, [pc, #32] @ (800cf94 ) 800cf74: 4806 ldr r0, [pc, #24] @ (800cf90 ) 800cf76: f006 f877 bl 8013068 800cf7a: 4603 mov r3, r0 800cf7c: 2b00 cmp r3, #0 800cf7e: d004 beq.n 800cf8a return; } SC_LogUartError("UART5 RX IT arm failed", &huart5); 800cf80: 4903 ldr r1, [pc, #12] @ (800cf90 ) 800cf82: 4805 ldr r0, [pc, #20] @ (800cf98 ) 800cf84: f000 f846 bl 800d014 800cf88: e000 b.n 800cf8c return; 800cf8a: bf00 nop } } 800cf8c: bd80 pop {r7, pc} 800cf8e: bf00 nop 800cf90: 20001258 .word 0x20001258 800cf94: 2000103c .word 0x2000103c 800cf98: 080178ac .word 0x080178ac 0800cf9c : void SC_RecoverUartDma(UART_HandleTypeDef *huart) { 800cf9c: b580 push {r7, lr} 800cf9e: b082 sub sp, #8 800cfa0: af00 add r7, sp, #0 800cfa2: 6078 str r0, [r7, #4] if (huart == &huart2) { 800cfa4: 687b ldr r3, [r7, #4] 800cfa6: 4a15 ldr r2, [pc, #84] @ (800cffc ) 800cfa8: 4293 cmp r3, r2 800cfaa: d115 bne.n 800cfd8 SC_LogUartError("UART2 recover start", &huart2); 800cfac: 4913 ldr r1, [pc, #76] @ (800cffc ) 800cfae: 4814 ldr r0, [pc, #80] @ (800d000 ) 800cfb0: f000 f830 bl 800d014 (void)HAL_UART_AbortReceive(&huart2); 800cfb4: 4811 ldr r0, [pc, #68] @ (800cffc ) 800cfb6: f006 f975 bl 80132a4 (void)HAL_UART_AbortTransmit(&huart2); 800cfba: 4810 ldr r0, [pc, #64] @ (800cffc ) 800cfbc: f006 f90a bl 80131d4 serial_control.tx_tick = 0; 800cfc0: 4b10 ldr r3, [pc, #64] @ (800d004 ) 800cfc2: 2200 movs r2, #0 800cfc4: f8c3 220c str.w r2, [r3, #524] @ 0x20c SC_ArmUart2RxDma(); 800cfc8: f7ff ffa6 bl 800cf18 sc_uart2_last_recover_tick = HAL_GetTick(); 800cfcc: f001 f9e0 bl 800e390 800cfd0: 4603 mov r3, r0 800cfd2: 4a0d ldr r2, [pc, #52] @ (800d008 ) 800cfd4: 6013 str r3, [r2, #0] } else if (huart == &huart5) { SC_LogUartError("UART5 recover start", &huart5); (void)HAL_UART_AbortReceive(&huart5); SC_ArmUart5RxDma(); } } 800cfd6: e00c b.n 800cff2 } else if (huart == &huart5) { 800cfd8: 687b ldr r3, [r7, #4] 800cfda: 4a0c ldr r2, [pc, #48] @ (800d00c ) 800cfdc: 4293 cmp r3, r2 800cfde: d108 bne.n 800cff2 SC_LogUartError("UART5 recover start", &huart5); 800cfe0: 490a ldr r1, [pc, #40] @ (800d00c ) 800cfe2: 480b ldr r0, [pc, #44] @ (800d010 ) 800cfe4: f000 f816 bl 800d014 (void)HAL_UART_AbortReceive(&huart5); 800cfe8: 4808 ldr r0, [pc, #32] @ (800d00c ) 800cfea: f006 f95b bl 80132a4 SC_ArmUart5RxDma(); 800cfee: f7ff ffb7 bl 800cf60 } 800cff2: bf00 nop 800cff4: 3708 adds r7, #8 800cff6: 46bd mov sp, r7 800cff8: bd80 pop {r7, pc} 800cffa: bf00 nop 800cffc: 200012e8 .word 0x200012e8 800d000: 080178c4 .word 0x080178c4 800d004: 20000d2c .word 0x20000d2c 800d008: 20001154 .word 0x20001154 800d00c: 20001258 .word 0x20001258 800d010: 080178d8 .word 0x080178d8 0800d014 : static void SC_LogUartError(const char *tag, UART_HandleTypeDef *huart) { 800d014: b590 push {r4, r7, lr} 800d016: b087 sub sp, #28 800d018: af04 add r7, sp, #16 800d01a: 6078 str r0, [r7, #4] 800d01c: 6039 str r1, [r7, #0] if (tag == NULL || huart == NULL) { 800d01e: 687b ldr r3, [r7, #4] 800d020: 2b00 cmp r3, #0 800d022: d01c beq.n 800d05e 800d024: 683b ldr r3, [r7, #0] 800d026: 2b00 cmp r3, #0 800d028: d019 beq.n 800d05e return; } log_printf(LOG_ERR, "%s: instance=0x%08lx err=0x%08lx g=%lu rx=%lu\n", tag, (unsigned long)huart->Instance, 800d02a: 683b ldr r3, [r7, #0] 800d02c: 681b ldr r3, [r3, #0] log_printf(LOG_ERR, "%s: instance=0x%08lx err=0x%08lx g=%lu rx=%lu\n", 800d02e: 461c mov r4, r3 (unsigned long)HAL_UART_GetError(huart), 800d030: 6838 ldr r0, [r7, #0] 800d032: f006 fc88 bl 8013946 800d036: 4602 mov r2, r0 (unsigned long)huart->gState, 800d038: 683b ldr r3, [r7, #0] 800d03a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800d03e: b2db uxtb r3, r3 log_printf(LOG_ERR, "%s: instance=0x%08lx err=0x%08lx g=%lu rx=%lu\n", 800d040: 4619 mov r1, r3 (unsigned long)huart->RxState); 800d042: 683b ldr r3, [r7, #0] 800d044: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800d048: b2db uxtb r3, r3 log_printf(LOG_ERR, "%s: instance=0x%08lx err=0x%08lx g=%lu rx=%lu\n", 800d04a: 9302 str r3, [sp, #8] 800d04c: 9101 str r1, [sp, #4] 800d04e: 9200 str r2, [sp, #0] 800d050: 4623 mov r3, r4 800d052: 687a ldr r2, [r7, #4] 800d054: 4904 ldr r1, [pc, #16] @ (800d068 ) 800d056: 2004 movs r0, #4 800d058: f7fd fa86 bl 800a568 800d05c: e000 b.n 800d060 return; 800d05e: bf00 nop } 800d060: 370c adds r7, #12 800d062: 46bd mov sp, r7 800d064: bd90 pop {r4, r7, pc} 800d066: bf00 nop 800d068: 080178ec .word 0x080178ec 0800d06c <__NVIC_SystemReset>: { 800d06c: b480 push {r7} 800d06e: af00 add r7, sp, #0 __ASM volatile ("dsb 0xF":::"memory"); 800d070: f3bf 8f4f dsb sy } 800d074: bf00 nop (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 800d076: 4b06 ldr r3, [pc, #24] @ (800d090 <__NVIC_SystemReset+0x24>) 800d078: 68db ldr r3, [r3, #12] 800d07a: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800d07e: 4904 ldr r1, [pc, #16] @ (800d090 <__NVIC_SystemReset+0x24>) 800d080: 4b04 ldr r3, [pc, #16] @ (800d094 <__NVIC_SystemReset+0x28>) 800d082: 4313 orrs r3, r2 800d084: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 800d086: f3bf 8f4f dsb sy } 800d08a: bf00 nop __NOP(); 800d08c: bf00 nop 800d08e: e7fd b.n 800d08c <__NVIC_SystemReset+0x20> 800d090: e000ed00 .word 0xe000ed00 800d094: 05fa0004 .word 0x05fa0004 0800d098 : .chargerNumber = 00001, .unixTime = 1721651966, }; // Единая функция-обработчик всех команд со switch-case void SC_CommandHandler(ReceivedCommand_t* cmd) { 800d098: b580 push {r7, lr} 800d09a: b084 sub sp, #16 800d09c: af00 add r7, sp, #0 800d09e: 6078 str r0, [r7, #4] uint8_t response_code = RESP_FAILED; 800d0a0: 2313 movs r3, #19 800d0a2: 73fb strb r3, [r7, #15] switch (cmd->command) { 800d0a4: 687b ldr r3, [r7, #4] 800d0a6: 781b ldrb r3, [r3, #0] 800d0a8: 2bc2 cmp r3, #194 @ 0xc2 800d0aa: f300 80d1 bgt.w 800d250 800d0ae: 2bb0 cmp r3, #176 @ 0xb0 800d0b0: da0f bge.n 800d0d2 800d0b2: 2b60 cmp r3, #96 @ 0x60 800d0b4: d042 beq.n 800d13c 800d0b6: 2b60 cmp r3, #96 @ 0x60 800d0b8: f300 80ca bgt.w 800d250 800d0bc: 2b50 cmp r3, #80 @ 0x50 800d0be: d043 beq.n 800d148 800d0c0: 2b50 cmp r3, #80 @ 0x50 800d0c2: f300 80c5 bgt.w 800d250 800d0c6: 2b01 cmp r3, #1 800d0c8: f000 80ab beq.w 800d222 800d0cc: 2b40 cmp r3, #64 @ 0x40 800d0ce: d02d beq.n 800d12c 800d0d0: e0be b.n 800d250 800d0d2: 3bb0 subs r3, #176 @ 0xb0 800d0d4: 2b12 cmp r3, #18 800d0d6: f200 80bb bhi.w 800d250 800d0da: a201 add r2, pc, #4 @ (adr r2, 800d0e0 ) 800d0dc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d0e0: 0800d14f .word 0x0800d14f 800d0e4: 0800d251 .word 0x0800d251 800d0e8: 0800d251 .word 0x0800d251 800d0ec: 0800d251 .word 0x0800d251 800d0f0: 0800d251 .word 0x0800d251 800d0f4: 0800d201 .word 0x0800d201 800d0f8: 0800d251 .word 0x0800d251 800d0fc: 0800d1f7 .word 0x0800d1f7 800d100: 0800d251 .word 0x0800d251 800d104: 0800d251 .word 0x0800d251 800d108: 0800d251 .word 0x0800d251 800d10c: 0800d251 .word 0x0800d251 800d110: 0800d251 .word 0x0800d251 800d114: 0800d251 .word 0x0800d251 800d118: 0800d251 .word 0x0800d251 800d11c: 0800d251 .word 0x0800d251 800d120: 0800d18d .word 0x0800d18d 800d124: 0800d1f1 .word 0x0800d1f1 800d128: 0800d1c5 .word 0x0800d1c5 // Команды БЕЗ аргументов case CMD_GET_STATUS: // Логика получения информации monitoring_data_callback(); 800d12c: f000 f8b6 bl 800d29c // Отправляем с нормальным приоритетом SC_SendPacket((uint8_t*)&statusPacket, sizeof(statusPacket), CMD_GET_STATUS); 800d130: 2240 movs r2, #64 @ 0x40 800d132: 2158 movs r1, #88 @ 0x58 800d134: 484d ldr r0, [pc, #308] @ (800d26c ) 800d136: f7ff fe43 bl 800cdc0 return; // Специальный ответ уже отправлен 800d13a: e094 b.n 800d266 case CMD_GET_INFO: SC_SendPacket((uint8_t*)&infoPacket, sizeof(infoPacket), CMD_GET_INFO); 800d13c: 2260 movs r2, #96 @ 0x60 800d13e: 210a movs r1, #10 800d140: 484b ldr r0, [pc, #300] @ (800d270 ) 800d142: f7ff fe3d bl 800cdc0 return; 800d146: e08e b.n 800d266 case CMD_GET_LOG: debug_buffer_send(); 800d148: f7fd f9ac bl 800a4a4 return; // Ответ формируется внутри debug_buffer_send 800d14c: e08b b.n 800d266 // Команды С аргументами case CMD_SET_CONFIG: if (cmd->argument_length == sizeof(ConfigBlock_t)) { 800d14e: 687b ldr r3, [r7, #4] 800d150: 785b ldrb r3, [r3, #1] 800d152: 2b0b cmp r3, #11 800d154: d117 bne.n 800d186 memcpy(&config, cmd->argument, sizeof(ConfigBlock_t)); 800d156: 687b ldr r3, [r7, #4] 800d158: 685a ldr r2, [r3, #4] 800d15a: 4b46 ldr r3, [pc, #280] @ (800d274 ) 800d15c: 6810 ldr r0, [r2, #0] 800d15e: 6851 ldr r1, [r2, #4] 800d160: c303 stmia r3!, {r0, r1} 800d162: 8911 ldrh r1, [r2, #8] 800d164: 7a92 ldrb r2, [r2, #10] 800d166: 8019 strh r1, [r3, #0] 800d168: 709a strb r2, [r3, #2] config_initialized = 1; 800d16a: 4b43 ldr r3, [pc, #268] @ (800d278 ) 800d16c: 2201 movs r2, #1 800d16e: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Set Config: %s %d\n", config.location, config.chargerNumber); 800d170: 4b40 ldr r3, [pc, #256] @ (800d274 ) 800d172: f8d3 3003 ldr.w r3, [r3, #3] 800d176: 4a3f ldr r2, [pc, #252] @ (800d274 ) 800d178: 4940 ldr r1, [pc, #256] @ (800d27c ) 800d17a: 2007 movs r0, #7 800d17c: f7fd f9f4 bl 800a568 response_code = RESP_SUCCESS; 800d180: 2312 movs r3, #18 800d182: 73fb strb r3, [r7, #15] break; 800d184: e067 b.n 800d256 } response_code = RESP_FAILED; 800d186: 2313 movs r3, #19 800d188: 73fb strb r3, [r7, #15] break; 800d18a: e064 b.n 800d256 case CMD_SET_POWER_LIMIT: if (cmd->argument_length == 1) { 800d18c: 687b ldr r3, [r7, #4] 800d18e: 785b ldrb r3, [r3, #1] 800d190: 2b01 cmp r3, #1 800d192: d114 bne.n 800d1be PSU0.power_limit = ((uint8_t*)cmd->argument)[0] * 1000; 800d194: 687b ldr r3, [r7, #4] 800d196: 685b ldr r3, [r3, #4] 800d198: 781b ldrb r3, [r3, #0] 800d19a: 461a mov r2, r3 800d19c: f44f 737a mov.w r3, #1000 @ 0x3e8 800d1a0: fb02 f303 mul.w r3, r2, r3 800d1a4: 461a mov r2, r3 800d1a6: 4b36 ldr r3, [pc, #216] @ (800d280 ) 800d1a8: 615a str r2, [r3, #20] log_printf(LOG_INFO, "Power limit: %d\n", PSU0.power_limit); 800d1aa: 4b35 ldr r3, [pc, #212] @ (800d280 ) 800d1ac: 695b ldr r3, [r3, #20] 800d1ae: 461a mov r2, r3 800d1b0: 4934 ldr r1, [pc, #208] @ (800d284 ) 800d1b2: 2007 movs r0, #7 800d1b4: f7fd f9d8 bl 800a568 //CONN.connState = (((uint8_t*)cmd->argument)[0])/4; response_code = RESP_SUCCESS; 800d1b8: 2312 movs r3, #18 800d1ba: 73fb strb r3, [r7, #15] break; 800d1bc: e04b b.n 800d256 } response_code = RESP_FAILED; 800d1be: 2313 movs r3, #19 800d1c0: 73fb strb r3, [r7, #15] break; 800d1c2: e048 b.n 800d256 case CMD_CHARGE_PERMIT: if (cmd->argument_length == 1) { 800d1c4: 687b ldr r3, [r7, #4] 800d1c6: 785b ldrb r3, [r3, #1] 800d1c8: 2b01 cmp r3, #1 800d1ca: d10e bne.n 800d1ea CONN.connControl = ((uint8_t*)cmd->argument)[0]; 800d1cc: 687b ldr r3, [r7, #4] 800d1ce: 685b ldr r3, [r3, #4] 800d1d0: 781a ldrb r2, [r3, #0] 800d1d2: 4b2d ldr r3, [pc, #180] @ (800d288 ) 800d1d4: 701a strb r2, [r3, #0] log_printf(LOG_INFO, "Charge permit: %d\n", CONN.connControl); 800d1d6: 4b2c ldr r3, [pc, #176] @ (800d288 ) 800d1d8: 781b ldrb r3, [r3, #0] 800d1da: 461a mov r2, r3 800d1dc: 492b ldr r1, [pc, #172] @ (800d28c ) 800d1de: 2007 movs r0, #7 800d1e0: f7fd f9c2 bl 800a568 response_code = RESP_SUCCESS; 800d1e4: 2312 movs r3, #18 800d1e6: 73fb strb r3, [r7, #15] break; 800d1e8: e035 b.n 800d256 } response_code = RESP_FAILED; 800d1ea: 2313 movs r3, #19 800d1ec: 73fb strb r3, [r7, #15] break; 800d1ee: e032 b.n 800d256 // memcpy(&PSU_TestMode, cmd->argument, sizeof(PSU_TestMode_t)); // log_printf(LOG_INFO, "Test PSU: %d %d %d\n", PSU_TestMode.enable, PSU_TestMode.voltage, PSU_TestMode.current); // response_code = RESP_SUCCESS; // break; // } response_code = RESP_FAILED; 800d1f0: 2313 movs r3, #19 800d1f2: 73fb strb r3, [r7, #15] break; 800d1f4: e02f b.n 800d256 case CMD_FIRE_ALARM: FireAlarm_Activate(); 800d1f6: f7fd fa35 bl 800a664 response_code = RESP_SUCCESS; 800d1fa: 2312 movs r3, #18 800d1fc: 73fb strb r3, [r7, #15] break; 800d1fe: e02a b.n 800d256 case CMD_DEVICE_RESET: // 2. Отправляем SUCCESS (хост может успеть получить его перед ребутом) SC_SendPacket(NULL, 0, RESP_SUCCESS); 800d200: 2212 movs r2, #18 800d202: 2100 movs r1, #0 800d204: 2000 movs r0, #0 800d206: f7ff fddb bl 800cdc0 while(huart2.gState == HAL_UART_STATE_BUSY_TX); // Ожидание завершения передачи 800d20a: bf00 nop 800d20c: 4b20 ldr r3, [pc, #128] @ (800d290 ) 800d20e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800d212: b2db uxtb r3, r3 800d214: 2b21 cmp r3, #33 @ 0x21 800d216: d0f9 beq.n 800d20c HAL_Delay(10); 800d218: 200a movs r0, #10 800d21a: f001 f8c3 bl 800e3a4 // 3. Выполняем программный сброс NVIC_SystemReset(); 800d21e: f7ff ff25 bl 800d06c <__NVIC_SystemReset> return; // Сюда код уже не дойдет, но для компилятора нxужно case CMD_ISOLATION_STATUS: if (cmd->argument_length == sizeof(IsolationStatusPacket_t)) { 800d222: 687b ldr r3, [r7, #4] 800d224: 785b ldrb r3, [r3, #1] 800d226: 2b09 cmp r3, #9 800d228: d10f bne.n 800d24a memcpy(&ISO, cmd->argument, sizeof(IsolationStatusPacket_t)); 800d22a: 687b ldr r3, [r7, #4] 800d22c: 685a ldr r2, [r3, #4] 800d22e: 4b19 ldr r3, [pc, #100] @ (800d294 ) 800d230: 6810 ldr r0, [r2, #0] 800d232: 6851 ldr r1, [r2, #4] 800d234: c303 stmia r3!, {r0, r1} 800d236: 7a12 ldrb r2, [r2, #8] 800d238: 701a strb r2, [r3, #0] // Для однонаправленного UART5 ответ не нужен if (g_sc_command_source == SC_SOURCE_UART5) { 800d23a: 4b17 ldr r3, [pc, #92] @ (800d298 ) 800d23c: 781b ldrb r3, [r3, #0] 800d23e: b2db uxtb r3, r3 800d240: 2b01 cmp r3, #1 800d242: d00f beq.n 800d264 return; } response_code = RESP_SUCCESS; 800d244: 2312 movs r3, #18 800d246: 73fb strb r3, [r7, #15] break; 800d248: e005 b.n 800d256 } response_code = RESP_FAILED; 800d24a: 2313 movs r3, #19 800d24c: 73fb strb r3, [r7, #15] break; 800d24e: e002 b.n 800d256 default: // Неизвестная команда response_code = RESP_FAILED; 800d250: 2313 movs r3, #19 800d252: 73fb strb r3, [r7, #15] break; 800d254: bf00 nop } // Отправляем финальный ответ (для команд без собственного ответа) SC_SendPacket(NULL, 0, response_code); 800d256: 7bfb ldrb r3, [r7, #15] 800d258: 461a mov r2, r3 800d25a: 2100 movs r1, #0 800d25c: 2000 movs r0, #0 800d25e: f7ff fdaf bl 800cdc0 800d262: e000 b.n 800d266 return; 800d264: bf00 nop } 800d266: 3710 adds r7, #16 800d268: 46bd mov sp, r7 800d26a: bd80 pop {r7, pc} 800d26c: 20001158 .word 0x20001158 800d270: 200011b0 .word 0x200011b0 800d274: 20000078 .word 0x20000078 800d278: 200011c0 .word 0x200011c0 800d27c: 0801791c .word 0x0801791c 800d280: 20000904 .word 0x20000904 800d284: 08017930 .word 0x08017930 800d288: 200003b0 .word 0x200003b0 800d28c: 08017944 .word 0x08017944 800d290: 200012e8 .word 0x200012e8 800d294: 2000006c .word 0x2000006c 800d298: 2000114c .word 0x2000114c 0800d29c : // Колбэк для заполнения данных мониторинга static void monitoring_data_callback(void) { 800d29c: b580 push {r7, lr} 800d29e: af00 add r7, sp, #0 // Информация о зарядной сессии statusPacket.SOC = CONN.SOC; 800d2a0: 4b8f ldr r3, [pc, #572] @ (800d4e0 ) 800d2a2: 789a ldrb r2, [r3, #2] 800d2a4: 4b8f ldr r3, [pc, #572] @ (800d4e4 ) 800d2a6: 709a strb r2, [r3, #2] statusPacket.Energy = CONN.Energy; 800d2a8: 4b8d ldr r3, [pc, #564] @ (800d4e0 ) 800d2aa: f8d3 3007 ldr.w r3, [r3, #7] 800d2ae: 4a8d ldr r2, [pc, #564] @ (800d4e4 ) 800d2b0: f8c2 3003 str.w r3, [r2, #3] statusPacket.RequestedVoltage = CONN.RequestedVoltage; 800d2b4: 4b8a ldr r3, [pc, #552] @ (800d4e0 ) 800d2b6: f8b3 300f ldrh.w r3, [r3, #15] 800d2ba: b29a uxth r2, r3 800d2bc: 4b89 ldr r3, [pc, #548] @ (800d4e4 ) 800d2be: f8a3 2007 strh.w r2, [r3, #7] statusPacket.RequestedCurrent = CONN.WantedCurrent; 800d2c2: 4b87 ldr r3, [pc, #540] @ (800d4e0 ) 800d2c4: f8b3 301b ldrh.w r3, [r3, #27] 800d2c8: b29a uxth r2, r3 800d2ca: 4b86 ldr r3, [pc, #536] @ (800d4e4 ) 800d2cc: f8a3 2009 strh.w r2, [r3, #9] statusPacket.MeasuredVoltage = CONN.MeasuredVoltage; 800d2d0: 4b83 ldr r3, [pc, #524] @ (800d4e0 ) 800d2d2: f8b3 3013 ldrh.w r3, [r3, #19] 800d2d6: b29a uxth r2, r3 800d2d8: 4b82 ldr r3, [pc, #520] @ (800d4e4 ) 800d2da: f8a3 200b strh.w r2, [r3, #11] statusPacket.MeasuredCurrent = CONN.MeasuredCurrent; 800d2de: 4b80 ldr r3, [pc, #512] @ (800d4e0 ) 800d2e0: f8b3 3015 ldrh.w r3, [r3, #21] 800d2e4: b29a uxth r2, r3 800d2e6: 4b7f ldr r3, [pc, #508] @ (800d4e4 ) 800d2e8: f8a3 200d strh.w r2, [r3, #13] statusPacket.outputEnabled = CONN.outputEnabled; 800d2ec: 4b7c ldr r3, [pc, #496] @ (800d4e0 ) 800d2ee: 7e1a ldrb r2, [r3, #24] 800d2f0: 4b7c ldr r3, [pc, #496] @ (800d4e4 ) 800d2f2: 73da strb r2, [r3, #15] statusPacket.chargingError = CONN.chargingError; 800d2f4: 4b7a ldr r3, [pc, #488] @ (800d4e0 ) 800d2f6: 7f5a ldrb r2, [r3, #29] 800d2f8: 4b7a ldr r3, [pc, #488] @ (800d4e4 ) 800d2fa: 705a strb r2, [r3, #1] statusPacket.connState = CONN.connState; 800d2fc: 4b78 ldr r3, [pc, #480] @ (800d4e0 ) 800d2fe: 785a ldrb r2, [r3, #1] 800d300: 4b78 ldr r3, [pc, #480] @ (800d4e4 ) 800d302: 701a strb r2, [r3, #0] statusPacket.chargingElapsedTimeMin = 0; 800d304: 4b77 ldr r3, [pc, #476] @ (800d4e4 ) 800d306: 2200 movs r2, #0 800d308: 741a strb r2, [r3, #16] 800d30a: 2200 movs r2, #0 800d30c: 745a strb r2, [r3, #17] statusPacket.chargingElapsedTimeSec = 0; 800d30e: 4b75 ldr r3, [pc, #468] @ (800d4e4 ) 800d310: 2200 movs r2, #0 800d312: 749a strb r2, [r3, #18] statusPacket.estimatedRemainingChargingTime = 0; 800d314: 4b73 ldr r3, [pc, #460] @ (800d4e4 ) 800d316: 2200 movs r2, #0 800d318: 74da strb r2, [r3, #19] 800d31a: 2200 movs r2, #0 800d31c: 751a strb r2, [r3, #20] // состояние зарядной станции statusPacket.relayAC = RELAY_Read(RELAY_AC); 800d31e: 2004 movs r0, #4 800d320: f7fc faba bl 8009898 800d324: 4603 mov r3, r0 800d326: f003 0301 and.w r3, r3, #1 800d32a: b2d9 uxtb r1, r3 800d32c: 4a6d ldr r2, [pc, #436] @ (800d4e4 ) 800d32e: 7d53 ldrb r3, [r2, #21] 800d330: f361 0300 bfi r3, r1, #0, #1 800d334: 7553 strb r3, [r2, #21] statusPacket.relayDC = RELAY_Read(RELAY_DC); 800d336: 2003 movs r0, #3 800d338: f7fc faae bl 8009898 800d33c: 4603 mov r3, r0 800d33e: f003 0301 and.w r3, r3, #1 800d342: b2d9 uxtb r1, r3 800d344: 4a67 ldr r2, [pc, #412] @ (800d4e4 ) 800d346: 7d53 ldrb r3, [r2, #21] 800d348: f361 0341 bfi r3, r1, #1, #1 800d34c: 7553 strb r3, [r2, #21] statusPacket.relayAUX = RELAY_Read(RELAY_AUX0); 800d34e: 2000 movs r0, #0 800d350: f7fc faa2 bl 8009898 800d354: 4603 mov r3, r0 800d356: f003 0301 and.w r3, r3, #1 800d35a: b2d9 uxtb r1, r3 800d35c: 4a61 ldr r2, [pc, #388] @ (800d4e4 ) 800d35e: 7d53 ldrb r3, [r2, #21] 800d360: f361 0382 bfi r3, r1, #2, #1 800d364: 7553 strb r3, [r2, #21] statusPacket.lockState = 0; 800d366: 4a5f ldr r2, [pc, #380] @ (800d4e4 ) 800d368: 7d53 ldrb r3, [r2, #21] 800d36a: f023 0308 bic.w r3, r3, #8 800d36e: 7553 strb r3, [r2, #21] statusPacket.stopButton = !IN_ReadInput(IN_ESTOP); 800d370: 2003 movs r0, #3 800d372: f7fc faa1 bl 80098b8 800d376: 4603 mov r3, r0 800d378: 2b00 cmp r3, #0 800d37a: bf0c ite eq 800d37c: 2301 moveq r3, #1 800d37e: 2300 movne r3, #0 800d380: b2d9 uxtb r1, r3 800d382: 4a58 ldr r2, [pc, #352] @ (800d4e4 ) 800d384: 7d53 ldrb r3, [r2, #21] 800d386: f361 1304 bfi r3, r1, #4, #1 800d38a: 7553 strb r3, [r2, #21] statusPacket.logAvailable = (debug_buffer_available()>0)?1:0; 800d38c: f7fd f876 bl 800a47c 800d390: 4603 mov r3, r0 800d392: 2b00 cmp r3, #0 800d394: bf14 ite ne 800d396: 2301 movne r3, #1 800d398: 2300 moveq r3, #0 800d39a: b2d9 uxtb r1, r3 800d39c: 4a51 ldr r2, [pc, #324] @ (800d4e4 ) 800d39e: 7d53 ldrb r3, [r2, #21] 800d3a0: f361 1345 bfi r3, r1, #5, #1 800d3a4: 7553 strb r3, [r2, #21] statusPacket.evInfoAvailable = 0; 800d3a6: 4a4f ldr r2, [pc, #316] @ (800d4e4 ) 800d3a8: 7d53 ldrb r3, [r2, #21] 800d3aa: f023 0340 bic.w r3, r3, #64 @ 0x40 800d3ae: 7553 strb r3, [r2, #21] statusPacket.psuOnline = PSU0.online; 800d3b0: 4b4d ldr r3, [pc, #308] @ (800d4e8 ) 800d3b2: 7a1b ldrb r3, [r3, #8] 800d3b4: f003 0301 and.w r3, r3, #1 800d3b8: b2d9 uxtb r1, r3 800d3ba: 4a4a ldr r2, [pc, #296] @ (800d4e4 ) 800d3bc: 7d53 ldrb r3, [r2, #21] 800d3be: f361 13c7 bfi r3, r1, #7, #1 800d3c2: 7553 strb r3, [r2, #21] statusPacket.tempConnector0 = CONN_ReadTemp(0); // температура коннектора 800d3c4: 2000 movs r0, #0 800d3c6: f7fc fb9d bl 8009b04 800d3ca: 4603 mov r3, r0 800d3cc: b25a sxtb r2, r3 800d3ce: 4b45 ldr r3, [pc, #276] @ (800d4e4 ) 800d3d0: 765a strb r2, [r3, #25] statusPacket.tempConnector1 = CONN_ReadTemp(1); 800d3d2: 2001 movs r0, #1 800d3d4: f7fc fb96 bl 8009b04 800d3d8: 4603 mov r3, r0 800d3da: b25a sxtb r2, r3 800d3dc: 4b41 ldr r3, [pc, #260] @ (800d4e4 ) 800d3de: 769a strb r2, [r3, #26] statusPacket.tempAmbient = PSU0.tempAmbient; // температура окружающего воздуха 800d3e0: 4b41 ldr r3, [pc, #260] @ (800d4e8 ) 800d3e2: 6a1b ldr r3, [r3, #32] 800d3e4: b25a sxtb r2, r3 800d3e6: 4b3f ldr r3, [pc, #252] @ (800d4e4 ) 800d3e8: 76da strb r2, [r3, #27] statusPacket.tempBatteryMax = 0; 800d3ea: 4b3e ldr r3, [pc, #248] @ (800d4e4 ) 800d3ec: 2200 movs r2, #0 800d3ee: 771a strb r2, [r3, #28] statusPacket.tempBatteryMin = 0; 800d3f0: 4b3c ldr r3, [pc, #240] @ (800d4e4 ) 800d3f2: 2200 movs r2, #0 800d3f4: 775a strb r2, [r3, #29] statusPacket.highestVoltageOfBatteryCell = 0; 800d3f6: 4b3b ldr r3, [pc, #236] @ (800d4e4 ) 800d3f8: 2200 movs r2, #0 800d3fa: 779a strb r2, [r3, #30] 800d3fc: 2200 movs r2, #0 800d3fe: 77da strb r2, [r3, #31] statusPacket.batteryStatus = 0; 800d400: 4b38 ldr r3, [pc, #224] @ (800d4e4 ) 800d402: 2200 movs r2, #0 800d404: f883 2020 strb.w r2, [r3, #32] statusPacket.phaseVoltageAB = PSU_06.VAB; 800d408: 4b38 ldr r3, [pc, #224] @ (800d4ec ) 800d40a: 689b ldr r3, [r3, #8] 800d40c: b29a uxth r2, r3 800d40e: 4b35 ldr r3, [pc, #212] @ (800d4e4 ) 800d410: f8a3 2021 strh.w r2, [r3, #33] @ 0x21 statusPacket.phaseVoltageBC = PSU_06.VBC; 800d414: 4b35 ldr r3, [pc, #212] @ (800d4ec ) 800d416: 68db ldr r3, [r3, #12] 800d418: b29a uxth r2, r3 800d41a: 4b32 ldr r3, [pc, #200] @ (800d4e4 ) 800d41c: f8a3 2023 strh.w r2, [r3, #35] @ 0x23 statusPacket.phaseVoltageCA = PSU_06.VCA; 800d420: 4b32 ldr r3, [pc, #200] @ (800d4ec ) 800d422: 691b ldr r3, [r3, #16] 800d424: b29a uxth r2, r3 800d426: 4b2f ldr r3, [pc, #188] @ (800d4e4 ) 800d428: f8a3 2025 strh.w r2, [r3, #37] @ 0x25 // GBT TODO memset(statusPacket.VIN, 0, sizeof(statusPacket.VIN)); 800d42c: 2211 movs r2, #17 800d42e: 2100 movs r1, #0 800d430: 482f ldr r0, [pc, #188] @ (800d4f0 ) 800d432: f007 fc67 bl 8014d04 // GBT TODO statusPacket.batteryType = 0; 800d436: 4b2b ldr r3, [pc, #172] @ (800d4e4 ) 800d438: 2200 movs r2, #0 800d43a: f883 2038 strb.w r2, [r3, #56] @ 0x38 statusPacket.batteryCapacity = 0; 800d43e: 4b29 ldr r3, [pc, #164] @ (800d4e4 ) 800d440: 2200 movs r2, #0 800d442: f883 2039 strb.w r2, [r3, #57] @ 0x39 800d446: 2200 movs r2, #0 800d448: f883 203a strb.w r2, [r3, #58] @ 0x3a statusPacket.batteryVoltage = 0; 800d44c: 4b25 ldr r3, [pc, #148] @ (800d4e4 ) 800d44e: 2200 movs r2, #0 800d450: f883 203b strb.w r2, [r3, #59] @ 0x3b 800d454: 2200 movs r2, #0 800d456: f883 203c strb.w r2, [r3, #60] @ 0x3c memset(statusPacket.batteryVendor, 0, sizeof(statusPacket.batteryVendor)); 800d45a: 2204 movs r2, #4 800d45c: 2100 movs r1, #0 800d45e: 4825 ldr r0, [pc, #148] @ (800d4f4 ) 800d460: f007 fc50 bl 8014d04 statusPacket.batterySN = 0; 800d464: 4b1f ldr r3, [pc, #124] @ (800d4e4 ) 800d466: 2200 movs r2, #0 800d468: f883 2041 strb.w r2, [r3, #65] @ 0x41 800d46c: 2200 movs r2, #0 800d46e: f883 2042 strb.w r2, [r3, #66] @ 0x42 800d472: 2200 movs r2, #0 800d474: f883 2043 strb.w r2, [r3, #67] @ 0x43 800d478: 2200 movs r2, #0 800d47a: f883 2044 strb.w r2, [r3, #68] @ 0x44 statusPacket.batteryManuD = 0; 800d47e: 4b19 ldr r3, [pc, #100] @ (800d4e4 ) 800d480: 2200 movs r2, #0 800d482: f883 2047 strb.w r2, [r3, #71] @ 0x47 statusPacket.batteryManuM = 0; 800d486: 4b17 ldr r3, [pc, #92] @ (800d4e4 ) 800d488: 2200 movs r2, #0 800d48a: f883 2046 strb.w r2, [r3, #70] @ 0x46 statusPacket.batteryManuY = 0; 800d48e: 4b15 ldr r3, [pc, #84] @ (800d4e4 ) 800d490: 2200 movs r2, #0 800d492: f883 2045 strb.w r2, [r3, #69] @ 0x45 statusPacket.batteryCycleCount = 0; 800d496: 4b13 ldr r3, [pc, #76] @ (800d4e4 ) 800d498: 2200 movs r2, #0 800d49a: f883 2048 strb.w r2, [r3, #72] @ 0x48 800d49e: 2200 movs r2, #0 800d4a0: f883 2049 strb.w r2, [r3, #73] @ 0x49 statusPacket.ownAuto = 0; 800d4a4: 4b0f ldr r3, [pc, #60] @ (800d4e4 ) 800d4a6: 2200 movs r2, #0 800d4a8: f883 204a strb.w r2, [r3, #74] @ 0x4a memset(statusPacket.EV_SW_VER, 0, sizeof(statusPacket.EV_SW_VER)); 800d4ac: 2208 movs r2, #8 800d4ae: 2100 movs r1, #0 800d4b0: 4811 ldr r0, [pc, #68] @ (800d4f8 ) 800d4b2: f007 fc27 bl 8014d04 statusPacket.testMode = 0; 800d4b6: 4b0b ldr r3, [pc, #44] @ (800d4e4 ) 800d4b8: 2200 movs r2, #0 800d4ba: f883 2053 strb.w r2, [r3, #83] @ 0x53 statusPacket.testVoltage = 0; 800d4be: 4b09 ldr r3, [pc, #36] @ (800d4e4 ) 800d4c0: 2200 movs r2, #0 800d4c2: f883 2054 strb.w r2, [r3, #84] @ 0x54 800d4c6: 2200 movs r2, #0 800d4c8: f883 2055 strb.w r2, [r3, #85] @ 0x55 statusPacket.testCurrent = 0; 800d4cc: 4b05 ldr r3, [pc, #20] @ (800d4e4 ) 800d4ce: 2200 movs r2, #0 800d4d0: f883 2056 strb.w r2, [r3, #86] @ 0x56 800d4d4: 2200 movs r2, #0 800d4d6: f883 2057 strb.w r2, [r3, #87] @ 0x57 // В debug.c есть CONN_SetState, предполагаем наличие CONN_GetState() // Если такой функции нет, закомментируйте следующую строку: // statusPacket.connState = CONN_GetState(); } 800d4da: bf00 nop 800d4dc: bd80 pop {r7, pc} 800d4de: bf00 nop 800d4e0: 200003b0 .word 0x200003b0 800d4e4: 20001158 .word 0x20001158 800d4e8: 20000904 .word 0x20000904 800d4ec: 200008d8 .word 0x200008d8 800d4f0: 2000117f .word 0x2000117f 800d4f4: 20001195 .word 0x20001195 800d4f8: 200011a3 .word 0x200011a3 0800d4fc : #include "sma_filter.h" void SMAFilter_Init(SMAFilter_t* f) { 800d4fc: b480 push {r7} 800d4fe: b085 sub sp, #20 800d500: af00 add r7, sp, #0 800d502: 6078 str r0, [r7, #4] if (f == 0) return; 800d504: 687b ldr r3, [r7, #4] 800d506: 2b00 cmp r3, #0 800d508: d018 beq.n 800d53c f->sum = 0; 800d50a: 687b ldr r3, [r7, #4] 800d50c: 2200 movs r2, #0 800d50e: 601a str r2, [r3, #0] f->idx = 0; 800d510: 687b ldr r3, [r7, #4] 800d512: 2200 movs r2, #0 800d514: 809a strh r2, [r3, #4] f->count = 0; 800d516: 687b ldr r3, [r7, #4] 800d518: 2200 movs r2, #0 800d51a: 80da strh r2, [r3, #6] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800d51c: 2300 movs r3, #0 800d51e: 81fb strh r3, [r7, #14] 800d520: e008 b.n 800d534 f->buffer[i] = 0; 800d522: 89fa ldrh r2, [r7, #14] 800d524: 687b ldr r3, [r7, #4] 800d526: 3202 adds r2, #2 800d528: 2100 movs r1, #0 800d52a: f843 1022 str.w r1, [r3, r2, lsl #2] for (uint16_t i = 0; i < SMA_FILTER_WINDOW; i++) { 800d52e: 89fb ldrh r3, [r7, #14] 800d530: 3301 adds r3, #1 800d532: 81fb strh r3, [r7, #14] 800d534: 89fb ldrh r3, [r7, #14] 800d536: 2b07 cmp r3, #7 800d538: d9f3 bls.n 800d522 800d53a: e000 b.n 800d53e if (f == 0) return; 800d53c: bf00 nop } } 800d53e: 3714 adds r7, #20 800d540: 46bd mov sp, r7 800d542: bc80 pop {r7} 800d544: 4770 bx lr 0800d546 : int32_t SMAFilter_Update(SMAFilter_t* f, int32_t x) { 800d546: b480 push {r7} 800d548: b085 sub sp, #20 800d54a: af00 add r7, sp, #0 800d54c: 6078 str r0, [r7, #4] 800d54e: 6039 str r1, [r7, #0] if (f == 0) return x; 800d550: 687b ldr r3, [r7, #4] 800d552: 2b00 cmp r3, #0 800d554: d101 bne.n 800d55a 800d556: 683b ldr r3, [r7, #0] 800d558: e056 b.n 800d608 // Пока окно не заполнено полностью, делим по фактическому count. if (f->count < SMA_FILTER_WINDOW) { 800d55a: 687b ldr r3, [r7, #4] 800d55c: 88db ldrh r3, [r3, #6] 800d55e: 2b07 cmp r3, #7 800d560: d827 bhi.n 800d5b2 f->buffer[f->idx] = x; 800d562: 687b ldr r3, [r7, #4] 800d564: 889b ldrh r3, [r3, #4] 800d566: 461a mov r2, r3 800d568: 687b ldr r3, [r7, #4] 800d56a: 3202 adds r2, #2 800d56c: 6839 ldr r1, [r7, #0] 800d56e: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += x; 800d572: 687b ldr r3, [r7, #4] 800d574: 681a ldr r2, [r3, #0] 800d576: 683b ldr r3, [r7, #0] 800d578: 441a add r2, r3 800d57a: 687b ldr r3, [r7, #4] 800d57c: 601a str r2, [r3, #0] f->idx++; 800d57e: 687b ldr r3, [r7, #4] 800d580: 889b ldrh r3, [r3, #4] 800d582: 3301 adds r3, #1 800d584: b29a uxth r2, r3 800d586: 687b ldr r3, [r7, #4] 800d588: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800d58a: 687b ldr r3, [r7, #4] 800d58c: 889b ldrh r3, [r3, #4] 800d58e: 2b07 cmp r3, #7 800d590: d902 bls.n 800d598 800d592: 687b ldr r3, [r7, #4] 800d594: 2200 movs r2, #0 800d596: 809a strh r2, [r3, #4] f->count++; 800d598: 687b ldr r3, [r7, #4] 800d59a: 88db ldrh r3, [r3, #6] 800d59c: 3301 adds r3, #1 800d59e: b29a uxth r2, r3 800d5a0: 687b ldr r3, [r7, #4] 800d5a2: 80da strh r2, [r3, #6] return (int32_t)(f->sum / (int32_t)f->count); 800d5a4: 687b ldr r3, [r7, #4] 800d5a6: 681b ldr r3, [r3, #0] 800d5a8: 687a ldr r2, [r7, #4] 800d5aa: 88d2 ldrh r2, [r2, #6] 800d5ac: fb93 f3f2 sdiv r3, r3, r2 800d5b0: e02a b.n 800d608 } // Окно заполнено: "вычитаем старое + добавляем новое". int32_t old = f->buffer[f->idx]; 800d5b2: 687b ldr r3, [r7, #4] 800d5b4: 889b ldrh r3, [r3, #4] 800d5b6: 461a mov r2, r3 800d5b8: 687b ldr r3, [r7, #4] 800d5ba: 3202 adds r2, #2 800d5bc: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800d5c0: 60fb str r3, [r7, #12] f->buffer[f->idx] = x; 800d5c2: 687b ldr r3, [r7, #4] 800d5c4: 889b ldrh r3, [r3, #4] 800d5c6: 461a mov r2, r3 800d5c8: 687b ldr r3, [r7, #4] 800d5ca: 3202 adds r2, #2 800d5cc: 6839 ldr r1, [r7, #0] 800d5ce: f843 1022 str.w r1, [r3, r2, lsl #2] f->sum += (x - old); 800d5d2: 687b ldr r3, [r7, #4] 800d5d4: 681a ldr r2, [r3, #0] 800d5d6: 6839 ldr r1, [r7, #0] 800d5d8: 68fb ldr r3, [r7, #12] 800d5da: 1acb subs r3, r1, r3 800d5dc: 441a add r2, r3 800d5de: 687b ldr r3, [r7, #4] 800d5e0: 601a str r2, [r3, #0] f->idx++; 800d5e2: 687b ldr r3, [r7, #4] 800d5e4: 889b ldrh r3, [r3, #4] 800d5e6: 3301 adds r3, #1 800d5e8: b29a uxth r2, r3 800d5ea: 687b ldr r3, [r7, #4] 800d5ec: 809a strh r2, [r3, #4] if (f->idx >= SMA_FILTER_WINDOW) f->idx = 0; 800d5ee: 687b ldr r3, [r7, #4] 800d5f0: 889b ldrh r3, [r3, #4] 800d5f2: 2b07 cmp r3, #7 800d5f4: d902 bls.n 800d5fc 800d5f6: 687b ldr r3, [r7, #4] 800d5f8: 2200 movs r2, #0 800d5fa: 809a strh r2, [r3, #4] return (int32_t)(f->sum / (int32_t)SMA_FILTER_WINDOW); 800d5fc: 687b ldr r3, [r7, #4] 800d5fe: 681b ldr r3, [r3, #0] 800d600: 2b00 cmp r3, #0 800d602: da00 bge.n 800d606 800d604: 3307 adds r3, #7 800d606: 10db asrs r3, r3, #3 } 800d608: 4618 mov r0, r3 800d60a: 3714 adds r7, #20 800d60c: 46bd mov sp, r7 800d60e: bc80 pop {r7} 800d610: 4770 bx lr ... 0800d614 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800d614: b480 push {r7} 800d616: b085 sub sp, #20 800d618: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 800d61a: 4b15 ldr r3, [pc, #84] @ (800d670 ) 800d61c: 699b ldr r3, [r3, #24] 800d61e: 4a14 ldr r2, [pc, #80] @ (800d670 ) 800d620: f043 0301 orr.w r3, r3, #1 800d624: 6193 str r3, [r2, #24] 800d626: 4b12 ldr r3, [pc, #72] @ (800d670 ) 800d628: 699b ldr r3, [r3, #24] 800d62a: f003 0301 and.w r3, r3, #1 800d62e: 60bb str r3, [r7, #8] 800d630: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800d632: 4b0f ldr r3, [pc, #60] @ (800d670 ) 800d634: 69db ldr r3, [r3, #28] 800d636: 4a0e ldr r2, [pc, #56] @ (800d670 ) 800d638: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800d63c: 61d3 str r3, [r2, #28] 800d63e: 4b0c ldr r3, [pc, #48] @ (800d670 ) 800d640: 69db ldr r3, [r3, #28] 800d642: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800d646: 607b str r3, [r7, #4] 800d648: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 800d64a: 4b0a ldr r3, [pc, #40] @ (800d674 ) 800d64c: 685b ldr r3, [r3, #4] 800d64e: 60fb str r3, [r7, #12] 800d650: 68fb ldr r3, [r7, #12] 800d652: f023 63e0 bic.w r3, r3, #117440512 @ 0x7000000 800d656: 60fb str r3, [r7, #12] 800d658: 68fb ldr r3, [r7, #12] 800d65a: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 800d65e: 60fb str r3, [r7, #12] 800d660: 4a04 ldr r2, [pc, #16] @ (800d674 ) 800d662: 68fb ldr r3, [r7, #12] 800d664: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800d666: bf00 nop 800d668: 3714 adds r7, #20 800d66a: 46bd mov sp, r7 800d66c: bc80 pop {r7} 800d66e: 4770 bx lr 800d670: 40021000 .word 0x40021000 800d674: 40010000 .word 0x40010000 0800d678 : { /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800d678: e7fe b.n 800d678 800d67a: bf00 nop 0800d67c : void HardFault_Handler(void) { /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800d67c: e7fe b.n 800d67c 800d67e: bf00 nop 0800d680 : void MemManage_Handler(void) { /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800d680: e7fe b.n 800d680 800d682: bf00 nop 0800d684 : void BusFault_Handler(void) { /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800d684: e7fe b.n 800d684 800d686: bf00 nop 0800d688 : void UsageFault_Handler(void) { /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 800d688: e7fe b.n 800d688 800d68a: bf00 nop 0800d68c : /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800d68c: 4770 bx lr 800d68e: bf00 nop 0800d690 : /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800d690: 4770 bx lr 800d692: bf00 nop 0800d694 : /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800d694: 4770 bx lr 800d696: bf00 nop 0800d698 : void SysTick_Handler(void) { /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800d698: f000 be68 b.w 800e36c 0800d69c : /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { 800d69c: b510 push {r4, lr} /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_SET); 800d69e: 4c09 ldr r4, [pc, #36] @ (800d6c4 ) 800d6a0: 2201 movs r2, #1 800d6a2: f44f 6100 mov.w r1, #2048 @ 0x800 800d6a6: 4620 mov r0, r4 800d6a8: f003 fa09 bl 8010abe /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 800d6ac: 4806 ldr r0, [pc, #24] @ (800d6c8 ) 800d6ae: f002 fdf7 bl 80102a0 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d6b2: 4620 mov r0, r4 /* USER CODE END DMA1_Channel1_IRQn 1 */ } 800d6b4: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d6b8: 2200 movs r2, #0 800d6ba: f44f 6100 mov.w r1, #2048 @ 0x800 800d6be: f003 b9fe b.w 8010abe 800d6c2: bf00 nop 800d6c4: 40010c00 .word 0x40010c00 800d6c8: 200002c0 .word 0x200002c0 0800d6cc : void DMA1_Channel2_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ /* USER CODE END DMA1_Channel2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart3_tx); 800d6cc: 4801 ldr r0, [pc, #4] @ (800d6d4 ) 800d6ce: f002 bde7 b.w 80102a0 800d6d2: bf00 nop 800d6d4: 20001444 .word 0x20001444 0800d6d8 : void DMA1_Channel3_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel3_IRQn 0 */ /* USER CODE END DMA1_Channel3_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart3_rx); 800d6d8: 4801 ldr r0, [pc, #4] @ (800d6e0 ) 800d6da: f002 bde1 b.w 80102a0 800d6de: bf00 nop 800d6e0: 20001400 .word 0x20001400 0800d6e4 : void DMA1_Channel6_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel6_IRQn 0 */ /* USER CODE END DMA1_Channel6_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_rx); 800d6e4: 4801 ldr r0, [pc, #4] @ (800d6ec ) 800d6e6: f002 bddb b.w 80102a0 800d6ea: bf00 nop 800d6ec: 20001378 .word 0x20001378 0800d6f0 : void DMA1_Channel7_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel7_IRQn 0 */ /* USER CODE END DMA1_Channel7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_tx); 800d6f0: 4801 ldr r0, [pc, #4] @ (800d6f8 ) 800d6f2: f002 bdd5 b.w 80102a0 800d6f6: bf00 nop 800d6f8: 200013bc .word 0x200013bc 0800d6fc : /** * @brief This function handles ADC1 and ADC2 global interrupts. */ void ADC1_2_IRQHandler(void) { 800d6fc: b510 push {r4, lr} /* USER CODE BEGIN ADC1_2_IRQn 0 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_SET); 800d6fe: 4c09 ldr r4, [pc, #36] @ (800d724 ) 800d700: 2201 movs r2, #1 800d702: f44f 6100 mov.w r1, #2048 @ 0x800 800d706: 4620 mov r0, r4 800d708: f003 f9d9 bl 8010abe /* USER CODE END ADC1_2_IRQn 0 */ HAL_ADC_IRQHandler(&hadc1); 800d70c: 4806 ldr r0, [pc, #24] @ (800d728 ) 800d70e: f001 f823 bl 800e758 /* USER CODE BEGIN ADC1_2_IRQn 1 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d712: 4620 mov r0, r4 /* USER CODE END ADC1_2_IRQn 1 */ } 800d714: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d718: 2200 movs r2, #0 800d71a: f44f 6100 mov.w r1, #2048 @ 0x800 800d71e: f003 b9ce b.w 8010abe 800d722: bf00 nop 800d724: 40010c00 .word 0x40010c00 800d728: 20000290 .word 0x20000290 0800d72c : /** * @brief This function handles CAN1 RX0 interrupt. */ void CAN1_RX0_IRQHandler(void) { 800d72c: b510 push {r4, lr} /* USER CODE BEGIN CAN1_RX0_IRQn 0 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_SET); 800d72e: 4c09 ldr r4, [pc, #36] @ (800d754 ) 800d730: 2201 movs r2, #1 800d732: f44f 6180 mov.w r1, #1024 @ 0x400 800d736: 4620 mov r0, r4 800d738: f003 f9c1 bl 8010abe /* USER CODE END CAN1_RX0_IRQn 0 */ HAL_CAN_IRQHandler(&hcan1); 800d73c: 4806 ldr r0, [pc, #24] @ (800d758 ) 800d73e: f002 f847 bl 800f7d0 /* USER CODE BEGIN CAN1_RX0_IRQn 1 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d742: 4620 mov r0, r4 /* USER CODE END CAN1_RX0_IRQn 1 */ } 800d744: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d748: 2200 movs r2, #0 800d74a: f44f 6180 mov.w r1, #1024 @ 0x400 800d74e: f003 b9b6 b.w 8010abe 800d752: bf00 nop 800d754: 40010c00 .word 0x40010c00 800d758: 2000035c .word 0x2000035c 0800d75c : /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 800d75c: b510 push {r4, lr} /* USER CODE BEGIN TIM3_IRQn 0 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_SET); 800d75e: 4c09 ldr r4, [pc, #36] @ (800d784 ) 800d760: 2201 movs r2, #1 800d762: f44f 6100 mov.w r1, #2048 @ 0x800 800d766: 4620 mov r0, r4 800d768: f003 f9a9 bl 8010abe /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); 800d76c: 4806 ldr r0, [pc, #24] @ (800d788 ) 800d76e: f004 fd87 bl 8012280 /* USER CODE BEGIN TIM3_IRQn 1 */ HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d772: 4620 mov r0, r4 /* USER CODE END TIM3_IRQn 1 */ } 800d774: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG4_GPIO_Port, DBG4_Pin, GPIO_PIN_RESET); 800d778: 2200 movs r2, #0 800d77a: f44f 6100 mov.w r1, #2048 @ 0x800 800d77e: f003 b99e b.w 8010abe 800d782: bf00 nop 800d784: 40010c00 .word 0x40010c00 800d788: 200011c8 .word 0x200011c8 0800d78c : void USART1_IRQHandler(void) { /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 800d78c: 4801 ldr r0, [pc, #4] @ (800d794 ) 800d78e: f005 be2d b.w 80133ec 800d792: bf00 nop 800d794: 200012a0 .word 0x200012a0 0800d798 : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 800d798: b510 push {r4, lr} /* USER CODE BEGIN USART2_IRQn 0 */ HAL_GPIO_WritePin(DBG2_GPIO_Port, DBG2_Pin, GPIO_PIN_SET); 800d79a: 4c08 ldr r4, [pc, #32] @ (800d7bc ) 800d79c: 2201 movs r2, #1 800d79e: 2120 movs r1, #32 800d7a0: 4620 mov r0, r4 800d7a2: f003 f98c bl 8010abe /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 800d7a6: 4806 ldr r0, [pc, #24] @ (800d7c0 ) 800d7a8: f005 fe20 bl 80133ec /* USER CODE BEGIN USART2_IRQn 1 */ HAL_GPIO_WritePin(DBG2_GPIO_Port, DBG2_Pin, GPIO_PIN_RESET); 800d7ac: 4620 mov r0, r4 /* USER CODE END USART2_IRQn 1 */ } 800d7ae: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG2_GPIO_Port, DBG2_Pin, GPIO_PIN_RESET); 800d7b2: 2200 movs r2, #0 800d7b4: 2120 movs r1, #32 800d7b6: f003 b982 b.w 8010abe 800d7ba: bf00 nop 800d7bc: 40010800 .word 0x40010800 800d7c0: 200012e8 .word 0x200012e8 0800d7c4 : /** * @brief This function handles USART3 global interrupt. */ void USART3_IRQHandler(void) { 800d7c4: b510 push {r4, lr} /* USER CODE BEGIN USART3_IRQn 0 */ HAL_GPIO_WritePin(DBG3_GPIO_Port, DBG3_Pin, GPIO_PIN_SET); 800d7c6: 4c08 ldr r4, [pc, #32] @ (800d7e8 ) 800d7c8: 2201 movs r2, #1 800d7ca: 2140 movs r1, #64 @ 0x40 800d7cc: 4620 mov r0, r4 800d7ce: f003 f976 bl 8010abe /* USER CODE END USART3_IRQn 0 */ HAL_UART_IRQHandler(&huart3); 800d7d2: 4806 ldr r0, [pc, #24] @ (800d7ec ) 800d7d4: f005 fe0a bl 80133ec /* USER CODE BEGIN USART3_IRQn 1 */ HAL_GPIO_WritePin(DBG3_GPIO_Port, DBG3_Pin, GPIO_PIN_RESET); 800d7d8: 4620 mov r0, r4 /* USER CODE END USART3_IRQn 1 */ } 800d7da: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG3_GPIO_Port, DBG3_Pin, GPIO_PIN_RESET); 800d7de: 2200 movs r2, #0 800d7e0: 2140 movs r1, #64 @ 0x40 800d7e2: f003 b96c b.w 8010abe 800d7e6: bf00 nop 800d7e8: 40010800 .word 0x40010800 800d7ec: 20001330 .word 0x20001330 0800d7f0 : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 800d7f0: b510 push {r4, lr} /* USER CODE BEGIN UART5_IRQn 0 */ HAL_GPIO_WritePin(DBG1_GPIO_Port, DBG1_Pin, GPIO_PIN_SET); 800d7f2: 4c08 ldr r4, [pc, #32] @ (800d814 ) 800d7f4: 2201 movs r2, #1 800d7f6: 2104 movs r1, #4 800d7f8: 4620 mov r0, r4 800d7fa: f003 f960 bl 8010abe /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 800d7fe: 4806 ldr r0, [pc, #24] @ (800d818 ) 800d800: f005 fdf4 bl 80133ec /* USER CODE BEGIN UART5_IRQn 1 */ HAL_GPIO_WritePin(DBG1_GPIO_Port, DBG1_Pin, GPIO_PIN_RESET); 800d804: 4620 mov r0, r4 /* USER CODE END UART5_IRQn 1 */ } 800d806: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG1_GPIO_Port, DBG1_Pin, GPIO_PIN_RESET); 800d80a: 2200 movs r2, #0 800d80c: 2104 movs r1, #4 800d80e: f003 b956 b.w 8010abe 800d812: bf00 nop 800d814: 40011000 .word 0x40011000 800d818: 20001258 .word 0x20001258 0800d81c : /** * @brief This function handles CAN2 TX interrupt. */ void CAN2_TX_IRQHandler(void) { 800d81c: b510 push {r4, lr} /* USER CODE BEGIN CAN2_TX_IRQn 0 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_SET); 800d81e: 4c09 ldr r4, [pc, #36] @ (800d844 ) 800d820: 2201 movs r2, #1 800d822: f44f 6180 mov.w r1, #1024 @ 0x400 800d826: 4620 mov r0, r4 800d828: f003 f949 bl 8010abe /* USER CODE END CAN2_TX_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800d82c: 4806 ldr r0, [pc, #24] @ (800d848 ) 800d82e: f001 ffcf bl 800f7d0 /* USER CODE BEGIN CAN2_TX_IRQn 1 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d832: 4620 mov r0, r4 /* USER CODE END CAN2_TX_IRQn 1 */ } 800d834: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d838: 2200 movs r2, #0 800d83a: f44f 6180 mov.w r1, #1024 @ 0x400 800d83e: f003 b93e b.w 8010abe 800d842: bf00 nop 800d844: 40010c00 .word 0x40010c00 800d848: 20000384 .word 0x20000384 0800d84c : /** * @brief This function handles CAN2 RX1 interrupt. */ void CAN2_RX1_IRQHandler(void) { 800d84c: b510 push {r4, lr} /* USER CODE BEGIN CAN2_RX1_IRQn 0 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_SET); 800d84e: 4c09 ldr r4, [pc, #36] @ (800d874 ) 800d850: 2201 movs r2, #1 800d852: f44f 6180 mov.w r1, #1024 @ 0x400 800d856: 4620 mov r0, r4 800d858: f003 f931 bl 8010abe /* USER CODE END CAN2_RX1_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 800d85c: 4806 ldr r0, [pc, #24] @ (800d878 ) 800d85e: f001 ffb7 bl 800f7d0 /* USER CODE BEGIN CAN2_RX1_IRQn 1 */ HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d862: 4620 mov r0, r4 /* USER CODE END CAN2_RX1_IRQn 1 */ } 800d864: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(DBG5_GPIO_Port, DBG5_Pin, GPIO_PIN_RESET); 800d868: 2200 movs r2, #0 800d86a: f44f 6180 mov.w r1, #1024 @ 0x400 800d86e: f003 b926 b.w 8010abe 800d872: bf00 nop 800d874: 40010c00 .word 0x40010c00 800d878: 20000384 .word 0x20000384 0800d87c <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 800d87c: b480 push {r7} 800d87e: af00 add r7, sp, #0 return 1; 800d880: 2301 movs r3, #1 } 800d882: 4618 mov r0, r3 800d884: 46bd mov sp, r7 800d886: bc80 pop {r7} 800d888: 4770 bx lr 0800d88a <_kill>: int _kill(int pid, int sig) { 800d88a: b580 push {r7, lr} 800d88c: b082 sub sp, #8 800d88e: af00 add r7, sp, #0 800d890: 6078 str r0, [r7, #4] 800d892: 6039 str r1, [r7, #0] (void)pid; (void)sig; errno = EINVAL; 800d894: f007 fa3e bl 8014d14 <__errno> 800d898: 4603 mov r3, r0 800d89a: 2216 movs r2, #22 800d89c: 601a str r2, [r3, #0] return -1; 800d89e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800d8a2: 4618 mov r0, r3 800d8a4: 3708 adds r7, #8 800d8a6: 46bd mov sp, r7 800d8a8: bd80 pop {r7, pc} 0800d8aa <_exit>: void _exit (int status) { 800d8aa: b580 push {r7, lr} 800d8ac: b082 sub sp, #8 800d8ae: af00 add r7, sp, #0 800d8b0: 6078 str r0, [r7, #4] _kill(status, -1); 800d8b2: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800d8b6: 6878 ldr r0, [r7, #4] 800d8b8: f7ff ffe7 bl 800d88a <_kill> while (1) {} /* Make sure we hang here */ 800d8bc: bf00 nop 800d8be: e7fd b.n 800d8bc <_exit+0x12> 0800d8c0 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 800d8c0: b580 push {r7, lr} 800d8c2: b086 sub sp, #24 800d8c4: af00 add r7, sp, #0 800d8c6: 60f8 str r0, [r7, #12] 800d8c8: 60b9 str r1, [r7, #8] 800d8ca: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800d8cc: 2300 movs r3, #0 800d8ce: 617b str r3, [r7, #20] 800d8d0: e00a b.n 800d8e8 <_read+0x28> { *ptr++ = __io_getchar(); 800d8d2: f3af 8000 nop.w 800d8d6: 4601 mov r1, r0 800d8d8: 68bb ldr r3, [r7, #8] 800d8da: 1c5a adds r2, r3, #1 800d8dc: 60ba str r2, [r7, #8] 800d8de: b2ca uxtb r2, r1 800d8e0: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 800d8e2: 697b ldr r3, [r7, #20] 800d8e4: 3301 adds r3, #1 800d8e6: 617b str r3, [r7, #20] 800d8e8: 697a ldr r2, [r7, #20] 800d8ea: 687b ldr r3, [r7, #4] 800d8ec: 429a cmp r2, r3 800d8ee: dbf0 blt.n 800d8d2 <_read+0x12> } return len; 800d8f0: 687b ldr r3, [r7, #4] } 800d8f2: 4618 mov r0, r3 800d8f4: 3718 adds r7, #24 800d8f6: 46bd mov sp, r7 800d8f8: bd80 pop {r7, pc} 0800d8fa <_close>: } return len; } int _close(int file) { 800d8fa: b480 push {r7} 800d8fc: b083 sub sp, #12 800d8fe: af00 add r7, sp, #0 800d900: 6078 str r0, [r7, #4] (void)file; return -1; 800d902: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800d906: 4618 mov r0, r3 800d908: 370c adds r7, #12 800d90a: 46bd mov sp, r7 800d90c: bc80 pop {r7} 800d90e: 4770 bx lr 0800d910 <_fstat>: int _fstat(int file, struct stat *st) { 800d910: b480 push {r7} 800d912: b083 sub sp, #12 800d914: af00 add r7, sp, #0 800d916: 6078 str r0, [r7, #4] 800d918: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 800d91a: 683b ldr r3, [r7, #0] 800d91c: f44f 5200 mov.w r2, #8192 @ 0x2000 800d920: 605a str r2, [r3, #4] return 0; 800d922: 2300 movs r3, #0 } 800d924: 4618 mov r0, r3 800d926: 370c adds r7, #12 800d928: 46bd mov sp, r7 800d92a: bc80 pop {r7} 800d92c: 4770 bx lr 0800d92e <_isatty>: int _isatty(int file) { 800d92e: b480 push {r7} 800d930: b083 sub sp, #12 800d932: af00 add r7, sp, #0 800d934: 6078 str r0, [r7, #4] (void)file; return 1; 800d936: 2301 movs r3, #1 } 800d938: 4618 mov r0, r3 800d93a: 370c adds r7, #12 800d93c: 46bd mov sp, r7 800d93e: bc80 pop {r7} 800d940: 4770 bx lr 0800d942 <_lseek>: int _lseek(int file, int ptr, int dir) { 800d942: b480 push {r7} 800d944: b085 sub sp, #20 800d946: af00 add r7, sp, #0 800d948: 60f8 str r0, [r7, #12] 800d94a: 60b9 str r1, [r7, #8] 800d94c: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 800d94e: 2300 movs r3, #0 } 800d950: 4618 mov r0, r3 800d952: 3714 adds r7, #20 800d954: 46bd mov sp, r7 800d956: bc80 pop {r7} 800d958: 4770 bx lr ... 0800d95c <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 800d95c: b580 push {r7, lr} 800d95e: b086 sub sp, #24 800d960: af00 add r7, sp, #0 800d962: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 800d964: 4a14 ldr r2, [pc, #80] @ (800d9b8 <_sbrk+0x5c>) 800d966: 4b15 ldr r3, [pc, #84] @ (800d9bc <_sbrk+0x60>) 800d968: 1ad3 subs r3, r2, r3 800d96a: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 800d96c: 697b ldr r3, [r7, #20] 800d96e: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 800d970: 4b13 ldr r3, [pc, #76] @ (800d9c0 <_sbrk+0x64>) 800d972: 681b ldr r3, [r3, #0] 800d974: 2b00 cmp r3, #0 800d976: d102 bne.n 800d97e <_sbrk+0x22> { __sbrk_heap_end = &_end; 800d978: 4b11 ldr r3, [pc, #68] @ (800d9c0 <_sbrk+0x64>) 800d97a: 4a12 ldr r2, [pc, #72] @ (800d9c4 <_sbrk+0x68>) 800d97c: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 800d97e: 4b10 ldr r3, [pc, #64] @ (800d9c0 <_sbrk+0x64>) 800d980: 681a ldr r2, [r3, #0] 800d982: 687b ldr r3, [r7, #4] 800d984: 4413 add r3, r2 800d986: 693a ldr r2, [r7, #16] 800d988: 429a cmp r2, r3 800d98a: d207 bcs.n 800d99c <_sbrk+0x40> { errno = ENOMEM; 800d98c: f007 f9c2 bl 8014d14 <__errno> 800d990: 4603 mov r3, r0 800d992: 220c movs r2, #12 800d994: 601a str r2, [r3, #0] return (void *)-1; 800d996: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800d99a: e009 b.n 800d9b0 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 800d99c: 4b08 ldr r3, [pc, #32] @ (800d9c0 <_sbrk+0x64>) 800d99e: 681b ldr r3, [r3, #0] 800d9a0: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 800d9a2: 4b07 ldr r3, [pc, #28] @ (800d9c0 <_sbrk+0x64>) 800d9a4: 681a ldr r2, [r3, #0] 800d9a6: 687b ldr r3, [r7, #4] 800d9a8: 4413 add r3, r2 800d9aa: 4a05 ldr r2, [pc, #20] @ (800d9c0 <_sbrk+0x64>) 800d9ac: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 800d9ae: 68fb ldr r3, [r7, #12] } 800d9b0: 4618 mov r0, r3 800d9b2: 3718 adds r7, #24 800d9b4: 46bd mov sp, r7 800d9b6: bd80 pop {r7, pc} 800d9b8: 20010000 .word 0x20010000 800d9bc: 00000400 .word 0x00000400 800d9c0: 200011c4 .word 0x200011c4 800d9c4: 200015d8 .word 0x200015d8 0800d9c8 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 800d9c8: b480 push {r7} 800d9ca: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 800d9cc: bf00 nop 800d9ce: 46bd mov sp, r7 800d9d0: bc80 pop {r7} 800d9d2: 4770 bx lr 0800d9d4 : TIM_HandleTypeDef htim3; TIM_HandleTypeDef htim4; /* TIM3 init function */ void MX_TIM3_Init(void) { 800d9d4: b580 push {r7, lr} 800d9d6: b08e sub sp, #56 @ 0x38 800d9d8: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800d9da: f107 0328 add.w r3, r7, #40 @ 0x28 800d9de: 2200 movs r2, #0 800d9e0: 601a str r2, [r3, #0] 800d9e2: 605a str r2, [r3, #4] 800d9e4: 609a str r2, [r3, #8] 800d9e6: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800d9e8: f107 0320 add.w r3, r7, #32 800d9ec: 2200 movs r2, #0 800d9ee: 601a str r2, [r3, #0] 800d9f0: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800d9f2: 1d3b adds r3, r7, #4 800d9f4: 2200 movs r2, #0 800d9f6: 601a str r2, [r3, #0] 800d9f8: 605a str r2, [r3, #4] 800d9fa: 609a str r2, [r3, #8] 800d9fc: 60da str r2, [r3, #12] 800d9fe: 611a str r2, [r3, #16] 800da00: 615a str r2, [r3, #20] 800da02: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 800da04: 4b38 ldr r3, [pc, #224] @ (800dae8 ) 800da06: 4a39 ldr r2, [pc, #228] @ (800daec ) 800da08: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 800da0a: 4b37 ldr r3, [pc, #220] @ (800dae8 ) 800da0c: 2200 movs r2, #0 800da0e: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 800da10: 4b35 ldr r3, [pc, #212] @ (800dae8 ) 800da12: 2200 movs r2, #0 800da14: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 800da16: 4b34 ldr r3, [pc, #208] @ (800dae8 ) 800da18: f64f 72ff movw r2, #65535 @ 0xffff 800da1c: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800da1e: 4b32 ldr r3, [pc, #200] @ (800dae8 ) 800da20: 2200 movs r2, #0 800da22: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800da24: 4b30 ldr r3, [pc, #192] @ (800dae8 ) 800da26: 2200 movs r2, #0 800da28: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 800da2a: 482f ldr r0, [pc, #188] @ (800dae8 ) 800da2c: f004 f9d5 bl 8011dda 800da30: 4603 mov r3, r0 800da32: 2b00 cmp r3, #0 800da34: d001 beq.n 800da3a { Error_Handler(); 800da36: f7fd f94d bl 800acd4 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800da3a: f44f 5380 mov.w r3, #4096 @ 0x1000 800da3e: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 800da40: f107 0328 add.w r3, r7, #40 @ 0x28 800da44: 4619 mov r1, r3 800da46: 4828 ldr r0, [pc, #160] @ (800dae8 ) 800da48: f004 fe28 bl 801269c 800da4c: 4603 mov r3, r0 800da4e: 2b00 cmp r3, #0 800da50: d001 beq.n 800da56 { Error_Handler(); 800da52: f7fd f93f bl 800acd4 } if (HAL_TIM_OC_Init(&htim3) != HAL_OK) 800da56: 4824 ldr r0, [pc, #144] @ (800dae8 ) 800da58: f004 fa0e bl 8011e78 800da5c: 4603 mov r3, r0 800da5e: 2b00 cmp r3, #0 800da60: d001 beq.n 800da66 { Error_Handler(); 800da62: f7fd f937 bl 800acd4 } if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 800da66: 4820 ldr r0, [pc, #128] @ (800dae8 ) 800da68: f004 fb08 bl 801207c 800da6c: 4603 mov r3, r0 800da6e: 2b00 cmp r3, #0 800da70: d001 beq.n 800da76 { Error_Handler(); 800da72: f7fd f92f bl 800acd4 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_OC1; 800da76: 2330 movs r3, #48 @ 0x30 800da78: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800da7a: 2300 movs r3, #0 800da7c: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800da7e: f107 0320 add.w r3, r7, #32 800da82: 4619 mov r1, r3 800da84: 4818 ldr r0, [pc, #96] @ (800dae8 ) 800da86: f005 f9b7 bl 8012df8 800da8a: 4603 mov r3, r0 800da8c: 2b00 cmp r3, #0 800da8e: d001 beq.n 800da94 { Error_Handler(); 800da90: f7fd f920 bl 800acd4 } sConfigOC.OCMode = TIM_OCMODE_TIMING; 800da94: 2300 movs r3, #0 800da96: 607b str r3, [r7, #4] sConfigOC.Pulse = 1; 800da98: 2301 movs r3, #1 800da9a: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800da9c: 2300 movs r3, #0 800da9e: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800daa0: 2300 movs r3, #0 800daa2: 617b str r3, [r7, #20] if (HAL_TIM_OC_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 800daa4: 1d3b adds r3, r7, #4 800daa6: 2200 movs r2, #0 800daa8: 4619 mov r1, r3 800daaa: 480f ldr r0, [pc, #60] @ (800dae8 ) 800daac: f004 fcd8 bl 8012460 800dab0: 4603 mov r3, r0 800dab2: 2b00 cmp r3, #0 800dab4: d001 beq.n 800daba { Error_Handler(); 800dab6: f7fd f90d bl 800acd4 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800daba: 2360 movs r3, #96 @ 0x60 800dabc: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800dabe: 2300 movs r3, #0 800dac0: 60bb str r3, [r7, #8] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800dac2: 1d3b adds r3, r7, #4 800dac4: 2204 movs r2, #4 800dac6: 4619 mov r1, r3 800dac8: 4807 ldr r0, [pc, #28] @ (800dae8 ) 800daca: f004 fd25 bl 8012518 800dace: 4603 mov r3, r0 800dad0: 2b00 cmp r3, #0 800dad2: d001 beq.n 800dad8 { Error_Handler(); 800dad4: f7fd f8fe bl 800acd4 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 800dad8: 4803 ldr r0, [pc, #12] @ (800dae8 ) 800dada: f000 f8cf bl 800dc7c } 800dade: bf00 nop 800dae0: 3738 adds r7, #56 @ 0x38 800dae2: 46bd mov sp, r7 800dae4: bd80 pop {r7, pc} 800dae6: bf00 nop 800dae8: 200011c8 .word 0x200011c8 800daec: 40000400 .word 0x40000400 0800daf0 : /* TIM4 init function */ void MX_TIM4_Init(void) { 800daf0: b580 push {r7, lr} 800daf2: b08e sub sp, #56 @ 0x38 800daf4: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800daf6: f107 0328 add.w r3, r7, #40 @ 0x28 800dafa: 2200 movs r2, #0 800dafc: 601a str r2, [r3, #0] 800dafe: 605a str r2, [r3, #4] 800db00: 609a str r2, [r3, #8] 800db02: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800db04: f107 0320 add.w r3, r7, #32 800db08: 2200 movs r2, #0 800db0a: 601a str r2, [r3, #0] 800db0c: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800db0e: 1d3b adds r3, r7, #4 800db10: 2200 movs r2, #0 800db12: 601a str r2, [r3, #0] 800db14: 605a str r2, [r3, #4] 800db16: 609a str r2, [r3, #8] 800db18: 60da str r2, [r3, #12] 800db1a: 611a str r2, [r3, #16] 800db1c: 615a str r2, [r3, #20] 800db1e: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM4_Init 1 */ /* USER CODE END TIM4_Init 1 */ htim4.Instance = TIM4; 800db20: 4b37 ldr r3, [pc, #220] @ (800dc00 ) 800db22: 4a38 ldr r2, [pc, #224] @ (800dc04 ) 800db24: 601a str r2, [r3, #0] htim4.Init.Prescaler = 720; 800db26: 4b36 ldr r3, [pc, #216] @ (800dc00 ) 800db28: f44f 7234 mov.w r2, #720 @ 0x2d0 800db2c: 605a str r2, [r3, #4] htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 800db2e: 4b34 ldr r3, [pc, #208] @ (800dc00 ) 800db30: 2200 movs r2, #0 800db32: 609a str r2, [r3, #8] htim4.Init.Period = 100; 800db34: 4b32 ldr r3, [pc, #200] @ (800dc00 ) 800db36: 2264 movs r2, #100 @ 0x64 800db38: 60da str r2, [r3, #12] htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800db3a: 4b31 ldr r3, [pc, #196] @ (800dc00 ) 800db3c: 2200 movs r2, #0 800db3e: 611a str r2, [r3, #16] htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800db40: 4b2f ldr r3, [pc, #188] @ (800dc00 ) 800db42: 2200 movs r2, #0 800db44: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 800db46: 482e ldr r0, [pc, #184] @ (800dc00 ) 800db48: f004 f947 bl 8011dda 800db4c: 4603 mov r3, r0 800db4e: 2b00 cmp r3, #0 800db50: d001 beq.n 800db56 { Error_Handler(); 800db52: f7fd f8bf bl 800acd4 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800db56: f44f 5380 mov.w r3, #4096 @ 0x1000 800db5a: 62bb str r3, [r7, #40] @ 0x28 if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 800db5c: f107 0328 add.w r3, r7, #40 @ 0x28 800db60: 4619 mov r1, r3 800db62: 4827 ldr r0, [pc, #156] @ (800dc00 ) 800db64: f004 fd9a bl 801269c 800db68: 4603 mov r3, r0 800db6a: 2b00 cmp r3, #0 800db6c: d001 beq.n 800db72 { Error_Handler(); 800db6e: f7fd f8b1 bl 800acd4 } if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) 800db72: 4823 ldr r0, [pc, #140] @ (800dc00 ) 800db74: f004 fa82 bl 801207c 800db78: 4603 mov r3, r0 800db7a: 2b00 cmp r3, #0 800db7c: d001 beq.n 800db82 { Error_Handler(); 800db7e: f7fd f8a9 bl 800acd4 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800db82: 2300 movs r3, #0 800db84: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800db86: 2300 movs r3, #0 800db88: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 800db8a: f107 0320 add.w r3, r7, #32 800db8e: 4619 mov r1, r3 800db90: 481b ldr r0, [pc, #108] @ (800dc00 ) 800db92: f005 f931 bl 8012df8 800db96: 4603 mov r3, r0 800db98: 2b00 cmp r3, #0 800db9a: d001 beq.n 800dba0 { Error_Handler(); 800db9c: f7fd f89a bl 800acd4 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800dba0: 2360 movs r3, #96 @ 0x60 800dba2: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 800dba4: 2300 movs r3, #0 800dba6: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800dba8: 2300 movs r3, #0 800dbaa: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800dbac: 2300 movs r3, #0 800dbae: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800dbb0: 1d3b adds r3, r7, #4 800dbb2: 2204 movs r2, #4 800dbb4: 4619 mov r1, r3 800dbb6: 4812 ldr r0, [pc, #72] @ (800dc00 ) 800dbb8: f004 fcae bl 8012518 800dbbc: 4603 mov r3, r0 800dbbe: 2b00 cmp r3, #0 800dbc0: d001 beq.n 800dbc6 { Error_Handler(); 800dbc2: f7fd f887 bl 800acd4 } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 800dbc6: 1d3b adds r3, r7, #4 800dbc8: 2208 movs r2, #8 800dbca: 4619 mov r1, r3 800dbcc: 480c ldr r0, [pc, #48] @ (800dc00 ) 800dbce: f004 fca3 bl 8012518 800dbd2: 4603 mov r3, r0 800dbd4: 2b00 cmp r3, #0 800dbd6: d001 beq.n 800dbdc { Error_Handler(); 800dbd8: f7fd f87c bl 800acd4 } if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 800dbdc: 1d3b adds r3, r7, #4 800dbde: 220c movs r2, #12 800dbe0: 4619 mov r1, r3 800dbe2: 4807 ldr r0, [pc, #28] @ (800dc00 ) 800dbe4: f004 fc98 bl 8012518 800dbe8: 4603 mov r3, r0 800dbea: 2b00 cmp r3, #0 800dbec: d001 beq.n 800dbf2 { Error_Handler(); 800dbee: f7fd f871 bl 800acd4 } /* USER CODE BEGIN TIM4_Init 2 */ /* USER CODE END TIM4_Init 2 */ HAL_TIM_MspPostInit(&htim4); 800dbf2: 4803 ldr r0, [pc, #12] @ (800dc00 ) 800dbf4: f000 f842 bl 800dc7c } 800dbf8: bf00 nop 800dbfa: 3738 adds r7, #56 @ 0x38 800dbfc: 46bd mov sp, r7 800dbfe: bd80 pop {r7, pc} 800dc00: 20001210 .word 0x20001210 800dc04: 40000800 .word 0x40000800 0800dc08 : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 800dc08: b580 push {r7, lr} 800dc0a: b084 sub sp, #16 800dc0c: af00 add r7, sp, #0 800dc0e: 6078 str r0, [r7, #4] if(tim_baseHandle->Instance==TIM3) 800dc10: 687b ldr r3, [r7, #4] 800dc12: 681b ldr r3, [r3, #0] 800dc14: 4a16 ldr r2, [pc, #88] @ (800dc70 ) 800dc16: 4293 cmp r3, r2 800dc18: d114 bne.n 800dc44 { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 800dc1a: 4b16 ldr r3, [pc, #88] @ (800dc74 ) 800dc1c: 69db ldr r3, [r3, #28] 800dc1e: 4a15 ldr r2, [pc, #84] @ (800dc74 ) 800dc20: f043 0302 orr.w r3, r3, #2 800dc24: 61d3 str r3, [r2, #28] 800dc26: 4b13 ldr r3, [pc, #76] @ (800dc74 ) 800dc28: 69db ldr r3, [r3, #28] 800dc2a: f003 0302 and.w r3, r3, #2 800dc2e: 60fb str r3, [r7, #12] 800dc30: 68fb ldr r3, [r7, #12] /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 6, 0); 800dc32: 2200 movs r2, #0 800dc34: 2106 movs r1, #6 800dc36: 201d movs r0, #29 800dc38: f002 f8c5 bl 800fdc6 HAL_NVIC_EnableIRQ(TIM3_IRQn); 800dc3c: 201d movs r0, #29 800dc3e: f002 f8de bl 800fdfe __HAL_RCC_TIM4_CLK_ENABLE(); /* USER CODE BEGIN TIM4_MspInit 1 */ /* USER CODE END TIM4_MspInit 1 */ } } 800dc42: e010 b.n 800dc66 else if(tim_baseHandle->Instance==TIM4) 800dc44: 687b ldr r3, [r7, #4] 800dc46: 681b ldr r3, [r3, #0] 800dc48: 4a0b ldr r2, [pc, #44] @ (800dc78 ) 800dc4a: 4293 cmp r3, r2 800dc4c: d10b bne.n 800dc66 __HAL_RCC_TIM4_CLK_ENABLE(); 800dc4e: 4b09 ldr r3, [pc, #36] @ (800dc74 ) 800dc50: 69db ldr r3, [r3, #28] 800dc52: 4a08 ldr r2, [pc, #32] @ (800dc74 ) 800dc54: f043 0304 orr.w r3, r3, #4 800dc58: 61d3 str r3, [r2, #28] 800dc5a: 4b06 ldr r3, [pc, #24] @ (800dc74 ) 800dc5c: 69db ldr r3, [r3, #28] 800dc5e: f003 0304 and.w r3, r3, #4 800dc62: 60bb str r3, [r7, #8] 800dc64: 68bb ldr r3, [r7, #8] } 800dc66: bf00 nop 800dc68: 3710 adds r7, #16 800dc6a: 46bd mov sp, r7 800dc6c: bd80 pop {r7, pc} 800dc6e: bf00 nop 800dc70: 40000400 .word 0x40000400 800dc74: 40021000 .word 0x40021000 800dc78: 40000800 .word 0x40000800 0800dc7c : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 800dc7c: b580 push {r7, lr} 800dc7e: b08a sub sp, #40 @ 0x28 800dc80: af00 add r7, sp, #0 800dc82: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800dc84: f107 0314 add.w r3, r7, #20 800dc88: 2200 movs r2, #0 800dc8a: 601a str r2, [r3, #0] 800dc8c: 605a str r2, [r3, #4] 800dc8e: 609a str r2, [r3, #8] 800dc90: 60da str r2, [r3, #12] if(timHandle->Instance==TIM3) 800dc92: 687b ldr r3, [r7, #4] 800dc94: 681b ldr r3, [r3, #0] 800dc96: 4a26 ldr r2, [pc, #152] @ (800dd30 ) 800dc98: 4293 cmp r3, r2 800dc9a: d118 bne.n 800dcce { /* USER CODE BEGIN TIM3_MspPostInit 0 */ /* USER CODE END TIM3_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800dc9c: 4b25 ldr r3, [pc, #148] @ (800dd34 ) 800dc9e: 699b ldr r3, [r3, #24] 800dca0: 4a24 ldr r2, [pc, #144] @ (800dd34 ) 800dca2: f043 0304 orr.w r3, r3, #4 800dca6: 6193 str r3, [r2, #24] 800dca8: 4b22 ldr r3, [pc, #136] @ (800dd34 ) 800dcaa: 699b ldr r3, [r3, #24] 800dcac: f003 0304 and.w r3, r3, #4 800dcb0: 613b str r3, [r7, #16] 800dcb2: 693b ldr r3, [r7, #16] /**TIM3 GPIO Configuration PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = CP_PWM_Pin; 800dcb4: 2380 movs r3, #128 @ 0x80 800dcb6: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800dcb8: 2302 movs r3, #2 800dcba: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800dcbc: 2302 movs r3, #2 800dcbe: 623b str r3, [r7, #32] HAL_GPIO_Init(CP_PWM_GPIO_Port, &GPIO_InitStruct); 800dcc0: f107 0314 add.w r3, r7, #20 800dcc4: 4619 mov r1, r3 800dcc6: 481c ldr r0, [pc, #112] @ (800dd38 ) 800dcc8: f002 fd5e bl 8010788 /* USER CODE BEGIN TIM4_MspPostInit 1 */ /* USER CODE END TIM4_MspPostInit 1 */ } } 800dccc: e02b b.n 800dd26 else if(timHandle->Instance==TIM4) 800dcce: 687b ldr r3, [r7, #4] 800dcd0: 681b ldr r3, [r3, #0] 800dcd2: 4a1a ldr r2, [pc, #104] @ (800dd3c ) 800dcd4: 4293 cmp r3, r2 800dcd6: d126 bne.n 800dd26 __HAL_RCC_GPIOD_CLK_ENABLE(); 800dcd8: 4b16 ldr r3, [pc, #88] @ (800dd34 ) 800dcda: 699b ldr r3, [r3, #24] 800dcdc: 4a15 ldr r2, [pc, #84] @ (800dd34 ) 800dcde: f043 0320 orr.w r3, r3, #32 800dce2: 6193 str r3, [r2, #24] 800dce4: 4b13 ldr r3, [pc, #76] @ (800dd34 ) 800dce6: 699b ldr r3, [r3, #24] 800dce8: f003 0320 and.w r3, r3, #32 800dcec: 60fb str r3, [r7, #12] 800dcee: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; 800dcf0: f44f 4360 mov.w r3, #57344 @ 0xe000 800dcf4: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800dcf6: 2302 movs r3, #2 800dcf8: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800dcfa: 2302 movs r3, #2 800dcfc: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800dcfe: f107 0314 add.w r3, r7, #20 800dd02: 4619 mov r1, r3 800dd04: 480e ldr r0, [pc, #56] @ (800dd40 ) 800dd06: f002 fd3f bl 8010788 __HAL_AFIO_REMAP_TIM4_ENABLE(); 800dd0a: 4b0e ldr r3, [pc, #56] @ (800dd44 ) 800dd0c: 685b ldr r3, [r3, #4] 800dd0e: 627b str r3, [r7, #36] @ 0x24 800dd10: 6a7b ldr r3, [r7, #36] @ 0x24 800dd12: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800dd16: 627b str r3, [r7, #36] @ 0x24 800dd18: 6a7b ldr r3, [r7, #36] @ 0x24 800dd1a: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800dd1e: 627b str r3, [r7, #36] @ 0x24 800dd20: 4a08 ldr r2, [pc, #32] @ (800dd44 ) 800dd22: 6a7b ldr r3, [r7, #36] @ 0x24 800dd24: 6053 str r3, [r2, #4] } 800dd26: bf00 nop 800dd28: 3728 adds r7, #40 @ 0x28 800dd2a: 46bd mov sp, r7 800dd2c: bd80 pop {r7, pc} 800dd2e: bf00 nop 800dd30: 40000400 .word 0x40000400 800dd34: 40021000 .word 0x40021000 800dd38: 40010800 .word 0x40010800 800dd3c: 40000800 .word 0x40000800 800dd40: 40011400 .word 0x40011400 800dd44: 40010000 .word 0x40010000 0800dd48 : DMA_HandleTypeDef hdma_usart3_rx; DMA_HandleTypeDef hdma_usart3_tx; /* UART5 init function */ void MX_UART5_Init(void) { 800dd48: b580 push {r7, lr} 800dd4a: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 800dd4c: 4b11 ldr r3, [pc, #68] @ (800dd94 ) 800dd4e: 4a12 ldr r2, [pc, #72] @ (800dd98 ) 800dd50: 601a str r2, [r3, #0] huart5.Init.BaudRate = 9600; 800dd52: 4b10 ldr r3, [pc, #64] @ (800dd94 ) 800dd54: f44f 5216 mov.w r2, #9600 @ 0x2580 800dd58: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 800dd5a: 4b0e ldr r3, [pc, #56] @ (800dd94 ) 800dd5c: 2200 movs r2, #0 800dd5e: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 800dd60: 4b0c ldr r3, [pc, #48] @ (800dd94 ) 800dd62: 2200 movs r2, #0 800dd64: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 800dd66: 4b0b ldr r3, [pc, #44] @ (800dd94 ) 800dd68: 2200 movs r2, #0 800dd6a: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 800dd6c: 4b09 ldr r3, [pc, #36] @ (800dd94 ) 800dd6e: 220c movs r2, #12 800dd70: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800dd72: 4b08 ldr r3, [pc, #32] @ (800dd94 ) 800dd74: 2200 movs r2, #0 800dd76: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 800dd78: 4b06 ldr r3, [pc, #24] @ (800dd94 ) 800dd7a: 2200 movs r2, #0 800dd7c: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 800dd7e: 4805 ldr r0, [pc, #20] @ (800dd94 ) 800dd80: f005 f8b2 bl 8012ee8 800dd84: 4603 mov r3, r0 800dd86: 2b00 cmp r3, #0 800dd88: d001 beq.n 800dd8e { Error_Handler(); 800dd8a: f7fc ffa3 bl 800acd4 } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 800dd8e: bf00 nop 800dd90: bd80 pop {r7, pc} 800dd92: bf00 nop 800dd94: 20001258 .word 0x20001258 800dd98: 40005000 .word 0x40005000 0800dd9c : /* USART1 init function */ void MX_USART1_UART_Init(void) { 800dd9c: b580 push {r7, lr} 800dd9e: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 800dda0: 4b11 ldr r3, [pc, #68] @ (800dde8 ) 800dda2: 4a12 ldr r2, [pc, #72] @ (800ddec ) 800dda4: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800dda6: 4b10 ldr r3, [pc, #64] @ (800dde8 ) 800dda8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800ddac: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800ddae: 4b0e ldr r3, [pc, #56] @ (800dde8 ) 800ddb0: 2200 movs r2, #0 800ddb2: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 800ddb4: 4b0c ldr r3, [pc, #48] @ (800dde8 ) 800ddb6: 2200 movs r2, #0 800ddb8: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800ddba: 4b0b ldr r3, [pc, #44] @ (800dde8 ) 800ddbc: 2200 movs r2, #0 800ddbe: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 800ddc0: 4b09 ldr r3, [pc, #36] @ (800dde8 ) 800ddc2: 220c movs r2, #12 800ddc4: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800ddc6: 4b08 ldr r3, [pc, #32] @ (800dde8 ) 800ddc8: 2200 movs r2, #0 800ddca: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 800ddcc: 4b06 ldr r3, [pc, #24] @ (800dde8 ) 800ddce: 2200 movs r2, #0 800ddd0: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 800ddd2: 4805 ldr r0, [pc, #20] @ (800dde8 ) 800ddd4: f005 f888 bl 8012ee8 800ddd8: 4603 mov r3, r0 800ddda: 2b00 cmp r3, #0 800dddc: d001 beq.n 800dde2 { Error_Handler(); 800ddde: f7fc ff79 bl 800acd4 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 800dde2: bf00 nop 800dde4: bd80 pop {r7, pc} 800dde6: bf00 nop 800dde8: 200012a0 .word 0x200012a0 800ddec: 40013800 .word 0x40013800 0800ddf0 : /* USART2 init function */ void MX_USART2_UART_Init(void) { 800ddf0: b580 push {r7, lr} 800ddf2: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 800ddf4: 4b11 ldr r3, [pc, #68] @ (800de3c ) 800ddf6: 4a12 ldr r2, [pc, #72] @ (800de40 ) 800ddf8: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 800ddfa: 4b10 ldr r3, [pc, #64] @ (800de3c ) 800ddfc: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800de00: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 800de02: 4b0e ldr r3, [pc, #56] @ (800de3c ) 800de04: 2200 movs r2, #0 800de06: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 800de08: 4b0c ldr r3, [pc, #48] @ (800de3c ) 800de0a: 2200 movs r2, #0 800de0c: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 800de0e: 4b0b ldr r3, [pc, #44] @ (800de3c ) 800de10: 2200 movs r2, #0 800de12: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 800de14: 4b09 ldr r3, [pc, #36] @ (800de3c ) 800de16: 220c movs r2, #12 800de18: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800de1a: 4b08 ldr r3, [pc, #32] @ (800de3c ) 800de1c: 2200 movs r2, #0 800de1e: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 800de20: 4b06 ldr r3, [pc, #24] @ (800de3c ) 800de22: 2200 movs r2, #0 800de24: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 800de26: 4805 ldr r0, [pc, #20] @ (800de3c ) 800de28: f005 f85e bl 8012ee8 800de2c: 4603 mov r3, r0 800de2e: 2b00 cmp r3, #0 800de30: d001 beq.n 800de36 { Error_Handler(); 800de32: f7fc ff4f bl 800acd4 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 800de36: bf00 nop 800de38: bd80 pop {r7, pc} 800de3a: bf00 nop 800de3c: 200012e8 .word 0x200012e8 800de40: 40004400 .word 0x40004400 0800de44 : /* USART3 init function */ void MX_USART3_UART_Init(void) { 800de44: b580 push {r7, lr} 800de46: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 800de48: 4b11 ldr r3, [pc, #68] @ (800de90 ) 800de4a: 4a12 ldr r2, [pc, #72] @ (800de94 ) 800de4c: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 800de4e: 4b10 ldr r3, [pc, #64] @ (800de90 ) 800de50: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800de54: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 800de56: 4b0e ldr r3, [pc, #56] @ (800de90 ) 800de58: 2200 movs r2, #0 800de5a: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 800de5c: 4b0c ldr r3, [pc, #48] @ (800de90 ) 800de5e: 2200 movs r2, #0 800de60: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 800de62: 4b0b ldr r3, [pc, #44] @ (800de90 ) 800de64: 2200 movs r2, #0 800de66: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 800de68: 4b09 ldr r3, [pc, #36] @ (800de90 ) 800de6a: 220c movs r2, #12 800de6c: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800de6e: 4b08 ldr r3, [pc, #32] @ (800de90 ) 800de70: 2200 movs r2, #0 800de72: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 800de74: 4b06 ldr r3, [pc, #24] @ (800de90 ) 800de76: 2200 movs r2, #0 800de78: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart3) != HAL_OK) 800de7a: 4805 ldr r0, [pc, #20] @ (800de90 ) 800de7c: f005 f834 bl 8012ee8 800de80: 4603 mov r3, r0 800de82: 2b00 cmp r3, #0 800de84: d001 beq.n 800de8a { Error_Handler(); 800de86: f7fc ff25 bl 800acd4 } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 800de8a: bf00 nop 800de8c: bd80 pop {r7, pc} 800de8e: bf00 nop 800de90: 20001330 .word 0x20001330 800de94: 40004800 .word 0x40004800 0800de98 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 800de98: b580 push {r7, lr} 800de9a: b092 sub sp, #72 @ 0x48 800de9c: af00 add r7, sp, #0 800de9e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800dea0: f107 0330 add.w r3, r7, #48 @ 0x30 800dea4: 2200 movs r2, #0 800dea6: 601a str r2, [r3, #0] 800dea8: 605a str r2, [r3, #4] 800deaa: 609a str r2, [r3, #8] 800deac: 60da str r2, [r3, #12] if(uartHandle->Instance==UART5) 800deae: 687b ldr r3, [r7, #4] 800deb0: 681b ldr r3, [r3, #0] 800deb2: 4a92 ldr r2, [pc, #584] @ (800e0fc ) 800deb4: 4293 cmp r3, r2 800deb6: d145 bne.n 800df44 { /* USER CODE BEGIN UART5_MspInit 0 */ /* USER CODE END UART5_MspInit 0 */ /* UART5 clock enable */ __HAL_RCC_UART5_CLK_ENABLE(); 800deb8: 4b91 ldr r3, [pc, #580] @ (800e100 ) 800deba: 69db ldr r3, [r3, #28] 800debc: 4a90 ldr r2, [pc, #576] @ (800e100 ) 800debe: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800dec2: 61d3 str r3, [r2, #28] 800dec4: 4b8e ldr r3, [pc, #568] @ (800e100 ) 800dec6: 69db ldr r3, [r3, #28] 800dec8: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800decc: 62fb str r3, [r7, #44] @ 0x2c 800dece: 6afb ldr r3, [r7, #44] @ 0x2c __HAL_RCC_GPIOC_CLK_ENABLE(); 800ded0: 4b8b ldr r3, [pc, #556] @ (800e100 ) 800ded2: 699b ldr r3, [r3, #24] 800ded4: 4a8a ldr r2, [pc, #552] @ (800e100 ) 800ded6: f043 0310 orr.w r3, r3, #16 800deda: 6193 str r3, [r2, #24] 800dedc: 4b88 ldr r3, [pc, #544] @ (800e100 ) 800dede: 699b ldr r3, [r3, #24] 800dee0: f003 0310 and.w r3, r3, #16 800dee4: 62bb str r3, [r7, #40] @ 0x28 800dee6: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOD_CLK_ENABLE(); 800dee8: 4b85 ldr r3, [pc, #532] @ (800e100 ) 800deea: 699b ldr r3, [r3, #24] 800deec: 4a84 ldr r2, [pc, #528] @ (800e100 ) 800deee: f043 0320 orr.w r3, r3, #32 800def2: 6193 str r3, [r2, #24] 800def4: 4b82 ldr r3, [pc, #520] @ (800e100 ) 800def6: 699b ldr r3, [r3, #24] 800def8: f003 0320 and.w r3, r3, #32 800defc: 627b str r3, [r7, #36] @ 0x24 800defe: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART5 GPIO Configuration PC12 ------> UART5_TX PD2 ------> UART5_RX */ GPIO_InitStruct.Pin = HEATER_Pin; 800df00: f44f 5380 mov.w r3, #4096 @ 0x1000 800df04: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800df06: 2302 movs r3, #2 800df08: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800df0a: 2303 movs r3, #3 800df0c: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(HEATER_GPIO_Port, &GPIO_InitStruct); 800df0e: f107 0330 add.w r3, r7, #48 @ 0x30 800df12: 4619 mov r1, r3 800df14: 487b ldr r0, [pc, #492] @ (800e104 ) 800df16: f002 fc37 bl 8010788 GPIO_InitStruct.Pin = GPIO_PIN_2; 800df1a: 2304 movs r3, #4 800df1c: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800df1e: 2300 movs r3, #0 800df20: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800df22: 2300 movs r3, #0 800df24: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800df26: f107 0330 add.w r3, r7, #48 @ 0x30 800df2a: 4619 mov r1, r3 800df2c: 4876 ldr r0, [pc, #472] @ (800e108 ) 800df2e: f002 fc2b bl 8010788 /* UART5 interrupt Init */ HAL_NVIC_SetPriority(UART5_IRQn, 5, 0); 800df32: 2200 movs r2, #0 800df34: 2105 movs r1, #5 800df36: 2035 movs r0, #53 @ 0x35 800df38: f001 ff45 bl 800fdc6 HAL_NVIC_EnableIRQ(UART5_IRQn); 800df3c: 2035 movs r0, #53 @ 0x35 800df3e: f001 ff5e bl 800fdfe HAL_NVIC_EnableIRQ(USART3_IRQn); /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } 800df42: e193 b.n 800e26c else if(uartHandle->Instance==USART1) 800df44: 687b ldr r3, [r7, #4] 800df46: 681b ldr r3, [r3, #0] 800df48: 4a70 ldr r2, [pc, #448] @ (800e10c ) 800df4a: 4293 cmp r3, r2 800df4c: d13a bne.n 800dfc4 __HAL_RCC_USART1_CLK_ENABLE(); 800df4e: 4b6c ldr r3, [pc, #432] @ (800e100 ) 800df50: 699b ldr r3, [r3, #24] 800df52: 4a6b ldr r2, [pc, #428] @ (800e100 ) 800df54: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800df58: 6193 str r3, [r2, #24] 800df5a: 4b69 ldr r3, [pc, #420] @ (800e100 ) 800df5c: 699b ldr r3, [r3, #24] 800df5e: f403 4380 and.w r3, r3, #16384 @ 0x4000 800df62: 623b str r3, [r7, #32] 800df64: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOA_CLK_ENABLE(); 800df66: 4b66 ldr r3, [pc, #408] @ (800e100 ) 800df68: 699b ldr r3, [r3, #24] 800df6a: 4a65 ldr r2, [pc, #404] @ (800e100 ) 800df6c: f043 0304 orr.w r3, r3, #4 800df70: 6193 str r3, [r2, #24] 800df72: 4b63 ldr r3, [pc, #396] @ (800e100 ) 800df74: 699b ldr r3, [r3, #24] 800df76: f003 0304 and.w r3, r3, #4 800df7a: 61fb str r3, [r7, #28] 800df7c: 69fb ldr r3, [r7, #28] GPIO_InitStruct.Pin = GPIO_PIN_9; 800df7e: f44f 7300 mov.w r3, #512 @ 0x200 800df82: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800df84: 2302 movs r3, #2 800df86: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800df88: 2303 movs r3, #3 800df8a: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800df8c: f107 0330 add.w r3, r7, #48 @ 0x30 800df90: 4619 mov r1, r3 800df92: 485f ldr r0, [pc, #380] @ (800e110 ) 800df94: f002 fbf8 bl 8010788 GPIO_InitStruct.Pin = GPIO_PIN_10; 800df98: f44f 6380 mov.w r3, #1024 @ 0x400 800df9c: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800df9e: 2300 movs r3, #0 800dfa0: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800dfa2: 2300 movs r3, #0 800dfa4: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800dfa6: f107 0330 add.w r3, r7, #48 @ 0x30 800dfaa: 4619 mov r1, r3 800dfac: 4858 ldr r0, [pc, #352] @ (800e110 ) 800dfae: f002 fbeb bl 8010788 HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 800dfb2: 2200 movs r2, #0 800dfb4: 2105 movs r1, #5 800dfb6: 2025 movs r0, #37 @ 0x25 800dfb8: f001 ff05 bl 800fdc6 HAL_NVIC_EnableIRQ(USART1_IRQn); 800dfbc: 2025 movs r0, #37 @ 0x25 800dfbe: f001 ff1e bl 800fdfe } 800dfc2: e153 b.n 800e26c else if(uartHandle->Instance==USART2) 800dfc4: 687b ldr r3, [r7, #4] 800dfc6: 681b ldr r3, [r3, #0] 800dfc8: 4a52 ldr r2, [pc, #328] @ (800e114 ) 800dfca: 4293 cmp r3, r2 800dfcc: f040 80ae bne.w 800e12c __HAL_RCC_USART2_CLK_ENABLE(); 800dfd0: 4b4b ldr r3, [pc, #300] @ (800e100 ) 800dfd2: 69db ldr r3, [r3, #28] 800dfd4: 4a4a ldr r2, [pc, #296] @ (800e100 ) 800dfd6: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800dfda: 61d3 str r3, [r2, #28] 800dfdc: 4b48 ldr r3, [pc, #288] @ (800e100 ) 800dfde: 69db ldr r3, [r3, #28] 800dfe0: f403 3300 and.w r3, r3, #131072 @ 0x20000 800dfe4: 61bb str r3, [r7, #24] 800dfe6: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOD_CLK_ENABLE(); 800dfe8: 4b45 ldr r3, [pc, #276] @ (800e100 ) 800dfea: 699b ldr r3, [r3, #24] 800dfec: 4a44 ldr r2, [pc, #272] @ (800e100 ) 800dfee: f043 0320 orr.w r3, r3, #32 800dff2: 6193 str r3, [r2, #24] 800dff4: 4b42 ldr r3, [pc, #264] @ (800e100 ) 800dff6: 699b ldr r3, [r3, #24] 800dff8: f003 0320 and.w r3, r3, #32 800dffc: 617b str r3, [r7, #20] 800dffe: 697b ldr r3, [r7, #20] GPIO_InitStruct.Pin = GPIO_PIN_5; 800e000: 2320 movs r3, #32 800e002: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800e004: 2302 movs r3, #2 800e006: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800e008: 2303 movs r3, #3 800e00a: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800e00c: f107 0330 add.w r3, r7, #48 @ 0x30 800e010: 4619 mov r1, r3 800e012: 483d ldr r0, [pc, #244] @ (800e108 ) 800e014: f002 fbb8 bl 8010788 GPIO_InitStruct.Pin = GPIO_PIN_6; 800e018: 2340 movs r3, #64 @ 0x40 800e01a: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800e01c: 2300 movs r3, #0 800e01e: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800e020: 2300 movs r3, #0 800e022: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800e024: f107 0330 add.w r3, r7, #48 @ 0x30 800e028: 4619 mov r1, r3 800e02a: 4837 ldr r0, [pc, #220] @ (800e108 ) 800e02c: f002 fbac bl 8010788 __HAL_AFIO_REMAP_USART2_ENABLE(); 800e030: 4b39 ldr r3, [pc, #228] @ (800e118 ) 800e032: 685b ldr r3, [r3, #4] 800e034: 643b str r3, [r7, #64] @ 0x40 800e036: 6c3b ldr r3, [r7, #64] @ 0x40 800e038: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800e03c: 643b str r3, [r7, #64] @ 0x40 800e03e: 6c3b ldr r3, [r7, #64] @ 0x40 800e040: f043 0308 orr.w r3, r3, #8 800e044: 643b str r3, [r7, #64] @ 0x40 800e046: 4a34 ldr r2, [pc, #208] @ (800e118 ) 800e048: 6c3b ldr r3, [r7, #64] @ 0x40 800e04a: 6053 str r3, [r2, #4] hdma_usart2_rx.Instance = DMA1_Channel6; 800e04c: 4b33 ldr r3, [pc, #204] @ (800e11c ) 800e04e: 4a34 ldr r2, [pc, #208] @ (800e120 ) 800e050: 601a str r2, [r3, #0] hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 800e052: 4b32 ldr r3, [pc, #200] @ (800e11c ) 800e054: 2200 movs r2, #0 800e056: 605a str r2, [r3, #4] hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; 800e058: 4b30 ldr r3, [pc, #192] @ (800e11c ) 800e05a: 2200 movs r2, #0 800e05c: 609a str r2, [r3, #8] hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; 800e05e: 4b2f ldr r3, [pc, #188] @ (800e11c ) 800e060: 2280 movs r2, #128 @ 0x80 800e062: 60da str r2, [r3, #12] hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800e064: 4b2d ldr r3, [pc, #180] @ (800e11c ) 800e066: 2200 movs r2, #0 800e068: 611a str r2, [r3, #16] hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800e06a: 4b2c ldr r3, [pc, #176] @ (800e11c ) 800e06c: 2200 movs r2, #0 800e06e: 615a str r2, [r3, #20] hdma_usart2_rx.Init.Mode = DMA_NORMAL; 800e070: 4b2a ldr r3, [pc, #168] @ (800e11c ) 800e072: 2200 movs r2, #0 800e074: 619a str r2, [r3, #24] hdma_usart2_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH; 800e076: 4b29 ldr r3, [pc, #164] @ (800e11c ) 800e078: f44f 5240 mov.w r2, #12288 @ 0x3000 800e07c: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) 800e07e: 4827 ldr r0, [pc, #156] @ (800e11c ) 800e080: f001 fef4 bl 800fe6c 800e084: 4603 mov r3, r0 800e086: 2b00 cmp r3, #0 800e088: d001 beq.n 800e08e Error_Handler(); 800e08a: f7fc fe23 bl 800acd4 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx); 800e08e: 687b ldr r3, [r7, #4] 800e090: 4a22 ldr r2, [pc, #136] @ (800e11c ) 800e092: 63da str r2, [r3, #60] @ 0x3c 800e094: 4a21 ldr r2, [pc, #132] @ (800e11c ) 800e096: 687b ldr r3, [r7, #4] 800e098: 6253 str r3, [r2, #36] @ 0x24 hdma_usart2_tx.Instance = DMA1_Channel7; 800e09a: 4b22 ldr r3, [pc, #136] @ (800e124 ) 800e09c: 4a22 ldr r2, [pc, #136] @ (800e128 ) 800e09e: 601a str r2, [r3, #0] hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 800e0a0: 4b20 ldr r3, [pc, #128] @ (800e124 ) 800e0a2: 2210 movs r2, #16 800e0a4: 605a str r2, [r3, #4] hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800e0a6: 4b1f ldr r3, [pc, #124] @ (800e124 ) 800e0a8: 2200 movs r2, #0 800e0aa: 609a str r2, [r3, #8] hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; 800e0ac: 4b1d ldr r3, [pc, #116] @ (800e124 ) 800e0ae: 2280 movs r2, #128 @ 0x80 800e0b0: 60da str r2, [r3, #12] hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800e0b2: 4b1c ldr r3, [pc, #112] @ (800e124 ) 800e0b4: 2200 movs r2, #0 800e0b6: 611a str r2, [r3, #16] hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800e0b8: 4b1a ldr r3, [pc, #104] @ (800e124 ) 800e0ba: 2200 movs r2, #0 800e0bc: 615a str r2, [r3, #20] hdma_usart2_tx.Init.Mode = DMA_NORMAL; 800e0be: 4b19 ldr r3, [pc, #100] @ (800e124 ) 800e0c0: 2200 movs r2, #0 800e0c2: 619a str r2, [r3, #24] hdma_usart2_tx.Init.Priority = DMA_PRIORITY_HIGH; 800e0c4: 4b17 ldr r3, [pc, #92] @ (800e124 ) 800e0c6: f44f 5200 mov.w r2, #8192 @ 0x2000 800e0ca: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) 800e0cc: 4815 ldr r0, [pc, #84] @ (800e124 ) 800e0ce: f001 fecd bl 800fe6c 800e0d2: 4603 mov r3, r0 800e0d4: 2b00 cmp r3, #0 800e0d6: d001 beq.n 800e0dc Error_Handler(); 800e0d8: f7fc fdfc bl 800acd4 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); 800e0dc: 687b ldr r3, [r7, #4] 800e0de: 4a11 ldr r2, [pc, #68] @ (800e124 ) 800e0e0: 639a str r2, [r3, #56] @ 0x38 800e0e2: 4a10 ldr r2, [pc, #64] @ (800e124 ) 800e0e4: 687b ldr r3, [r7, #4] 800e0e6: 6253 str r3, [r2, #36] @ 0x24 HAL_NVIC_SetPriority(USART2_IRQn, 2, 0); 800e0e8: 2200 movs r2, #0 800e0ea: 2102 movs r1, #2 800e0ec: 2026 movs r0, #38 @ 0x26 800e0ee: f001 fe6a bl 800fdc6 HAL_NVIC_EnableIRQ(USART2_IRQn); 800e0f2: 2026 movs r0, #38 @ 0x26 800e0f4: f001 fe83 bl 800fdfe } 800e0f8: e0b8 b.n 800e26c 800e0fa: bf00 nop 800e0fc: 40005000 .word 0x40005000 800e100: 40021000 .word 0x40021000 800e104: 40011000 .word 0x40011000 800e108: 40011400 .word 0x40011400 800e10c: 40013800 .word 0x40013800 800e110: 40010800 .word 0x40010800 800e114: 40004400 .word 0x40004400 800e118: 40010000 .word 0x40010000 800e11c: 20001378 .word 0x20001378 800e120: 4002006c .word 0x4002006c 800e124: 200013bc .word 0x200013bc 800e128: 40020080 .word 0x40020080 else if(uartHandle->Instance==USART3) 800e12c: 687b ldr r3, [r7, #4] 800e12e: 681b ldr r3, [r3, #0] 800e130: 4a50 ldr r2, [pc, #320] @ (800e274 ) 800e132: 4293 cmp r3, r2 800e134: f040 809a bne.w 800e26c __HAL_RCC_USART3_CLK_ENABLE(); 800e138: 4b4f ldr r3, [pc, #316] @ (800e278 ) 800e13a: 69db ldr r3, [r3, #28] 800e13c: 4a4e ldr r2, [pc, #312] @ (800e278 ) 800e13e: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800e142: 61d3 str r3, [r2, #28] 800e144: 4b4c ldr r3, [pc, #304] @ (800e278 ) 800e146: 69db ldr r3, [r3, #28] 800e148: f403 2380 and.w r3, r3, #262144 @ 0x40000 800e14c: 613b str r3, [r7, #16] 800e14e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 800e150: 4b49 ldr r3, [pc, #292] @ (800e278 ) 800e152: 699b ldr r3, [r3, #24] 800e154: 4a48 ldr r2, [pc, #288] @ (800e278 ) 800e156: f043 0310 orr.w r3, r3, #16 800e15a: 6193 str r3, [r2, #24] 800e15c: 4b46 ldr r3, [pc, #280] @ (800e278 ) 800e15e: 699b ldr r3, [r3, #24] 800e160: f003 0310 and.w r3, r3, #16 800e164: 60fb str r3, [r7, #12] 800e166: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_10; 800e168: f44f 6380 mov.w r3, #1024 @ 0x400 800e16c: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800e16e: 2302 movs r3, #2 800e170: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800e172: 2303 movs r3, #3 800e174: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800e176: f107 0330 add.w r3, r7, #48 @ 0x30 800e17a: 4619 mov r1, r3 800e17c: 483f ldr r0, [pc, #252] @ (800e27c ) 800e17e: f002 fb03 bl 8010788 GPIO_InitStruct.Pin = GPIO_PIN_11; 800e182: f44f 6300 mov.w r3, #2048 @ 0x800 800e186: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800e188: 2300 movs r3, #0 800e18a: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Pull = GPIO_NOPULL; 800e18c: 2300 movs r3, #0 800e18e: 63bb str r3, [r7, #56] @ 0x38 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800e190: f107 0330 add.w r3, r7, #48 @ 0x30 800e194: 4619 mov r1, r3 800e196: 4839 ldr r0, [pc, #228] @ (800e27c ) 800e198: f002 faf6 bl 8010788 __HAL_AFIO_REMAP_USART3_PARTIAL(); 800e19c: 4b38 ldr r3, [pc, #224] @ (800e280 ) 800e19e: 685b ldr r3, [r3, #4] 800e1a0: 647b str r3, [r7, #68] @ 0x44 800e1a2: 6c7b ldr r3, [r7, #68] @ 0x44 800e1a4: f023 0330 bic.w r3, r3, #48 @ 0x30 800e1a8: 647b str r3, [r7, #68] @ 0x44 800e1aa: 6c7b ldr r3, [r7, #68] @ 0x44 800e1ac: f043 63e0 orr.w r3, r3, #117440512 @ 0x7000000 800e1b0: 647b str r3, [r7, #68] @ 0x44 800e1b2: 6c7b ldr r3, [r7, #68] @ 0x44 800e1b4: f043 0310 orr.w r3, r3, #16 800e1b8: 647b str r3, [r7, #68] @ 0x44 800e1ba: 4a31 ldr r2, [pc, #196] @ (800e280 ) 800e1bc: 6c7b ldr r3, [r7, #68] @ 0x44 800e1be: 6053 str r3, [r2, #4] hdma_usart3_rx.Instance = DMA1_Channel3; 800e1c0: 4b30 ldr r3, [pc, #192] @ (800e284 ) 800e1c2: 4a31 ldr r2, [pc, #196] @ (800e288 ) 800e1c4: 601a str r2, [r3, #0] hdma_usart3_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 800e1c6: 4b2f ldr r3, [pc, #188] @ (800e284 ) 800e1c8: 2200 movs r2, #0 800e1ca: 605a str r2, [r3, #4] hdma_usart3_rx.Init.PeriphInc = DMA_PINC_DISABLE; 800e1cc: 4b2d ldr r3, [pc, #180] @ (800e284 ) 800e1ce: 2200 movs r2, #0 800e1d0: 609a str r2, [r3, #8] hdma_usart3_rx.Init.MemInc = DMA_MINC_ENABLE; 800e1d2: 4b2c ldr r3, [pc, #176] @ (800e284 ) 800e1d4: 2280 movs r2, #128 @ 0x80 800e1d6: 60da str r2, [r3, #12] hdma_usart3_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800e1d8: 4b2a ldr r3, [pc, #168] @ (800e284 ) 800e1da: 2200 movs r2, #0 800e1dc: 611a str r2, [r3, #16] hdma_usart3_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800e1de: 4b29 ldr r3, [pc, #164] @ (800e284 ) 800e1e0: 2200 movs r2, #0 800e1e2: 615a str r2, [r3, #20] hdma_usart3_rx.Init.Mode = DMA_NORMAL; 800e1e4: 4b27 ldr r3, [pc, #156] @ (800e284 ) 800e1e6: 2200 movs r2, #0 800e1e8: 619a str r2, [r3, #24] hdma_usart3_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH; 800e1ea: 4b26 ldr r3, [pc, #152] @ (800e284 ) 800e1ec: f44f 5240 mov.w r2, #12288 @ 0x3000 800e1f0: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart3_rx) != HAL_OK) 800e1f2: 4824 ldr r0, [pc, #144] @ (800e284 ) 800e1f4: f001 fe3a bl 800fe6c 800e1f8: 4603 mov r3, r0 800e1fa: 2b00 cmp r3, #0 800e1fc: d001 beq.n 800e202 Error_Handler(); 800e1fe: f7fc fd69 bl 800acd4 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart3_rx); 800e202: 687b ldr r3, [r7, #4] 800e204: 4a1f ldr r2, [pc, #124] @ (800e284 ) 800e206: 63da str r2, [r3, #60] @ 0x3c 800e208: 4a1e ldr r2, [pc, #120] @ (800e284 ) 800e20a: 687b ldr r3, [r7, #4] 800e20c: 6253 str r3, [r2, #36] @ 0x24 hdma_usart3_tx.Instance = DMA1_Channel2; 800e20e: 4b1f ldr r3, [pc, #124] @ (800e28c ) 800e210: 4a1f ldr r2, [pc, #124] @ (800e290 ) 800e212: 601a str r2, [r3, #0] hdma_usart3_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 800e214: 4b1d ldr r3, [pc, #116] @ (800e28c ) 800e216: 2210 movs r2, #16 800e218: 605a str r2, [r3, #4] hdma_usart3_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800e21a: 4b1c ldr r3, [pc, #112] @ (800e28c ) 800e21c: 2200 movs r2, #0 800e21e: 609a str r2, [r3, #8] hdma_usart3_tx.Init.MemInc = DMA_MINC_ENABLE; 800e220: 4b1a ldr r3, [pc, #104] @ (800e28c ) 800e222: 2280 movs r2, #128 @ 0x80 800e224: 60da str r2, [r3, #12] hdma_usart3_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800e226: 4b19 ldr r3, [pc, #100] @ (800e28c ) 800e228: 2200 movs r2, #0 800e22a: 611a str r2, [r3, #16] hdma_usart3_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800e22c: 4b17 ldr r3, [pc, #92] @ (800e28c ) 800e22e: 2200 movs r2, #0 800e230: 615a str r2, [r3, #20] hdma_usart3_tx.Init.Mode = DMA_NORMAL; 800e232: 4b16 ldr r3, [pc, #88] @ (800e28c ) 800e234: 2200 movs r2, #0 800e236: 619a str r2, [r3, #24] hdma_usart3_tx.Init.Priority = DMA_PRIORITY_HIGH; 800e238: 4b14 ldr r3, [pc, #80] @ (800e28c ) 800e23a: f44f 5200 mov.w r2, #8192 @ 0x2000 800e23e: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart3_tx) != HAL_OK) 800e240: 4812 ldr r0, [pc, #72] @ (800e28c ) 800e242: f001 fe13 bl 800fe6c 800e246: 4603 mov r3, r0 800e248: 2b00 cmp r3, #0 800e24a: d001 beq.n 800e250 Error_Handler(); 800e24c: f7fc fd42 bl 800acd4 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart3_tx); 800e250: 687b ldr r3, [r7, #4] 800e252: 4a0e ldr r2, [pc, #56] @ (800e28c ) 800e254: 639a str r2, [r3, #56] @ 0x38 800e256: 4a0d ldr r2, [pc, #52] @ (800e28c ) 800e258: 687b ldr r3, [r7, #4] 800e25a: 6253 str r3, [r2, #36] @ 0x24 HAL_NVIC_SetPriority(USART3_IRQn, 2, 0); 800e25c: 2200 movs r2, #0 800e25e: 2102 movs r1, #2 800e260: 2027 movs r0, #39 @ 0x27 800e262: f001 fdb0 bl 800fdc6 HAL_NVIC_EnableIRQ(USART3_IRQn); 800e266: 2027 movs r0, #39 @ 0x27 800e268: f001 fdc9 bl 800fdfe } 800e26c: bf00 nop 800e26e: 3748 adds r7, #72 @ 0x48 800e270: 46bd mov sp, r7 800e272: bd80 pop {r7, pc} 800e274: 40004800 .word 0x40004800 800e278: 40021000 .word 0x40021000 800e27c: 40011000 .word 0x40011000 800e280: 40010000 .word 0x40010000 800e284: 20001400 .word 0x20001400 800e288: 40020030 .word 0x40020030 800e28c: 20001444 .word 0x20001444 800e290: 4002001c .word 0x4002001c 0800e294 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 800e294: f7ff fb98 bl 800d9c8 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 800e298: 480b ldr r0, [pc, #44] @ (800e2c8 ) ldr r1, =_edata 800e29a: 490c ldr r1, [pc, #48] @ (800e2cc ) ldr r2, =_sidata 800e29c: 4a0c ldr r2, [pc, #48] @ (800e2d0 ) movs r3, #0 800e29e: 2300 movs r3, #0 b LoopCopyDataInit 800e2a0: e002 b.n 800e2a8 0800e2a2 : CopyDataInit: ldr r4, [r2, r3] 800e2a2: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800e2a4: 50c4 str r4, [r0, r3] adds r3, r3, #4 800e2a6: 3304 adds r3, #4 0800e2a8 : LoopCopyDataInit: adds r4, r0, r3 800e2a8: 18c4 adds r4, r0, r3 cmp r4, r1 800e2aa: 428c cmp r4, r1 bcc CopyDataInit 800e2ac: d3f9 bcc.n 800e2a2 /* Zero fill the bss segment. */ ldr r2, =_sbss 800e2ae: 4a09 ldr r2, [pc, #36] @ (800e2d4 ) ldr r4, =_ebss 800e2b0: 4c09 ldr r4, [pc, #36] @ (800e2d8 ) movs r3, #0 800e2b2: 2300 movs r3, #0 b LoopFillZerobss 800e2b4: e001 b.n 800e2ba 0800e2b6 : FillZerobss: str r3, [r2] 800e2b6: 6013 str r3, [r2, #0] adds r2, r2, #4 800e2b8: 3204 adds r2, #4 0800e2ba : LoopFillZerobss: cmp r2, r4 800e2ba: 42a2 cmp r2, r4 bcc FillZerobss 800e2bc: d3fb bcc.n 800e2b6 /* Call static constructors */ bl __libc_init_array 800e2be: f006 fd2f bl 8014d20 <__libc_init_array> /* Call the application's entry point.*/ bl main 800e2c2: f7fc fc1d bl 800ab00
bx lr 800e2c6: 4770 bx lr ldr r0, =_sdata 800e2c8: 20000000 .word 0x20000000 ldr r1, =_edata 800e2cc: 20000258 .word 0x20000258 ldr r2, =_sidata 800e2d0: 08017d4c .word 0x08017d4c ldr r2, =_sbss 800e2d4: 20000258 .word 0x20000258 ldr r4, =_ebss 800e2d8: 200015d8 .word 0x200015d8 0800e2dc : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 800e2dc: e7fe b.n 800e2dc ... 0800e2e0 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800e2e0: b580 push {r7, lr} 800e2e2: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 800e2e4: 4b08 ldr r3, [pc, #32] @ (800e308 ) 800e2e6: 681b ldr r3, [r3, #0] 800e2e8: 4a07 ldr r2, [pc, #28] @ (800e308 ) 800e2ea: f043 0310 orr.w r3, r3, #16 800e2ee: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800e2f0: 2003 movs r0, #3 800e2f2: f001 fd5d bl 800fdb0 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800e2f6: 200f movs r0, #15 800e2f8: f000 f808 bl 800e30c /* Init the low level hardware */ HAL_MspInit(); 800e2fc: f7ff f98a bl 800d614 /* Return function status */ return HAL_OK; 800e300: 2300 movs r3, #0 } 800e302: 4618 mov r0, r3 800e304: bd80 pop {r7, pc} 800e306: bf00 nop 800e308: 40022000 .word 0x40022000 0800e30c : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800e30c: b580 push {r7, lr} 800e30e: b082 sub sp, #8 800e310: af00 add r7, sp, #0 800e312: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 800e314: 4b12 ldr r3, [pc, #72] @ (800e360 ) 800e316: 681a ldr r2, [r3, #0] 800e318: 4b12 ldr r3, [pc, #72] @ (800e364 ) 800e31a: 781b ldrb r3, [r3, #0] 800e31c: 4619 mov r1, r3 800e31e: f44f 737a mov.w r3, #1000 @ 0x3e8 800e322: fbb3 f3f1 udiv r3, r3, r1 800e326: fbb2 f3f3 udiv r3, r2, r3 800e32a: 4618 mov r0, r3 800e32c: f001 fd75 bl 800fe1a 800e330: 4603 mov r3, r0 800e332: 2b00 cmp r3, #0 800e334: d001 beq.n 800e33a { return HAL_ERROR; 800e336: 2301 movs r3, #1 800e338: e00e b.n 800e358 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800e33a: 687b ldr r3, [r7, #4] 800e33c: 2b0f cmp r3, #15 800e33e: d80a bhi.n 800e356 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800e340: 2200 movs r2, #0 800e342: 6879 ldr r1, [r7, #4] 800e344: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800e348: f001 fd3d bl 800fdc6 uwTickPrio = TickPriority; 800e34c: 4a06 ldr r2, [pc, #24] @ (800e368 ) 800e34e: 687b ldr r3, [r7, #4] 800e350: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800e352: 2300 movs r3, #0 800e354: e000 b.n 800e358 return HAL_ERROR; 800e356: 2301 movs r3, #1 } 800e358: 4618 mov r0, r3 800e35a: 3708 adds r7, #8 800e35c: 46bd mov sp, r7 800e35e: bd80 pop {r7, pc} 800e360: 20000084 .word 0x20000084 800e364: 2000008c .word 0x2000008c 800e368: 20000088 .word 0x20000088 0800e36c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800e36c: b480 push {r7} 800e36e: af00 add r7, sp, #0 uwTick += uwTickFreq; 800e370: 4b05 ldr r3, [pc, #20] @ (800e388 ) 800e372: 781b ldrb r3, [r3, #0] 800e374: 461a mov r2, r3 800e376: 4b05 ldr r3, [pc, #20] @ (800e38c ) 800e378: 681b ldr r3, [r3, #0] 800e37a: 4413 add r3, r2 800e37c: 4a03 ldr r2, [pc, #12] @ (800e38c ) 800e37e: 6013 str r3, [r2, #0] } 800e380: bf00 nop 800e382: 46bd mov sp, r7 800e384: bc80 pop {r7} 800e386: 4770 bx lr 800e388: 2000008c .word 0x2000008c 800e38c: 20001488 .word 0x20001488 0800e390 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 800e390: b480 push {r7} 800e392: af00 add r7, sp, #0 return uwTick; 800e394: 4b02 ldr r3, [pc, #8] @ (800e3a0 ) 800e396: 681b ldr r3, [r3, #0] } 800e398: 4618 mov r0, r3 800e39a: 46bd mov sp, r7 800e39c: bc80 pop {r7} 800e39e: 4770 bx lr 800e3a0: 20001488 .word 0x20001488 0800e3a4 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 800e3a4: b580 push {r7, lr} 800e3a6: b084 sub sp, #16 800e3a8: af00 add r7, sp, #0 800e3aa: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800e3ac: f7ff fff0 bl 800e390 800e3b0: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800e3b2: 687b ldr r3, [r7, #4] 800e3b4: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800e3b6: 68fb ldr r3, [r7, #12] 800e3b8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800e3bc: d005 beq.n 800e3ca { wait += (uint32_t)(uwTickFreq); 800e3be: 4b0a ldr r3, [pc, #40] @ (800e3e8 ) 800e3c0: 781b ldrb r3, [r3, #0] 800e3c2: 461a mov r2, r3 800e3c4: 68fb ldr r3, [r7, #12] 800e3c6: 4413 add r3, r2 800e3c8: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 800e3ca: bf00 nop 800e3cc: f7ff ffe0 bl 800e390 800e3d0: 4602 mov r2, r0 800e3d2: 68bb ldr r3, [r7, #8] 800e3d4: 1ad3 subs r3, r2, r3 800e3d6: 68fa ldr r2, [r7, #12] 800e3d8: 429a cmp r2, r3 800e3da: d8f7 bhi.n 800e3cc { } } 800e3dc: bf00 nop 800e3de: bf00 nop 800e3e0: 3710 adds r7, #16 800e3e2: 46bd mov sp, r7 800e3e4: bd80 pop {r7, pc} 800e3e6: bf00 nop 800e3e8: 2000008c .word 0x2000008c 0800e3ec : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 800e3ec: b580 push {r7, lr} 800e3ee: b086 sub sp, #24 800e3f0: af00 add r7, sp, #0 800e3f2: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e3f4: 2300 movs r3, #0 800e3f6: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 800e3f8: 2300 movs r3, #0 800e3fa: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 800e3fc: 2300 movs r3, #0 800e3fe: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 800e400: 2300 movs r3, #0 800e402: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 800e404: 687b ldr r3, [r7, #4] 800e406: 2b00 cmp r3, #0 800e408: d101 bne.n 800e40e { return HAL_ERROR; 800e40a: 2301 movs r3, #1 800e40c: e0be b.n 800e58c assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 800e40e: 687b ldr r3, [r7, #4] 800e410: 689b ldr r3, [r3, #8] 800e412: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 800e414: 687b ldr r3, [r7, #4] 800e416: 6a9b ldr r3, [r3, #40] @ 0x28 800e418: 2b00 cmp r3, #0 800e41a: d109 bne.n 800e430 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 800e41c: 687b ldr r3, [r7, #4] 800e41e: 2200 movs r2, #0 800e420: 62da str r2, [r3, #44] @ 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 800e422: 687b ldr r3, [r7, #4] 800e424: 2200 movs r2, #0 800e426: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800e42a: 6878 ldr r0, [r7, #4] 800e42c: f7fb f93a bl 80096a4 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800e430: 6878 ldr r0, [r7, #4] 800e432: f000 fbbd bl 800ebb0 800e436: 4603 mov r3, r0 800e438: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 800e43a: 687b ldr r3, [r7, #4] 800e43c: 6a9b ldr r3, [r3, #40] @ 0x28 800e43e: f003 0310 and.w r3, r3, #16 800e442: 2b00 cmp r3, #0 800e444: f040 8099 bne.w 800e57a 800e448: 7dfb ldrb r3, [r7, #23] 800e44a: 2b00 cmp r3, #0 800e44c: f040 8095 bne.w 800e57a (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e450: 687b ldr r3, [r7, #4] 800e452: 6a9b ldr r3, [r3, #40] @ 0x28 800e454: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800e458: f023 0302 bic.w r3, r3, #2 800e45c: f043 0202 orr.w r2, r3, #2 800e460: 687b ldr r3, [r7, #4] 800e462: 629a str r2, [r3, #40] @ 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 800e464: 687b ldr r3, [r7, #4] 800e466: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800e468: 687b ldr r3, [r7, #4] 800e46a: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 800e46c: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 800e46e: 687b ldr r3, [r7, #4] 800e470: 7b1b ldrb r3, [r3, #12] 800e472: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800e474: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 800e476: 68ba ldr r2, [r7, #8] 800e478: 4313 orrs r3, r2 800e47a: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 800e47c: 687b ldr r3, [r7, #4] 800e47e: 689b ldr r3, [r3, #8] 800e480: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e484: d003 beq.n 800e48e 800e486: 687b ldr r3, [r7, #4] 800e488: 689b ldr r3, [r3, #8] 800e48a: 2b01 cmp r3, #1 800e48c: d102 bne.n 800e494 800e48e: f44f 7380 mov.w r3, #256 @ 0x100 800e492: e000 b.n 800e496 800e494: 2300 movs r3, #0 800e496: 693a ldr r2, [r7, #16] 800e498: 4313 orrs r3, r2 800e49a: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 800e49c: 687b ldr r3, [r7, #4] 800e49e: 7d1b ldrb r3, [r3, #20] 800e4a0: 2b01 cmp r3, #1 800e4a2: d119 bne.n 800e4d8 { if (hadc->Init.ContinuousConvMode == DISABLE) 800e4a4: 687b ldr r3, [r7, #4] 800e4a6: 7b1b ldrb r3, [r3, #12] 800e4a8: 2b00 cmp r3, #0 800e4aa: d109 bne.n 800e4c0 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 800e4ac: 687b ldr r3, [r7, #4] 800e4ae: 699b ldr r3, [r3, #24] 800e4b0: 3b01 subs r3, #1 800e4b2: 035a lsls r2, r3, #13 800e4b4: 693b ldr r3, [r7, #16] 800e4b6: 4313 orrs r3, r2 800e4b8: f443 6300 orr.w r3, r3, #2048 @ 0x800 800e4bc: 613b str r3, [r7, #16] 800e4be: e00b b.n 800e4d8 { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800e4c0: 687b ldr r3, [r7, #4] 800e4c2: 6a9b ldr r3, [r3, #40] @ 0x28 800e4c4: f043 0220 orr.w r2, r3, #32 800e4c8: 687b ldr r3, [r7, #4] 800e4ca: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e4cc: 687b ldr r3, [r7, #4] 800e4ce: 6adb ldr r3, [r3, #44] @ 0x2c 800e4d0: f043 0201 orr.w r2, r3, #1 800e4d4: 687b ldr r3, [r7, #4] 800e4d6: 62da str r2, [r3, #44] @ 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 800e4d8: 687b ldr r3, [r7, #4] 800e4da: 681b ldr r3, [r3, #0] 800e4dc: 685b ldr r3, [r3, #4] 800e4de: f423 4169 bic.w r1, r3, #59648 @ 0xe900 800e4e2: 687b ldr r3, [r7, #4] 800e4e4: 681b ldr r3, [r3, #0] 800e4e6: 693a ldr r2, [r7, #16] 800e4e8: 430a orrs r2, r1 800e4ea: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 800e4ec: 687b ldr r3, [r7, #4] 800e4ee: 681b ldr r3, [r3, #0] 800e4f0: 689a ldr r2, [r3, #8] 800e4f2: 4b28 ldr r3, [pc, #160] @ (800e594 ) 800e4f4: 4013 ands r3, r2 800e4f6: 687a ldr r2, [r7, #4] 800e4f8: 6812 ldr r2, [r2, #0] 800e4fa: 68b9 ldr r1, [r7, #8] 800e4fc: 430b orrs r3, r1 800e4fe: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 800e500: 687b ldr r3, [r7, #4] 800e502: 689b ldr r3, [r3, #8] 800e504: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e508: d003 beq.n 800e512 800e50a: 687b ldr r3, [r7, #4] 800e50c: 689b ldr r3, [r3, #8] 800e50e: 2b01 cmp r3, #1 800e510: d104 bne.n 800e51c { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 800e512: 687b ldr r3, [r7, #4] 800e514: 691b ldr r3, [r3, #16] 800e516: 3b01 subs r3, #1 800e518: 051b lsls r3, r3, #20 800e51a: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 800e51c: 687b ldr r3, [r7, #4] 800e51e: 681b ldr r3, [r3, #0] 800e520: 6adb ldr r3, [r3, #44] @ 0x2c 800e522: f423 0170 bic.w r1, r3, #15728640 @ 0xf00000 800e526: 687b ldr r3, [r7, #4] 800e528: 681b ldr r3, [r3, #0] 800e52a: 68fa ldr r2, [r7, #12] 800e52c: 430a orrs r2, r1 800e52e: 62da str r2, [r3, #44] @ 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800e530: 687b ldr r3, [r7, #4] 800e532: 681b ldr r3, [r3, #0] 800e534: 689a ldr r2, [r3, #8] 800e536: 4b18 ldr r3, [pc, #96] @ (800e598 ) 800e538: 4013 ands r3, r2 800e53a: 68ba ldr r2, [r7, #8] 800e53c: 429a cmp r2, r3 800e53e: d10b bne.n 800e558 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 800e540: 687b ldr r3, [r7, #4] 800e542: 2200 movs r2, #0 800e544: 62da str r2, [r3, #44] @ 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 800e546: 687b ldr r3, [r7, #4] 800e548: 6a9b ldr r3, [r3, #40] @ 0x28 800e54a: f023 0303 bic.w r3, r3, #3 800e54e: f043 0201 orr.w r2, r3, #1 800e552: 687b ldr r3, [r7, #4] 800e554: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800e556: e018 b.n 800e58a HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800e558: 687b ldr r3, [r7, #4] 800e55a: 6a9b ldr r3, [r3, #40] @ 0x28 800e55c: f023 0312 bic.w r3, r3, #18 800e560: f043 0210 orr.w r2, r3, #16 800e564: 687b ldr r3, [r7, #4] 800e566: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800e568: 687b ldr r3, [r7, #4] 800e56a: 6adb ldr r3, [r3, #44] @ 0x2c 800e56c: f043 0201 orr.w r2, r3, #1 800e570: 687b ldr r3, [r7, #4] 800e572: 62da str r2, [r3, #44] @ 0x2c tmp_hal_status = HAL_ERROR; 800e574: 2301 movs r3, #1 800e576: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800e578: e007 b.n 800e58a } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800e57a: 687b ldr r3, [r7, #4] 800e57c: 6a9b ldr r3, [r3, #40] @ 0x28 800e57e: f043 0210 orr.w r2, r3, #16 800e582: 687b ldr r3, [r7, #4] 800e584: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800e586: 2301 movs r3, #1 800e588: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800e58a: 7dfb ldrb r3, [r7, #23] } 800e58c: 4618 mov r0, r3 800e58e: 3718 adds r7, #24 800e590: 46bd mov sp, r7 800e592: bd80 pop {r7, pc} 800e594: ffe1f7fd .word 0xffe1f7fd 800e598: ff1f0efe .word 0xff1f0efe 0800e59c : * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { 800e59c: b580 push {r7, lr} 800e59e: b086 sub sp, #24 800e5a0: af00 add r7, sp, #0 800e5a2: 60f8 str r0, [r7, #12] 800e5a4: 60b9 str r1, [r7, #8] 800e5a6: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e5a8: 2300 movs r3, #0 800e5aa: 75fb strb r3, [r7, #23] assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); /* Verification if multimode is disabled (for devices with several ADC) */ /* If multimode is enabled, dedicated function multimode conversion */ /* start DMA must be used. */ if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) 800e5ac: 68fb ldr r3, [r7, #12] 800e5ae: 681b ldr r3, [r3, #0] 800e5b0: 4a64 ldr r2, [pc, #400] @ (800e744 ) 800e5b2: 4293 cmp r3, r2 800e5b4: d004 beq.n 800e5c0 800e5b6: 68fb ldr r3, [r7, #12] 800e5b8: 681b ldr r3, [r3, #0] 800e5ba: 4a63 ldr r2, [pc, #396] @ (800e748 ) 800e5bc: 4293 cmp r3, r2 800e5be: d106 bne.n 800e5ce 800e5c0: 4b60 ldr r3, [pc, #384] @ (800e744 ) 800e5c2: 685b ldr r3, [r3, #4] 800e5c4: f403 2370 and.w r3, r3, #983040 @ 0xf0000 800e5c8: 2b00 cmp r3, #0 800e5ca: f040 80b3 bne.w 800e734 { /* Process locked */ __HAL_LOCK(hadc); 800e5ce: 68fb ldr r3, [r7, #12] 800e5d0: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800e5d4: 2b01 cmp r3, #1 800e5d6: d101 bne.n 800e5dc 800e5d8: 2302 movs r3, #2 800e5da: e0ae b.n 800e73a 800e5dc: 68fb ldr r3, [r7, #12] 800e5de: 2201 movs r2, #1 800e5e0: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 800e5e4: 68f8 ldr r0, [r7, #12] 800e5e6: f000 fa89 bl 800eafc 800e5ea: 4603 mov r3, r0 800e5ec: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800e5ee: 7dfb ldrb r3, [r7, #23] 800e5f0: 2b00 cmp r3, #0 800e5f2: f040 809a bne.w 800e72a { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 800e5f6: 68fb ldr r3, [r7, #12] 800e5f8: 6a9b ldr r3, [r3, #40] @ 0x28 800e5fa: f423 6370 bic.w r3, r3, #3840 @ 0xf00 800e5fe: f023 0301 bic.w r3, r3, #1 800e602: f443 7280 orr.w r2, r3, #256 @ 0x100 800e606: 68fb ldr r3, [r7, #12] 800e608: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 800e60a: 68fb ldr r3, [r7, #12] 800e60c: 681b ldr r3, [r3, #0] 800e60e: 4a4e ldr r2, [pc, #312] @ (800e748 ) 800e610: 4293 cmp r3, r2 800e612: d105 bne.n 800e620 800e614: 4b4b ldr r3, [pc, #300] @ (800e744 ) 800e616: 685b ldr r3, [r3, #4] 800e618: f403 2370 and.w r3, r3, #983040 @ 0xf0000 800e61c: 2b00 cmp r3, #0 800e61e: d115 bne.n 800e64c { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800e620: 68fb ldr r3, [r7, #12] 800e622: 6a9b ldr r3, [r3, #40] @ 0x28 800e624: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 800e628: 68fb ldr r3, [r7, #12] 800e62a: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800e62c: 68fb ldr r3, [r7, #12] 800e62e: 681b ldr r3, [r3, #0] 800e630: 685b ldr r3, [r3, #4] 800e632: f403 6380 and.w r3, r3, #1024 @ 0x400 800e636: 2b00 cmp r3, #0 800e638: d026 beq.n 800e688 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800e63a: 68fb ldr r3, [r7, #12] 800e63c: 6a9b ldr r3, [r3, #40] @ 0x28 800e63e: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800e642: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800e646: 68fb ldr r3, [r7, #12] 800e648: 629a str r2, [r3, #40] @ 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800e64a: e01d b.n 800e688 } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800e64c: 68fb ldr r3, [r7, #12] 800e64e: 6a9b ldr r3, [r3, #40] @ 0x28 800e650: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800e654: 68fb ldr r3, [r7, #12] 800e656: 629a str r2, [r3, #40] @ 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 800e658: 68fb ldr r3, [r7, #12] 800e65a: 681b ldr r3, [r3, #0] 800e65c: 4a39 ldr r2, [pc, #228] @ (800e744 ) 800e65e: 4293 cmp r3, r2 800e660: d004 beq.n 800e66c 800e662: 68fb ldr r3, [r7, #12] 800e664: 681b ldr r3, [r3, #0] 800e666: 4a38 ldr r2, [pc, #224] @ (800e748 ) 800e668: 4293 cmp r3, r2 800e66a: d10d bne.n 800e688 800e66c: 4b35 ldr r3, [pc, #212] @ (800e744 ) 800e66e: 685b ldr r3, [r3, #4] 800e670: f403 6380 and.w r3, r3, #1024 @ 0x400 800e674: 2b00 cmp r3, #0 800e676: d007 beq.n 800e688 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800e678: 68fb ldr r3, [r7, #12] 800e67a: 6a9b ldr r3, [r3, #40] @ 0x28 800e67c: f423 5340 bic.w r3, r3, #12288 @ 0x3000 800e680: f443 5280 orr.w r2, r3, #4096 @ 0x1000 800e684: 68fb ldr r3, [r7, #12] 800e686: 629a str r2, [r3, #40] @ 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800e688: 68fb ldr r3, [r7, #12] 800e68a: 6a9b ldr r3, [r3, #40] @ 0x28 800e68c: f403 5380 and.w r3, r3, #4096 @ 0x1000 800e690: 2b00 cmp r3, #0 800e692: d006 beq.n 800e6a2 { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 800e694: 68fb ldr r3, [r7, #12] 800e696: 6adb ldr r3, [r3, #44] @ 0x2c 800e698: f023 0206 bic.w r2, r3, #6 800e69c: 68fb ldr r3, [r7, #12] 800e69e: 62da str r2, [r3, #44] @ 0x2c 800e6a0: e002 b.n 800e6a8 } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 800e6a2: 68fb ldr r3, [r7, #12] 800e6a4: 2200 movs r2, #0 800e6a6: 62da str r2, [r3, #44] @ 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 800e6a8: 68fb ldr r3, [r7, #12] 800e6aa: 2200 movs r2, #0 800e6ac: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 800e6b0: 68fb ldr r3, [r7, #12] 800e6b2: 6a1b ldr r3, [r3, #32] 800e6b4: 4a25 ldr r2, [pc, #148] @ (800e74c ) 800e6b6: 629a str r2, [r3, #40] @ 0x28 /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 800e6b8: 68fb ldr r3, [r7, #12] 800e6ba: 6a1b ldr r3, [r3, #32] 800e6bc: 4a24 ldr r2, [pc, #144] @ (800e750 ) 800e6be: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 800e6c0: 68fb ldr r3, [r7, #12] 800e6c2: 6a1b ldr r3, [r3, #32] 800e6c4: 4a23 ldr r2, [pc, #140] @ (800e754 ) 800e6c6: 631a str r2, [r3, #48] @ 0x30 /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 800e6c8: 68fb ldr r3, [r7, #12] 800e6ca: 681b ldr r3, [r3, #0] 800e6cc: f06f 0202 mvn.w r2, #2 800e6d0: 601a str r2, [r3, #0] /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); 800e6d2: 68fb ldr r3, [r7, #12] 800e6d4: 681b ldr r3, [r3, #0] 800e6d6: 689a ldr r2, [r3, #8] 800e6d8: 68fb ldr r3, [r7, #12] 800e6da: 681b ldr r3, [r3, #0] 800e6dc: f442 7280 orr.w r2, r2, #256 @ 0x100 800e6e0: 609a str r2, [r3, #8] /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 800e6e2: 68fb ldr r3, [r7, #12] 800e6e4: 6a18 ldr r0, [r3, #32] 800e6e6: 68fb ldr r3, [r7, #12] 800e6e8: 681b ldr r3, [r3, #0] 800e6ea: 334c adds r3, #76 @ 0x4c 800e6ec: 4619 mov r1, r3 800e6ee: 68ba ldr r2, [r7, #8] 800e6f0: 687b ldr r3, [r7, #4] 800e6f2: f001 fc31 bl 800ff58 /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) 800e6f6: 68fb ldr r3, [r7, #12] 800e6f8: 681b ldr r3, [r3, #0] 800e6fa: 689b ldr r3, [r3, #8] 800e6fc: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800e700: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e704: d108 bne.n 800e718 { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 800e706: 68fb ldr r3, [r7, #12] 800e708: 681b ldr r3, [r3, #0] 800e70a: 689a ldr r2, [r3, #8] 800e70c: 68fb ldr r3, [r7, #12] 800e70e: 681b ldr r3, [r3, #0] 800e710: f442 02a0 orr.w r2, r2, #5242880 @ 0x500000 800e714: 609a str r2, [r3, #8] if (tmp_hal_status == HAL_OK) 800e716: e00f b.n 800e738 } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 800e718: 68fb ldr r3, [r7, #12] 800e71a: 681b ldr r3, [r3, #0] 800e71c: 689a ldr r2, [r3, #8] 800e71e: 68fb ldr r3, [r7, #12] 800e720: 681b ldr r3, [r3, #0] 800e722: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 800e726: 609a str r2, [r3, #8] if (tmp_hal_status == HAL_OK) 800e728: e006 b.n 800e738 } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 800e72a: 68fb ldr r3, [r7, #12] 800e72c: 2200 movs r2, #0 800e72e: f883 2024 strb.w r2, [r3, #36] @ 0x24 if (tmp_hal_status == HAL_OK) 800e732: e001 b.n 800e738 } } else { tmp_hal_status = HAL_ERROR; 800e734: 2301 movs r3, #1 800e736: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800e738: 7dfb ldrb r3, [r7, #23] } 800e73a: 4618 mov r0, r3 800e73c: 3718 adds r7, #24 800e73e: 46bd mov sp, r7 800e740: bd80 pop {r7, pc} 800e742: bf00 nop 800e744: 40012400 .word 0x40012400 800e748: 40012800 .word 0x40012800 800e74c: 0800ec33 .word 0x0800ec33 800e750: 0800ecaf .word 0x0800ecaf 800e754: 0800eccb .word 0x0800eccb 0800e758 : * @brief Handles ADC interrupt request * @param hadc: ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { 800e758: b580 push {r7, lr} 800e75a: b084 sub sp, #16 800e75c: af00 add r7, sp, #0 800e75e: 6078 str r0, [r7, #4] uint32_t tmp_sr = hadc->Instance->SR; 800e760: 687b ldr r3, [r7, #4] 800e762: 681b ldr r3, [r3, #0] 800e764: 681b ldr r3, [r3, #0] 800e766: 60fb str r3, [r7, #12] uint32_t tmp_cr1 = hadc->Instance->CR1; 800e768: 687b ldr r3, [r7, #4] 800e76a: 681b ldr r3, [r3, #0] 800e76c: 685b ldr r3, [r3, #4] 800e76e: 60bb str r3, [r7, #8] assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); /* ========== Check End of Conversion flag for regular group ========== */ if((tmp_cr1 & ADC_IT_EOC) == ADC_IT_EOC) 800e770: 68bb ldr r3, [r7, #8] 800e772: f003 0320 and.w r3, r3, #32 800e776: 2b00 cmp r3, #0 800e778: d03e beq.n 800e7f8 { if((tmp_sr & ADC_FLAG_EOC) == ADC_FLAG_EOC) 800e77a: 68fb ldr r3, [r7, #12] 800e77c: f003 0302 and.w r3, r3, #2 800e780: 2b00 cmp r3, #0 800e782: d039 beq.n 800e7f8 { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 800e784: 687b ldr r3, [r7, #4] 800e786: 6a9b ldr r3, [r3, #40] @ 0x28 800e788: f003 0310 and.w r3, r3, #16 800e78c: 2b00 cmp r3, #0 800e78e: d105 bne.n 800e79c { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800e790: 687b ldr r3, [r7, #4] 800e792: 6a9b ldr r3, [r3, #40] @ 0x28 800e794: f443 7200 orr.w r2, r3, #512 @ 0x200 800e798: 687b ldr r3, [r7, #4] 800e79a: 629a str r2, [r3, #40] @ 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e79c: 687b ldr r3, [r7, #4] 800e79e: 681b ldr r3, [r3, #0] 800e7a0: 689b ldr r3, [r3, #8] 800e7a2: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800e7a6: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e7aa: d11d bne.n 800e7e8 (hadc->Init.ContinuousConvMode == DISABLE) ) 800e7ac: 687b ldr r3, [r7, #4] 800e7ae: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e7b0: 2b00 cmp r3, #0 800e7b2: d119 bne.n 800e7e8 { /* Disable ADC end of conversion interrupt on group regular */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); 800e7b4: 687b ldr r3, [r7, #4] 800e7b6: 681b ldr r3, [r3, #0] 800e7b8: 685a ldr r2, [r3, #4] 800e7ba: 687b ldr r3, [r7, #4] 800e7bc: 681b ldr r3, [r3, #0] 800e7be: f022 0220 bic.w r2, r2, #32 800e7c2: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800e7c4: 687b ldr r3, [r7, #4] 800e7c6: 6a9b ldr r3, [r3, #40] @ 0x28 800e7c8: f423 7280 bic.w r2, r3, #256 @ 0x100 800e7cc: 687b ldr r3, [r7, #4] 800e7ce: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800e7d0: 687b ldr r3, [r7, #4] 800e7d2: 6a9b ldr r3, [r3, #40] @ 0x28 800e7d4: f403 5380 and.w r3, r3, #4096 @ 0x1000 800e7d8: 2b00 cmp r3, #0 800e7da: d105 bne.n 800e7e8 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800e7dc: 687b ldr r3, [r7, #4] 800e7de: 6a9b ldr r3, [r3, #40] @ 0x28 800e7e0: f043 0201 orr.w r2, r3, #1 800e7e4: 687b ldr r3, [r7, #4] 800e7e6: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800e7e8: 6878 ldr r0, [r7, #4] 800e7ea: f7fa feaf bl 800954c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 800e7ee: 687b ldr r3, [r7, #4] 800e7f0: 681b ldr r3, [r3, #0] 800e7f2: f06f 0212 mvn.w r2, #18 800e7f6: 601a str r2, [r3, #0] } } /* ========== Check End of Conversion flag for injected group ========== */ if((tmp_cr1 & ADC_IT_JEOC) == ADC_IT_JEOC) 800e7f8: 68bb ldr r3, [r7, #8] 800e7fa: f003 0380 and.w r3, r3, #128 @ 0x80 800e7fe: 2b00 cmp r3, #0 800e800: d04d beq.n 800e89e { if((tmp_sr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) 800e802: 68fb ldr r3, [r7, #12] 800e804: f003 0304 and.w r3, r3, #4 800e808: 2b00 cmp r3, #0 800e80a: d048 beq.n 800e89e { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 800e80c: 687b ldr r3, [r7, #4] 800e80e: 6a9b ldr r3, [r3, #40] @ 0x28 800e810: f003 0310 and.w r3, r3, #16 800e814: 2b00 cmp r3, #0 800e816: d105 bne.n 800e824 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 800e818: 687b ldr r3, [r7, #4] 800e81a: 6a9b ldr r3, [r3, #40] @ 0x28 800e81c: f443 5200 orr.w r2, r3, #8192 @ 0x2000 800e820: 687b ldr r3, [r7, #4] 800e822: 629a str r2, [r3, #40] @ 0x28 /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 800e824: 687b ldr r3, [r7, #4] 800e826: 681b ldr r3, [r3, #0] 800e828: 689b ldr r3, [r3, #8] 800e82a: f403 43e0 and.w r3, r3, #28672 @ 0x7000 800e82e: f5b3 4fe0 cmp.w r3, #28672 @ 0x7000 800e832: d012 beq.n 800e85a (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 800e834: 687b ldr r3, [r7, #4] 800e836: 681b ldr r3, [r3, #0] 800e838: 685b ldr r3, [r3, #4] 800e83a: f403 6380 and.w r3, r3, #1024 @ 0x400 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 800e83e: 2b00 cmp r3, #0 800e840: d125 bne.n 800e88e (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e842: 687b ldr r3, [r7, #4] 800e844: 681b ldr r3, [r3, #0] 800e846: 689b ldr r3, [r3, #8] 800e848: f403 2360 and.w r3, r3, #917504 @ 0xe0000 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 800e84c: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800e850: d11d bne.n 800e88e (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) 800e852: 687b ldr r3, [r7, #4] 800e854: 7b1b ldrb r3, [r3, #12] (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800e856: 2b00 cmp r3, #0 800e858: d119 bne.n 800e88e { /* Disable ADC end of conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); 800e85a: 687b ldr r3, [r7, #4] 800e85c: 681b ldr r3, [r3, #0] 800e85e: 685a ldr r2, [r3, #4] 800e860: 687b ldr r3, [r7, #4] 800e862: 681b ldr r3, [r3, #0] 800e864: f022 0280 bic.w r2, r2, #128 @ 0x80 800e868: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 800e86a: 687b ldr r3, [r7, #4] 800e86c: 6a9b ldr r3, [r3, #40] @ 0x28 800e86e: f423 5280 bic.w r2, r3, #4096 @ 0x1000 800e872: 687b ldr r3, [r7, #4] 800e874: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 800e876: 687b ldr r3, [r7, #4] 800e878: 6a9b ldr r3, [r3, #40] @ 0x28 800e87a: f403 7380 and.w r3, r3, #256 @ 0x100 800e87e: 2b00 cmp r3, #0 800e880: d105 bne.n 800e88e { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800e882: 687b ldr r3, [r7, #4] 800e884: 6a9b ldr r3, [r3, #40] @ 0x28 800e886: f043 0201 orr.w r2, r3, #1 800e88a: 687b ldr r3, [r7, #4] 800e88c: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); 800e88e: 6878 ldr r0, [r7, #4] 800e890: f000 fae4 bl 800ee5c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); 800e894: 687b ldr r3, [r7, #4] 800e896: 681b ldr r3, [r3, #0] 800e898: f06f 020c mvn.w r2, #12 800e89c: 601a str r2, [r3, #0] } } /* ========== Check Analog watchdog flags ========== */ if((tmp_cr1 & ADC_IT_AWD) == ADC_IT_AWD) 800e89e: 68bb ldr r3, [r7, #8] 800e8a0: f003 0340 and.w r3, r3, #64 @ 0x40 800e8a4: 2b00 cmp r3, #0 800e8a6: d012 beq.n 800e8ce { if((tmp_sr & ADC_FLAG_AWD) == ADC_FLAG_AWD) 800e8a8: 68fb ldr r3, [r7, #12] 800e8aa: f003 0301 and.w r3, r3, #1 800e8ae: 2b00 cmp r3, #0 800e8b0: d00d beq.n 800e8ce { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); 800e8b2: 687b ldr r3, [r7, #4] 800e8b4: 6a9b ldr r3, [r3, #40] @ 0x28 800e8b6: f443 3280 orr.w r2, r3, #65536 @ 0x10000 800e8ba: 687b ldr r3, [r7, #4] 800e8bc: 629a str r2, [r3, #40] @ 0x28 /* Level out of window callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); 800e8be: 6878 ldr r0, [r7, #4] 800e8c0: f000 f812 bl 800e8e8 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear the ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); 800e8c4: 687b ldr r3, [r7, #4] 800e8c6: 681b ldr r3, [r3, #0] 800e8c8: f06f 0201 mvn.w r2, #1 800e8cc: 601a str r2, [r3, #0] } } } 800e8ce: bf00 nop 800e8d0: 3710 adds r7, #16 800e8d2: 46bd mov sp, r7 800e8d4: bd80 pop {r7, pc} 0800e8d6 : * @brief Conversion DMA half-transfer callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) { 800e8d6: b480 push {r7} 800e8d8: b083 sub sp, #12 800e8da: af00 add r7, sp, #0 800e8dc: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 800e8de: bf00 nop 800e8e0: 370c adds r7, #12 800e8e2: 46bd mov sp, r7 800e8e4: bc80 pop {r7} 800e8e6: 4770 bx lr 0800e8e8 : * @brief Analog watchdog callback in non blocking mode. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { 800e8e8: b480 push {r7} 800e8ea: b083 sub sp, #12 800e8ec: af00 add r7, sp, #0 800e8ee: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ } 800e8f0: bf00 nop 800e8f2: 370c adds r7, #12 800e8f4: 46bd mov sp, r7 800e8f6: bc80 pop {r7} 800e8f8: 4770 bx lr 0800e8fa : * (ADC conversion with interruption or transfer by DMA) * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 800e8fa: b480 push {r7} 800e8fc: b083 sub sp, #12 800e8fe: af00 add r7, sp, #0 800e900: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 800e902: bf00 nop 800e904: 370c adds r7, #12 800e906: 46bd mov sp, r7 800e908: bc80 pop {r7} 800e90a: 4770 bx lr 0800e90c : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 800e90c: b480 push {r7} 800e90e: b085 sub sp, #20 800e910: af00 add r7, sp, #0 800e912: 6078 str r0, [r7, #4] 800e914: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800e916: 2300 movs r3, #0 800e918: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 800e91a: 2300 movs r3, #0 800e91c: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 800e91e: 687b ldr r3, [r7, #4] 800e920: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800e924: 2b01 cmp r3, #1 800e926: d101 bne.n 800e92c 800e928: 2302 movs r3, #2 800e92a: e0dc b.n 800eae6 800e92c: 687b ldr r3, [r7, #4] 800e92e: 2201 movs r2, #1 800e930: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 800e934: 683b ldr r3, [r7, #0] 800e936: 685b ldr r3, [r3, #4] 800e938: 2b06 cmp r3, #6 800e93a: d81c bhi.n 800e976 { MODIFY_REG(hadc->Instance->SQR3 , 800e93c: 687b ldr r3, [r7, #4] 800e93e: 681b ldr r3, [r3, #0] 800e940: 6b59 ldr r1, [r3, #52] @ 0x34 800e942: 683b ldr r3, [r7, #0] 800e944: 685a ldr r2, [r3, #4] 800e946: 4613 mov r3, r2 800e948: 009b lsls r3, r3, #2 800e94a: 4413 add r3, r2 800e94c: 3b05 subs r3, #5 800e94e: 221f movs r2, #31 800e950: fa02 f303 lsl.w r3, r2, r3 800e954: 43db mvns r3, r3 800e956: 4019 ands r1, r3 800e958: 683b ldr r3, [r7, #0] 800e95a: 6818 ldr r0, [r3, #0] 800e95c: 683b ldr r3, [r7, #0] 800e95e: 685a ldr r2, [r3, #4] 800e960: 4613 mov r3, r2 800e962: 009b lsls r3, r3, #2 800e964: 4413 add r3, r2 800e966: 3b05 subs r3, #5 800e968: fa00 f203 lsl.w r2, r0, r3 800e96c: 687b ldr r3, [r7, #4] 800e96e: 681b ldr r3, [r3, #0] 800e970: 430a orrs r2, r1 800e972: 635a str r2, [r3, #52] @ 0x34 800e974: e03c b.n 800e9f0 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 800e976: 683b ldr r3, [r7, #0] 800e978: 685b ldr r3, [r3, #4] 800e97a: 2b0c cmp r3, #12 800e97c: d81c bhi.n 800e9b8 { MODIFY_REG(hadc->Instance->SQR2 , 800e97e: 687b ldr r3, [r7, #4] 800e980: 681b ldr r3, [r3, #0] 800e982: 6b19 ldr r1, [r3, #48] @ 0x30 800e984: 683b ldr r3, [r7, #0] 800e986: 685a ldr r2, [r3, #4] 800e988: 4613 mov r3, r2 800e98a: 009b lsls r3, r3, #2 800e98c: 4413 add r3, r2 800e98e: 3b23 subs r3, #35 @ 0x23 800e990: 221f movs r2, #31 800e992: fa02 f303 lsl.w r3, r2, r3 800e996: 43db mvns r3, r3 800e998: 4019 ands r1, r3 800e99a: 683b ldr r3, [r7, #0] 800e99c: 6818 ldr r0, [r3, #0] 800e99e: 683b ldr r3, [r7, #0] 800e9a0: 685a ldr r2, [r3, #4] 800e9a2: 4613 mov r3, r2 800e9a4: 009b lsls r3, r3, #2 800e9a6: 4413 add r3, r2 800e9a8: 3b23 subs r3, #35 @ 0x23 800e9aa: fa00 f203 lsl.w r2, r0, r3 800e9ae: 687b ldr r3, [r7, #4] 800e9b0: 681b ldr r3, [r3, #0] 800e9b2: 430a orrs r2, r1 800e9b4: 631a str r2, [r3, #48] @ 0x30 800e9b6: e01b b.n 800e9f0 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 800e9b8: 687b ldr r3, [r7, #4] 800e9ba: 681b ldr r3, [r3, #0] 800e9bc: 6ad9 ldr r1, [r3, #44] @ 0x2c 800e9be: 683b ldr r3, [r7, #0] 800e9c0: 685a ldr r2, [r3, #4] 800e9c2: 4613 mov r3, r2 800e9c4: 009b lsls r3, r3, #2 800e9c6: 4413 add r3, r2 800e9c8: 3b41 subs r3, #65 @ 0x41 800e9ca: 221f movs r2, #31 800e9cc: fa02 f303 lsl.w r3, r2, r3 800e9d0: 43db mvns r3, r3 800e9d2: 4019 ands r1, r3 800e9d4: 683b ldr r3, [r7, #0] 800e9d6: 6818 ldr r0, [r3, #0] 800e9d8: 683b ldr r3, [r7, #0] 800e9da: 685a ldr r2, [r3, #4] 800e9dc: 4613 mov r3, r2 800e9de: 009b lsls r3, r3, #2 800e9e0: 4413 add r3, r2 800e9e2: 3b41 subs r3, #65 @ 0x41 800e9e4: fa00 f203 lsl.w r2, r0, r3 800e9e8: 687b ldr r3, [r7, #4] 800e9ea: 681b ldr r3, [r3, #0] 800e9ec: 430a orrs r2, r1 800e9ee: 62da str r2, [r3, #44] @ 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 800e9f0: 683b ldr r3, [r7, #0] 800e9f2: 681b ldr r3, [r3, #0] 800e9f4: 2b09 cmp r3, #9 800e9f6: d91c bls.n 800ea32 { MODIFY_REG(hadc->Instance->SMPR1 , 800e9f8: 687b ldr r3, [r7, #4] 800e9fa: 681b ldr r3, [r3, #0] 800e9fc: 68d9 ldr r1, [r3, #12] 800e9fe: 683b ldr r3, [r7, #0] 800ea00: 681a ldr r2, [r3, #0] 800ea02: 4613 mov r3, r2 800ea04: 005b lsls r3, r3, #1 800ea06: 4413 add r3, r2 800ea08: 3b1e subs r3, #30 800ea0a: 2207 movs r2, #7 800ea0c: fa02 f303 lsl.w r3, r2, r3 800ea10: 43db mvns r3, r3 800ea12: 4019 ands r1, r3 800ea14: 683b ldr r3, [r7, #0] 800ea16: 6898 ldr r0, [r3, #8] 800ea18: 683b ldr r3, [r7, #0] 800ea1a: 681a ldr r2, [r3, #0] 800ea1c: 4613 mov r3, r2 800ea1e: 005b lsls r3, r3, #1 800ea20: 4413 add r3, r2 800ea22: 3b1e subs r3, #30 800ea24: fa00 f203 lsl.w r2, r0, r3 800ea28: 687b ldr r3, [r7, #4] 800ea2a: 681b ldr r3, [r3, #0] 800ea2c: 430a orrs r2, r1 800ea2e: 60da str r2, [r3, #12] 800ea30: e019 b.n 800ea66 ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 800ea32: 687b ldr r3, [r7, #4] 800ea34: 681b ldr r3, [r3, #0] 800ea36: 6919 ldr r1, [r3, #16] 800ea38: 683b ldr r3, [r7, #0] 800ea3a: 681a ldr r2, [r3, #0] 800ea3c: 4613 mov r3, r2 800ea3e: 005b lsls r3, r3, #1 800ea40: 4413 add r3, r2 800ea42: 2207 movs r2, #7 800ea44: fa02 f303 lsl.w r3, r2, r3 800ea48: 43db mvns r3, r3 800ea4a: 4019 ands r1, r3 800ea4c: 683b ldr r3, [r7, #0] 800ea4e: 6898 ldr r0, [r3, #8] 800ea50: 683b ldr r3, [r7, #0] 800ea52: 681a ldr r2, [r3, #0] 800ea54: 4613 mov r3, r2 800ea56: 005b lsls r3, r3, #1 800ea58: 4413 add r3, r2 800ea5a: fa00 f203 lsl.w r2, r0, r3 800ea5e: 687b ldr r3, [r7, #4] 800ea60: 681b ldr r3, [r3, #0] 800ea62: 430a orrs r2, r1 800ea64: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800ea66: 683b ldr r3, [r7, #0] 800ea68: 681b ldr r3, [r3, #0] 800ea6a: 2b10 cmp r3, #16 800ea6c: d003 beq.n 800ea76 (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 800ea6e: 683b ldr r3, [r7, #0] 800ea70: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800ea72: 2b11 cmp r3, #17 800ea74: d132 bne.n 800eadc { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 800ea76: 687b ldr r3, [r7, #4] 800ea78: 681b ldr r3, [r3, #0] 800ea7a: 4a1d ldr r2, [pc, #116] @ (800eaf0 ) 800ea7c: 4293 cmp r3, r2 800ea7e: d125 bne.n 800eacc { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 800ea80: 687b ldr r3, [r7, #4] 800ea82: 681b ldr r3, [r3, #0] 800ea84: 689b ldr r3, [r3, #8] 800ea86: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800ea8a: 2b00 cmp r3, #0 800ea8c: d126 bne.n 800eadc { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 800ea8e: 687b ldr r3, [r7, #4] 800ea90: 681b ldr r3, [r3, #0] 800ea92: 689a ldr r2, [r3, #8] 800ea94: 687b ldr r3, [r7, #4] 800ea96: 681b ldr r3, [r3, #0] 800ea98: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 800ea9c: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 800ea9e: 683b ldr r3, [r7, #0] 800eaa0: 681b ldr r3, [r3, #0] 800eaa2: 2b10 cmp r3, #16 800eaa4: d11a bne.n 800eadc { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 800eaa6: 4b13 ldr r3, [pc, #76] @ (800eaf4 ) 800eaa8: 681b ldr r3, [r3, #0] 800eaaa: 4a13 ldr r2, [pc, #76] @ (800eaf8 ) 800eaac: fba2 2303 umull r2, r3, r2, r3 800eab0: 0c9a lsrs r2, r3, #18 800eab2: 4613 mov r3, r2 800eab4: 009b lsls r3, r3, #2 800eab6: 4413 add r3, r2 800eab8: 005b lsls r3, r3, #1 800eaba: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800eabc: e002 b.n 800eac4 { wait_loop_index--; 800eabe: 68bb ldr r3, [r7, #8] 800eac0: 3b01 subs r3, #1 800eac2: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800eac4: 68bb ldr r3, [r7, #8] 800eac6: 2b00 cmp r3, #0 800eac8: d1f9 bne.n 800eabe 800eaca: e007 b.n 800eadc } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800eacc: 687b ldr r3, [r7, #4] 800eace: 6a9b ldr r3, [r3, #40] @ 0x28 800ead0: f043 0220 orr.w r2, r3, #32 800ead4: 687b ldr r3, [r7, #4] 800ead6: 629a str r2, [r3, #40] @ 0x28 tmp_hal_status = HAL_ERROR; 800ead8: 2301 movs r3, #1 800eada: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 800eadc: 687b ldr r3, [r7, #4] 800eade: 2200 movs r2, #0 800eae0: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800eae4: 7bfb ldrb r3, [r7, #15] } 800eae6: 4618 mov r0, r3 800eae8: 3714 adds r7, #20 800eaea: 46bd mov sp, r7 800eaec: bc80 pop {r7} 800eaee: 4770 bx lr 800eaf0: 40012400 .word 0x40012400 800eaf4: 20000084 .word 0x20000084 800eaf8: 431bde83 .word 0x431bde83 0800eafc : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 800eafc: b580 push {r7, lr} 800eafe: b084 sub sp, #16 800eb00: af00 add r7, sp, #0 800eb02: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800eb04: 2300 movs r3, #0 800eb06: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 800eb08: 2300 movs r3, #0 800eb0a: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 800eb0c: 687b ldr r3, [r7, #4] 800eb0e: 681b ldr r3, [r3, #0] 800eb10: 689b ldr r3, [r3, #8] 800eb12: f003 0301 and.w r3, r3, #1 800eb16: 2b01 cmp r3, #1 800eb18: d040 beq.n 800eb9c { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 800eb1a: 687b ldr r3, [r7, #4] 800eb1c: 681b ldr r3, [r3, #0] 800eb1e: 689a ldr r2, [r3, #8] 800eb20: 687b ldr r3, [r7, #4] 800eb22: 681b ldr r3, [r3, #0] 800eb24: f042 0201 orr.w r2, r2, #1 800eb28: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 800eb2a: 4b1f ldr r3, [pc, #124] @ (800eba8 ) 800eb2c: 681b ldr r3, [r3, #0] 800eb2e: 4a1f ldr r2, [pc, #124] @ (800ebac ) 800eb30: fba2 2303 umull r2, r3, r2, r3 800eb34: 0c9b lsrs r3, r3, #18 800eb36: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800eb38: e002 b.n 800eb40 { wait_loop_index--; 800eb3a: 68bb ldr r3, [r7, #8] 800eb3c: 3b01 subs r3, #1 800eb3e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800eb40: 68bb ldr r3, [r7, #8] 800eb42: 2b00 cmp r3, #0 800eb44: d1f9 bne.n 800eb3a } /* Get tick count */ tickstart = HAL_GetTick(); 800eb46: f7ff fc23 bl 800e390 800eb4a: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 800eb4c: e01f b.n 800eb8e { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 800eb4e: f7ff fc1f bl 800e390 800eb52: 4602 mov r2, r0 800eb54: 68fb ldr r3, [r7, #12] 800eb56: 1ad3 subs r3, r2, r3 800eb58: 2b02 cmp r3, #2 800eb5a: d918 bls.n 800eb8e { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) 800eb5c: 687b ldr r3, [r7, #4] 800eb5e: 681b ldr r3, [r3, #0] 800eb60: 689b ldr r3, [r3, #8] 800eb62: f003 0301 and.w r3, r3, #1 800eb66: 2b01 cmp r3, #1 800eb68: d011 beq.n 800eb8e { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800eb6a: 687b ldr r3, [r7, #4] 800eb6c: 6a9b ldr r3, [r3, #40] @ 0x28 800eb6e: f043 0210 orr.w r2, r3, #16 800eb72: 687b ldr r3, [r7, #4] 800eb74: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800eb76: 687b ldr r3, [r7, #4] 800eb78: 6adb ldr r3, [r3, #44] @ 0x2c 800eb7a: f043 0201 orr.w r2, r3, #1 800eb7e: 687b ldr r3, [r7, #4] 800eb80: 62da str r2, [r3, #44] @ 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 800eb82: 687b ldr r3, [r7, #4] 800eb84: 2200 movs r2, #0 800eb86: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800eb8a: 2301 movs r3, #1 800eb8c: e007 b.n 800eb9e while(ADC_IS_ENABLE(hadc) == RESET) 800eb8e: 687b ldr r3, [r7, #4] 800eb90: 681b ldr r3, [r3, #0] 800eb92: 689b ldr r3, [r3, #8] 800eb94: f003 0301 and.w r3, r3, #1 800eb98: 2b01 cmp r3, #1 800eb9a: d1d8 bne.n 800eb4e } } } /* Return HAL status */ return HAL_OK; 800eb9c: 2300 movs r3, #0 } 800eb9e: 4618 mov r0, r3 800eba0: 3710 adds r7, #16 800eba2: 46bd mov sp, r7 800eba4: bd80 pop {r7, pc} 800eba6: bf00 nop 800eba8: 20000084 .word 0x20000084 800ebac: 431bde83 .word 0x431bde83 0800ebb0 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 800ebb0: b580 push {r7, lr} 800ebb2: b084 sub sp, #16 800ebb4: af00 add r7, sp, #0 800ebb6: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800ebb8: 2300 movs r3, #0 800ebba: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 800ebbc: 687b ldr r3, [r7, #4] 800ebbe: 681b ldr r3, [r3, #0] 800ebc0: 689b ldr r3, [r3, #8] 800ebc2: f003 0301 and.w r3, r3, #1 800ebc6: 2b01 cmp r3, #1 800ebc8: d12e bne.n 800ec28 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 800ebca: 687b ldr r3, [r7, #4] 800ebcc: 681b ldr r3, [r3, #0] 800ebce: 689a ldr r2, [r3, #8] 800ebd0: 687b ldr r3, [r7, #4] 800ebd2: 681b ldr r3, [r3, #0] 800ebd4: f022 0201 bic.w r2, r2, #1 800ebd8: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 800ebda: f7ff fbd9 bl 800e390 800ebde: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 800ebe0: e01b b.n 800ec1a { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800ebe2: f7ff fbd5 bl 800e390 800ebe6: 4602 mov r2, r0 800ebe8: 68fb ldr r3, [r7, #12] 800ebea: 1ad3 subs r3, r2, r3 800ebec: 2b02 cmp r3, #2 800ebee: d914 bls.n 800ec1a { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 800ebf0: 687b ldr r3, [r7, #4] 800ebf2: 681b ldr r3, [r3, #0] 800ebf4: 689b ldr r3, [r3, #8] 800ebf6: f003 0301 and.w r3, r3, #1 800ebfa: 2b01 cmp r3, #1 800ebfc: d10d bne.n 800ec1a { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800ebfe: 687b ldr r3, [r7, #4] 800ec00: 6a9b ldr r3, [r3, #40] @ 0x28 800ec02: f043 0210 orr.w r2, r3, #16 800ec06: 687b ldr r3, [r7, #4] 800ec08: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800ec0a: 687b ldr r3, [r7, #4] 800ec0c: 6adb ldr r3, [r3, #44] @ 0x2c 800ec0e: f043 0201 orr.w r2, r3, #1 800ec12: 687b ldr r3, [r7, #4] 800ec14: 62da str r2, [r3, #44] @ 0x2c return HAL_ERROR; 800ec16: 2301 movs r3, #1 800ec18: e007 b.n 800ec2a while(ADC_IS_ENABLE(hadc) != RESET) 800ec1a: 687b ldr r3, [r7, #4] 800ec1c: 681b ldr r3, [r3, #0] 800ec1e: 689b ldr r3, [r3, #8] 800ec20: f003 0301 and.w r3, r3, #1 800ec24: 2b01 cmp r3, #1 800ec26: d0dc beq.n 800ebe2 } } } /* Return HAL status */ return HAL_OK; 800ec28: 2300 movs r3, #0 } 800ec2a: 4618 mov r0, r3 800ec2c: 3710 adds r7, #16 800ec2e: 46bd mov sp, r7 800ec30: bd80 pop {r7, pc} 0800ec32 : * @brief DMA transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 800ec32: b580 push {r7, lr} 800ec34: b084 sub sp, #16 800ec36: af00 add r7, sp, #0 800ec38: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800ec3a: 687b ldr r3, [r7, #4] 800ec3c: 6a5b ldr r3, [r3, #36] @ 0x24 800ec3e: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) 800ec40: 68fb ldr r3, [r7, #12] 800ec42: 6a9b ldr r3, [r3, #40] @ 0x28 800ec44: f003 0350 and.w r3, r3, #80 @ 0x50 800ec48: 2b00 cmp r3, #0 800ec4a: d127 bne.n 800ec9c { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800ec4c: 68fb ldr r3, [r7, #12] 800ec4e: 6a9b ldr r3, [r3, #40] @ 0x28 800ec50: f443 7200 orr.w r2, r3, #512 @ 0x200 800ec54: 68fb ldr r3, [r7, #12] 800ec56: 629a str r2, [r3, #40] @ 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800ec58: 68fb ldr r3, [r7, #12] 800ec5a: 681b ldr r3, [r3, #0] 800ec5c: 689b ldr r3, [r3, #8] 800ec5e: f403 2360 and.w r3, r3, #917504 @ 0xe0000 800ec62: f5b3 2f60 cmp.w r3, #917504 @ 0xe0000 800ec66: d115 bne.n 800ec94 (hadc->Init.ContinuousConvMode == DISABLE) ) 800ec68: 68fb ldr r3, [r7, #12] 800ec6a: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800ec6c: 2b00 cmp r3, #0 800ec6e: d111 bne.n 800ec94 { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800ec70: 68fb ldr r3, [r7, #12] 800ec72: 6a9b ldr r3, [r3, #40] @ 0x28 800ec74: f423 7280 bic.w r2, r3, #256 @ 0x100 800ec78: 68fb ldr r3, [r7, #12] 800ec7a: 629a str r2, [r3, #40] @ 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800ec7c: 68fb ldr r3, [r7, #12] 800ec7e: 6a9b ldr r3, [r3, #40] @ 0x28 800ec80: f403 5380 and.w r3, r3, #4096 @ 0x1000 800ec84: 2b00 cmp r3, #0 800ec86: d105 bne.n 800ec94 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800ec88: 68fb ldr r3, [r7, #12] 800ec8a: 6a9b ldr r3, [r3, #40] @ 0x28 800ec8c: f043 0201 orr.w r2, r3, #1 800ec90: 68fb ldr r3, [r7, #12] 800ec92: 629a str r2, [r3, #40] @ 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800ec94: 68f8 ldr r0, [r7, #12] 800ec96: f7fa fc59 bl 800954c else { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } 800ec9a: e004 b.n 800eca6 hadc->DMA_Handle->XferErrorCallback(hdma); 800ec9c: 68fb ldr r3, [r7, #12] 800ec9e: 6a1b ldr r3, [r3, #32] 800eca0: 6b1b ldr r3, [r3, #48] @ 0x30 800eca2: 6878 ldr r0, [r7, #4] 800eca4: 4798 blx r3 } 800eca6: bf00 nop 800eca8: 3710 adds r7, #16 800ecaa: 46bd mov sp, r7 800ecac: bd80 pop {r7, pc} 0800ecae : * @brief DMA half transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 800ecae: b580 push {r7, lr} 800ecb0: b084 sub sp, #16 800ecb2: af00 add r7, sp, #0 800ecb4: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800ecb6: 687b ldr r3, [r7, #4] 800ecb8: 6a5b ldr r3, [r3, #36] @ 0x24 800ecba: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 800ecbc: 68f8 ldr r0, [r7, #12] 800ecbe: f7ff fe0a bl 800e8d6 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800ecc2: bf00 nop 800ecc4: 3710 adds r7, #16 800ecc6: 46bd mov sp, r7 800ecc8: bd80 pop {r7, pc} 0800ecca : * @brief DMA error callback * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 800ecca: b580 push {r7, lr} 800eccc: b084 sub sp, #16 800ecce: af00 add r7, sp, #0 800ecd0: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800ecd2: 687b ldr r3, [r7, #4] 800ecd4: 6a5b ldr r3, [r3, #36] @ 0x24 800ecd6: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 800ecd8: 68fb ldr r3, [r7, #12] 800ecda: 6a9b ldr r3, [r3, #40] @ 0x28 800ecdc: f043 0240 orr.w r2, r3, #64 @ 0x40 800ece0: 68fb ldr r3, [r7, #12] 800ece2: 629a str r2, [r3, #40] @ 0x28 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 800ece4: 68fb ldr r3, [r7, #12] 800ece6: 6adb ldr r3, [r3, #44] @ 0x2c 800ece8: f043 0204 orr.w r2, r3, #4 800ecec: 68fb ldr r3, [r7, #12] 800ecee: 62da str r2, [r3, #44] @ 0x2c /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 800ecf0: 68f8 ldr r0, [r7, #12] 800ecf2: f7ff fe02 bl 800e8fa #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800ecf6: bf00 nop 800ecf8: 3710 adds r7, #16 800ecfa: 46bd mov sp, r7 800ecfc: bd80 pop {r7, pc} ... 0800ed00 : * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { 800ed00: b590 push {r4, r7, lr} 800ed02: b087 sub sp, #28 800ed04: af00 add r7, sp, #0 800ed06: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800ed08: 2300 movs r3, #0 800ed0a: 75fb strb r3, [r7, #23] uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; 800ed0c: 2300 movs r3, #0 800ed0e: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800ed10: 687b ldr r3, [r7, #4] 800ed12: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800ed16: 2b01 cmp r3, #1 800ed18: d101 bne.n 800ed1e 800ed1a: 2302 movs r3, #2 800ed1c: e097 b.n 800ee4e 800ed1e: 687b ldr r3, [r7, #4] 800ed20: 2201 movs r2, #1 800ed22: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* 1. Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800ed26: 6878 ldr r0, [r7, #4] 800ed28: f7ff ff42 bl 800ebb0 800ed2c: 4603 mov r3, r0 800ed2e: 75fb strb r3, [r7, #23] /* 2. Calibration prerequisite delay before starting the calibration. */ /* - ADC must be enabled for at least two ADC clock cycles */ tmp_hal_status = ADC_Enable(hadc); 800ed30: 6878 ldr r0, [r7, #4] 800ed32: f7ff fee3 bl 800eafc 800ed36: 4603 mov r3, r0 800ed38: 75fb strb r3, [r7, #23] /* Check if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800ed3a: 7dfb ldrb r3, [r7, #23] 800ed3c: 2b00 cmp r3, #0 800ed3e: f040 8081 bne.w 800ee44 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800ed42: 687b ldr r3, [r7, #4] 800ed44: 6a9b ldr r3, [r3, #40] @ 0x28 800ed46: f423 5388 bic.w r3, r3, #4352 @ 0x1100 800ed4a: f023 0302 bic.w r3, r3, #2 800ed4e: f043 0202 orr.w r2, r3, #2 800ed52: 687b ldr r3, [r7, #4] 800ed54: 629a str r2, [r3, #40] @ 0x28 /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 800ed56: 4b40 ldr r3, [pc, #256] @ (800ee58 ) 800ed58: 681c ldr r4, [r3, #0] 800ed5a: 2002 movs r0, #2 800ed5c: f002 fde2 bl 8011924 800ed60: 4603 mov r3, r0 800ed62: fbb4 f3f3 udiv r3, r4, r3 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); 800ed66: 005b lsls r3, r3, #1 wait_loop_index = ((SystemCoreClock 800ed68: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800ed6a: e002 b.n 800ed72 { wait_loop_index--; 800ed6c: 68fb ldr r3, [r7, #12] 800ed6e: 3b01 subs r3, #1 800ed70: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800ed72: 68fb ldr r3, [r7, #12] 800ed74: 2b00 cmp r3, #0 800ed76: d1f9 bne.n 800ed6c } /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); 800ed78: 687b ldr r3, [r7, #4] 800ed7a: 681b ldr r3, [r3, #0] 800ed7c: 689a ldr r2, [r3, #8] 800ed7e: 687b ldr r3, [r7, #4] 800ed80: 681b ldr r3, [r3, #0] 800ed82: f042 0208 orr.w r2, r2, #8 800ed86: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800ed88: f7ff fb02 bl 800e390 800ed8c: 6138 str r0, [r7, #16] /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800ed8e: e01b b.n 800edc8 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800ed90: f7ff fafe bl 800e390 800ed94: 4602 mov r2, r0 800ed96: 693b ldr r3, [r7, #16] 800ed98: 1ad3 subs r3, r2, r3 800ed9a: 2b0a cmp r3, #10 800ed9c: d914 bls.n 800edc8 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800ed9e: 687b ldr r3, [r7, #4] 800eda0: 681b ldr r3, [r3, #0] 800eda2: 689b ldr r3, [r3, #8] 800eda4: f003 0308 and.w r3, r3, #8 800eda8: 2b00 cmp r3, #0 800edaa: d00d beq.n 800edc8 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800edac: 687b ldr r3, [r7, #4] 800edae: 6a9b ldr r3, [r3, #40] @ 0x28 800edb0: f023 0312 bic.w r3, r3, #18 800edb4: f043 0210 orr.w r2, r3, #16 800edb8: 687b ldr r3, [r7, #4] 800edba: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800edbc: 687b ldr r3, [r7, #4] 800edbe: 2200 movs r2, #0 800edc0: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800edc4: 2301 movs r3, #1 800edc6: e042 b.n 800ee4e while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800edc8: 687b ldr r3, [r7, #4] 800edca: 681b ldr r3, [r3, #0] 800edcc: 689b ldr r3, [r3, #8] 800edce: f003 0308 and.w r3, r3, #8 800edd2: 2b00 cmp r3, #0 800edd4: d1dc bne.n 800ed90 } } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); 800edd6: 687b ldr r3, [r7, #4] 800edd8: 681b ldr r3, [r3, #0] 800edda: 689a ldr r2, [r3, #8] 800eddc: 687b ldr r3, [r7, #4] 800edde: 681b ldr r3, [r3, #0] 800ede0: f042 0204 orr.w r2, r2, #4 800ede4: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800ede6: f7ff fad3 bl 800e390 800edea: 6138 str r0, [r7, #16] /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800edec: e01b b.n 800ee26 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800edee: f7ff facf bl 800e390 800edf2: 4602 mov r2, r0 800edf4: 693b ldr r3, [r7, #16] 800edf6: 1ad3 subs r3, r2, r3 800edf8: 2b0a cmp r3, #10 800edfa: d914 bls.n 800ee26 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800edfc: 687b ldr r3, [r7, #4] 800edfe: 681b ldr r3, [r3, #0] 800ee00: 689b ldr r3, [r3, #8] 800ee02: f003 0304 and.w r3, r3, #4 800ee06: 2b00 cmp r3, #0 800ee08: d00d beq.n 800ee26 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800ee0a: 687b ldr r3, [r7, #4] 800ee0c: 6a9b ldr r3, [r3, #40] @ 0x28 800ee0e: f023 0312 bic.w r3, r3, #18 800ee12: f043 0210 orr.w r2, r3, #16 800ee16: 687b ldr r3, [r7, #4] 800ee18: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800ee1a: 687b ldr r3, [r7, #4] 800ee1c: 2200 movs r2, #0 800ee1e: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 800ee22: 2301 movs r3, #1 800ee24: e013 b.n 800ee4e while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800ee26: 687b ldr r3, [r7, #4] 800ee28: 681b ldr r3, [r3, #0] 800ee2a: 689b ldr r3, [r3, #8] 800ee2c: f003 0304 and.w r3, r3, #4 800ee30: 2b00 cmp r3, #0 800ee32: d1dc bne.n 800edee } } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800ee34: 687b ldr r3, [r7, #4] 800ee36: 6a9b ldr r3, [r3, #40] @ 0x28 800ee38: f023 0303 bic.w r3, r3, #3 800ee3c: f043 0201 orr.w r2, r3, #1 800ee40: 687b ldr r3, [r7, #4] 800ee42: 629a str r2, [r3, #40] @ 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 800ee44: 687b ldr r3, [r7, #4] 800ee46: 2200 movs r2, #0 800ee48: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Return function status */ return tmp_hal_status; 800ee4c: 7dfb ldrb r3, [r7, #23] } 800ee4e: 4618 mov r0, r3 800ee50: 371c adds r7, #28 800ee52: 46bd mov sp, r7 800ee54: bd90 pop {r4, r7, pc} 800ee56: bf00 nop 800ee58: 20000084 .word 0x20000084 0800ee5c : * @brief Injected conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { 800ee5c: b480 push {r7} 800ee5e: b083 sub sp, #12 800ee60: af00 add r7, sp, #0 800ee62: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } 800ee64: bf00 nop 800ee66: 370c adds r7, #12 800ee68: 46bd mov sp, r7 800ee6a: bc80 pop {r7} 800ee6c: 4770 bx lr 0800ee6e : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { 800ee6e: b580 push {r7, lr} 800ee70: b084 sub sp, #16 800ee72: af00 add r7, sp, #0 800ee74: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) 800ee76: 687b ldr r3, [r7, #4] 800ee78: 2b00 cmp r3, #0 800ee7a: d101 bne.n 800ee80 { return HAL_ERROR; 800ee7c: 2301 movs r3, #1 800ee7e: e0ed b.n 800f05c /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); } #else if (hcan->State == HAL_CAN_STATE_RESET) 800ee80: 687b ldr r3, [r7, #4] 800ee82: f893 3020 ldrb.w r3, [r3, #32] 800ee86: b2db uxtb r3, r3 800ee88: 2b00 cmp r3, #0 800ee8a: d102 bne.n 800ee92 { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); 800ee8c: 6878 ldr r0, [r7, #4] 800ee8e: f7fa fef3 bl 8009c78 } #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800ee92: 687b ldr r3, [r7, #4] 800ee94: 681b ldr r3, [r3, #0] 800ee96: 681a ldr r2, [r3, #0] 800ee98: 687b ldr r3, [r7, #4] 800ee9a: 681b ldr r3, [r3, #0] 800ee9c: f042 0201 orr.w r2, r2, #1 800eea0: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800eea2: f7ff fa75 bl 800e390 800eea6: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800eea8: e012 b.n 800eed0 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800eeaa: f7ff fa71 bl 800e390 800eeae: 4602 mov r2, r0 800eeb0: 68fb ldr r3, [r7, #12] 800eeb2: 1ad3 subs r3, r2, r3 800eeb4: 2b0a cmp r3, #10 800eeb6: d90b bls.n 800eed0 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800eeb8: 687b ldr r3, [r7, #4] 800eeba: 6a5b ldr r3, [r3, #36] @ 0x24 800eebc: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800eec0: 687b ldr r3, [r7, #4] 800eec2: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800eec4: 687b ldr r3, [r7, #4] 800eec6: 2205 movs r2, #5 800eec8: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800eecc: 2301 movs r3, #1 800eece: e0c5 b.n 800f05c while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800eed0: 687b ldr r3, [r7, #4] 800eed2: 681b ldr r3, [r3, #0] 800eed4: 685b ldr r3, [r3, #4] 800eed6: f003 0301 and.w r3, r3, #1 800eeda: 2b00 cmp r3, #0 800eedc: d0e5 beq.n 800eeaa } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800eede: 687b ldr r3, [r7, #4] 800eee0: 681b ldr r3, [r3, #0] 800eee2: 681a ldr r2, [r3, #0] 800eee4: 687b ldr r3, [r7, #4] 800eee6: 681b ldr r3, [r3, #0] 800eee8: f022 0202 bic.w r2, r2, #2 800eeec: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800eeee: f7ff fa4f bl 800e390 800eef2: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800eef4: e012 b.n 800ef1c { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800eef6: f7ff fa4b bl 800e390 800eefa: 4602 mov r2, r0 800eefc: 68fb ldr r3, [r7, #12] 800eefe: 1ad3 subs r3, r2, r3 800ef00: 2b0a cmp r3, #10 800ef02: d90b bls.n 800ef1c { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800ef04: 687b ldr r3, [r7, #4] 800ef06: 6a5b ldr r3, [r3, #36] @ 0x24 800ef08: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800ef0c: 687b ldr r3, [r7, #4] 800ef0e: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800ef10: 687b ldr r3, [r7, #4] 800ef12: 2205 movs r2, #5 800ef14: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800ef18: 2301 movs r3, #1 800ef1a: e09f b.n 800f05c while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800ef1c: 687b ldr r3, [r7, #4] 800ef1e: 681b ldr r3, [r3, #0] 800ef20: 685b ldr r3, [r3, #4] 800ef22: f003 0302 and.w r3, r3, #2 800ef26: 2b00 cmp r3, #0 800ef28: d1e5 bne.n 800eef6 } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) 800ef2a: 687b ldr r3, [r7, #4] 800ef2c: 7e1b ldrb r3, [r3, #24] 800ef2e: 2b01 cmp r3, #1 800ef30: d108 bne.n 800ef44 { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800ef32: 687b ldr r3, [r7, #4] 800ef34: 681b ldr r3, [r3, #0] 800ef36: 681a ldr r2, [r3, #0] 800ef38: 687b ldr r3, [r7, #4] 800ef3a: 681b ldr r3, [r3, #0] 800ef3c: f042 0280 orr.w r2, r2, #128 @ 0x80 800ef40: 601a str r2, [r3, #0] 800ef42: e007 b.n 800ef54 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800ef44: 687b ldr r3, [r7, #4] 800ef46: 681b ldr r3, [r3, #0] 800ef48: 681a ldr r2, [r3, #0] 800ef4a: 687b ldr r3, [r7, #4] 800ef4c: 681b ldr r3, [r3, #0] 800ef4e: f022 0280 bic.w r2, r2, #128 @ 0x80 800ef52: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) 800ef54: 687b ldr r3, [r7, #4] 800ef56: 7e5b ldrb r3, [r3, #25] 800ef58: 2b01 cmp r3, #1 800ef5a: d108 bne.n 800ef6e { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800ef5c: 687b ldr r3, [r7, #4] 800ef5e: 681b ldr r3, [r3, #0] 800ef60: 681a ldr r2, [r3, #0] 800ef62: 687b ldr r3, [r7, #4] 800ef64: 681b ldr r3, [r3, #0] 800ef66: f042 0240 orr.w r2, r2, #64 @ 0x40 800ef6a: 601a str r2, [r3, #0] 800ef6c: e007 b.n 800ef7e } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 800ef6e: 687b ldr r3, [r7, #4] 800ef70: 681b ldr r3, [r3, #0] 800ef72: 681a ldr r2, [r3, #0] 800ef74: 687b ldr r3, [r7, #4] 800ef76: 681b ldr r3, [r3, #0] 800ef78: f022 0240 bic.w r2, r2, #64 @ 0x40 800ef7c: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) 800ef7e: 687b ldr r3, [r7, #4] 800ef80: 7e9b ldrb r3, [r3, #26] 800ef82: 2b01 cmp r3, #1 800ef84: d108 bne.n 800ef98 { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800ef86: 687b ldr r3, [r7, #4] 800ef88: 681b ldr r3, [r3, #0] 800ef8a: 681a ldr r2, [r3, #0] 800ef8c: 687b ldr r3, [r7, #4] 800ef8e: 681b ldr r3, [r3, #0] 800ef90: f042 0220 orr.w r2, r2, #32 800ef94: 601a str r2, [r3, #0] 800ef96: e007 b.n 800efa8 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 800ef98: 687b ldr r3, [r7, #4] 800ef9a: 681b ldr r3, [r3, #0] 800ef9c: 681a ldr r2, [r3, #0] 800ef9e: 687b ldr r3, [r7, #4] 800efa0: 681b ldr r3, [r3, #0] 800efa2: f022 0220 bic.w r2, r2, #32 800efa6: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) 800efa8: 687b ldr r3, [r7, #4] 800efaa: 7edb ldrb r3, [r3, #27] 800efac: 2b01 cmp r3, #1 800efae: d108 bne.n 800efc2 { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800efb0: 687b ldr r3, [r7, #4] 800efb2: 681b ldr r3, [r3, #0] 800efb4: 681a ldr r2, [r3, #0] 800efb6: 687b ldr r3, [r7, #4] 800efb8: 681b ldr r3, [r3, #0] 800efba: f022 0210 bic.w r2, r2, #16 800efbe: 601a str r2, [r3, #0] 800efc0: e007 b.n 800efd2 } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); 800efc2: 687b ldr r3, [r7, #4] 800efc4: 681b ldr r3, [r3, #0] 800efc6: 681a ldr r2, [r3, #0] 800efc8: 687b ldr r3, [r7, #4] 800efca: 681b ldr r3, [r3, #0] 800efcc: f042 0210 orr.w r2, r2, #16 800efd0: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) 800efd2: 687b ldr r3, [r7, #4] 800efd4: 7f1b ldrb r3, [r3, #28] 800efd6: 2b01 cmp r3, #1 800efd8: d108 bne.n 800efec { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800efda: 687b ldr r3, [r7, #4] 800efdc: 681b ldr r3, [r3, #0] 800efde: 681a ldr r2, [r3, #0] 800efe0: 687b ldr r3, [r7, #4] 800efe2: 681b ldr r3, [r3, #0] 800efe4: f042 0208 orr.w r2, r2, #8 800efe8: 601a str r2, [r3, #0] 800efea: e007 b.n 800effc } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 800efec: 687b ldr r3, [r7, #4] 800efee: 681b ldr r3, [r3, #0] 800eff0: 681a ldr r2, [r3, #0] 800eff2: 687b ldr r3, [r7, #4] 800eff4: 681b ldr r3, [r3, #0] 800eff6: f022 0208 bic.w r2, r2, #8 800effa: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) 800effc: 687b ldr r3, [r7, #4] 800effe: 7f5b ldrb r3, [r3, #29] 800f000: 2b01 cmp r3, #1 800f002: d108 bne.n 800f016 { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800f004: 687b ldr r3, [r7, #4] 800f006: 681b ldr r3, [r3, #0] 800f008: 681a ldr r2, [r3, #0] 800f00a: 687b ldr r3, [r7, #4] 800f00c: 681b ldr r3, [r3, #0] 800f00e: f042 0204 orr.w r2, r2, #4 800f012: 601a str r2, [r3, #0] 800f014: e007 b.n 800f026 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800f016: 687b ldr r3, [r7, #4] 800f018: 681b ldr r3, [r3, #0] 800f01a: 681a ldr r2, [r3, #0] 800f01c: 687b ldr r3, [r7, #4] 800f01e: 681b ldr r3, [r3, #0] 800f020: f022 0204 bic.w r2, r2, #4 800f024: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | 800f026: 687b ldr r3, [r7, #4] 800f028: 689a ldr r2, [r3, #8] 800f02a: 687b ldr r3, [r7, #4] 800f02c: 68db ldr r3, [r3, #12] 800f02e: 431a orrs r2, r3 800f030: 687b ldr r3, [r7, #4] 800f032: 691b ldr r3, [r3, #16] 800f034: 431a orrs r2, r3 800f036: 687b ldr r3, [r7, #4] 800f038: 695b ldr r3, [r3, #20] 800f03a: ea42 0103 orr.w r1, r2, r3 800f03e: 687b ldr r3, [r7, #4] 800f040: 685b ldr r3, [r3, #4] 800f042: 1e5a subs r2, r3, #1 800f044: 687b ldr r3, [r7, #4] 800f046: 681b ldr r3, [r3, #0] 800f048: 430a orrs r2, r1 800f04a: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800f04c: 687b ldr r3, [r7, #4] 800f04e: 2200 movs r2, #0 800f050: 625a str r2, [r3, #36] @ 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; 800f052: 687b ldr r3, [r7, #4] 800f054: 2201 movs r2, #1 800f056: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800f05a: 2300 movs r3, #0 } 800f05c: 4618 mov r0, r3 800f05e: 3710 adds r7, #16 800f060: 46bd mov sp, r7 800f062: bd80 pop {r7, pc} 0800f064 : * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) { 800f064: b480 push {r7} 800f066: b087 sub sp, #28 800f068: af00 add r7, sp, #0 800f06a: 6078 str r0, [r7, #4] 800f06c: 6039 str r1, [r7, #0] uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; 800f06e: 687b ldr r3, [r7, #4] 800f070: 681b ldr r3, [r3, #0] 800f072: 617b str r3, [r7, #20] HAL_CAN_StateTypeDef state = hcan->State; 800f074: 687b ldr r3, [r7, #4] 800f076: f893 3020 ldrb.w r3, [r3, #32] 800f07a: 74fb strb r3, [r7, #19] if ((state == HAL_CAN_STATE_READY) || 800f07c: 7cfb ldrb r3, [r7, #19] 800f07e: 2b01 cmp r3, #1 800f080: d003 beq.n 800f08a 800f082: 7cfb ldrb r3, [r7, #19] 800f084: 2b02 cmp r3, #2 800f086: f040 80be bne.w 800f206 assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); #if defined(CAN2) /* CAN1 and CAN2 are dual instances with 28 common filters banks */ /* Select master instance to access the filter banks */ can_ip = CAN1; 800f08a: 4b65 ldr r3, [pc, #404] @ (800f220 ) 800f08c: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); #endif /* CAN3 */ /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); 800f08e: 697b ldr r3, [r7, #20] 800f090: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800f094: f043 0201 orr.w r2, r3, #1 800f098: 697b ldr r3, [r7, #20] 800f09a: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #if defined(CAN2) /* Select the start filter number of CAN2 slave instance */ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); 800f09e: 697b ldr r3, [r7, #20] 800f0a0: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800f0a4: f423 527c bic.w r2, r3, #16128 @ 0x3f00 800f0a8: 697b ldr r3, [r7, #20] 800f0aa: f8c3 2200 str.w r2, [r3, #512] @ 0x200 SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); 800f0ae: 697b ldr r3, [r7, #20] 800f0b0: f8d3 2200 ldr.w r2, [r3, #512] @ 0x200 800f0b4: 683b ldr r3, [r7, #0] 800f0b6: 6a5b ldr r3, [r3, #36] @ 0x24 800f0b8: 021b lsls r3, r3, #8 800f0ba: 431a orrs r2, r3 800f0bc: 697b ldr r3, [r7, #20] 800f0be: f8c3 2200 str.w r2, [r3, #512] @ 0x200 #endif /* CAN3 */ /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); 800f0c2: 683b ldr r3, [r7, #0] 800f0c4: 695b ldr r3, [r3, #20] 800f0c6: f003 031f and.w r3, r3, #31 800f0ca: 2201 movs r2, #1 800f0cc: fa02 f303 lsl.w r3, r2, r3 800f0d0: 60fb str r3, [r7, #12] /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); 800f0d2: 697b ldr r3, [r7, #20] 800f0d4: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800f0d8: 68fb ldr r3, [r7, #12] 800f0da: 43db mvns r3, r3 800f0dc: 401a ands r2, r3 800f0de: 697b ldr r3, [r7, #20] 800f0e0: f8c3 221c str.w r2, [r3, #540] @ 0x21c /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) 800f0e4: 683b ldr r3, [r7, #0] 800f0e6: 69db ldr r3, [r3, #28] 800f0e8: 2b00 cmp r3, #0 800f0ea: d123 bne.n 800f134 { /* 16-bit scale for the filter */ CLEAR_BIT(can_ip->FS1R, filternbrbitpos); 800f0ec: 697b ldr r3, [r7, #20] 800f0ee: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800f0f2: 68fb ldr r3, [r7, #12] 800f0f4: 43db mvns r3, r3 800f0f6: 401a ands r2, r3 800f0f8: 697b ldr r3, [r7, #20] 800f0fa: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800f0fe: 683b ldr r3, [r7, #0] 800f100: 68db ldr r3, [r3, #12] 800f102: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800f104: 683b ldr r3, [r7, #0] 800f106: 685b ldr r3, [r3, #4] 800f108: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800f10a: 683a ldr r2, [r7, #0] 800f10c: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 800f10e: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800f110: 697b ldr r3, [r7, #20] 800f112: 3248 adds r2, #72 @ 0x48 800f114: f843 1032 str.w r1, [r3, r2, lsl #3] /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800f118: 683b ldr r3, [r7, #0] 800f11a: 689b ldr r3, [r3, #8] 800f11c: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); 800f11e: 683b ldr r3, [r7, #0] 800f120: 681b ldr r3, [r3, #0] 800f122: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800f124: 683b ldr r3, [r7, #0] 800f126: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800f128: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800f12a: 6979 ldr r1, [r7, #20] 800f12c: 3348 adds r3, #72 @ 0x48 800f12e: 00db lsls r3, r3, #3 800f130: 440b add r3, r1 800f132: 605a str r2, [r3, #4] } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) 800f134: 683b ldr r3, [r7, #0] 800f136: 69db ldr r3, [r3, #28] 800f138: 2b01 cmp r3, #1 800f13a: d122 bne.n 800f182 { /* 32-bit scale for the filter */ SET_BIT(can_ip->FS1R, filternbrbitpos); 800f13c: 697b ldr r3, [r7, #20] 800f13e: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c 800f142: 68fb ldr r3, [r7, #12] 800f144: 431a orrs r2, r3 800f146: 697b ldr r3, [r7, #20] 800f148: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* 32-bit identifier or First 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800f14c: 683b ldr r3, [r7, #0] 800f14e: 681b ldr r3, [r3, #0] 800f150: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800f152: 683b ldr r3, [r7, #0] 800f154: 685b ldr r3, [r3, #4] 800f156: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800f158: 683a ldr r2, [r7, #0] 800f15a: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 800f15c: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 800f15e: 697b ldr r3, [r7, #20] 800f160: 3248 adds r2, #72 @ 0x48 800f162: f843 1032 str.w r1, [r3, r2, lsl #3] /* 32-bit mask or Second 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800f166: 683b ldr r3, [r7, #0] 800f168: 689b ldr r3, [r3, #8] 800f16a: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); 800f16c: 683b ldr r3, [r7, #0] 800f16e: 68db ldr r3, [r3, #12] 800f170: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800f172: 683b ldr r3, [r7, #0] 800f174: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 800f176: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800f178: 6979 ldr r1, [r7, #20] 800f17a: 3348 adds r3, #72 @ 0x48 800f17c: 00db lsls r3, r3, #3 800f17e: 440b add r3, r1 800f180: 605a str r2, [r3, #4] } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) 800f182: 683b ldr r3, [r7, #0] 800f184: 699b ldr r3, [r3, #24] 800f186: 2b00 cmp r3, #0 800f188: d109 bne.n 800f19e { /* Id/Mask mode for the filter*/ CLEAR_BIT(can_ip->FM1R, filternbrbitpos); 800f18a: 697b ldr r3, [r7, #20] 800f18c: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800f190: 68fb ldr r3, [r7, #12] 800f192: 43db mvns r3, r3 800f194: 401a ands r2, r3 800f196: 697b ldr r3, [r7, #20] 800f198: f8c3 2204 str.w r2, [r3, #516] @ 0x204 800f19c: e007 b.n 800f1ae } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /* Identifier list mode for the filter*/ SET_BIT(can_ip->FM1R, filternbrbitpos); 800f19e: 697b ldr r3, [r7, #20] 800f1a0: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 800f1a4: 68fb ldr r3, [r7, #12] 800f1a6: 431a orrs r2, r3 800f1a8: 697b ldr r3, [r7, #20] 800f1aa: f8c3 2204 str.w r2, [r3, #516] @ 0x204 } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) 800f1ae: 683b ldr r3, [r7, #0] 800f1b0: 691b ldr r3, [r3, #16] 800f1b2: 2b00 cmp r3, #0 800f1b4: d109 bne.n 800f1ca { /* FIFO 0 assignation for the filter */ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); 800f1b6: 697b ldr r3, [r7, #20] 800f1b8: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800f1bc: 68fb ldr r3, [r7, #12] 800f1be: 43db mvns r3, r3 800f1c0: 401a ands r2, r3 800f1c2: 697b ldr r3, [r7, #20] 800f1c4: f8c3 2214 str.w r2, [r3, #532] @ 0x214 800f1c8: e007 b.n 800f1da } else { /* FIFO 1 assignation for the filter */ SET_BIT(can_ip->FFA1R, filternbrbitpos); 800f1ca: 697b ldr r3, [r7, #20] 800f1cc: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214 800f1d0: 68fb ldr r3, [r7, #12] 800f1d2: 431a orrs r2, r3 800f1d4: 697b ldr r3, [r7, #20] 800f1d6: f8c3 2214 str.w r2, [r3, #532] @ 0x214 } /* Filter activation */ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) 800f1da: 683b ldr r3, [r7, #0] 800f1dc: 6a1b ldr r3, [r3, #32] 800f1de: 2b01 cmp r3, #1 800f1e0: d107 bne.n 800f1f2 { SET_BIT(can_ip->FA1R, filternbrbitpos); 800f1e2: 697b ldr r3, [r7, #20] 800f1e4: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c 800f1e8: 68fb ldr r3, [r7, #12] 800f1ea: 431a orrs r2, r3 800f1ec: 697b ldr r3, [r7, #20] 800f1ee: f8c3 221c str.w r2, [r3, #540] @ 0x21c } /* Leave the initialisation mode for the filter */ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); 800f1f2: 697b ldr r3, [r7, #20] 800f1f4: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200 800f1f8: f023 0201 bic.w r2, r3, #1 800f1fc: 697b ldr r3, [r7, #20] 800f1fe: f8c3 2200 str.w r2, [r3, #512] @ 0x200 /* Return function status */ return HAL_OK; 800f202: 2300 movs r3, #0 800f204: e006 b.n 800f214 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f206: 687b ldr r3, [r7, #4] 800f208: 6a5b ldr r3, [r3, #36] @ 0x24 800f20a: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f20e: 687b ldr r3, [r7, #4] 800f210: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f212: 2301 movs r3, #1 } } 800f214: 4618 mov r0, r3 800f216: 371c adds r7, #28 800f218: 46bd mov sp, r7 800f21a: bc80 pop {r7} 800f21c: 4770 bx lr 800f21e: bf00 nop 800f220: 40006400 .word 0x40006400 0800f224 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { 800f224: b580 push {r7, lr} 800f226: b084 sub sp, #16 800f228: af00 add r7, sp, #0 800f22a: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) 800f22c: 687b ldr r3, [r7, #4] 800f22e: f893 3020 ldrb.w r3, [r3, #32] 800f232: b2db uxtb r3, r3 800f234: 2b01 cmp r3, #1 800f236: d12e bne.n 800f296 { /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_LISTENING; 800f238: 687b ldr r3, [r7, #4] 800f23a: 2202 movs r2, #2 800f23c: f883 2020 strb.w r2, [r3, #32] /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800f240: 687b ldr r3, [r7, #4] 800f242: 681b ldr r3, [r3, #0] 800f244: 681a ldr r2, [r3, #0] 800f246: 687b ldr r3, [r7, #4] 800f248: 681b ldr r3, [r3, #0] 800f24a: f022 0201 bic.w r2, r2, #1 800f24e: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800f250: f7ff f89e bl 800e390 800f254: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800f256: e012 b.n 800f27e { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800f258: f7ff f89a bl 800e390 800f25c: 4602 mov r2, r0 800f25e: 68fb ldr r3, [r7, #12] 800f260: 1ad3 subs r3, r2, r3 800f262: 2b0a cmp r3, #10 800f264: d90b bls.n 800f27e { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800f266: 687b ldr r3, [r7, #4] 800f268: 6a5b ldr r3, [r3, #36] @ 0x24 800f26a: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800f26e: 687b ldr r3, [r7, #4] 800f270: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800f272: 687b ldr r3, [r7, #4] 800f274: 2205 movs r2, #5 800f276: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800f27a: 2301 movs r3, #1 800f27c: e012 b.n 800f2a4 while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 800f27e: 687b ldr r3, [r7, #4] 800f280: 681b ldr r3, [r3, #0] 800f282: 685b ldr r3, [r3, #4] 800f284: f003 0301 and.w r3, r3, #1 800f288: 2b00 cmp r3, #0 800f28a: d1e5 bne.n 800f258 } } /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 800f28c: 687b ldr r3, [r7, #4] 800f28e: 2200 movs r2, #0 800f290: 625a str r2, [r3, #36] @ 0x24 /* Return function status */ return HAL_OK; 800f292: 2300 movs r3, #0 800f294: e006 b.n 800f2a4 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; 800f296: 687b ldr r3, [r7, #4] 800f298: 6a5b ldr r3, [r3, #36] @ 0x24 800f29a: f443 2200 orr.w r2, r3, #524288 @ 0x80000 800f29e: 687b ldr r3, [r7, #4] 800f2a0: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f2a2: 2301 movs r3, #1 } } 800f2a4: 4618 mov r0, r3 800f2a6: 3710 adds r7, #16 800f2a8: 46bd mov sp, r7 800f2aa: bd80 pop {r7, pc} 0800f2ac : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { 800f2ac: b580 push {r7, lr} 800f2ae: b084 sub sp, #16 800f2b0: af00 add r7, sp, #0 800f2b2: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_LISTENING) 800f2b4: 687b ldr r3, [r7, #4] 800f2b6: f893 3020 ldrb.w r3, [r3, #32] 800f2ba: b2db uxtb r3, r3 800f2bc: 2b02 cmp r3, #2 800f2be: d133 bne.n 800f328 { /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 800f2c0: 687b ldr r3, [r7, #4] 800f2c2: 681b ldr r3, [r3, #0] 800f2c4: 681a ldr r2, [r3, #0] 800f2c6: 687b ldr r3, [r7, #4] 800f2c8: 681b ldr r3, [r3, #0] 800f2ca: f042 0201 orr.w r2, r2, #1 800f2ce: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800f2d0: f7ff f85e bl 800e390 800f2d4: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800f2d6: e012 b.n 800f2fe { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800f2d8: f7ff f85a bl 800e390 800f2dc: 4602 mov r2, r0 800f2de: 68fb ldr r3, [r7, #12] 800f2e0: 1ad3 subs r3, r2, r3 800f2e2: 2b0a cmp r3, #10 800f2e4: d90b bls.n 800f2fe { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800f2e6: 687b ldr r3, [r7, #4] 800f2e8: 6a5b ldr r3, [r3, #36] @ 0x24 800f2ea: f443 3200 orr.w r2, r3, #131072 @ 0x20000 800f2ee: 687b ldr r3, [r7, #4] 800f2f0: 625a str r2, [r3, #36] @ 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800f2f2: 687b ldr r3, [r7, #4] 800f2f4: 2205 movs r2, #5 800f2f6: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800f2fa: 2301 movs r3, #1 800f2fc: e01b b.n 800f336 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 800f2fe: 687b ldr r3, [r7, #4] 800f300: 681b ldr r3, [r3, #0] 800f302: 685b ldr r3, [r3, #4] 800f304: f003 0301 and.w r3, r3, #1 800f308: 2b00 cmp r3, #0 800f30a: d0e5 beq.n 800f2d8 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 800f30c: 687b ldr r3, [r7, #4] 800f30e: 681b ldr r3, [r3, #0] 800f310: 681a ldr r2, [r3, #0] 800f312: 687b ldr r3, [r7, #4] 800f314: 681b ldr r3, [r3, #0] 800f316: f022 0202 bic.w r2, r2, #2 800f31a: 601a str r2, [r3, #0] /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_READY; 800f31c: 687b ldr r3, [r7, #4] 800f31e: 2201 movs r2, #1 800f320: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 800f324: 2300 movs r3, #0 800f326: e006 b.n 800f336 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; 800f328: 687b ldr r3, [r7, #4] 800f32a: 6a5b ldr r3, [r3, #36] @ 0x24 800f32c: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 800f330: 687b ldr r3, [r7, #4] 800f332: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f334: 2301 movs r3, #1 } } 800f336: 4618 mov r0, r3 800f338: 3710 adds r7, #16 800f33a: 46bd mov sp, r7 800f33c: bd80 pop {r7, pc} 0800f33e : * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, const uint8_t aData[], uint32_t *pTxMailbox) { 800f33e: b480 push {r7} 800f340: b089 sub sp, #36 @ 0x24 800f342: af00 add r7, sp, #0 800f344: 60f8 str r0, [r7, #12] 800f346: 60b9 str r1, [r7, #8] 800f348: 607a str r2, [r7, #4] 800f34a: 603b str r3, [r7, #0] uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; 800f34c: 68fb ldr r3, [r7, #12] 800f34e: f893 3020 ldrb.w r3, [r3, #32] 800f352: 77fb strb r3, [r7, #31] uint32_t tsr = READ_REG(hcan->Instance->TSR); 800f354: 68fb ldr r3, [r7, #12] 800f356: 681b ldr r3, [r3, #0] 800f358: 689b ldr r3, [r3, #8] 800f35a: 61bb str r3, [r7, #24] { assert_param(IS_CAN_EXTID(pHeader->ExtId)); } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); if ((state == HAL_CAN_STATE_READY) || 800f35c: 7ffb ldrb r3, [r7, #31] 800f35e: 2b01 cmp r3, #1 800f360: d003 beq.n 800f36a 800f362: 7ffb ldrb r3, [r7, #31] 800f364: 2b02 cmp r3, #2 800f366: f040 80ad bne.w 800f4c4 (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ if (((tsr & CAN_TSR_TME0) != 0U) || 800f36a: 69bb ldr r3, [r7, #24] 800f36c: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800f370: 2b00 cmp r3, #0 800f372: d10a bne.n 800f38a ((tsr & CAN_TSR_TME1) != 0U) || 800f374: 69bb ldr r3, [r7, #24] 800f376: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 if (((tsr & CAN_TSR_TME0) != 0U) || 800f37a: 2b00 cmp r3, #0 800f37c: d105 bne.n 800f38a ((tsr & CAN_TSR_TME2) != 0U)) 800f37e: 69bb ldr r3, [r7, #24] 800f380: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 ((tsr & CAN_TSR_TME1) != 0U) || 800f384: 2b00 cmp r3, #0 800f386: f000 8095 beq.w 800f4b4 { /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; 800f38a: 69bb ldr r3, [r7, #24] 800f38c: 0e1b lsrs r3, r3, #24 800f38e: f003 0303 and.w r3, r3, #3 800f392: 617b str r3, [r7, #20] /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; 800f394: 2201 movs r2, #1 800f396: 697b ldr r3, [r7, #20] 800f398: 409a lsls r2, r3 800f39a: 683b ldr r3, [r7, #0] 800f39c: 601a str r2, [r3, #0] /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) 800f39e: 68bb ldr r3, [r7, #8] 800f3a0: 689b ldr r3, [r3, #8] 800f3a2: 2b00 cmp r3, #0 800f3a4: d10d bne.n 800f3c2 { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800f3a6: 68bb ldr r3, [r7, #8] 800f3a8: 681b ldr r3, [r3, #0] 800f3aa: 055a lsls r2, r3, #21 pHeader->RTR); 800f3ac: 68bb ldr r3, [r7, #8] 800f3ae: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 800f3b0: 68f9 ldr r1, [r7, #12] 800f3b2: 6809 ldr r1, [r1, #0] 800f3b4: 431a orrs r2, r3 800f3b6: 697b ldr r3, [r7, #20] 800f3b8: 3318 adds r3, #24 800f3ba: 011b lsls r3, r3, #4 800f3bc: 440b add r3, r1 800f3be: 601a str r2, [r3, #0] 800f3c0: e00f b.n 800f3e2 } else { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f3c2: 68bb ldr r3, [r7, #8] 800f3c4: 685b ldr r3, [r3, #4] 800f3c6: 00da lsls r2, r3, #3 pHeader->IDE | 800f3c8: 68bb ldr r3, [r7, #8] 800f3ca: 689b ldr r3, [r3, #8] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f3cc: 431a orrs r2, r3 pHeader->RTR); 800f3ce: 68bb ldr r3, [r7, #8] 800f3d0: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f3d2: 68f9 ldr r1, [r7, #12] 800f3d4: 6809 ldr r1, [r1, #0] pHeader->IDE | 800f3d6: 431a orrs r2, r3 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 800f3d8: 697b ldr r3, [r7, #20] 800f3da: 3318 adds r3, #24 800f3dc: 011b lsls r3, r3, #4 800f3de: 440b add r3, r1 800f3e0: 601a str r2, [r3, #0] } /* Set up the DLC */ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); 800f3e2: 68fb ldr r3, [r7, #12] 800f3e4: 6819 ldr r1, [r3, #0] 800f3e6: 68bb ldr r3, [r7, #8] 800f3e8: 691a ldr r2, [r3, #16] 800f3ea: 697b ldr r3, [r7, #20] 800f3ec: 3318 adds r3, #24 800f3ee: 011b lsls r3, r3, #4 800f3f0: 440b add r3, r1 800f3f2: 3304 adds r3, #4 800f3f4: 601a str r2, [r3, #0] /* Set up the Transmit Global Time mode */ if (pHeader->TransmitGlobalTime == ENABLE) 800f3f6: 68bb ldr r3, [r7, #8] 800f3f8: 7d1b ldrb r3, [r3, #20] 800f3fa: 2b01 cmp r3, #1 800f3fc: d111 bne.n 800f422 { SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); 800f3fe: 68fb ldr r3, [r7, #12] 800f400: 681a ldr r2, [r3, #0] 800f402: 697b ldr r3, [r7, #20] 800f404: 3318 adds r3, #24 800f406: 011b lsls r3, r3, #4 800f408: 4413 add r3, r2 800f40a: 3304 adds r3, #4 800f40c: 681b ldr r3, [r3, #0] 800f40e: 68fa ldr r2, [r7, #12] 800f410: 6811 ldr r1, [r2, #0] 800f412: f443 7280 orr.w r2, r3, #256 @ 0x100 800f416: 697b ldr r3, [r7, #20] 800f418: 3318 adds r3, #24 800f41a: 011b lsls r3, r3, #4 800f41c: 440b add r3, r1 800f41e: 3304 adds r3, #4 800f420: 601a str r2, [r3, #0] } /* Set up the data field */ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, 800f422: 687b ldr r3, [r7, #4] 800f424: 3307 adds r3, #7 800f426: 781b ldrb r3, [r3, #0] 800f428: 061a lsls r2, r3, #24 800f42a: 687b ldr r3, [r7, #4] 800f42c: 3306 adds r3, #6 800f42e: 781b ldrb r3, [r3, #0] 800f430: 041b lsls r3, r3, #16 800f432: 431a orrs r2, r3 800f434: 687b ldr r3, [r7, #4] 800f436: 3305 adds r3, #5 800f438: 781b ldrb r3, [r3, #0] 800f43a: 021b lsls r3, r3, #8 800f43c: 4313 orrs r3, r2 800f43e: 687a ldr r2, [r7, #4] 800f440: 3204 adds r2, #4 800f442: 7812 ldrb r2, [r2, #0] 800f444: 4610 mov r0, r2 800f446: 68fa ldr r2, [r7, #12] 800f448: 6811 ldr r1, [r2, #0] 800f44a: ea43 0200 orr.w r2, r3, r0 800f44e: 697b ldr r3, [r7, #20] 800f450: 011b lsls r3, r3, #4 800f452: 440b add r3, r1 800f454: f503 73c6 add.w r3, r3, #396 @ 0x18c 800f458: 601a str r2, [r3, #0] ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, 800f45a: 687b ldr r3, [r7, #4] 800f45c: 3303 adds r3, #3 800f45e: 781b ldrb r3, [r3, #0] 800f460: 061a lsls r2, r3, #24 800f462: 687b ldr r3, [r7, #4] 800f464: 3302 adds r3, #2 800f466: 781b ldrb r3, [r3, #0] 800f468: 041b lsls r3, r3, #16 800f46a: 431a orrs r2, r3 800f46c: 687b ldr r3, [r7, #4] 800f46e: 3301 adds r3, #1 800f470: 781b ldrb r3, [r3, #0] 800f472: 021b lsls r3, r3, #8 800f474: 4313 orrs r3, r2 800f476: 687a ldr r2, [r7, #4] 800f478: 7812 ldrb r2, [r2, #0] 800f47a: 4610 mov r0, r2 800f47c: 68fa ldr r2, [r7, #12] 800f47e: 6811 ldr r1, [r2, #0] 800f480: ea43 0200 orr.w r2, r3, r0 800f484: 697b ldr r3, [r7, #20] 800f486: 011b lsls r3, r3, #4 800f488: 440b add r3, r1 800f48a: f503 73c4 add.w r3, r3, #392 @ 0x188 800f48e: 601a str r2, [r3, #0] ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); 800f490: 68fb ldr r3, [r7, #12] 800f492: 681a ldr r2, [r3, #0] 800f494: 697b ldr r3, [r7, #20] 800f496: 3318 adds r3, #24 800f498: 011b lsls r3, r3, #4 800f49a: 4413 add r3, r2 800f49c: 681b ldr r3, [r3, #0] 800f49e: 68fa ldr r2, [r7, #12] 800f4a0: 6811 ldr r1, [r2, #0] 800f4a2: f043 0201 orr.w r2, r3, #1 800f4a6: 697b ldr r3, [r7, #20] 800f4a8: 3318 adds r3, #24 800f4aa: 011b lsls r3, r3, #4 800f4ac: 440b add r3, r1 800f4ae: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 800f4b0: 2300 movs r3, #0 800f4b2: e00e b.n 800f4d2 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800f4b4: 68fb ldr r3, [r7, #12] 800f4b6: 6a5b ldr r3, [r3, #36] @ 0x24 800f4b8: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800f4bc: 68fb ldr r3, [r7, #12] 800f4be: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f4c0: 2301 movs r3, #1 800f4c2: e006 b.n 800f4d2 } } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f4c4: 68fb ldr r3, [r7, #12] 800f4c6: 6a5b ldr r3, [r3, #36] @ 0x24 800f4c8: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f4cc: 68fb ldr r3, [r7, #12] 800f4ce: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f4d0: 2301 movs r3, #1 } } 800f4d2: 4618 mov r0, r3 800f4d4: 3724 adds r7, #36 @ 0x24 800f4d6: 46bd mov sp, r7 800f4d8: bc80 pop {r7} 800f4da: 4770 bx lr 0800f4dc : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval Number of free Tx Mailboxes. */ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) { 800f4dc: b480 push {r7} 800f4de: b085 sub sp, #20 800f4e0: af00 add r7, sp, #0 800f4e2: 6078 str r0, [r7, #4] uint32_t freelevel = 0U; 800f4e4: 2300 movs r3, #0 800f4e6: 60fb str r3, [r7, #12] HAL_CAN_StateTypeDef state = hcan->State; 800f4e8: 687b ldr r3, [r7, #4] 800f4ea: f893 3020 ldrb.w r3, [r3, #32] 800f4ee: 72fb strb r3, [r7, #11] if ((state == HAL_CAN_STATE_READY) || 800f4f0: 7afb ldrb r3, [r7, #11] 800f4f2: 2b01 cmp r3, #1 800f4f4: d002 beq.n 800f4fc 800f4f6: 7afb ldrb r3, [r7, #11] 800f4f8: 2b02 cmp r3, #2 800f4fa: d11d bne.n 800f538 (state == HAL_CAN_STATE_LISTENING)) { /* Check Tx Mailbox 0 status */ if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) 800f4fc: 687b ldr r3, [r7, #4] 800f4fe: 681b ldr r3, [r3, #0] 800f500: 689b ldr r3, [r3, #8] 800f502: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800f506: 2b00 cmp r3, #0 800f508: d002 beq.n 800f510 { freelevel++; 800f50a: 68fb ldr r3, [r7, #12] 800f50c: 3301 adds r3, #1 800f50e: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 1 status */ if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) 800f510: 687b ldr r3, [r7, #4] 800f512: 681b ldr r3, [r3, #0] 800f514: 689b ldr r3, [r3, #8] 800f516: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800f51a: 2b00 cmp r3, #0 800f51c: d002 beq.n 800f524 { freelevel++; 800f51e: 68fb ldr r3, [r7, #12] 800f520: 3301 adds r3, #1 800f522: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 2 status */ if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) 800f524: 687b ldr r3, [r7, #4] 800f526: 681b ldr r3, [r3, #0] 800f528: 689b ldr r3, [r3, #8] 800f52a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800f52e: 2b00 cmp r3, #0 800f530: d002 beq.n 800f538 { freelevel++; 800f532: 68fb ldr r3, [r7, #12] 800f534: 3301 adds r3, #1 800f536: 60fb str r3, [r7, #12] } } /* Return Tx Mailboxes free level */ return freelevel; 800f538: 68fb ldr r3, [r7, #12] } 800f53a: 4618 mov r0, r3 800f53c: 3714 adds r7, #20 800f53e: 46bd mov sp, r7 800f540: bc80 pop {r7} 800f542: 4770 bx lr 0800f544 : * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { 800f544: b480 push {r7} 800f546: b087 sub sp, #28 800f548: af00 add r7, sp, #0 800f54a: 60f8 str r0, [r7, #12] 800f54c: 60b9 str r1, [r7, #8] 800f54e: 607a str r2, [r7, #4] 800f550: 603b str r3, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800f552: 68fb ldr r3, [r7, #12] 800f554: f893 3020 ldrb.w r3, [r3, #32] 800f558: 75fb strb r3, [r7, #23] assert_param(IS_CAN_RX_FIFO(RxFifo)); if ((state == HAL_CAN_STATE_READY) || 800f55a: 7dfb ldrb r3, [r7, #23] 800f55c: 2b01 cmp r3, #1 800f55e: d003 beq.n 800f568 800f560: 7dfb ldrb r3, [r7, #23] 800f562: 2b02 cmp r3, #2 800f564: f040 8103 bne.w 800f76e (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800f568: 68bb ldr r3, [r7, #8] 800f56a: 2b00 cmp r3, #0 800f56c: d10e bne.n 800f58c { /* Check that the Rx FIFO 0 is not empty */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) 800f56e: 68fb ldr r3, [r7, #12] 800f570: 681b ldr r3, [r3, #0] 800f572: 68db ldr r3, [r3, #12] 800f574: f003 0303 and.w r3, r3, #3 800f578: 2b00 cmp r3, #0 800f57a: d116 bne.n 800f5aa { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800f57c: 68fb ldr r3, [r7, #12] 800f57e: 6a5b ldr r3, [r3, #36] @ 0x24 800f580: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800f584: 68fb ldr r3, [r7, #12] 800f586: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f588: 2301 movs r3, #1 800f58a: e0f7 b.n 800f77c } } else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) 800f58c: 68fb ldr r3, [r7, #12] 800f58e: 681b ldr r3, [r3, #0] 800f590: 691b ldr r3, [r3, #16] 800f592: f003 0303 and.w r3, r3, #3 800f596: 2b00 cmp r3, #0 800f598: d107 bne.n 800f5aa { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 800f59a: 68fb ldr r3, [r7, #12] 800f59c: 6a5b ldr r3, [r3, #36] @ 0x24 800f59e: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800f5a2: 68fb ldr r3, [r7, #12] 800f5a4: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f5a6: 2301 movs r3, #1 800f5a8: e0e8 b.n 800f77c } } /* Get the header */ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; 800f5aa: 68fb ldr r3, [r7, #12] 800f5ac: 681a ldr r2, [r3, #0] 800f5ae: 68bb ldr r3, [r7, #8] 800f5b0: 331b adds r3, #27 800f5b2: 011b lsls r3, r3, #4 800f5b4: 4413 add r3, r2 800f5b6: 681b ldr r3, [r3, #0] 800f5b8: f003 0204 and.w r2, r3, #4 800f5bc: 687b ldr r3, [r7, #4] 800f5be: 609a str r2, [r3, #8] if (pHeader->IDE == CAN_ID_STD) 800f5c0: 687b ldr r3, [r7, #4] 800f5c2: 689b ldr r3, [r3, #8] 800f5c4: 2b00 cmp r3, #0 800f5c6: d10c bne.n 800f5e2 { pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; 800f5c8: 68fb ldr r3, [r7, #12] 800f5ca: 681a ldr r2, [r3, #0] 800f5cc: 68bb ldr r3, [r7, #8] 800f5ce: 331b adds r3, #27 800f5d0: 011b lsls r3, r3, #4 800f5d2: 4413 add r3, r2 800f5d4: 681b ldr r3, [r3, #0] 800f5d6: 0d5b lsrs r3, r3, #21 800f5d8: f3c3 020a ubfx r2, r3, #0, #11 800f5dc: 687b ldr r3, [r7, #4] 800f5de: 601a str r2, [r3, #0] 800f5e0: e00b b.n 800f5fa } else { pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; 800f5e2: 68fb ldr r3, [r7, #12] 800f5e4: 681a ldr r2, [r3, #0] 800f5e6: 68bb ldr r3, [r7, #8] 800f5e8: 331b adds r3, #27 800f5ea: 011b lsls r3, r3, #4 800f5ec: 4413 add r3, r2 800f5ee: 681b ldr r3, [r3, #0] 800f5f0: 08db lsrs r3, r3, #3 800f5f2: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & 800f5f6: 687b ldr r3, [r7, #4] 800f5f8: 605a str r2, [r3, #4] } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); 800f5fa: 68fb ldr r3, [r7, #12] 800f5fc: 681a ldr r2, [r3, #0] 800f5fe: 68bb ldr r3, [r7, #8] 800f600: 331b adds r3, #27 800f602: 011b lsls r3, r3, #4 800f604: 4413 add r3, r2 800f606: 681b ldr r3, [r3, #0] 800f608: f003 0202 and.w r2, r3, #2 800f60c: 687b ldr r3, [r7, #4] 800f60e: 60da str r2, [r3, #12] if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) 800f610: 68fb ldr r3, [r7, #12] 800f612: 681a ldr r2, [r3, #0] 800f614: 68bb ldr r3, [r7, #8] 800f616: 331b adds r3, #27 800f618: 011b lsls r3, r3, #4 800f61a: 4413 add r3, r2 800f61c: 3304 adds r3, #4 800f61e: 681b ldr r3, [r3, #0] 800f620: f003 0308 and.w r3, r3, #8 800f624: 2b00 cmp r3, #0 800f626: d003 beq.n 800f630 { /* Truncate DLC to 8 if received field is over range */ pHeader->DLC = 8U; 800f628: 687b ldr r3, [r7, #4] 800f62a: 2208 movs r2, #8 800f62c: 611a str r2, [r3, #16] 800f62e: e00b b.n 800f648 } else { pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; 800f630: 68fb ldr r3, [r7, #12] 800f632: 681a ldr r2, [r3, #0] 800f634: 68bb ldr r3, [r7, #8] 800f636: 331b adds r3, #27 800f638: 011b lsls r3, r3, #4 800f63a: 4413 add r3, r2 800f63c: 3304 adds r3, #4 800f63e: 681b ldr r3, [r3, #0] 800f640: f003 020f and.w r2, r3, #15 800f644: 687b ldr r3, [r7, #4] 800f646: 611a str r2, [r3, #16] } pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; 800f648: 68fb ldr r3, [r7, #12] 800f64a: 681a ldr r2, [r3, #0] 800f64c: 68bb ldr r3, [r7, #8] 800f64e: 331b adds r3, #27 800f650: 011b lsls r3, r3, #4 800f652: 4413 add r3, r2 800f654: 3304 adds r3, #4 800f656: 681b ldr r3, [r3, #0] 800f658: 0a1b lsrs r3, r3, #8 800f65a: b2da uxtb r2, r3 800f65c: 687b ldr r3, [r7, #4] 800f65e: 619a str r2, [r3, #24] pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; 800f660: 68fb ldr r3, [r7, #12] 800f662: 681a ldr r2, [r3, #0] 800f664: 68bb ldr r3, [r7, #8] 800f666: 331b adds r3, #27 800f668: 011b lsls r3, r3, #4 800f66a: 4413 add r3, r2 800f66c: 3304 adds r3, #4 800f66e: 681b ldr r3, [r3, #0] 800f670: 0c1b lsrs r3, r3, #16 800f672: b29a uxth r2, r3 800f674: 687b ldr r3, [r7, #4] 800f676: 615a str r2, [r3, #20] /* Get the data */ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); 800f678: 68fb ldr r3, [r7, #12] 800f67a: 681a ldr r2, [r3, #0] 800f67c: 68bb ldr r3, [r7, #8] 800f67e: 011b lsls r3, r3, #4 800f680: 4413 add r3, r2 800f682: f503 73dc add.w r3, r3, #440 @ 0x1b8 800f686: 681b ldr r3, [r3, #0] 800f688: b2da uxtb r2, r3 800f68a: 683b ldr r3, [r7, #0] 800f68c: 701a strb r2, [r3, #0] aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); 800f68e: 68fb ldr r3, [r7, #12] 800f690: 681a ldr r2, [r3, #0] 800f692: 68bb ldr r3, [r7, #8] 800f694: 011b lsls r3, r3, #4 800f696: 4413 add r3, r2 800f698: f503 73dc add.w r3, r3, #440 @ 0x1b8 800f69c: 681b ldr r3, [r3, #0] 800f69e: 0a1a lsrs r2, r3, #8 800f6a0: 683b ldr r3, [r7, #0] 800f6a2: 3301 adds r3, #1 800f6a4: b2d2 uxtb r2, r2 800f6a6: 701a strb r2, [r3, #0] aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); 800f6a8: 68fb ldr r3, [r7, #12] 800f6aa: 681a ldr r2, [r3, #0] 800f6ac: 68bb ldr r3, [r7, #8] 800f6ae: 011b lsls r3, r3, #4 800f6b0: 4413 add r3, r2 800f6b2: f503 73dc add.w r3, r3, #440 @ 0x1b8 800f6b6: 681b ldr r3, [r3, #0] 800f6b8: 0c1a lsrs r2, r3, #16 800f6ba: 683b ldr r3, [r7, #0] 800f6bc: 3302 adds r3, #2 800f6be: b2d2 uxtb r2, r2 800f6c0: 701a strb r2, [r3, #0] aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); 800f6c2: 68fb ldr r3, [r7, #12] 800f6c4: 681a ldr r2, [r3, #0] 800f6c6: 68bb ldr r3, [r7, #8] 800f6c8: 011b lsls r3, r3, #4 800f6ca: 4413 add r3, r2 800f6cc: f503 73dc add.w r3, r3, #440 @ 0x1b8 800f6d0: 681b ldr r3, [r3, #0] 800f6d2: 0e1a lsrs r2, r3, #24 800f6d4: 683b ldr r3, [r7, #0] 800f6d6: 3303 adds r3, #3 800f6d8: b2d2 uxtb r2, r2 800f6da: 701a strb r2, [r3, #0] aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); 800f6dc: 68fb ldr r3, [r7, #12] 800f6de: 681a ldr r2, [r3, #0] 800f6e0: 68bb ldr r3, [r7, #8] 800f6e2: 011b lsls r3, r3, #4 800f6e4: 4413 add r3, r2 800f6e6: f503 73de add.w r3, r3, #444 @ 0x1bc 800f6ea: 681a ldr r2, [r3, #0] 800f6ec: 683b ldr r3, [r7, #0] 800f6ee: 3304 adds r3, #4 800f6f0: b2d2 uxtb r2, r2 800f6f2: 701a strb r2, [r3, #0] aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); 800f6f4: 68fb ldr r3, [r7, #12] 800f6f6: 681a ldr r2, [r3, #0] 800f6f8: 68bb ldr r3, [r7, #8] 800f6fa: 011b lsls r3, r3, #4 800f6fc: 4413 add r3, r2 800f6fe: f503 73de add.w r3, r3, #444 @ 0x1bc 800f702: 681b ldr r3, [r3, #0] 800f704: 0a1a lsrs r2, r3, #8 800f706: 683b ldr r3, [r7, #0] 800f708: 3305 adds r3, #5 800f70a: b2d2 uxtb r2, r2 800f70c: 701a strb r2, [r3, #0] aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); 800f70e: 68fb ldr r3, [r7, #12] 800f710: 681a ldr r2, [r3, #0] 800f712: 68bb ldr r3, [r7, #8] 800f714: 011b lsls r3, r3, #4 800f716: 4413 add r3, r2 800f718: f503 73de add.w r3, r3, #444 @ 0x1bc 800f71c: 681b ldr r3, [r3, #0] 800f71e: 0c1a lsrs r2, r3, #16 800f720: 683b ldr r3, [r7, #0] 800f722: 3306 adds r3, #6 800f724: b2d2 uxtb r2, r2 800f726: 701a strb r2, [r3, #0] aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); 800f728: 68fb ldr r3, [r7, #12] 800f72a: 681a ldr r2, [r3, #0] 800f72c: 68bb ldr r3, [r7, #8] 800f72e: 011b lsls r3, r3, #4 800f730: 4413 add r3, r2 800f732: f503 73de add.w r3, r3, #444 @ 0x1bc 800f736: 681b ldr r3, [r3, #0] 800f738: 0e1a lsrs r2, r3, #24 800f73a: 683b ldr r3, [r7, #0] 800f73c: 3307 adds r3, #7 800f73e: b2d2 uxtb r2, r2 800f740: 701a strb r2, [r3, #0] /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 800f742: 68bb ldr r3, [r7, #8] 800f744: 2b00 cmp r3, #0 800f746: d108 bne.n 800f75a { /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); 800f748: 68fb ldr r3, [r7, #12] 800f74a: 681b ldr r3, [r3, #0] 800f74c: 68da ldr r2, [r3, #12] 800f74e: 68fb ldr r3, [r7, #12] 800f750: 681b ldr r3, [r3, #0] 800f752: f042 0220 orr.w r2, r2, #32 800f756: 60da str r2, [r3, #12] 800f758: e007 b.n 800f76a } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); 800f75a: 68fb ldr r3, [r7, #12] 800f75c: 681b ldr r3, [r3, #0] 800f75e: 691a ldr r2, [r3, #16] 800f760: 68fb ldr r3, [r7, #12] 800f762: 681b ldr r3, [r3, #0] 800f764: f042 0220 orr.w r2, r2, #32 800f768: 611a str r2, [r3, #16] } /* Return function status */ return HAL_OK; 800f76a: 2300 movs r3, #0 800f76c: e006 b.n 800f77c } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f76e: 68fb ldr r3, [r7, #12] 800f770: 6a5b ldr r3, [r3, #36] @ 0x24 800f772: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f776: 68fb ldr r3, [r7, #12] 800f778: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f77a: 2301 movs r3, #1 } } 800f77c: 4618 mov r0, r3 800f77e: 371c adds r7, #28 800f780: 46bd mov sp, r7 800f782: bc80 pop {r7} 800f784: 4770 bx lr 0800f786 : * @param ActiveITs indicates which interrupts will be enabled. * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { 800f786: b480 push {r7} 800f788: b085 sub sp, #20 800f78a: af00 add r7, sp, #0 800f78c: 6078 str r0, [r7, #4] 800f78e: 6039 str r1, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 800f790: 687b ldr r3, [r7, #4] 800f792: f893 3020 ldrb.w r3, [r3, #32] 800f796: 73fb strb r3, [r7, #15] /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); if ((state == HAL_CAN_STATE_READY) || 800f798: 7bfb ldrb r3, [r7, #15] 800f79a: 2b01 cmp r3, #1 800f79c: d002 beq.n 800f7a4 800f79e: 7bfb ldrb r3, [r7, #15] 800f7a0: 2b02 cmp r3, #2 800f7a2: d109 bne.n 800f7b8 (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); 800f7a4: 687b ldr r3, [r7, #4] 800f7a6: 681b ldr r3, [r3, #0] 800f7a8: 6959 ldr r1, [r3, #20] 800f7aa: 687b ldr r3, [r7, #4] 800f7ac: 681b ldr r3, [r3, #0] 800f7ae: 683a ldr r2, [r7, #0] 800f7b0: 430a orrs r2, r1 800f7b2: 615a str r2, [r3, #20] /* Return function status */ return HAL_OK; 800f7b4: 2300 movs r3, #0 800f7b6: e006 b.n 800f7c6 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 800f7b8: 687b ldr r3, [r7, #4] 800f7ba: 6a5b ldr r3, [r3, #36] @ 0x24 800f7bc: f443 2280 orr.w r2, r3, #262144 @ 0x40000 800f7c0: 687b ldr r3, [r7, #4] 800f7c2: 625a str r2, [r3, #36] @ 0x24 return HAL_ERROR; 800f7c4: 2301 movs r3, #1 } } 800f7c6: 4618 mov r0, r3 800f7c8: 3714 adds r7, #20 800f7ca: 46bd mov sp, r7 800f7cc: bc80 pop {r7} 800f7ce: 4770 bx lr 0800f7d0 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { 800f7d0: b580 push {r7, lr} 800f7d2: b08a sub sp, #40 @ 0x28 800f7d4: af00 add r7, sp, #0 800f7d6: 6078 str r0, [r7, #4] uint32_t errorcode = HAL_CAN_ERROR_NONE; 800f7d8: 2300 movs r3, #0 800f7da: 627b str r3, [r7, #36] @ 0x24 uint32_t interrupts = READ_REG(hcan->Instance->IER); 800f7dc: 687b ldr r3, [r7, #4] 800f7de: 681b ldr r3, [r3, #0] 800f7e0: 695b ldr r3, [r3, #20] 800f7e2: 623b str r3, [r7, #32] uint32_t msrflags = READ_REG(hcan->Instance->MSR); 800f7e4: 687b ldr r3, [r7, #4] 800f7e6: 681b ldr r3, [r3, #0] 800f7e8: 685b ldr r3, [r3, #4] 800f7ea: 61fb str r3, [r7, #28] uint32_t tsrflags = READ_REG(hcan->Instance->TSR); 800f7ec: 687b ldr r3, [r7, #4] 800f7ee: 681b ldr r3, [r3, #0] 800f7f0: 689b ldr r3, [r3, #8] 800f7f2: 61bb str r3, [r7, #24] uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); 800f7f4: 687b ldr r3, [r7, #4] 800f7f6: 681b ldr r3, [r3, #0] 800f7f8: 68db ldr r3, [r3, #12] 800f7fa: 617b str r3, [r7, #20] uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); 800f7fc: 687b ldr r3, [r7, #4] 800f7fe: 681b ldr r3, [r3, #0] 800f800: 691b ldr r3, [r3, #16] 800f802: 613b str r3, [r7, #16] uint32_t esrflags = READ_REG(hcan->Instance->ESR); 800f804: 687b ldr r3, [r7, #4] 800f806: 681b ldr r3, [r3, #0] 800f808: 699b ldr r3, [r3, #24] 800f80a: 60fb str r3, [r7, #12] /* Transmit Mailbox empty interrupt management *****************************/ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) 800f80c: 6a3b ldr r3, [r7, #32] 800f80e: f003 0301 and.w r3, r3, #1 800f812: 2b00 cmp r3, #0 800f814: d07c beq.n 800f910 { /* Transmit Mailbox 0 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP0) != 0U) 800f816: 69bb ldr r3, [r7, #24] 800f818: f003 0301 and.w r3, r3, #1 800f81c: 2b00 cmp r3, #0 800f81e: d023 beq.n 800f868 { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); 800f820: 687b ldr r3, [r7, #4] 800f822: 681b ldr r3, [r3, #0] 800f824: 2201 movs r2, #1 800f826: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK0) != 0U) 800f828: 69bb ldr r3, [r7, #24] 800f82a: f003 0302 and.w r3, r3, #2 800f82e: 2b00 cmp r3, #0 800f830: d003 beq.n 800f83a #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); 800f832: 6878 ldr r0, [r7, #4] 800f834: f000 f983 bl 800fb3e 800f838: e016 b.n 800f868 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST0) != 0U) 800f83a: 69bb ldr r3, [r7, #24] 800f83c: f003 0304 and.w r3, r3, #4 800f840: 2b00 cmp r3, #0 800f842: d004 beq.n 800f84e { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; 800f844: 6a7b ldr r3, [r7, #36] @ 0x24 800f846: f443 6300 orr.w r3, r3, #2048 @ 0x800 800f84a: 627b str r3, [r7, #36] @ 0x24 800f84c: e00c b.n 800f868 } else if ((tsrflags & CAN_TSR_TERR0) != 0U) 800f84e: 69bb ldr r3, [r7, #24] 800f850: f003 0308 and.w r3, r3, #8 800f854: 2b00 cmp r3, #0 800f856: d004 beq.n 800f862 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; 800f858: 6a7b ldr r3, [r7, #36] @ 0x24 800f85a: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800f85e: 627b str r3, [r7, #36] @ 0x24 800f860: e002 b.n 800f868 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); 800f862: 6878 ldr r0, [r7, #4] 800f864: f000 f986 bl 800fb74 } } } /* Transmit Mailbox 1 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP1) != 0U) 800f868: 69bb ldr r3, [r7, #24] 800f86a: f403 7380 and.w r3, r3, #256 @ 0x100 800f86e: 2b00 cmp r3, #0 800f870: d024 beq.n 800f8bc { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); 800f872: 687b ldr r3, [r7, #4] 800f874: 681b ldr r3, [r3, #0] 800f876: f44f 7280 mov.w r2, #256 @ 0x100 800f87a: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK1) != 0U) 800f87c: 69bb ldr r3, [r7, #24] 800f87e: f403 7300 and.w r3, r3, #512 @ 0x200 800f882: 2b00 cmp r3, #0 800f884: d003 beq.n 800f88e #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); 800f886: 6878 ldr r0, [r7, #4] 800f888: f000 f962 bl 800fb50 800f88c: e016 b.n 800f8bc #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST1) != 0U) 800f88e: 69bb ldr r3, [r7, #24] 800f890: f403 6380 and.w r3, r3, #1024 @ 0x400 800f894: 2b00 cmp r3, #0 800f896: d004 beq.n 800f8a2 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; 800f898: 6a7b ldr r3, [r7, #36] @ 0x24 800f89a: f443 5300 orr.w r3, r3, #8192 @ 0x2000 800f89e: 627b str r3, [r7, #36] @ 0x24 800f8a0: e00c b.n 800f8bc } else if ((tsrflags & CAN_TSR_TERR1) != 0U) 800f8a2: 69bb ldr r3, [r7, #24] 800f8a4: f403 6300 and.w r3, r3, #2048 @ 0x800 800f8a8: 2b00 cmp r3, #0 800f8aa: d004 beq.n 800f8b6 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; 800f8ac: 6a7b ldr r3, [r7, #36] @ 0x24 800f8ae: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800f8b2: 627b str r3, [r7, #36] @ 0x24 800f8b4: e002 b.n 800f8bc #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); 800f8b6: 6878 ldr r0, [r7, #4] 800f8b8: f000 f965 bl 800fb86 } } } /* Transmit Mailbox 2 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP2) != 0U) 800f8bc: 69bb ldr r3, [r7, #24] 800f8be: f403 3380 and.w r3, r3, #65536 @ 0x10000 800f8c2: 2b00 cmp r3, #0 800f8c4: d024 beq.n 800f910 { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); 800f8c6: 687b ldr r3, [r7, #4] 800f8c8: 681b ldr r3, [r3, #0] 800f8ca: f44f 3280 mov.w r2, #65536 @ 0x10000 800f8ce: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK2) != 0U) 800f8d0: 69bb ldr r3, [r7, #24] 800f8d2: f403 3300 and.w r3, r3, #131072 @ 0x20000 800f8d6: 2b00 cmp r3, #0 800f8d8: d003 beq.n 800f8e2 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); 800f8da: 6878 ldr r0, [r7, #4] 800f8dc: f000 f941 bl 800fb62 800f8e0: e016 b.n 800f910 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST2) != 0U) 800f8e2: 69bb ldr r3, [r7, #24] 800f8e4: f403 2380 and.w r3, r3, #262144 @ 0x40000 800f8e8: 2b00 cmp r3, #0 800f8ea: d004 beq.n 800f8f6 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; 800f8ec: 6a7b ldr r3, [r7, #36] @ 0x24 800f8ee: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f8f2: 627b str r3, [r7, #36] @ 0x24 800f8f4: e00c b.n 800f910 } else if ((tsrflags & CAN_TSR_TERR2) != 0U) 800f8f6: 69bb ldr r3, [r7, #24] 800f8f8: f403 2300 and.w r3, r3, #524288 @ 0x80000 800f8fc: 2b00 cmp r3, #0 800f8fe: d004 beq.n 800f90a { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; 800f900: 6a7b ldr r3, [r7, #36] @ 0x24 800f902: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800f906: 627b str r3, [r7, #36] @ 0x24 800f908: e002 b.n 800f910 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); 800f90a: 6878 ldr r0, [r7, #4] 800f90c: f000 f944 bl 800fb98 } } } /* Receive FIFO 0 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) 800f910: 6a3b ldr r3, [r7, #32] 800f912: f003 0308 and.w r3, r3, #8 800f916: 2b00 cmp r3, #0 800f918: d00c beq.n 800f934 { if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) 800f91a: 697b ldr r3, [r7, #20] 800f91c: f003 0310 and.w r3, r3, #16 800f920: 2b00 cmp r3, #0 800f922: d007 beq.n 800f934 { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; 800f924: 6a7b ldr r3, [r7, #36] @ 0x24 800f926: f443 7300 orr.w r3, r3, #512 @ 0x200 800f92a: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO0 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); 800f92c: 687b ldr r3, [r7, #4] 800f92e: 681b ldr r3, [r3, #0] 800f930: 2210 movs r2, #16 800f932: 60da str r2, [r3, #12] } } /* Receive FIFO 0 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) 800f934: 6a3b ldr r3, [r7, #32] 800f936: f003 0304 and.w r3, r3, #4 800f93a: 2b00 cmp r3, #0 800f93c: d00b beq.n 800f956 { if ((rf0rflags & CAN_RF0R_FULL0) != 0U) 800f93e: 697b ldr r3, [r7, #20] 800f940: f003 0308 and.w r3, r3, #8 800f944: 2b00 cmp r3, #0 800f946: d006 beq.n 800f956 { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); 800f948: 687b ldr r3, [r7, #4] 800f94a: 681b ldr r3, [r3, #0] 800f94c: 2208 movs r2, #8 800f94e: 60da str r2, [r3, #12] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); 800f950: 6878 ldr r0, [r7, #4] 800f952: f000 f933 bl 800fbbc #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) 800f956: 6a3b ldr r3, [r7, #32] 800f958: f003 0302 and.w r3, r3, #2 800f95c: 2b00 cmp r3, #0 800f95e: d009 beq.n 800f974 { /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) 800f960: 687b ldr r3, [r7, #4] 800f962: 681b ldr r3, [r3, #0] 800f964: 68db ldr r3, [r3, #12] 800f966: f003 0303 and.w r3, r3, #3 800f96a: 2b00 cmp r3, #0 800f96c: d002 beq.n 800f974 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); 800f96e: 6878 ldr r0, [r7, #4] 800f970: f000 f91b bl 800fbaa #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) 800f974: 6a3b ldr r3, [r7, #32] 800f976: f003 0340 and.w r3, r3, #64 @ 0x40 800f97a: 2b00 cmp r3, #0 800f97c: d00c beq.n 800f998 { if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) 800f97e: 693b ldr r3, [r7, #16] 800f980: f003 0310 and.w r3, r3, #16 800f984: 2b00 cmp r3, #0 800f986: d007 beq.n 800f998 { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; 800f988: 6a7b ldr r3, [r7, #36] @ 0x24 800f98a: f443 6380 orr.w r3, r3, #1024 @ 0x400 800f98e: 627b str r3, [r7, #36] @ 0x24 /* Clear FIFO1 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); 800f990: 687b ldr r3, [r7, #4] 800f992: 681b ldr r3, [r3, #0] 800f994: 2210 movs r2, #16 800f996: 611a str r2, [r3, #16] } } /* Receive FIFO 1 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) 800f998: 6a3b ldr r3, [r7, #32] 800f99a: f003 0320 and.w r3, r3, #32 800f99e: 2b00 cmp r3, #0 800f9a0: d00b beq.n 800f9ba { if ((rf1rflags & CAN_RF1R_FULL1) != 0U) 800f9a2: 693b ldr r3, [r7, #16] 800f9a4: f003 0308 and.w r3, r3, #8 800f9a8: 2b00 cmp r3, #0 800f9aa: d006 beq.n 800f9ba { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); 800f9ac: 687b ldr r3, [r7, #4] 800f9ae: 681b ldr r3, [r3, #0] 800f9b0: 2208 movs r2, #8 800f9b2: 611a str r2, [r3, #16] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); 800f9b4: 6878 ldr r0, [r7, #4] 800f9b6: f000 f90a bl 800fbce #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) 800f9ba: 6a3b ldr r3, [r7, #32] 800f9bc: f003 0310 and.w r3, r3, #16 800f9c0: 2b00 cmp r3, #0 800f9c2: d009 beq.n 800f9d8 { /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) 800f9c4: 687b ldr r3, [r7, #4] 800f9c6: 681b ldr r3, [r3, #0] 800f9c8: 691b ldr r3, [r3, #16] 800f9ca: f003 0303 and.w r3, r3, #3 800f9ce: 2b00 cmp r3, #0 800f9d0: d002 beq.n 800f9d8 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); 800f9d2: 6878 ldr r0, [r7, #4] 800f9d4: f7fb fa0a bl 800adec #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) 800f9d8: 6a3b ldr r3, [r7, #32] 800f9da: f403 3300 and.w r3, r3, #131072 @ 0x20000 800f9de: 2b00 cmp r3, #0 800f9e0: d00b beq.n 800f9fa { if ((msrflags & CAN_MSR_SLAKI) != 0U) 800f9e2: 69fb ldr r3, [r7, #28] 800f9e4: f003 0310 and.w r3, r3, #16 800f9e8: 2b00 cmp r3, #0 800f9ea: d006 beq.n 800f9fa { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); 800f9ec: 687b ldr r3, [r7, #4] 800f9ee: 681b ldr r3, [r3, #0] 800f9f0: 2210 movs r2, #16 800f9f2: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->SleepCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); 800f9f4: 6878 ldr r0, [r7, #4] 800f9f6: f000 f8f3 bl 800fbe0 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ if ((interrupts & CAN_IT_WAKEUP) != 0U) 800f9fa: 6a3b ldr r3, [r7, #32] 800f9fc: f403 3380 and.w r3, r3, #65536 @ 0x10000 800fa00: 2b00 cmp r3, #0 800fa02: d00b beq.n 800fa1c { if ((msrflags & CAN_MSR_WKUI) != 0U) 800fa04: 69fb ldr r3, [r7, #28] 800fa06: f003 0308 and.w r3, r3, #8 800fa0a: 2b00 cmp r3, #0 800fa0c: d006 beq.n 800fa1c { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); 800fa0e: 687b ldr r3, [r7, #4] 800fa10: 681b ldr r3, [r3, #0] 800fa12: 2208 movs r2, #8 800fa14: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->WakeUpFromRxMsgCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); 800fa16: 6878 ldr r0, [r7, #4] 800fa18: f000 f8eb bl 800fbf2 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ if ((interrupts & CAN_IT_ERROR) != 0U) 800fa1c: 6a3b ldr r3, [r7, #32] 800fa1e: f403 4300 and.w r3, r3, #32768 @ 0x8000 800fa22: 2b00 cmp r3, #0 800fa24: d07b beq.n 800fb1e { if ((msrflags & CAN_MSR_ERRI) != 0U) 800fa26: 69fb ldr r3, [r7, #28] 800fa28: f003 0304 and.w r3, r3, #4 800fa2c: 2b00 cmp r3, #0 800fa2e: d072 beq.n 800fb16 { /* Check Error Warning Flag */ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800fa30: 6a3b ldr r3, [r7, #32] 800fa32: f403 7380 and.w r3, r3, #256 @ 0x100 800fa36: 2b00 cmp r3, #0 800fa38: d008 beq.n 800fa4c ((esrflags & CAN_ESR_EWGF) != 0U)) 800fa3a: 68fb ldr r3, [r7, #12] 800fa3c: f003 0301 and.w r3, r3, #1 if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800fa40: 2b00 cmp r3, #0 800fa42: d003 beq.n 800fa4c { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; 800fa44: 6a7b ldr r3, [r7, #36] @ 0x24 800fa46: f043 0301 orr.w r3, r3, #1 800fa4a: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Warning Flag as read-only */ } /* Check Error Passive Flag */ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800fa4c: 6a3b ldr r3, [r7, #32] 800fa4e: f403 7300 and.w r3, r3, #512 @ 0x200 800fa52: 2b00 cmp r3, #0 800fa54: d008 beq.n 800fa68 ((esrflags & CAN_ESR_EPVF) != 0U)) 800fa56: 68fb ldr r3, [r7, #12] 800fa58: f003 0302 and.w r3, r3, #2 if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800fa5c: 2b00 cmp r3, #0 800fa5e: d003 beq.n 800fa68 { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; 800fa60: 6a7b ldr r3, [r7, #36] @ 0x24 800fa62: f043 0302 orr.w r3, r3, #2 800fa66: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-off Flag */ if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800fa68: 6a3b ldr r3, [r7, #32] 800fa6a: f403 6380 and.w r3, r3, #1024 @ 0x400 800fa6e: 2b00 cmp r3, #0 800fa70: d008 beq.n 800fa84 ((esrflags & CAN_ESR_BOFF) != 0U)) 800fa72: 68fb ldr r3, [r7, #12] 800fa74: f003 0304 and.w r3, r3, #4 if (((interrupts & CAN_IT_BUSOFF) != 0U) && 800fa78: 2b00 cmp r3, #0 800fa7a: d003 beq.n 800fa84 { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; 800fa7c: 6a7b ldr r3, [r7, #36] @ 0x24 800fa7e: f043 0304 orr.w r3, r3, #4 800fa82: 627b str r3, [r7, #36] @ 0x24 /* No need for clear of Error Bus-Off as read-only */ } /* Check Last Error Code Flag */ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800fa84: 6a3b ldr r3, [r7, #32] 800fa86: f403 6300 and.w r3, r3, #2048 @ 0x800 800fa8a: 2b00 cmp r3, #0 800fa8c: d043 beq.n 800fb16 ((esrflags & CAN_ESR_LEC) != 0U)) 800fa8e: 68fb ldr r3, [r7, #12] 800fa90: f003 0370 and.w r3, r3, #112 @ 0x70 if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 800fa94: 2b00 cmp r3, #0 800fa96: d03e beq.n 800fb16 { switch (esrflags & CAN_ESR_LEC) 800fa98: 68fb ldr r3, [r7, #12] 800fa9a: f003 0370 and.w r3, r3, #112 @ 0x70 800fa9e: 2b60 cmp r3, #96 @ 0x60 800faa0: d02b beq.n 800fafa 800faa2: 2b60 cmp r3, #96 @ 0x60 800faa4: d82e bhi.n 800fb04 800faa6: 2b50 cmp r3, #80 @ 0x50 800faa8: d022 beq.n 800faf0 800faaa: 2b50 cmp r3, #80 @ 0x50 800faac: d82a bhi.n 800fb04 800faae: 2b40 cmp r3, #64 @ 0x40 800fab0: d019 beq.n 800fae6 800fab2: 2b40 cmp r3, #64 @ 0x40 800fab4: d826 bhi.n 800fb04 800fab6: 2b30 cmp r3, #48 @ 0x30 800fab8: d010 beq.n 800fadc 800faba: 2b30 cmp r3, #48 @ 0x30 800fabc: d822 bhi.n 800fb04 800fabe: 2b10 cmp r3, #16 800fac0: d002 beq.n 800fac8 800fac2: 2b20 cmp r3, #32 800fac4: d005 beq.n 800fad2 case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): /* Set CAN error code to CRC error */ errorcode |= HAL_CAN_ERROR_CRC; break; default: break; 800fac6: e01d b.n 800fb04 errorcode |= HAL_CAN_ERROR_STF; 800fac8: 6a7b ldr r3, [r7, #36] @ 0x24 800faca: f043 0308 orr.w r3, r3, #8 800face: 627b str r3, [r7, #36] @ 0x24 break; 800fad0: e019 b.n 800fb06 errorcode |= HAL_CAN_ERROR_FOR; 800fad2: 6a7b ldr r3, [r7, #36] @ 0x24 800fad4: f043 0310 orr.w r3, r3, #16 800fad8: 627b str r3, [r7, #36] @ 0x24 break; 800fada: e014 b.n 800fb06 errorcode |= HAL_CAN_ERROR_ACK; 800fadc: 6a7b ldr r3, [r7, #36] @ 0x24 800fade: f043 0320 orr.w r3, r3, #32 800fae2: 627b str r3, [r7, #36] @ 0x24 break; 800fae4: e00f b.n 800fb06 errorcode |= HAL_CAN_ERROR_BR; 800fae6: 6a7b ldr r3, [r7, #36] @ 0x24 800fae8: f043 0340 orr.w r3, r3, #64 @ 0x40 800faec: 627b str r3, [r7, #36] @ 0x24 break; 800faee: e00a b.n 800fb06 errorcode |= HAL_CAN_ERROR_BD; 800faf0: 6a7b ldr r3, [r7, #36] @ 0x24 800faf2: f043 0380 orr.w r3, r3, #128 @ 0x80 800faf6: 627b str r3, [r7, #36] @ 0x24 break; 800faf8: e005 b.n 800fb06 errorcode |= HAL_CAN_ERROR_CRC; 800fafa: 6a7b ldr r3, [r7, #36] @ 0x24 800fafc: f443 7380 orr.w r3, r3, #256 @ 0x100 800fb00: 627b str r3, [r7, #36] @ 0x24 break; 800fb02: e000 b.n 800fb06 break; 800fb04: bf00 nop } /* Clear Last error code Flag */ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); 800fb06: 687b ldr r3, [r7, #4] 800fb08: 681b ldr r3, [r3, #0] 800fb0a: 699a ldr r2, [r3, #24] 800fb0c: 687b ldr r3, [r7, #4] 800fb0e: 681b ldr r3, [r3, #0] 800fb10: f022 0270 bic.w r2, r2, #112 @ 0x70 800fb14: 619a str r2, [r3, #24] } } /* Clear ERRI Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); 800fb16: 687b ldr r3, [r7, #4] 800fb18: 681b ldr r3, [r3, #0] 800fb1a: 2204 movs r2, #4 800fb1c: 605a str r2, [r3, #4] } /* Call the Error call Back in case of Errors */ if (errorcode != HAL_CAN_ERROR_NONE) 800fb1e: 6a7b ldr r3, [r7, #36] @ 0x24 800fb20: 2b00 cmp r3, #0 800fb22: d008 beq.n 800fb36 { /* Update error code in handle */ hcan->ErrorCode |= errorcode; 800fb24: 687b ldr r3, [r7, #4] 800fb26: 6a5a ldr r2, [r3, #36] @ 0x24 800fb28: 6a7b ldr r3, [r7, #36] @ 0x24 800fb2a: 431a orrs r2, r3 800fb2c: 687b ldr r3, [r7, #4] 800fb2e: 625a str r2, [r3, #36] @ 0x24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->ErrorCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); 800fb30: 6878 ldr r0, [r7, #4] 800fb32: f000 f867 bl 800fc04 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } 800fb36: bf00 nop 800fb38: 3728 adds r7, #40 @ 0x28 800fb3a: 46bd mov sp, r7 800fb3c: bd80 pop {r7, pc} 0800fb3e : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { 800fb3e: b480 push {r7} 800fb40: b083 sub sp, #12 800fb42: af00 add r7, sp, #0 800fb44: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the user file */ } 800fb46: bf00 nop 800fb48: 370c adds r7, #12 800fb4a: 46bd mov sp, r7 800fb4c: bc80 pop {r7} 800fb4e: 4770 bx lr 0800fb50 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { 800fb50: b480 push {r7} 800fb52: b083 sub sp, #12 800fb54: af00 add r7, sp, #0 800fb56: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the user file */ } 800fb58: bf00 nop 800fb5a: 370c adds r7, #12 800fb5c: 46bd mov sp, r7 800fb5e: bc80 pop {r7} 800fb60: 4770 bx lr 0800fb62 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) { 800fb62: b480 push {r7} 800fb64: b083 sub sp, #12 800fb66: af00 add r7, sp, #0 800fb68: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the user file */ } 800fb6a: bf00 nop 800fb6c: 370c adds r7, #12 800fb6e: 46bd mov sp, r7 800fb70: bc80 pop {r7} 800fb72: 4770 bx lr 0800fb74 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { 800fb74: b480 push {r7} 800fb76: b083 sub sp, #12 800fb78: af00 add r7, sp, #0 800fb7a: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0AbortCallback could be implemented in the user file */ } 800fb7c: bf00 nop 800fb7e: 370c adds r7, #12 800fb80: 46bd mov sp, r7 800fb82: bc80 pop {r7} 800fb84: 4770 bx lr 0800fb86 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { 800fb86: b480 push {r7} 800fb88: b083 sub sp, #12 800fb8a: af00 add r7, sp, #0 800fb8c: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1AbortCallback could be implemented in the user file */ } 800fb8e: bf00 nop 800fb90: 370c adds r7, #12 800fb92: 46bd mov sp, r7 800fb94: bc80 pop {r7} 800fb96: 4770 bx lr 0800fb98 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { 800fb98: b480 push {r7} 800fb9a: b083 sub sp, #12 800fb9c: af00 add r7, sp, #0 800fb9e: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2AbortCallback could be implemented in the user file */ } 800fba0: bf00 nop 800fba2: 370c adds r7, #12 800fba4: 46bd mov sp, r7 800fba6: bc80 pop {r7} 800fba8: 4770 bx lr 0800fbaa : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) { 800fbaa: b480 push {r7} 800fbac: b083 sub sp, #12 800fbae: af00 add r7, sp, #0 800fbb0: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the user file */ } 800fbb2: bf00 nop 800fbb4: 370c adds r7, #12 800fbb6: 46bd mov sp, r7 800fbb8: bc80 pop {r7} 800fbba: 4770 bx lr 0800fbbc : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { 800fbbc: b480 push {r7} 800fbbe: b083 sub sp, #12 800fbc0: af00 add r7, sp, #0 800fbc2: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0FullCallback could be implemented in the user file */ } 800fbc4: bf00 nop 800fbc6: 370c adds r7, #12 800fbc8: 46bd mov sp, r7 800fbca: bc80 pop {r7} 800fbcc: 4770 bx lr 0800fbce : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { 800fbce: b480 push {r7} 800fbd0: b083 sub sp, #12 800fbd2: af00 add r7, sp, #0 800fbd4: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1FullCallback could be implemented in the user file */ } 800fbd6: bf00 nop 800fbd8: 370c adds r7, #12 800fbda: 46bd mov sp, r7 800fbdc: bc80 pop {r7} 800fbde: 4770 bx lr 0800fbe0 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { 800fbe0: b480 push {r7} 800fbe2: b083 sub sp, #12 800fbe4: af00 add r7, sp, #0 800fbe6: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_SleepCallback could be implemented in the user file */ } 800fbe8: bf00 nop 800fbea: 370c adds r7, #12 800fbec: 46bd mov sp, r7 800fbee: bc80 pop {r7} 800fbf0: 4770 bx lr 0800fbf2 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { 800fbf2: b480 push {r7} 800fbf4: b083 sub sp, #12 800fbf6: af00 add r7, sp, #0 800fbf8: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the user file */ } 800fbfa: bf00 nop 800fbfc: 370c adds r7, #12 800fbfe: 46bd mov sp, r7 800fc00: bc80 pop {r7} 800fc02: 4770 bx lr 0800fc04 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { 800fc04: b480 push {r7} 800fc06: b083 sub sp, #12 800fc08: af00 add r7, sp, #0 800fc0a: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } 800fc0c: bf00 nop 800fc0e: 370c adds r7, #12 800fc10: 46bd mov sp, r7 800fc12: bc80 pop {r7} 800fc14: 4770 bx lr ... 0800fc18 <__NVIC_SetPriorityGrouping>: { 800fc18: b480 push {r7} 800fc1a: b085 sub sp, #20 800fc1c: af00 add r7, sp, #0 800fc1e: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800fc20: 687b ldr r3, [r7, #4] 800fc22: f003 0307 and.w r3, r3, #7 800fc26: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 800fc28: 4b0c ldr r3, [pc, #48] @ (800fc5c <__NVIC_SetPriorityGrouping+0x44>) 800fc2a: 68db ldr r3, [r3, #12] 800fc2c: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800fc2e: 68ba ldr r2, [r7, #8] 800fc30: f64f 03ff movw r3, #63743 @ 0xf8ff 800fc34: 4013 ands r3, r2 800fc36: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 800fc38: 68fb ldr r3, [r7, #12] 800fc3a: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800fc3c: 68bb ldr r3, [r7, #8] 800fc3e: 4313 orrs r3, r2 reg_value = (reg_value | 800fc40: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 800fc44: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800fc48: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800fc4a: 4a04 ldr r2, [pc, #16] @ (800fc5c <__NVIC_SetPriorityGrouping+0x44>) 800fc4c: 68bb ldr r3, [r7, #8] 800fc4e: 60d3 str r3, [r2, #12] } 800fc50: bf00 nop 800fc52: 3714 adds r7, #20 800fc54: 46bd mov sp, r7 800fc56: bc80 pop {r7} 800fc58: 4770 bx lr 800fc5a: bf00 nop 800fc5c: e000ed00 .word 0xe000ed00 0800fc60 <__NVIC_GetPriorityGrouping>: { 800fc60: b480 push {r7} 800fc62: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800fc64: 4b04 ldr r3, [pc, #16] @ (800fc78 <__NVIC_GetPriorityGrouping+0x18>) 800fc66: 68db ldr r3, [r3, #12] 800fc68: 0a1b lsrs r3, r3, #8 800fc6a: f003 0307 and.w r3, r3, #7 } 800fc6e: 4618 mov r0, r3 800fc70: 46bd mov sp, r7 800fc72: bc80 pop {r7} 800fc74: 4770 bx lr 800fc76: bf00 nop 800fc78: e000ed00 .word 0xe000ed00 0800fc7c <__NVIC_EnableIRQ>: { 800fc7c: b480 push {r7} 800fc7e: b083 sub sp, #12 800fc80: af00 add r7, sp, #0 800fc82: 4603 mov r3, r0 800fc84: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800fc86: f997 3007 ldrsb.w r3, [r7, #7] 800fc8a: 2b00 cmp r3, #0 800fc8c: db0b blt.n 800fca6 <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800fc8e: 79fb ldrb r3, [r7, #7] 800fc90: f003 021f and.w r2, r3, #31 800fc94: 4906 ldr r1, [pc, #24] @ (800fcb0 <__NVIC_EnableIRQ+0x34>) 800fc96: f997 3007 ldrsb.w r3, [r7, #7] 800fc9a: 095b lsrs r3, r3, #5 800fc9c: 2001 movs r0, #1 800fc9e: fa00 f202 lsl.w r2, r0, r2 800fca2: f841 2023 str.w r2, [r1, r3, lsl #2] } 800fca6: bf00 nop 800fca8: 370c adds r7, #12 800fcaa: 46bd mov sp, r7 800fcac: bc80 pop {r7} 800fcae: 4770 bx lr 800fcb0: e000e100 .word 0xe000e100 0800fcb4 <__NVIC_SetPriority>: { 800fcb4: b480 push {r7} 800fcb6: b083 sub sp, #12 800fcb8: af00 add r7, sp, #0 800fcba: 4603 mov r3, r0 800fcbc: 6039 str r1, [r7, #0] 800fcbe: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800fcc0: f997 3007 ldrsb.w r3, [r7, #7] 800fcc4: 2b00 cmp r3, #0 800fcc6: db0a blt.n 800fcde <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800fcc8: 683b ldr r3, [r7, #0] 800fcca: b2da uxtb r2, r3 800fccc: 490c ldr r1, [pc, #48] @ (800fd00 <__NVIC_SetPriority+0x4c>) 800fcce: f997 3007 ldrsb.w r3, [r7, #7] 800fcd2: 0112 lsls r2, r2, #4 800fcd4: b2d2 uxtb r2, r2 800fcd6: 440b add r3, r1 800fcd8: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 800fcdc: e00a b.n 800fcf4 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800fcde: 683b ldr r3, [r7, #0] 800fce0: b2da uxtb r2, r3 800fce2: 4908 ldr r1, [pc, #32] @ (800fd04 <__NVIC_SetPriority+0x50>) 800fce4: 79fb ldrb r3, [r7, #7] 800fce6: f003 030f and.w r3, r3, #15 800fcea: 3b04 subs r3, #4 800fcec: 0112 lsls r2, r2, #4 800fcee: b2d2 uxtb r2, r2 800fcf0: 440b add r3, r1 800fcf2: 761a strb r2, [r3, #24] } 800fcf4: bf00 nop 800fcf6: 370c adds r7, #12 800fcf8: 46bd mov sp, r7 800fcfa: bc80 pop {r7} 800fcfc: 4770 bx lr 800fcfe: bf00 nop 800fd00: e000e100 .word 0xe000e100 800fd04: e000ed00 .word 0xe000ed00 0800fd08 : { 800fd08: b480 push {r7} 800fd0a: b089 sub sp, #36 @ 0x24 800fd0c: af00 add r7, sp, #0 800fd0e: 60f8 str r0, [r7, #12] 800fd10: 60b9 str r1, [r7, #8] 800fd12: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800fd14: 68fb ldr r3, [r7, #12] 800fd16: f003 0307 and.w r3, r3, #7 800fd1a: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 800fd1c: 69fb ldr r3, [r7, #28] 800fd1e: f1c3 0307 rsb r3, r3, #7 800fd22: 2b04 cmp r3, #4 800fd24: bf28 it cs 800fd26: 2304 movcs r3, #4 800fd28: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800fd2a: 69fb ldr r3, [r7, #28] 800fd2c: 3304 adds r3, #4 800fd2e: 2b06 cmp r3, #6 800fd30: d902 bls.n 800fd38 800fd32: 69fb ldr r3, [r7, #28] 800fd34: 3b03 subs r3, #3 800fd36: e000 b.n 800fd3a 800fd38: 2300 movs r3, #0 800fd3a: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800fd3c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800fd40: 69bb ldr r3, [r7, #24] 800fd42: fa02 f303 lsl.w r3, r2, r3 800fd46: 43da mvns r2, r3 800fd48: 68bb ldr r3, [r7, #8] 800fd4a: 401a ands r2, r3 800fd4c: 697b ldr r3, [r7, #20] 800fd4e: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 800fd50: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800fd54: 697b ldr r3, [r7, #20] 800fd56: fa01 f303 lsl.w r3, r1, r3 800fd5a: 43d9 mvns r1, r3 800fd5c: 687b ldr r3, [r7, #4] 800fd5e: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800fd60: 4313 orrs r3, r2 } 800fd62: 4618 mov r0, r3 800fd64: 3724 adds r7, #36 @ 0x24 800fd66: 46bd mov sp, r7 800fd68: bc80 pop {r7} 800fd6a: 4770 bx lr 0800fd6c : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800fd6c: b580 push {r7, lr} 800fd6e: b082 sub sp, #8 800fd70: af00 add r7, sp, #0 800fd72: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 800fd74: 687b ldr r3, [r7, #4] 800fd76: 3b01 subs r3, #1 800fd78: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800fd7c: d301 bcc.n 800fd82 { return (1UL); /* Reload value impossible */ 800fd7e: 2301 movs r3, #1 800fd80: e00f b.n 800fda2 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800fd82: 4a0a ldr r2, [pc, #40] @ (800fdac ) 800fd84: 687b ldr r3, [r7, #4] 800fd86: 3b01 subs r3, #1 800fd88: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800fd8a: 210f movs r1, #15 800fd8c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800fd90: f7ff ff90 bl 800fcb4 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 800fd94: 4b05 ldr r3, [pc, #20] @ (800fdac ) 800fd96: 2200 movs r2, #0 800fd98: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800fd9a: 4b04 ldr r3, [pc, #16] @ (800fdac ) 800fd9c: 2207 movs r2, #7 800fd9e: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 800fda0: 2300 movs r3, #0 } 800fda2: 4618 mov r0, r3 800fda4: 3708 adds r7, #8 800fda6: 46bd mov sp, r7 800fda8: bd80 pop {r7, pc} 800fdaa: bf00 nop 800fdac: e000e010 .word 0xe000e010 0800fdb0 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 800fdb0: b580 push {r7, lr} 800fdb2: b082 sub sp, #8 800fdb4: af00 add r7, sp, #0 800fdb6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800fdb8: 6878 ldr r0, [r7, #4] 800fdba: f7ff ff2d bl 800fc18 <__NVIC_SetPriorityGrouping> } 800fdbe: bf00 nop 800fdc0: 3708 adds r7, #8 800fdc2: 46bd mov sp, r7 800fdc4: bd80 pop {r7, pc} 0800fdc6 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800fdc6: b580 push {r7, lr} 800fdc8: b086 sub sp, #24 800fdca: af00 add r7, sp, #0 800fdcc: 4603 mov r3, r0 800fdce: 60b9 str r1, [r7, #8] 800fdd0: 607a str r2, [r7, #4] 800fdd2: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 800fdd4: 2300 movs r3, #0 800fdd6: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800fdd8: f7ff ff42 bl 800fc60 <__NVIC_GetPriorityGrouping> 800fddc: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 800fdde: 687a ldr r2, [r7, #4] 800fde0: 68b9 ldr r1, [r7, #8] 800fde2: 6978 ldr r0, [r7, #20] 800fde4: f7ff ff90 bl 800fd08 800fde8: 4602 mov r2, r0 800fdea: f997 300f ldrsb.w r3, [r7, #15] 800fdee: 4611 mov r1, r2 800fdf0: 4618 mov r0, r3 800fdf2: f7ff ff5f bl 800fcb4 <__NVIC_SetPriority> } 800fdf6: bf00 nop 800fdf8: 3718 adds r7, #24 800fdfa: 46bd mov sp, r7 800fdfc: bd80 pop {r7, pc} 0800fdfe : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 800fdfe: b580 push {r7, lr} 800fe00: b082 sub sp, #8 800fe02: af00 add r7, sp, #0 800fe04: 4603 mov r3, r0 800fe06: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800fe08: f997 3007 ldrsb.w r3, [r7, #7] 800fe0c: 4618 mov r0, r3 800fe0e: f7ff ff35 bl 800fc7c <__NVIC_EnableIRQ> } 800fe12: bf00 nop 800fe14: 3708 adds r7, #8 800fe16: 46bd mov sp, r7 800fe18: bd80 pop {r7, pc} 0800fe1a : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800fe1a: b580 push {r7, lr} 800fe1c: b082 sub sp, #8 800fe1e: af00 add r7, sp, #0 800fe20: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800fe22: 6878 ldr r0, [r7, #4] 800fe24: f7ff ffa2 bl 800fd6c 800fe28: 4603 mov r3, r0 } 800fe2a: 4618 mov r0, r3 800fe2c: 3708 adds r7, #8 800fe2e: 46bd mov sp, r7 800fe30: bd80 pop {r7, pc} 0800fe32 : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 800fe32: b580 push {r7, lr} 800fe34: b082 sub sp, #8 800fe36: af00 add r7, sp, #0 800fe38: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 800fe3a: 687b ldr r3, [r7, #4] 800fe3c: 2b00 cmp r3, #0 800fe3e: d101 bne.n 800fe44 { return HAL_ERROR; 800fe40: 2301 movs r3, #1 800fe42: e00e b.n 800fe62 } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 800fe44: 687b ldr r3, [r7, #4] 800fe46: 795b ldrb r3, [r3, #5] 800fe48: b2db uxtb r3, r3 800fe4a: 2b00 cmp r3, #0 800fe4c: d105 bne.n 800fe5a { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 800fe4e: 687b ldr r3, [r7, #4] 800fe50: 2200 movs r2, #0 800fe52: 711a strb r2, [r3, #4] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 800fe54: 6878 ldr r0, [r7, #4] 800fe56: f7fa fa83 bl 800a360 } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 800fe5a: 687b ldr r3, [r7, #4] 800fe5c: 2201 movs r2, #1 800fe5e: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 800fe60: 2300 movs r3, #0 } 800fe62: 4618 mov r0, r3 800fe64: 3708 adds r7, #8 800fe66: 46bd mov sp, r7 800fe68: bd80 pop {r7, pc} ... 0800fe6c : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 800fe6c: b480 push {r7} 800fe6e: b085 sub sp, #20 800fe70: af00 add r7, sp, #0 800fe72: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 800fe74: 2300 movs r3, #0 800fe76: 60fb str r3, [r7, #12] /* Check the DMA handle allocation */ if(hdma == NULL) 800fe78: 687b ldr r3, [r7, #4] 800fe7a: 2b00 cmp r3, #0 800fe7c: d101 bne.n 800fe82 { return HAL_ERROR; 800fe7e: 2301 movs r3, #1 800fe80: e059 b.n 800ff36 assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); #if defined (DMA2) /* calculation of the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 800fe82: 687b ldr r3, [r7, #4] 800fe84: 681b ldr r3, [r3, #0] 800fe86: 461a mov r2, r3 800fe88: 4b2d ldr r3, [pc, #180] @ (800ff40 ) 800fe8a: 429a cmp r2, r3 800fe8c: d80f bhi.n 800feae { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 800fe8e: 687b ldr r3, [r7, #4] 800fe90: 681b ldr r3, [r3, #0] 800fe92: 461a mov r2, r3 800fe94: 4b2b ldr r3, [pc, #172] @ (800ff44 ) 800fe96: 4413 add r3, r2 800fe98: 4a2b ldr r2, [pc, #172] @ (800ff48 ) 800fe9a: fba2 2303 umull r2, r3, r2, r3 800fe9e: 091b lsrs r3, r3, #4 800fea0: 009a lsls r2, r3, #2 800fea2: 687b ldr r3, [r7, #4] 800fea4: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA1; 800fea6: 687b ldr r3, [r7, #4] 800fea8: 4a28 ldr r2, [pc, #160] @ (800ff4c ) 800feaa: 63da str r2, [r3, #60] @ 0x3c 800feac: e00e b.n 800fecc } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; 800feae: 687b ldr r3, [r7, #4] 800feb0: 681b ldr r3, [r3, #0] 800feb2: 461a mov r2, r3 800feb4: 4b26 ldr r3, [pc, #152] @ (800ff50 ) 800feb6: 4413 add r3, r2 800feb8: 4a23 ldr r2, [pc, #140] @ (800ff48 ) 800feba: fba2 2303 umull r2, r3, r2, r3 800febe: 091b lsrs r3, r3, #4 800fec0: 009a lsls r2, r3, #2 800fec2: 687b ldr r3, [r7, #4] 800fec4: 641a str r2, [r3, #64] @ 0x40 hdma->DmaBaseAddress = DMA2; 800fec6: 687b ldr r3, [r7, #4] 800fec8: 4a22 ldr r2, [pc, #136] @ (800ff54 ) 800feca: 63da str r2, [r3, #60] @ 0x3c hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; #endif /* DMA2 */ /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 800fecc: 687b ldr r3, [r7, #4] 800fece: 2202 movs r2, #2 800fed0: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Get the CR register value */ tmp = hdma->Instance->CCR; 800fed4: 687b ldr r3, [r7, #4] 800fed6: 681b ldr r3, [r3, #0] 800fed8: 681b ldr r3, [r3, #0] 800feda: 60fb str r3, [r7, #12] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 800fedc: 68fb ldr r3, [r7, #12] 800fede: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 800fee2: f023 0330 bic.w r3, r3, #48 @ 0x30 800fee6: 60fb str r3, [r7, #12] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 800fee8: 687b ldr r3, [r7, #4] 800feea: 685a ldr r2, [r3, #4] hdma->Init.PeriphInc | hdma->Init.MemInc | 800feec: 687b ldr r3, [r7, #4] 800feee: 689b ldr r3, [r3, #8] tmp |= hdma->Init.Direction | 800fef0: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 800fef2: 687b ldr r3, [r7, #4] 800fef4: 68db ldr r3, [r3, #12] 800fef6: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800fef8: 687b ldr r3, [r7, #4] 800fefa: 691b ldr r3, [r3, #16] hdma->Init.PeriphInc | hdma->Init.MemInc | 800fefc: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800fefe: 687b ldr r3, [r7, #4] 800ff00: 695b ldr r3, [r3, #20] 800ff02: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800ff04: 687b ldr r3, [r7, #4] 800ff06: 699b ldr r3, [r3, #24] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800ff08: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800ff0a: 687b ldr r3, [r7, #4] 800ff0c: 69db ldr r3, [r3, #28] 800ff0e: 4313 orrs r3, r2 tmp |= hdma->Init.Direction | 800ff10: 68fa ldr r2, [r7, #12] 800ff12: 4313 orrs r3, r2 800ff14: 60fb str r3, [r7, #12] /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; 800ff16: 687b ldr r3, [r7, #4] 800ff18: 681b ldr r3, [r3, #0] 800ff1a: 68fa ldr r2, [r7, #12] 800ff1c: 601a str r2, [r3, #0] /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800ff1e: 687b ldr r3, [r7, #4] 800ff20: 2200 movs r2, #0 800ff22: 639a str r2, [r3, #56] @ 0x38 /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 800ff24: 687b ldr r3, [r7, #4] 800ff26: 2201 movs r2, #1 800ff28: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; 800ff2c: 687b ldr r3, [r7, #4] 800ff2e: 2200 movs r2, #0 800ff30: f883 2020 strb.w r2, [r3, #32] return HAL_OK; 800ff34: 2300 movs r3, #0 } 800ff36: 4618 mov r0, r3 800ff38: 3714 adds r7, #20 800ff3a: 46bd mov sp, r7 800ff3c: bc80 pop {r7} 800ff3e: 4770 bx lr 800ff40: 40020407 .word 0x40020407 800ff44: bffdfff8 .word 0xbffdfff8 800ff48: cccccccd .word 0xcccccccd 800ff4c: 40020000 .word 0x40020000 800ff50: bffdfbf8 .word 0xbffdfbf8 800ff54: 40020400 .word 0x40020400 0800ff58 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 800ff58: b580 push {r7, lr} 800ff5a: b086 sub sp, #24 800ff5c: af00 add r7, sp, #0 800ff5e: 60f8 str r0, [r7, #12] 800ff60: 60b9 str r1, [r7, #8] 800ff62: 607a str r2, [r7, #4] 800ff64: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800ff66: 2300 movs r3, #0 800ff68: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 800ff6a: 68fb ldr r3, [r7, #12] 800ff6c: f893 3020 ldrb.w r3, [r3, #32] 800ff70: 2b01 cmp r3, #1 800ff72: d101 bne.n 800ff78 800ff74: 2302 movs r3, #2 800ff76: e04b b.n 8010010 800ff78: 68fb ldr r3, [r7, #12] 800ff7a: 2201 movs r2, #1 800ff7c: f883 2020 strb.w r2, [r3, #32] if(HAL_DMA_STATE_READY == hdma->State) 800ff80: 68fb ldr r3, [r7, #12] 800ff82: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800ff86: b2db uxtb r3, r3 800ff88: 2b01 cmp r3, #1 800ff8a: d13a bne.n 8010002 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 800ff8c: 68fb ldr r3, [r7, #12] 800ff8e: 2202 movs r2, #2 800ff90: f883 2021 strb.w r2, [r3, #33] @ 0x21 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800ff94: 68fb ldr r3, [r7, #12] 800ff96: 2200 movs r2, #0 800ff98: 639a str r2, [r3, #56] @ 0x38 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 800ff9a: 68fb ldr r3, [r7, #12] 800ff9c: 681b ldr r3, [r3, #0] 800ff9e: 681a ldr r2, [r3, #0] 800ffa0: 68fb ldr r3, [r7, #12] 800ffa2: 681b ldr r3, [r3, #0] 800ffa4: f022 0201 bic.w r2, r2, #1 800ffa8: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 800ffaa: 683b ldr r3, [r7, #0] 800ffac: 687a ldr r2, [r7, #4] 800ffae: 68b9 ldr r1, [r7, #8] 800ffb0: 68f8 ldr r0, [r7, #12] 800ffb2: f000 fbbc bl 801072e /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if(NULL != hdma->XferHalfCpltCallback) 800ffb6: 68fb ldr r3, [r7, #12] 800ffb8: 6adb ldr r3, [r3, #44] @ 0x2c 800ffba: 2b00 cmp r3, #0 800ffbc: d008 beq.n 800ffd0 { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800ffbe: 68fb ldr r3, [r7, #12] 800ffc0: 681b ldr r3, [r3, #0] 800ffc2: 681a ldr r2, [r3, #0] 800ffc4: 68fb ldr r3, [r7, #12] 800ffc6: 681b ldr r3, [r3, #0] 800ffc8: f042 020e orr.w r2, r2, #14 800ffcc: 601a str r2, [r3, #0] 800ffce: e00f b.n 800fff0 } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800ffd0: 68fb ldr r3, [r7, #12] 800ffd2: 681b ldr r3, [r3, #0] 800ffd4: 681a ldr r2, [r3, #0] 800ffd6: 68fb ldr r3, [r7, #12] 800ffd8: 681b ldr r3, [r3, #0] 800ffda: f022 0204 bic.w r2, r2, #4 800ffde: 601a str r2, [r3, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 800ffe0: 68fb ldr r3, [r7, #12] 800ffe2: 681b ldr r3, [r3, #0] 800ffe4: 681a ldr r2, [r3, #0] 800ffe6: 68fb ldr r3, [r7, #12] 800ffe8: 681b ldr r3, [r3, #0] 800ffea: f042 020a orr.w r2, r2, #10 800ffee: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 800fff0: 68fb ldr r3, [r7, #12] 800fff2: 681b ldr r3, [r3, #0] 800fff4: 681a ldr r2, [r3, #0] 800fff6: 68fb ldr r3, [r7, #12] 800fff8: 681b ldr r3, [r3, #0] 800fffa: f042 0201 orr.w r2, r2, #1 800fffe: 601a str r2, [r3, #0] 8010000: e005 b.n 801000e } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); 8010002: 68fb ldr r3, [r7, #12] 8010004: 2200 movs r2, #0 8010006: f883 2020 strb.w r2, [r3, #32] /* Remain BUSY */ status = HAL_BUSY; 801000a: 2302 movs r3, #2 801000c: 75fb strb r3, [r7, #23] } return status; 801000e: 7dfb ldrb r3, [r7, #23] } 8010010: 4618 mov r0, r3 8010012: 3718 adds r7, #24 8010014: 46bd mov sp, r7 8010016: bd80 pop {r7, pc} 08010018 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8010018: b480 push {r7} 801001a: b085 sub sp, #20 801001c: af00 add r7, sp, #0 801001e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8010020: 2300 movs r3, #0 8010022: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 8010024: 687b ldr r3, [r7, #4] 8010026: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 801002a: b2db uxtb r3, r3 801002c: 2b02 cmp r3, #2 801002e: d008 beq.n 8010042 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8010030: 687b ldr r3, [r7, #4] 8010032: 2204 movs r2, #4 8010034: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8010036: 687b ldr r3, [r7, #4] 8010038: 2200 movs r2, #0 801003a: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 801003e: 2301 movs r3, #1 8010040: e020 b.n 8010084 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8010042: 687b ldr r3, [r7, #4] 8010044: 681b ldr r3, [r3, #0] 8010046: 681a ldr r2, [r3, #0] 8010048: 687b ldr r3, [r7, #4] 801004a: 681b ldr r3, [r3, #0] 801004c: f022 020e bic.w r2, r2, #14 8010050: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8010052: 687b ldr r3, [r7, #4] 8010054: 681b ldr r3, [r3, #0] 8010056: 681a ldr r2, [r3, #0] 8010058: 687b ldr r3, [r7, #4] 801005a: 681b ldr r3, [r3, #0] 801005c: f022 0201 bic.w r2, r2, #1 8010060: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8010062: 687b ldr r3, [r7, #4] 8010064: 6c1a ldr r2, [r3, #64] @ 0x40 8010066: 687b ldr r3, [r7, #4] 8010068: 6bdb ldr r3, [r3, #60] @ 0x3c 801006a: 2101 movs r1, #1 801006c: fa01 f202 lsl.w r2, r1, r2 8010070: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8010072: 687b ldr r3, [r7, #4] 8010074: 2201 movs r2, #1 8010076: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 801007a: 687b ldr r3, [r7, #4] 801007c: 2200 movs r2, #0 801007e: f883 2020 strb.w r2, [r3, #32] return status; 8010082: 7bfb ldrb r3, [r7, #15] } 8010084: 4618 mov r0, r3 8010086: 3714 adds r7, #20 8010088: 46bd mov sp, r7 801008a: bc80 pop {r7} 801008c: 4770 bx lr ... 08010090 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8010090: b580 push {r7, lr} 8010092: b084 sub sp, #16 8010094: af00 add r7, sp, #0 8010096: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8010098: 2300 movs r3, #0 801009a: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 801009c: 687b ldr r3, [r7, #4] 801009e: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 80100a2: b2db uxtb r3, r3 80100a4: 2b02 cmp r3, #2 80100a6: d005 beq.n 80100b4 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80100a8: 687b ldr r3, [r7, #4] 80100aa: 2204 movs r2, #4 80100ac: 639a str r2, [r3, #56] @ 0x38 status = HAL_ERROR; 80100ae: 2301 movs r3, #1 80100b0: 73fb strb r3, [r7, #15] 80100b2: e0d6 b.n 8010262 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80100b4: 687b ldr r3, [r7, #4] 80100b6: 681b ldr r3, [r3, #0] 80100b8: 681a ldr r2, [r3, #0] 80100ba: 687b ldr r3, [r7, #4] 80100bc: 681b ldr r3, [r3, #0] 80100be: f022 020e bic.w r2, r2, #14 80100c2: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 80100c4: 687b ldr r3, [r7, #4] 80100c6: 681b ldr r3, [r3, #0] 80100c8: 681a ldr r2, [r3, #0] 80100ca: 687b ldr r3, [r7, #4] 80100cc: 681b ldr r3, [r3, #0] 80100ce: f022 0201 bic.w r2, r2, #1 80100d2: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 80100d4: 687b ldr r3, [r7, #4] 80100d6: 681b ldr r3, [r3, #0] 80100d8: 461a mov r2, r3 80100da: 4b64 ldr r3, [pc, #400] @ (801026c ) 80100dc: 429a cmp r2, r3 80100de: d958 bls.n 8010192 80100e0: 687b ldr r3, [r7, #4] 80100e2: 681b ldr r3, [r3, #0] 80100e4: 4a62 ldr r2, [pc, #392] @ (8010270 ) 80100e6: 4293 cmp r3, r2 80100e8: d04f beq.n 801018a 80100ea: 687b ldr r3, [r7, #4] 80100ec: 681b ldr r3, [r3, #0] 80100ee: 4a61 ldr r2, [pc, #388] @ (8010274 ) 80100f0: 4293 cmp r3, r2 80100f2: d048 beq.n 8010186 80100f4: 687b ldr r3, [r7, #4] 80100f6: 681b ldr r3, [r3, #0] 80100f8: 4a5f ldr r2, [pc, #380] @ (8010278 ) 80100fa: 4293 cmp r3, r2 80100fc: d040 beq.n 8010180 80100fe: 687b ldr r3, [r7, #4] 8010100: 681b ldr r3, [r3, #0] 8010102: 4a5e ldr r2, [pc, #376] @ (801027c ) 8010104: 4293 cmp r3, r2 8010106: d038 beq.n 801017a 8010108: 687b ldr r3, [r7, #4] 801010a: 681b ldr r3, [r3, #0] 801010c: 4a5c ldr r2, [pc, #368] @ (8010280 ) 801010e: 4293 cmp r3, r2 8010110: d030 beq.n 8010174 8010112: 687b ldr r3, [r7, #4] 8010114: 681b ldr r3, [r3, #0] 8010116: 4a5b ldr r2, [pc, #364] @ (8010284 ) 8010118: 4293 cmp r3, r2 801011a: d028 beq.n 801016e 801011c: 687b ldr r3, [r7, #4] 801011e: 681b ldr r3, [r3, #0] 8010120: 4a52 ldr r2, [pc, #328] @ (801026c ) 8010122: 4293 cmp r3, r2 8010124: d020 beq.n 8010168 8010126: 687b ldr r3, [r7, #4] 8010128: 681b ldr r3, [r3, #0] 801012a: 4a57 ldr r2, [pc, #348] @ (8010288 ) 801012c: 4293 cmp r3, r2 801012e: d019 beq.n 8010164 8010130: 687b ldr r3, [r7, #4] 8010132: 681b ldr r3, [r3, #0] 8010134: 4a55 ldr r2, [pc, #340] @ (801028c ) 8010136: 4293 cmp r3, r2 8010138: d012 beq.n 8010160 801013a: 687b ldr r3, [r7, #4] 801013c: 681b ldr r3, [r3, #0] 801013e: 4a54 ldr r2, [pc, #336] @ (8010290 ) 8010140: 4293 cmp r3, r2 8010142: d00a beq.n 801015a 8010144: 687b ldr r3, [r7, #4] 8010146: 681b ldr r3, [r3, #0] 8010148: 4a52 ldr r2, [pc, #328] @ (8010294 ) 801014a: 4293 cmp r3, r2 801014c: d102 bne.n 8010154 801014e: f44f 5380 mov.w r3, #4096 @ 0x1000 8010152: e01b b.n 801018c 8010154: f44f 3380 mov.w r3, #65536 @ 0x10000 8010158: e018 b.n 801018c 801015a: f44f 7380 mov.w r3, #256 @ 0x100 801015e: e015 b.n 801018c 8010160: 2310 movs r3, #16 8010162: e013 b.n 801018c 8010164: 2301 movs r3, #1 8010166: e011 b.n 801018c 8010168: f04f 7380 mov.w r3, #16777216 @ 0x1000000 801016c: e00e b.n 801018c 801016e: f44f 1380 mov.w r3, #1048576 @ 0x100000 8010172: e00b b.n 801018c 8010174: f44f 3380 mov.w r3, #65536 @ 0x10000 8010178: e008 b.n 801018c 801017a: f44f 5380 mov.w r3, #4096 @ 0x1000 801017e: e005 b.n 801018c 8010180: f44f 7380 mov.w r3, #256 @ 0x100 8010184: e002 b.n 801018c 8010186: 2310 movs r3, #16 8010188: e000 b.n 801018c 801018a: 2301 movs r3, #1 801018c: 4a42 ldr r2, [pc, #264] @ (8010298 ) 801018e: 6053 str r3, [r2, #4] 8010190: e057 b.n 8010242 8010192: 687b ldr r3, [r7, #4] 8010194: 681b ldr r3, [r3, #0] 8010196: 4a36 ldr r2, [pc, #216] @ (8010270 ) 8010198: 4293 cmp r3, r2 801019a: d04f beq.n 801023c 801019c: 687b ldr r3, [r7, #4] 801019e: 681b ldr r3, [r3, #0] 80101a0: 4a34 ldr r2, [pc, #208] @ (8010274 ) 80101a2: 4293 cmp r3, r2 80101a4: d048 beq.n 8010238 80101a6: 687b ldr r3, [r7, #4] 80101a8: 681b ldr r3, [r3, #0] 80101aa: 4a33 ldr r2, [pc, #204] @ (8010278 ) 80101ac: 4293 cmp r3, r2 80101ae: d040 beq.n 8010232 80101b0: 687b ldr r3, [r7, #4] 80101b2: 681b ldr r3, [r3, #0] 80101b4: 4a31 ldr r2, [pc, #196] @ (801027c ) 80101b6: 4293 cmp r3, r2 80101b8: d038 beq.n 801022c 80101ba: 687b ldr r3, [r7, #4] 80101bc: 681b ldr r3, [r3, #0] 80101be: 4a30 ldr r2, [pc, #192] @ (8010280 ) 80101c0: 4293 cmp r3, r2 80101c2: d030 beq.n 8010226 80101c4: 687b ldr r3, [r7, #4] 80101c6: 681b ldr r3, [r3, #0] 80101c8: 4a2e ldr r2, [pc, #184] @ (8010284 ) 80101ca: 4293 cmp r3, r2 80101cc: d028 beq.n 8010220 80101ce: 687b ldr r3, [r7, #4] 80101d0: 681b ldr r3, [r3, #0] 80101d2: 4a26 ldr r2, [pc, #152] @ (801026c ) 80101d4: 4293 cmp r3, r2 80101d6: d020 beq.n 801021a 80101d8: 687b ldr r3, [r7, #4] 80101da: 681b ldr r3, [r3, #0] 80101dc: 4a2a ldr r2, [pc, #168] @ (8010288 ) 80101de: 4293 cmp r3, r2 80101e0: d019 beq.n 8010216 80101e2: 687b ldr r3, [r7, #4] 80101e4: 681b ldr r3, [r3, #0] 80101e6: 4a29 ldr r2, [pc, #164] @ (801028c ) 80101e8: 4293 cmp r3, r2 80101ea: d012 beq.n 8010212 80101ec: 687b ldr r3, [r7, #4] 80101ee: 681b ldr r3, [r3, #0] 80101f0: 4a27 ldr r2, [pc, #156] @ (8010290 ) 80101f2: 4293 cmp r3, r2 80101f4: d00a beq.n 801020c 80101f6: 687b ldr r3, [r7, #4] 80101f8: 681b ldr r3, [r3, #0] 80101fa: 4a26 ldr r2, [pc, #152] @ (8010294 ) 80101fc: 4293 cmp r3, r2 80101fe: d102 bne.n 8010206 8010200: f44f 5380 mov.w r3, #4096 @ 0x1000 8010204: e01b b.n 801023e 8010206: f44f 3380 mov.w r3, #65536 @ 0x10000 801020a: e018 b.n 801023e 801020c: f44f 7380 mov.w r3, #256 @ 0x100 8010210: e015 b.n 801023e 8010212: 2310 movs r3, #16 8010214: e013 b.n 801023e 8010216: 2301 movs r3, #1 8010218: e011 b.n 801023e 801021a: f04f 7380 mov.w r3, #16777216 @ 0x1000000 801021e: e00e b.n 801023e 8010220: f44f 1380 mov.w r3, #1048576 @ 0x100000 8010224: e00b b.n 801023e 8010226: f44f 3380 mov.w r3, #65536 @ 0x10000 801022a: e008 b.n 801023e 801022c: f44f 5380 mov.w r3, #4096 @ 0x1000 8010230: e005 b.n 801023e 8010232: f44f 7380 mov.w r3, #256 @ 0x100 8010236: e002 b.n 801023e 8010238: 2310 movs r3, #16 801023a: e000 b.n 801023e 801023c: 2301 movs r3, #1 801023e: 4a17 ldr r2, [pc, #92] @ (801029c ) 8010240: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8010242: 687b ldr r3, [r7, #4] 8010244: 2201 movs r2, #1 8010246: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 801024a: 687b ldr r3, [r7, #4] 801024c: 2200 movs r2, #0 801024e: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8010252: 687b ldr r3, [r7, #4] 8010254: 6b5b ldr r3, [r3, #52] @ 0x34 8010256: 2b00 cmp r3, #0 8010258: d003 beq.n 8010262 { hdma->XferAbortCallback(hdma); 801025a: 687b ldr r3, [r7, #4] 801025c: 6b5b ldr r3, [r3, #52] @ 0x34 801025e: 6878 ldr r0, [r7, #4] 8010260: 4798 blx r3 } } return status; 8010262: 7bfb ldrb r3, [r7, #15] } 8010264: 4618 mov r0, r3 8010266: 3710 adds r7, #16 8010268: 46bd mov sp, r7 801026a: bd80 pop {r7, pc} 801026c: 40020080 .word 0x40020080 8010270: 40020008 .word 0x40020008 8010274: 4002001c .word 0x4002001c 8010278: 40020030 .word 0x40020030 801027c: 40020044 .word 0x40020044 8010280: 40020058 .word 0x40020058 8010284: 4002006c .word 0x4002006c 8010288: 40020408 .word 0x40020408 801028c: 4002041c .word 0x4002041c 8010290: 40020430 .word 0x40020430 8010294: 40020444 .word 0x40020444 8010298: 40020400 .word 0x40020400 801029c: 40020000 .word 0x40020000 080102a0 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 80102a0: b580 push {r7, lr} 80102a2: b084 sub sp, #16 80102a4: af00 add r7, sp, #0 80102a6: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; 80102a8: 687b ldr r3, [r7, #4] 80102aa: 6bdb ldr r3, [r3, #60] @ 0x3c 80102ac: 681b ldr r3, [r3, #0] 80102ae: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; 80102b0: 687b ldr r3, [r7, #4] 80102b2: 681b ldr r3, [r3, #0] 80102b4: 681b ldr r3, [r3, #0] 80102b6: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 80102b8: 687b ldr r3, [r7, #4] 80102ba: 6c1b ldr r3, [r3, #64] @ 0x40 80102bc: 2204 movs r2, #4 80102be: 409a lsls r2, r3 80102c0: 68fb ldr r3, [r7, #12] 80102c2: 4013 ands r3, r2 80102c4: 2b00 cmp r3, #0 80102c6: f000 80f1 beq.w 80104ac 80102ca: 68bb ldr r3, [r7, #8] 80102cc: f003 0304 and.w r3, r3, #4 80102d0: 2b00 cmp r3, #0 80102d2: f000 80eb beq.w 80104ac { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 80102d6: 687b ldr r3, [r7, #4] 80102d8: 681b ldr r3, [r3, #0] 80102da: 681b ldr r3, [r3, #0] 80102dc: f003 0320 and.w r3, r3, #32 80102e0: 2b00 cmp r3, #0 80102e2: d107 bne.n 80102f4 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 80102e4: 687b ldr r3, [r7, #4] 80102e6: 681b ldr r3, [r3, #0] 80102e8: 681a ldr r2, [r3, #0] 80102ea: 687b ldr r3, [r7, #4] 80102ec: 681b ldr r3, [r3, #0] 80102ee: f022 0204 bic.w r2, r2, #4 80102f2: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); 80102f4: 687b ldr r3, [r7, #4] 80102f6: 681b ldr r3, [r3, #0] 80102f8: 461a mov r2, r3 80102fa: 4b5f ldr r3, [pc, #380] @ (8010478 ) 80102fc: 429a cmp r2, r3 80102fe: d958 bls.n 80103b2 8010300: 687b ldr r3, [r7, #4] 8010302: 681b ldr r3, [r3, #0] 8010304: 4a5d ldr r2, [pc, #372] @ (801047c ) 8010306: 4293 cmp r3, r2 8010308: d04f beq.n 80103aa 801030a: 687b ldr r3, [r7, #4] 801030c: 681b ldr r3, [r3, #0] 801030e: 4a5c ldr r2, [pc, #368] @ (8010480 ) 8010310: 4293 cmp r3, r2 8010312: d048 beq.n 80103a6 8010314: 687b ldr r3, [r7, #4] 8010316: 681b ldr r3, [r3, #0] 8010318: 4a5a ldr r2, [pc, #360] @ (8010484 ) 801031a: 4293 cmp r3, r2 801031c: d040 beq.n 80103a0 801031e: 687b ldr r3, [r7, #4] 8010320: 681b ldr r3, [r3, #0] 8010322: 4a59 ldr r2, [pc, #356] @ (8010488 ) 8010324: 4293 cmp r3, r2 8010326: d038 beq.n 801039a 8010328: 687b ldr r3, [r7, #4] 801032a: 681b ldr r3, [r3, #0] 801032c: 4a57 ldr r2, [pc, #348] @ (801048c ) 801032e: 4293 cmp r3, r2 8010330: d030 beq.n 8010394 8010332: 687b ldr r3, [r7, #4] 8010334: 681b ldr r3, [r3, #0] 8010336: 4a56 ldr r2, [pc, #344] @ (8010490 ) 8010338: 4293 cmp r3, r2 801033a: d028 beq.n 801038e 801033c: 687b ldr r3, [r7, #4] 801033e: 681b ldr r3, [r3, #0] 8010340: 4a4d ldr r2, [pc, #308] @ (8010478 ) 8010342: 4293 cmp r3, r2 8010344: d020 beq.n 8010388 8010346: 687b ldr r3, [r7, #4] 8010348: 681b ldr r3, [r3, #0] 801034a: 4a52 ldr r2, [pc, #328] @ (8010494 ) 801034c: 4293 cmp r3, r2 801034e: d019 beq.n 8010384 8010350: 687b ldr r3, [r7, #4] 8010352: 681b ldr r3, [r3, #0] 8010354: 4a50 ldr r2, [pc, #320] @ (8010498 ) 8010356: 4293 cmp r3, r2 8010358: d012 beq.n 8010380 801035a: 687b ldr r3, [r7, #4] 801035c: 681b ldr r3, [r3, #0] 801035e: 4a4f ldr r2, [pc, #316] @ (801049c ) 8010360: 4293 cmp r3, r2 8010362: d00a beq.n 801037a 8010364: 687b ldr r3, [r7, #4] 8010366: 681b ldr r3, [r3, #0] 8010368: 4a4d ldr r2, [pc, #308] @ (80104a0 ) 801036a: 4293 cmp r3, r2 801036c: d102 bne.n 8010374 801036e: f44f 4380 mov.w r3, #16384 @ 0x4000 8010372: e01b b.n 80103ac 8010374: f44f 2380 mov.w r3, #262144 @ 0x40000 8010378: e018 b.n 80103ac 801037a: f44f 6380 mov.w r3, #1024 @ 0x400 801037e: e015 b.n 80103ac 8010380: 2340 movs r3, #64 @ 0x40 8010382: e013 b.n 80103ac 8010384: 2304 movs r3, #4 8010386: e011 b.n 80103ac 8010388: f04f 6380 mov.w r3, #67108864 @ 0x4000000 801038c: e00e b.n 80103ac 801038e: f44f 0380 mov.w r3, #4194304 @ 0x400000 8010392: e00b b.n 80103ac 8010394: f44f 2380 mov.w r3, #262144 @ 0x40000 8010398: e008 b.n 80103ac 801039a: f44f 4380 mov.w r3, #16384 @ 0x4000 801039e: e005 b.n 80103ac 80103a0: f44f 6380 mov.w r3, #1024 @ 0x400 80103a4: e002 b.n 80103ac 80103a6: 2340 movs r3, #64 @ 0x40 80103a8: e000 b.n 80103ac 80103aa: 2304 movs r3, #4 80103ac: 4a3d ldr r2, [pc, #244] @ (80104a4 ) 80103ae: 6053 str r3, [r2, #4] 80103b0: e057 b.n 8010462 80103b2: 687b ldr r3, [r7, #4] 80103b4: 681b ldr r3, [r3, #0] 80103b6: 4a31 ldr r2, [pc, #196] @ (801047c ) 80103b8: 4293 cmp r3, r2 80103ba: d04f beq.n 801045c 80103bc: 687b ldr r3, [r7, #4] 80103be: 681b ldr r3, [r3, #0] 80103c0: 4a2f ldr r2, [pc, #188] @ (8010480 ) 80103c2: 4293 cmp r3, r2 80103c4: d048 beq.n 8010458 80103c6: 687b ldr r3, [r7, #4] 80103c8: 681b ldr r3, [r3, #0] 80103ca: 4a2e ldr r2, [pc, #184] @ (8010484 ) 80103cc: 4293 cmp r3, r2 80103ce: d040 beq.n 8010452 80103d0: 687b ldr r3, [r7, #4] 80103d2: 681b ldr r3, [r3, #0] 80103d4: 4a2c ldr r2, [pc, #176] @ (8010488 ) 80103d6: 4293 cmp r3, r2 80103d8: d038 beq.n 801044c 80103da: 687b ldr r3, [r7, #4] 80103dc: 681b ldr r3, [r3, #0] 80103de: 4a2b ldr r2, [pc, #172] @ (801048c ) 80103e0: 4293 cmp r3, r2 80103e2: d030 beq.n 8010446 80103e4: 687b ldr r3, [r7, #4] 80103e6: 681b ldr r3, [r3, #0] 80103e8: 4a29 ldr r2, [pc, #164] @ (8010490 ) 80103ea: 4293 cmp r3, r2 80103ec: d028 beq.n 8010440 80103ee: 687b ldr r3, [r7, #4] 80103f0: 681b ldr r3, [r3, #0] 80103f2: 4a21 ldr r2, [pc, #132] @ (8010478 ) 80103f4: 4293 cmp r3, r2 80103f6: d020 beq.n 801043a 80103f8: 687b ldr r3, [r7, #4] 80103fa: 681b ldr r3, [r3, #0] 80103fc: 4a25 ldr r2, [pc, #148] @ (8010494 ) 80103fe: 4293 cmp r3, r2 8010400: d019 beq.n 8010436 8010402: 687b ldr r3, [r7, #4] 8010404: 681b ldr r3, [r3, #0] 8010406: 4a24 ldr r2, [pc, #144] @ (8010498 ) 8010408: 4293 cmp r3, r2 801040a: d012 beq.n 8010432 801040c: 687b ldr r3, [r7, #4] 801040e: 681b ldr r3, [r3, #0] 8010410: 4a22 ldr r2, [pc, #136] @ (801049c ) 8010412: 4293 cmp r3, r2 8010414: d00a beq.n 801042c 8010416: 687b ldr r3, [r7, #4] 8010418: 681b ldr r3, [r3, #0] 801041a: 4a21 ldr r2, [pc, #132] @ (80104a0 ) 801041c: 4293 cmp r3, r2 801041e: d102 bne.n 8010426 8010420: f44f 4380 mov.w r3, #16384 @ 0x4000 8010424: e01b b.n 801045e 8010426: f44f 2380 mov.w r3, #262144 @ 0x40000 801042a: e018 b.n 801045e 801042c: f44f 6380 mov.w r3, #1024 @ 0x400 8010430: e015 b.n 801045e 8010432: 2340 movs r3, #64 @ 0x40 8010434: e013 b.n 801045e 8010436: 2304 movs r3, #4 8010438: e011 b.n 801045e 801043a: f04f 6380 mov.w r3, #67108864 @ 0x4000000 801043e: e00e b.n 801045e 8010440: f44f 0380 mov.w r3, #4194304 @ 0x400000 8010444: e00b b.n 801045e 8010446: f44f 2380 mov.w r3, #262144 @ 0x40000 801044a: e008 b.n 801045e 801044c: f44f 4380 mov.w r3, #16384 @ 0x4000 8010450: e005 b.n 801045e 8010452: f44f 6380 mov.w r3, #1024 @ 0x400 8010456: e002 b.n 801045e 8010458: 2340 movs r3, #64 @ 0x40 801045a: e000 b.n 801045e 801045c: 2304 movs r3, #4 801045e: 4a12 ldr r2, [pc, #72] @ (80104a8 ) 8010460: 6053 str r3, [r2, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 8010462: 687b ldr r3, [r7, #4] 8010464: 6adb ldr r3, [r3, #44] @ 0x2c 8010466: 2b00 cmp r3, #0 8010468: f000 8136 beq.w 80106d8 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 801046c: 687b ldr r3, [r7, #4] 801046e: 6adb ldr r3, [r3, #44] @ 0x2c 8010470: 6878 ldr r0, [r7, #4] 8010472: 4798 blx r3 if(hdma->XferHalfCpltCallback != NULL) 8010474: e130 b.n 80106d8 8010476: bf00 nop 8010478: 40020080 .word 0x40020080 801047c: 40020008 .word 0x40020008 8010480: 4002001c .word 0x4002001c 8010484: 40020030 .word 0x40020030 8010488: 40020044 .word 0x40020044 801048c: 40020058 .word 0x40020058 8010490: 4002006c .word 0x4002006c 8010494: 40020408 .word 0x40020408 8010498: 4002041c .word 0x4002041c 801049c: 40020430 .word 0x40020430 80104a0: 40020444 .word 0x40020444 80104a4: 40020400 .word 0x40020400 80104a8: 40020000 .word 0x40020000 } } /* Transfer Complete Interrupt management ***********************************/ else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) 80104ac: 687b ldr r3, [r7, #4] 80104ae: 6c1b ldr r3, [r3, #64] @ 0x40 80104b0: 2202 movs r2, #2 80104b2: 409a lsls r2, r3 80104b4: 68fb ldr r3, [r7, #12] 80104b6: 4013 ands r3, r2 80104b8: 2b00 cmp r3, #0 80104ba: f000 80dd beq.w 8010678 80104be: 68bb ldr r3, [r7, #8] 80104c0: f003 0302 and.w r3, r3, #2 80104c4: 2b00 cmp r3, #0 80104c6: f000 80d7 beq.w 8010678 { if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 80104ca: 687b ldr r3, [r7, #4] 80104cc: 681b ldr r3, [r3, #0] 80104ce: 681b ldr r3, [r3, #0] 80104d0: f003 0320 and.w r3, r3, #32 80104d4: 2b00 cmp r3, #0 80104d6: d10b bne.n 80104f0 { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 80104d8: 687b ldr r3, [r7, #4] 80104da: 681b ldr r3, [r3, #0] 80104dc: 681a ldr r2, [r3, #0] 80104de: 687b ldr r3, [r7, #4] 80104e0: 681b ldr r3, [r3, #0] 80104e2: f022 020a bic.w r2, r2, #10 80104e6: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80104e8: 687b ldr r3, [r7, #4] 80104ea: 2201 movs r2, #1 80104ec: f883 2021 strb.w r2, [r3, #33] @ 0x21 } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); 80104f0: 687b ldr r3, [r7, #4] 80104f2: 681b ldr r3, [r3, #0] 80104f4: 461a mov r2, r3 80104f6: 4b7b ldr r3, [pc, #492] @ (80106e4 ) 80104f8: 429a cmp r2, r3 80104fa: d958 bls.n 80105ae 80104fc: 687b ldr r3, [r7, #4] 80104fe: 681b ldr r3, [r3, #0] 8010500: 4a79 ldr r2, [pc, #484] @ (80106e8 ) 8010502: 4293 cmp r3, r2 8010504: d04f beq.n 80105a6 8010506: 687b ldr r3, [r7, #4] 8010508: 681b ldr r3, [r3, #0] 801050a: 4a78 ldr r2, [pc, #480] @ (80106ec ) 801050c: 4293 cmp r3, r2 801050e: d048 beq.n 80105a2 8010510: 687b ldr r3, [r7, #4] 8010512: 681b ldr r3, [r3, #0] 8010514: 4a76 ldr r2, [pc, #472] @ (80106f0 ) 8010516: 4293 cmp r3, r2 8010518: d040 beq.n 801059c 801051a: 687b ldr r3, [r7, #4] 801051c: 681b ldr r3, [r3, #0] 801051e: 4a75 ldr r2, [pc, #468] @ (80106f4 ) 8010520: 4293 cmp r3, r2 8010522: d038 beq.n 8010596 8010524: 687b ldr r3, [r7, #4] 8010526: 681b ldr r3, [r3, #0] 8010528: 4a73 ldr r2, [pc, #460] @ (80106f8 ) 801052a: 4293 cmp r3, r2 801052c: d030 beq.n 8010590 801052e: 687b ldr r3, [r7, #4] 8010530: 681b ldr r3, [r3, #0] 8010532: 4a72 ldr r2, [pc, #456] @ (80106fc ) 8010534: 4293 cmp r3, r2 8010536: d028 beq.n 801058a 8010538: 687b ldr r3, [r7, #4] 801053a: 681b ldr r3, [r3, #0] 801053c: 4a69 ldr r2, [pc, #420] @ (80106e4 ) 801053e: 4293 cmp r3, r2 8010540: d020 beq.n 8010584 8010542: 687b ldr r3, [r7, #4] 8010544: 681b ldr r3, [r3, #0] 8010546: 4a6e ldr r2, [pc, #440] @ (8010700 ) 8010548: 4293 cmp r3, r2 801054a: d019 beq.n 8010580 801054c: 687b ldr r3, [r7, #4] 801054e: 681b ldr r3, [r3, #0] 8010550: 4a6c ldr r2, [pc, #432] @ (8010704 ) 8010552: 4293 cmp r3, r2 8010554: d012 beq.n 801057c 8010556: 687b ldr r3, [r7, #4] 8010558: 681b ldr r3, [r3, #0] 801055a: 4a6b ldr r2, [pc, #428] @ (8010708 ) 801055c: 4293 cmp r3, r2 801055e: d00a beq.n 8010576 8010560: 687b ldr r3, [r7, #4] 8010562: 681b ldr r3, [r3, #0] 8010564: 4a69 ldr r2, [pc, #420] @ (801070c ) 8010566: 4293 cmp r3, r2 8010568: d102 bne.n 8010570 801056a: f44f 5300 mov.w r3, #8192 @ 0x2000 801056e: e01b b.n 80105a8 8010570: f44f 3300 mov.w r3, #131072 @ 0x20000 8010574: e018 b.n 80105a8 8010576: f44f 7300 mov.w r3, #512 @ 0x200 801057a: e015 b.n 80105a8 801057c: 2320 movs r3, #32 801057e: e013 b.n 80105a8 8010580: 2302 movs r3, #2 8010582: e011 b.n 80105a8 8010584: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8010588: e00e b.n 80105a8 801058a: f44f 1300 mov.w r3, #2097152 @ 0x200000 801058e: e00b b.n 80105a8 8010590: f44f 3300 mov.w r3, #131072 @ 0x20000 8010594: e008 b.n 80105a8 8010596: f44f 5300 mov.w r3, #8192 @ 0x2000 801059a: e005 b.n 80105a8 801059c: f44f 7300 mov.w r3, #512 @ 0x200 80105a0: e002 b.n 80105a8 80105a2: 2320 movs r3, #32 80105a4: e000 b.n 80105a8 80105a6: 2302 movs r3, #2 80105a8: 4a59 ldr r2, [pc, #356] @ (8010710 ) 80105aa: 6053 str r3, [r2, #4] 80105ac: e057 b.n 801065e 80105ae: 687b ldr r3, [r7, #4] 80105b0: 681b ldr r3, [r3, #0] 80105b2: 4a4d ldr r2, [pc, #308] @ (80106e8 ) 80105b4: 4293 cmp r3, r2 80105b6: d04f beq.n 8010658 80105b8: 687b ldr r3, [r7, #4] 80105ba: 681b ldr r3, [r3, #0] 80105bc: 4a4b ldr r2, [pc, #300] @ (80106ec ) 80105be: 4293 cmp r3, r2 80105c0: d048 beq.n 8010654 80105c2: 687b ldr r3, [r7, #4] 80105c4: 681b ldr r3, [r3, #0] 80105c6: 4a4a ldr r2, [pc, #296] @ (80106f0 ) 80105c8: 4293 cmp r3, r2 80105ca: d040 beq.n 801064e 80105cc: 687b ldr r3, [r7, #4] 80105ce: 681b ldr r3, [r3, #0] 80105d0: 4a48 ldr r2, [pc, #288] @ (80106f4 ) 80105d2: 4293 cmp r3, r2 80105d4: d038 beq.n 8010648 80105d6: 687b ldr r3, [r7, #4] 80105d8: 681b ldr r3, [r3, #0] 80105da: 4a47 ldr r2, [pc, #284] @ (80106f8 ) 80105dc: 4293 cmp r3, r2 80105de: d030 beq.n 8010642 80105e0: 687b ldr r3, [r7, #4] 80105e2: 681b ldr r3, [r3, #0] 80105e4: 4a45 ldr r2, [pc, #276] @ (80106fc ) 80105e6: 4293 cmp r3, r2 80105e8: d028 beq.n 801063c 80105ea: 687b ldr r3, [r7, #4] 80105ec: 681b ldr r3, [r3, #0] 80105ee: 4a3d ldr r2, [pc, #244] @ (80106e4 ) 80105f0: 4293 cmp r3, r2 80105f2: d020 beq.n 8010636 80105f4: 687b ldr r3, [r7, #4] 80105f6: 681b ldr r3, [r3, #0] 80105f8: 4a41 ldr r2, [pc, #260] @ (8010700 ) 80105fa: 4293 cmp r3, r2 80105fc: d019 beq.n 8010632 80105fe: 687b ldr r3, [r7, #4] 8010600: 681b ldr r3, [r3, #0] 8010602: 4a40 ldr r2, [pc, #256] @ (8010704 ) 8010604: 4293 cmp r3, r2 8010606: d012 beq.n 801062e 8010608: 687b ldr r3, [r7, #4] 801060a: 681b ldr r3, [r3, #0] 801060c: 4a3e ldr r2, [pc, #248] @ (8010708 ) 801060e: 4293 cmp r3, r2 8010610: d00a beq.n 8010628 8010612: 687b ldr r3, [r7, #4] 8010614: 681b ldr r3, [r3, #0] 8010616: 4a3d ldr r2, [pc, #244] @ (801070c ) 8010618: 4293 cmp r3, r2 801061a: d102 bne.n 8010622 801061c: f44f 5300 mov.w r3, #8192 @ 0x2000 8010620: e01b b.n 801065a 8010622: f44f 3300 mov.w r3, #131072 @ 0x20000 8010626: e018 b.n 801065a 8010628: f44f 7300 mov.w r3, #512 @ 0x200 801062c: e015 b.n 801065a 801062e: 2320 movs r3, #32 8010630: e013 b.n 801065a 8010632: 2302 movs r3, #2 8010634: e011 b.n 801065a 8010636: f04f 7300 mov.w r3, #33554432 @ 0x2000000 801063a: e00e b.n 801065a 801063c: f44f 1300 mov.w r3, #2097152 @ 0x200000 8010640: e00b b.n 801065a 8010642: f44f 3300 mov.w r3, #131072 @ 0x20000 8010646: e008 b.n 801065a 8010648: f44f 5300 mov.w r3, #8192 @ 0x2000 801064c: e005 b.n 801065a 801064e: f44f 7300 mov.w r3, #512 @ 0x200 8010652: e002 b.n 801065a 8010654: 2320 movs r3, #32 8010656: e000 b.n 801065a 8010658: 2302 movs r3, #2 801065a: 4a2e ldr r2, [pc, #184] @ (8010714 ) 801065c: 6053 str r3, [r2, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); 801065e: 687b ldr r3, [r7, #4] 8010660: 2200 movs r2, #0 8010662: f883 2020 strb.w r2, [r3, #32] if(hdma->XferCpltCallback != NULL) 8010666: 687b ldr r3, [r7, #4] 8010668: 6a9b ldr r3, [r3, #40] @ 0x28 801066a: 2b00 cmp r3, #0 801066c: d034 beq.n 80106d8 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 801066e: 687b ldr r3, [r7, #4] 8010670: 6a9b ldr r3, [r3, #40] @ 0x28 8010672: 6878 ldr r0, [r7, #4] 8010674: 4798 blx r3 if(hdma->XferCpltCallback != NULL) 8010676: e02f b.n 80106d8 } } /* Transfer Error Interrupt management **************************************/ else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) 8010678: 687b ldr r3, [r7, #4] 801067a: 6c1b ldr r3, [r3, #64] @ 0x40 801067c: 2208 movs r2, #8 801067e: 409a lsls r2, r3 8010680: 68fb ldr r3, [r7, #12] 8010682: 4013 ands r3, r2 8010684: 2b00 cmp r3, #0 8010686: d028 beq.n 80106da 8010688: 68bb ldr r3, [r7, #8] 801068a: f003 0308 and.w r3, r3, #8 801068e: 2b00 cmp r3, #0 8010690: d023 beq.n 80106da { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8010692: 687b ldr r3, [r7, #4] 8010694: 681b ldr r3, [r3, #0] 8010696: 681a ldr r2, [r3, #0] 8010698: 687b ldr r3, [r7, #4] 801069a: 681b ldr r3, [r3, #0] 801069c: f022 020e bic.w r2, r2, #14 80106a0: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 80106a2: 687b ldr r3, [r7, #4] 80106a4: 6c1a ldr r2, [r3, #64] @ 0x40 80106a6: 687b ldr r3, [r7, #4] 80106a8: 6bdb ldr r3, [r3, #60] @ 0x3c 80106aa: 2101 movs r1, #1 80106ac: fa01 f202 lsl.w r2, r1, r2 80106b0: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 80106b2: 687b ldr r3, [r7, #4] 80106b4: 2201 movs r2, #1 80106b6: 639a str r2, [r3, #56] @ 0x38 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80106b8: 687b ldr r3, [r7, #4] 80106ba: 2201 movs r2, #1 80106bc: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80106c0: 687b ldr r3, [r7, #4] 80106c2: 2200 movs r2, #0 80106c4: f883 2020 strb.w r2, [r3, #32] if (hdma->XferErrorCallback != NULL) 80106c8: 687b ldr r3, [r7, #4] 80106ca: 6b1b ldr r3, [r3, #48] @ 0x30 80106cc: 2b00 cmp r3, #0 80106ce: d004 beq.n 80106da { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 80106d0: 687b ldr r3, [r7, #4] 80106d2: 6b1b ldr r3, [r3, #48] @ 0x30 80106d4: 6878 ldr r0, [r7, #4] 80106d6: 4798 blx r3 } } return; 80106d8: bf00 nop 80106da: bf00 nop } 80106dc: 3710 adds r7, #16 80106de: 46bd mov sp, r7 80106e0: bd80 pop {r7, pc} 80106e2: bf00 nop 80106e4: 40020080 .word 0x40020080 80106e8: 40020008 .word 0x40020008 80106ec: 4002001c .word 0x4002001c 80106f0: 40020030 .word 0x40020030 80106f4: 40020044 .word 0x40020044 80106f8: 40020058 .word 0x40020058 80106fc: 4002006c .word 0x4002006c 8010700: 40020408 .word 0x40020408 8010704: 4002041c .word 0x4002041c 8010708: 40020430 .word 0x40020430 801070c: 40020444 .word 0x40020444 8010710: 40020400 .word 0x40020400 8010714: 40020000 .word 0x40020000 08010718 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval DMA Error Code */ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) { 8010718: b480 push {r7} 801071a: b083 sub sp, #12 801071c: af00 add r7, sp, #0 801071e: 6078 str r0, [r7, #4] return hdma->ErrorCode; 8010720: 687b ldr r3, [r7, #4] 8010722: 6b9b ldr r3, [r3, #56] @ 0x38 } 8010724: 4618 mov r0, r3 8010726: 370c adds r7, #12 8010728: 46bd mov sp, r7 801072a: bc80 pop {r7} 801072c: 4770 bx lr 0801072e : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 801072e: b480 push {r7} 8010730: b085 sub sp, #20 8010732: af00 add r7, sp, #0 8010734: 60f8 str r0, [r7, #12] 8010736: 60b9 str r1, [r7, #8] 8010738: 607a str r2, [r7, #4] 801073a: 603b str r3, [r7, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 801073c: 68fb ldr r3, [r7, #12] 801073e: 6c1a ldr r2, [r3, #64] @ 0x40 8010740: 68fb ldr r3, [r7, #12] 8010742: 6bdb ldr r3, [r3, #60] @ 0x3c 8010744: 2101 movs r1, #1 8010746: fa01 f202 lsl.w r2, r1, r2 801074a: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 801074c: 68fb ldr r3, [r7, #12] 801074e: 681b ldr r3, [r3, #0] 8010750: 683a ldr r2, [r7, #0] 8010752: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8010754: 68fb ldr r3, [r7, #12] 8010756: 685b ldr r3, [r3, #4] 8010758: 2b10 cmp r3, #16 801075a: d108 bne.n 801076e { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 801075c: 68fb ldr r3, [r7, #12] 801075e: 681b ldr r3, [r3, #0] 8010760: 687a ldr r2, [r7, #4] 8010762: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; 8010764: 68fb ldr r3, [r7, #12] 8010766: 681b ldr r3, [r3, #0] 8010768: 68ba ldr r2, [r7, #8] 801076a: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } 801076c: e007 b.n 801077e hdma->Instance->CPAR = SrcAddress; 801076e: 68fb ldr r3, [r7, #12] 8010770: 681b ldr r3, [r3, #0] 8010772: 68ba ldr r2, [r7, #8] 8010774: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; 8010776: 68fb ldr r3, [r7, #12] 8010778: 681b ldr r3, [r3, #0] 801077a: 687a ldr r2, [r7, #4] 801077c: 60da str r2, [r3, #12] } 801077e: bf00 nop 8010780: 3714 adds r7, #20 8010782: 46bd mov sp, r7 8010784: bc80 pop {r7} 8010786: 4770 bx lr 08010788 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8010788: b480 push {r7} 801078a: b08b sub sp, #44 @ 0x2c 801078c: af00 add r7, sp, #0 801078e: 6078 str r0, [r7, #4] 8010790: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8010792: 2300 movs r3, #0 8010794: 627b str r3, [r7, #36] @ 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 8010796: 2300 movs r3, #0 8010798: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 801079a: e169 b.n 8010a70 { /* Get the IO position */ ioposition = (0x01uL << position); 801079c: 2201 movs r2, #1 801079e: 6a7b ldr r3, [r7, #36] @ 0x24 80107a0: fa02 f303 lsl.w r3, r2, r3 80107a4: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80107a6: 683b ldr r3, [r7, #0] 80107a8: 681b ldr r3, [r3, #0] 80107aa: 69fa ldr r2, [r7, #28] 80107ac: 4013 ands r3, r2 80107ae: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 80107b0: 69ba ldr r2, [r7, #24] 80107b2: 69fb ldr r3, [r7, #28] 80107b4: 429a cmp r2, r3 80107b6: f040 8158 bne.w 8010a6a { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 80107ba: 683b ldr r3, [r7, #0] 80107bc: 685b ldr r3, [r3, #4] 80107be: 4a9a ldr r2, [pc, #616] @ (8010a28 ) 80107c0: 4293 cmp r3, r2 80107c2: d05e beq.n 8010882 80107c4: 4a98 ldr r2, [pc, #608] @ (8010a28 ) 80107c6: 4293 cmp r3, r2 80107c8: d875 bhi.n 80108b6 80107ca: 4a98 ldr r2, [pc, #608] @ (8010a2c ) 80107cc: 4293 cmp r3, r2 80107ce: d058 beq.n 8010882 80107d0: 4a96 ldr r2, [pc, #600] @ (8010a2c ) 80107d2: 4293 cmp r3, r2 80107d4: d86f bhi.n 80108b6 80107d6: 4a96 ldr r2, [pc, #600] @ (8010a30 ) 80107d8: 4293 cmp r3, r2 80107da: d052 beq.n 8010882 80107dc: 4a94 ldr r2, [pc, #592] @ (8010a30 ) 80107de: 4293 cmp r3, r2 80107e0: d869 bhi.n 80108b6 80107e2: 4a94 ldr r2, [pc, #592] @ (8010a34 ) 80107e4: 4293 cmp r3, r2 80107e6: d04c beq.n 8010882 80107e8: 4a92 ldr r2, [pc, #584] @ (8010a34 ) 80107ea: 4293 cmp r3, r2 80107ec: d863 bhi.n 80108b6 80107ee: 4a92 ldr r2, [pc, #584] @ (8010a38 ) 80107f0: 4293 cmp r3, r2 80107f2: d046 beq.n 8010882 80107f4: 4a90 ldr r2, [pc, #576] @ (8010a38 ) 80107f6: 4293 cmp r3, r2 80107f8: d85d bhi.n 80108b6 80107fa: 2b12 cmp r3, #18 80107fc: d82a bhi.n 8010854 80107fe: 2b12 cmp r3, #18 8010800: d859 bhi.n 80108b6 8010802: a201 add r2, pc, #4 @ (adr r2, 8010808 ) 8010804: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8010808: 08010883 .word 0x08010883 801080c: 0801085d .word 0x0801085d 8010810: 0801086f .word 0x0801086f 8010814: 080108b1 .word 0x080108b1 8010818: 080108b7 .word 0x080108b7 801081c: 080108b7 .word 0x080108b7 8010820: 080108b7 .word 0x080108b7 8010824: 080108b7 .word 0x080108b7 8010828: 080108b7 .word 0x080108b7 801082c: 080108b7 .word 0x080108b7 8010830: 080108b7 .word 0x080108b7 8010834: 080108b7 .word 0x080108b7 8010838: 080108b7 .word 0x080108b7 801083c: 080108b7 .word 0x080108b7 8010840: 080108b7 .word 0x080108b7 8010844: 080108b7 .word 0x080108b7 8010848: 080108b7 .word 0x080108b7 801084c: 08010865 .word 0x08010865 8010850: 08010879 .word 0x08010879 8010854: 4a79 ldr r2, [pc, #484] @ (8010a3c ) 8010856: 4293 cmp r3, r2 8010858: d013 beq.n 8010882 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 801085a: e02c b.n 80108b6 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 801085c: 683b ldr r3, [r7, #0] 801085e: 68db ldr r3, [r3, #12] 8010860: 623b str r3, [r7, #32] break; 8010862: e029 b.n 80108b8 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8010864: 683b ldr r3, [r7, #0] 8010866: 68db ldr r3, [r3, #12] 8010868: 3304 adds r3, #4 801086a: 623b str r3, [r7, #32] break; 801086c: e024 b.n 80108b8 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 801086e: 683b ldr r3, [r7, #0] 8010870: 68db ldr r3, [r3, #12] 8010872: 3308 adds r3, #8 8010874: 623b str r3, [r7, #32] break; 8010876: e01f b.n 80108b8 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8010878: 683b ldr r3, [r7, #0] 801087a: 68db ldr r3, [r3, #12] 801087c: 330c adds r3, #12 801087e: 623b str r3, [r7, #32] break; 8010880: e01a b.n 80108b8 if (GPIO_Init->Pull == GPIO_NOPULL) 8010882: 683b ldr r3, [r7, #0] 8010884: 689b ldr r3, [r3, #8] 8010886: 2b00 cmp r3, #0 8010888: d102 bne.n 8010890 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 801088a: 2304 movs r3, #4 801088c: 623b str r3, [r7, #32] break; 801088e: e013 b.n 80108b8 else if (GPIO_Init->Pull == GPIO_PULLUP) 8010890: 683b ldr r3, [r7, #0] 8010892: 689b ldr r3, [r3, #8] 8010894: 2b01 cmp r3, #1 8010896: d105 bne.n 80108a4 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8010898: 2308 movs r3, #8 801089a: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 801089c: 687b ldr r3, [r7, #4] 801089e: 69fa ldr r2, [r7, #28] 80108a0: 611a str r2, [r3, #16] break; 80108a2: e009 b.n 80108b8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80108a4: 2308 movs r3, #8 80108a6: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 80108a8: 687b ldr r3, [r7, #4] 80108aa: 69fa ldr r2, [r7, #28] 80108ac: 615a str r2, [r3, #20] break; 80108ae: e003 b.n 80108b8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 80108b0: 2300 movs r3, #0 80108b2: 623b str r3, [r7, #32] break; 80108b4: e000 b.n 80108b8 break; 80108b6: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 80108b8: 69bb ldr r3, [r7, #24] 80108ba: 2bff cmp r3, #255 @ 0xff 80108bc: d801 bhi.n 80108c2 80108be: 687b ldr r3, [r7, #4] 80108c0: e001 b.n 80108c6 80108c2: 687b ldr r3, [r7, #4] 80108c4: 3304 adds r3, #4 80108c6: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 80108c8: 69bb ldr r3, [r7, #24] 80108ca: 2bff cmp r3, #255 @ 0xff 80108cc: d802 bhi.n 80108d4 80108ce: 6a7b ldr r3, [r7, #36] @ 0x24 80108d0: 009b lsls r3, r3, #2 80108d2: e002 b.n 80108da 80108d4: 6a7b ldr r3, [r7, #36] @ 0x24 80108d6: 3b08 subs r3, #8 80108d8: 009b lsls r3, r3, #2 80108da: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 80108dc: 697b ldr r3, [r7, #20] 80108de: 681a ldr r2, [r3, #0] 80108e0: 210f movs r1, #15 80108e2: 693b ldr r3, [r7, #16] 80108e4: fa01 f303 lsl.w r3, r1, r3 80108e8: 43db mvns r3, r3 80108ea: 401a ands r2, r3 80108ec: 6a39 ldr r1, [r7, #32] 80108ee: 693b ldr r3, [r7, #16] 80108f0: fa01 f303 lsl.w r3, r1, r3 80108f4: 431a orrs r2, r3 80108f6: 697b ldr r3, [r7, #20] 80108f8: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 80108fa: 683b ldr r3, [r7, #0] 80108fc: 685b ldr r3, [r3, #4] 80108fe: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010902: 2b00 cmp r3, #0 8010904: f000 80b1 beq.w 8010a6a { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8010908: 4b4d ldr r3, [pc, #308] @ (8010a40 ) 801090a: 699b ldr r3, [r3, #24] 801090c: 4a4c ldr r2, [pc, #304] @ (8010a40 ) 801090e: f043 0301 orr.w r3, r3, #1 8010912: 6193 str r3, [r2, #24] 8010914: 4b4a ldr r3, [pc, #296] @ (8010a40 ) 8010916: 699b ldr r3, [r3, #24] 8010918: f003 0301 and.w r3, r3, #1 801091c: 60bb str r3, [r7, #8] 801091e: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8010920: 4a48 ldr r2, [pc, #288] @ (8010a44 ) 8010922: 6a7b ldr r3, [r7, #36] @ 0x24 8010924: 089b lsrs r3, r3, #2 8010926: 3302 adds r3, #2 8010928: f852 3023 ldr.w r3, [r2, r3, lsl #2] 801092c: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 801092e: 6a7b ldr r3, [r7, #36] @ 0x24 8010930: f003 0303 and.w r3, r3, #3 8010934: 009b lsls r3, r3, #2 8010936: 220f movs r2, #15 8010938: fa02 f303 lsl.w r3, r2, r3 801093c: 43db mvns r3, r3 801093e: 68fa ldr r2, [r7, #12] 8010940: 4013 ands r3, r2 8010942: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8010944: 687b ldr r3, [r7, #4] 8010946: 4a40 ldr r2, [pc, #256] @ (8010a48 ) 8010948: 4293 cmp r3, r2 801094a: d013 beq.n 8010974 801094c: 687b ldr r3, [r7, #4] 801094e: 4a3f ldr r2, [pc, #252] @ (8010a4c ) 8010950: 4293 cmp r3, r2 8010952: d00d beq.n 8010970 8010954: 687b ldr r3, [r7, #4] 8010956: 4a3e ldr r2, [pc, #248] @ (8010a50 ) 8010958: 4293 cmp r3, r2 801095a: d007 beq.n 801096c 801095c: 687b ldr r3, [r7, #4] 801095e: 4a3d ldr r2, [pc, #244] @ (8010a54 ) 8010960: 4293 cmp r3, r2 8010962: d101 bne.n 8010968 8010964: 2303 movs r3, #3 8010966: e006 b.n 8010976 8010968: 2304 movs r3, #4 801096a: e004 b.n 8010976 801096c: 2302 movs r3, #2 801096e: e002 b.n 8010976 8010970: 2301 movs r3, #1 8010972: e000 b.n 8010976 8010974: 2300 movs r3, #0 8010976: 6a7a ldr r2, [r7, #36] @ 0x24 8010978: f002 0203 and.w r2, r2, #3 801097c: 0092 lsls r2, r2, #2 801097e: 4093 lsls r3, r2 8010980: 68fa ldr r2, [r7, #12] 8010982: 4313 orrs r3, r2 8010984: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 8010986: 492f ldr r1, [pc, #188] @ (8010a44 ) 8010988: 6a7b ldr r3, [r7, #36] @ 0x24 801098a: 089b lsrs r3, r3, #2 801098c: 3302 adds r3, #2 801098e: 68fa ldr r2, [r7, #12] 8010990: f841 2023 str.w r2, [r1, r3, lsl #2] /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8010994: 683b ldr r3, [r7, #0] 8010996: 685b ldr r3, [r3, #4] 8010998: f403 1380 and.w r3, r3, #1048576 @ 0x100000 801099c: 2b00 cmp r3, #0 801099e: d006 beq.n 80109ae { SET_BIT(EXTI->RTSR, iocurrent); 80109a0: 4b2d ldr r3, [pc, #180] @ (8010a58 ) 80109a2: 689a ldr r2, [r3, #8] 80109a4: 492c ldr r1, [pc, #176] @ (8010a58 ) 80109a6: 69bb ldr r3, [r7, #24] 80109a8: 4313 orrs r3, r2 80109aa: 608b str r3, [r1, #8] 80109ac: e006 b.n 80109bc } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 80109ae: 4b2a ldr r3, [pc, #168] @ (8010a58 ) 80109b0: 689a ldr r2, [r3, #8] 80109b2: 69bb ldr r3, [r7, #24] 80109b4: 43db mvns r3, r3 80109b6: 4928 ldr r1, [pc, #160] @ (8010a58 ) 80109b8: 4013 ands r3, r2 80109ba: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 80109bc: 683b ldr r3, [r7, #0] 80109be: 685b ldr r3, [r3, #4] 80109c0: f403 1300 and.w r3, r3, #2097152 @ 0x200000 80109c4: 2b00 cmp r3, #0 80109c6: d006 beq.n 80109d6 { SET_BIT(EXTI->FTSR, iocurrent); 80109c8: 4b23 ldr r3, [pc, #140] @ (8010a58 ) 80109ca: 68da ldr r2, [r3, #12] 80109cc: 4922 ldr r1, [pc, #136] @ (8010a58 ) 80109ce: 69bb ldr r3, [r7, #24] 80109d0: 4313 orrs r3, r2 80109d2: 60cb str r3, [r1, #12] 80109d4: e006 b.n 80109e4 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 80109d6: 4b20 ldr r3, [pc, #128] @ (8010a58 ) 80109d8: 68da ldr r2, [r3, #12] 80109da: 69bb ldr r3, [r7, #24] 80109dc: 43db mvns r3, r3 80109de: 491e ldr r1, [pc, #120] @ (8010a58 ) 80109e0: 4013 ands r3, r2 80109e2: 60cb str r3, [r1, #12] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 80109e4: 683b ldr r3, [r7, #0] 80109e6: 685b ldr r3, [r3, #4] 80109e8: f403 3300 and.w r3, r3, #131072 @ 0x20000 80109ec: 2b00 cmp r3, #0 80109ee: d006 beq.n 80109fe { SET_BIT(EXTI->EMR, iocurrent); 80109f0: 4b19 ldr r3, [pc, #100] @ (8010a58 ) 80109f2: 685a ldr r2, [r3, #4] 80109f4: 4918 ldr r1, [pc, #96] @ (8010a58 ) 80109f6: 69bb ldr r3, [r7, #24] 80109f8: 4313 orrs r3, r2 80109fa: 604b str r3, [r1, #4] 80109fc: e006 b.n 8010a0c } else { CLEAR_BIT(EXTI->EMR, iocurrent); 80109fe: 4b16 ldr r3, [pc, #88] @ (8010a58 ) 8010a00: 685a ldr r2, [r3, #4] 8010a02: 69bb ldr r3, [r7, #24] 8010a04: 43db mvns r3, r3 8010a06: 4914 ldr r1, [pc, #80] @ (8010a58 ) 8010a08: 4013 ands r3, r2 8010a0a: 604b str r3, [r1, #4] } /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8010a0c: 683b ldr r3, [r7, #0] 8010a0e: 685b ldr r3, [r3, #4] 8010a10: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010a14: 2b00 cmp r3, #0 8010a16: d021 beq.n 8010a5c { SET_BIT(EXTI->IMR, iocurrent); 8010a18: 4b0f ldr r3, [pc, #60] @ (8010a58 ) 8010a1a: 681a ldr r2, [r3, #0] 8010a1c: 490e ldr r1, [pc, #56] @ (8010a58 ) 8010a1e: 69bb ldr r3, [r7, #24] 8010a20: 4313 orrs r3, r2 8010a22: 600b str r3, [r1, #0] 8010a24: e021 b.n 8010a6a 8010a26: bf00 nop 8010a28: 10320000 .word 0x10320000 8010a2c: 10310000 .word 0x10310000 8010a30: 10220000 .word 0x10220000 8010a34: 10210000 .word 0x10210000 8010a38: 10120000 .word 0x10120000 8010a3c: 10110000 .word 0x10110000 8010a40: 40021000 .word 0x40021000 8010a44: 40010000 .word 0x40010000 8010a48: 40010800 .word 0x40010800 8010a4c: 40010c00 .word 0x40010c00 8010a50: 40011000 .word 0x40011000 8010a54: 40011400 .word 0x40011400 8010a58: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8010a5c: 4b0b ldr r3, [pc, #44] @ (8010a8c ) 8010a5e: 681a ldr r2, [r3, #0] 8010a60: 69bb ldr r3, [r7, #24] 8010a62: 43db mvns r3, r3 8010a64: 4909 ldr r1, [pc, #36] @ (8010a8c ) 8010a66: 4013 ands r3, r2 8010a68: 600b str r3, [r1, #0] } } } position++; 8010a6a: 6a7b ldr r3, [r7, #36] @ 0x24 8010a6c: 3301 adds r3, #1 8010a6e: 627b str r3, [r7, #36] @ 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8010a70: 683b ldr r3, [r7, #0] 8010a72: 681a ldr r2, [r3, #0] 8010a74: 6a7b ldr r3, [r7, #36] @ 0x24 8010a76: fa22 f303 lsr.w r3, r2, r3 8010a7a: 2b00 cmp r3, #0 8010a7c: f47f ae8e bne.w 801079c } } 8010a80: bf00 nop 8010a82: bf00 nop 8010a84: 372c adds r7, #44 @ 0x2c 8010a86: 46bd mov sp, r7 8010a88: bc80 pop {r7} 8010a8a: 4770 bx lr 8010a8c: 40010400 .word 0x40010400 08010a90 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8010a90: b480 push {r7} 8010a92: b085 sub sp, #20 8010a94: af00 add r7, sp, #0 8010a96: 6078 str r0, [r7, #4] 8010a98: 460b mov r3, r1 8010a9a: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8010a9c: 687b ldr r3, [r7, #4] 8010a9e: 689a ldr r2, [r3, #8] 8010aa0: 887b ldrh r3, [r7, #2] 8010aa2: 4013 ands r3, r2 8010aa4: 2b00 cmp r3, #0 8010aa6: d002 beq.n 8010aae { bitstatus = GPIO_PIN_SET; 8010aa8: 2301 movs r3, #1 8010aaa: 73fb strb r3, [r7, #15] 8010aac: e001 b.n 8010ab2 } else { bitstatus = GPIO_PIN_RESET; 8010aae: 2300 movs r3, #0 8010ab0: 73fb strb r3, [r7, #15] } return bitstatus; 8010ab2: 7bfb ldrb r3, [r7, #15] } 8010ab4: 4618 mov r0, r3 8010ab6: 3714 adds r7, #20 8010ab8: 46bd mov sp, r7 8010aba: bc80 pop {r7} 8010abc: 4770 bx lr 08010abe : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8010abe: b480 push {r7} 8010ac0: b083 sub sp, #12 8010ac2: af00 add r7, sp, #0 8010ac4: 6078 str r0, [r7, #4] 8010ac6: 460b mov r3, r1 8010ac8: 807b strh r3, [r7, #2] 8010aca: 4613 mov r3, r2 8010acc: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8010ace: 787b ldrb r3, [r7, #1] 8010ad0: 2b00 cmp r3, #0 8010ad2: d003 beq.n 8010adc { GPIOx->BSRR = GPIO_Pin; 8010ad4: 887a ldrh r2, [r7, #2] 8010ad6: 687b ldr r3, [r7, #4] 8010ad8: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 8010ada: e003 b.n 8010ae4 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 8010adc: 887b ldrh r3, [r7, #2] 8010ade: 041a lsls r2, r3, #16 8010ae0: 687b ldr r3, [r7, #4] 8010ae2: 611a str r2, [r3, #16] } 8010ae4: bf00 nop 8010ae6: 370c adds r7, #12 8010ae8: 46bd mov sp, r7 8010aea: bc80 pop {r7} 8010aec: 4770 bx lr ... 08010af0 : * @note If the HSE divided by 128 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { 8010af0: b480 push {r7} 8010af2: af00 add r7, sp, #0 /* Enable access to RTC and backup registers */ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 8010af4: 4b03 ldr r3, [pc, #12] @ (8010b04 ) 8010af6: 2201 movs r2, #1 8010af8: 601a str r2, [r3, #0] } 8010afa: bf00 nop 8010afc: 46bd mov sp, r7 8010afe: bc80 pop {r7} 8010b00: 4770 bx lr 8010b02: bf00 nop 8010b04: 420e0020 .word 0x420e0020 08010b08 : * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval HAL_StatusTypeDef */ HAL_StatusTypeDef HAL_RCC_DeInit(void) { 8010b08: b580 push {r7, lr} 8010b0a: b082 sub sp, #8 8010b0c: af00 add r7, sp, #0 uint32_t tickstart; /* Get Start Tick */ tickstart = HAL_GetTick(); 8010b0e: f7fd fc3f bl 800e390 8010b12: 6078 str r0, [r7, #4] /* Set HSION bit */ SET_BIT(RCC->CR, RCC_CR_HSION); 8010b14: 4b60 ldr r3, [pc, #384] @ (8010c98 ) 8010b16: 681b ldr r3, [r3, #0] 8010b18: 4a5f ldr r2, [pc, #380] @ (8010c98 ) 8010b1a: f043 0301 orr.w r3, r3, #1 8010b1e: 6013 str r3, [r2, #0] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 8010b20: e008 b.n 8010b34 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8010b22: f7fd fc35 bl 800e390 8010b26: 4602 mov r2, r0 8010b28: 687b ldr r3, [r7, #4] 8010b2a: 1ad3 subs r3, r2, r3 8010b2c: 2b02 cmp r3, #2 8010b2e: d901 bls.n 8010b34 { return HAL_TIMEOUT; 8010b30: 2303 movs r3, #3 8010b32: e0ac b.n 8010c8e while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 8010b34: 4b58 ldr r3, [pc, #352] @ (8010c98 ) 8010b36: 681b ldr r3, [r3, #0] 8010b38: f003 0302 and.w r3, r3, #2 8010b3c: 2b00 cmp r3, #0 8010b3e: d0f0 beq.n 8010b22 } } /* Set HSITRIM bits to the reset value */ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos)); 8010b40: 4b55 ldr r3, [pc, #340] @ (8010c98 ) 8010b42: 681b ldr r3, [r3, #0] 8010b44: f023 03f8 bic.w r3, r3, #248 @ 0xf8 8010b48: 4a53 ldr r2, [pc, #332] @ (8010c98 ) 8010b4a: f043 0380 orr.w r3, r3, #128 @ 0x80 8010b4e: 6013 str r3, [r2, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010b50: f7fd fc1e bl 800e390 8010b54: 6078 str r0, [r7, #4] /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); 8010b56: 4b50 ldr r3, [pc, #320] @ (8010c98 ) 8010b58: 2200 movs r2, #0 8010b5a: 605a str r2, [r3, #4] /* Wait till clock switch is ready */ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 8010b5c: e00a b.n 8010b74 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8010b5e: f7fd fc17 bl 800e390 8010b62: 4602 mov r2, r0 8010b64: 687b ldr r3, [r7, #4] 8010b66: 1ad3 subs r3, r2, r3 8010b68: f241 3288 movw r2, #5000 @ 0x1388 8010b6c: 4293 cmp r3, r2 8010b6e: d901 bls.n 8010b74 { return HAL_TIMEOUT; 8010b70: 2303 movs r3, #3 8010b72: e08c b.n 8010c8e while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 8010b74: 4b48 ldr r3, [pc, #288] @ (8010c98 ) 8010b76: 685b ldr r3, [r3, #4] 8010b78: f003 030c and.w r3, r3, #12 8010b7c: 2b00 cmp r3, #0 8010b7e: d1ee bne.n 8010b5e } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HSI_VALUE; 8010b80: 4b46 ldr r3, [pc, #280] @ (8010c9c ) 8010b82: 4a47 ldr r2, [pc, #284] @ (8010ca0 ) 8010b84: 601a str r2, [r3, #0] /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 8010b86: 4b47 ldr r3, [pc, #284] @ (8010ca4 ) 8010b88: 681b ldr r3, [r3, #0] 8010b8a: 4618 mov r0, r3 8010b8c: f7fd fbbe bl 800e30c 8010b90: 4603 mov r3, r0 8010b92: 2b00 cmp r3, #0 8010b94: d001 beq.n 8010b9a { return HAL_ERROR; 8010b96: 2301 movs r3, #1 8010b98: e079 b.n 8010c8e } /* Get Start Tick */ tickstart = HAL_GetTick(); 8010b9a: f7fd fbf9 bl 800e390 8010b9e: 6078 str r0, [r7, #4] /* Second step is to clear PLLON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 8010ba0: 4b3d ldr r3, [pc, #244] @ (8010c98 ) 8010ba2: 681b ldr r3, [r3, #0] 8010ba4: 4a3c ldr r2, [pc, #240] @ (8010c98 ) 8010ba6: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 8010baa: 6013 str r3, [r2, #0] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 8010bac: e008 b.n 8010bc0 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8010bae: f7fd fbef bl 800e390 8010bb2: 4602 mov r2, r0 8010bb4: 687b ldr r3, [r7, #4] 8010bb6: 1ad3 subs r3, r2, r3 8010bb8: 2b02 cmp r3, #2 8010bba: d901 bls.n 8010bc0 { return HAL_TIMEOUT; 8010bbc: 2303 movs r3, #3 8010bbe: e066 b.n 8010c8e while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 8010bc0: 4b35 ldr r3, [pc, #212] @ (8010c98 ) 8010bc2: 681b ldr r3, [r3, #0] 8010bc4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8010bc8: 2b00 cmp r3, #0 8010bca: d1f0 bne.n 8010bae } } /* Ensure to reset PLLSRC and PLLMUL bits */ CLEAR_REG(RCC->CFGR); 8010bcc: 4b32 ldr r3, [pc, #200] @ (8010c98 ) 8010bce: 2200 movs r2, #0 8010bd0: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010bd2: f7fd fbdd bl 800e390 8010bd6: 6078 str r0, [r7, #4] /* Reset HSEON & CSSON bits */ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON); 8010bd8: 4b2f ldr r3, [pc, #188] @ (8010c98 ) 8010bda: 681b ldr r3, [r3, #0] 8010bdc: 4a2e ldr r2, [pc, #184] @ (8010c98 ) 8010bde: f423 2310 bic.w r3, r3, #589824 @ 0x90000 8010be2: 6013 str r3, [r2, #0] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 8010be4: e008 b.n 8010bf8 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8010be6: f7fd fbd3 bl 800e390 8010bea: 4602 mov r2, r0 8010bec: 687b ldr r3, [r7, #4] 8010bee: 1ad3 subs r3, r2, r3 8010bf0: 2b64 cmp r3, #100 @ 0x64 8010bf2: d901 bls.n 8010bf8 { return HAL_TIMEOUT; 8010bf4: 2303 movs r3, #3 8010bf6: e04a b.n 8010c8e while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 8010bf8: 4b27 ldr r3, [pc, #156] @ (8010c98 ) 8010bfa: 681b ldr r3, [r3, #0] 8010bfc: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010c00: 2b00 cmp r3, #0 8010c02: d1f0 bne.n 8010be6 } } /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 8010c04: 4b24 ldr r3, [pc, #144] @ (8010c98 ) 8010c06: 681b ldr r3, [r3, #0] 8010c08: 4a23 ldr r2, [pc, #140] @ (8010c98 ) 8010c0a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010c0e: 6013 str r3, [r2, #0] #if defined(RCC_PLL2_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 8010c10: f7fd fbbe bl 800e390 8010c14: 6078 str r0, [r7, #4] /* Clear PLL2ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); 8010c16: 4b20 ldr r3, [pc, #128] @ (8010c98 ) 8010c18: 681b ldr r3, [r3, #0] 8010c1a: 4a1f ldr r2, [pc, #124] @ (8010c98 ) 8010c1c: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8010c20: 6013 str r3, [r2, #0] /* Wait till PLL2 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 8010c22: e008 b.n 8010c36 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8010c24: f7fd fbb4 bl 800e390 8010c28: 4602 mov r2, r0 8010c2a: 687b ldr r3, [r7, #4] 8010c2c: 1ad3 subs r3, r2, r3 8010c2e: 2b64 cmp r3, #100 @ 0x64 8010c30: d901 bls.n 8010c36 { return HAL_TIMEOUT; 8010c32: 2303 movs r3, #3 8010c34: e02b b.n 8010c8e while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) 8010c36: 4b18 ldr r3, [pc, #96] @ (8010c98 ) 8010c38: 681b ldr r3, [r3, #0] 8010c3a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8010c3e: 2b00 cmp r3, #0 8010c40: d1f0 bne.n 8010c24 } #endif /* RCC_PLL2_SUPPORT */ #if defined(RCC_PLLI2S_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); 8010c42: f7fd fba5 bl 800e390 8010c46: 6078 str r0, [r7, #4] /* Clear PLL3ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); 8010c48: 4b13 ldr r3, [pc, #76] @ (8010c98 ) 8010c4a: 681b ldr r3, [r3, #0] 8010c4c: 4a12 ldr r2, [pc, #72] @ (8010c98 ) 8010c4e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8010c52: 6013 str r3, [r2, #0] /* Wait till PLL3 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 8010c54: e008 b.n 8010c68 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8010c56: f7fd fb9b bl 800e390 8010c5a: 4602 mov r2, r0 8010c5c: 687b ldr r3, [r7, #4] 8010c5e: 1ad3 subs r3, r2, r3 8010c60: 2b64 cmp r3, #100 @ 0x64 8010c62: d901 bls.n 8010c68 { return HAL_TIMEOUT; 8010c64: 2303 movs r3, #3 8010c66: e012 b.n 8010c8e while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) 8010c68: 4b0b ldr r3, [pc, #44] @ (8010c98 ) 8010c6a: 681b ldr r3, [r3, #0] 8010c6c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8010c70: 2b00 cmp r3, #0 8010c72: d1f0 bne.n 8010c56 } #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_CFGR2_PREDIV1) /* Reset CFGR2 register */ CLEAR_REG(RCC->CFGR2); 8010c74: 4b08 ldr r3, [pc, #32] @ (8010c98 ) 8010c76: 2200 movs r2, #0 8010c78: 62da str r2, [r3, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1 */ /* Reset all CSR flags */ SET_BIT(RCC->CSR, RCC_CSR_RMVF); 8010c7a: 4b07 ldr r3, [pc, #28] @ (8010c98 ) 8010c7c: 6a5b ldr r3, [r3, #36] @ 0x24 8010c7e: 4a06 ldr r2, [pc, #24] @ (8010c98 ) 8010c80: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8010c84: 6253 str r3, [r2, #36] @ 0x24 /* Disable all interrupts */ CLEAR_REG(RCC->CIR); 8010c86: 4b04 ldr r3, [pc, #16] @ (8010c98 ) 8010c88: 2200 movs r2, #0 8010c8a: 609a str r2, [r3, #8] return HAL_OK; 8010c8c: 2300 movs r3, #0 } 8010c8e: 4618 mov r0, r3 8010c90: 3708 adds r7, #8 8010c92: 46bd mov sp, r7 8010c94: bd80 pop {r7, pc} 8010c96: bf00 nop 8010c98: 40021000 .word 0x40021000 8010c9c: 20000084 .word 0x20000084 8010ca0: 007a1200 .word 0x007a1200 8010ca4: 20000088 .word 0x20000088 08010ca8 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8010ca8: b580 push {r7, lr} 8010caa: b086 sub sp, #24 8010cac: af00 add r7, sp, #0 8010cae: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8010cb0: 687b ldr r3, [r7, #4] 8010cb2: 2b00 cmp r3, #0 8010cb4: d101 bne.n 8010cba { return HAL_ERROR; 8010cb6: 2301 movs r3, #1 8010cb8: e304 b.n 80112c4 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8010cba: 687b ldr r3, [r7, #4] 8010cbc: 681b ldr r3, [r3, #0] 8010cbe: f003 0301 and.w r3, r3, #1 8010cc2: 2b00 cmp r3, #0 8010cc4: f000 8087 beq.w 8010dd6 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8010cc8: 4b92 ldr r3, [pc, #584] @ (8010f14 ) 8010cca: 685b ldr r3, [r3, #4] 8010ccc: f003 030c and.w r3, r3, #12 8010cd0: 2b04 cmp r3, #4 8010cd2: d00c beq.n 8010cee || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8010cd4: 4b8f ldr r3, [pc, #572] @ (8010f14 ) 8010cd6: 685b ldr r3, [r3, #4] 8010cd8: f003 030c and.w r3, r3, #12 8010cdc: 2b08 cmp r3, #8 8010cde: d112 bne.n 8010d06 8010ce0: 4b8c ldr r3, [pc, #560] @ (8010f14 ) 8010ce2: 685b ldr r3, [r3, #4] 8010ce4: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010ce8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010cec: d10b bne.n 8010d06 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8010cee: 4b89 ldr r3, [pc, #548] @ (8010f14 ) 8010cf0: 681b ldr r3, [r3, #0] 8010cf2: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010cf6: 2b00 cmp r3, #0 8010cf8: d06c beq.n 8010dd4 8010cfa: 687b ldr r3, [r7, #4] 8010cfc: 689b ldr r3, [r3, #8] 8010cfe: 2b00 cmp r3, #0 8010d00: d168 bne.n 8010dd4 { return HAL_ERROR; 8010d02: 2301 movs r3, #1 8010d04: e2de b.n 80112c4 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8010d06: 687b ldr r3, [r7, #4] 8010d08: 689b ldr r3, [r3, #8] 8010d0a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8010d0e: d106 bne.n 8010d1e 8010d10: 4b80 ldr r3, [pc, #512] @ (8010f14 ) 8010d12: 681b ldr r3, [r3, #0] 8010d14: 4a7f ldr r2, [pc, #508] @ (8010f14 ) 8010d16: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8010d1a: 6013 str r3, [r2, #0] 8010d1c: e02e b.n 8010d7c 8010d1e: 687b ldr r3, [r7, #4] 8010d20: 689b ldr r3, [r3, #8] 8010d22: 2b00 cmp r3, #0 8010d24: d10c bne.n 8010d40 8010d26: 4b7b ldr r3, [pc, #492] @ (8010f14 ) 8010d28: 681b ldr r3, [r3, #0] 8010d2a: 4a7a ldr r2, [pc, #488] @ (8010f14 ) 8010d2c: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8010d30: 6013 str r3, [r2, #0] 8010d32: 4b78 ldr r3, [pc, #480] @ (8010f14 ) 8010d34: 681b ldr r3, [r3, #0] 8010d36: 4a77 ldr r2, [pc, #476] @ (8010f14 ) 8010d38: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010d3c: 6013 str r3, [r2, #0] 8010d3e: e01d b.n 8010d7c 8010d40: 687b ldr r3, [r7, #4] 8010d42: 689b ldr r3, [r3, #8] 8010d44: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8010d48: d10c bne.n 8010d64 8010d4a: 4b72 ldr r3, [pc, #456] @ (8010f14 ) 8010d4c: 681b ldr r3, [r3, #0] 8010d4e: 4a71 ldr r2, [pc, #452] @ (8010f14 ) 8010d50: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8010d54: 6013 str r3, [r2, #0] 8010d56: 4b6f ldr r3, [pc, #444] @ (8010f14 ) 8010d58: 681b ldr r3, [r3, #0] 8010d5a: 4a6e ldr r2, [pc, #440] @ (8010f14 ) 8010d5c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8010d60: 6013 str r3, [r2, #0] 8010d62: e00b b.n 8010d7c 8010d64: 4b6b ldr r3, [pc, #428] @ (8010f14 ) 8010d66: 681b ldr r3, [r3, #0] 8010d68: 4a6a ldr r2, [pc, #424] @ (8010f14 ) 8010d6a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8010d6e: 6013 str r3, [r2, #0] 8010d70: 4b68 ldr r3, [pc, #416] @ (8010f14 ) 8010d72: 681b ldr r3, [r3, #0] 8010d74: 4a67 ldr r2, [pc, #412] @ (8010f14 ) 8010d76: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010d7a: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8010d7c: 687b ldr r3, [r7, #4] 8010d7e: 689b ldr r3, [r3, #8] 8010d80: 2b00 cmp r3, #0 8010d82: d013 beq.n 8010dac { /* Get Start Tick */ tickstart = HAL_GetTick(); 8010d84: f7fd fb04 bl 800e390 8010d88: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8010d8a: e008 b.n 8010d9e { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8010d8c: f7fd fb00 bl 800e390 8010d90: 4602 mov r2, r0 8010d92: 693b ldr r3, [r7, #16] 8010d94: 1ad3 subs r3, r2, r3 8010d96: 2b64 cmp r3, #100 @ 0x64 8010d98: d901 bls.n 8010d9e { return HAL_TIMEOUT; 8010d9a: 2303 movs r3, #3 8010d9c: e292 b.n 80112c4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8010d9e: 4b5d ldr r3, [pc, #372] @ (8010f14 ) 8010da0: 681b ldr r3, [r3, #0] 8010da2: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010da6: 2b00 cmp r3, #0 8010da8: d0f0 beq.n 8010d8c 8010daa: e014 b.n 8010dd6 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8010dac: f7fd faf0 bl 800e390 8010db0: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8010db2: e008 b.n 8010dc6 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8010db4: f7fd faec bl 800e390 8010db8: 4602 mov r2, r0 8010dba: 693b ldr r3, [r7, #16] 8010dbc: 1ad3 subs r3, r2, r3 8010dbe: 2b64 cmp r3, #100 @ 0x64 8010dc0: d901 bls.n 8010dc6 { return HAL_TIMEOUT; 8010dc2: 2303 movs r3, #3 8010dc4: e27e b.n 80112c4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8010dc6: 4b53 ldr r3, [pc, #332] @ (8010f14 ) 8010dc8: 681b ldr r3, [r3, #0] 8010dca: f403 3300 and.w r3, r3, #131072 @ 0x20000 8010dce: 2b00 cmp r3, #0 8010dd0: d1f0 bne.n 8010db4 8010dd2: e000 b.n 8010dd6 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8010dd4: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8010dd6: 687b ldr r3, [r7, #4] 8010dd8: 681b ldr r3, [r3, #0] 8010dda: f003 0302 and.w r3, r3, #2 8010dde: 2b00 cmp r3, #0 8010de0: d063 beq.n 8010eaa /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8010de2: 4b4c ldr r3, [pc, #304] @ (8010f14 ) 8010de4: 685b ldr r3, [r3, #4] 8010de6: f003 030c and.w r3, r3, #12 8010dea: 2b00 cmp r3, #0 8010dec: d00b beq.n 8010e06 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 8010dee: 4b49 ldr r3, [pc, #292] @ (8010f14 ) 8010df0: 685b ldr r3, [r3, #4] 8010df2: f003 030c and.w r3, r3, #12 8010df6: 2b08 cmp r3, #8 8010df8: d11c bne.n 8010e34 8010dfa: 4b46 ldr r3, [pc, #280] @ (8010f14 ) 8010dfc: 685b ldr r3, [r3, #4] 8010dfe: f403 3380 and.w r3, r3, #65536 @ 0x10000 8010e02: 2b00 cmp r3, #0 8010e04: d116 bne.n 8010e34 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8010e06: 4b43 ldr r3, [pc, #268] @ (8010f14 ) 8010e08: 681b ldr r3, [r3, #0] 8010e0a: f003 0302 and.w r3, r3, #2 8010e0e: 2b00 cmp r3, #0 8010e10: d005 beq.n 8010e1e 8010e12: 687b ldr r3, [r7, #4] 8010e14: 695b ldr r3, [r3, #20] 8010e16: 2b01 cmp r3, #1 8010e18: d001 beq.n 8010e1e { return HAL_ERROR; 8010e1a: 2301 movs r3, #1 8010e1c: e252 b.n 80112c4 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8010e1e: 4b3d ldr r3, [pc, #244] @ (8010f14 ) 8010e20: 681b ldr r3, [r3, #0] 8010e22: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8010e26: 687b ldr r3, [r7, #4] 8010e28: 699b ldr r3, [r3, #24] 8010e2a: 00db lsls r3, r3, #3 8010e2c: 4939 ldr r1, [pc, #228] @ (8010f14 ) 8010e2e: 4313 orrs r3, r2 8010e30: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8010e32: e03a b.n 8010eaa } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8010e34: 687b ldr r3, [r7, #4] 8010e36: 695b ldr r3, [r3, #20] 8010e38: 2b00 cmp r3, #0 8010e3a: d020 beq.n 8010e7e { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8010e3c: 4b36 ldr r3, [pc, #216] @ (8010f18 ) 8010e3e: 2201 movs r2, #1 8010e40: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010e42: f7fd faa5 bl 800e390 8010e46: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8010e48: e008 b.n 8010e5c { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8010e4a: f7fd faa1 bl 800e390 8010e4e: 4602 mov r2, r0 8010e50: 693b ldr r3, [r7, #16] 8010e52: 1ad3 subs r3, r2, r3 8010e54: 2b02 cmp r3, #2 8010e56: d901 bls.n 8010e5c { return HAL_TIMEOUT; 8010e58: 2303 movs r3, #3 8010e5a: e233 b.n 80112c4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8010e5c: 4b2d ldr r3, [pc, #180] @ (8010f14 ) 8010e5e: 681b ldr r3, [r3, #0] 8010e60: f003 0302 and.w r3, r3, #2 8010e64: 2b00 cmp r3, #0 8010e66: d0f0 beq.n 8010e4a } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8010e68: 4b2a ldr r3, [pc, #168] @ (8010f14 ) 8010e6a: 681b ldr r3, [r3, #0] 8010e6c: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8010e70: 687b ldr r3, [r7, #4] 8010e72: 699b ldr r3, [r3, #24] 8010e74: 00db lsls r3, r3, #3 8010e76: 4927 ldr r1, [pc, #156] @ (8010f14 ) 8010e78: 4313 orrs r3, r2 8010e7a: 600b str r3, [r1, #0] 8010e7c: e015 b.n 8010eaa } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8010e7e: 4b26 ldr r3, [pc, #152] @ (8010f18 ) 8010e80: 2200 movs r2, #0 8010e82: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010e84: f7fd fa84 bl 800e390 8010e88: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8010e8a: e008 b.n 8010e9e { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8010e8c: f7fd fa80 bl 800e390 8010e90: 4602 mov r2, r0 8010e92: 693b ldr r3, [r7, #16] 8010e94: 1ad3 subs r3, r2, r3 8010e96: 2b02 cmp r3, #2 8010e98: d901 bls.n 8010e9e { return HAL_TIMEOUT; 8010e9a: 2303 movs r3, #3 8010e9c: e212 b.n 80112c4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8010e9e: 4b1d ldr r3, [pc, #116] @ (8010f14 ) 8010ea0: 681b ldr r3, [r3, #0] 8010ea2: f003 0302 and.w r3, r3, #2 8010ea6: 2b00 cmp r3, #0 8010ea8: d1f0 bne.n 8010e8c } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8010eaa: 687b ldr r3, [r7, #4] 8010eac: 681b ldr r3, [r3, #0] 8010eae: f003 0308 and.w r3, r3, #8 8010eb2: 2b00 cmp r3, #0 8010eb4: d03a beq.n 8010f2c { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8010eb6: 687b ldr r3, [r7, #4] 8010eb8: 69db ldr r3, [r3, #28] 8010eba: 2b00 cmp r3, #0 8010ebc: d019 beq.n 8010ef2 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8010ebe: 4b17 ldr r3, [pc, #92] @ (8010f1c ) 8010ec0: 2201 movs r2, #1 8010ec2: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010ec4: f7fd fa64 bl 800e390 8010ec8: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8010eca: e008 b.n 8010ede { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8010ecc: f7fd fa60 bl 800e390 8010ed0: 4602 mov r2, r0 8010ed2: 693b ldr r3, [r7, #16] 8010ed4: 1ad3 subs r3, r2, r3 8010ed6: 2b02 cmp r3, #2 8010ed8: d901 bls.n 8010ede { return HAL_TIMEOUT; 8010eda: 2303 movs r3, #3 8010edc: e1f2 b.n 80112c4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8010ede: 4b0d ldr r3, [pc, #52] @ (8010f14 ) 8010ee0: 6a5b ldr r3, [r3, #36] @ 0x24 8010ee2: f003 0302 and.w r3, r3, #2 8010ee6: 2b00 cmp r3, #0 8010ee8: d0f0 beq.n 8010ecc } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 8010eea: 2001 movs r0, #1 8010eec: f000 fbca bl 8011684 8010ef0: e01c b.n 8010f2c } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8010ef2: 4b0a ldr r3, [pc, #40] @ (8010f1c ) 8010ef4: 2200 movs r2, #0 8010ef6: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8010ef8: f7fd fa4a bl 800e390 8010efc: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8010efe: e00f b.n 8010f20 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8010f00: f7fd fa46 bl 800e390 8010f04: 4602 mov r2, r0 8010f06: 693b ldr r3, [r7, #16] 8010f08: 1ad3 subs r3, r2, r3 8010f0a: 2b02 cmp r3, #2 8010f0c: d908 bls.n 8010f20 { return HAL_TIMEOUT; 8010f0e: 2303 movs r3, #3 8010f10: e1d8 b.n 80112c4 8010f12: bf00 nop 8010f14: 40021000 .word 0x40021000 8010f18: 42420000 .word 0x42420000 8010f1c: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8010f20: 4b9b ldr r3, [pc, #620] @ (8011190 ) 8010f22: 6a5b ldr r3, [r3, #36] @ 0x24 8010f24: f003 0302 and.w r3, r3, #2 8010f28: 2b00 cmp r3, #0 8010f2a: d1e9 bne.n 8010f00 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8010f2c: 687b ldr r3, [r7, #4] 8010f2e: 681b ldr r3, [r3, #0] 8010f30: f003 0304 and.w r3, r3, #4 8010f34: 2b00 cmp r3, #0 8010f36: f000 80a6 beq.w 8011086 { FlagStatus pwrclkchanged = RESET; 8010f3a: 2300 movs r3, #0 8010f3c: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8010f3e: 4b94 ldr r3, [pc, #592] @ (8011190 ) 8010f40: 69db ldr r3, [r3, #28] 8010f42: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010f46: 2b00 cmp r3, #0 8010f48: d10d bne.n 8010f66 { __HAL_RCC_PWR_CLK_ENABLE(); 8010f4a: 4b91 ldr r3, [pc, #580] @ (8011190 ) 8010f4c: 69db ldr r3, [r3, #28] 8010f4e: 4a90 ldr r2, [pc, #576] @ (8011190 ) 8010f50: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8010f54: 61d3 str r3, [r2, #28] 8010f56: 4b8e ldr r3, [pc, #568] @ (8011190 ) 8010f58: 69db ldr r3, [r3, #28] 8010f5a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010f5e: 60bb str r3, [r7, #8] 8010f60: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8010f62: 2301 movs r3, #1 8010f64: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010f66: 4b8b ldr r3, [pc, #556] @ (8011194 ) 8010f68: 681b ldr r3, [r3, #0] 8010f6a: f403 7380 and.w r3, r3, #256 @ 0x100 8010f6e: 2b00 cmp r3, #0 8010f70: d118 bne.n 8010fa4 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8010f72: 4b88 ldr r3, [pc, #544] @ (8011194 ) 8010f74: 681b ldr r3, [r3, #0] 8010f76: 4a87 ldr r2, [pc, #540] @ (8011194 ) 8010f78: f443 7380 orr.w r3, r3, #256 @ 0x100 8010f7c: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8010f7e: f7fd fa07 bl 800e390 8010f82: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010f84: e008 b.n 8010f98 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8010f86: f7fd fa03 bl 800e390 8010f8a: 4602 mov r2, r0 8010f8c: 693b ldr r3, [r7, #16] 8010f8e: 1ad3 subs r3, r2, r3 8010f90: 2b64 cmp r3, #100 @ 0x64 8010f92: d901 bls.n 8010f98 { return HAL_TIMEOUT; 8010f94: 2303 movs r3, #3 8010f96: e195 b.n 80112c4 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8010f98: 4b7e ldr r3, [pc, #504] @ (8011194 ) 8010f9a: 681b ldr r3, [r3, #0] 8010f9c: f403 7380 and.w r3, r3, #256 @ 0x100 8010fa0: 2b00 cmp r3, #0 8010fa2: d0f0 beq.n 8010f86 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8010fa4: 687b ldr r3, [r7, #4] 8010fa6: 691b ldr r3, [r3, #16] 8010fa8: 2b01 cmp r3, #1 8010faa: d106 bne.n 8010fba 8010fac: 4b78 ldr r3, [pc, #480] @ (8011190 ) 8010fae: 6a1b ldr r3, [r3, #32] 8010fb0: 4a77 ldr r2, [pc, #476] @ (8011190 ) 8010fb2: f043 0301 orr.w r3, r3, #1 8010fb6: 6213 str r3, [r2, #32] 8010fb8: e02d b.n 8011016 8010fba: 687b ldr r3, [r7, #4] 8010fbc: 691b ldr r3, [r3, #16] 8010fbe: 2b00 cmp r3, #0 8010fc0: d10c bne.n 8010fdc 8010fc2: 4b73 ldr r3, [pc, #460] @ (8011190 ) 8010fc4: 6a1b ldr r3, [r3, #32] 8010fc6: 4a72 ldr r2, [pc, #456] @ (8011190 ) 8010fc8: f023 0301 bic.w r3, r3, #1 8010fcc: 6213 str r3, [r2, #32] 8010fce: 4b70 ldr r3, [pc, #448] @ (8011190 ) 8010fd0: 6a1b ldr r3, [r3, #32] 8010fd2: 4a6f ldr r2, [pc, #444] @ (8011190 ) 8010fd4: f023 0304 bic.w r3, r3, #4 8010fd8: 6213 str r3, [r2, #32] 8010fda: e01c b.n 8011016 8010fdc: 687b ldr r3, [r7, #4] 8010fde: 691b ldr r3, [r3, #16] 8010fe0: 2b05 cmp r3, #5 8010fe2: d10c bne.n 8010ffe 8010fe4: 4b6a ldr r3, [pc, #424] @ (8011190 ) 8010fe6: 6a1b ldr r3, [r3, #32] 8010fe8: 4a69 ldr r2, [pc, #420] @ (8011190 ) 8010fea: f043 0304 orr.w r3, r3, #4 8010fee: 6213 str r3, [r2, #32] 8010ff0: 4b67 ldr r3, [pc, #412] @ (8011190 ) 8010ff2: 6a1b ldr r3, [r3, #32] 8010ff4: 4a66 ldr r2, [pc, #408] @ (8011190 ) 8010ff6: f043 0301 orr.w r3, r3, #1 8010ffa: 6213 str r3, [r2, #32] 8010ffc: e00b b.n 8011016 8010ffe: 4b64 ldr r3, [pc, #400] @ (8011190 ) 8011000: 6a1b ldr r3, [r3, #32] 8011002: 4a63 ldr r2, [pc, #396] @ (8011190 ) 8011004: f023 0301 bic.w r3, r3, #1 8011008: 6213 str r3, [r2, #32] 801100a: 4b61 ldr r3, [pc, #388] @ (8011190 ) 801100c: 6a1b ldr r3, [r3, #32] 801100e: 4a60 ldr r2, [pc, #384] @ (8011190 ) 8011010: f023 0304 bic.w r3, r3, #4 8011014: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8011016: 687b ldr r3, [r7, #4] 8011018: 691b ldr r3, [r3, #16] 801101a: 2b00 cmp r3, #0 801101c: d015 beq.n 801104a { /* Get Start Tick */ tickstart = HAL_GetTick(); 801101e: f7fd f9b7 bl 800e390 8011022: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8011024: e00a b.n 801103c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8011026: f7fd f9b3 bl 800e390 801102a: 4602 mov r2, r0 801102c: 693b ldr r3, [r7, #16] 801102e: 1ad3 subs r3, r2, r3 8011030: f241 3288 movw r2, #5000 @ 0x1388 8011034: 4293 cmp r3, r2 8011036: d901 bls.n 801103c { return HAL_TIMEOUT; 8011038: 2303 movs r3, #3 801103a: e143 b.n 80112c4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 801103c: 4b54 ldr r3, [pc, #336] @ (8011190 ) 801103e: 6a1b ldr r3, [r3, #32] 8011040: f003 0302 and.w r3, r3, #2 8011044: 2b00 cmp r3, #0 8011046: d0ee beq.n 8011026 8011048: e014 b.n 8011074 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 801104a: f7fd f9a1 bl 800e390 801104e: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8011050: e00a b.n 8011068 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8011052: f7fd f99d bl 800e390 8011056: 4602 mov r2, r0 8011058: 693b ldr r3, [r7, #16] 801105a: 1ad3 subs r3, r2, r3 801105c: f241 3288 movw r2, #5000 @ 0x1388 8011060: 4293 cmp r3, r2 8011062: d901 bls.n 8011068 { return HAL_TIMEOUT; 8011064: 2303 movs r3, #3 8011066: e12d b.n 80112c4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8011068: 4b49 ldr r3, [pc, #292] @ (8011190 ) 801106a: 6a1b ldr r3, [r3, #32] 801106c: f003 0302 and.w r3, r3, #2 8011070: 2b00 cmp r3, #0 8011072: d1ee bne.n 8011052 } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8011074: 7dfb ldrb r3, [r7, #23] 8011076: 2b01 cmp r3, #1 8011078: d105 bne.n 8011086 { __HAL_RCC_PWR_CLK_DISABLE(); 801107a: 4b45 ldr r3, [pc, #276] @ (8011190 ) 801107c: 69db ldr r3, [r3, #28] 801107e: 4a44 ldr r2, [pc, #272] @ (8011190 ) 8011080: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8011084: 61d3 str r3, [r2, #28] #if defined(RCC_CR_PLL2ON) /*-------------------------------- PLL2 Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) 8011086: 687b ldr r3, [r7, #4] 8011088: 6adb ldr r3, [r3, #44] @ 0x2c 801108a: 2b00 cmp r3, #0 801108c: f000 808c beq.w 80111a8 { /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 8011090: 4b3f ldr r3, [pc, #252] @ (8011190 ) 8011092: 685b ldr r3, [r3, #4] 8011094: f403 3380 and.w r3, r3, #65536 @ 0x10000 8011098: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 801109c: d10e bne.n 80110bc (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 801109e: 4b3c ldr r3, [pc, #240] @ (8011190 ) 80110a0: 685b ldr r3, [r3, #4] 80110a2: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 80110a6: 2b08 cmp r3, #8 80110a8: d108 bne.n 80110bc ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) 80110aa: 4b39 ldr r3, [pc, #228] @ (8011190 ) 80110ac: 6adb ldr r3, [r3, #44] @ 0x2c 80110ae: f403 3380 and.w r3, r3, #65536 @ 0x10000 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 80110b2: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80110b6: d101 bne.n 80110bc { return HAL_ERROR; 80110b8: 2301 movs r3, #1 80110ba: e103 b.n 80112c4 } else { if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) 80110bc: 687b ldr r3, [r7, #4] 80110be: 6adb ldr r3, [r3, #44] @ 0x2c 80110c0: 2b02 cmp r3, #2 80110c2: d14e bne.n 8011162 assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); /* Prediv2 can be written only when the PLLI2S is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 80110c4: 4b32 ldr r3, [pc, #200] @ (8011190 ) 80110c6: 681b ldr r3, [r3, #0] 80110c8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80110cc: 2b00 cmp r3, #0 80110ce: d009 beq.n 80110e4 (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) 80110d0: 4b2f ldr r3, [pc, #188] @ (8011190 ) 80110d2: 6adb ldr r3, [r3, #44] @ 0x2c 80110d4: f003 02f0 and.w r2, r3, #240 @ 0xf0 80110d8: 687b ldr r3, [r7, #4] 80110da: 6b5b ldr r3, [r3, #52] @ 0x34 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 80110dc: 429a cmp r2, r3 80110de: d001 beq.n 80110e4 { return HAL_ERROR; 80110e0: 2301 movs r3, #1 80110e2: e0ef b.n 80112c4 } /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 80110e4: 4b2c ldr r3, [pc, #176] @ (8011198 ) 80110e6: 2200 movs r2, #0 80110e8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80110ea: f7fd f951 bl 800e390 80110ee: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 80110f0: e008 b.n 8011104 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 80110f2: f7fd f94d bl 800e390 80110f6: 4602 mov r2, r0 80110f8: 693b ldr r3, [r7, #16] 80110fa: 1ad3 subs r3, r2, r3 80110fc: 2b64 cmp r3, #100 @ 0x64 80110fe: d901 bls.n 8011104 { return HAL_TIMEOUT; 8011100: 2303 movs r3, #3 8011102: e0df b.n 80112c4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8011104: 4b22 ldr r3, [pc, #136] @ (8011190 ) 8011106: 681b ldr r3, [r3, #0] 8011108: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 801110c: 2b00 cmp r3, #0 801110e: d1f0 bne.n 80110f2 } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); 8011110: 4b1f ldr r3, [pc, #124] @ (8011190 ) 8011112: 6adb ldr r3, [r3, #44] @ 0x2c 8011114: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8011118: 687b ldr r3, [r7, #4] 801111a: 6b5b ldr r3, [r3, #52] @ 0x34 801111c: 491c ldr r1, [pc, #112] @ (8011190 ) 801111e: 4313 orrs r3, r2 8011120: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); 8011122: 4b1b ldr r3, [pc, #108] @ (8011190 ) 8011124: 6adb ldr r3, [r3, #44] @ 0x2c 8011126: f423 6270 bic.w r2, r3, #3840 @ 0xf00 801112a: 687b ldr r3, [r7, #4] 801112c: 6b1b ldr r3, [r3, #48] @ 0x30 801112e: 4918 ldr r1, [pc, #96] @ (8011190 ) 8011130: 4313 orrs r3, r2 8011132: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); 8011134: 4b18 ldr r3, [pc, #96] @ (8011198 ) 8011136: 2201 movs r2, #1 8011138: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 801113a: f7fd f929 bl 800e390 801113e: 6138 str r0, [r7, #16] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 8011140: e008 b.n 8011154 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8011142: f7fd f925 bl 800e390 8011146: 4602 mov r2, r0 8011148: 693b ldr r3, [r7, #16] 801114a: 1ad3 subs r3, r2, r3 801114c: 2b64 cmp r3, #100 @ 0x64 801114e: d901 bls.n 8011154 { return HAL_TIMEOUT; 8011150: 2303 movs r3, #3 8011152: e0b7 b.n 80112c4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 8011154: 4b0e ldr r3, [pc, #56] @ (8011190 ) 8011156: 681b ldr r3, [r3, #0] 8011158: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 801115c: 2b00 cmp r3, #0 801115e: d0f0 beq.n 8011142 8011160: e022 b.n 80111a8 } } else { /* Set PREDIV1 source to HSE */ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); 8011162: 4b0b ldr r3, [pc, #44] @ (8011190 ) 8011164: 6adb ldr r3, [r3, #44] @ 0x2c 8011166: 4a0a ldr r2, [pc, #40] @ (8011190 ) 8011168: f423 3380 bic.w r3, r3, #65536 @ 0x10000 801116c: 62d3 str r3, [r2, #44] @ 0x2c /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 801116e: 4b0a ldr r3, [pc, #40] @ (8011198 ) 8011170: 2200 movs r2, #0 8011172: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8011174: f7fd f90c bl 800e390 8011178: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 801117a: e00f b.n 801119c { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 801117c: f7fd f908 bl 800e390 8011180: 4602 mov r2, r0 8011182: 693b ldr r3, [r7, #16] 8011184: 1ad3 subs r3, r2, r3 8011186: 2b64 cmp r3, #100 @ 0x64 8011188: d908 bls.n 801119c { return HAL_TIMEOUT; 801118a: 2303 movs r3, #3 801118c: e09a b.n 80112c4 801118e: bf00 nop 8011190: 40021000 .word 0x40021000 8011194: 40007000 .word 0x40007000 8011198: 42420068 .word 0x42420068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 801119c: 4b4b ldr r3, [pc, #300] @ (80112cc ) 801119e: 681b ldr r3, [r3, #0] 80111a0: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80111a4: 2b00 cmp r3, #0 80111a6: d1e9 bne.n 801117c #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 80111a8: 687b ldr r3, [r7, #4] 80111aa: 6a1b ldr r3, [r3, #32] 80111ac: 2b00 cmp r3, #0 80111ae: f000 8088 beq.w 80112c2 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 80111b2: 4b46 ldr r3, [pc, #280] @ (80112cc ) 80111b4: 685b ldr r3, [r3, #4] 80111b6: f003 030c and.w r3, r3, #12 80111ba: 2b08 cmp r3, #8 80111bc: d068 beq.n 8011290 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 80111be: 687b ldr r3, [r7, #4] 80111c0: 6a1b ldr r3, [r3, #32] 80111c2: 2b02 cmp r3, #2 80111c4: d14d bne.n 8011262 /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80111c6: 4b42 ldr r3, [pc, #264] @ (80112d0 ) 80111c8: 2200 movs r2, #0 80111ca: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80111cc: f7fd f8e0 bl 800e390 80111d0: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80111d2: e008 b.n 80111e6 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80111d4: f7fd f8dc bl 800e390 80111d8: 4602 mov r2, r0 80111da: 693b ldr r3, [r7, #16] 80111dc: 1ad3 subs r3, r2, r3 80111de: 2b02 cmp r3, #2 80111e0: d901 bls.n 80111e6 { return HAL_TIMEOUT; 80111e2: 2303 movs r3, #3 80111e4: e06e b.n 80112c4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80111e6: 4b39 ldr r3, [pc, #228] @ (80112cc ) 80111e8: 681b ldr r3, [r3, #0] 80111ea: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80111ee: 2b00 cmp r3, #0 80111f0: d1f0 bne.n 80111d4 } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 80111f2: 687b ldr r3, [r7, #4] 80111f4: 6a5b ldr r3, [r3, #36] @ 0x24 80111f6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80111fa: d10f bne.n 801121c assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); #if defined(RCC_CFGR2_PREDIV1SRC) assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); 80111fc: 4b33 ldr r3, [pc, #204] @ (80112cc ) 80111fe: 6ada ldr r2, [r3, #44] @ 0x2c 8011200: 687b ldr r3, [r7, #4] 8011202: 685b ldr r3, [r3, #4] 8011204: 4931 ldr r1, [pc, #196] @ (80112cc ) 8011206: 4313 orrs r3, r2 8011208: 62cb str r3, [r1, #44] @ 0x2c #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 801120a: 4b30 ldr r3, [pc, #192] @ (80112cc ) 801120c: 6adb ldr r3, [r3, #44] @ 0x2c 801120e: f023 020f bic.w r2, r3, #15 8011212: 687b ldr r3, [r7, #4] 8011214: 68db ldr r3, [r3, #12] 8011216: 492d ldr r1, [pc, #180] @ (80112cc ) 8011218: 4313 orrs r3, r2 801121a: 62cb str r3, [r1, #44] @ 0x2c } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 801121c: 4b2b ldr r3, [pc, #172] @ (80112cc ) 801121e: 685b ldr r3, [r3, #4] 8011220: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000 8011224: 687b ldr r3, [r7, #4] 8011226: 6a59 ldr r1, [r3, #36] @ 0x24 8011228: 687b ldr r3, [r7, #4] 801122a: 6a9b ldr r3, [r3, #40] @ 0x28 801122c: 430b orrs r3, r1 801122e: 4927 ldr r1, [pc, #156] @ (80112cc ) 8011230: 4313 orrs r3, r2 8011232: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8011234: 4b26 ldr r3, [pc, #152] @ (80112d0 ) 8011236: 2201 movs r2, #1 8011238: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 801123a: f7fd f8a9 bl 800e390 801123e: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8011240: e008 b.n 8011254 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8011242: f7fd f8a5 bl 800e390 8011246: 4602 mov r2, r0 8011248: 693b ldr r3, [r7, #16] 801124a: 1ad3 subs r3, r2, r3 801124c: 2b02 cmp r3, #2 801124e: d901 bls.n 8011254 { return HAL_TIMEOUT; 8011250: 2303 movs r3, #3 8011252: e037 b.n 80112c4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8011254: 4b1d ldr r3, [pc, #116] @ (80112cc ) 8011256: 681b ldr r3, [r3, #0] 8011258: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 801125c: 2b00 cmp r3, #0 801125e: d0f0 beq.n 8011242 8011260: e02f b.n 80112c2 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8011262: 4b1b ldr r3, [pc, #108] @ (80112d0 ) 8011264: 2200 movs r2, #0 8011266: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8011268: f7fd f892 bl 800e390 801126c: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 801126e: e008 b.n 8011282 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8011270: f7fd f88e bl 800e390 8011274: 4602 mov r2, r0 8011276: 693b ldr r3, [r7, #16] 8011278: 1ad3 subs r3, r2, r3 801127a: 2b02 cmp r3, #2 801127c: d901 bls.n 8011282 { return HAL_TIMEOUT; 801127e: 2303 movs r3, #3 8011280: e020 b.n 80112c4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8011282: 4b12 ldr r3, [pc, #72] @ (80112cc ) 8011284: 681b ldr r3, [r3, #0] 8011286: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 801128a: 2b00 cmp r3, #0 801128c: d1f0 bne.n 8011270 801128e: e018 b.n 80112c2 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8011290: 687b ldr r3, [r7, #4] 8011292: 6a1b ldr r3, [r3, #32] 8011294: 2b01 cmp r3, #1 8011296: d101 bne.n 801129c { return HAL_ERROR; 8011298: 2301 movs r3, #1 801129a: e013 b.n 80112c4 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 801129c: 4b0b ldr r3, [pc, #44] @ (80112cc ) 801129e: 685b ldr r3, [r3, #4] 80112a0: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80112a2: 68fb ldr r3, [r7, #12] 80112a4: f403 3280 and.w r2, r3, #65536 @ 0x10000 80112a8: 687b ldr r3, [r7, #4] 80112aa: 6a5b ldr r3, [r3, #36] @ 0x24 80112ac: 429a cmp r2, r3 80112ae: d106 bne.n 80112be (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 80112b0: 68fb ldr r3, [r7, #12] 80112b2: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 80112b6: 687b ldr r3, [r7, #4] 80112b8: 6a9b ldr r3, [r3, #40] @ 0x28 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80112ba: 429a cmp r2, r3 80112bc: d001 beq.n 80112c2 { return HAL_ERROR; 80112be: 2301 movs r3, #1 80112c0: e000 b.n 80112c4 } } } } return HAL_OK; 80112c2: 2300 movs r3, #0 } 80112c4: 4618 mov r0, r3 80112c6: 3718 adds r7, #24 80112c8: 46bd mov sp, r7 80112ca: bd80 pop {r7, pc} 80112cc: 40021000 .word 0x40021000 80112d0: 42420060 .word 0x42420060 080112d4 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 80112d4: b580 push {r7, lr} 80112d6: b084 sub sp, #16 80112d8: af00 add r7, sp, #0 80112da: 6078 str r0, [r7, #4] 80112dc: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 80112de: 687b ldr r3, [r7, #4] 80112e0: 2b00 cmp r3, #0 80112e2: d101 bne.n 80112e8 { return HAL_ERROR; 80112e4: 2301 movs r3, #1 80112e6: e0d0 b.n 801148a must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 80112e8: 4b6a ldr r3, [pc, #424] @ (8011494 ) 80112ea: 681b ldr r3, [r3, #0] 80112ec: f003 0307 and.w r3, r3, #7 80112f0: 683a ldr r2, [r7, #0] 80112f2: 429a cmp r2, r3 80112f4: d910 bls.n 8011318 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80112f6: 4b67 ldr r3, [pc, #412] @ (8011494 ) 80112f8: 681b ldr r3, [r3, #0] 80112fa: f023 0207 bic.w r2, r3, #7 80112fe: 4965 ldr r1, [pc, #404] @ (8011494 ) 8011300: 683b ldr r3, [r7, #0] 8011302: 4313 orrs r3, r2 8011304: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8011306: 4b63 ldr r3, [pc, #396] @ (8011494 ) 8011308: 681b ldr r3, [r3, #0] 801130a: f003 0307 and.w r3, r3, #7 801130e: 683a ldr r2, [r7, #0] 8011310: 429a cmp r2, r3 8011312: d001 beq.n 8011318 { return HAL_ERROR; 8011314: 2301 movs r3, #1 8011316: e0b8 b.n 801148a } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8011318: 687b ldr r3, [r7, #4] 801131a: 681b ldr r3, [r3, #0] 801131c: f003 0302 and.w r3, r3, #2 8011320: 2b00 cmp r3, #0 8011322: d020 beq.n 8011366 { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8011324: 687b ldr r3, [r7, #4] 8011326: 681b ldr r3, [r3, #0] 8011328: f003 0304 and.w r3, r3, #4 801132c: 2b00 cmp r3, #0 801132e: d005 beq.n 801133c { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8011330: 4b59 ldr r3, [pc, #356] @ (8011498 ) 8011332: 685b ldr r3, [r3, #4] 8011334: 4a58 ldr r2, [pc, #352] @ (8011498 ) 8011336: f443 63e0 orr.w r3, r3, #1792 @ 0x700 801133a: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 801133c: 687b ldr r3, [r7, #4] 801133e: 681b ldr r3, [r3, #0] 8011340: f003 0308 and.w r3, r3, #8 8011344: 2b00 cmp r3, #0 8011346: d005 beq.n 8011354 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8011348: 4b53 ldr r3, [pc, #332] @ (8011498 ) 801134a: 685b ldr r3, [r3, #4] 801134c: 4a52 ldr r2, [pc, #328] @ (8011498 ) 801134e: f443 5360 orr.w r3, r3, #14336 @ 0x3800 8011352: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8011354: 4b50 ldr r3, [pc, #320] @ (8011498 ) 8011356: 685b ldr r3, [r3, #4] 8011358: f023 02f0 bic.w r2, r3, #240 @ 0xf0 801135c: 687b ldr r3, [r7, #4] 801135e: 689b ldr r3, [r3, #8] 8011360: 494d ldr r1, [pc, #308] @ (8011498 ) 8011362: 4313 orrs r3, r2 8011364: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8011366: 687b ldr r3, [r7, #4] 8011368: 681b ldr r3, [r3, #0] 801136a: f003 0301 and.w r3, r3, #1 801136e: 2b00 cmp r3, #0 8011370: d040 beq.n 80113f4 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8011372: 687b ldr r3, [r7, #4] 8011374: 685b ldr r3, [r3, #4] 8011376: 2b01 cmp r3, #1 8011378: d107 bne.n 801138a { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 801137a: 4b47 ldr r3, [pc, #284] @ (8011498 ) 801137c: 681b ldr r3, [r3, #0] 801137e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8011382: 2b00 cmp r3, #0 8011384: d115 bne.n 80113b2 { return HAL_ERROR; 8011386: 2301 movs r3, #1 8011388: e07f b.n 801148a } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 801138a: 687b ldr r3, [r7, #4] 801138c: 685b ldr r3, [r3, #4] 801138e: 2b02 cmp r3, #2 8011390: d107 bne.n 80113a2 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8011392: 4b41 ldr r3, [pc, #260] @ (8011498 ) 8011394: 681b ldr r3, [r3, #0] 8011396: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 801139a: 2b00 cmp r3, #0 801139c: d109 bne.n 80113b2 { return HAL_ERROR; 801139e: 2301 movs r3, #1 80113a0: e073 b.n 801148a } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80113a2: 4b3d ldr r3, [pc, #244] @ (8011498 ) 80113a4: 681b ldr r3, [r3, #0] 80113a6: f003 0302 and.w r3, r3, #2 80113aa: 2b00 cmp r3, #0 80113ac: d101 bne.n 80113b2 { return HAL_ERROR; 80113ae: 2301 movs r3, #1 80113b0: e06b b.n 801148a } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 80113b2: 4b39 ldr r3, [pc, #228] @ (8011498 ) 80113b4: 685b ldr r3, [r3, #4] 80113b6: f023 0203 bic.w r2, r3, #3 80113ba: 687b ldr r3, [r7, #4] 80113bc: 685b ldr r3, [r3, #4] 80113be: 4936 ldr r1, [pc, #216] @ (8011498 ) 80113c0: 4313 orrs r3, r2 80113c2: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 80113c4: f7fc ffe4 bl 800e390 80113c8: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80113ca: e00a b.n 80113e2 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80113cc: f7fc ffe0 bl 800e390 80113d0: 4602 mov r2, r0 80113d2: 68fb ldr r3, [r7, #12] 80113d4: 1ad3 subs r3, r2, r3 80113d6: f241 3288 movw r2, #5000 @ 0x1388 80113da: 4293 cmp r3, r2 80113dc: d901 bls.n 80113e2 { return HAL_TIMEOUT; 80113de: 2303 movs r3, #3 80113e0: e053 b.n 801148a while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80113e2: 4b2d ldr r3, [pc, #180] @ (8011498 ) 80113e4: 685b ldr r3, [r3, #4] 80113e6: f003 020c and.w r2, r3, #12 80113ea: 687b ldr r3, [r7, #4] 80113ec: 685b ldr r3, [r3, #4] 80113ee: 009b lsls r3, r3, #2 80113f0: 429a cmp r2, r3 80113f2: d1eb bne.n 80113cc } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 80113f4: 4b27 ldr r3, [pc, #156] @ (8011494 ) 80113f6: 681b ldr r3, [r3, #0] 80113f8: f003 0307 and.w r3, r3, #7 80113fc: 683a ldr r2, [r7, #0] 80113fe: 429a cmp r2, r3 8011400: d210 bcs.n 8011424 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8011402: 4b24 ldr r3, [pc, #144] @ (8011494 ) 8011404: 681b ldr r3, [r3, #0] 8011406: f023 0207 bic.w r2, r3, #7 801140a: 4922 ldr r1, [pc, #136] @ (8011494 ) 801140c: 683b ldr r3, [r7, #0] 801140e: 4313 orrs r3, r2 8011410: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8011412: 4b20 ldr r3, [pc, #128] @ (8011494 ) 8011414: 681b ldr r3, [r3, #0] 8011416: f003 0307 and.w r3, r3, #7 801141a: 683a ldr r2, [r7, #0] 801141c: 429a cmp r2, r3 801141e: d001 beq.n 8011424 { return HAL_ERROR; 8011420: 2301 movs r3, #1 8011422: e032 b.n 801148a } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8011424: 687b ldr r3, [r7, #4] 8011426: 681b ldr r3, [r3, #0] 8011428: f003 0304 and.w r3, r3, #4 801142c: 2b00 cmp r3, #0 801142e: d008 beq.n 8011442 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8011430: 4b19 ldr r3, [pc, #100] @ (8011498 ) 8011432: 685b ldr r3, [r3, #4] 8011434: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8011438: 687b ldr r3, [r7, #4] 801143a: 68db ldr r3, [r3, #12] 801143c: 4916 ldr r1, [pc, #88] @ (8011498 ) 801143e: 4313 orrs r3, r2 8011440: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8011442: 687b ldr r3, [r7, #4] 8011444: 681b ldr r3, [r3, #0] 8011446: f003 0308 and.w r3, r3, #8 801144a: 2b00 cmp r3, #0 801144c: d009 beq.n 8011462 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 801144e: 4b12 ldr r3, [pc, #72] @ (8011498 ) 8011450: 685b ldr r3, [r3, #4] 8011452: f423 5260 bic.w r2, r3, #14336 @ 0x3800 8011456: 687b ldr r3, [r7, #4] 8011458: 691b ldr r3, [r3, #16] 801145a: 00db lsls r3, r3, #3 801145c: 490e ldr r1, [pc, #56] @ (8011498 ) 801145e: 4313 orrs r3, r2 8011460: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 8011462: f000 f821 bl 80114a8 8011466: 4602 mov r2, r0 8011468: 4b0b ldr r3, [pc, #44] @ (8011498 ) 801146a: 685b ldr r3, [r3, #4] 801146c: 091b lsrs r3, r3, #4 801146e: f003 030f and.w r3, r3, #15 8011472: 490a ldr r1, [pc, #40] @ (801149c ) 8011474: 5ccb ldrb r3, [r1, r3] 8011476: fa22 f303 lsr.w r3, r2, r3 801147a: 4a09 ldr r2, [pc, #36] @ (80114a0 ) 801147c: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 801147e: 4b09 ldr r3, [pc, #36] @ (80114a4 ) 8011480: 681b ldr r3, [r3, #0] 8011482: 4618 mov r0, r3 8011484: f7fc ff42 bl 800e30c return HAL_OK; 8011488: 2300 movs r3, #0 } 801148a: 4618 mov r0, r3 801148c: 3710 adds r7, #16 801148e: 46bd mov sp, r7 8011490: bd80 pop {r7, pc} 8011492: bf00 nop 8011494: 40022000 .word 0x40022000 8011498: 40021000 .word 0x40021000 801149c: 0801796c .word 0x0801796c 80114a0: 20000084 .word 0x20000084 80114a4: 20000088 .word 0x20000088 080114a8 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 80114a8: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 80114ac: b08e sub sp, #56 @ 0x38 80114ae: af00 add r7, sp, #0 #else static const uint8_t aPredivFactorTable[2U] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 80114b0: 2300 movs r3, #0 80114b2: 62fb str r3, [r7, #44] @ 0x2c 80114b4: 2300 movs r3, #0 80114b6: 62bb str r3, [r7, #40] @ 0x28 80114b8: 2300 movs r3, #0 80114ba: 637b str r3, [r7, #52] @ 0x34 80114bc: 2300 movs r3, #0 80114be: 627b str r3, [r7, #36] @ 0x24 uint32_t sysclockfreq = 0U; 80114c0: 2300 movs r3, #0 80114c2: 633b str r3, [r7, #48] @ 0x30 #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; 80114c4: 2300 movs r3, #0 80114c6: 623b str r3, [r7, #32] 80114c8: 2300 movs r3, #0 80114ca: 61fb str r3, [r7, #28] #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 80114cc: 4b4e ldr r3, [pc, #312] @ (8011608 ) 80114ce: 685b ldr r3, [r3, #4] 80114d0: 62fb str r3, [r7, #44] @ 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 80114d2: 6afb ldr r3, [r7, #44] @ 0x2c 80114d4: f003 030c and.w r3, r3, #12 80114d8: 2b04 cmp r3, #4 80114da: d002 beq.n 80114e2 80114dc: 2b08 cmp r3, #8 80114de: d003 beq.n 80114e8 80114e0: e089 b.n 80115f6 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 80114e2: 4b4a ldr r3, [pc, #296] @ (801160c ) 80114e4: 633b str r3, [r7, #48] @ 0x30 break; 80114e6: e089 b.n 80115fc } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 80114e8: 6afb ldr r3, [r7, #44] @ 0x2c 80114ea: 0c9b lsrs r3, r3, #18 80114ec: f003 020f and.w r2, r3, #15 80114f0: 4b47 ldr r3, [pc, #284] @ (8011610 ) 80114f2: 5c9b ldrb r3, [r3, r2] 80114f4: 627b str r3, [r7, #36] @ 0x24 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 80114f6: 6afb ldr r3, [r7, #44] @ 0x2c 80114f8: f403 3380 and.w r3, r3, #65536 @ 0x10000 80114fc: 2b00 cmp r3, #0 80114fe: d072 beq.n 80115e6 { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 8011500: 4b41 ldr r3, [pc, #260] @ (8011608 ) 8011502: 6adb ldr r3, [r3, #44] @ 0x2c 8011504: f003 020f and.w r2, r3, #15 8011508: 4b42 ldr r3, [pc, #264] @ (8011614 ) 801150a: 5c9b ldrb r3, [r3, r2] 801150c: 62bb str r3, [r7, #40] @ 0x28 #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /*RCC_CFGR2_PREDIV1*/ #if defined(RCC_CFGR2_PREDIV1SRC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 801150e: 4b3e ldr r3, [pc, #248] @ (8011608 ) 8011510: 6adb ldr r3, [r3, #44] @ 0x2c 8011512: f403 3380 and.w r3, r3, #65536 @ 0x10000 8011516: 2b00 cmp r3, #0 8011518: d053 beq.n 80115c2 { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 801151a: 4b3b ldr r3, [pc, #236] @ (8011608 ) 801151c: 6adb ldr r3, [r3, #44] @ 0x2c 801151e: 091b lsrs r3, r3, #4 8011520: f003 030f and.w r3, r3, #15 8011524: 3301 adds r3, #1 8011526: 623b str r3, [r7, #32] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 8011528: 4b37 ldr r3, [pc, #220] @ (8011608 ) 801152a: 6adb ldr r3, [r3, #44] @ 0x2c 801152c: 0a1b lsrs r3, r3, #8 801152e: f003 030f and.w r3, r3, #15 8011532: 3302 adds r3, #2 8011534: 61fb str r3, [r7, #28] pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); 8011536: 69fb ldr r3, [r7, #28] 8011538: 2200 movs r2, #0 801153a: 469a mov sl, r3 801153c: 4693 mov fp, r2 801153e: 6a7b ldr r3, [r7, #36] @ 0x24 8011540: 2200 movs r2, #0 8011542: 613b str r3, [r7, #16] 8011544: 617a str r2, [r7, #20] 8011546: 693b ldr r3, [r7, #16] 8011548: fb03 f20b mul.w r2, r3, fp 801154c: 697b ldr r3, [r7, #20] 801154e: fb0a f303 mul.w r3, sl, r3 8011552: 4413 add r3, r2 8011554: 693a ldr r2, [r7, #16] 8011556: fbaa 0102 umull r0, r1, sl, r2 801155a: 440b add r3, r1 801155c: 4619 mov r1, r3 801155e: 4b2b ldr r3, [pc, #172] @ (801160c ) 8011560: fb03 f201 mul.w r2, r3, r1 8011564: 2300 movs r3, #0 8011566: fb00 f303 mul.w r3, r0, r3 801156a: 4413 add r3, r2 801156c: 4a27 ldr r2, [pc, #156] @ (801160c ) 801156e: fba0 4502 umull r4, r5, r0, r2 8011572: 442b add r3, r5 8011574: 461d mov r5, r3 8011576: 6a3b ldr r3, [r7, #32] 8011578: 2200 movs r2, #0 801157a: 60bb str r3, [r7, #8] 801157c: 60fa str r2, [r7, #12] 801157e: 6abb ldr r3, [r7, #40] @ 0x28 8011580: 2200 movs r2, #0 8011582: 603b str r3, [r7, #0] 8011584: 607a str r2, [r7, #4] 8011586: e9d7 0102 ldrd r0, r1, [r7, #8] 801158a: 460b mov r3, r1 801158c: e9d7 ab00 ldrd sl, fp, [r7] 8011590: 4652 mov r2, sl 8011592: fb02 f203 mul.w r2, r2, r3 8011596: 465b mov r3, fp 8011598: 4684 mov ip, r0 801159a: fb0c f303 mul.w r3, ip, r3 801159e: 4413 add r3, r2 80115a0: 4602 mov r2, r0 80115a2: 4651 mov r1, sl 80115a4: fba2 8901 umull r8, r9, r2, r1 80115a8: 444b add r3, r9 80115aa: 4699 mov r9, r3 80115ac: 4642 mov r2, r8 80115ae: 464b mov r3, r9 80115b0: 4620 mov r0, r4 80115b2: 4629 mov r1, r5 80115b4: f7f7 fe1e bl 80091f4 <__aeabi_uldivmod> 80115b8: 4602 mov r2, r0 80115ba: 460b mov r3, r1 80115bc: 4613 mov r3, r2 80115be: 637b str r3, [r7, #52] @ 0x34 80115c0: e007 b.n 80115d2 } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 80115c2: 6a7b ldr r3, [r7, #36] @ 0x24 80115c4: 4a11 ldr r2, [pc, #68] @ (801160c ) 80115c6: fb03 f202 mul.w r2, r3, r2 80115ca: 6abb ldr r3, [r7, #40] @ 0x28 80115cc: fbb2 f3f3 udiv r3, r2, r3 80115d0: 637b str r3, [r7, #52] @ 0x34 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 80115d2: 4b0f ldr r3, [pc, #60] @ (8011610 ) 80115d4: 7b5b ldrb r3, [r3, #13] 80115d6: 461a mov r2, r3 80115d8: 6a7b ldr r3, [r7, #36] @ 0x24 80115da: 4293 cmp r3, r2 80115dc: d108 bne.n 80115f0 { pllclk = pllclk / 2; 80115de: 6b7b ldr r3, [r7, #52] @ 0x34 80115e0: 085b lsrs r3, r3, #1 80115e2: 637b str r3, [r7, #52] @ 0x34 80115e4: e004 b.n 80115f0 #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 80115e6: 6a7b ldr r3, [r7, #36] @ 0x24 80115e8: 4a0b ldr r2, [pc, #44] @ (8011618 ) 80115ea: fb02 f303 mul.w r3, r2, r3 80115ee: 637b str r3, [r7, #52] @ 0x34 } sysclockfreq = pllclk; 80115f0: 6b7b ldr r3, [r7, #52] @ 0x34 80115f2: 633b str r3, [r7, #48] @ 0x30 break; 80115f4: e002 b.n 80115fc } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 80115f6: 4b09 ldr r3, [pc, #36] @ (801161c ) 80115f8: 633b str r3, [r7, #48] @ 0x30 break; 80115fa: bf00 nop } } return sysclockfreq; 80115fc: 6b3b ldr r3, [r7, #48] @ 0x30 } 80115fe: 4618 mov r0, r3 8011600: 3738 adds r7, #56 @ 0x38 8011602: 46bd mov sp, r7 8011604: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8011608: 40021000 .word 0x40021000 801160c: 017d7840 .word 0x017d7840 8011610: 08017984 .word 0x08017984 8011614: 08017994 .word 0x08017994 8011618: 003d0900 .word 0x003d0900 801161c: 007a1200 .word 0x007a1200 08011620 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8011620: b480 push {r7} 8011622: af00 add r7, sp, #0 return SystemCoreClock; 8011624: 4b02 ldr r3, [pc, #8] @ (8011630 ) 8011626: 681b ldr r3, [r3, #0] } 8011628: 4618 mov r0, r3 801162a: 46bd mov sp, r7 801162c: bc80 pop {r7} 801162e: 4770 bx lr 8011630: 20000084 .word 0x20000084 08011634 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8011634: b580 push {r7, lr} 8011636: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8011638: f7ff fff2 bl 8011620 801163c: 4602 mov r2, r0 801163e: 4b05 ldr r3, [pc, #20] @ (8011654 ) 8011640: 685b ldr r3, [r3, #4] 8011642: 0a1b lsrs r3, r3, #8 8011644: f003 0307 and.w r3, r3, #7 8011648: 4903 ldr r1, [pc, #12] @ (8011658 ) 801164a: 5ccb ldrb r3, [r1, r3] 801164c: fa22 f303 lsr.w r3, r2, r3 } 8011650: 4618 mov r0, r3 8011652: bd80 pop {r7, pc} 8011654: 40021000 .word 0x40021000 8011658: 0801797c .word 0x0801797c 0801165c : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 801165c: b580 push {r7, lr} 801165e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8011660: f7ff ffde bl 8011620 8011664: 4602 mov r2, r0 8011666: 4b05 ldr r3, [pc, #20] @ (801167c ) 8011668: 685b ldr r3, [r3, #4] 801166a: 0adb lsrs r3, r3, #11 801166c: f003 0307 and.w r3, r3, #7 8011670: 4903 ldr r1, [pc, #12] @ (8011680 ) 8011672: 5ccb ldrb r3, [r1, r3] 8011674: fa22 f303 lsr.w r3, r2, r3 } 8011678: 4618 mov r0, r3 801167a: bd80 pop {r7, pc} 801167c: 40021000 .word 0x40021000 8011680: 0801797c .word 0x0801797c 08011684 : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 8011684: b480 push {r7} 8011686: b085 sub sp, #20 8011688: af00 add r7, sp, #0 801168a: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 801168c: 4b0a ldr r3, [pc, #40] @ (80116b8 ) 801168e: 681b ldr r3, [r3, #0] 8011690: 4a0a ldr r2, [pc, #40] @ (80116bc ) 8011692: fba2 2303 umull r2, r3, r2, r3 8011696: 0a5b lsrs r3, r3, #9 8011698: 687a ldr r2, [r7, #4] 801169a: fb02 f303 mul.w r3, r2, r3 801169e: 60fb str r3, [r7, #12] do { __NOP(); 80116a0: bf00 nop } while (Delay --); 80116a2: 68fb ldr r3, [r7, #12] 80116a4: 1e5a subs r2, r3, #1 80116a6: 60fa str r2, [r7, #12] 80116a8: 2b00 cmp r3, #0 80116aa: d1f9 bne.n 80116a0 } 80116ac: bf00 nop 80116ae: bf00 nop 80116b0: 3714 adds r7, #20 80116b2: 46bd mov sp, r7 80116b4: bc80 pop {r7} 80116b6: 4770 bx lr 80116b8: 20000084 .word 0x20000084 80116bc: 10624dd3 .word 0x10624dd3 080116c0 : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 80116c0: b580 push {r7, lr} 80116c2: b088 sub sp, #32 80116c4: af00 add r7, sp, #0 80116c6: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 80116c8: 2300 movs r3, #0 80116ca: 617b str r3, [r7, #20] 80116cc: 2300 movs r3, #0 80116ce: 613b str r3, [r7, #16] #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t pllactive = 0U; 80116d0: 2300 movs r3, #0 80116d2: 61fb str r3, [r7, #28] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 80116d4: 687b ldr r3, [r7, #4] 80116d6: 681b ldr r3, [r3, #0] 80116d8: f003 0301 and.w r3, r3, #1 80116dc: 2b00 cmp r3, #0 80116de: d07d beq.n 80117dc { FlagStatus pwrclkchanged = RESET; 80116e0: 2300 movs r3, #0 80116e2: 76fb strb r3, [r7, #27] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80116e4: 4b8b ldr r3, [pc, #556] @ (8011914 ) 80116e6: 69db ldr r3, [r3, #28] 80116e8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80116ec: 2b00 cmp r3, #0 80116ee: d10d bne.n 801170c { __HAL_RCC_PWR_CLK_ENABLE(); 80116f0: 4b88 ldr r3, [pc, #544] @ (8011914 ) 80116f2: 69db ldr r3, [r3, #28] 80116f4: 4a87 ldr r2, [pc, #540] @ (8011914 ) 80116f6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80116fa: 61d3 str r3, [r2, #28] 80116fc: 4b85 ldr r3, [pc, #532] @ (8011914 ) 80116fe: 69db ldr r3, [r3, #28] 8011700: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011704: 60fb str r3, [r7, #12] 8011706: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 8011708: 2301 movs r3, #1 801170a: 76fb strb r3, [r7, #27] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 801170c: 4b82 ldr r3, [pc, #520] @ (8011918 ) 801170e: 681b ldr r3, [r3, #0] 8011710: f403 7380 and.w r3, r3, #256 @ 0x100 8011714: 2b00 cmp r3, #0 8011716: d118 bne.n 801174a { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8011718: 4b7f ldr r3, [pc, #508] @ (8011918 ) 801171a: 681b ldr r3, [r3, #0] 801171c: 4a7e ldr r2, [pc, #504] @ (8011918 ) 801171e: f443 7380 orr.w r3, r3, #256 @ 0x100 8011722: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8011724: f7fc fe34 bl 800e390 8011728: 6178 str r0, [r7, #20] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 801172a: e008 b.n 801173e { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 801172c: f7fc fe30 bl 800e390 8011730: 4602 mov r2, r0 8011732: 697b ldr r3, [r7, #20] 8011734: 1ad3 subs r3, r2, r3 8011736: 2b64 cmp r3, #100 @ 0x64 8011738: d901 bls.n 801173e { return HAL_TIMEOUT; 801173a: 2303 movs r3, #3 801173c: e0e5 b.n 801190a while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 801173e: 4b76 ldr r3, [pc, #472] @ (8011918 ) 8011740: 681b ldr r3, [r3, #0] 8011742: f403 7380 and.w r3, r3, #256 @ 0x100 8011746: 2b00 cmp r3, #0 8011748: d0f0 beq.n 801172c } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 801174a: 4b72 ldr r3, [pc, #456] @ (8011914 ) 801174c: 6a1b ldr r3, [r3, #32] 801174e: f403 7340 and.w r3, r3, #768 @ 0x300 8011752: 613b str r3, [r7, #16] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8011754: 693b ldr r3, [r7, #16] 8011756: 2b00 cmp r3, #0 8011758: d02e beq.n 80117b8 801175a: 687b ldr r3, [r7, #4] 801175c: 685b ldr r3, [r3, #4] 801175e: f403 7340 and.w r3, r3, #768 @ 0x300 8011762: 693a ldr r2, [r7, #16] 8011764: 429a cmp r2, r3 8011766: d027 beq.n 80117b8 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8011768: 4b6a ldr r3, [pc, #424] @ (8011914 ) 801176a: 6a1b ldr r3, [r3, #32] 801176c: f423 7340 bic.w r3, r3, #768 @ 0x300 8011770: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8011772: 4b6a ldr r3, [pc, #424] @ (801191c ) 8011774: 2201 movs r2, #1 8011776: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8011778: 4b68 ldr r3, [pc, #416] @ (801191c ) 801177a: 2200 movs r2, #0 801177c: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 801177e: 4a65 ldr r2, [pc, #404] @ (8011914 ) 8011780: 693b ldr r3, [r7, #16] 8011782: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8011784: 693b ldr r3, [r7, #16] 8011786: f003 0301 and.w r3, r3, #1 801178a: 2b00 cmp r3, #0 801178c: d014 beq.n 80117b8 { /* Get Start Tick */ tickstart = HAL_GetTick(); 801178e: f7fc fdff bl 800e390 8011792: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8011794: e00a b.n 80117ac { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8011796: f7fc fdfb bl 800e390 801179a: 4602 mov r2, r0 801179c: 697b ldr r3, [r7, #20] 801179e: 1ad3 subs r3, r2, r3 80117a0: f241 3288 movw r2, #5000 @ 0x1388 80117a4: 4293 cmp r3, r2 80117a6: d901 bls.n 80117ac { return HAL_TIMEOUT; 80117a8: 2303 movs r3, #3 80117aa: e0ae b.n 801190a while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80117ac: 4b59 ldr r3, [pc, #356] @ (8011914 ) 80117ae: 6a1b ldr r3, [r3, #32] 80117b0: f003 0302 and.w r3, r3, #2 80117b4: 2b00 cmp r3, #0 80117b6: d0ee beq.n 8011796 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80117b8: 4b56 ldr r3, [pc, #344] @ (8011914 ) 80117ba: 6a1b ldr r3, [r3, #32] 80117bc: f423 7240 bic.w r2, r3, #768 @ 0x300 80117c0: 687b ldr r3, [r7, #4] 80117c2: 685b ldr r3, [r3, #4] 80117c4: 4953 ldr r1, [pc, #332] @ (8011914 ) 80117c6: 4313 orrs r3, r2 80117c8: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 80117ca: 7efb ldrb r3, [r7, #27] 80117cc: 2b01 cmp r3, #1 80117ce: d105 bne.n 80117dc { __HAL_RCC_PWR_CLK_DISABLE(); 80117d0: 4b50 ldr r3, [pc, #320] @ (8011914 ) 80117d2: 69db ldr r3, [r3, #28] 80117d4: 4a4f ldr r2, [pc, #316] @ (8011914 ) 80117d6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80117da: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 80117dc: 687b ldr r3, [r7, #4] 80117de: 681b ldr r3, [r3, #0] 80117e0: f003 0302 and.w r3, r3, #2 80117e4: 2b00 cmp r3, #0 80117e6: d008 beq.n 80117fa { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 80117e8: 4b4a ldr r3, [pc, #296] @ (8011914 ) 80117ea: 685b ldr r3, [r3, #4] 80117ec: f423 4240 bic.w r2, r3, #49152 @ 0xc000 80117f0: 687b ldr r3, [r7, #4] 80117f2: 689b ldr r3, [r3, #8] 80117f4: 4947 ldr r1, [pc, #284] @ (8011914 ) 80117f6: 4313 orrs r3, r2 80117f8: 604b str r3, [r1, #4] } #if defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ I2S2 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) 80117fa: 687b ldr r3, [r7, #4] 80117fc: 681b ldr r3, [r3, #0] 80117fe: f003 0304 and.w r3, r3, #4 8011802: 2b00 cmp r3, #0 8011804: d008 beq.n 8011818 { /* Check the parameters */ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); /* Configure the I2S2 clock source */ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); 8011806: 4b43 ldr r3, [pc, #268] @ (8011914 ) 8011808: 6adb ldr r3, [r3, #44] @ 0x2c 801180a: f423 3200 bic.w r2, r3, #131072 @ 0x20000 801180e: 687b ldr r3, [r7, #4] 8011810: 68db ldr r3, [r3, #12] 8011812: 4940 ldr r1, [pc, #256] @ (8011914 ) 8011814: 4313 orrs r3, r2 8011816: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ I2S3 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) 8011818: 687b ldr r3, [r7, #4] 801181a: 681b ldr r3, [r3, #0] 801181c: f003 0308 and.w r3, r3, #8 8011820: 2b00 cmp r3, #0 8011822: d008 beq.n 8011836 { /* Check the parameters */ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); /* Configure the I2S3 clock source */ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); 8011824: 4b3b ldr r3, [pc, #236] @ (8011914 ) 8011826: 6adb ldr r3, [r3, #44] @ 0x2c 8011828: f423 2280 bic.w r2, r3, #262144 @ 0x40000 801182c: 687b ldr r3, [r7, #4] 801182e: 691b ldr r3, [r3, #16] 8011830: 4938 ldr r1, [pc, #224] @ (8011914 ) 8011832: 4313 orrs r3, r2 8011834: 62cb str r3, [r1, #44] @ 0x2c } /*------------------------------ PLL I2S Configuration ----------------------*/ /* Check that PLLI2S need to be enabled */ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) 8011836: 4b37 ldr r3, [pc, #220] @ (8011914 ) 8011838: 6adb ldr r3, [r3, #44] @ 0x2c 801183a: f403 3300 and.w r3, r3, #131072 @ 0x20000 801183e: 2b00 cmp r3, #0 8011840: d105 bne.n 801184e 8011842: 4b34 ldr r3, [pc, #208] @ (8011914 ) 8011844: 6adb ldr r3, [r3, #44] @ 0x2c 8011846: f403 2380 and.w r3, r3, #262144 @ 0x40000 801184a: 2b00 cmp r3, #0 801184c: d001 beq.n 8011852 { /* Update flag to indicate that PLL I2S should be active */ pllactive = 1; 801184e: 2301 movs r3, #1 8011850: 61fb str r3, [r7, #28] } /* Check if PLL I2S need to be enabled */ if (pllactive == 1) 8011852: 69fb ldr r3, [r7, #28] 8011854: 2b01 cmp r3, #1 8011856: d148 bne.n 80118ea { /* Enable PLL I2S only if not active */ if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) 8011858: 4b2e ldr r3, [pc, #184] @ (8011914 ) 801185a: 681b ldr r3, [r3, #0] 801185c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011860: 2b00 cmp r3, #0 8011862: d138 bne.n 80118d6 assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); /* Prediv2 can be written only when the PLL2 is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 8011864: 4b2b ldr r3, [pc, #172] @ (8011914 ) 8011866: 681b ldr r3, [r3, #0] 8011868: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 801186c: 2b00 cmp r3, #0 801186e: d009 beq.n 8011884 (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) 8011870: 4b28 ldr r3, [pc, #160] @ (8011914 ) 8011872: 6adb ldr r3, [r3, #44] @ 0x2c 8011874: f003 02f0 and.w r2, r3, #240 @ 0xf0 8011878: 687b ldr r3, [r7, #4] 801187a: 699b ldr r3, [r3, #24] if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 801187c: 429a cmp r2, r3 801187e: d001 beq.n 8011884 { return HAL_ERROR; 8011880: 2301 movs r3, #1 8011882: e042 b.n 801190a } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); 8011884: 4b23 ldr r3, [pc, #140] @ (8011914 ) 8011886: 6adb ldr r3, [r3, #44] @ 0x2c 8011888: f023 02f0 bic.w r2, r3, #240 @ 0xf0 801188c: 687b ldr r3, [r7, #4] 801188e: 699b ldr r3, [r3, #24] 8011890: 4920 ldr r1, [pc, #128] @ (8011914 ) 8011892: 4313 orrs r3, r2 8011894: 62cb str r3, [r1, #44] @ 0x2c /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); 8011896: 4b1f ldr r3, [pc, #124] @ (8011914 ) 8011898: 6adb ldr r3, [r3, #44] @ 0x2c 801189a: f423 4270 bic.w r2, r3, #61440 @ 0xf000 801189e: 687b ldr r3, [r7, #4] 80118a0: 695b ldr r3, [r3, #20] 80118a2: 491c ldr r1, [pc, #112] @ (8011914 ) 80118a4: 4313 orrs r3, r2 80118a6: 62cb str r3, [r1, #44] @ 0x2c /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); 80118a8: 4b1d ldr r3, [pc, #116] @ (8011920 ) 80118aa: 2201 movs r2, #1 80118ac: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80118ae: f7fc fd6f bl 800e390 80118b2: 6178 str r0, [r7, #20] /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 80118b4: e008 b.n 80118c8 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 80118b6: f7fc fd6b bl 800e390 80118ba: 4602 mov r2, r0 80118bc: 697b ldr r3, [r7, #20] 80118be: 1ad3 subs r3, r2, r3 80118c0: 2b64 cmp r3, #100 @ 0x64 80118c2: d901 bls.n 80118c8 { return HAL_TIMEOUT; 80118c4: 2303 movs r3, #3 80118c6: e020 b.n 801190a while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 80118c8: 4b12 ldr r3, [pc, #72] @ (8011914 ) 80118ca: 681b ldr r3, [r3, #0] 80118cc: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80118d0: 2b00 cmp r3, #0 80118d2: d0f0 beq.n 80118b6 80118d4: e009 b.n 80118ea } } else { /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) 80118d6: 4b0f ldr r3, [pc, #60] @ (8011914 ) 80118d8: 6adb ldr r3, [r3, #44] @ 0x2c 80118da: f403 4270 and.w r2, r3, #61440 @ 0xf000 80118de: 687b ldr r3, [r7, #4] 80118e0: 695b ldr r3, [r3, #20] 80118e2: 429a cmp r2, r3 80118e4: d001 beq.n 80118ea { return HAL_ERROR; 80118e6: 2301 movs r3, #1 80118e8: e00f b.n 801190a #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 80118ea: 687b ldr r3, [r7, #4] 80118ec: 681b ldr r3, [r3, #0] 80118ee: f003 0310 and.w r3, r3, #16 80118f2: 2b00 cmp r3, #0 80118f4: d008 beq.n 8011908 { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 80118f6: 4b07 ldr r3, [pc, #28] @ (8011914 ) 80118f8: 685b ldr r3, [r3, #4] 80118fa: f423 0280 bic.w r2, r3, #4194304 @ 0x400000 80118fe: 687b ldr r3, [r7, #4] 8011900: 69db ldr r3, [r3, #28] 8011902: 4904 ldr r1, [pc, #16] @ (8011914 ) 8011904: 4313 orrs r3, r2 8011906: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 8011908: 2300 movs r3, #0 } 801190a: 4618 mov r0, r3 801190c: 3720 adds r7, #32 801190e: 46bd mov sp, r7 8011910: bd80 pop {r7, pc} 8011912: bf00 nop 8011914: 40021000 .word 0x40021000 8011918: 40007000 .word 0x40007000 801191c: 42420440 .word 0x42420440 8011920: 42420070 .word 0x42420070 08011924 : * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 8011924: b580 push {r7, lr} 8011926: b08a sub sp, #40 @ 0x28 8011928: af00 add r7, sp, #0 801192a: 6078 str r0, [r7, #4] #if defined(STM32F105xC) || defined(STM32F107xC) static const uint8_t aPLLMULFactorTable[14U] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; 801192c: 2300 movs r3, #0 801192e: 61fb str r3, [r7, #28] 8011930: 2300 movs r3, #0 8011932: 627b str r3, [r7, #36] @ 0x24 8011934: 2300 movs r3, #0 8011936: 61bb str r3, [r7, #24] uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; 8011938: 2300 movs r3, #0 801193a: 617b str r3, [r7, #20] 801193c: 2300 movs r3, #0 801193e: 613b str r3, [r7, #16] 8011940: 2300 movs r3, #0 8011942: 60fb str r3, [r7, #12] static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; static const uint8_t aPredivFactorTable[2U] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 8011944: 2300 movs r3, #0 8011946: 60bb str r3, [r7, #8] 8011948: 2300 movs r3, #0 801194a: 623b str r3, [r7, #32] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 801194c: 687b ldr r3, [r7, #4] 801194e: 3b01 subs r3, #1 8011950: 2b0f cmp r3, #15 8011952: f200 811d bhi.w 8011b90 8011956: a201 add r2, pc, #4 @ (adr r2, 801195c ) 8011958: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801195c: 08011b11 .word 0x08011b11 8011960: 08011b75 .word 0x08011b75 8011964: 08011b91 .word 0x08011b91 8011968: 08011a6f .word 0x08011a6f 801196c: 08011b91 .word 0x08011b91 8011970: 08011b91 .word 0x08011b91 8011974: 08011b91 .word 0x08011b91 8011978: 08011ac1 .word 0x08011ac1 801197c: 08011b91 .word 0x08011b91 8011980: 08011b91 .word 0x08011b91 8011984: 08011b91 .word 0x08011b91 8011988: 08011b91 .word 0x08011b91 801198c: 08011b91 .word 0x08011b91 8011990: 08011b91 .word 0x08011b91 8011994: 08011b91 .word 0x08011b91 8011998: 0801199d .word 0x0801199d || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) case RCC_PERIPHCLK_USB: { /* Get RCC configuration ------------------------------------------------------*/ temp_reg = RCC->CFGR; 801199c: 4b83 ldr r3, [pc, #524] @ (8011bac ) 801199e: 685b ldr r3, [r3, #4] 80119a0: 60bb str r3, [r7, #8] /* Check if PLL is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) 80119a2: 4b82 ldr r3, [pc, #520] @ (8011bac ) 80119a4: 681b ldr r3, [r3, #0] 80119a6: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80119aa: 2b00 cmp r3, #0 80119ac: f000 80f2 beq.w 8011b94 { pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 80119b0: 68bb ldr r3, [r7, #8] 80119b2: 0c9b lsrs r3, r3, #18 80119b4: f003 030f and.w r3, r3, #15 80119b8: 4a7d ldr r2, [pc, #500] @ (8011bb0 ) 80119ba: 5cd3 ldrb r3, [r2, r3] 80119bc: 61bb str r3, [r7, #24] if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 80119be: 68bb ldr r3, [r7, #8] 80119c0: f403 3380 and.w r3, r3, #65536 @ 0x10000 80119c4: 2b00 cmp r3, #0 80119c6: d03b beq.n 8011a40 { #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ || defined(STM32F100xE) prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 80119c8: 4b78 ldr r3, [pc, #480] @ (8011bac ) 80119ca: 6adb ldr r3, [r3, #44] @ 0x2c 80119cc: f003 030f and.w r3, r3, #15 80119d0: 4a78 ldr r2, [pc, #480] @ (8011bb4 ) 80119d2: 5cd3 ldrb r3, [r2, r3] 80119d4: 61fb str r3, [r7, #28] #else prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 80119d6: 4b75 ldr r3, [pc, #468] @ (8011bac ) 80119d8: 6adb ldr r3, [r3, #44] @ 0x2c 80119da: f403 3380 and.w r3, r3, #65536 @ 0x10000 80119de: 2b00 cmp r3, #0 80119e0: d01c beq.n 8011a1c { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 80119e2: 4b72 ldr r3, [pc, #456] @ (8011bac ) 80119e4: 6adb ldr r3, [r3, #44] @ 0x2c 80119e6: 091b lsrs r3, r3, #4 80119e8: f003 030f and.w r3, r3, #15 80119ec: 3301 adds r3, #1 80119ee: 60fb str r3, [r7, #12] pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 80119f0: 4b6e ldr r3, [pc, #440] @ (8011bac ) 80119f2: 6adb ldr r3, [r3, #44] @ 0x2c 80119f4: 0a1b lsrs r3, r3, #8 80119f6: f003 030f and.w r3, r3, #15 80119fa: 3302 adds r3, #2 80119fc: 617b str r3, [r7, #20] pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); 80119fe: 4a6e ldr r2, [pc, #440] @ (8011bb8 ) 8011a00: 68fb ldr r3, [r7, #12] 8011a02: fbb2 f3f3 udiv r3, r2, r3 8011a06: 697a ldr r2, [r7, #20] 8011a08: fb03 f202 mul.w r2, r3, r2 8011a0c: 69fb ldr r3, [r7, #28] 8011a0e: fbb2 f2f3 udiv r2, r2, r3 8011a12: 69bb ldr r3, [r7, #24] 8011a14: fb02 f303 mul.w r3, r2, r3 8011a18: 627b str r3, [r7, #36] @ 0x24 8011a1a: e007 b.n 8011a2c } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); 8011a1c: 4a66 ldr r2, [pc, #408] @ (8011bb8 ) 8011a1e: 69fb ldr r3, [r7, #28] 8011a20: fbb2 f2f3 udiv r2, r2, r3 8011a24: 69bb ldr r3, [r7, #24] 8011a26: fb02 f303 mul.w r3, r2, r3 8011a2a: 627b str r3, [r7, #36] @ 0x24 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 8011a2c: 4b60 ldr r3, [pc, #384] @ (8011bb0 ) 8011a2e: 7b5b ldrb r3, [r3, #13] 8011a30: 461a mov r2, r3 8011a32: 69bb ldr r3, [r7, #24] 8011a34: 4293 cmp r3, r2 8011a36: d108 bne.n 8011a4a { pllclk = pllclk / 2; 8011a38: 6a7b ldr r3, [r7, #36] @ 0x24 8011a3a: 085b lsrs r3, r3, #1 8011a3c: 627b str r3, [r7, #36] @ 0x24 8011a3e: e004 b.n 8011a4a #endif /* STM32F105xC || STM32F107xC */ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8011a40: 69bb ldr r3, [r7, #24] 8011a42: 4a5e ldr r2, [pc, #376] @ (8011bbc ) 8011a44: fb02 f303 mul.w r3, r2, r3 8011a48: 627b str r3, [r7, #36] @ 0x24 } /* Calcul of the USB frequency*/ #if defined(STM32F105xC) || defined(STM32F107xC) /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) 8011a4a: 4b58 ldr r3, [pc, #352] @ (8011bac ) 8011a4c: 685b ldr r3, [r3, #4] 8011a4e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8011a52: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8011a56: d102 bne.n 8011a5e { /* Prescaler of 2 selected for USB */ frequency = pllclk; 8011a58: 6a7b ldr r3, [r7, #36] @ 0x24 8011a5a: 623b str r3, [r7, #32] /* Prescaler of 1.5 selected for USB */ frequency = (pllclk * 2) / 3; } #endif } break; 8011a5c: e09a b.n 8011b94 frequency = (2 * pllclk) / 3; 8011a5e: 6a7b ldr r3, [r7, #36] @ 0x24 8011a60: 005b lsls r3, r3, #1 8011a62: 4a57 ldr r2, [pc, #348] @ (8011bc0 ) 8011a64: fba2 2303 umull r2, r3, r2, r3 8011a68: 085b lsrs r3, r3, #1 8011a6a: 623b str r3, [r7, #32] break; 8011a6c: e092 b.n 8011b94 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) 8011a6e: 4b4f ldr r3, [pc, #316] @ (8011bac ) 8011a70: 6adb ldr r3, [r3, #44] @ 0x2c 8011a72: f403 3300 and.w r3, r3, #131072 @ 0x20000 8011a76: 2b00 cmp r3, #0 8011a78: d103 bne.n 8011a82 { /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); 8011a7a: f7ff fd15 bl 80114a8 8011a7e: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 8011a80: e08a b.n 8011b98 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8011a82: 4b4a ldr r3, [pc, #296] @ (8011bac ) 8011a84: 681b ldr r3, [r3, #0] 8011a86: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011a8a: 2b00 cmp r3, #0 8011a8c: f000 8084 beq.w 8011b98 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8011a90: 4b46 ldr r3, [pc, #280] @ (8011bac ) 8011a92: 6adb ldr r3, [r3, #44] @ 0x2c 8011a94: 091b lsrs r3, r3, #4 8011a96: f003 030f and.w r3, r3, #15 8011a9a: 3301 adds r3, #1 8011a9c: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 8011a9e: 4b43 ldr r3, [pc, #268] @ (8011bac ) 8011aa0: 6adb ldr r3, [r3, #44] @ 0x2c 8011aa2: 0b1b lsrs r3, r3, #12 8011aa4: f003 030f and.w r3, r3, #15 8011aa8: 3302 adds r3, #2 8011aaa: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 8011aac: 4a42 ldr r2, [pc, #264] @ (8011bb8 ) 8011aae: 68fb ldr r3, [r7, #12] 8011ab0: fbb2 f3f3 udiv r3, r2, r3 8011ab4: 693a ldr r2, [r7, #16] 8011ab6: fb02 f303 mul.w r3, r2, r3 8011aba: 005b lsls r3, r3, #1 8011abc: 623b str r3, [r7, #32] break; 8011abe: e06b b.n 8011b98 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) 8011ac0: 4b3a ldr r3, [pc, #232] @ (8011bac ) 8011ac2: 6adb ldr r3, [r3, #44] @ 0x2c 8011ac4: f403 2380 and.w r3, r3, #262144 @ 0x40000 8011ac8: 2b00 cmp r3, #0 8011aca: d103 bne.n 8011ad4 { /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); 8011acc: f7ff fcec bl 80114a8 8011ad0: 6238 str r0, [r7, #32] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 8011ad2: e063 b.n 8011b9c if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8011ad4: 4b35 ldr r3, [pc, #212] @ (8011bac ) 8011ad6: 681b ldr r3, [r3, #0] 8011ad8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011adc: 2b00 cmp r3, #0 8011ade: d05d beq.n 8011b9c prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8011ae0: 4b32 ldr r3, [pc, #200] @ (8011bac ) 8011ae2: 6adb ldr r3, [r3, #44] @ 0x2c 8011ae4: 091b lsrs r3, r3, #4 8011ae6: f003 030f and.w r3, r3, #15 8011aea: 3301 adds r3, #1 8011aec: 60fb str r3, [r7, #12] pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 8011aee: 4b2f ldr r3, [pc, #188] @ (8011bac ) 8011af0: 6adb ldr r3, [r3, #44] @ 0x2c 8011af2: 0b1b lsrs r3, r3, #12 8011af4: f003 030f and.w r3, r3, #15 8011af8: 3302 adds r3, #2 8011afa: 613b str r3, [r7, #16] frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 8011afc: 4a2e ldr r2, [pc, #184] @ (8011bb8 ) 8011afe: 68fb ldr r3, [r7, #12] 8011b00: fbb2 f3f3 udiv r3, r2, r3 8011b04: 693a ldr r2, [r7, #16] 8011b06: fb02 f303 mul.w r3, r2, r3 8011b0a: 005b lsls r3, r3, #1 8011b0c: 623b str r3, [r7, #32] break; 8011b0e: e045 b.n 8011b9c } #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ case RCC_PERIPHCLK_RTC: { /* Get RCC BDCR configuration ------------------------------------------------------*/ temp_reg = RCC->BDCR; 8011b10: 4b26 ldr r3, [pc, #152] @ (8011bac ) 8011b12: 6a1b ldr r3, [r3, #32] 8011b14: 60bb str r3, [r7, #8] /* Check if LSE is ready if RTC clock selection is LSE */ if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 8011b16: 68bb ldr r3, [r7, #8] 8011b18: f403 7340 and.w r3, r3, #768 @ 0x300 8011b1c: f5b3 7f80 cmp.w r3, #256 @ 0x100 8011b20: d108 bne.n 8011b34 8011b22: 68bb ldr r3, [r7, #8] 8011b24: f003 0302 and.w r3, r3, #2 8011b28: 2b00 cmp r3, #0 8011b2a: d003 beq.n 8011b34 { frequency = LSE_VALUE; 8011b2c: f44f 4300 mov.w r3, #32768 @ 0x8000 8011b30: 623b str r3, [r7, #32] 8011b32: e01e b.n 8011b72 } /* Check if LSI is ready if RTC clock selection is LSI */ else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 8011b34: 68bb ldr r3, [r7, #8] 8011b36: f403 7340 and.w r3, r3, #768 @ 0x300 8011b3a: f5b3 7f00 cmp.w r3, #512 @ 0x200 8011b3e: d109 bne.n 8011b54 8011b40: 4b1a ldr r3, [pc, #104] @ (8011bac ) 8011b42: 6a5b ldr r3, [r3, #36] @ 0x24 8011b44: f003 0302 and.w r3, r3, #2 8011b48: 2b00 cmp r3, #0 8011b4a: d003 beq.n 8011b54 { frequency = LSI_VALUE; 8011b4c: f649 4340 movw r3, #40000 @ 0x9c40 8011b50: 623b str r3, [r7, #32] 8011b52: e00e b.n 8011b72 } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 8011b54: 68bb ldr r3, [r7, #8] 8011b56: f403 7340 and.w r3, r3, #768 @ 0x300 8011b5a: f5b3 7f40 cmp.w r3, #768 @ 0x300 8011b5e: d11f bne.n 8011ba0 8011b60: 4b12 ldr r3, [pc, #72] @ (8011bac ) 8011b62: 681b ldr r3, [r3, #0] 8011b64: f403 3300 and.w r3, r3, #131072 @ 0x20000 8011b68: 2b00 cmp r3, #0 8011b6a: d019 beq.n 8011ba0 { frequency = HSE_VALUE / 128U; 8011b6c: 4b15 ldr r3, [pc, #84] @ (8011bc4 ) 8011b6e: 623b str r3, [r7, #32] /* Clock not enabled for RTC*/ else { /* nothing to do: frequency already initialized to 0U */ } break; 8011b70: e016 b.n 8011ba0 8011b72: e015 b.n 8011ba0 } case RCC_PERIPHCLK_ADC: { frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 8011b74: f7ff fd72 bl 801165c 8011b78: 4602 mov r2, r0 8011b7a: 4b0c ldr r3, [pc, #48] @ (8011bac ) 8011b7c: 685b ldr r3, [r3, #4] 8011b7e: 0b9b lsrs r3, r3, #14 8011b80: f003 0303 and.w r3, r3, #3 8011b84: 3301 adds r3, #1 8011b86: 005b lsls r3, r3, #1 8011b88: fbb2 f3f3 udiv r3, r2, r3 8011b8c: 623b str r3, [r7, #32] break; 8011b8e: e008 b.n 8011ba2 } default: { break; 8011b90: bf00 nop 8011b92: e006 b.n 8011ba2 break; 8011b94: bf00 nop 8011b96: e004 b.n 8011ba2 break; 8011b98: bf00 nop 8011b9a: e002 b.n 8011ba2 break; 8011b9c: bf00 nop 8011b9e: e000 b.n 8011ba2 break; 8011ba0: bf00 nop } } return (frequency); 8011ba2: 6a3b ldr r3, [r7, #32] } 8011ba4: 4618 mov r0, r3 8011ba6: 3728 adds r7, #40 @ 0x28 8011ba8: 46bd mov sp, r7 8011baa: bd80 pop {r7, pc} 8011bac: 40021000 .word 0x40021000 8011bb0: 080179a4 .word 0x080179a4 8011bb4: 080179b4 .word 0x080179b4 8011bb8: 017d7840 .word 0x017d7840 8011bbc: 003d0900 .word 0x003d0900 8011bc0: aaaaaaab .word 0xaaaaaaab 8011bc4: 0002faf0 .word 0x0002faf0 08011bc8 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { 8011bc8: b580 push {r7, lr} 8011bca: b084 sub sp, #16 8011bcc: af00 add r7, sp, #0 8011bce: 6078 str r0, [r7, #4] uint32_t prescaler = 0U; 8011bd0: 2300 movs r3, #0 8011bd2: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8011bd4: 687b ldr r3, [r7, #4] 8011bd6: 2b00 cmp r3, #0 8011bd8: d101 bne.n 8011bde { return HAL_ERROR; 8011bda: 2301 movs r3, #1 8011bdc: e07a b.n 8011cd4 { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } #else if (hrtc->State == HAL_RTC_STATE_RESET) 8011bde: 687b ldr r3, [r7, #4] 8011be0: 7c5b ldrb r3, [r3, #17] 8011be2: b2db uxtb r3, r3 8011be4: 2b00 cmp r3, #0 8011be6: d105 bne.n 8011bf4 { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; 8011be8: 687b ldr r3, [r7, #4] 8011bea: 2200 movs r2, #0 8011bec: 741a strb r2, [r3, #16] /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); 8011bee: 6878 ldr r0, [r7, #4] 8011bf0: f7f9 ffb6 bl 800bb60 } #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; 8011bf4: 687b ldr r3, [r7, #4] 8011bf6: 2202 movs r2, #2 8011bf8: 745a strb r2, [r3, #17] /* Waiting for synchro */ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 8011bfa: 6878 ldr r0, [r7, #4] 8011bfc: f000 f870 bl 8011ce0 8011c00: 4603 mov r3, r0 8011c02: 2b00 cmp r3, #0 8011c04: d004 beq.n 8011c10 { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8011c06: 687b ldr r3, [r7, #4] 8011c08: 2204 movs r2, #4 8011c0a: 745a strb r2, [r3, #17] return HAL_ERROR; 8011c0c: 2301 movs r3, #1 8011c0e: e061 b.n 8011cd4 } /* Set Initialization mode */ if (RTC_EnterInitMode(hrtc) != HAL_OK) 8011c10: 6878 ldr r0, [r7, #4] 8011c12: f000 f892 bl 8011d3a 8011c16: 4603 mov r3, r0 8011c18: 2b00 cmp r3, #0 8011c1a: d004 beq.n 8011c26 { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8011c1c: 687b ldr r3, [r7, #4] 8011c1e: 2204 movs r2, #4 8011c20: 745a strb r2, [r3, #17] return HAL_ERROR; 8011c22: 2301 movs r3, #1 8011c24: e056 b.n 8011cd4 } else { /* Clear Flags Bits */ CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC)); 8011c26: 687b ldr r3, [r7, #4] 8011c28: 681b ldr r3, [r3, #0] 8011c2a: 685a ldr r2, [r3, #4] 8011c2c: 687b ldr r3, [r7, #4] 8011c2e: 681b ldr r3, [r3, #0] 8011c30: f022 0207 bic.w r2, r2, #7 8011c34: 605a str r2, [r3, #4] if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE) 8011c36: 687b ldr r3, [r7, #4] 8011c38: 689b ldr r3, [r3, #8] 8011c3a: 2b00 cmp r3, #0 8011c3c: d005 beq.n 8011c4a { /* Disable the selected Tamper pin */ CLEAR_BIT(BKP->CR, BKP_CR_TPE); 8011c3e: 4b27 ldr r3, [pc, #156] @ (8011cdc ) 8011c40: 6b1b ldr r3, [r3, #48] @ 0x30 8011c42: 4a26 ldr r2, [pc, #152] @ (8011cdc ) 8011c44: f023 0301 bic.w r3, r3, #1 8011c48: 6313 str r3, [r2, #48] @ 0x30 } /* Set the signal which will be routed to RTC Tamper pin*/ MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut); 8011c4a: 4b24 ldr r3, [pc, #144] @ (8011cdc ) 8011c4c: 6adb ldr r3, [r3, #44] @ 0x2c 8011c4e: f423 7260 bic.w r2, r3, #896 @ 0x380 8011c52: 687b ldr r3, [r7, #4] 8011c54: 689b ldr r3, [r3, #8] 8011c56: 4921 ldr r1, [pc, #132] @ (8011cdc ) 8011c58: 4313 orrs r3, r2 8011c5a: 62cb str r3, [r1, #44] @ 0x2c if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND) 8011c5c: 687b ldr r3, [r7, #4] 8011c5e: 685b ldr r3, [r3, #4] 8011c60: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8011c64: d003 beq.n 8011c6e { /* RTC Prescaler provided directly by end-user*/ prescaler = hrtc->Init.AsynchPrediv; 8011c66: 687b ldr r3, [r7, #4] 8011c68: 685b ldr r3, [r3, #4] 8011c6a: 60fb str r3, [r7, #12] 8011c6c: e00e b.n 8011c8c } else { /* RTC Prescaler will be automatically calculated to get 1 second timebase */ /* Get the RTCCLK frequency */ prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); 8011c6e: 2001 movs r0, #1 8011c70: f7ff fe58 bl 8011924 8011c74: 60f8 str r0, [r7, #12] /* Check that RTC clock is enabled*/ if (prescaler == 0U) 8011c76: 68fb ldr r3, [r7, #12] 8011c78: 2b00 cmp r3, #0 8011c7a: d104 bne.n 8011c86 { /* Should not happen. Frequency is not available*/ hrtc->State = HAL_RTC_STATE_ERROR; 8011c7c: 687b ldr r3, [r7, #4] 8011c7e: 2204 movs r2, #4 8011c80: 745a strb r2, [r3, #17] return HAL_ERROR; 8011c82: 2301 movs r3, #1 8011c84: e026 b.n 8011cd4 } else { /* RTC period = RTCCLK/(RTC_PR + 1) */ prescaler = prescaler - 1U; 8011c86: 68fb ldr r3, [r7, #12] 8011c88: 3b01 subs r3, #1 8011c8a: 60fb str r3, [r7, #12] } } /* Configure the RTC_PRLH / RTC_PRLL */ WRITE_REG(hrtc->Instance->PRLH, ((prescaler >> 16U) & RTC_PRLH_PRL)); 8011c8c: 68fb ldr r3, [r7, #12] 8011c8e: 0c1a lsrs r2, r3, #16 8011c90: 687b ldr r3, [r7, #4] 8011c92: 681b ldr r3, [r3, #0] 8011c94: f002 020f and.w r2, r2, #15 8011c98: 609a str r2, [r3, #8] WRITE_REG(hrtc->Instance->PRLL, (prescaler & RTC_PRLL_PRL)); 8011c9a: 687b ldr r3, [r7, #4] 8011c9c: 681b ldr r3, [r3, #0] 8011c9e: 68fa ldr r2, [r7, #12] 8011ca0: b292 uxth r2, r2 8011ca2: 60da str r2, [r3, #12] /* Wait for synchro */ if (RTC_ExitInitMode(hrtc) != HAL_OK) 8011ca4: 6878 ldr r0, [r7, #4] 8011ca6: f000 f870 bl 8011d8a 8011caa: 4603 mov r3, r0 8011cac: 2b00 cmp r3, #0 8011cae: d004 beq.n 8011cba { hrtc->State = HAL_RTC_STATE_ERROR; 8011cb0: 687b ldr r3, [r7, #4] 8011cb2: 2204 movs r2, #4 8011cb4: 745a strb r2, [r3, #17] return HAL_ERROR; 8011cb6: 2301 movs r3, #1 8011cb8: e00c b.n 8011cd4 } /* Initialize date to 1st of January 2000 */ hrtc->DateToUpdate.Year = 0x00U; 8011cba: 687b ldr r3, [r7, #4] 8011cbc: 2200 movs r2, #0 8011cbe: 73da strb r2, [r3, #15] hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; 8011cc0: 687b ldr r3, [r7, #4] 8011cc2: 2201 movs r2, #1 8011cc4: 735a strb r2, [r3, #13] hrtc->DateToUpdate.Date = 0x01U; 8011cc6: 687b ldr r3, [r7, #4] 8011cc8: 2201 movs r2, #1 8011cca: 739a strb r2, [r3, #14] /* Set RTC state */ hrtc->State = HAL_RTC_STATE_READY; 8011ccc: 687b ldr r3, [r7, #4] 8011cce: 2201 movs r2, #1 8011cd0: 745a strb r2, [r3, #17] return HAL_OK; 8011cd2: 2300 movs r3, #0 } } 8011cd4: 4618 mov r0, r3 8011cd6: 3710 adds r7, #16 8011cd8: 46bd mov sp, r7 8011cda: bd80 pop {r7, pc} 8011cdc: 40006c00 .word 0x40006c00 08011ce0 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { 8011ce0: b580 push {r7, lr} 8011ce2: b084 sub sp, #16 8011ce4: af00 add r7, sp, #0 8011ce6: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8011ce8: 2300 movs r3, #0 8011cea: 60fb str r3, [r7, #12] /* Check input parameters */ if (hrtc == NULL) 8011cec: 687b ldr r3, [r7, #4] 8011cee: 2b00 cmp r3, #0 8011cf0: d101 bne.n 8011cf6 { return HAL_ERROR; 8011cf2: 2301 movs r3, #1 8011cf4: e01d b.n 8011d32 } /* Clear RSF flag */ CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); 8011cf6: 687b ldr r3, [r7, #4] 8011cf8: 681b ldr r3, [r3, #0] 8011cfa: 685a ldr r2, [r3, #4] 8011cfc: 687b ldr r3, [r7, #4] 8011cfe: 681b ldr r3, [r3, #0] 8011d00: f022 0208 bic.w r2, r2, #8 8011d04: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8011d06: f7fc fb43 bl 800e390 8011d0a: 60f8 str r0, [r7, #12] /* Wait the registers to be synchronised */ while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8011d0c: e009 b.n 8011d22 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8011d0e: f7fc fb3f bl 800e390 8011d12: 4602 mov r2, r0 8011d14: 68fb ldr r3, [r7, #12] 8011d16: 1ad3 subs r3, r2, r3 8011d18: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8011d1c: d901 bls.n 8011d22 { return HAL_TIMEOUT; 8011d1e: 2303 movs r3, #3 8011d20: e007 b.n 8011d32 while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) 8011d22: 687b ldr r3, [r7, #4] 8011d24: 681b ldr r3, [r3, #0] 8011d26: 685b ldr r3, [r3, #4] 8011d28: f003 0308 and.w r3, r3, #8 8011d2c: 2b00 cmp r3, #0 8011d2e: d0ee beq.n 8011d0e } } return HAL_OK; 8011d30: 2300 movs r3, #0 } 8011d32: 4618 mov r0, r3 8011d34: 3710 adds r7, #16 8011d36: 46bd mov sp, r7 8011d38: bd80 pop {r7, pc} 08011d3a : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { 8011d3a: b580 push {r7, lr} 8011d3c: b084 sub sp, #16 8011d3e: af00 add r7, sp, #0 8011d40: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8011d42: 2300 movs r3, #0 8011d44: 60fb str r3, [r7, #12] tickstart = HAL_GetTick(); 8011d46: f7fc fb23 bl 800e390 8011d4a: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8011d4c: e009 b.n 8011d62 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8011d4e: f7fc fb1f bl 800e390 8011d52: 4602 mov r2, r0 8011d54: 68fb ldr r3, [r7, #12] 8011d56: 1ad3 subs r3, r2, r3 8011d58: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8011d5c: d901 bls.n 8011d62 { return HAL_TIMEOUT; 8011d5e: 2303 movs r3, #3 8011d60: e00f b.n 8011d82 while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8011d62: 687b ldr r3, [r7, #4] 8011d64: 681b ldr r3, [r3, #0] 8011d66: 685b ldr r3, [r3, #4] 8011d68: f003 0320 and.w r3, r3, #32 8011d6c: 2b00 cmp r3, #0 8011d6e: d0ee beq.n 8011d4e } } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 8011d70: 687b ldr r3, [r7, #4] 8011d72: 681b ldr r3, [r3, #0] 8011d74: 685a ldr r2, [r3, #4] 8011d76: 687b ldr r3, [r7, #4] 8011d78: 681b ldr r3, [r3, #0] 8011d7a: f042 0210 orr.w r2, r2, #16 8011d7e: 605a str r2, [r3, #4] return HAL_OK; 8011d80: 2300 movs r3, #0 } 8011d82: 4618 mov r0, r3 8011d84: 3710 adds r7, #16 8011d86: 46bd mov sp, r7 8011d88: bd80 pop {r7, pc} 08011d8a : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) { 8011d8a: b580 push {r7, lr} 8011d8c: b084 sub sp, #16 8011d8e: af00 add r7, sp, #0 8011d90: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8011d92: 2300 movs r3, #0 8011d94: 60fb str r3, [r7, #12] /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 8011d96: 687b ldr r3, [r7, #4] 8011d98: 681b ldr r3, [r3, #0] 8011d9a: 685a ldr r2, [r3, #4] 8011d9c: 687b ldr r3, [r7, #4] 8011d9e: 681b ldr r3, [r3, #0] 8011da0: f022 0210 bic.w r2, r2, #16 8011da4: 605a str r2, [r3, #4] tickstart = HAL_GetTick(); 8011da6: f7fc faf3 bl 800e390 8011daa: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8011dac: e009 b.n 8011dc2 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8011dae: f7fc faef bl 800e390 8011db2: 4602 mov r2, r0 8011db4: 68fb ldr r3, [r7, #12] 8011db6: 1ad3 subs r3, r2, r3 8011db8: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8011dbc: d901 bls.n 8011dc2 { return HAL_TIMEOUT; 8011dbe: 2303 movs r3, #3 8011dc0: e007 b.n 8011dd2 while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) 8011dc2: 687b ldr r3, [r7, #4] 8011dc4: 681b ldr r3, [r3, #0] 8011dc6: 685b ldr r3, [r3, #4] 8011dc8: f003 0320 and.w r3, r3, #32 8011dcc: 2b00 cmp r3, #0 8011dce: d0ee beq.n 8011dae } } return HAL_OK; 8011dd0: 2300 movs r3, #0 } 8011dd2: 4618 mov r0, r3 8011dd4: 3710 adds r7, #16 8011dd6: 46bd mov sp, r7 8011dd8: bd80 pop {r7, pc} 08011dda : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8011dda: b580 push {r7, lr} 8011ddc: b082 sub sp, #8 8011dde: af00 add r7, sp, #0 8011de0: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8011de2: 687b ldr r3, [r7, #4] 8011de4: 2b00 cmp r3, #0 8011de6: d101 bne.n 8011dec { return HAL_ERROR; 8011de8: 2301 movs r3, #1 8011dea: e041 b.n 8011e70 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8011dec: 687b ldr r3, [r7, #4] 8011dee: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8011df2: b2db uxtb r3, r3 8011df4: 2b00 cmp r3, #0 8011df6: d106 bne.n 8011e06 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8011df8: 687b ldr r3, [r7, #4] 8011dfa: 2200 movs r2, #0 8011dfc: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8011e00: 6878 ldr r0, [r7, #4] 8011e02: f7fb ff01 bl 800dc08 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8011e06: 687b ldr r3, [r7, #4] 8011e08: 2202 movs r2, #2 8011e0a: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8011e0e: 687b ldr r3, [r7, #4] 8011e10: 681a ldr r2, [r3, #0] 8011e12: 687b ldr r3, [r7, #4] 8011e14: 3304 adds r3, #4 8011e16: 4619 mov r1, r3 8011e18: 4610 mov r0, r2 8011e1a: f000 fd33 bl 8012884 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8011e1e: 687b ldr r3, [r7, #4] 8011e20: 2201 movs r2, #1 8011e22: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011e26: 687b ldr r3, [r7, #4] 8011e28: 2201 movs r2, #1 8011e2a: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011e2e: 687b ldr r3, [r7, #4] 8011e30: 2201 movs r2, #1 8011e32: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011e36: 687b ldr r3, [r7, #4] 8011e38: 2201 movs r2, #1 8011e3a: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011e3e: 687b ldr r3, [r7, #4] 8011e40: 2201 movs r2, #1 8011e42: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011e46: 687b ldr r3, [r7, #4] 8011e48: 2201 movs r2, #1 8011e4a: f883 2042 strb.w r2, [r3, #66] @ 0x42 8011e4e: 687b ldr r3, [r7, #4] 8011e50: 2201 movs r2, #1 8011e52: f883 2043 strb.w r2, [r3, #67] @ 0x43 8011e56: 687b ldr r3, [r7, #4] 8011e58: 2201 movs r2, #1 8011e5a: f883 2044 strb.w r2, [r3, #68] @ 0x44 8011e5e: 687b ldr r3, [r7, #4] 8011e60: 2201 movs r2, #1 8011e62: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8011e66: 687b ldr r3, [r7, #4] 8011e68: 2201 movs r2, #1 8011e6a: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8011e6e: 2300 movs r3, #0 } 8011e70: 4618 mov r0, r3 8011e72: 3708 adds r7, #8 8011e74: 46bd mov sp, r7 8011e76: bd80 pop {r7, pc} 08011e78 : * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { 8011e78: b580 push {r7, lr} 8011e7a: b082 sub sp, #8 8011e7c: af00 add r7, sp, #0 8011e7e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8011e80: 687b ldr r3, [r7, #4] 8011e82: 2b00 cmp r3, #0 8011e84: d101 bne.n 8011e8a { return HAL_ERROR; 8011e86: 2301 movs r3, #1 8011e88: e041 b.n 8011f0e assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8011e8a: 687b ldr r3, [r7, #4] 8011e8c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8011e90: b2db uxtb r3, r3 8011e92: 2b00 cmp r3, #0 8011e94: d106 bne.n 8011ea4 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8011e96: 687b ldr r3, [r7, #4] 8011e98: 2200 movs r2, #0 8011e9a: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); 8011e9e: 6878 ldr r0, [r7, #4] 8011ea0: f000 f839 bl 8011f16 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8011ea4: 687b ldr r3, [r7, #4] 8011ea6: 2202 movs r2, #2 8011ea8: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8011eac: 687b ldr r3, [r7, #4] 8011eae: 681a ldr r2, [r3, #0] 8011eb0: 687b ldr r3, [r7, #4] 8011eb2: 3304 adds r3, #4 8011eb4: 4619 mov r1, r3 8011eb6: 4610 mov r0, r2 8011eb8: f000 fce4 bl 8012884 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8011ebc: 687b ldr r3, [r7, #4] 8011ebe: 2201 movs r2, #1 8011ec0: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011ec4: 687b ldr r3, [r7, #4] 8011ec6: 2201 movs r2, #1 8011ec8: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011ecc: 687b ldr r3, [r7, #4] 8011ece: 2201 movs r2, #1 8011ed0: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011ed4: 687b ldr r3, [r7, #4] 8011ed6: 2201 movs r2, #1 8011ed8: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011edc: 687b ldr r3, [r7, #4] 8011ede: 2201 movs r2, #1 8011ee0: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8011ee4: 687b ldr r3, [r7, #4] 8011ee6: 2201 movs r2, #1 8011ee8: f883 2042 strb.w r2, [r3, #66] @ 0x42 8011eec: 687b ldr r3, [r7, #4] 8011eee: 2201 movs r2, #1 8011ef0: f883 2043 strb.w r2, [r3, #67] @ 0x43 8011ef4: 687b ldr r3, [r7, #4] 8011ef6: 2201 movs r2, #1 8011ef8: f883 2044 strb.w r2, [r3, #68] @ 0x44 8011efc: 687b ldr r3, [r7, #4] 8011efe: 2201 movs r2, #1 8011f00: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8011f04: 687b ldr r3, [r7, #4] 8011f06: 2201 movs r2, #1 8011f08: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8011f0c: 2300 movs r3, #0 } 8011f0e: 4618 mov r0, r3 8011f10: 3708 adds r7, #8 8011f12: 46bd mov sp, r7 8011f14: bd80 pop {r7, pc} 08011f16 : * @brief Initializes the TIM Output Compare MSP. * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) { 8011f16: b480 push {r7} 8011f18: b083 sub sp, #12 8011f1a: af00 add r7, sp, #0 8011f1c: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_MspInit could be implemented in the user file */ } 8011f1e: bf00 nop 8011f20: 370c adds r7, #12 8011f22: 46bd mov sp, r7 8011f24: bc80 pop {r7} 8011f26: 4770 bx lr 08011f28 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 8011f28: b580 push {r7, lr} 8011f2a: b084 sub sp, #16 8011f2c: af00 add r7, sp, #0 8011f2e: 6078 str r0, [r7, #4] 8011f30: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 8011f32: 683b ldr r3, [r7, #0] 8011f34: 2b00 cmp r3, #0 8011f36: d109 bne.n 8011f4c 8011f38: 687b ldr r3, [r7, #4] 8011f3a: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8011f3e: b2db uxtb r3, r3 8011f40: 2b01 cmp r3, #1 8011f42: bf14 ite ne 8011f44: 2301 movne r3, #1 8011f46: 2300 moveq r3, #0 8011f48: b2db uxtb r3, r3 8011f4a: e022 b.n 8011f92 8011f4c: 683b ldr r3, [r7, #0] 8011f4e: 2b04 cmp r3, #4 8011f50: d109 bne.n 8011f66 8011f52: 687b ldr r3, [r7, #4] 8011f54: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8011f58: b2db uxtb r3, r3 8011f5a: 2b01 cmp r3, #1 8011f5c: bf14 ite ne 8011f5e: 2301 movne r3, #1 8011f60: 2300 moveq r3, #0 8011f62: b2db uxtb r3, r3 8011f64: e015 b.n 8011f92 8011f66: 683b ldr r3, [r7, #0] 8011f68: 2b08 cmp r3, #8 8011f6a: d109 bne.n 8011f80 8011f6c: 687b ldr r3, [r7, #4] 8011f6e: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8011f72: b2db uxtb r3, r3 8011f74: 2b01 cmp r3, #1 8011f76: bf14 ite ne 8011f78: 2301 movne r3, #1 8011f7a: 2300 moveq r3, #0 8011f7c: b2db uxtb r3, r3 8011f7e: e008 b.n 8011f92 8011f80: 687b ldr r3, [r7, #4] 8011f82: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8011f86: b2db uxtb r3, r3 8011f88: 2b01 cmp r3, #1 8011f8a: bf14 ite ne 8011f8c: 2301 movne r3, #1 8011f8e: 2300 moveq r3, #0 8011f90: b2db uxtb r3, r3 8011f92: 2b00 cmp r3, #0 8011f94: d001 beq.n 8011f9a { return HAL_ERROR; 8011f96: 2301 movs r3, #1 8011f98: e063 b.n 8012062 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8011f9a: 683b ldr r3, [r7, #0] 8011f9c: 2b00 cmp r3, #0 8011f9e: d104 bne.n 8011faa 8011fa0: 687b ldr r3, [r7, #4] 8011fa2: 2202 movs r2, #2 8011fa4: f883 203e strb.w r2, [r3, #62] @ 0x3e 8011fa8: e013 b.n 8011fd2 8011faa: 683b ldr r3, [r7, #0] 8011fac: 2b04 cmp r3, #4 8011fae: d104 bne.n 8011fba 8011fb0: 687b ldr r3, [r7, #4] 8011fb2: 2202 movs r2, #2 8011fb4: f883 203f strb.w r2, [r3, #63] @ 0x3f 8011fb8: e00b b.n 8011fd2 8011fba: 683b ldr r3, [r7, #0] 8011fbc: 2b08 cmp r3, #8 8011fbe: d104 bne.n 8011fca 8011fc0: 687b ldr r3, [r7, #4] 8011fc2: 2202 movs r2, #2 8011fc4: f883 2040 strb.w r2, [r3, #64] @ 0x40 8011fc8: e003 b.n 8011fd2 8011fca: 687b ldr r3, [r7, #4] 8011fcc: 2202 movs r2, #2 8011fce: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 8011fd2: 687b ldr r3, [r7, #4] 8011fd4: 681b ldr r3, [r3, #0] 8011fd6: 2201 movs r2, #1 8011fd8: 6839 ldr r1, [r7, #0] 8011fda: 4618 mov r0, r3 8011fdc: f000 fee8 bl 8012db0 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8011fe0: 687b ldr r3, [r7, #4] 8011fe2: 681b ldr r3, [r3, #0] 8011fe4: 4a21 ldr r2, [pc, #132] @ (801206c ) 8011fe6: 4293 cmp r3, r2 8011fe8: d107 bne.n 8011ffa { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8011fea: 687b ldr r3, [r7, #4] 8011fec: 681b ldr r3, [r3, #0] 8011fee: 6c5a ldr r2, [r3, #68] @ 0x44 8011ff0: 687b ldr r3, [r7, #4] 8011ff2: 681b ldr r3, [r3, #0] 8011ff4: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8011ff8: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8011ffa: 687b ldr r3, [r7, #4] 8011ffc: 681b ldr r3, [r3, #0] 8011ffe: 4a1b ldr r2, [pc, #108] @ (801206c ) 8012000: 4293 cmp r3, r2 8012002: d013 beq.n 801202c 8012004: 687b ldr r3, [r7, #4] 8012006: 681b ldr r3, [r3, #0] 8012008: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 801200c: d00e beq.n 801202c 801200e: 687b ldr r3, [r7, #4] 8012010: 681b ldr r3, [r3, #0] 8012012: 4a17 ldr r2, [pc, #92] @ (8012070 ) 8012014: 4293 cmp r3, r2 8012016: d009 beq.n 801202c 8012018: 687b ldr r3, [r7, #4] 801201a: 681b ldr r3, [r3, #0] 801201c: 4a15 ldr r2, [pc, #84] @ (8012074 ) 801201e: 4293 cmp r3, r2 8012020: d004 beq.n 801202c 8012022: 687b ldr r3, [r7, #4] 8012024: 681b ldr r3, [r3, #0] 8012026: 4a14 ldr r2, [pc, #80] @ (8012078 ) 8012028: 4293 cmp r3, r2 801202a: d111 bne.n 8012050 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 801202c: 687b ldr r3, [r7, #4] 801202e: 681b ldr r3, [r3, #0] 8012030: 689b ldr r3, [r3, #8] 8012032: f003 0307 and.w r3, r3, #7 8012036: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8012038: 68fb ldr r3, [r7, #12] 801203a: 2b06 cmp r3, #6 801203c: d010 beq.n 8012060 { __HAL_TIM_ENABLE(htim); 801203e: 687b ldr r3, [r7, #4] 8012040: 681b ldr r3, [r3, #0] 8012042: 681a ldr r2, [r3, #0] 8012044: 687b ldr r3, [r7, #4] 8012046: 681b ldr r3, [r3, #0] 8012048: f042 0201 orr.w r2, r2, #1 801204c: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 801204e: e007 b.n 8012060 } } else { __HAL_TIM_ENABLE(htim); 8012050: 687b ldr r3, [r7, #4] 8012052: 681b ldr r3, [r3, #0] 8012054: 681a ldr r2, [r3, #0] 8012056: 687b ldr r3, [r7, #4] 8012058: 681b ldr r3, [r3, #0] 801205a: f042 0201 orr.w r2, r2, #1 801205e: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8012060: 2300 movs r3, #0 } 8012062: 4618 mov r0, r3 8012064: 3710 adds r7, #16 8012066: 46bd mov sp, r7 8012068: bd80 pop {r7, pc} 801206a: bf00 nop 801206c: 40012c00 .word 0x40012c00 8012070: 40000400 .word 0x40000400 8012074: 40000800 .word 0x40000800 8012078: 40000c00 .word 0x40000c00 0801207c : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 801207c: b580 push {r7, lr} 801207e: b082 sub sp, #8 8012080: af00 add r7, sp, #0 8012082: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8012084: 687b ldr r3, [r7, #4] 8012086: 2b00 cmp r3, #0 8012088: d101 bne.n 801208e { return HAL_ERROR; 801208a: 2301 movs r3, #1 801208c: e041 b.n 8012112 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 801208e: 687b ldr r3, [r7, #4] 8012090: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8012094: b2db uxtb r3, r3 8012096: 2b00 cmp r3, #0 8012098: d106 bne.n 80120a8 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 801209a: 687b ldr r3, [r7, #4] 801209c: 2200 movs r2, #0 801209e: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 80120a2: 6878 ldr r0, [r7, #4] 80120a4: f000 f839 bl 801211a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80120a8: 687b ldr r3, [r7, #4] 80120aa: 2202 movs r2, #2 80120ac: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 80120b0: 687b ldr r3, [r7, #4] 80120b2: 681a ldr r2, [r3, #0] 80120b4: 687b ldr r3, [r7, #4] 80120b6: 3304 adds r3, #4 80120b8: 4619 mov r1, r3 80120ba: 4610 mov r0, r2 80120bc: f000 fbe2 bl 8012884 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 80120c0: 687b ldr r3, [r7, #4] 80120c2: 2201 movs r2, #1 80120c4: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80120c8: 687b ldr r3, [r7, #4] 80120ca: 2201 movs r2, #1 80120cc: f883 203e strb.w r2, [r3, #62] @ 0x3e 80120d0: 687b ldr r3, [r7, #4] 80120d2: 2201 movs r2, #1 80120d4: f883 203f strb.w r2, [r3, #63] @ 0x3f 80120d8: 687b ldr r3, [r7, #4] 80120da: 2201 movs r2, #1 80120dc: f883 2040 strb.w r2, [r3, #64] @ 0x40 80120e0: 687b ldr r3, [r7, #4] 80120e2: 2201 movs r2, #1 80120e4: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80120e8: 687b ldr r3, [r7, #4] 80120ea: 2201 movs r2, #1 80120ec: f883 2042 strb.w r2, [r3, #66] @ 0x42 80120f0: 687b ldr r3, [r7, #4] 80120f2: 2201 movs r2, #1 80120f4: f883 2043 strb.w r2, [r3, #67] @ 0x43 80120f8: 687b ldr r3, [r7, #4] 80120fa: 2201 movs r2, #1 80120fc: f883 2044 strb.w r2, [r3, #68] @ 0x44 8012100: 687b ldr r3, [r7, #4] 8012102: 2201 movs r2, #1 8012104: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8012108: 687b ldr r3, [r7, #4] 801210a: 2201 movs r2, #1 801210c: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8012110: 2300 movs r3, #0 } 8012112: 4618 mov r0, r3 8012114: 3708 adds r7, #8 8012116: 46bd mov sp, r7 8012118: bd80 pop {r7, pc} 0801211a : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 801211a: b480 push {r7} 801211c: b083 sub sp, #12 801211e: af00 add r7, sp, #0 8012120: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 8012122: bf00 nop 8012124: 370c adds r7, #12 8012126: 46bd mov sp, r7 8012128: bc80 pop {r7} 801212a: 4770 bx lr 0801212c : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 801212c: b580 push {r7, lr} 801212e: b084 sub sp, #16 8012130: af00 add r7, sp, #0 8012132: 6078 str r0, [r7, #4] 8012134: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 8012136: 683b ldr r3, [r7, #0] 8012138: 2b00 cmp r3, #0 801213a: d109 bne.n 8012150 801213c: 687b ldr r3, [r7, #4] 801213e: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8012142: b2db uxtb r3, r3 8012144: 2b01 cmp r3, #1 8012146: bf14 ite ne 8012148: 2301 movne r3, #1 801214a: 2300 moveq r3, #0 801214c: b2db uxtb r3, r3 801214e: e022 b.n 8012196 8012150: 683b ldr r3, [r7, #0] 8012152: 2b04 cmp r3, #4 8012154: d109 bne.n 801216a 8012156: 687b ldr r3, [r7, #4] 8012158: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 801215c: b2db uxtb r3, r3 801215e: 2b01 cmp r3, #1 8012160: bf14 ite ne 8012162: 2301 movne r3, #1 8012164: 2300 moveq r3, #0 8012166: b2db uxtb r3, r3 8012168: e015 b.n 8012196 801216a: 683b ldr r3, [r7, #0] 801216c: 2b08 cmp r3, #8 801216e: d109 bne.n 8012184 8012170: 687b ldr r3, [r7, #4] 8012172: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8012176: b2db uxtb r3, r3 8012178: 2b01 cmp r3, #1 801217a: bf14 ite ne 801217c: 2301 movne r3, #1 801217e: 2300 moveq r3, #0 8012180: b2db uxtb r3, r3 8012182: e008 b.n 8012196 8012184: 687b ldr r3, [r7, #4] 8012186: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 801218a: b2db uxtb r3, r3 801218c: 2b01 cmp r3, #1 801218e: bf14 ite ne 8012190: 2301 movne r3, #1 8012192: 2300 moveq r3, #0 8012194: b2db uxtb r3, r3 8012196: 2b00 cmp r3, #0 8012198: d001 beq.n 801219e { return HAL_ERROR; 801219a: 2301 movs r3, #1 801219c: e063 b.n 8012266 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 801219e: 683b ldr r3, [r7, #0] 80121a0: 2b00 cmp r3, #0 80121a2: d104 bne.n 80121ae 80121a4: 687b ldr r3, [r7, #4] 80121a6: 2202 movs r2, #2 80121a8: f883 203e strb.w r2, [r3, #62] @ 0x3e 80121ac: e013 b.n 80121d6 80121ae: 683b ldr r3, [r7, #0] 80121b0: 2b04 cmp r3, #4 80121b2: d104 bne.n 80121be 80121b4: 687b ldr r3, [r7, #4] 80121b6: 2202 movs r2, #2 80121b8: f883 203f strb.w r2, [r3, #63] @ 0x3f 80121bc: e00b b.n 80121d6 80121be: 683b ldr r3, [r7, #0] 80121c0: 2b08 cmp r3, #8 80121c2: d104 bne.n 80121ce 80121c4: 687b ldr r3, [r7, #4] 80121c6: 2202 movs r2, #2 80121c8: f883 2040 strb.w r2, [r3, #64] @ 0x40 80121cc: e003 b.n 80121d6 80121ce: 687b ldr r3, [r7, #4] 80121d0: 2202 movs r2, #2 80121d2: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 80121d6: 687b ldr r3, [r7, #4] 80121d8: 681b ldr r3, [r3, #0] 80121da: 2201 movs r2, #1 80121dc: 6839 ldr r1, [r7, #0] 80121de: 4618 mov r0, r3 80121e0: f000 fde6 bl 8012db0 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 80121e4: 687b ldr r3, [r7, #4] 80121e6: 681b ldr r3, [r3, #0] 80121e8: 4a21 ldr r2, [pc, #132] @ (8012270 ) 80121ea: 4293 cmp r3, r2 80121ec: d107 bne.n 80121fe { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 80121ee: 687b ldr r3, [r7, #4] 80121f0: 681b ldr r3, [r3, #0] 80121f2: 6c5a ldr r2, [r3, #68] @ 0x44 80121f4: 687b ldr r3, [r7, #4] 80121f6: 681b ldr r3, [r3, #0] 80121f8: f442 4200 orr.w r2, r2, #32768 @ 0x8000 80121fc: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80121fe: 687b ldr r3, [r7, #4] 8012200: 681b ldr r3, [r3, #0] 8012202: 4a1b ldr r2, [pc, #108] @ (8012270 ) 8012204: 4293 cmp r3, r2 8012206: d013 beq.n 8012230 8012208: 687b ldr r3, [r7, #4] 801220a: 681b ldr r3, [r3, #0] 801220c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8012210: d00e beq.n 8012230 8012212: 687b ldr r3, [r7, #4] 8012214: 681b ldr r3, [r3, #0] 8012216: 4a17 ldr r2, [pc, #92] @ (8012274 ) 8012218: 4293 cmp r3, r2 801221a: d009 beq.n 8012230 801221c: 687b ldr r3, [r7, #4] 801221e: 681b ldr r3, [r3, #0] 8012220: 4a15 ldr r2, [pc, #84] @ (8012278 ) 8012222: 4293 cmp r3, r2 8012224: d004 beq.n 8012230 8012226: 687b ldr r3, [r7, #4] 8012228: 681b ldr r3, [r3, #0] 801222a: 4a14 ldr r2, [pc, #80] @ (801227c ) 801222c: 4293 cmp r3, r2 801222e: d111 bne.n 8012254 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8012230: 687b ldr r3, [r7, #4] 8012232: 681b ldr r3, [r3, #0] 8012234: 689b ldr r3, [r3, #8] 8012236: f003 0307 and.w r3, r3, #7 801223a: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 801223c: 68fb ldr r3, [r7, #12] 801223e: 2b06 cmp r3, #6 8012240: d010 beq.n 8012264 { __HAL_TIM_ENABLE(htim); 8012242: 687b ldr r3, [r7, #4] 8012244: 681b ldr r3, [r3, #0] 8012246: 681a ldr r2, [r3, #0] 8012248: 687b ldr r3, [r7, #4] 801224a: 681b ldr r3, [r3, #0] 801224c: f042 0201 orr.w r2, r2, #1 8012250: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8012252: e007 b.n 8012264 } } else { __HAL_TIM_ENABLE(htim); 8012254: 687b ldr r3, [r7, #4] 8012256: 681b ldr r3, [r3, #0] 8012258: 681a ldr r2, [r3, #0] 801225a: 687b ldr r3, [r7, #4] 801225c: 681b ldr r3, [r3, #0] 801225e: f042 0201 orr.w r2, r2, #1 8012262: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8012264: 2300 movs r3, #0 } 8012266: 4618 mov r0, r3 8012268: 3710 adds r7, #16 801226a: 46bd mov sp, r7 801226c: bd80 pop {r7, pc} 801226e: bf00 nop 8012270: 40012c00 .word 0x40012c00 8012274: 40000400 .word 0x40000400 8012278: 40000800 .word 0x40000800 801227c: 40000c00 .word 0x40000c00 08012280 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8012280: b580 push {r7, lr} 8012282: b084 sub sp, #16 8012284: af00 add r7, sp, #0 8012286: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 8012288: 687b ldr r3, [r7, #4] 801228a: 681b ldr r3, [r3, #0] 801228c: 68db ldr r3, [r3, #12] 801228e: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 8012290: 687b ldr r3, [r7, #4] 8012292: 681b ldr r3, [r3, #0] 8012294: 691b ldr r3, [r3, #16] 8012296: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 8012298: 68bb ldr r3, [r7, #8] 801229a: f003 0302 and.w r3, r3, #2 801229e: 2b00 cmp r3, #0 80122a0: d020 beq.n 80122e4 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 80122a2: 68fb ldr r3, [r7, #12] 80122a4: f003 0302 and.w r3, r3, #2 80122a8: 2b00 cmp r3, #0 80122aa: d01b beq.n 80122e4 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 80122ac: 687b ldr r3, [r7, #4] 80122ae: 681b ldr r3, [r3, #0] 80122b0: f06f 0202 mvn.w r2, #2 80122b4: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 80122b6: 687b ldr r3, [r7, #4] 80122b8: 2201 movs r2, #1 80122ba: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 80122bc: 687b ldr r3, [r7, #4] 80122be: 681b ldr r3, [r3, #0] 80122c0: 699b ldr r3, [r3, #24] 80122c2: f003 0303 and.w r3, r3, #3 80122c6: 2b00 cmp r3, #0 80122c8: d003 beq.n 80122d2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80122ca: 6878 ldr r0, [r7, #4] 80122cc: f000 fabf bl 801284e 80122d0: e005 b.n 80122de { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80122d2: 6878 ldr r0, [r7, #4] 80122d4: f000 fab2 bl 801283c HAL_TIM_PWM_PulseFinishedCallback(htim); 80122d8: 6878 ldr r0, [r7, #4] 80122da: f000 fac1 bl 8012860 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80122de: 687b ldr r3, [r7, #4] 80122e0: 2200 movs r2, #0 80122e2: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 80122e4: 68bb ldr r3, [r7, #8] 80122e6: f003 0304 and.w r3, r3, #4 80122ea: 2b00 cmp r3, #0 80122ec: d020 beq.n 8012330 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 80122ee: 68fb ldr r3, [r7, #12] 80122f0: f003 0304 and.w r3, r3, #4 80122f4: 2b00 cmp r3, #0 80122f6: d01b beq.n 8012330 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 80122f8: 687b ldr r3, [r7, #4] 80122fa: 681b ldr r3, [r3, #0] 80122fc: f06f 0204 mvn.w r2, #4 8012300: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 8012302: 687b ldr r3, [r7, #4] 8012304: 2202 movs r2, #2 8012306: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8012308: 687b ldr r3, [r7, #4] 801230a: 681b ldr r3, [r3, #0] 801230c: 699b ldr r3, [r3, #24] 801230e: f403 7340 and.w r3, r3, #768 @ 0x300 8012312: 2b00 cmp r3, #0 8012314: d003 beq.n 801231e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8012316: 6878 ldr r0, [r7, #4] 8012318: f000 fa99 bl 801284e 801231c: e005 b.n 801232a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 801231e: 6878 ldr r0, [r7, #4] 8012320: f000 fa8c bl 801283c HAL_TIM_PWM_PulseFinishedCallback(htim); 8012324: 6878 ldr r0, [r7, #4] 8012326: f000 fa9b bl 8012860 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 801232a: 687b ldr r3, [r7, #4] 801232c: 2200 movs r2, #0 801232e: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 8012330: 68bb ldr r3, [r7, #8] 8012332: f003 0308 and.w r3, r3, #8 8012336: 2b00 cmp r3, #0 8012338: d020 beq.n 801237c { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 801233a: 68fb ldr r3, [r7, #12] 801233c: f003 0308 and.w r3, r3, #8 8012340: 2b00 cmp r3, #0 8012342: d01b beq.n 801237c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 8012344: 687b ldr r3, [r7, #4] 8012346: 681b ldr r3, [r3, #0] 8012348: f06f 0208 mvn.w r2, #8 801234c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 801234e: 687b ldr r3, [r7, #4] 8012350: 2204 movs r2, #4 8012352: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8012354: 687b ldr r3, [r7, #4] 8012356: 681b ldr r3, [r3, #0] 8012358: 69db ldr r3, [r3, #28] 801235a: f003 0303 and.w r3, r3, #3 801235e: 2b00 cmp r3, #0 8012360: d003 beq.n 801236a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8012362: 6878 ldr r0, [r7, #4] 8012364: f000 fa73 bl 801284e 8012368: e005 b.n 8012376 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 801236a: 6878 ldr r0, [r7, #4] 801236c: f000 fa66 bl 801283c HAL_TIM_PWM_PulseFinishedCallback(htim); 8012370: 6878 ldr r0, [r7, #4] 8012372: f000 fa75 bl 8012860 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8012376: 687b ldr r3, [r7, #4] 8012378: 2200 movs r2, #0 801237a: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 801237c: 68bb ldr r3, [r7, #8] 801237e: f003 0310 and.w r3, r3, #16 8012382: 2b00 cmp r3, #0 8012384: d020 beq.n 80123c8 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 8012386: 68fb ldr r3, [r7, #12] 8012388: f003 0310 and.w r3, r3, #16 801238c: 2b00 cmp r3, #0 801238e: d01b beq.n 80123c8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 8012390: 687b ldr r3, [r7, #4] 8012392: 681b ldr r3, [r3, #0] 8012394: f06f 0210 mvn.w r2, #16 8012398: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 801239a: 687b ldr r3, [r7, #4] 801239c: 2208 movs r2, #8 801239e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 80123a0: 687b ldr r3, [r7, #4] 80123a2: 681b ldr r3, [r3, #0] 80123a4: 69db ldr r3, [r3, #28] 80123a6: f403 7340 and.w r3, r3, #768 @ 0x300 80123aa: 2b00 cmp r3, #0 80123ac: d003 beq.n 80123b6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80123ae: 6878 ldr r0, [r7, #4] 80123b0: f000 fa4d bl 801284e 80123b4: e005 b.n 80123c2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80123b6: 6878 ldr r0, [r7, #4] 80123b8: f000 fa40 bl 801283c HAL_TIM_PWM_PulseFinishedCallback(htim); 80123bc: 6878 ldr r0, [r7, #4] 80123be: f000 fa4f bl 8012860 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80123c2: 687b ldr r3, [r7, #4] 80123c4: 2200 movs r2, #0 80123c6: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 80123c8: 68bb ldr r3, [r7, #8] 80123ca: f003 0301 and.w r3, r3, #1 80123ce: 2b00 cmp r3, #0 80123d0: d00c beq.n 80123ec { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 80123d2: 68fb ldr r3, [r7, #12] 80123d4: f003 0301 and.w r3, r3, #1 80123d8: 2b00 cmp r3, #0 80123da: d007 beq.n 80123ec { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 80123dc: 687b ldr r3, [r7, #4] 80123de: 681b ldr r3, [r3, #0] 80123e0: f06f 0201 mvn.w r2, #1 80123e4: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 80123e6: 6878 ldr r0, [r7, #4] 80123e8: f000 fa1f bl 801282a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) 80123ec: 68bb ldr r3, [r7, #8] 80123ee: f003 0380 and.w r3, r3, #128 @ 0x80 80123f2: 2b00 cmp r3, #0 80123f4: d00c beq.n 8012410 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 80123f6: 68fb ldr r3, [r7, #12] 80123f8: f003 0380 and.w r3, r3, #128 @ 0x80 80123fc: 2b00 cmp r3, #0 80123fe: d007 beq.n 8012410 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); 8012400: 687b ldr r3, [r7, #4] 8012402: 681b ldr r3, [r3, #0] 8012404: f06f 0280 mvn.w r2, #128 @ 0x80 8012408: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 801240a: 6878 ldr r0, [r7, #4] 801240c: f000 fd63 bl 8012ed6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 8012410: 68bb ldr r3, [r7, #8] 8012412: f003 0340 and.w r3, r3, #64 @ 0x40 8012416: 2b00 cmp r3, #0 8012418: d00c beq.n 8012434 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 801241a: 68fb ldr r3, [r7, #12] 801241c: f003 0340 and.w r3, r3, #64 @ 0x40 8012420: 2b00 cmp r3, #0 8012422: d007 beq.n 8012434 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 8012424: 687b ldr r3, [r7, #4] 8012426: 681b ldr r3, [r3, #0] 8012428: f06f 0240 mvn.w r2, #64 @ 0x40 801242c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 801242e: 6878 ldr r0, [r7, #4] 8012430: f000 fa1f bl 8012872 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 8012434: 68bb ldr r3, [r7, #8] 8012436: f003 0320 and.w r3, r3, #32 801243a: 2b00 cmp r3, #0 801243c: d00c beq.n 8012458 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 801243e: 68fb ldr r3, [r7, #12] 8012440: f003 0320 and.w r3, r3, #32 8012444: 2b00 cmp r3, #0 8012446: d007 beq.n 8012458 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 8012448: 687b ldr r3, [r7, #4] 801244a: 681b ldr r3, [r3, #0] 801244c: f06f 0220 mvn.w r2, #32 8012450: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8012452: 6878 ldr r0, [r7, #4] 8012454: f000 fd36 bl 8012ec4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8012458: bf00 nop 801245a: 3710 adds r7, #16 801245c: 46bd mov sp, r7 801245e: bd80 pop {r7, pc} 08012460 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8012460: b580 push {r7, lr} 8012462: b086 sub sp, #24 8012464: af00 add r7, sp, #0 8012466: 60f8 str r0, [r7, #12] 8012468: 60b9 str r1, [r7, #8] 801246a: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 801246c: 2300 movs r3, #0 801246e: 75fb strb r3, [r7, #23] assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); 8012470: 68fb ldr r3, [r7, #12] 8012472: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8012476: 2b01 cmp r3, #1 8012478: d101 bne.n 801247e 801247a: 2302 movs r3, #2 801247c: e048 b.n 8012510 801247e: 68fb ldr r3, [r7, #12] 8012480: 2201 movs r2, #1 8012482: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 8012486: 687b ldr r3, [r7, #4] 8012488: 2b0c cmp r3, #12 801248a: d839 bhi.n 8012500 801248c: a201 add r2, pc, #4 @ (adr r2, 8012494 ) 801248e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012492: bf00 nop 8012494: 080124c9 .word 0x080124c9 8012498: 08012501 .word 0x08012501 801249c: 08012501 .word 0x08012501 80124a0: 08012501 .word 0x08012501 80124a4: 080124d7 .word 0x080124d7 80124a8: 08012501 .word 0x08012501 80124ac: 08012501 .word 0x08012501 80124b0: 08012501 .word 0x08012501 80124b4: 080124e5 .word 0x080124e5 80124b8: 08012501 .word 0x08012501 80124bc: 08012501 .word 0x08012501 80124c0: 08012501 .word 0x08012501 80124c4: 080124f3 .word 0x080124f3 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); 80124c8: 68fb ldr r3, [r7, #12] 80124ca: 681b ldr r3, [r3, #0] 80124cc: 68b9 ldr r1, [r7, #8] 80124ce: 4618 mov r0, r3 80124d0: f000 fa50 bl 8012974 break; 80124d4: e017 b.n 8012506 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); 80124d6: 68fb ldr r3, [r7, #12] 80124d8: 681b ldr r3, [r3, #0] 80124da: 68b9 ldr r1, [r7, #8] 80124dc: 4618 mov r0, r3 80124de: f000 faaf bl 8012a40 break; 80124e2: e010 b.n 8012506 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); 80124e4: 68fb ldr r3, [r7, #12] 80124e6: 681b ldr r3, [r3, #0] 80124e8: 68b9 ldr r1, [r7, #8] 80124ea: 4618 mov r0, r3 80124ec: f000 fb12 bl 8012b14 break; 80124f0: e009 b.n 8012506 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); 80124f2: 68fb ldr r3, [r7, #12] 80124f4: 681b ldr r3, [r3, #0] 80124f6: 68b9 ldr r1, [r7, #8] 80124f8: 4618 mov r0, r3 80124fa: f000 fb75 bl 8012be8 break; 80124fe: e002 b.n 8012506 } default: status = HAL_ERROR; 8012500: 2301 movs r3, #1 8012502: 75fb strb r3, [r7, #23] break; 8012504: bf00 nop } __HAL_UNLOCK(htim); 8012506: 68fb ldr r3, [r7, #12] 8012508: 2200 movs r2, #0 801250a: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 801250e: 7dfb ldrb r3, [r7, #23] } 8012510: 4618 mov r0, r3 8012512: 3718 adds r7, #24 8012514: 46bd mov sp, r7 8012516: bd80 pop {r7, pc} 08012518 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8012518: b580 push {r7, lr} 801251a: b086 sub sp, #24 801251c: af00 add r7, sp, #0 801251e: 60f8 str r0, [r7, #12] 8012520: 60b9 str r1, [r7, #8] 8012522: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8012524: 2300 movs r3, #0 8012526: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 8012528: 68fb ldr r3, [r7, #12] 801252a: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 801252e: 2b01 cmp r3, #1 8012530: d101 bne.n 8012536 8012532: 2302 movs r3, #2 8012534: e0ae b.n 8012694 8012536: 68fb ldr r3, [r7, #12] 8012538: 2201 movs r2, #1 801253a: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 801253e: 687b ldr r3, [r7, #4] 8012540: 2b0c cmp r3, #12 8012542: f200 809f bhi.w 8012684 8012546: a201 add r2, pc, #4 @ (adr r2, 801254c ) 8012548: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801254c: 08012581 .word 0x08012581 8012550: 08012685 .word 0x08012685 8012554: 08012685 .word 0x08012685 8012558: 08012685 .word 0x08012685 801255c: 080125c1 .word 0x080125c1 8012560: 08012685 .word 0x08012685 8012564: 08012685 .word 0x08012685 8012568: 08012685 .word 0x08012685 801256c: 08012603 .word 0x08012603 8012570: 08012685 .word 0x08012685 8012574: 08012685 .word 0x08012685 8012578: 08012685 .word 0x08012685 801257c: 08012643 .word 0x08012643 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8012580: 68fb ldr r3, [r7, #12] 8012582: 681b ldr r3, [r3, #0] 8012584: 68b9 ldr r1, [r7, #8] 8012586: 4618 mov r0, r3 8012588: f000 f9f4 bl 8012974 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 801258c: 68fb ldr r3, [r7, #12] 801258e: 681b ldr r3, [r3, #0] 8012590: 699a ldr r2, [r3, #24] 8012592: 68fb ldr r3, [r7, #12] 8012594: 681b ldr r3, [r3, #0] 8012596: f042 0208 orr.w r2, r2, #8 801259a: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 801259c: 68fb ldr r3, [r7, #12] 801259e: 681b ldr r3, [r3, #0] 80125a0: 699a ldr r2, [r3, #24] 80125a2: 68fb ldr r3, [r7, #12] 80125a4: 681b ldr r3, [r3, #0] 80125a6: f022 0204 bic.w r2, r2, #4 80125aa: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 80125ac: 68fb ldr r3, [r7, #12] 80125ae: 681b ldr r3, [r3, #0] 80125b0: 6999 ldr r1, [r3, #24] 80125b2: 68bb ldr r3, [r7, #8] 80125b4: 691a ldr r2, [r3, #16] 80125b6: 68fb ldr r3, [r7, #12] 80125b8: 681b ldr r3, [r3, #0] 80125ba: 430a orrs r2, r1 80125bc: 619a str r2, [r3, #24] break; 80125be: e064 b.n 801268a { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 80125c0: 68fb ldr r3, [r7, #12] 80125c2: 681b ldr r3, [r3, #0] 80125c4: 68b9 ldr r1, [r7, #8] 80125c6: 4618 mov r0, r3 80125c8: f000 fa3a bl 8012a40 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 80125cc: 68fb ldr r3, [r7, #12] 80125ce: 681b ldr r3, [r3, #0] 80125d0: 699a ldr r2, [r3, #24] 80125d2: 68fb ldr r3, [r7, #12] 80125d4: 681b ldr r3, [r3, #0] 80125d6: f442 6200 orr.w r2, r2, #2048 @ 0x800 80125da: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 80125dc: 68fb ldr r3, [r7, #12] 80125de: 681b ldr r3, [r3, #0] 80125e0: 699a ldr r2, [r3, #24] 80125e2: 68fb ldr r3, [r7, #12] 80125e4: 681b ldr r3, [r3, #0] 80125e6: f422 6280 bic.w r2, r2, #1024 @ 0x400 80125ea: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 80125ec: 68fb ldr r3, [r7, #12] 80125ee: 681b ldr r3, [r3, #0] 80125f0: 6999 ldr r1, [r3, #24] 80125f2: 68bb ldr r3, [r7, #8] 80125f4: 691b ldr r3, [r3, #16] 80125f6: 021a lsls r2, r3, #8 80125f8: 68fb ldr r3, [r7, #12] 80125fa: 681b ldr r3, [r3, #0] 80125fc: 430a orrs r2, r1 80125fe: 619a str r2, [r3, #24] break; 8012600: e043 b.n 801268a { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8012602: 68fb ldr r3, [r7, #12] 8012604: 681b ldr r3, [r3, #0] 8012606: 68b9 ldr r1, [r7, #8] 8012608: 4618 mov r0, r3 801260a: f000 fa83 bl 8012b14 /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 801260e: 68fb ldr r3, [r7, #12] 8012610: 681b ldr r3, [r3, #0] 8012612: 69da ldr r2, [r3, #28] 8012614: 68fb ldr r3, [r7, #12] 8012616: 681b ldr r3, [r3, #0] 8012618: f042 0208 orr.w r2, r2, #8 801261c: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 801261e: 68fb ldr r3, [r7, #12] 8012620: 681b ldr r3, [r3, #0] 8012622: 69da ldr r2, [r3, #28] 8012624: 68fb ldr r3, [r7, #12] 8012626: 681b ldr r3, [r3, #0] 8012628: f022 0204 bic.w r2, r2, #4 801262c: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 801262e: 68fb ldr r3, [r7, #12] 8012630: 681b ldr r3, [r3, #0] 8012632: 69d9 ldr r1, [r3, #28] 8012634: 68bb ldr r3, [r7, #8] 8012636: 691a ldr r2, [r3, #16] 8012638: 68fb ldr r3, [r7, #12] 801263a: 681b ldr r3, [r3, #0] 801263c: 430a orrs r2, r1 801263e: 61da str r2, [r3, #28] break; 8012640: e023 b.n 801268a { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8012642: 68fb ldr r3, [r7, #12] 8012644: 681b ldr r3, [r3, #0] 8012646: 68b9 ldr r1, [r7, #8] 8012648: 4618 mov r0, r3 801264a: f000 facd bl 8012be8 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 801264e: 68fb ldr r3, [r7, #12] 8012650: 681b ldr r3, [r3, #0] 8012652: 69da ldr r2, [r3, #28] 8012654: 68fb ldr r3, [r7, #12] 8012656: 681b ldr r3, [r3, #0] 8012658: f442 6200 orr.w r2, r2, #2048 @ 0x800 801265c: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 801265e: 68fb ldr r3, [r7, #12] 8012660: 681b ldr r3, [r3, #0] 8012662: 69da ldr r2, [r3, #28] 8012664: 68fb ldr r3, [r7, #12] 8012666: 681b ldr r3, [r3, #0] 8012668: f422 6280 bic.w r2, r2, #1024 @ 0x400 801266c: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 801266e: 68fb ldr r3, [r7, #12] 8012670: 681b ldr r3, [r3, #0] 8012672: 69d9 ldr r1, [r3, #28] 8012674: 68bb ldr r3, [r7, #8] 8012676: 691b ldr r3, [r3, #16] 8012678: 021a lsls r2, r3, #8 801267a: 68fb ldr r3, [r7, #12] 801267c: 681b ldr r3, [r3, #0] 801267e: 430a orrs r2, r1 8012680: 61da str r2, [r3, #28] break; 8012682: e002 b.n 801268a } default: status = HAL_ERROR; 8012684: 2301 movs r3, #1 8012686: 75fb strb r3, [r7, #23] break; 8012688: bf00 nop } __HAL_UNLOCK(htim); 801268a: 68fb ldr r3, [r7, #12] 801268c: 2200 movs r2, #0 801268e: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8012692: 7dfb ldrb r3, [r7, #23] } 8012694: 4618 mov r0, r3 8012696: 3718 adds r7, #24 8012698: 46bd mov sp, r7 801269a: bd80 pop {r7, pc} 0801269c : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 801269c: b580 push {r7, lr} 801269e: b084 sub sp, #16 80126a0: af00 add r7, sp, #0 80126a2: 6078 str r0, [r7, #4] 80126a4: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 80126a6: 2300 movs r3, #0 80126a8: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 80126aa: 687b ldr r3, [r7, #4] 80126ac: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80126b0: 2b01 cmp r3, #1 80126b2: d101 bne.n 80126b8 80126b4: 2302 movs r3, #2 80126b6: e0b4 b.n 8012822 80126b8: 687b ldr r3, [r7, #4] 80126ba: 2201 movs r2, #1 80126bc: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 80126c0: 687b ldr r3, [r7, #4] 80126c2: 2202 movs r2, #2 80126c4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 80126c8: 687b ldr r3, [r7, #4] 80126ca: 681b ldr r3, [r3, #0] 80126cc: 689b ldr r3, [r3, #8] 80126ce: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 80126d0: 68bb ldr r3, [r7, #8] 80126d2: f023 0377 bic.w r3, r3, #119 @ 0x77 80126d6: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80126d8: 68bb ldr r3, [r7, #8] 80126da: f423 437f bic.w r3, r3, #65280 @ 0xff00 80126de: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 80126e0: 687b ldr r3, [r7, #4] 80126e2: 681b ldr r3, [r3, #0] 80126e4: 68ba ldr r2, [r7, #8] 80126e6: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 80126e8: 683b ldr r3, [r7, #0] 80126ea: 681b ldr r3, [r3, #0] 80126ec: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80126f0: d03e beq.n 8012770 80126f2: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80126f6: f200 8087 bhi.w 8012808 80126fa: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80126fe: f000 8086 beq.w 801280e 8012702: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012706: d87f bhi.n 8012808 8012708: 2b70 cmp r3, #112 @ 0x70 801270a: d01a beq.n 8012742 801270c: 2b70 cmp r3, #112 @ 0x70 801270e: d87b bhi.n 8012808 8012710: 2b60 cmp r3, #96 @ 0x60 8012712: d050 beq.n 80127b6 8012714: 2b60 cmp r3, #96 @ 0x60 8012716: d877 bhi.n 8012808 8012718: 2b50 cmp r3, #80 @ 0x50 801271a: d03c beq.n 8012796 801271c: 2b50 cmp r3, #80 @ 0x50 801271e: d873 bhi.n 8012808 8012720: 2b40 cmp r3, #64 @ 0x40 8012722: d058 beq.n 80127d6 8012724: 2b40 cmp r3, #64 @ 0x40 8012726: d86f bhi.n 8012808 8012728: 2b30 cmp r3, #48 @ 0x30 801272a: d064 beq.n 80127f6 801272c: 2b30 cmp r3, #48 @ 0x30 801272e: d86b bhi.n 8012808 8012730: 2b20 cmp r3, #32 8012732: d060 beq.n 80127f6 8012734: 2b20 cmp r3, #32 8012736: d867 bhi.n 8012808 8012738: 2b00 cmp r3, #0 801273a: d05c beq.n 80127f6 801273c: 2b10 cmp r3, #16 801273e: d05a beq.n 80127f6 8012740: e062 b.n 8012808 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8012742: 687b ldr r3, [r7, #4] 8012744: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8012746: 683b ldr r3, [r7, #0] 8012748: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 801274a: 683b ldr r3, [r7, #0] 801274c: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 801274e: 683b ldr r3, [r7, #0] 8012750: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8012752: f000 fb0e bl 8012d72 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 8012756: 687b ldr r3, [r7, #4] 8012758: 681b ldr r3, [r3, #0] 801275a: 689b ldr r3, [r3, #8] 801275c: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 801275e: 68bb ldr r3, [r7, #8] 8012760: f043 0377 orr.w r3, r3, #119 @ 0x77 8012764: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8012766: 687b ldr r3, [r7, #4] 8012768: 681b ldr r3, [r3, #0] 801276a: 68ba ldr r2, [r7, #8] 801276c: 609a str r2, [r3, #8] break; 801276e: e04f b.n 8012810 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8012770: 687b ldr r3, [r7, #4] 8012772: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8012774: 683b ldr r3, [r7, #0] 8012776: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 8012778: 683b ldr r3, [r7, #0] 801277a: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 801277c: 683b ldr r3, [r7, #0] 801277e: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8012780: f000 faf7 bl 8012d72 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 8012784: 687b ldr r3, [r7, #4] 8012786: 681b ldr r3, [r3, #0] 8012788: 689a ldr r2, [r3, #8] 801278a: 687b ldr r3, [r7, #4] 801278c: 681b ldr r3, [r3, #0] 801278e: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8012792: 609a str r2, [r3, #8] break; 8012794: e03c b.n 8012810 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8012796: 687b ldr r3, [r7, #4] 8012798: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 801279a: 683b ldr r3, [r7, #0] 801279c: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 801279e: 683b ldr r3, [r7, #0] 80127a0: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 80127a2: 461a mov r2, r3 80127a4: f000 fa6e bl 8012c84 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 80127a8: 687b ldr r3, [r7, #4] 80127aa: 681b ldr r3, [r3, #0] 80127ac: 2150 movs r1, #80 @ 0x50 80127ae: 4618 mov r0, r3 80127b0: f000 fac5 bl 8012d3e break; 80127b4: e02c b.n 8012810 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 80127b6: 687b ldr r3, [r7, #4] 80127b8: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80127ba: 683b ldr r3, [r7, #0] 80127bc: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80127be: 683b ldr r3, [r7, #0] 80127c0: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 80127c2: 461a mov r2, r3 80127c4: f000 fa8c bl 8012ce0 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 80127c8: 687b ldr r3, [r7, #4] 80127ca: 681b ldr r3, [r3, #0] 80127cc: 2160 movs r1, #96 @ 0x60 80127ce: 4618 mov r0, r3 80127d0: f000 fab5 bl 8012d3e break; 80127d4: e01c b.n 8012810 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 80127d6: 687b ldr r3, [r7, #4] 80127d8: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80127da: 683b ldr r3, [r7, #0] 80127dc: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80127de: 683b ldr r3, [r7, #0] 80127e0: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 80127e2: 461a mov r2, r3 80127e4: f000 fa4e bl 8012c84 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 80127e8: 687b ldr r3, [r7, #4] 80127ea: 681b ldr r3, [r3, #0] 80127ec: 2140 movs r1, #64 @ 0x40 80127ee: 4618 mov r0, r3 80127f0: f000 faa5 bl 8012d3e break; 80127f4: e00c b.n 8012810 case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 80127f6: 687b ldr r3, [r7, #4] 80127f8: 681a ldr r2, [r3, #0] 80127fa: 683b ldr r3, [r7, #0] 80127fc: 681b ldr r3, [r3, #0] 80127fe: 4619 mov r1, r3 8012800: 4610 mov r0, r2 8012802: f000 fa9c bl 8012d3e break; 8012806: e003 b.n 8012810 } default: status = HAL_ERROR; 8012808: 2301 movs r3, #1 801280a: 73fb strb r3, [r7, #15] break; 801280c: e000 b.n 8012810 break; 801280e: bf00 nop } htim->State = HAL_TIM_STATE_READY; 8012810: 687b ldr r3, [r7, #4] 8012812: 2201 movs r2, #1 8012814: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8012818: 687b ldr r3, [r7, #4] 801281a: 2200 movs r2, #0 801281c: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8012820: 7bfb ldrb r3, [r7, #15] } 8012822: 4618 mov r0, r3 8012824: 3710 adds r7, #16 8012826: 46bd mov sp, r7 8012828: bd80 pop {r7, pc} 0801282a : * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 801282a: b480 push {r7} 801282c: b083 sub sp, #12 801282e: af00 add r7, sp, #0 8012830: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } 8012832: bf00 nop 8012834: 370c adds r7, #12 8012836: 46bd mov sp, r7 8012838: bc80 pop {r7} 801283a: 4770 bx lr 0801283c : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 801283c: b480 push {r7} 801283e: b083 sub sp, #12 8012840: af00 add r7, sp, #0 8012842: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 8012844: bf00 nop 8012846: 370c adds r7, #12 8012848: 46bd mov sp, r7 801284a: bc80 pop {r7} 801284c: 4770 bx lr 0801284e : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 801284e: b480 push {r7} 8012850: b083 sub sp, #12 8012852: af00 add r7, sp, #0 8012854: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 8012856: bf00 nop 8012858: 370c adds r7, #12 801285a: 46bd mov sp, r7 801285c: bc80 pop {r7} 801285e: 4770 bx lr 08012860 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8012860: b480 push {r7} 8012862: b083 sub sp, #12 8012864: af00 add r7, sp, #0 8012866: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8012868: bf00 nop 801286a: 370c adds r7, #12 801286c: 46bd mov sp, r7 801286e: bc80 pop {r7} 8012870: 4770 bx lr 08012872 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 8012872: b480 push {r7} 8012874: b083 sub sp, #12 8012876: af00 add r7, sp, #0 8012878: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 801287a: bf00 nop 801287c: 370c adds r7, #12 801287e: 46bd mov sp, r7 8012880: bc80 pop {r7} 8012882: 4770 bx lr 08012884 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8012884: b480 push {r7} 8012886: b085 sub sp, #20 8012888: af00 add r7, sp, #0 801288a: 6078 str r0, [r7, #4] 801288c: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 801288e: 687b ldr r3, [r7, #4] 8012890: 681b ldr r3, [r3, #0] 8012892: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8012894: 687b ldr r3, [r7, #4] 8012896: 4a33 ldr r2, [pc, #204] @ (8012964 ) 8012898: 4293 cmp r3, r2 801289a: d00f beq.n 80128bc 801289c: 687b ldr r3, [r7, #4] 801289e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80128a2: d00b beq.n 80128bc 80128a4: 687b ldr r3, [r7, #4] 80128a6: 4a30 ldr r2, [pc, #192] @ (8012968 ) 80128a8: 4293 cmp r3, r2 80128aa: d007 beq.n 80128bc 80128ac: 687b ldr r3, [r7, #4] 80128ae: 4a2f ldr r2, [pc, #188] @ (801296c ) 80128b0: 4293 cmp r3, r2 80128b2: d003 beq.n 80128bc 80128b4: 687b ldr r3, [r7, #4] 80128b6: 4a2e ldr r2, [pc, #184] @ (8012970 ) 80128b8: 4293 cmp r3, r2 80128ba: d108 bne.n 80128ce { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80128bc: 68fb ldr r3, [r7, #12] 80128be: f023 0370 bic.w r3, r3, #112 @ 0x70 80128c2: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80128c4: 683b ldr r3, [r7, #0] 80128c6: 685b ldr r3, [r3, #4] 80128c8: 68fa ldr r2, [r7, #12] 80128ca: 4313 orrs r3, r2 80128cc: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80128ce: 687b ldr r3, [r7, #4] 80128d0: 4a24 ldr r2, [pc, #144] @ (8012964 ) 80128d2: 4293 cmp r3, r2 80128d4: d00f beq.n 80128f6 80128d6: 687b ldr r3, [r7, #4] 80128d8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80128dc: d00b beq.n 80128f6 80128de: 687b ldr r3, [r7, #4] 80128e0: 4a21 ldr r2, [pc, #132] @ (8012968 ) 80128e2: 4293 cmp r3, r2 80128e4: d007 beq.n 80128f6 80128e6: 687b ldr r3, [r7, #4] 80128e8: 4a20 ldr r2, [pc, #128] @ (801296c ) 80128ea: 4293 cmp r3, r2 80128ec: d003 beq.n 80128f6 80128ee: 687b ldr r3, [r7, #4] 80128f0: 4a1f ldr r2, [pc, #124] @ (8012970 ) 80128f2: 4293 cmp r3, r2 80128f4: d108 bne.n 8012908 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 80128f6: 68fb ldr r3, [r7, #12] 80128f8: f423 7340 bic.w r3, r3, #768 @ 0x300 80128fc: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80128fe: 683b ldr r3, [r7, #0] 8012900: 68db ldr r3, [r3, #12] 8012902: 68fa ldr r2, [r7, #12] 8012904: 4313 orrs r3, r2 8012906: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8012908: 68fb ldr r3, [r7, #12] 801290a: f023 0280 bic.w r2, r3, #128 @ 0x80 801290e: 683b ldr r3, [r7, #0] 8012910: 695b ldr r3, [r3, #20] 8012912: 4313 orrs r3, r2 8012914: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 8012916: 687b ldr r3, [r7, #4] 8012918: 68fa ldr r2, [r7, #12] 801291a: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 801291c: 683b ldr r3, [r7, #0] 801291e: 689a ldr r2, [r3, #8] 8012920: 687b ldr r3, [r7, #4] 8012922: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8012924: 683b ldr r3, [r7, #0] 8012926: 681a ldr r2, [r3, #0] 8012928: 687b ldr r3, [r7, #4] 801292a: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 801292c: 687b ldr r3, [r7, #4] 801292e: 4a0d ldr r2, [pc, #52] @ (8012964 ) 8012930: 4293 cmp r3, r2 8012932: d103 bne.n 801293c { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8012934: 683b ldr r3, [r7, #0] 8012936: 691a ldr r2, [r3, #16] 8012938: 687b ldr r3, [r7, #4] 801293a: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 801293c: 687b ldr r3, [r7, #4] 801293e: 2201 movs r2, #1 8012940: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 8012942: 687b ldr r3, [r7, #4] 8012944: 691b ldr r3, [r3, #16] 8012946: f003 0301 and.w r3, r3, #1 801294a: 2b00 cmp r3, #0 801294c: d005 beq.n 801295a { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 801294e: 687b ldr r3, [r7, #4] 8012950: 691b ldr r3, [r3, #16] 8012952: f023 0201 bic.w r2, r3, #1 8012956: 687b ldr r3, [r7, #4] 8012958: 611a str r2, [r3, #16] } } 801295a: bf00 nop 801295c: 3714 adds r7, #20 801295e: 46bd mov sp, r7 8012960: bc80 pop {r7} 8012962: 4770 bx lr 8012964: 40012c00 .word 0x40012c00 8012968: 40000400 .word 0x40000400 801296c: 40000800 .word 0x40000800 8012970: 40000c00 .word 0x40000c00 08012974 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8012974: b480 push {r7} 8012976: b087 sub sp, #28 8012978: af00 add r7, sp, #0 801297a: 6078 str r0, [r7, #4] 801297c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 801297e: 687b ldr r3, [r7, #4] 8012980: 6a1b ldr r3, [r3, #32] 8012982: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 8012984: 687b ldr r3, [r7, #4] 8012986: 6a1b ldr r3, [r3, #32] 8012988: f023 0201 bic.w r2, r3, #1 801298c: 687b ldr r3, [r7, #4] 801298e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8012990: 687b ldr r3, [r7, #4] 8012992: 685b ldr r3, [r3, #4] 8012994: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8012996: 687b ldr r3, [r7, #4] 8012998: 699b ldr r3, [r3, #24] 801299a: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 801299c: 68fb ldr r3, [r7, #12] 801299e: f023 0370 bic.w r3, r3, #112 @ 0x70 80129a2: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 80129a4: 68fb ldr r3, [r7, #12] 80129a6: f023 0303 bic.w r3, r3, #3 80129aa: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80129ac: 683b ldr r3, [r7, #0] 80129ae: 681b ldr r3, [r3, #0] 80129b0: 68fa ldr r2, [r7, #12] 80129b2: 4313 orrs r3, r2 80129b4: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 80129b6: 697b ldr r3, [r7, #20] 80129b8: f023 0302 bic.w r3, r3, #2 80129bc: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 80129be: 683b ldr r3, [r7, #0] 80129c0: 689b ldr r3, [r3, #8] 80129c2: 697a ldr r2, [r7, #20] 80129c4: 4313 orrs r3, r2 80129c6: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 80129c8: 687b ldr r3, [r7, #4] 80129ca: 4a1c ldr r2, [pc, #112] @ (8012a3c ) 80129cc: 4293 cmp r3, r2 80129ce: d10c bne.n 80129ea { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 80129d0: 697b ldr r3, [r7, #20] 80129d2: f023 0308 bic.w r3, r3, #8 80129d6: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 80129d8: 683b ldr r3, [r7, #0] 80129da: 68db ldr r3, [r3, #12] 80129dc: 697a ldr r2, [r7, #20] 80129de: 4313 orrs r3, r2 80129e0: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 80129e2: 697b ldr r3, [r7, #20] 80129e4: f023 0304 bic.w r3, r3, #4 80129e8: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80129ea: 687b ldr r3, [r7, #4] 80129ec: 4a13 ldr r2, [pc, #76] @ (8012a3c ) 80129ee: 4293 cmp r3, r2 80129f0: d111 bne.n 8012a16 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 80129f2: 693b ldr r3, [r7, #16] 80129f4: f423 7380 bic.w r3, r3, #256 @ 0x100 80129f8: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 80129fa: 693b ldr r3, [r7, #16] 80129fc: f423 7300 bic.w r3, r3, #512 @ 0x200 8012a00: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 8012a02: 683b ldr r3, [r7, #0] 8012a04: 695b ldr r3, [r3, #20] 8012a06: 693a ldr r2, [r7, #16] 8012a08: 4313 orrs r3, r2 8012a0a: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 8012a0c: 683b ldr r3, [r7, #0] 8012a0e: 699b ldr r3, [r3, #24] 8012a10: 693a ldr r2, [r7, #16] 8012a12: 4313 orrs r3, r2 8012a14: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8012a16: 687b ldr r3, [r7, #4] 8012a18: 693a ldr r2, [r7, #16] 8012a1a: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8012a1c: 687b ldr r3, [r7, #4] 8012a1e: 68fa ldr r2, [r7, #12] 8012a20: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 8012a22: 683b ldr r3, [r7, #0] 8012a24: 685a ldr r2, [r3, #4] 8012a26: 687b ldr r3, [r7, #4] 8012a28: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8012a2a: 687b ldr r3, [r7, #4] 8012a2c: 697a ldr r2, [r7, #20] 8012a2e: 621a str r2, [r3, #32] } 8012a30: bf00 nop 8012a32: 371c adds r7, #28 8012a34: 46bd mov sp, r7 8012a36: bc80 pop {r7} 8012a38: 4770 bx lr 8012a3a: bf00 nop 8012a3c: 40012c00 .word 0x40012c00 08012a40 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8012a40: b480 push {r7} 8012a42: b087 sub sp, #28 8012a44: af00 add r7, sp, #0 8012a46: 6078 str r0, [r7, #4] 8012a48: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8012a4a: 687b ldr r3, [r7, #4] 8012a4c: 6a1b ldr r3, [r3, #32] 8012a4e: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8012a50: 687b ldr r3, [r7, #4] 8012a52: 6a1b ldr r3, [r3, #32] 8012a54: f023 0210 bic.w r2, r3, #16 8012a58: 687b ldr r3, [r7, #4] 8012a5a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8012a5c: 687b ldr r3, [r7, #4] 8012a5e: 685b ldr r3, [r3, #4] 8012a60: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8012a62: 687b ldr r3, [r7, #4] 8012a64: 699b ldr r3, [r3, #24] 8012a66: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 8012a68: 68fb ldr r3, [r7, #12] 8012a6a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8012a6e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 8012a70: 68fb ldr r3, [r7, #12] 8012a72: f423 7340 bic.w r3, r3, #768 @ 0x300 8012a76: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8012a78: 683b ldr r3, [r7, #0] 8012a7a: 681b ldr r3, [r3, #0] 8012a7c: 021b lsls r3, r3, #8 8012a7e: 68fa ldr r2, [r7, #12] 8012a80: 4313 orrs r3, r2 8012a82: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 8012a84: 697b ldr r3, [r7, #20] 8012a86: f023 0320 bic.w r3, r3, #32 8012a8a: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 8012a8c: 683b ldr r3, [r7, #0] 8012a8e: 689b ldr r3, [r3, #8] 8012a90: 011b lsls r3, r3, #4 8012a92: 697a ldr r2, [r7, #20] 8012a94: 4313 orrs r3, r2 8012a96: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 8012a98: 687b ldr r3, [r7, #4] 8012a9a: 4a1d ldr r2, [pc, #116] @ (8012b10 ) 8012a9c: 4293 cmp r3, r2 8012a9e: d10d bne.n 8012abc { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 8012aa0: 697b ldr r3, [r7, #20] 8012aa2: f023 0380 bic.w r3, r3, #128 @ 0x80 8012aa6: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8012aa8: 683b ldr r3, [r7, #0] 8012aaa: 68db ldr r3, [r3, #12] 8012aac: 011b lsls r3, r3, #4 8012aae: 697a ldr r2, [r7, #20] 8012ab0: 4313 orrs r3, r2 8012ab2: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8012ab4: 697b ldr r3, [r7, #20] 8012ab6: f023 0340 bic.w r3, r3, #64 @ 0x40 8012aba: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8012abc: 687b ldr r3, [r7, #4] 8012abe: 4a14 ldr r2, [pc, #80] @ (8012b10 ) 8012ac0: 4293 cmp r3, r2 8012ac2: d113 bne.n 8012aec /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8012ac4: 693b ldr r3, [r7, #16] 8012ac6: f423 6380 bic.w r3, r3, #1024 @ 0x400 8012aca: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8012acc: 693b ldr r3, [r7, #16] 8012ace: f423 6300 bic.w r3, r3, #2048 @ 0x800 8012ad2: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8012ad4: 683b ldr r3, [r7, #0] 8012ad6: 695b ldr r3, [r3, #20] 8012ad8: 009b lsls r3, r3, #2 8012ada: 693a ldr r2, [r7, #16] 8012adc: 4313 orrs r3, r2 8012ade: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8012ae0: 683b ldr r3, [r7, #0] 8012ae2: 699b ldr r3, [r3, #24] 8012ae4: 009b lsls r3, r3, #2 8012ae6: 693a ldr r2, [r7, #16] 8012ae8: 4313 orrs r3, r2 8012aea: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8012aec: 687b ldr r3, [r7, #4] 8012aee: 693a ldr r2, [r7, #16] 8012af0: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8012af2: 687b ldr r3, [r7, #4] 8012af4: 68fa ldr r2, [r7, #12] 8012af6: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8012af8: 683b ldr r3, [r7, #0] 8012afa: 685a ldr r2, [r3, #4] 8012afc: 687b ldr r3, [r7, #4] 8012afe: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8012b00: 687b ldr r3, [r7, #4] 8012b02: 697a ldr r2, [r7, #20] 8012b04: 621a str r2, [r3, #32] } 8012b06: bf00 nop 8012b08: 371c adds r7, #28 8012b0a: 46bd mov sp, r7 8012b0c: bc80 pop {r7} 8012b0e: 4770 bx lr 8012b10: 40012c00 .word 0x40012c00 08012b14 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8012b14: b480 push {r7} 8012b16: b087 sub sp, #28 8012b18: af00 add r7, sp, #0 8012b1a: 6078 str r0, [r7, #4] 8012b1c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8012b1e: 687b ldr r3, [r7, #4] 8012b20: 6a1b ldr r3, [r3, #32] 8012b22: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8012b24: 687b ldr r3, [r7, #4] 8012b26: 6a1b ldr r3, [r3, #32] 8012b28: f423 7280 bic.w r2, r3, #256 @ 0x100 8012b2c: 687b ldr r3, [r7, #4] 8012b2e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8012b30: 687b ldr r3, [r7, #4] 8012b32: 685b ldr r3, [r3, #4] 8012b34: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8012b36: 687b ldr r3, [r7, #4] 8012b38: 69db ldr r3, [r3, #28] 8012b3a: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8012b3c: 68fb ldr r3, [r7, #12] 8012b3e: f023 0370 bic.w r3, r3, #112 @ 0x70 8012b42: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8012b44: 68fb ldr r3, [r7, #12] 8012b46: f023 0303 bic.w r3, r3, #3 8012b4a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8012b4c: 683b ldr r3, [r7, #0] 8012b4e: 681b ldr r3, [r3, #0] 8012b50: 68fa ldr r2, [r7, #12] 8012b52: 4313 orrs r3, r2 8012b54: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8012b56: 697b ldr r3, [r7, #20] 8012b58: f423 7300 bic.w r3, r3, #512 @ 0x200 8012b5c: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 8012b5e: 683b ldr r3, [r7, #0] 8012b60: 689b ldr r3, [r3, #8] 8012b62: 021b lsls r3, r3, #8 8012b64: 697a ldr r2, [r7, #20] 8012b66: 4313 orrs r3, r2 8012b68: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8012b6a: 687b ldr r3, [r7, #4] 8012b6c: 4a1d ldr r2, [pc, #116] @ (8012be4 ) 8012b6e: 4293 cmp r3, r2 8012b70: d10d bne.n 8012b8e { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8012b72: 697b ldr r3, [r7, #20] 8012b74: f423 6300 bic.w r3, r3, #2048 @ 0x800 8012b78: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 8012b7a: 683b ldr r3, [r7, #0] 8012b7c: 68db ldr r3, [r3, #12] 8012b7e: 021b lsls r3, r3, #8 8012b80: 697a ldr r2, [r7, #20] 8012b82: 4313 orrs r3, r2 8012b84: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8012b86: 697b ldr r3, [r7, #20] 8012b88: f423 6380 bic.w r3, r3, #1024 @ 0x400 8012b8c: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8012b8e: 687b ldr r3, [r7, #4] 8012b90: 4a14 ldr r2, [pc, #80] @ (8012be4 ) 8012b92: 4293 cmp r3, r2 8012b94: d113 bne.n 8012bbe /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8012b96: 693b ldr r3, [r7, #16] 8012b98: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8012b9c: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 8012b9e: 693b ldr r3, [r7, #16] 8012ba0: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8012ba4: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8012ba6: 683b ldr r3, [r7, #0] 8012ba8: 695b ldr r3, [r3, #20] 8012baa: 011b lsls r3, r3, #4 8012bac: 693a ldr r2, [r7, #16] 8012bae: 4313 orrs r3, r2 8012bb0: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 8012bb2: 683b ldr r3, [r7, #0] 8012bb4: 699b ldr r3, [r3, #24] 8012bb6: 011b lsls r3, r3, #4 8012bb8: 693a ldr r2, [r7, #16] 8012bba: 4313 orrs r3, r2 8012bbc: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8012bbe: 687b ldr r3, [r7, #4] 8012bc0: 693a ldr r2, [r7, #16] 8012bc2: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8012bc4: 687b ldr r3, [r7, #4] 8012bc6: 68fa ldr r2, [r7, #12] 8012bc8: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8012bca: 683b ldr r3, [r7, #0] 8012bcc: 685a ldr r2, [r3, #4] 8012bce: 687b ldr r3, [r7, #4] 8012bd0: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8012bd2: 687b ldr r3, [r7, #4] 8012bd4: 697a ldr r2, [r7, #20] 8012bd6: 621a str r2, [r3, #32] } 8012bd8: bf00 nop 8012bda: 371c adds r7, #28 8012bdc: 46bd mov sp, r7 8012bde: bc80 pop {r7} 8012be0: 4770 bx lr 8012be2: bf00 nop 8012be4: 40012c00 .word 0x40012c00 08012be8 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8012be8: b480 push {r7} 8012bea: b087 sub sp, #28 8012bec: af00 add r7, sp, #0 8012bee: 6078 str r0, [r7, #4] 8012bf0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8012bf2: 687b ldr r3, [r7, #4] 8012bf4: 6a1b ldr r3, [r3, #32] 8012bf6: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8012bf8: 687b ldr r3, [r7, #4] 8012bfa: 6a1b ldr r3, [r3, #32] 8012bfc: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8012c00: 687b ldr r3, [r7, #4] 8012c02: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8012c04: 687b ldr r3, [r7, #4] 8012c06: 685b ldr r3, [r3, #4] 8012c08: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8012c0a: 687b ldr r3, [r7, #4] 8012c0c: 69db ldr r3, [r3, #28] 8012c0e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8012c10: 68fb ldr r3, [r7, #12] 8012c12: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8012c16: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8012c18: 68fb ldr r3, [r7, #12] 8012c1a: f423 7340 bic.w r3, r3, #768 @ 0x300 8012c1e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8012c20: 683b ldr r3, [r7, #0] 8012c22: 681b ldr r3, [r3, #0] 8012c24: 021b lsls r3, r3, #8 8012c26: 68fa ldr r2, [r7, #12] 8012c28: 4313 orrs r3, r2 8012c2a: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8012c2c: 693b ldr r3, [r7, #16] 8012c2e: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8012c32: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8012c34: 683b ldr r3, [r7, #0] 8012c36: 689b ldr r3, [r3, #8] 8012c38: 031b lsls r3, r3, #12 8012c3a: 693a ldr r2, [r7, #16] 8012c3c: 4313 orrs r3, r2 8012c3e: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8012c40: 687b ldr r3, [r7, #4] 8012c42: 4a0f ldr r2, [pc, #60] @ (8012c80 ) 8012c44: 4293 cmp r3, r2 8012c46: d109 bne.n 8012c5c { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8012c48: 697b ldr r3, [r7, #20] 8012c4a: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8012c4e: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8012c50: 683b ldr r3, [r7, #0] 8012c52: 695b ldr r3, [r3, #20] 8012c54: 019b lsls r3, r3, #6 8012c56: 697a ldr r2, [r7, #20] 8012c58: 4313 orrs r3, r2 8012c5a: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8012c5c: 687b ldr r3, [r7, #4] 8012c5e: 697a ldr r2, [r7, #20] 8012c60: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8012c62: 687b ldr r3, [r7, #4] 8012c64: 68fa ldr r2, [r7, #12] 8012c66: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8012c68: 683b ldr r3, [r7, #0] 8012c6a: 685a ldr r2, [r3, #4] 8012c6c: 687b ldr r3, [r7, #4] 8012c6e: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8012c70: 687b ldr r3, [r7, #4] 8012c72: 693a ldr r2, [r7, #16] 8012c74: 621a str r2, [r3, #32] } 8012c76: bf00 nop 8012c78: 371c adds r7, #28 8012c7a: 46bd mov sp, r7 8012c7c: bc80 pop {r7} 8012c7e: 4770 bx lr 8012c80: 40012c00 .word 0x40012c00 08012c84 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8012c84: b480 push {r7} 8012c86: b087 sub sp, #28 8012c88: af00 add r7, sp, #0 8012c8a: 60f8 str r0, [r7, #12] 8012c8c: 60b9 str r1, [r7, #8] 8012c8e: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8012c90: 68fb ldr r3, [r7, #12] 8012c92: 6a1b ldr r3, [r3, #32] 8012c94: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8012c96: 68fb ldr r3, [r7, #12] 8012c98: 6a1b ldr r3, [r3, #32] 8012c9a: f023 0201 bic.w r2, r3, #1 8012c9e: 68fb ldr r3, [r7, #12] 8012ca0: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8012ca2: 68fb ldr r3, [r7, #12] 8012ca4: 699b ldr r3, [r3, #24] 8012ca6: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8012ca8: 693b ldr r3, [r7, #16] 8012caa: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8012cae: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8012cb0: 687b ldr r3, [r7, #4] 8012cb2: 011b lsls r3, r3, #4 8012cb4: 693a ldr r2, [r7, #16] 8012cb6: 4313 orrs r3, r2 8012cb8: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8012cba: 697b ldr r3, [r7, #20] 8012cbc: f023 030a bic.w r3, r3, #10 8012cc0: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8012cc2: 697a ldr r2, [r7, #20] 8012cc4: 68bb ldr r3, [r7, #8] 8012cc6: 4313 orrs r3, r2 8012cc8: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8012cca: 68fb ldr r3, [r7, #12] 8012ccc: 693a ldr r2, [r7, #16] 8012cce: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8012cd0: 68fb ldr r3, [r7, #12] 8012cd2: 697a ldr r2, [r7, #20] 8012cd4: 621a str r2, [r3, #32] } 8012cd6: bf00 nop 8012cd8: 371c adds r7, #28 8012cda: 46bd mov sp, r7 8012cdc: bc80 pop {r7} 8012cde: 4770 bx lr 08012ce0 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8012ce0: b480 push {r7} 8012ce2: b087 sub sp, #28 8012ce4: af00 add r7, sp, #0 8012ce6: 60f8 str r0, [r7, #12] 8012ce8: 60b9 str r1, [r7, #8] 8012cea: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8012cec: 68fb ldr r3, [r7, #12] 8012cee: 6a1b ldr r3, [r3, #32] 8012cf0: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8012cf2: 68fb ldr r3, [r7, #12] 8012cf4: 6a1b ldr r3, [r3, #32] 8012cf6: f023 0210 bic.w r2, r3, #16 8012cfa: 68fb ldr r3, [r7, #12] 8012cfc: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8012cfe: 68fb ldr r3, [r7, #12] 8012d00: 699b ldr r3, [r3, #24] 8012d02: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8012d04: 693b ldr r3, [r7, #16] 8012d06: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8012d0a: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8012d0c: 687b ldr r3, [r7, #4] 8012d0e: 031b lsls r3, r3, #12 8012d10: 693a ldr r2, [r7, #16] 8012d12: 4313 orrs r3, r2 8012d14: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8012d16: 697b ldr r3, [r7, #20] 8012d18: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8012d1c: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8012d1e: 68bb ldr r3, [r7, #8] 8012d20: 011b lsls r3, r3, #4 8012d22: 697a ldr r2, [r7, #20] 8012d24: 4313 orrs r3, r2 8012d26: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8012d28: 68fb ldr r3, [r7, #12] 8012d2a: 693a ldr r2, [r7, #16] 8012d2c: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8012d2e: 68fb ldr r3, [r7, #12] 8012d30: 697a ldr r2, [r7, #20] 8012d32: 621a str r2, [r3, #32] } 8012d34: bf00 nop 8012d36: 371c adds r7, #28 8012d38: 46bd mov sp, r7 8012d3a: bc80 pop {r7} 8012d3c: 4770 bx lr 08012d3e : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8012d3e: b480 push {r7} 8012d40: b085 sub sp, #20 8012d42: af00 add r7, sp, #0 8012d44: 6078 str r0, [r7, #4] 8012d46: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8012d48: 687b ldr r3, [r7, #4] 8012d4a: 689b ldr r3, [r3, #8] 8012d4c: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8012d4e: 68fb ldr r3, [r7, #12] 8012d50: f023 0370 bic.w r3, r3, #112 @ 0x70 8012d54: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8012d56: 683a ldr r2, [r7, #0] 8012d58: 68fb ldr r3, [r7, #12] 8012d5a: 4313 orrs r3, r2 8012d5c: f043 0307 orr.w r3, r3, #7 8012d60: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8012d62: 687b ldr r3, [r7, #4] 8012d64: 68fa ldr r2, [r7, #12] 8012d66: 609a str r2, [r3, #8] } 8012d68: bf00 nop 8012d6a: 3714 adds r7, #20 8012d6c: 46bd mov sp, r7 8012d6e: bc80 pop {r7} 8012d70: 4770 bx lr 08012d72 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8012d72: b480 push {r7} 8012d74: b087 sub sp, #28 8012d76: af00 add r7, sp, #0 8012d78: 60f8 str r0, [r7, #12] 8012d7a: 60b9 str r1, [r7, #8] 8012d7c: 607a str r2, [r7, #4] 8012d7e: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8012d80: 68fb ldr r3, [r7, #12] 8012d82: 689b ldr r3, [r3, #8] 8012d84: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8012d86: 697b ldr r3, [r7, #20] 8012d88: f423 437f bic.w r3, r3, #65280 @ 0xff00 8012d8c: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8012d8e: 683b ldr r3, [r7, #0] 8012d90: 021a lsls r2, r3, #8 8012d92: 687b ldr r3, [r7, #4] 8012d94: 431a orrs r2, r3 8012d96: 68bb ldr r3, [r7, #8] 8012d98: 4313 orrs r3, r2 8012d9a: 697a ldr r2, [r7, #20] 8012d9c: 4313 orrs r3, r2 8012d9e: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8012da0: 68fb ldr r3, [r7, #12] 8012da2: 697a ldr r2, [r7, #20] 8012da4: 609a str r2, [r3, #8] } 8012da6: bf00 nop 8012da8: 371c adds r7, #28 8012daa: 46bd mov sp, r7 8012dac: bc80 pop {r7} 8012dae: 4770 bx lr 08012db0 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8012db0: b480 push {r7} 8012db2: b087 sub sp, #28 8012db4: af00 add r7, sp, #0 8012db6: 60f8 str r0, [r7, #12] 8012db8: 60b9 str r1, [r7, #8] 8012dba: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8012dbc: 68bb ldr r3, [r7, #8] 8012dbe: f003 031f and.w r3, r3, #31 8012dc2: 2201 movs r2, #1 8012dc4: fa02 f303 lsl.w r3, r2, r3 8012dc8: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 8012dca: 68fb ldr r3, [r7, #12] 8012dcc: 6a1a ldr r2, [r3, #32] 8012dce: 697b ldr r3, [r7, #20] 8012dd0: 43db mvns r3, r3 8012dd2: 401a ands r2, r3 8012dd4: 68fb ldr r3, [r7, #12] 8012dd6: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8012dd8: 68fb ldr r3, [r7, #12] 8012dda: 6a1a ldr r2, [r3, #32] 8012ddc: 68bb ldr r3, [r7, #8] 8012dde: f003 031f and.w r3, r3, #31 8012de2: 6879 ldr r1, [r7, #4] 8012de4: fa01 f303 lsl.w r3, r1, r3 8012de8: 431a orrs r2, r3 8012dea: 68fb ldr r3, [r7, #12] 8012dec: 621a str r2, [r3, #32] } 8012dee: bf00 nop 8012df0: 371c adds r7, #28 8012df2: 46bd mov sp, r7 8012df4: bc80 pop {r7} 8012df6: 4770 bx lr 08012df8 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8012df8: b480 push {r7} 8012dfa: b085 sub sp, #20 8012dfc: af00 add r7, sp, #0 8012dfe: 6078 str r0, [r7, #4] 8012e00: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8012e02: 687b ldr r3, [r7, #4] 8012e04: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8012e08: 2b01 cmp r3, #1 8012e0a: d101 bne.n 8012e10 8012e0c: 2302 movs r3, #2 8012e0e: e04b b.n 8012ea8 8012e10: 687b ldr r3, [r7, #4] 8012e12: 2201 movs r2, #1 8012e14: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8012e18: 687b ldr r3, [r7, #4] 8012e1a: 2202 movs r2, #2 8012e1c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8012e20: 687b ldr r3, [r7, #4] 8012e22: 681b ldr r3, [r3, #0] 8012e24: 685b ldr r3, [r3, #4] 8012e26: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8012e28: 687b ldr r3, [r7, #4] 8012e2a: 681b ldr r3, [r3, #0] 8012e2c: 689b ldr r3, [r3, #8] 8012e2e: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8012e30: 68fb ldr r3, [r7, #12] 8012e32: f023 0370 bic.w r3, r3, #112 @ 0x70 8012e36: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8012e38: 683b ldr r3, [r7, #0] 8012e3a: 681b ldr r3, [r3, #0] 8012e3c: 68fa ldr r2, [r7, #12] 8012e3e: 4313 orrs r3, r2 8012e40: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8012e42: 687b ldr r3, [r7, #4] 8012e44: 681b ldr r3, [r3, #0] 8012e46: 68fa ldr r2, [r7, #12] 8012e48: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8012e4a: 687b ldr r3, [r7, #4] 8012e4c: 681b ldr r3, [r3, #0] 8012e4e: 4a19 ldr r2, [pc, #100] @ (8012eb4 ) 8012e50: 4293 cmp r3, r2 8012e52: d013 beq.n 8012e7c 8012e54: 687b ldr r3, [r7, #4] 8012e56: 681b ldr r3, [r3, #0] 8012e58: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8012e5c: d00e beq.n 8012e7c 8012e5e: 687b ldr r3, [r7, #4] 8012e60: 681b ldr r3, [r3, #0] 8012e62: 4a15 ldr r2, [pc, #84] @ (8012eb8 ) 8012e64: 4293 cmp r3, r2 8012e66: d009 beq.n 8012e7c 8012e68: 687b ldr r3, [r7, #4] 8012e6a: 681b ldr r3, [r3, #0] 8012e6c: 4a13 ldr r2, [pc, #76] @ (8012ebc ) 8012e6e: 4293 cmp r3, r2 8012e70: d004 beq.n 8012e7c 8012e72: 687b ldr r3, [r7, #4] 8012e74: 681b ldr r3, [r3, #0] 8012e76: 4a12 ldr r2, [pc, #72] @ (8012ec0 ) 8012e78: 4293 cmp r3, r2 8012e7a: d10c bne.n 8012e96 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8012e7c: 68bb ldr r3, [r7, #8] 8012e7e: f023 0380 bic.w r3, r3, #128 @ 0x80 8012e82: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8012e84: 683b ldr r3, [r7, #0] 8012e86: 685b ldr r3, [r3, #4] 8012e88: 68ba ldr r2, [r7, #8] 8012e8a: 4313 orrs r3, r2 8012e8c: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8012e8e: 687b ldr r3, [r7, #4] 8012e90: 681b ldr r3, [r3, #0] 8012e92: 68ba ldr r2, [r7, #8] 8012e94: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8012e96: 687b ldr r3, [r7, #4] 8012e98: 2201 movs r2, #1 8012e9a: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8012e9e: 687b ldr r3, [r7, #4] 8012ea0: 2200 movs r2, #0 8012ea2: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8012ea6: 2300 movs r3, #0 } 8012ea8: 4618 mov r0, r3 8012eaa: 3714 adds r7, #20 8012eac: 46bd mov sp, r7 8012eae: bc80 pop {r7} 8012eb0: 4770 bx lr 8012eb2: bf00 nop 8012eb4: 40012c00 .word 0x40012c00 8012eb8: 40000400 .word 0x40000400 8012ebc: 40000800 .word 0x40000800 8012ec0: 40000c00 .word 0x40000c00 08012ec4 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8012ec4: b480 push {r7} 8012ec6: b083 sub sp, #12 8012ec8: af00 add r7, sp, #0 8012eca: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8012ecc: bf00 nop 8012ece: 370c adds r7, #12 8012ed0: 46bd mov sp, r7 8012ed2: bc80 pop {r7} 8012ed4: 4770 bx lr 08012ed6 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8012ed6: b480 push {r7} 8012ed8: b083 sub sp, #12 8012eda: af00 add r7, sp, #0 8012edc: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8012ede: bf00 nop 8012ee0: 370c adds r7, #12 8012ee2: 46bd mov sp, r7 8012ee4: bc80 pop {r7} 8012ee6: 4770 bx lr 08012ee8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8012ee8: b580 push {r7, lr} 8012eea: b082 sub sp, #8 8012eec: af00 add r7, sp, #0 8012eee: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8012ef0: 687b ldr r3, [r7, #4] 8012ef2: 2b00 cmp r3, #0 8012ef4: d101 bne.n 8012efa { return HAL_ERROR; 8012ef6: 2301 movs r3, #1 8012ef8: e042 b.n 8012f80 assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 8012efa: 687b ldr r3, [r7, #4] 8012efc: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8012f00: b2db uxtb r3, r3 8012f02: 2b00 cmp r3, #0 8012f04: d106 bne.n 8012f14 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8012f06: 687b ldr r3, [r7, #4] 8012f08: 2200 movs r2, #0 8012f0a: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8012f0e: 6878 ldr r0, [r7, #4] 8012f10: f7fa ffc2 bl 800de98 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8012f14: 687b ldr r3, [r7, #4] 8012f16: 2224 movs r2, #36 @ 0x24 8012f18: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8012f1c: 687b ldr r3, [r7, #4] 8012f1e: 681b ldr r3, [r3, #0] 8012f20: 68da ldr r2, [r3, #12] 8012f22: 687b ldr r3, [r7, #4] 8012f24: 681b ldr r3, [r3, #0] 8012f26: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8012f2a: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8012f2c: 6878 ldr r0, [r7, #4] 8012f2e: f001 f903 bl 8014138 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8012f32: 687b ldr r3, [r7, #4] 8012f34: 681b ldr r3, [r3, #0] 8012f36: 691a ldr r2, [r3, #16] 8012f38: 687b ldr r3, [r7, #4] 8012f3a: 681b ldr r3, [r3, #0] 8012f3c: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8012f40: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8012f42: 687b ldr r3, [r7, #4] 8012f44: 681b ldr r3, [r3, #0] 8012f46: 695a ldr r2, [r3, #20] 8012f48: 687b ldr r3, [r7, #4] 8012f4a: 681b ldr r3, [r3, #0] 8012f4c: f022 022a bic.w r2, r2, #42 @ 0x2a 8012f50: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8012f52: 687b ldr r3, [r7, #4] 8012f54: 681b ldr r3, [r3, #0] 8012f56: 68da ldr r2, [r3, #12] 8012f58: 687b ldr r3, [r7, #4] 8012f5a: 681b ldr r3, [r3, #0] 8012f5c: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8012f60: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012f62: 687b ldr r3, [r7, #4] 8012f64: 2200 movs r2, #0 8012f66: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8012f68: 687b ldr r3, [r7, #4] 8012f6a: 2220 movs r2, #32 8012f6c: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8012f70: 687b ldr r3, [r7, #4] 8012f72: 2220 movs r2, #32 8012f74: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8012f78: 687b ldr r3, [r7, #4] 8012f7a: 2200 movs r2, #0 8012f7c: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 8012f7e: 2300 movs r3, #0 } 8012f80: 4618 mov r0, r3 8012f82: 3708 adds r7, #8 8012f84: 46bd mov sp, r7 8012f86: bd80 pop {r7, pc} 08012f88 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8012f88: b580 push {r7, lr} 8012f8a: b08c sub sp, #48 @ 0x30 8012f8c: af00 add r7, sp, #0 8012f8e: 60f8 str r0, [r7, #12] 8012f90: 60b9 str r1, [r7, #8] 8012f92: 4613 mov r3, r2 8012f94: 80fb strh r3, [r7, #6] const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8012f96: 68fb ldr r3, [r7, #12] 8012f98: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8012f9c: b2db uxtb r3, r3 8012f9e: 2b20 cmp r3, #32 8012fa0: d156 bne.n 8013050 { if ((pData == NULL) || (Size == 0U)) 8012fa2: 68bb ldr r3, [r7, #8] 8012fa4: 2b00 cmp r3, #0 8012fa6: d002 beq.n 8012fae 8012fa8: 88fb ldrh r3, [r7, #6] 8012faa: 2b00 cmp r3, #0 8012fac: d101 bne.n 8012fb2 { return HAL_ERROR; 8012fae: 2301 movs r3, #1 8012fb0: e04f b.n 8013052 } huart->pTxBuffPtr = pData; 8012fb2: 68ba ldr r2, [r7, #8] 8012fb4: 68fb ldr r3, [r7, #12] 8012fb6: 621a str r2, [r3, #32] huart->TxXferSize = Size; 8012fb8: 68fb ldr r3, [r7, #12] 8012fba: 88fa ldrh r2, [r7, #6] 8012fbc: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8012fbe: 68fb ldr r3, [r7, #12] 8012fc0: 88fa ldrh r2, [r7, #6] 8012fc2: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 8012fc4: 68fb ldr r3, [r7, #12] 8012fc6: 2200 movs r2, #0 8012fc8: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8012fca: 68fb ldr r3, [r7, #12] 8012fcc: 2221 movs r2, #33 @ 0x21 8012fce: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 8012fd2: 68fb ldr r3, [r7, #12] 8012fd4: 6b9b ldr r3, [r3, #56] @ 0x38 8012fd6: 4a21 ldr r2, [pc, #132] @ (801305c ) 8012fd8: 629a str r2, [r3, #40] @ 0x28 /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 8012fda: 68fb ldr r3, [r7, #12] 8012fdc: 6b9b ldr r3, [r3, #56] @ 0x38 8012fde: 4a20 ldr r2, [pc, #128] @ (8013060 ) 8012fe0: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 8012fe2: 68fb ldr r3, [r7, #12] 8012fe4: 6b9b ldr r3, [r3, #56] @ 0x38 8012fe6: 4a1f ldr r2, [pc, #124] @ (8013064 ) 8012fe8: 631a str r2, [r3, #48] @ 0x30 /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 8012fea: 68fb ldr r3, [r7, #12] 8012fec: 6b9b ldr r3, [r3, #56] @ 0x38 8012fee: 2200 movs r2, #0 8012ff0: 635a str r2, [r3, #52] @ 0x34 /* Enable the UART transmit DMA channel */ tmp = (const uint32_t *)&pData; 8012ff2: f107 0308 add.w r3, r7, #8 8012ff6: 62fb str r3, [r7, #44] @ 0x2c HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size); 8012ff8: 68fb ldr r3, [r7, #12] 8012ffa: 6b98 ldr r0, [r3, #56] @ 0x38 8012ffc: 6afb ldr r3, [r7, #44] @ 0x2c 8012ffe: 6819 ldr r1, [r3, #0] 8013000: 68fb ldr r3, [r7, #12] 8013002: 681b ldr r3, [r3, #0] 8013004: 3304 adds r3, #4 8013006: 461a mov r2, r3 8013008: 88fb ldrh r3, [r7, #6] 801300a: f7fc ffa5 bl 800ff58 /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); 801300e: 68fb ldr r3, [r7, #12] 8013010: 681b ldr r3, [r3, #0] 8013012: f06f 0240 mvn.w r2, #64 @ 0x40 8013016: 601a str r2, [r3, #0] /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8013018: 68fb ldr r3, [r7, #12] 801301a: 681b ldr r3, [r3, #0] 801301c: 3314 adds r3, #20 801301e: 61bb str r3, [r7, #24] */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013020: 69bb ldr r3, [r7, #24] 8013022: e853 3f00 ldrex r3, [r3] 8013026: 617b str r3, [r7, #20] return(result); 8013028: 697b ldr r3, [r7, #20] 801302a: f043 0380 orr.w r3, r3, #128 @ 0x80 801302e: 62bb str r3, [r7, #40] @ 0x28 8013030: 68fb ldr r3, [r7, #12] 8013032: 681b ldr r3, [r3, #0] 8013034: 3314 adds r3, #20 8013036: 6aba ldr r2, [r7, #40] @ 0x28 8013038: 627a str r2, [r7, #36] @ 0x24 801303a: 623b str r3, [r7, #32] */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801303c: 6a39 ldr r1, [r7, #32] 801303e: 6a7a ldr r2, [r7, #36] @ 0x24 8013040: e841 2300 strex r3, r2, [r1] 8013044: 61fb str r3, [r7, #28] return(result); 8013046: 69fb ldr r3, [r7, #28] 8013048: 2b00 cmp r3, #0 801304a: d1e5 bne.n 8013018 return HAL_OK; 801304c: 2300 movs r3, #0 801304e: e000 b.n 8013052 } else { return HAL_BUSY; 8013050: 2302 movs r3, #2 } } 8013052: 4618 mov r0, r3 8013054: 3730 adds r7, #48 @ 0x30 8013056: 46bd mov sp, r7 8013058: bd80 pop {r7, pc} 801305a: bf00 nop 801305c: 0801395d .word 0x0801395d 8013060: 080139f7 .word 0x080139f7 8013064: 08013b7b .word 0x08013b7b 08013068 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8013068: b580 push {r7, lr} 801306a: b08c sub sp, #48 @ 0x30 801306c: af00 add r7, sp, #0 801306e: 60f8 str r0, [r7, #12] 8013070: 60b9 str r1, [r7, #8] 8013072: 4613 mov r3, r2 8013074: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8013076: 68fb ldr r3, [r7, #12] 8013078: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 801307c: b2db uxtb r3, r3 801307e: 2b20 cmp r3, #32 8013080: d14a bne.n 8013118 { if ((pData == NULL) || (Size == 0U)) 8013082: 68bb ldr r3, [r7, #8] 8013084: 2b00 cmp r3, #0 8013086: d002 beq.n 801308e 8013088: 88fb ldrh r3, [r7, #6] 801308a: 2b00 cmp r3, #0 801308c: d101 bne.n 8013092 { return HAL_ERROR; 801308e: 2301 movs r3, #1 8013090: e043 b.n 801311a } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8013092: 68fb ldr r3, [r7, #12] 8013094: 2201 movs r2, #1 8013096: 631a str r2, [r3, #48] @ 0x30 huart->RxEventType = HAL_UART_RXEVENT_TC; 8013098: 68fb ldr r3, [r7, #12] 801309a: 2200 movs r2, #0 801309c: 635a str r2, [r3, #52] @ 0x34 status = UART_Start_Receive_IT(huart, pData, Size); 801309e: 88fb ldrh r3, [r7, #6] 80130a0: 461a mov r2, r3 80130a2: 68b9 ldr r1, [r7, #8] 80130a4: 68f8 ldr r0, [r7, #12] 80130a6: f000 fdb2 bl 8013c0e 80130aa: 4603 mov r3, r0 80130ac: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check Rx process has been successfully started */ if (status == HAL_OK) 80130b0: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 80130b4: 2b00 cmp r3, #0 80130b6: d12c bne.n 8013112 { if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80130b8: 68fb ldr r3, [r7, #12] 80130ba: 6b1b ldr r3, [r3, #48] @ 0x30 80130bc: 2b01 cmp r3, #1 80130be: d125 bne.n 801310c { __HAL_UART_CLEAR_IDLEFLAG(huart); 80130c0: 2300 movs r3, #0 80130c2: 613b str r3, [r7, #16] 80130c4: 68fb ldr r3, [r7, #12] 80130c6: 681b ldr r3, [r3, #0] 80130c8: 681b ldr r3, [r3, #0] 80130ca: 613b str r3, [r7, #16] 80130cc: 68fb ldr r3, [r7, #12] 80130ce: 681b ldr r3, [r3, #0] 80130d0: 685b ldr r3, [r3, #4] 80130d2: 613b str r3, [r7, #16] 80130d4: 693b ldr r3, [r7, #16] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80130d6: 68fb ldr r3, [r7, #12] 80130d8: 681b ldr r3, [r3, #0] 80130da: 330c adds r3, #12 80130dc: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80130de: 69bb ldr r3, [r7, #24] 80130e0: e853 3f00 ldrex r3, [r3] 80130e4: 617b str r3, [r7, #20] return(result); 80130e6: 697b ldr r3, [r7, #20] 80130e8: f043 0310 orr.w r3, r3, #16 80130ec: 62bb str r3, [r7, #40] @ 0x28 80130ee: 68fb ldr r3, [r7, #12] 80130f0: 681b ldr r3, [r3, #0] 80130f2: 330c adds r3, #12 80130f4: 6aba ldr r2, [r7, #40] @ 0x28 80130f6: 627a str r2, [r7, #36] @ 0x24 80130f8: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80130fa: 6a39 ldr r1, [r7, #32] 80130fc: 6a7a ldr r2, [r7, #36] @ 0x24 80130fe: e841 2300 strex r3, r2, [r1] 8013102: 61fb str r3, [r7, #28] return(result); 8013104: 69fb ldr r3, [r7, #28] 8013106: 2b00 cmp r3, #0 8013108: d1e5 bne.n 80130d6 801310a: e002 b.n 8013112 { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 801310c: 2301 movs r3, #1 801310e: f887 302f strb.w r3, [r7, #47] @ 0x2f } } return status; 8013112: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8013116: e000 b.n 801311a } else { return HAL_BUSY; 8013118: 2302 movs r3, #2 } } 801311a: 4618 mov r0, r3 801311c: 3730 adds r7, #48 @ 0x30 801311e: 46bd mov sp, r7 8013120: bd80 pop {r7, pc} 08013122 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8013122: b580 push {r7, lr} 8013124: b08c sub sp, #48 @ 0x30 8013126: af00 add r7, sp, #0 8013128: 60f8 str r0, [r7, #12] 801312a: 60b9 str r1, [r7, #8] 801312c: 4613 mov r3, r2 801312e: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8013130: 68fb ldr r3, [r7, #12] 8013132: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8013136: b2db uxtb r3, r3 8013138: 2b20 cmp r3, #32 801313a: d146 bne.n 80131ca { if ((pData == NULL) || (Size == 0U)) 801313c: 68bb ldr r3, [r7, #8] 801313e: 2b00 cmp r3, #0 8013140: d002 beq.n 8013148 8013142: 88fb ldrh r3, [r7, #6] 8013144: 2b00 cmp r3, #0 8013146: d101 bne.n 801314c { return HAL_ERROR; 8013148: 2301 movs r3, #1 801314a: e03f b.n 80131cc } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 801314c: 68fb ldr r3, [r7, #12] 801314e: 2201 movs r2, #1 8013150: 631a str r2, [r3, #48] @ 0x30 huart->RxEventType = HAL_UART_RXEVENT_TC; 8013152: 68fb ldr r3, [r7, #12] 8013154: 2200 movs r2, #0 8013156: 635a str r2, [r3, #52] @ 0x34 status = UART_Start_Receive_DMA(huart, pData, Size); 8013158: 88fb ldrh r3, [r7, #6] 801315a: 461a mov r2, r3 801315c: 68b9 ldr r1, [r7, #8] 801315e: 68f8 ldr r0, [r7, #12] 8013160: f000 fd8e bl 8013c80 8013164: 4603 mov r3, r0 8013166: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check Rx process has been successfully started */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 801316a: 68fb ldr r3, [r7, #12] 801316c: 6b1b ldr r3, [r3, #48] @ 0x30 801316e: 2b01 cmp r3, #1 8013170: d125 bne.n 80131be { __HAL_UART_CLEAR_IDLEFLAG(huart); 8013172: 2300 movs r3, #0 8013174: 613b str r3, [r7, #16] 8013176: 68fb ldr r3, [r7, #12] 8013178: 681b ldr r3, [r3, #0] 801317a: 681b ldr r3, [r3, #0] 801317c: 613b str r3, [r7, #16] 801317e: 68fb ldr r3, [r7, #12] 8013180: 681b ldr r3, [r3, #0] 8013182: 685b ldr r3, [r3, #4] 8013184: 613b str r3, [r7, #16] 8013186: 693b ldr r3, [r7, #16] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013188: 68fb ldr r3, [r7, #12] 801318a: 681b ldr r3, [r3, #0] 801318c: 330c adds r3, #12 801318e: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013190: 69bb ldr r3, [r7, #24] 8013192: e853 3f00 ldrex r3, [r3] 8013196: 617b str r3, [r7, #20] return(result); 8013198: 697b ldr r3, [r7, #20] 801319a: f043 0310 orr.w r3, r3, #16 801319e: 62bb str r3, [r7, #40] @ 0x28 80131a0: 68fb ldr r3, [r7, #12] 80131a2: 681b ldr r3, [r3, #0] 80131a4: 330c adds r3, #12 80131a6: 6aba ldr r2, [r7, #40] @ 0x28 80131a8: 627a str r2, [r7, #36] @ 0x24 80131aa: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80131ac: 6a39 ldr r1, [r7, #32] 80131ae: 6a7a ldr r2, [r7, #36] @ 0x24 80131b0: e841 2300 strex r3, r2, [r1] 80131b4: 61fb str r3, [r7, #28] return(result); 80131b6: 69fb ldr r3, [r7, #28] 80131b8: 2b00 cmp r3, #0 80131ba: d1e5 bne.n 8013188 80131bc: e002 b.n 80131c4 { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 80131be: 2301 movs r3, #1 80131c0: f887 302f strb.w r3, [r7, #47] @ 0x2f } return status; 80131c4: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 80131c8: e000 b.n 80131cc } else { return HAL_BUSY; 80131ca: 2302 movs r3, #2 } } 80131cc: 4618 mov r0, r3 80131ce: 3730 adds r7, #48 @ 0x30 80131d0: 46bd mov sp, r7 80131d2: bd80 pop {r7, pc} 080131d4 : * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { 80131d4: b580 push {r7, lr} 80131d6: b08e sub sp, #56 @ 0x38 80131d8: af00 add r7, sp, #0 80131da: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 80131dc: 687b ldr r3, [r7, #4] 80131de: 681b ldr r3, [r3, #0] 80131e0: 330c adds r3, #12 80131e2: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80131e4: 6a3b ldr r3, [r7, #32] 80131e6: e853 3f00 ldrex r3, [r3] 80131ea: 61fb str r3, [r7, #28] return(result); 80131ec: 69fb ldr r3, [r7, #28] 80131ee: f023 03c0 bic.w r3, r3, #192 @ 0xc0 80131f2: 637b str r3, [r7, #52] @ 0x34 80131f4: 687b ldr r3, [r7, #4] 80131f6: 681b ldr r3, [r3, #0] 80131f8: 330c adds r3, #12 80131fa: 6b7a ldr r2, [r7, #52] @ 0x34 80131fc: 62fa str r2, [r7, #44] @ 0x2c 80131fe: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013200: 6ab9 ldr r1, [r7, #40] @ 0x28 8013202: 6afa ldr r2, [r7, #44] @ 0x2c 8013204: e841 2300 strex r3, r2, [r1] 8013208: 627b str r3, [r7, #36] @ 0x24 return(result); 801320a: 6a7b ldr r3, [r7, #36] @ 0x24 801320c: 2b00 cmp r3, #0 801320e: d1e5 bne.n 80131dc /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) 8013210: 687b ldr r3, [r7, #4] 8013212: 681b ldr r3, [r3, #0] 8013214: 695b ldr r3, [r3, #20] 8013216: f003 0380 and.w r3, r3, #128 @ 0x80 801321a: 2b00 cmp r3, #0 801321c: d036 beq.n 801328c { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 801321e: 687b ldr r3, [r7, #4] 8013220: 681b ldr r3, [r3, #0] 8013222: 3314 adds r3, #20 8013224: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013226: 68fb ldr r3, [r7, #12] 8013228: e853 3f00 ldrex r3, [r3] 801322c: 60bb str r3, [r7, #8] return(result); 801322e: 68bb ldr r3, [r7, #8] 8013230: f023 0380 bic.w r3, r3, #128 @ 0x80 8013234: 633b str r3, [r7, #48] @ 0x30 8013236: 687b ldr r3, [r7, #4] 8013238: 681b ldr r3, [r3, #0] 801323a: 3314 adds r3, #20 801323c: 6b3a ldr r2, [r7, #48] @ 0x30 801323e: 61ba str r2, [r7, #24] 8013240: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013242: 6979 ldr r1, [r7, #20] 8013244: 69ba ldr r2, [r7, #24] 8013246: e841 2300 strex r3, r2, [r1] 801324a: 613b str r3, [r7, #16] return(result); 801324c: 693b ldr r3, [r7, #16] 801324e: 2b00 cmp r3, #0 8013250: d1e5 bne.n 801321e /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) 8013252: 687b ldr r3, [r7, #4] 8013254: 6b9b ldr r3, [r3, #56] @ 0x38 8013256: 2b00 cmp r3, #0 8013258: d018 beq.n 801328c { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = NULL; 801325a: 687b ldr r3, [r7, #4] 801325c: 6b9b ldr r3, [r3, #56] @ 0x38 801325e: 2200 movs r2, #0 8013260: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) 8013262: 687b ldr r3, [r7, #4] 8013264: 6b9b ldr r3, [r3, #56] @ 0x38 8013266: 4618 mov r0, r3 8013268: f7fc fed6 bl 8010018 801326c: 4603 mov r3, r0 801326e: 2b00 cmp r3, #0 8013270: d00c beq.n 801328c { if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) 8013272: 687b ldr r3, [r7, #4] 8013274: 6b9b ldr r3, [r3, #56] @ 0x38 8013276: 4618 mov r0, r3 8013278: f7fd fa4e bl 8010718 801327c: 4603 mov r3, r0 801327e: 2b20 cmp r3, #32 8013280: d104 bne.n 801328c { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 8013282: 687b ldr r3, [r7, #4] 8013284: 2210 movs r2, #16 8013286: 645a str r2, [r3, #68] @ 0x44 return HAL_TIMEOUT; 8013288: 2303 movs r3, #3 801328a: e007 b.n 801329c } } } /* Reset Tx transfer counter */ huart->TxXferCount = 0x00U; 801328c: 687b ldr r3, [r7, #4] 801328e: 2200 movs r2, #0 8013290: 84da strh r2, [r3, #38] @ 0x26 /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8013292: 687b ldr r3, [r7, #4] 8013294: 2220 movs r2, #32 8013296: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_OK; 801329a: 2300 movs r3, #0 } 801329c: 4618 mov r0, r3 801329e: 3738 adds r7, #56 @ 0x38 80132a0: 46bd mov sp, r7 80132a2: bd80 pop {r7, pc} 080132a4 : * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { 80132a4: b580 push {r7, lr} 80132a6: b09a sub sp, #104 @ 0x68 80132a8: af00 add r7, sp, #0 80132aa: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 80132ac: 687b ldr r3, [r7, #4] 80132ae: 681b ldr r3, [r3, #0] 80132b0: 330c adds r3, #12 80132b2: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80132b4: 6cbb ldr r3, [r7, #72] @ 0x48 80132b6: e853 3f00 ldrex r3, [r3] 80132ba: 647b str r3, [r7, #68] @ 0x44 return(result); 80132bc: 6c7b ldr r3, [r7, #68] @ 0x44 80132be: f423 7390 bic.w r3, r3, #288 @ 0x120 80132c2: 667b str r3, [r7, #100] @ 0x64 80132c4: 687b ldr r3, [r7, #4] 80132c6: 681b ldr r3, [r3, #0] 80132c8: 330c adds r3, #12 80132ca: 6e7a ldr r2, [r7, #100] @ 0x64 80132cc: 657a str r2, [r7, #84] @ 0x54 80132ce: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80132d0: 6d39 ldr r1, [r7, #80] @ 0x50 80132d2: 6d7a ldr r2, [r7, #84] @ 0x54 80132d4: e841 2300 strex r3, r2, [r1] 80132d8: 64fb str r3, [r7, #76] @ 0x4c return(result); 80132da: 6cfb ldr r3, [r7, #76] @ 0x4c 80132dc: 2b00 cmp r3, #0 80132de: d1e5 bne.n 80132ac ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80132e0: 687b ldr r3, [r7, #4] 80132e2: 681b ldr r3, [r3, #0] 80132e4: 3314 adds r3, #20 80132e6: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80132e8: 6b7b ldr r3, [r7, #52] @ 0x34 80132ea: e853 3f00 ldrex r3, [r3] 80132ee: 633b str r3, [r7, #48] @ 0x30 return(result); 80132f0: 6b3b ldr r3, [r7, #48] @ 0x30 80132f2: f023 0301 bic.w r3, r3, #1 80132f6: 663b str r3, [r7, #96] @ 0x60 80132f8: 687b ldr r3, [r7, #4] 80132fa: 681b ldr r3, [r3, #0] 80132fc: 3314 adds r3, #20 80132fe: 6e3a ldr r2, [r7, #96] @ 0x60 8013300: 643a str r2, [r7, #64] @ 0x40 8013302: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013304: 6bf9 ldr r1, [r7, #60] @ 0x3c 8013306: 6c3a ldr r2, [r7, #64] @ 0x40 8013308: e841 2300 strex r3, r2, [r1] 801330c: 63bb str r3, [r7, #56] @ 0x38 return(result); 801330e: 6bbb ldr r3, [r7, #56] @ 0x38 8013310: 2b00 cmp r3, #0 8013312: d1e5 bne.n 80132e0 /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013314: 687b ldr r3, [r7, #4] 8013316: 6b1b ldr r3, [r3, #48] @ 0x30 8013318: 2b01 cmp r3, #1 801331a: d119 bne.n 8013350 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); 801331c: 687b ldr r3, [r7, #4] 801331e: 681b ldr r3, [r3, #0] 8013320: 330c adds r3, #12 8013322: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013324: 6a3b ldr r3, [r7, #32] 8013326: e853 3f00 ldrex r3, [r3] 801332a: 61fb str r3, [r7, #28] return(result); 801332c: 69fb ldr r3, [r7, #28] 801332e: f023 0310 bic.w r3, r3, #16 8013332: 65fb str r3, [r7, #92] @ 0x5c 8013334: 687b ldr r3, [r7, #4] 8013336: 681b ldr r3, [r3, #0] 8013338: 330c adds r3, #12 801333a: 6dfa ldr r2, [r7, #92] @ 0x5c 801333c: 62fa str r2, [r7, #44] @ 0x2c 801333e: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013340: 6ab9 ldr r1, [r7, #40] @ 0x28 8013342: 6afa ldr r2, [r7, #44] @ 0x2c 8013344: e841 2300 strex r3, r2, [r1] 8013348: 627b str r3, [r7, #36] @ 0x24 return(result); 801334a: 6a7b ldr r3, [r7, #36] @ 0x24 801334c: 2b00 cmp r3, #0 801334e: d1e5 bne.n 801331c } /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013350: 687b ldr r3, [r7, #4] 8013352: 681b ldr r3, [r3, #0] 8013354: 695b ldr r3, [r3, #20] 8013356: f003 0340 and.w r3, r3, #64 @ 0x40 801335a: 2b00 cmp r3, #0 801335c: d036 beq.n 80133cc { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 801335e: 687b ldr r3, [r7, #4] 8013360: 681b ldr r3, [r3, #0] 8013362: 3314 adds r3, #20 8013364: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013366: 68fb ldr r3, [r7, #12] 8013368: e853 3f00 ldrex r3, [r3] 801336c: 60bb str r3, [r7, #8] return(result); 801336e: 68bb ldr r3, [r7, #8] 8013370: f023 0340 bic.w r3, r3, #64 @ 0x40 8013374: 65bb str r3, [r7, #88] @ 0x58 8013376: 687b ldr r3, [r7, #4] 8013378: 681b ldr r3, [r3, #0] 801337a: 3314 adds r3, #20 801337c: 6dba ldr r2, [r7, #88] @ 0x58 801337e: 61ba str r2, [r7, #24] 8013380: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013382: 6979 ldr r1, [r7, #20] 8013384: 69ba ldr r2, [r7, #24] 8013386: e841 2300 strex r3, r2, [r1] 801338a: 613b str r3, [r7, #16] return(result); 801338c: 693b ldr r3, [r7, #16] 801338e: 2b00 cmp r3, #0 8013390: d1e5 bne.n 801335e /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) 8013392: 687b ldr r3, [r7, #4] 8013394: 6bdb ldr r3, [r3, #60] @ 0x3c 8013396: 2b00 cmp r3, #0 8013398: d018 beq.n 80133cc { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = NULL; 801339a: 687b ldr r3, [r7, #4] 801339c: 6bdb ldr r3, [r3, #60] @ 0x3c 801339e: 2200 movs r2, #0 80133a0: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) 80133a2: 687b ldr r3, [r7, #4] 80133a4: 6bdb ldr r3, [r3, #60] @ 0x3c 80133a6: 4618 mov r0, r3 80133a8: f7fc fe36 bl 8010018 80133ac: 4603 mov r3, r0 80133ae: 2b00 cmp r3, #0 80133b0: d00c beq.n 80133cc { if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) 80133b2: 687b ldr r3, [r7, #4] 80133b4: 6bdb ldr r3, [r3, #60] @ 0x3c 80133b6: 4618 mov r0, r3 80133b8: f7fd f9ae bl 8010718 80133bc: 4603 mov r3, r0 80133be: 2b20 cmp r3, #32 80133c0: d104 bne.n 80133cc { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 80133c2: 687b ldr r3, [r7, #4] 80133c4: 2210 movs r2, #16 80133c6: 645a str r2, [r3, #68] @ 0x44 return HAL_TIMEOUT; 80133c8: 2303 movs r3, #3 80133ca: e00a b.n 80133e2 } } } /* Reset Rx transfer counter */ huart->RxXferCount = 0x00U; 80133cc: 687b ldr r3, [r7, #4] 80133ce: 2200 movs r2, #0 80133d0: 85da strh r2, [r3, #46] @ 0x2e /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80133d2: 687b ldr r3, [r7, #4] 80133d4: 2220 movs r2, #32 80133d6: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80133da: 687b ldr r3, [r7, #4] 80133dc: 2200 movs r2, #0 80133de: 631a str r2, [r3, #48] @ 0x30 return HAL_OK; 80133e0: 2300 movs r3, #0 } 80133e2: 4618 mov r0, r3 80133e4: 3768 adds r7, #104 @ 0x68 80133e6: 46bd mov sp, r7 80133e8: bd80 pop {r7, pc} ... 080133ec : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 80133ec: b580 push {r7, lr} 80133ee: b0ba sub sp, #232 @ 0xe8 80133f0: af00 add r7, sp, #0 80133f2: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 80133f4: 687b ldr r3, [r7, #4] 80133f6: 681b ldr r3, [r3, #0] 80133f8: 681b ldr r3, [r3, #0] 80133fa: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 80133fe: 687b ldr r3, [r7, #4] 8013400: 681b ldr r3, [r3, #0] 8013402: 68db ldr r3, [r3, #12] 8013404: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8013408: 687b ldr r3, [r7, #4] 801340a: 681b ldr r3, [r3, #0] 801340c: 695b ldr r3, [r3, #20] 801340e: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 8013412: 2300 movs r3, #0 8013414: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 8013418: 2300 movs r3, #0 801341a: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 801341e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013422: f003 030f and.w r3, r3, #15 8013426: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 801342a: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 801342e: 2b00 cmp r3, #0 8013430: d10f bne.n 8013452 { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8013432: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013436: f003 0320 and.w r3, r3, #32 801343a: 2b00 cmp r3, #0 801343c: d009 beq.n 8013452 801343e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013442: f003 0320 and.w r3, r3, #32 8013446: 2b00 cmp r3, #0 8013448: d003 beq.n 8013452 { UART_Receive_IT(huart); 801344a: 6878 ldr r0, [r7, #4] 801344c: f000 fdb6 bl 8013fbc return; 8013450: e25b b.n 801390a } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 8013452: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8013456: 2b00 cmp r3, #0 8013458: f000 80de beq.w 8013618 801345c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8013460: f003 0301 and.w r3, r3, #1 8013464: 2b00 cmp r3, #0 8013466: d106 bne.n 8013476 || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 8013468: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801346c: f403 7390 and.w r3, r3, #288 @ 0x120 8013470: 2b00 cmp r3, #0 8013472: f000 80d1 beq.w 8013618 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 8013476: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801347a: f003 0301 and.w r3, r3, #1 801347e: 2b00 cmp r3, #0 8013480: d00b beq.n 801349a 8013482: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013486: f403 7380 and.w r3, r3, #256 @ 0x100 801348a: 2b00 cmp r3, #0 801348c: d005 beq.n 801349a { huart->ErrorCode |= HAL_UART_ERROR_PE; 801348e: 687b ldr r3, [r7, #4] 8013490: 6c5b ldr r3, [r3, #68] @ 0x44 8013492: f043 0201 orr.w r2, r3, #1 8013496: 687b ldr r3, [r7, #4] 8013498: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 801349a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801349e: f003 0304 and.w r3, r3, #4 80134a2: 2b00 cmp r3, #0 80134a4: d00b beq.n 80134be 80134a6: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80134aa: f003 0301 and.w r3, r3, #1 80134ae: 2b00 cmp r3, #0 80134b0: d005 beq.n 80134be { huart->ErrorCode |= HAL_UART_ERROR_NE; 80134b2: 687b ldr r3, [r7, #4] 80134b4: 6c5b ldr r3, [r3, #68] @ 0x44 80134b6: f043 0202 orr.w r2, r3, #2 80134ba: 687b ldr r3, [r7, #4] 80134bc: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 80134be: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80134c2: f003 0302 and.w r3, r3, #2 80134c6: 2b00 cmp r3, #0 80134c8: d00b beq.n 80134e2 80134ca: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80134ce: f003 0301 and.w r3, r3, #1 80134d2: 2b00 cmp r3, #0 80134d4: d005 beq.n 80134e2 { huart->ErrorCode |= HAL_UART_ERROR_FE; 80134d6: 687b ldr r3, [r7, #4] 80134d8: 6c5b ldr r3, [r3, #68] @ 0x44 80134da: f043 0204 orr.w r2, r3, #4 80134de: 687b ldr r3, [r7, #4] 80134e0: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 80134e2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80134e6: f003 0308 and.w r3, r3, #8 80134ea: 2b00 cmp r3, #0 80134ec: d011 beq.n 8013512 80134ee: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80134f2: f003 0320 and.w r3, r3, #32 80134f6: 2b00 cmp r3, #0 80134f8: d105 bne.n 8013506 || ((cr3its & USART_CR3_EIE) != RESET))) 80134fa: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80134fe: f003 0301 and.w r3, r3, #1 8013502: 2b00 cmp r3, #0 8013504: d005 beq.n 8013512 { huart->ErrorCode |= HAL_UART_ERROR_ORE; 8013506: 687b ldr r3, [r7, #4] 8013508: 6c5b ldr r3, [r3, #68] @ 0x44 801350a: f043 0208 orr.w r2, r3, #8 801350e: 687b ldr r3, [r7, #4] 8013510: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8013512: 687b ldr r3, [r7, #4] 8013514: 6c5b ldr r3, [r3, #68] @ 0x44 8013516: 2b00 cmp r3, #0 8013518: f000 81f2 beq.w 8013900 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 801351c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013520: f003 0320 and.w r3, r3, #32 8013524: 2b00 cmp r3, #0 8013526: d008 beq.n 801353a 8013528: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801352c: f003 0320 and.w r3, r3, #32 8013530: 2b00 cmp r3, #0 8013532: d002 beq.n 801353a { UART_Receive_IT(huart); 8013534: 6878 ldr r0, [r7, #4] 8013536: f000 fd41 bl 8013fbc } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 801353a: 687b ldr r3, [r7, #4] 801353c: 681b ldr r3, [r3, #0] 801353e: 695b ldr r3, [r3, #20] 8013540: f003 0340 and.w r3, r3, #64 @ 0x40 8013544: 2b00 cmp r3, #0 8013546: bf14 ite ne 8013548: 2301 movne r3, #1 801354a: 2300 moveq r3, #0 801354c: b2db uxtb r3, r3 801354e: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 8013552: 687b ldr r3, [r7, #4] 8013554: 6c5b ldr r3, [r3, #68] @ 0x44 8013556: f003 0308 and.w r3, r3, #8 801355a: 2b00 cmp r3, #0 801355c: d103 bne.n 8013566 801355e: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8013562: 2b00 cmp r3, #0 8013564: d04f beq.n 8013606 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8013566: 6878 ldr r0, [r7, #4] 8013568: f000 fc4b bl 8013e02 /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801356c: 687b ldr r3, [r7, #4] 801356e: 681b ldr r3, [r3, #0] 8013570: 695b ldr r3, [r3, #20] 8013572: f003 0340 and.w r3, r3, #64 @ 0x40 8013576: 2b00 cmp r3, #0 8013578: d041 beq.n 80135fe { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 801357a: 687b ldr r3, [r7, #4] 801357c: 681b ldr r3, [r3, #0] 801357e: 3314 adds r3, #20 8013580: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013584: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8013588: e853 3f00 ldrex r3, [r3] 801358c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8013590: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8013594: f023 0340 bic.w r3, r3, #64 @ 0x40 8013598: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 801359c: 687b ldr r3, [r7, #4] 801359e: 681b ldr r3, [r3, #0] 80135a0: 3314 adds r3, #20 80135a2: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 80135a6: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 80135aa: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80135ae: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 80135b2: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 80135b6: e841 2300 strex r3, r2, [r1] 80135ba: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 80135be: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 80135c2: 2b00 cmp r3, #0 80135c4: d1d9 bne.n 801357a /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 80135c6: 687b ldr r3, [r7, #4] 80135c8: 6bdb ldr r3, [r3, #60] @ 0x3c 80135ca: 2b00 cmp r3, #0 80135cc: d013 beq.n 80135f6 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 80135ce: 687b ldr r3, [r7, #4] 80135d0: 6bdb ldr r3, [r3, #60] @ 0x3c 80135d2: 4a7e ldr r2, [pc, #504] @ (80137cc ) 80135d4: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 80135d6: 687b ldr r3, [r7, #4] 80135d8: 6bdb ldr r3, [r3, #60] @ 0x3c 80135da: 4618 mov r0, r3 80135dc: f7fc fd58 bl 8010090 80135e0: 4603 mov r3, r0 80135e2: 2b00 cmp r3, #0 80135e4: d016 beq.n 8013614 { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 80135e6: 687b ldr r3, [r7, #4] 80135e8: 6bdb ldr r3, [r3, #60] @ 0x3c 80135ea: 6b5b ldr r3, [r3, #52] @ 0x34 80135ec: 687a ldr r2, [r7, #4] 80135ee: 6bd2 ldr r2, [r2, #60] @ 0x3c 80135f0: 4610 mov r0, r2 80135f2: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80135f4: e00e b.n 8013614 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80135f6: 6878 ldr r0, [r7, #4] 80135f8: f7f8 fb8e bl 800bd18 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80135fc: e00a b.n 8013614 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80135fe: 6878 ldr r0, [r7, #4] 8013600: f7f8 fb8a bl 800bd18 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013604: e006 b.n 8013614 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013606: 6878 ldr r0, [r7, #4] 8013608: f7f8 fb86 bl 800bd18 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 801360c: 687b ldr r3, [r7, #4] 801360e: 2200 movs r2, #0 8013610: 645a str r2, [r3, #68] @ 0x44 } } return; 8013612: e175 b.n 8013900 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013614: bf00 nop return; 8013616: e173 b.n 8013900 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013618: 687b ldr r3, [r7, #4] 801361a: 6b1b ldr r3, [r3, #48] @ 0x30 801361c: 2b01 cmp r3, #1 801361e: f040 814f bne.w 80138c0 && ((isrflags & USART_SR_IDLE) != 0U) 8013622: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8013626: f003 0310 and.w r3, r3, #16 801362a: 2b00 cmp r3, #0 801362c: f000 8148 beq.w 80138c0 && ((cr1its & USART_SR_IDLE) != 0U)) 8013630: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8013634: f003 0310 and.w r3, r3, #16 8013638: 2b00 cmp r3, #0 801363a: f000 8141 beq.w 80138c0 { __HAL_UART_CLEAR_IDLEFLAG(huart); 801363e: 2300 movs r3, #0 8013640: 60bb str r3, [r7, #8] 8013642: 687b ldr r3, [r7, #4] 8013644: 681b ldr r3, [r3, #0] 8013646: 681b ldr r3, [r3, #0] 8013648: 60bb str r3, [r7, #8] 801364a: 687b ldr r3, [r7, #4] 801364c: 681b ldr r3, [r3, #0] 801364e: 685b ldr r3, [r3, #4] 8013650: 60bb str r3, [r7, #8] 8013652: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8013654: 687b ldr r3, [r7, #4] 8013656: 681b ldr r3, [r3, #0] 8013658: 695b ldr r3, [r3, #20] 801365a: f003 0340 and.w r3, r3, #64 @ 0x40 801365e: 2b00 cmp r3, #0 8013660: f000 80b6 beq.w 80137d0 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8013664: 687b ldr r3, [r7, #4] 8013666: 6bdb ldr r3, [r3, #60] @ 0x3c 8013668: 681b ldr r3, [r3, #0] 801366a: 685b ldr r3, [r3, #4] 801366c: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8013670: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8013674: 2b00 cmp r3, #0 8013676: f000 8145 beq.w 8013904 && (nb_remaining_rx_data < huart->RxXferSize)) 801367a: 687b ldr r3, [r7, #4] 801367c: 8d9b ldrh r3, [r3, #44] @ 0x2c 801367e: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8013682: 429a cmp r2, r3 8013684: f080 813e bcs.w 8013904 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8013688: 687b ldr r3, [r7, #4] 801368a: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 801368e: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8013690: 687b ldr r3, [r7, #4] 8013692: 6bdb ldr r3, [r3, #60] @ 0x3c 8013694: 699b ldr r3, [r3, #24] 8013696: 2b20 cmp r3, #32 8013698: f000 8088 beq.w 80137ac { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 801369c: 687b ldr r3, [r7, #4] 801369e: 681b ldr r3, [r3, #0] 80136a0: 330c adds r3, #12 80136a2: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80136a6: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 80136aa: e853 3f00 ldrex r3, [r3] 80136ae: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 80136b2: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 80136b6: f423 7380 bic.w r3, r3, #256 @ 0x100 80136ba: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 80136be: 687b ldr r3, [r7, #4] 80136c0: 681b ldr r3, [r3, #0] 80136c2: 330c adds r3, #12 80136c4: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 80136c8: f8c7 2094 str.w r2, [r7, #148] @ 0x94 80136cc: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80136d0: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 80136d4: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 80136d8: e841 2300 strex r3, r2, [r1] 80136dc: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 80136e0: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 80136e4: 2b00 cmp r3, #0 80136e6: d1d9 bne.n 801369c ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80136e8: 687b ldr r3, [r7, #4] 80136ea: 681b ldr r3, [r3, #0] 80136ec: 3314 adds r3, #20 80136ee: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80136f0: 6f7b ldr r3, [r7, #116] @ 0x74 80136f2: e853 3f00 ldrex r3, [r3] 80136f6: 673b str r3, [r7, #112] @ 0x70 return(result); 80136f8: 6f3b ldr r3, [r7, #112] @ 0x70 80136fa: f023 0301 bic.w r3, r3, #1 80136fe: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8013702: 687b ldr r3, [r7, #4] 8013704: 681b ldr r3, [r3, #0] 8013706: 3314 adds r3, #20 8013708: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 801370c: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8013710: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013712: 6ff9 ldr r1, [r7, #124] @ 0x7c 8013714: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8013718: e841 2300 strex r3, r2, [r1] 801371c: 67bb str r3, [r7, #120] @ 0x78 return(result); 801371e: 6fbb ldr r3, [r7, #120] @ 0x78 8013720: 2b00 cmp r3, #0 8013722: d1e1 bne.n 80136e8 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8013724: 687b ldr r3, [r7, #4] 8013726: 681b ldr r3, [r3, #0] 8013728: 3314 adds r3, #20 801372a: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801372c: 6e3b ldr r3, [r7, #96] @ 0x60 801372e: e853 3f00 ldrex r3, [r3] 8013732: 65fb str r3, [r7, #92] @ 0x5c return(result); 8013734: 6dfb ldr r3, [r7, #92] @ 0x5c 8013736: f023 0340 bic.w r3, r3, #64 @ 0x40 801373a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 801373e: 687b ldr r3, [r7, #4] 8013740: 681b ldr r3, [r3, #0] 8013742: 3314 adds r3, #20 8013744: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 8013748: 66fa str r2, [r7, #108] @ 0x6c 801374a: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801374c: 6eb9 ldr r1, [r7, #104] @ 0x68 801374e: 6efa ldr r2, [r7, #108] @ 0x6c 8013750: e841 2300 strex r3, r2, [r1] 8013754: 667b str r3, [r7, #100] @ 0x64 return(result); 8013756: 6e7b ldr r3, [r7, #100] @ 0x64 8013758: 2b00 cmp r3, #0 801375a: d1e3 bne.n 8013724 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 801375c: 687b ldr r3, [r7, #4] 801375e: 2220 movs r2, #32 8013760: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013764: 687b ldr r3, [r7, #4] 8013766: 2200 movs r2, #0 8013768: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801376a: 687b ldr r3, [r7, #4] 801376c: 681b ldr r3, [r3, #0] 801376e: 330c adds r3, #12 8013770: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013772: 6cfb ldr r3, [r7, #76] @ 0x4c 8013774: e853 3f00 ldrex r3, [r3] 8013778: 64bb str r3, [r7, #72] @ 0x48 return(result); 801377a: 6cbb ldr r3, [r7, #72] @ 0x48 801377c: f023 0310 bic.w r3, r3, #16 8013780: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8013784: 687b ldr r3, [r7, #4] 8013786: 681b ldr r3, [r3, #0] 8013788: 330c adds r3, #12 801378a: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 801378e: 65ba str r2, [r7, #88] @ 0x58 8013790: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013792: 6d79 ldr r1, [r7, #84] @ 0x54 8013794: 6dba ldr r2, [r7, #88] @ 0x58 8013796: e841 2300 strex r3, r2, [r1] 801379a: 653b str r3, [r7, #80] @ 0x50 return(result); 801379c: 6d3b ldr r3, [r7, #80] @ 0x50 801379e: 2b00 cmp r3, #0 80137a0: d1e3 bne.n 801376a /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 80137a2: 687b ldr r3, [r7, #4] 80137a4: 6bdb ldr r3, [r3, #60] @ 0x3c 80137a6: 4618 mov r0, r3 80137a8: f7fc fc36 bl 8010018 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 80137ac: 687b ldr r3, [r7, #4] 80137ae: 2202 movs r2, #2 80137b0: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 80137b2: 687b ldr r3, [r7, #4] 80137b4: 8d9a ldrh r2, [r3, #44] @ 0x2c 80137b6: 687b ldr r3, [r7, #4] 80137b8: 8ddb ldrh r3, [r3, #46] @ 0x2e 80137ba: b29b uxth r3, r3 80137bc: 1ad3 subs r3, r2, r3 80137be: b29b uxth r3, r3 80137c0: 4619 mov r1, r3 80137c2: 6878 ldr r0, [r7, #4] 80137c4: f7f9 f9f2 bl 800cbac #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 80137c8: e09c b.n 8013904 80137ca: bf00 nop 80137cc: 08013ec7 .word 0x08013ec7 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 80137d0: 687b ldr r3, [r7, #4] 80137d2: 8d9a ldrh r2, [r3, #44] @ 0x2c 80137d4: 687b ldr r3, [r7, #4] 80137d6: 8ddb ldrh r3, [r3, #46] @ 0x2e 80137d8: b29b uxth r3, r3 80137da: 1ad3 subs r3, r2, r3 80137dc: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 80137e0: 687b ldr r3, [r7, #4] 80137e2: 8ddb ldrh r3, [r3, #46] @ 0x2e 80137e4: b29b uxth r3, r3 80137e6: 2b00 cmp r3, #0 80137e8: f000 808e beq.w 8013908 && (nb_rx_data > 0U)) 80137ec: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 80137f0: 2b00 cmp r3, #0 80137f2: f000 8089 beq.w 8013908 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 80137f6: 687b ldr r3, [r7, #4] 80137f8: 681b ldr r3, [r3, #0] 80137fa: 330c adds r3, #12 80137fc: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80137fe: 6bbb ldr r3, [r7, #56] @ 0x38 8013800: e853 3f00 ldrex r3, [r3] 8013804: 637b str r3, [r7, #52] @ 0x34 return(result); 8013806: 6b7b ldr r3, [r7, #52] @ 0x34 8013808: f423 7390 bic.w r3, r3, #288 @ 0x120 801380c: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8013810: 687b ldr r3, [r7, #4] 8013812: 681b ldr r3, [r3, #0] 8013814: 330c adds r3, #12 8013816: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 801381a: 647a str r2, [r7, #68] @ 0x44 801381c: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801381e: 6c39 ldr r1, [r7, #64] @ 0x40 8013820: 6c7a ldr r2, [r7, #68] @ 0x44 8013822: e841 2300 strex r3, r2, [r1] 8013826: 63fb str r3, [r7, #60] @ 0x3c return(result); 8013828: 6bfb ldr r3, [r7, #60] @ 0x3c 801382a: 2b00 cmp r3, #0 801382c: d1e3 bne.n 80137f6 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 801382e: 687b ldr r3, [r7, #4] 8013830: 681b ldr r3, [r3, #0] 8013832: 3314 adds r3, #20 8013834: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013836: 6a7b ldr r3, [r7, #36] @ 0x24 8013838: e853 3f00 ldrex r3, [r3] 801383c: 623b str r3, [r7, #32] return(result); 801383e: 6a3b ldr r3, [r7, #32] 8013840: f023 0301 bic.w r3, r3, #1 8013844: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8013848: 687b ldr r3, [r7, #4] 801384a: 681b ldr r3, [r3, #0] 801384c: 3314 adds r3, #20 801384e: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 8013852: 633a str r2, [r7, #48] @ 0x30 8013854: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013856: 6af9 ldr r1, [r7, #44] @ 0x2c 8013858: 6b3a ldr r2, [r7, #48] @ 0x30 801385a: e841 2300 strex r3, r2, [r1] 801385e: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013860: 6abb ldr r3, [r7, #40] @ 0x28 8013862: 2b00 cmp r3, #0 8013864: d1e3 bne.n 801382e /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013866: 687b ldr r3, [r7, #4] 8013868: 2220 movs r2, #32 801386a: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 801386e: 687b ldr r3, [r7, #4] 8013870: 2200 movs r2, #0 8013872: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013874: 687b ldr r3, [r7, #4] 8013876: 681b ldr r3, [r3, #0] 8013878: 330c adds r3, #12 801387a: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801387c: 693b ldr r3, [r7, #16] 801387e: e853 3f00 ldrex r3, [r3] 8013882: 60fb str r3, [r7, #12] return(result); 8013884: 68fb ldr r3, [r7, #12] 8013886: f023 0310 bic.w r3, r3, #16 801388a: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 801388e: 687b ldr r3, [r7, #4] 8013890: 681b ldr r3, [r3, #0] 8013892: 330c adds r3, #12 8013894: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 8013898: 61fa str r2, [r7, #28] 801389a: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801389c: 69b9 ldr r1, [r7, #24] 801389e: 69fa ldr r2, [r7, #28] 80138a0: e841 2300 strex r3, r2, [r1] 80138a4: 617b str r3, [r7, #20] return(result); 80138a6: 697b ldr r3, [r7, #20] 80138a8: 2b00 cmp r3, #0 80138aa: d1e3 bne.n 8013874 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 80138ac: 687b ldr r3, [r7, #4] 80138ae: 2202 movs r2, #2 80138b0: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 80138b2: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 80138b6: 4619 mov r1, r3 80138b8: 6878 ldr r0, [r7, #4] 80138ba: f7f9 f977 bl 800cbac #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 80138be: e023 b.n 8013908 } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 80138c0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80138c4: f003 0380 and.w r3, r3, #128 @ 0x80 80138c8: 2b00 cmp r3, #0 80138ca: d009 beq.n 80138e0 80138cc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80138d0: f003 0380 and.w r3, r3, #128 @ 0x80 80138d4: 2b00 cmp r3, #0 80138d6: d003 beq.n 80138e0 { UART_Transmit_IT(huart); 80138d8: 6878 ldr r0, [r7, #4] 80138da: f000 fb08 bl 8013eee return; 80138de: e014 b.n 801390a } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 80138e0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80138e4: f003 0340 and.w r3, r3, #64 @ 0x40 80138e8: 2b00 cmp r3, #0 80138ea: d00e beq.n 801390a 80138ec: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80138f0: f003 0340 and.w r3, r3, #64 @ 0x40 80138f4: 2b00 cmp r3, #0 80138f6: d008 beq.n 801390a { UART_EndTransmit_IT(huart); 80138f8: 6878 ldr r0, [r7, #4] 80138fa: f000 fb47 bl 8013f8c return; 80138fe: e004 b.n 801390a return; 8013900: bf00 nop 8013902: e002 b.n 801390a return; 8013904: bf00 nop 8013906: e000 b.n 801390a return; 8013908: bf00 nop } } 801390a: 37e8 adds r7, #232 @ 0xe8 801390c: 46bd mov sp, r7 801390e: bd80 pop {r7, pc} 08013910 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 8013910: b480 push {r7} 8013912: b083 sub sp, #12 8013914: af00 add r7, sp, #0 8013916: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback could be implemented in the user file */ } 8013918: bf00 nop 801391a: 370c adds r7, #12 801391c: 46bd mov sp, r7 801391e: bc80 pop {r7} 8013920: 4770 bx lr 08013922 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8013922: b480 push {r7} 8013924: b083 sub sp, #12 8013926: af00 add r7, sp, #0 8013928: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback could be implemented in the user file */ } 801392a: bf00 nop 801392c: 370c adds r7, #12 801392e: 46bd mov sp, r7 8013930: bc80 pop {r7} 8013932: 4770 bx lr 08013934 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { 8013934: b480 push {r7} 8013936: b083 sub sp, #12 8013938: af00 add r7, sp, #0 801393a: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback could be implemented in the user file */ } 801393c: bf00 nop 801393e: 370c adds r7, #12 8013940: 46bd mov sp, r7 8013942: bc80 pop {r7} 8013944: 4770 bx lr 08013946 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART. * @retval UART Error Code */ uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) { 8013946: b480 push {r7} 8013948: b083 sub sp, #12 801394a: af00 add r7, sp, #0 801394c: 6078 str r0, [r7, #4] return huart->ErrorCode; 801394e: 687b ldr r3, [r7, #4] 8013950: 6c5b ldr r3, [r3, #68] @ 0x44 } 8013952: 4618 mov r0, r3 8013954: 370c adds r7, #12 8013956: 46bd mov sp, r7 8013958: bc80 pop {r7} 801395a: 4770 bx lr 0801395c : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 801395c: b580 push {r7, lr} 801395e: b090 sub sp, #64 @ 0x40 8013960: af00 add r7, sp, #0 8013962: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013964: 687b ldr r3, [r7, #4] 8013966: 6a5b ldr r3, [r3, #36] @ 0x24 8013968: 63fb str r3, [r7, #60] @ 0x3c /* DMA Normal mode*/ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 801396a: 687b ldr r3, [r7, #4] 801396c: 681b ldr r3, [r3, #0] 801396e: 681b ldr r3, [r3, #0] 8013970: f003 0320 and.w r3, r3, #32 8013974: 2b00 cmp r3, #0 8013976: d137 bne.n 80139e8 { huart->TxXferCount = 0x00U; 8013978: 6bfb ldr r3, [r7, #60] @ 0x3c 801397a: 2200 movs r2, #0 801397c: 84da strh r2, [r3, #38] @ 0x26 /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 801397e: 6bfb ldr r3, [r7, #60] @ 0x3c 8013980: 681b ldr r3, [r3, #0] 8013982: 3314 adds r3, #20 8013984: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013986: 6a7b ldr r3, [r7, #36] @ 0x24 8013988: e853 3f00 ldrex r3, [r3] 801398c: 623b str r3, [r7, #32] return(result); 801398e: 6a3b ldr r3, [r7, #32] 8013990: f023 0380 bic.w r3, r3, #128 @ 0x80 8013994: 63bb str r3, [r7, #56] @ 0x38 8013996: 6bfb ldr r3, [r7, #60] @ 0x3c 8013998: 681b ldr r3, [r3, #0] 801399a: 3314 adds r3, #20 801399c: 6bba ldr r2, [r7, #56] @ 0x38 801399e: 633a str r2, [r7, #48] @ 0x30 80139a0: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80139a2: 6af9 ldr r1, [r7, #44] @ 0x2c 80139a4: 6b3a ldr r2, [r7, #48] @ 0x30 80139a6: e841 2300 strex r3, r2, [r1] 80139aa: 62bb str r3, [r7, #40] @ 0x28 return(result); 80139ac: 6abb ldr r3, [r7, #40] @ 0x28 80139ae: 2b00 cmp r3, #0 80139b0: d1e5 bne.n 801397e /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80139b2: 6bfb ldr r3, [r7, #60] @ 0x3c 80139b4: 681b ldr r3, [r3, #0] 80139b6: 330c adds r3, #12 80139b8: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80139ba: 693b ldr r3, [r7, #16] 80139bc: e853 3f00 ldrex r3, [r3] 80139c0: 60fb str r3, [r7, #12] return(result); 80139c2: 68fb ldr r3, [r7, #12] 80139c4: f043 0340 orr.w r3, r3, #64 @ 0x40 80139c8: 637b str r3, [r7, #52] @ 0x34 80139ca: 6bfb ldr r3, [r7, #60] @ 0x3c 80139cc: 681b ldr r3, [r3, #0] 80139ce: 330c adds r3, #12 80139d0: 6b7a ldr r2, [r7, #52] @ 0x34 80139d2: 61fa str r2, [r7, #28] 80139d4: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80139d6: 69b9 ldr r1, [r7, #24] 80139d8: 69fa ldr r2, [r7, #28] 80139da: e841 2300 strex r3, r2, [r1] 80139de: 617b str r3, [r7, #20] return(result); 80139e0: 697b ldr r3, [r7, #20] 80139e2: 2b00 cmp r3, #0 80139e4: d1e5 bne.n 80139b2 #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 80139e6: e002 b.n 80139ee HAL_UART_TxCpltCallback(huart); 80139e8: 6bf8 ldr r0, [r7, #60] @ 0x3c 80139ea: f7f9 f959 bl 800cca0 } 80139ee: bf00 nop 80139f0: 3740 adds r7, #64 @ 0x40 80139f2: 46bd mov sp, r7 80139f4: bd80 pop {r7, pc} 080139f6 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 80139f6: b580 push {r7, lr} 80139f8: b084 sub sp, #16 80139fa: af00 add r7, sp, #0 80139fc: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80139fe: 687b ldr r3, [r7, #4] 8013a00: 6a5b ldr r3, [r3, #36] @ 0x24 8013a02: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 8013a04: 68f8 ldr r0, [r7, #12] 8013a06: f7ff ff83 bl 8013910 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8013a0a: bf00 nop 8013a0c: 3710 adds r7, #16 8013a0e: 46bd mov sp, r7 8013a10: bd80 pop {r7, pc} 08013a12 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 8013a12: b580 push {r7, lr} 8013a14: b09c sub sp, #112 @ 0x70 8013a16: af00 add r7, sp, #0 8013a18: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013a1a: 687b ldr r3, [r7, #4] 8013a1c: 6a5b ldr r3, [r3, #36] @ 0x24 8013a1e: 66fb str r3, [r7, #108] @ 0x6c /* DMA Normal mode*/ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8013a20: 687b ldr r3, [r7, #4] 8013a22: 681b ldr r3, [r3, #0] 8013a24: 681b ldr r3, [r3, #0] 8013a26: f003 0320 and.w r3, r3, #32 8013a2a: 2b00 cmp r3, #0 8013a2c: d172 bne.n 8013b14 { huart->RxXferCount = 0U; 8013a2e: 6efb ldr r3, [r7, #108] @ 0x6c 8013a30: 2200 movs r2, #0 8013a32: 85da strh r2, [r3, #46] @ 0x2e /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8013a34: 6efb ldr r3, [r7, #108] @ 0x6c 8013a36: 681b ldr r3, [r3, #0] 8013a38: 330c adds r3, #12 8013a3a: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013a3c: 6cfb ldr r3, [r7, #76] @ 0x4c 8013a3e: e853 3f00 ldrex r3, [r3] 8013a42: 64bb str r3, [r7, #72] @ 0x48 return(result); 8013a44: 6cbb ldr r3, [r7, #72] @ 0x48 8013a46: f423 7380 bic.w r3, r3, #256 @ 0x100 8013a4a: 66bb str r3, [r7, #104] @ 0x68 8013a4c: 6efb ldr r3, [r7, #108] @ 0x6c 8013a4e: 681b ldr r3, [r3, #0] 8013a50: 330c adds r3, #12 8013a52: 6eba ldr r2, [r7, #104] @ 0x68 8013a54: 65ba str r2, [r7, #88] @ 0x58 8013a56: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013a58: 6d79 ldr r1, [r7, #84] @ 0x54 8013a5a: 6dba ldr r2, [r7, #88] @ 0x58 8013a5c: e841 2300 strex r3, r2, [r1] 8013a60: 653b str r3, [r7, #80] @ 0x50 return(result); 8013a62: 6d3b ldr r3, [r7, #80] @ 0x50 8013a64: 2b00 cmp r3, #0 8013a66: d1e5 bne.n 8013a34 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013a68: 6efb ldr r3, [r7, #108] @ 0x6c 8013a6a: 681b ldr r3, [r3, #0] 8013a6c: 3314 adds r3, #20 8013a6e: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013a70: 6bbb ldr r3, [r7, #56] @ 0x38 8013a72: e853 3f00 ldrex r3, [r3] 8013a76: 637b str r3, [r7, #52] @ 0x34 return(result); 8013a78: 6b7b ldr r3, [r7, #52] @ 0x34 8013a7a: f023 0301 bic.w r3, r3, #1 8013a7e: 667b str r3, [r7, #100] @ 0x64 8013a80: 6efb ldr r3, [r7, #108] @ 0x6c 8013a82: 681b ldr r3, [r3, #0] 8013a84: 3314 adds r3, #20 8013a86: 6e7a ldr r2, [r7, #100] @ 0x64 8013a88: 647a str r2, [r7, #68] @ 0x44 8013a8a: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013a8c: 6c39 ldr r1, [r7, #64] @ 0x40 8013a8e: 6c7a ldr r2, [r7, #68] @ 0x44 8013a90: e841 2300 strex r3, r2, [r1] 8013a94: 63fb str r3, [r7, #60] @ 0x3c return(result); 8013a96: 6bfb ldr r3, [r7, #60] @ 0x3c 8013a98: 2b00 cmp r3, #0 8013a9a: d1e5 bne.n 8013a68 /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8013a9c: 6efb ldr r3, [r7, #108] @ 0x6c 8013a9e: 681b ldr r3, [r3, #0] 8013aa0: 3314 adds r3, #20 8013aa2: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013aa4: 6a7b ldr r3, [r7, #36] @ 0x24 8013aa6: e853 3f00 ldrex r3, [r3] 8013aaa: 623b str r3, [r7, #32] return(result); 8013aac: 6a3b ldr r3, [r7, #32] 8013aae: f023 0340 bic.w r3, r3, #64 @ 0x40 8013ab2: 663b str r3, [r7, #96] @ 0x60 8013ab4: 6efb ldr r3, [r7, #108] @ 0x6c 8013ab6: 681b ldr r3, [r3, #0] 8013ab8: 3314 adds r3, #20 8013aba: 6e3a ldr r2, [r7, #96] @ 0x60 8013abc: 633a str r2, [r7, #48] @ 0x30 8013abe: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013ac0: 6af9 ldr r1, [r7, #44] @ 0x2c 8013ac2: 6b3a ldr r2, [r7, #48] @ 0x30 8013ac4: e841 2300 strex r3, r2, [r1] 8013ac8: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013aca: 6abb ldr r3, [r7, #40] @ 0x28 8013acc: 2b00 cmp r3, #0 8013ace: d1e5 bne.n 8013a9c /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013ad0: 6efb ldr r3, [r7, #108] @ 0x6c 8013ad2: 2220 movs r2, #32 8013ad4: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013ad8: 6efb ldr r3, [r7, #108] @ 0x6c 8013ada: 6b1b ldr r3, [r3, #48] @ 0x30 8013adc: 2b01 cmp r3, #1 8013ade: d119 bne.n 8013b14 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013ae0: 6efb ldr r3, [r7, #108] @ 0x6c 8013ae2: 681b ldr r3, [r3, #0] 8013ae4: 330c adds r3, #12 8013ae6: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013ae8: 693b ldr r3, [r7, #16] 8013aea: e853 3f00 ldrex r3, [r3] 8013aee: 60fb str r3, [r7, #12] return(result); 8013af0: 68fb ldr r3, [r7, #12] 8013af2: f023 0310 bic.w r3, r3, #16 8013af6: 65fb str r3, [r7, #92] @ 0x5c 8013af8: 6efb ldr r3, [r7, #108] @ 0x6c 8013afa: 681b ldr r3, [r3, #0] 8013afc: 330c adds r3, #12 8013afe: 6dfa ldr r2, [r7, #92] @ 0x5c 8013b00: 61fa str r2, [r7, #28] 8013b02: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013b04: 69b9 ldr r1, [r7, #24] 8013b06: 69fa ldr r2, [r7, #28] 8013b08: e841 2300 strex r3, r2, [r1] 8013b0c: 617b str r3, [r7, #20] return(result); 8013b0e: 697b ldr r3, [r7, #20] 8013b10: 2b00 cmp r3, #0 8013b12: d1e5 bne.n 8013ae0 } } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8013b14: 6efb ldr r3, [r7, #108] @ 0x6c 8013b16: 2200 movs r2, #0 8013b18: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013b1a: 6efb ldr r3, [r7, #108] @ 0x6c 8013b1c: 6b1b ldr r3, [r3, #48] @ 0x30 8013b1e: 2b01 cmp r3, #1 8013b20: d106 bne.n 8013b30 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8013b22: 6efb ldr r3, [r7, #108] @ 0x6c 8013b24: 8d9b ldrh r3, [r3, #44] @ 0x2c 8013b26: 4619 mov r1, r3 8013b28: 6ef8 ldr r0, [r7, #108] @ 0x6c 8013b2a: f7f9 f83f bl 800cbac #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8013b2e: e002 b.n 8013b36 HAL_UART_RxCpltCallback(huart); 8013b30: 6ef8 ldr r0, [r7, #108] @ 0x6c 8013b32: f7ff fef6 bl 8013922 } 8013b36: bf00 nop 8013b38: 3770 adds r7, #112 @ 0x70 8013b3a: 46bd mov sp, r7 8013b3c: bd80 pop {r7, pc} 08013b3e : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { 8013b3e: b580 push {r7, lr} 8013b40: b084 sub sp, #16 8013b42: af00 add r7, sp, #0 8013b44: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013b46: 687b ldr r3, [r7, #4] 8013b48: 6a5b ldr r3, [r3, #36] @ 0x24 8013b4a: 60fb str r3, [r7, #12] /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Half Transfer */ huart->RxEventType = HAL_UART_RXEVENT_HT; 8013b4c: 68fb ldr r3, [r7, #12] 8013b4e: 2201 movs r2, #1 8013b50: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013b52: 68fb ldr r3, [r7, #12] 8013b54: 6b1b ldr r3, [r3, #48] @ 0x30 8013b56: 2b01 cmp r3, #1 8013b58: d108 bne.n 8013b6c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); 8013b5a: 68fb ldr r3, [r7, #12] 8013b5c: 8d9b ldrh r3, [r3, #44] @ 0x2c 8013b5e: 085b lsrs r3, r3, #1 8013b60: b29b uxth r3, r3 8013b62: 4619 mov r1, r3 8013b64: 68f8 ldr r0, [r7, #12] 8013b66: f7f9 f821 bl 800cbac #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8013b6a: e002 b.n 8013b72 HAL_UART_RxHalfCpltCallback(huart); 8013b6c: 68f8 ldr r0, [r7, #12] 8013b6e: f7ff fee1 bl 8013934 } 8013b72: bf00 nop 8013b74: 3710 adds r7, #16 8013b76: 46bd mov sp, r7 8013b78: bd80 pop {r7, pc} 08013b7a : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 8013b7a: b580 push {r7, lr} 8013b7c: b084 sub sp, #16 8013b7e: af00 add r7, sp, #0 8013b80: 6078 str r0, [r7, #4] uint32_t dmarequest = 0x00U; 8013b82: 2300 movs r3, #0 8013b84: 60fb str r3, [r7, #12] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013b86: 687b ldr r3, [r7, #4] 8013b88: 6a5b ldr r3, [r3, #36] @ 0x24 8013b8a: 60bb str r3, [r7, #8] /* Stop UART DMA Tx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 8013b8c: 68bb ldr r3, [r7, #8] 8013b8e: 681b ldr r3, [r3, #0] 8013b90: 695b ldr r3, [r3, #20] 8013b92: f003 0380 and.w r3, r3, #128 @ 0x80 8013b96: 2b00 cmp r3, #0 8013b98: bf14 ite ne 8013b9a: 2301 movne r3, #1 8013b9c: 2300 moveq r3, #0 8013b9e: b2db uxtb r3, r3 8013ba0: 60fb str r3, [r7, #12] if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 8013ba2: 68bb ldr r3, [r7, #8] 8013ba4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8013ba8: b2db uxtb r3, r3 8013baa: 2b21 cmp r3, #33 @ 0x21 8013bac: d108 bne.n 8013bc0 8013bae: 68fb ldr r3, [r7, #12] 8013bb0: 2b00 cmp r3, #0 8013bb2: d005 beq.n 8013bc0 { huart->TxXferCount = 0x00U; 8013bb4: 68bb ldr r3, [r7, #8] 8013bb6: 2200 movs r2, #0 8013bb8: 84da strh r2, [r3, #38] @ 0x26 UART_EndTxTransfer(huart); 8013bba: 68b8 ldr r0, [r7, #8] 8013bbc: f000 f8fa bl 8013db4 } /* Stop UART DMA Rx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8013bc0: 68bb ldr r3, [r7, #8] 8013bc2: 681b ldr r3, [r3, #0] 8013bc4: 695b ldr r3, [r3, #20] 8013bc6: f003 0340 and.w r3, r3, #64 @ 0x40 8013bca: 2b00 cmp r3, #0 8013bcc: bf14 ite ne 8013bce: 2301 movne r3, #1 8013bd0: 2300 moveq r3, #0 8013bd2: b2db uxtb r3, r3 8013bd4: 60fb str r3, [r7, #12] if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 8013bd6: 68bb ldr r3, [r7, #8] 8013bd8: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8013bdc: b2db uxtb r3, r3 8013bde: 2b22 cmp r3, #34 @ 0x22 8013be0: d108 bne.n 8013bf4 8013be2: 68fb ldr r3, [r7, #12] 8013be4: 2b00 cmp r3, #0 8013be6: d005 beq.n 8013bf4 { huart->RxXferCount = 0x00U; 8013be8: 68bb ldr r3, [r7, #8] 8013bea: 2200 movs r2, #0 8013bec: 85da strh r2, [r3, #46] @ 0x2e UART_EndRxTransfer(huart); 8013bee: 68b8 ldr r0, [r7, #8] 8013bf0: f000 f907 bl 8013e02 } huart->ErrorCode |= HAL_UART_ERROR_DMA; 8013bf4: 68bb ldr r3, [r7, #8] 8013bf6: 6c5b ldr r3, [r3, #68] @ 0x44 8013bf8: f043 0210 orr.w r2, r3, #16 8013bfc: 68bb ldr r3, [r7, #8] 8013bfe: 645a str r2, [r3, #68] @ 0x44 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013c00: 68b8 ldr r0, [r7, #8] 8013c02: f7f8 f889 bl 800bd18 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8013c06: bf00 nop 8013c08: 3710 adds r7, #16 8013c0a: 46bd mov sp, r7 8013c0c: bd80 pop {r7, pc} 08013c0e : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8013c0e: b480 push {r7} 8013c10: b085 sub sp, #20 8013c12: af00 add r7, sp, #0 8013c14: 60f8 str r0, [r7, #12] 8013c16: 60b9 str r1, [r7, #8] 8013c18: 4613 mov r3, r2 8013c1a: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 8013c1c: 68fb ldr r3, [r7, #12] 8013c1e: 68ba ldr r2, [r7, #8] 8013c20: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 8013c22: 68fb ldr r3, [r7, #12] 8013c24: 88fa ldrh r2, [r7, #6] 8013c26: 859a strh r2, [r3, #44] @ 0x2c huart->RxXferCount = Size; 8013c28: 68fb ldr r3, [r7, #12] 8013c2a: 88fa ldrh r2, [r7, #6] 8013c2c: 85da strh r2, [r3, #46] @ 0x2e huart->ErrorCode = HAL_UART_ERROR_NONE; 8013c2e: 68fb ldr r3, [r7, #12] 8013c30: 2200 movs r2, #0 8013c32: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 8013c34: 68fb ldr r3, [r7, #12] 8013c36: 2222 movs r2, #34 @ 0x22 8013c38: f883 2042 strb.w r2, [r3, #66] @ 0x42 if (huart->Init.Parity != UART_PARITY_NONE) 8013c3c: 68fb ldr r3, [r7, #12] 8013c3e: 691b ldr r3, [r3, #16] 8013c40: 2b00 cmp r3, #0 8013c42: d007 beq.n 8013c54 { /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); 8013c44: 68fb ldr r3, [r7, #12] 8013c46: 681b ldr r3, [r3, #0] 8013c48: 68da ldr r2, [r3, #12] 8013c4a: 68fb ldr r3, [r7, #12] 8013c4c: 681b ldr r3, [r3, #0] 8013c4e: f442 7280 orr.w r2, r2, #256 @ 0x100 8013c52: 60da str r2, [r3, #12] } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); 8013c54: 68fb ldr r3, [r7, #12] 8013c56: 681b ldr r3, [r3, #0] 8013c58: 695a ldr r2, [r3, #20] 8013c5a: 68fb ldr r3, [r7, #12] 8013c5c: 681b ldr r3, [r3, #0] 8013c5e: f042 0201 orr.w r2, r2, #1 8013c62: 615a str r2, [r3, #20] /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); 8013c64: 68fb ldr r3, [r7, #12] 8013c66: 681b ldr r3, [r3, #0] 8013c68: 68da ldr r2, [r3, #12] 8013c6a: 68fb ldr r3, [r7, #12] 8013c6c: 681b ldr r3, [r3, #0] 8013c6e: f042 0220 orr.w r2, r2, #32 8013c72: 60da str r2, [r3, #12] return HAL_OK; 8013c74: 2300 movs r3, #0 } 8013c76: 4618 mov r0, r3 8013c78: 3714 adds r7, #20 8013c7a: 46bd mov sp, r7 8013c7c: bc80 pop {r7} 8013c7e: 4770 bx lr 08013c80 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8013c80: b580 push {r7, lr} 8013c82: b098 sub sp, #96 @ 0x60 8013c84: af00 add r7, sp, #0 8013c86: 60f8 str r0, [r7, #12] 8013c88: 60b9 str r1, [r7, #8] 8013c8a: 4613 mov r3, r2 8013c8c: 80fb strh r3, [r7, #6] uint32_t *tmp; huart->pRxBuffPtr = pData; 8013c8e: 68ba ldr r2, [r7, #8] 8013c90: 68fb ldr r3, [r7, #12] 8013c92: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 8013c94: 68fb ldr r3, [r7, #12] 8013c96: 88fa ldrh r2, [r7, #6] 8013c98: 859a strh r2, [r3, #44] @ 0x2c huart->ErrorCode = HAL_UART_ERROR_NONE; 8013c9a: 68fb ldr r3, [r7, #12] 8013c9c: 2200 movs r2, #0 8013c9e: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 8013ca0: 68fb ldr r3, [r7, #12] 8013ca2: 2222 movs r2, #34 @ 0x22 8013ca4: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 8013ca8: 68fb ldr r3, [r7, #12] 8013caa: 6bdb ldr r3, [r3, #60] @ 0x3c 8013cac: 4a3e ldr r2, [pc, #248] @ (8013da8 ) 8013cae: 629a str r2, [r3, #40] @ 0x28 /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 8013cb0: 68fb ldr r3, [r7, #12] 8013cb2: 6bdb ldr r3, [r3, #60] @ 0x3c 8013cb4: 4a3d ldr r2, [pc, #244] @ (8013dac ) 8013cb6: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; 8013cb8: 68fb ldr r3, [r7, #12] 8013cba: 6bdb ldr r3, [r3, #60] @ 0x3c 8013cbc: 4a3c ldr r2, [pc, #240] @ (8013db0 ) 8013cbe: 631a str r2, [r3, #48] @ 0x30 /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; 8013cc0: 68fb ldr r3, [r7, #12] 8013cc2: 6bdb ldr r3, [r3, #60] @ 0x3c 8013cc4: 2200 movs r2, #0 8013cc6: 635a str r2, [r3, #52] @ 0x34 /* Enable the DMA stream */ tmp = (uint32_t *)&pData; 8013cc8: f107 0308 add.w r3, r7, #8 8013ccc: 65fb str r3, [r7, #92] @ 0x5c HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size); 8013cce: 68fb ldr r3, [r7, #12] 8013cd0: 6bd8 ldr r0, [r3, #60] @ 0x3c 8013cd2: 68fb ldr r3, [r7, #12] 8013cd4: 681b ldr r3, [r3, #0] 8013cd6: 3304 adds r3, #4 8013cd8: 4619 mov r1, r3 8013cda: 6dfb ldr r3, [r7, #92] @ 0x5c 8013cdc: 681a ldr r2, [r3, #0] 8013cde: 88fb ldrh r3, [r7, #6] 8013ce0: f7fc f93a bl 800ff58 /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ __HAL_UART_CLEAR_OREFLAG(huart); 8013ce4: 2300 movs r3, #0 8013ce6: 613b str r3, [r7, #16] 8013ce8: 68fb ldr r3, [r7, #12] 8013cea: 681b ldr r3, [r3, #0] 8013cec: 681b ldr r3, [r3, #0] 8013cee: 613b str r3, [r7, #16] 8013cf0: 68fb ldr r3, [r7, #12] 8013cf2: 681b ldr r3, [r3, #0] 8013cf4: 685b ldr r3, [r3, #4] 8013cf6: 613b str r3, [r7, #16] 8013cf8: 693b ldr r3, [r7, #16] if (huart->Init.Parity != UART_PARITY_NONE) 8013cfa: 68fb ldr r3, [r7, #12] 8013cfc: 691b ldr r3, [r3, #16] 8013cfe: 2b00 cmp r3, #0 8013d00: d019 beq.n 8013d36 { /* Enable the UART Parity Error Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8013d02: 68fb ldr r3, [r7, #12] 8013d04: 681b ldr r3, [r3, #0] 8013d06: 330c adds r3, #12 8013d08: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013d0a: 6c3b ldr r3, [r7, #64] @ 0x40 8013d0c: e853 3f00 ldrex r3, [r3] 8013d10: 63fb str r3, [r7, #60] @ 0x3c return(result); 8013d12: 6bfb ldr r3, [r7, #60] @ 0x3c 8013d14: f443 7380 orr.w r3, r3, #256 @ 0x100 8013d18: 65bb str r3, [r7, #88] @ 0x58 8013d1a: 68fb ldr r3, [r7, #12] 8013d1c: 681b ldr r3, [r3, #0] 8013d1e: 330c adds r3, #12 8013d20: 6dba ldr r2, [r7, #88] @ 0x58 8013d22: 64fa str r2, [r7, #76] @ 0x4c 8013d24: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013d26: 6cb9 ldr r1, [r7, #72] @ 0x48 8013d28: 6cfa ldr r2, [r7, #76] @ 0x4c 8013d2a: e841 2300 strex r3, r2, [r1] 8013d2e: 647b str r3, [r7, #68] @ 0x44 return(result); 8013d30: 6c7b ldr r3, [r7, #68] @ 0x44 8013d32: 2b00 cmp r3, #0 8013d34: d1e5 bne.n 8013d02 } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013d36: 68fb ldr r3, [r7, #12] 8013d38: 681b ldr r3, [r3, #0] 8013d3a: 3314 adds r3, #20 8013d3c: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013d3e: 6afb ldr r3, [r7, #44] @ 0x2c 8013d40: e853 3f00 ldrex r3, [r3] 8013d44: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013d46: 6abb ldr r3, [r7, #40] @ 0x28 8013d48: f043 0301 orr.w r3, r3, #1 8013d4c: 657b str r3, [r7, #84] @ 0x54 8013d4e: 68fb ldr r3, [r7, #12] 8013d50: 681b ldr r3, [r3, #0] 8013d52: 3314 adds r3, #20 8013d54: 6d7a ldr r2, [r7, #84] @ 0x54 8013d56: 63ba str r2, [r7, #56] @ 0x38 8013d58: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013d5a: 6b79 ldr r1, [r7, #52] @ 0x34 8013d5c: 6bba ldr r2, [r7, #56] @ 0x38 8013d5e: e841 2300 strex r3, r2, [r1] 8013d62: 633b str r3, [r7, #48] @ 0x30 return(result); 8013d64: 6b3b ldr r3, [r7, #48] @ 0x30 8013d66: 2b00 cmp r3, #0 8013d68: d1e5 bne.n 8013d36 /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8013d6a: 68fb ldr r3, [r7, #12] 8013d6c: 681b ldr r3, [r3, #0] 8013d6e: 3314 adds r3, #20 8013d70: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013d72: 69bb ldr r3, [r7, #24] 8013d74: e853 3f00 ldrex r3, [r3] 8013d78: 617b str r3, [r7, #20] return(result); 8013d7a: 697b ldr r3, [r7, #20] 8013d7c: f043 0340 orr.w r3, r3, #64 @ 0x40 8013d80: 653b str r3, [r7, #80] @ 0x50 8013d82: 68fb ldr r3, [r7, #12] 8013d84: 681b ldr r3, [r3, #0] 8013d86: 3314 adds r3, #20 8013d88: 6d3a ldr r2, [r7, #80] @ 0x50 8013d8a: 627a str r2, [r7, #36] @ 0x24 8013d8c: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013d8e: 6a39 ldr r1, [r7, #32] 8013d90: 6a7a ldr r2, [r7, #36] @ 0x24 8013d92: e841 2300 strex r3, r2, [r1] 8013d96: 61fb str r3, [r7, #28] return(result); 8013d98: 69fb ldr r3, [r7, #28] 8013d9a: 2b00 cmp r3, #0 8013d9c: d1e5 bne.n 8013d6a return HAL_OK; 8013d9e: 2300 movs r3, #0 } 8013da0: 4618 mov r0, r3 8013da2: 3760 adds r7, #96 @ 0x60 8013da4: 46bd mov sp, r7 8013da6: bd80 pop {r7, pc} 8013da8: 08013a13 .word 0x08013a13 8013dac: 08013b3f .word 0x08013b3f 8013db0: 08013b7b .word 0x08013b7b 08013db4 : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 8013db4: b480 push {r7} 8013db6: b089 sub sp, #36 @ 0x24 8013db8: af00 add r7, sp, #0 8013dba: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 8013dbc: 687b ldr r3, [r7, #4] 8013dbe: 681b ldr r3, [r3, #0] 8013dc0: 330c adds r3, #12 8013dc2: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013dc4: 68fb ldr r3, [r7, #12] 8013dc6: e853 3f00 ldrex r3, [r3] 8013dca: 60bb str r3, [r7, #8] return(result); 8013dcc: 68bb ldr r3, [r7, #8] 8013dce: f023 03c0 bic.w r3, r3, #192 @ 0xc0 8013dd2: 61fb str r3, [r7, #28] 8013dd4: 687b ldr r3, [r7, #4] 8013dd6: 681b ldr r3, [r3, #0] 8013dd8: 330c adds r3, #12 8013dda: 69fa ldr r2, [r7, #28] 8013ddc: 61ba str r2, [r7, #24] 8013dde: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013de0: 6979 ldr r1, [r7, #20] 8013de2: 69ba ldr r2, [r7, #24] 8013de4: e841 2300 strex r3, r2, [r1] 8013de8: 613b str r3, [r7, #16] return(result); 8013dea: 693b ldr r3, [r7, #16] 8013dec: 2b00 cmp r3, #0 8013dee: d1e5 bne.n 8013dbc /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8013df0: 687b ldr r3, [r7, #4] 8013df2: 2220 movs r2, #32 8013df4: f883 2041 strb.w r2, [r3, #65] @ 0x41 } 8013df8: bf00 nop 8013dfa: 3724 adds r7, #36 @ 0x24 8013dfc: 46bd mov sp, r7 8013dfe: bc80 pop {r7} 8013e00: 4770 bx lr 08013e02 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8013e02: b480 push {r7} 8013e04: b095 sub sp, #84 @ 0x54 8013e06: af00 add r7, sp, #0 8013e08: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8013e0a: 687b ldr r3, [r7, #4] 8013e0c: 681b ldr r3, [r3, #0] 8013e0e: 330c adds r3, #12 8013e10: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013e12: 6b7b ldr r3, [r7, #52] @ 0x34 8013e14: e853 3f00 ldrex r3, [r3] 8013e18: 633b str r3, [r7, #48] @ 0x30 return(result); 8013e1a: 6b3b ldr r3, [r7, #48] @ 0x30 8013e1c: f423 7390 bic.w r3, r3, #288 @ 0x120 8013e20: 64fb str r3, [r7, #76] @ 0x4c 8013e22: 687b ldr r3, [r7, #4] 8013e24: 681b ldr r3, [r3, #0] 8013e26: 330c adds r3, #12 8013e28: 6cfa ldr r2, [r7, #76] @ 0x4c 8013e2a: 643a str r2, [r7, #64] @ 0x40 8013e2c: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013e2e: 6bf9 ldr r1, [r7, #60] @ 0x3c 8013e30: 6c3a ldr r2, [r7, #64] @ 0x40 8013e32: e841 2300 strex r3, r2, [r1] 8013e36: 63bb str r3, [r7, #56] @ 0x38 return(result); 8013e38: 6bbb ldr r3, [r7, #56] @ 0x38 8013e3a: 2b00 cmp r3, #0 8013e3c: d1e5 bne.n 8013e0a ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013e3e: 687b ldr r3, [r7, #4] 8013e40: 681b ldr r3, [r3, #0] 8013e42: 3314 adds r3, #20 8013e44: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013e46: 6a3b ldr r3, [r7, #32] 8013e48: e853 3f00 ldrex r3, [r3] 8013e4c: 61fb str r3, [r7, #28] return(result); 8013e4e: 69fb ldr r3, [r7, #28] 8013e50: f023 0301 bic.w r3, r3, #1 8013e54: 64bb str r3, [r7, #72] @ 0x48 8013e56: 687b ldr r3, [r7, #4] 8013e58: 681b ldr r3, [r3, #0] 8013e5a: 3314 adds r3, #20 8013e5c: 6cba ldr r2, [r7, #72] @ 0x48 8013e5e: 62fa str r2, [r7, #44] @ 0x2c 8013e60: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013e62: 6ab9 ldr r1, [r7, #40] @ 0x28 8013e64: 6afa ldr r2, [r7, #44] @ 0x2c 8013e66: e841 2300 strex r3, r2, [r1] 8013e6a: 627b str r3, [r7, #36] @ 0x24 return(result); 8013e6c: 6a7b ldr r3, [r7, #36] @ 0x24 8013e6e: 2b00 cmp r3, #0 8013e70: d1e5 bne.n 8013e3e /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013e72: 687b ldr r3, [r7, #4] 8013e74: 6b1b ldr r3, [r3, #48] @ 0x30 8013e76: 2b01 cmp r3, #1 8013e78: d119 bne.n 8013eae { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013e7a: 687b ldr r3, [r7, #4] 8013e7c: 681b ldr r3, [r3, #0] 8013e7e: 330c adds r3, #12 8013e80: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013e82: 68fb ldr r3, [r7, #12] 8013e84: e853 3f00 ldrex r3, [r3] 8013e88: 60bb str r3, [r7, #8] return(result); 8013e8a: 68bb ldr r3, [r7, #8] 8013e8c: f023 0310 bic.w r3, r3, #16 8013e90: 647b str r3, [r7, #68] @ 0x44 8013e92: 687b ldr r3, [r7, #4] 8013e94: 681b ldr r3, [r3, #0] 8013e96: 330c adds r3, #12 8013e98: 6c7a ldr r2, [r7, #68] @ 0x44 8013e9a: 61ba str r2, [r7, #24] 8013e9c: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013e9e: 6979 ldr r1, [r7, #20] 8013ea0: 69ba ldr r2, [r7, #24] 8013ea2: e841 2300 strex r3, r2, [r1] 8013ea6: 613b str r3, [r7, #16] return(result); 8013ea8: 693b ldr r3, [r7, #16] 8013eaa: 2b00 cmp r3, #0 8013eac: d1e5 bne.n 8013e7a } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013eae: 687b ldr r3, [r7, #4] 8013eb0: 2220 movs r2, #32 8013eb2: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013eb6: 687b ldr r3, [r7, #4] 8013eb8: 2200 movs r2, #0 8013eba: 631a str r2, [r3, #48] @ 0x30 } 8013ebc: bf00 nop 8013ebe: 3754 adds r7, #84 @ 0x54 8013ec0: 46bd mov sp, r7 8013ec2: bc80 pop {r7} 8013ec4: 4770 bx lr 08013ec6 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8013ec6: b580 push {r7, lr} 8013ec8: b084 sub sp, #16 8013eca: af00 add r7, sp, #0 8013ecc: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8013ece: 687b ldr r3, [r7, #4] 8013ed0: 6a5b ldr r3, [r3, #36] @ 0x24 8013ed2: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 8013ed4: 68fb ldr r3, [r7, #12] 8013ed6: 2200 movs r2, #0 8013ed8: 85da strh r2, [r3, #46] @ 0x2e huart->TxXferCount = 0x00U; 8013eda: 68fb ldr r3, [r7, #12] 8013edc: 2200 movs r2, #0 8013ede: 84da strh r2, [r3, #38] @ 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013ee0: 68f8 ldr r0, [r7, #12] 8013ee2: f7f7 ff19 bl 800bd18 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8013ee6: bf00 nop 8013ee8: 3710 adds r7, #16 8013eea: 46bd mov sp, r7 8013eec: bd80 pop {r7, pc} 08013eee : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 8013eee: b480 push {r7} 8013ef0: b085 sub sp, #20 8013ef2: af00 add r7, sp, #0 8013ef4: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8013ef6: 687b ldr r3, [r7, #4] 8013ef8: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8013efc: b2db uxtb r3, r3 8013efe: 2b21 cmp r3, #33 @ 0x21 8013f00: d13e bne.n 8013f80 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8013f02: 687b ldr r3, [r7, #4] 8013f04: 689b ldr r3, [r3, #8] 8013f06: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8013f0a: d114 bne.n 8013f36 8013f0c: 687b ldr r3, [r7, #4] 8013f0e: 691b ldr r3, [r3, #16] 8013f10: 2b00 cmp r3, #0 8013f12: d110 bne.n 8013f36 { tmp = (const uint16_t *) huart->pTxBuffPtr; 8013f14: 687b ldr r3, [r7, #4] 8013f16: 6a1b ldr r3, [r3, #32] 8013f18: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8013f1a: 68fb ldr r3, [r7, #12] 8013f1c: 881b ldrh r3, [r3, #0] 8013f1e: 461a mov r2, r3 8013f20: 687b ldr r3, [r7, #4] 8013f22: 681b ldr r3, [r3, #0] 8013f24: f3c2 0208 ubfx r2, r2, #0, #9 8013f28: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 8013f2a: 687b ldr r3, [r7, #4] 8013f2c: 6a1b ldr r3, [r3, #32] 8013f2e: 1c9a adds r2, r3, #2 8013f30: 687b ldr r3, [r7, #4] 8013f32: 621a str r2, [r3, #32] 8013f34: e008 b.n 8013f48 } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 8013f36: 687b ldr r3, [r7, #4] 8013f38: 6a1b ldr r3, [r3, #32] 8013f3a: 1c59 adds r1, r3, #1 8013f3c: 687a ldr r2, [r7, #4] 8013f3e: 6211 str r1, [r2, #32] 8013f40: 781a ldrb r2, [r3, #0] 8013f42: 687b ldr r3, [r7, #4] 8013f44: 681b ldr r3, [r3, #0] 8013f46: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 8013f48: 687b ldr r3, [r7, #4] 8013f4a: 8cdb ldrh r3, [r3, #38] @ 0x26 8013f4c: b29b uxth r3, r3 8013f4e: 3b01 subs r3, #1 8013f50: b29b uxth r3, r3 8013f52: 687a ldr r2, [r7, #4] 8013f54: 4619 mov r1, r3 8013f56: 84d1 strh r1, [r2, #38] @ 0x26 8013f58: 2b00 cmp r3, #0 8013f5a: d10f bne.n 8013f7c { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8013f5c: 687b ldr r3, [r7, #4] 8013f5e: 681b ldr r3, [r3, #0] 8013f60: 68da ldr r2, [r3, #12] 8013f62: 687b ldr r3, [r7, #4] 8013f64: 681b ldr r3, [r3, #0] 8013f66: f022 0280 bic.w r2, r2, #128 @ 0x80 8013f6a: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 8013f6c: 687b ldr r3, [r7, #4] 8013f6e: 681b ldr r3, [r3, #0] 8013f70: 68da ldr r2, [r3, #12] 8013f72: 687b ldr r3, [r7, #4] 8013f74: 681b ldr r3, [r3, #0] 8013f76: f042 0240 orr.w r2, r2, #64 @ 0x40 8013f7a: 60da str r2, [r3, #12] } return HAL_OK; 8013f7c: 2300 movs r3, #0 8013f7e: e000 b.n 8013f82 } else { return HAL_BUSY; 8013f80: 2302 movs r3, #2 } } 8013f82: 4618 mov r0, r3 8013f84: 3714 adds r7, #20 8013f86: 46bd mov sp, r7 8013f88: bc80 pop {r7} 8013f8a: 4770 bx lr 08013f8c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8013f8c: b580 push {r7, lr} 8013f8e: b082 sub sp, #8 8013f90: af00 add r7, sp, #0 8013f92: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 8013f94: 687b ldr r3, [r7, #4] 8013f96: 681b ldr r3, [r3, #0] 8013f98: 68da ldr r2, [r3, #12] 8013f9a: 687b ldr r3, [r7, #4] 8013f9c: 681b ldr r3, [r3, #0] 8013f9e: f022 0240 bic.w r2, r2, #64 @ 0x40 8013fa2: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8013fa4: 687b ldr r3, [r7, #4] 8013fa6: 2220 movs r2, #32 8013fa8: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8013fac: 6878 ldr r0, [r7, #4] 8013fae: f7f8 fe77 bl 800cca0 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8013fb2: 2300 movs r3, #0 } 8013fb4: 4618 mov r0, r3 8013fb6: 3708 adds r7, #8 8013fb8: 46bd mov sp, r7 8013fba: bd80 pop {r7, pc} 08013fbc : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 8013fbc: b580 push {r7, lr} 8013fbe: b08c sub sp, #48 @ 0x30 8013fc0: af00 add r7, sp, #0 8013fc2: 6078 str r0, [r7, #4] uint8_t *pdata8bits; uint16_t *pdata16bits; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8013fc4: 687b ldr r3, [r7, #4] 8013fc6: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8013fca: b2db uxtb r3, r3 8013fcc: 2b22 cmp r3, #34 @ 0x22 8013fce: f040 80ae bne.w 801412e { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8013fd2: 687b ldr r3, [r7, #4] 8013fd4: 689b ldr r3, [r3, #8] 8013fd6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8013fda: d117 bne.n 801400c 8013fdc: 687b ldr r3, [r7, #4] 8013fde: 691b ldr r3, [r3, #16] 8013fe0: 2b00 cmp r3, #0 8013fe2: d113 bne.n 801400c { pdata8bits = NULL; 8013fe4: 2300 movs r3, #0 8013fe6: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = (uint16_t *) huart->pRxBuffPtr; 8013fe8: 687b ldr r3, [r7, #4] 8013fea: 6a9b ldr r3, [r3, #40] @ 0x28 8013fec: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8013fee: 687b ldr r3, [r7, #4] 8013ff0: 681b ldr r3, [r3, #0] 8013ff2: 685b ldr r3, [r3, #4] 8013ff4: b29b uxth r3, r3 8013ff6: f3c3 0308 ubfx r3, r3, #0, #9 8013ffa: b29a uxth r2, r3 8013ffc: 6abb ldr r3, [r7, #40] @ 0x28 8013ffe: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8014000: 687b ldr r3, [r7, #4] 8014002: 6a9b ldr r3, [r3, #40] @ 0x28 8014004: 1c9a adds r2, r3, #2 8014006: 687b ldr r3, [r7, #4] 8014008: 629a str r2, [r3, #40] @ 0x28 801400a: e026 b.n 801405a } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 801400c: 687b ldr r3, [r7, #4] 801400e: 6a9b ldr r3, [r3, #40] @ 0x28 8014010: 62fb str r3, [r7, #44] @ 0x2c pdata16bits = NULL; 8014012: 2300 movs r3, #0 8014014: 62bb str r3, [r7, #40] @ 0x28 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 8014016: 687b ldr r3, [r7, #4] 8014018: 689b ldr r3, [r3, #8] 801401a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 801401e: d007 beq.n 8014030 8014020: 687b ldr r3, [r7, #4] 8014022: 689b ldr r3, [r3, #8] 8014024: 2b00 cmp r3, #0 8014026: d10a bne.n 801403e 8014028: 687b ldr r3, [r7, #4] 801402a: 691b ldr r3, [r3, #16] 801402c: 2b00 cmp r3, #0 801402e: d106 bne.n 801403e { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8014030: 687b ldr r3, [r7, #4] 8014032: 681b ldr r3, [r3, #0] 8014034: 685b ldr r3, [r3, #4] 8014036: b2da uxtb r2, r3 8014038: 6afb ldr r3, [r7, #44] @ 0x2c 801403a: 701a strb r2, [r3, #0] 801403c: e008 b.n 8014050 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 801403e: 687b ldr r3, [r7, #4] 8014040: 681b ldr r3, [r3, #0] 8014042: 685b ldr r3, [r3, #4] 8014044: b2db uxtb r3, r3 8014046: f003 037f and.w r3, r3, #127 @ 0x7f 801404a: b2da uxtb r2, r3 801404c: 6afb ldr r3, [r7, #44] @ 0x2c 801404e: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 8014050: 687b ldr r3, [r7, #4] 8014052: 6a9b ldr r3, [r3, #40] @ 0x28 8014054: 1c5a adds r2, r3, #1 8014056: 687b ldr r3, [r7, #4] 8014058: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 801405a: 687b ldr r3, [r7, #4] 801405c: 8ddb ldrh r3, [r3, #46] @ 0x2e 801405e: b29b uxth r3, r3 8014060: 3b01 subs r3, #1 8014062: b29b uxth r3, r3 8014064: 687a ldr r2, [r7, #4] 8014066: 4619 mov r1, r3 8014068: 85d1 strh r1, [r2, #46] @ 0x2e 801406a: 2b00 cmp r3, #0 801406c: d15d bne.n 801412a { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 801406e: 687b ldr r3, [r7, #4] 8014070: 681b ldr r3, [r3, #0] 8014072: 68da ldr r2, [r3, #12] 8014074: 687b ldr r3, [r7, #4] 8014076: 681b ldr r3, [r3, #0] 8014078: f022 0220 bic.w r2, r2, #32 801407c: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 801407e: 687b ldr r3, [r7, #4] 8014080: 681b ldr r3, [r3, #0] 8014082: 68da ldr r2, [r3, #12] 8014084: 687b ldr r3, [r7, #4] 8014086: 681b ldr r3, [r3, #0] 8014088: f422 7280 bic.w r2, r2, #256 @ 0x100 801408c: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 801408e: 687b ldr r3, [r7, #4] 8014090: 681b ldr r3, [r3, #0] 8014092: 695a ldr r2, [r3, #20] 8014094: 687b ldr r3, [r7, #4] 8014096: 681b ldr r3, [r3, #0] 8014098: f022 0201 bic.w r2, r2, #1 801409c: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 801409e: 687b ldr r3, [r7, #4] 80140a0: 2220 movs r2, #32 80140a2: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 80140a6: 687b ldr r3, [r7, #4] 80140a8: 2200 movs r2, #0 80140aa: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80140ac: 687b ldr r3, [r7, #4] 80140ae: 6b1b ldr r3, [r3, #48] @ 0x30 80140b0: 2b01 cmp r3, #1 80140b2: d135 bne.n 8014120 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80140b4: 687b ldr r3, [r7, #4] 80140b6: 2200 movs r2, #0 80140b8: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80140ba: 687b ldr r3, [r7, #4] 80140bc: 681b ldr r3, [r3, #0] 80140be: 330c adds r3, #12 80140c0: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80140c2: 697b ldr r3, [r7, #20] 80140c4: e853 3f00 ldrex r3, [r3] 80140c8: 613b str r3, [r7, #16] return(result); 80140ca: 693b ldr r3, [r7, #16] 80140cc: f023 0310 bic.w r3, r3, #16 80140d0: 627b str r3, [r7, #36] @ 0x24 80140d2: 687b ldr r3, [r7, #4] 80140d4: 681b ldr r3, [r3, #0] 80140d6: 330c adds r3, #12 80140d8: 6a7a ldr r2, [r7, #36] @ 0x24 80140da: 623a str r2, [r7, #32] 80140dc: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80140de: 69f9 ldr r1, [r7, #28] 80140e0: 6a3a ldr r2, [r7, #32] 80140e2: e841 2300 strex r3, r2, [r1] 80140e6: 61bb str r3, [r7, #24] return(result); 80140e8: 69bb ldr r3, [r7, #24] 80140ea: 2b00 cmp r3, #0 80140ec: d1e5 bne.n 80140ba /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 80140ee: 687b ldr r3, [r7, #4] 80140f0: 681b ldr r3, [r3, #0] 80140f2: 681b ldr r3, [r3, #0] 80140f4: f003 0310 and.w r3, r3, #16 80140f8: 2b10 cmp r3, #16 80140fa: d10a bne.n 8014112 { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 80140fc: 2300 movs r3, #0 80140fe: 60fb str r3, [r7, #12] 8014100: 687b ldr r3, [r7, #4] 8014102: 681b ldr r3, [r3, #0] 8014104: 681b ldr r3, [r3, #0] 8014106: 60fb str r3, [r7, #12] 8014108: 687b ldr r3, [r7, #4] 801410a: 681b ldr r3, [r3, #0] 801410c: 685b ldr r3, [r3, #4] 801410e: 60fb str r3, [r7, #12] 8014110: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8014112: 687b ldr r3, [r7, #4] 8014114: 8d9b ldrh r3, [r3, #44] @ 0x2c 8014116: 4619 mov r1, r3 8014118: 6878 ldr r0, [r7, #4] 801411a: f7f8 fd47 bl 800cbac 801411e: e002 b.n 8014126 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8014120: 6878 ldr r0, [r7, #4] 8014122: f7ff fbfe bl 8013922 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8014126: 2300 movs r3, #0 8014128: e002 b.n 8014130 } return HAL_OK; 801412a: 2300 movs r3, #0 801412c: e000 b.n 8014130 } else { return HAL_BUSY; 801412e: 2302 movs r3, #2 } } 8014130: 4618 mov r0, r3 8014132: 3730 adds r7, #48 @ 0x30 8014134: 46bd mov sp, r7 8014136: bd80 pop {r7, pc} 08014138 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8014138: b580 push {r7, lr} 801413a: b084 sub sp, #16 801413c: af00 add r7, sp, #0 801413e: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8014140: 687b ldr r3, [r7, #4] 8014142: 681b ldr r3, [r3, #0] 8014144: 691b ldr r3, [r3, #16] 8014146: f423 5140 bic.w r1, r3, #12288 @ 0x3000 801414a: 687b ldr r3, [r7, #4] 801414c: 68da ldr r2, [r3, #12] 801414e: 687b ldr r3, [r7, #4] 8014150: 681b ldr r3, [r3, #0] 8014152: 430a orrs r2, r1 8014154: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 8014156: 687b ldr r3, [r7, #4] 8014158: 689a ldr r2, [r3, #8] 801415a: 687b ldr r3, [r7, #4] 801415c: 691b ldr r3, [r3, #16] 801415e: 431a orrs r2, r3 8014160: 687b ldr r3, [r7, #4] 8014162: 695b ldr r3, [r3, #20] 8014164: 4313 orrs r3, r2 8014166: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 8014168: 687b ldr r3, [r7, #4] 801416a: 681b ldr r3, [r3, #0] 801416c: 68db ldr r3, [r3, #12] 801416e: f423 53b0 bic.w r3, r3, #5632 @ 0x1600 8014172: f023 030c bic.w r3, r3, #12 8014176: 687a ldr r2, [r7, #4] 8014178: 6812 ldr r2, [r2, #0] 801417a: 68b9 ldr r1, [r7, #8] 801417c: 430b orrs r3, r1 801417e: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8014180: 687b ldr r3, [r7, #4] 8014182: 681b ldr r3, [r3, #0] 8014184: 695b ldr r3, [r3, #20] 8014186: f423 7140 bic.w r1, r3, #768 @ 0x300 801418a: 687b ldr r3, [r7, #4] 801418c: 699a ldr r2, [r3, #24] 801418e: 687b ldr r3, [r7, #4] 8014190: 681b ldr r3, [r3, #0] 8014192: 430a orrs r2, r1 8014194: 615a str r2, [r3, #20] if(huart->Instance == USART1) 8014196: 687b ldr r3, [r7, #4] 8014198: 681b ldr r3, [r3, #0] 801419a: 4a2c ldr r2, [pc, #176] @ (801424c ) 801419c: 4293 cmp r3, r2 801419e: d103 bne.n 80141a8 { pclk = HAL_RCC_GetPCLK2Freq(); 80141a0: f7fd fa5c bl 801165c 80141a4: 60f8 str r0, [r7, #12] 80141a6: e002 b.n 80141ae } else { pclk = HAL_RCC_GetPCLK1Freq(); 80141a8: f7fd fa44 bl 8011634 80141ac: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 80141ae: 68fa ldr r2, [r7, #12] 80141b0: 4613 mov r3, r2 80141b2: 009b lsls r3, r3, #2 80141b4: 4413 add r3, r2 80141b6: 009a lsls r2, r3, #2 80141b8: 441a add r2, r3 80141ba: 687b ldr r3, [r7, #4] 80141bc: 685b ldr r3, [r3, #4] 80141be: 009b lsls r3, r3, #2 80141c0: fbb2 f3f3 udiv r3, r2, r3 80141c4: 4a22 ldr r2, [pc, #136] @ (8014250 ) 80141c6: fba2 2303 umull r2, r3, r2, r3 80141ca: 095b lsrs r3, r3, #5 80141cc: 0119 lsls r1, r3, #4 80141ce: 68fa ldr r2, [r7, #12] 80141d0: 4613 mov r3, r2 80141d2: 009b lsls r3, r3, #2 80141d4: 4413 add r3, r2 80141d6: 009a lsls r2, r3, #2 80141d8: 441a add r2, r3 80141da: 687b ldr r3, [r7, #4] 80141dc: 685b ldr r3, [r3, #4] 80141de: 009b lsls r3, r3, #2 80141e0: fbb2 f2f3 udiv r2, r2, r3 80141e4: 4b1a ldr r3, [pc, #104] @ (8014250 ) 80141e6: fba3 0302 umull r0, r3, r3, r2 80141ea: 095b lsrs r3, r3, #5 80141ec: 2064 movs r0, #100 @ 0x64 80141ee: fb00 f303 mul.w r3, r0, r3 80141f2: 1ad3 subs r3, r2, r3 80141f4: 011b lsls r3, r3, #4 80141f6: 3332 adds r3, #50 @ 0x32 80141f8: 4a15 ldr r2, [pc, #84] @ (8014250 ) 80141fa: fba2 2303 umull r2, r3, r2, r3 80141fe: 095b lsrs r3, r3, #5 8014200: f003 03f0 and.w r3, r3, #240 @ 0xf0 8014204: 4419 add r1, r3 8014206: 68fa ldr r2, [r7, #12] 8014208: 4613 mov r3, r2 801420a: 009b lsls r3, r3, #2 801420c: 4413 add r3, r2 801420e: 009a lsls r2, r3, #2 8014210: 441a add r2, r3 8014212: 687b ldr r3, [r7, #4] 8014214: 685b ldr r3, [r3, #4] 8014216: 009b lsls r3, r3, #2 8014218: fbb2 f2f3 udiv r2, r2, r3 801421c: 4b0c ldr r3, [pc, #48] @ (8014250 ) 801421e: fba3 0302 umull r0, r3, r3, r2 8014222: 095b lsrs r3, r3, #5 8014224: 2064 movs r0, #100 @ 0x64 8014226: fb00 f303 mul.w r3, r0, r3 801422a: 1ad3 subs r3, r2, r3 801422c: 011b lsls r3, r3, #4 801422e: 3332 adds r3, #50 @ 0x32 8014230: 4a07 ldr r2, [pc, #28] @ (8014250 ) 8014232: fba2 2303 umull r2, r3, r2, r3 8014236: 095b lsrs r3, r3, #5 8014238: f003 020f and.w r2, r3, #15 801423c: 687b ldr r3, [r7, #4] 801423e: 681b ldr r3, [r3, #0] 8014240: 440a add r2, r1 8014242: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 8014244: bf00 nop 8014246: 3710 adds r7, #16 8014248: 46bd mov sp, r7 801424a: bd80 pop {r7, pc} 801424c: 40013800 .word 0x40013800 8014250: 51eb851f .word 0x51eb851f 08014254 <__cvt>: 8014254: 2b00 cmp r3, #0 8014256: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 801425a: 461d mov r5, r3 801425c: bfbb ittet lt 801425e: f103 4300 addlt.w r3, r3, #2147483648 @ 0x80000000 8014262: 461d movlt r5, r3 8014264: 2300 movge r3, #0 8014266: 232d movlt r3, #45 @ 0x2d 8014268: b088 sub sp, #32 801426a: 4614 mov r4, r2 801426c: bfb8 it lt 801426e: 4614 movlt r4, r2 8014270: 9a12 ldr r2, [sp, #72] @ 0x48 8014272: 9e10 ldr r6, [sp, #64] @ 0x40 8014274: 7013 strb r3, [r2, #0] 8014276: 9b14 ldr r3, [sp, #80] @ 0x50 8014278: f8dd a04c ldr.w sl, [sp, #76] @ 0x4c 801427c: f023 0820 bic.w r8, r3, #32 8014280: f1b8 0f46 cmp.w r8, #70 @ 0x46 8014284: d005 beq.n 8014292 <__cvt+0x3e> 8014286: f1b8 0f45 cmp.w r8, #69 @ 0x45 801428a: d100 bne.n 801428e <__cvt+0x3a> 801428c: 3601 adds r6, #1 801428e: 2302 movs r3, #2 8014290: e000 b.n 8014294 <__cvt+0x40> 8014292: 2303 movs r3, #3 8014294: aa07 add r2, sp, #28 8014296: 9204 str r2, [sp, #16] 8014298: aa06 add r2, sp, #24 801429a: e9cd a202 strd sl, r2, [sp, #8] 801429e: e9cd 3600 strd r3, r6, [sp] 80142a2: 4622 mov r2, r4 80142a4: 462b mov r3, r5 80142a6: f000 fe2b bl 8014f00 <_dtoa_r> 80142aa: f1b8 0f47 cmp.w r8, #71 @ 0x47 80142ae: 4607 mov r7, r0 80142b0: d119 bne.n 80142e6 <__cvt+0x92> 80142b2: 9b11 ldr r3, [sp, #68] @ 0x44 80142b4: 07db lsls r3, r3, #31 80142b6: d50e bpl.n 80142d6 <__cvt+0x82> 80142b8: eb00 0906 add.w r9, r0, r6 80142bc: 2200 movs r2, #0 80142be: 2300 movs r3, #0 80142c0: 4620 mov r0, r4 80142c2: 4629 mov r1, r5 80142c4: f7f4 fbdc bl 8008a80 <__aeabi_dcmpeq> 80142c8: b108 cbz r0, 80142ce <__cvt+0x7a> 80142ca: f8cd 901c str.w r9, [sp, #28] 80142ce: 2230 movs r2, #48 @ 0x30 80142d0: 9b07 ldr r3, [sp, #28] 80142d2: 454b cmp r3, r9 80142d4: d31e bcc.n 8014314 <__cvt+0xc0> 80142d6: 4638 mov r0, r7 80142d8: 9b07 ldr r3, [sp, #28] 80142da: 9a15 ldr r2, [sp, #84] @ 0x54 80142dc: 1bdb subs r3, r3, r7 80142de: 6013 str r3, [r2, #0] 80142e0: b008 add sp, #32 80142e2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80142e6: f1b8 0f46 cmp.w r8, #70 @ 0x46 80142ea: eb00 0906 add.w r9, r0, r6 80142ee: d1e5 bne.n 80142bc <__cvt+0x68> 80142f0: 7803 ldrb r3, [r0, #0] 80142f2: 2b30 cmp r3, #48 @ 0x30 80142f4: d10a bne.n 801430c <__cvt+0xb8> 80142f6: 2200 movs r2, #0 80142f8: 2300 movs r3, #0 80142fa: 4620 mov r0, r4 80142fc: 4629 mov r1, r5 80142fe: f7f4 fbbf bl 8008a80 <__aeabi_dcmpeq> 8014302: b918 cbnz r0, 801430c <__cvt+0xb8> 8014304: f1c6 0601 rsb r6, r6, #1 8014308: f8ca 6000 str.w r6, [sl] 801430c: f8da 3000 ldr.w r3, [sl] 8014310: 4499 add r9, r3 8014312: e7d3 b.n 80142bc <__cvt+0x68> 8014314: 1c59 adds r1, r3, #1 8014316: 9107 str r1, [sp, #28] 8014318: 701a strb r2, [r3, #0] 801431a: e7d9 b.n 80142d0 <__cvt+0x7c> 0801431c <__exponent>: 801431c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 801431e: 2900 cmp r1, #0 8014320: bfb6 itet lt 8014322: 232d movlt r3, #45 @ 0x2d 8014324: 232b movge r3, #43 @ 0x2b 8014326: 4249 neglt r1, r1 8014328: 2909 cmp r1, #9 801432a: 7002 strb r2, [r0, #0] 801432c: 7043 strb r3, [r0, #1] 801432e: dd29 ble.n 8014384 <__exponent+0x68> 8014330: f10d 0307 add.w r3, sp, #7 8014334: 461d mov r5, r3 8014336: 270a movs r7, #10 8014338: fbb1 f6f7 udiv r6, r1, r7 801433c: 461a mov r2, r3 801433e: fb07 1416 mls r4, r7, r6, r1 8014342: 3430 adds r4, #48 @ 0x30 8014344: f802 4c01 strb.w r4, [r2, #-1] 8014348: 460c mov r4, r1 801434a: 2c63 cmp r4, #99 @ 0x63 801434c: 4631 mov r1, r6 801434e: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff 8014352: dcf1 bgt.n 8014338 <__exponent+0x1c> 8014354: 3130 adds r1, #48 @ 0x30 8014356: 1e94 subs r4, r2, #2 8014358: f803 1c01 strb.w r1, [r3, #-1] 801435c: 4623 mov r3, r4 801435e: 1c41 adds r1, r0, #1 8014360: 42ab cmp r3, r5 8014362: d30a bcc.n 801437a <__exponent+0x5e> 8014364: f10d 0309 add.w r3, sp, #9 8014368: 1a9b subs r3, r3, r2 801436a: 42ac cmp r4, r5 801436c: bf88 it hi 801436e: 2300 movhi r3, #0 8014370: 3302 adds r3, #2 8014372: 4403 add r3, r0 8014374: 1a18 subs r0, r3, r0 8014376: b003 add sp, #12 8014378: bdf0 pop {r4, r5, r6, r7, pc} 801437a: f813 6b01 ldrb.w r6, [r3], #1 801437e: f801 6f01 strb.w r6, [r1, #1]! 8014382: e7ed b.n 8014360 <__exponent+0x44> 8014384: 2330 movs r3, #48 @ 0x30 8014386: 3130 adds r1, #48 @ 0x30 8014388: 7083 strb r3, [r0, #2] 801438a: 70c1 strb r1, [r0, #3] 801438c: 1d03 adds r3, r0, #4 801438e: e7f1 b.n 8014374 <__exponent+0x58> 08014390 <_printf_float>: 8014390: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8014394: b091 sub sp, #68 @ 0x44 8014396: 460c mov r4, r1 8014398: f8dd 8068 ldr.w r8, [sp, #104] @ 0x68 801439c: 4616 mov r6, r2 801439e: 461f mov r7, r3 80143a0: 4605 mov r5, r0 80143a2: f000 fce5 bl 8014d70 <_localeconv_r> 80143a6: 6803 ldr r3, [r0, #0] 80143a8: 4618 mov r0, r3 80143aa: 9308 str r3, [sp, #32] 80143ac: f7f3 ff3c bl 8008228 80143b0: 2300 movs r3, #0 80143b2: 930e str r3, [sp, #56] @ 0x38 80143b4: f8d8 3000 ldr.w r3, [r8] 80143b8: 9009 str r0, [sp, #36] @ 0x24 80143ba: 3307 adds r3, #7 80143bc: f023 0307 bic.w r3, r3, #7 80143c0: f103 0208 add.w r2, r3, #8 80143c4: f894 a018 ldrb.w sl, [r4, #24] 80143c8: f8d4 b000 ldr.w fp, [r4] 80143cc: f8c8 2000 str.w r2, [r8] 80143d0: e9d3 8900 ldrd r8, r9, [r3] 80143d4: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000 80143d8: 930b str r3, [sp, #44] @ 0x2c 80143da: f8cd 8028 str.w r8, [sp, #40] @ 0x28 80143de: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80143e2: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 80143e6: e9c4 8912 strd r8, r9, [r4, #72] @ 0x48 80143ea: 4b9c ldr r3, [pc, #624] @ (801465c <_printf_float+0x2cc>) 80143ec: f7f4 fb7a bl 8008ae4 <__aeabi_dcmpun> 80143f0: bb70 cbnz r0, 8014450 <_printf_float+0xc0> 80143f2: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 80143f6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80143fa: 4b98 ldr r3, [pc, #608] @ (801465c <_printf_float+0x2cc>) 80143fc: f7f4 fb54 bl 8008aa8 <__aeabi_dcmple> 8014400: bb30 cbnz r0, 8014450 <_printf_float+0xc0> 8014402: 2200 movs r2, #0 8014404: 2300 movs r3, #0 8014406: 4640 mov r0, r8 8014408: 4649 mov r1, r9 801440a: f7f4 fb43 bl 8008a94 <__aeabi_dcmplt> 801440e: b110 cbz r0, 8014416 <_printf_float+0x86> 8014410: 232d movs r3, #45 @ 0x2d 8014412: f884 3043 strb.w r3, [r4, #67] @ 0x43 8014416: 4a92 ldr r2, [pc, #584] @ (8014660 <_printf_float+0x2d0>) 8014418: 4b92 ldr r3, [pc, #584] @ (8014664 <_printf_float+0x2d4>) 801441a: f1ba 0f47 cmp.w sl, #71 @ 0x47 801441e: bf8c ite hi 8014420: 4690 movhi r8, r2 8014422: 4698 movls r8, r3 8014424: 2303 movs r3, #3 8014426: f04f 0900 mov.w r9, #0 801442a: 6123 str r3, [r4, #16] 801442c: f02b 0304 bic.w r3, fp, #4 8014430: 6023 str r3, [r4, #0] 8014432: 4633 mov r3, r6 8014434: 4621 mov r1, r4 8014436: 4628 mov r0, r5 8014438: 9700 str r7, [sp, #0] 801443a: aa0f add r2, sp, #60 @ 0x3c 801443c: f000 f9d4 bl 80147e8 <_printf_common> 8014440: 3001 adds r0, #1 8014442: f040 8090 bne.w 8014566 <_printf_float+0x1d6> 8014446: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801444a: b011 add sp, #68 @ 0x44 801444c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8014450: 4642 mov r2, r8 8014452: 464b mov r3, r9 8014454: 4640 mov r0, r8 8014456: 4649 mov r1, r9 8014458: f7f4 fb44 bl 8008ae4 <__aeabi_dcmpun> 801445c: b148 cbz r0, 8014472 <_printf_float+0xe2> 801445e: 464b mov r3, r9 8014460: 2b00 cmp r3, #0 8014462: bfb8 it lt 8014464: 232d movlt r3, #45 @ 0x2d 8014466: 4a80 ldr r2, [pc, #512] @ (8014668 <_printf_float+0x2d8>) 8014468: bfb8 it lt 801446a: f884 3043 strblt.w r3, [r4, #67] @ 0x43 801446e: 4b7f ldr r3, [pc, #508] @ (801466c <_printf_float+0x2dc>) 8014470: e7d3 b.n 801441a <_printf_float+0x8a> 8014472: 6863 ldr r3, [r4, #4] 8014474: f00a 01df and.w r1, sl, #223 @ 0xdf 8014478: 1c5a adds r2, r3, #1 801447a: d13f bne.n 80144fc <_printf_float+0x16c> 801447c: 2306 movs r3, #6 801447e: 6063 str r3, [r4, #4] 8014480: 2200 movs r2, #0 8014482: f44b 6380 orr.w r3, fp, #1024 @ 0x400 8014486: 6023 str r3, [r4, #0] 8014488: 9206 str r2, [sp, #24] 801448a: aa0e add r2, sp, #56 @ 0x38 801448c: e9cd a204 strd sl, r2, [sp, #16] 8014490: aa0d add r2, sp, #52 @ 0x34 8014492: 9203 str r2, [sp, #12] 8014494: f10d 0233 add.w r2, sp, #51 @ 0x33 8014498: e9cd 3201 strd r3, r2, [sp, #4] 801449c: 6863 ldr r3, [r4, #4] 801449e: 4642 mov r2, r8 80144a0: 9300 str r3, [sp, #0] 80144a2: 4628 mov r0, r5 80144a4: 464b mov r3, r9 80144a6: 910a str r1, [sp, #40] @ 0x28 80144a8: f7ff fed4 bl 8014254 <__cvt> 80144ac: 990a ldr r1, [sp, #40] @ 0x28 80144ae: 4680 mov r8, r0 80144b0: 2947 cmp r1, #71 @ 0x47 80144b2: 990d ldr r1, [sp, #52] @ 0x34 80144b4: d128 bne.n 8014508 <_printf_float+0x178> 80144b6: 1cc8 adds r0, r1, #3 80144b8: db02 blt.n 80144c0 <_printf_float+0x130> 80144ba: 6863 ldr r3, [r4, #4] 80144bc: 4299 cmp r1, r3 80144be: dd40 ble.n 8014542 <_printf_float+0x1b2> 80144c0: f1aa 0a02 sub.w sl, sl, #2 80144c4: fa5f fa8a uxtb.w sl, sl 80144c8: 4652 mov r2, sl 80144ca: 3901 subs r1, #1 80144cc: f104 0050 add.w r0, r4, #80 @ 0x50 80144d0: 910d str r1, [sp, #52] @ 0x34 80144d2: f7ff ff23 bl 801431c <__exponent> 80144d6: 9a0e ldr r2, [sp, #56] @ 0x38 80144d8: 4681 mov r9, r0 80144da: 1813 adds r3, r2, r0 80144dc: 2a01 cmp r2, #1 80144de: 6123 str r3, [r4, #16] 80144e0: dc02 bgt.n 80144e8 <_printf_float+0x158> 80144e2: 6822 ldr r2, [r4, #0] 80144e4: 07d2 lsls r2, r2, #31 80144e6: d501 bpl.n 80144ec <_printf_float+0x15c> 80144e8: 3301 adds r3, #1 80144ea: 6123 str r3, [r4, #16] 80144ec: f89d 3033 ldrb.w r3, [sp, #51] @ 0x33 80144f0: 2b00 cmp r3, #0 80144f2: d09e beq.n 8014432 <_printf_float+0xa2> 80144f4: 232d movs r3, #45 @ 0x2d 80144f6: f884 3043 strb.w r3, [r4, #67] @ 0x43 80144fa: e79a b.n 8014432 <_printf_float+0xa2> 80144fc: 2947 cmp r1, #71 @ 0x47 80144fe: d1bf bne.n 8014480 <_printf_float+0xf0> 8014500: 2b00 cmp r3, #0 8014502: d1bd bne.n 8014480 <_printf_float+0xf0> 8014504: 2301 movs r3, #1 8014506: e7ba b.n 801447e <_printf_float+0xee> 8014508: f1ba 0f65 cmp.w sl, #101 @ 0x65 801450c: d9dc bls.n 80144c8 <_printf_float+0x138> 801450e: f1ba 0f66 cmp.w sl, #102 @ 0x66 8014512: d118 bne.n 8014546 <_printf_float+0x1b6> 8014514: 2900 cmp r1, #0 8014516: 6863 ldr r3, [r4, #4] 8014518: dd0b ble.n 8014532 <_printf_float+0x1a2> 801451a: 6121 str r1, [r4, #16] 801451c: b913 cbnz r3, 8014524 <_printf_float+0x194> 801451e: 6822 ldr r2, [r4, #0] 8014520: 07d0 lsls r0, r2, #31 8014522: d502 bpl.n 801452a <_printf_float+0x19a> 8014524: 3301 adds r3, #1 8014526: 440b add r3, r1 8014528: 6123 str r3, [r4, #16] 801452a: f04f 0900 mov.w r9, #0 801452e: 65a1 str r1, [r4, #88] @ 0x58 8014530: e7dc b.n 80144ec <_printf_float+0x15c> 8014532: b913 cbnz r3, 801453a <_printf_float+0x1aa> 8014534: 6822 ldr r2, [r4, #0] 8014536: 07d2 lsls r2, r2, #31 8014538: d501 bpl.n 801453e <_printf_float+0x1ae> 801453a: 3302 adds r3, #2 801453c: e7f4 b.n 8014528 <_printf_float+0x198> 801453e: 2301 movs r3, #1 8014540: e7f2 b.n 8014528 <_printf_float+0x198> 8014542: f04f 0a67 mov.w sl, #103 @ 0x67 8014546: 9b0e ldr r3, [sp, #56] @ 0x38 8014548: 4299 cmp r1, r3 801454a: db05 blt.n 8014558 <_printf_float+0x1c8> 801454c: 6823 ldr r3, [r4, #0] 801454e: 6121 str r1, [r4, #16] 8014550: 07d8 lsls r0, r3, #31 8014552: d5ea bpl.n 801452a <_printf_float+0x19a> 8014554: 1c4b adds r3, r1, #1 8014556: e7e7 b.n 8014528 <_printf_float+0x198> 8014558: 2900 cmp r1, #0 801455a: bfcc ite gt 801455c: 2201 movgt r2, #1 801455e: f1c1 0202 rsble r2, r1, #2 8014562: 4413 add r3, r2 8014564: e7e0 b.n 8014528 <_printf_float+0x198> 8014566: 6823 ldr r3, [r4, #0] 8014568: 055a lsls r2, r3, #21 801456a: d407 bmi.n 801457c <_printf_float+0x1ec> 801456c: 6923 ldr r3, [r4, #16] 801456e: 4642 mov r2, r8 8014570: 4631 mov r1, r6 8014572: 4628 mov r0, r5 8014574: 47b8 blx r7 8014576: 3001 adds r0, #1 8014578: d12b bne.n 80145d2 <_printf_float+0x242> 801457a: e764 b.n 8014446 <_printf_float+0xb6> 801457c: f1ba 0f65 cmp.w sl, #101 @ 0x65 8014580: f240 80dc bls.w 801473c <_printf_float+0x3ac> 8014584: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 8014588: 2200 movs r2, #0 801458a: 2300 movs r3, #0 801458c: f7f4 fa78 bl 8008a80 <__aeabi_dcmpeq> 8014590: 2800 cmp r0, #0 8014592: d033 beq.n 80145fc <_printf_float+0x26c> 8014594: 2301 movs r3, #1 8014596: 4631 mov r1, r6 8014598: 4628 mov r0, r5 801459a: 4a35 ldr r2, [pc, #212] @ (8014670 <_printf_float+0x2e0>) 801459c: 47b8 blx r7 801459e: 3001 adds r0, #1 80145a0: f43f af51 beq.w 8014446 <_printf_float+0xb6> 80145a4: e9dd 380d ldrd r3, r8, [sp, #52] @ 0x34 80145a8: 4543 cmp r3, r8 80145aa: db02 blt.n 80145b2 <_printf_float+0x222> 80145ac: 6823 ldr r3, [r4, #0] 80145ae: 07d8 lsls r0, r3, #31 80145b0: d50f bpl.n 80145d2 <_printf_float+0x242> 80145b2: e9dd 2308 ldrd r2, r3, [sp, #32] 80145b6: 4631 mov r1, r6 80145b8: 4628 mov r0, r5 80145ba: 47b8 blx r7 80145bc: 3001 adds r0, #1 80145be: f43f af42 beq.w 8014446 <_printf_float+0xb6> 80145c2: f04f 0900 mov.w r9, #0 80145c6: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 80145ca: f104 0a1a add.w sl, r4, #26 80145ce: 45c8 cmp r8, r9 80145d0: dc09 bgt.n 80145e6 <_printf_float+0x256> 80145d2: 6823 ldr r3, [r4, #0] 80145d4: 079b lsls r3, r3, #30 80145d6: f100 8102 bmi.w 80147de <_printf_float+0x44e> 80145da: 68e0 ldr r0, [r4, #12] 80145dc: 9b0f ldr r3, [sp, #60] @ 0x3c 80145de: 4298 cmp r0, r3 80145e0: bfb8 it lt 80145e2: 4618 movlt r0, r3 80145e4: e731 b.n 801444a <_printf_float+0xba> 80145e6: 2301 movs r3, #1 80145e8: 4652 mov r2, sl 80145ea: 4631 mov r1, r6 80145ec: 4628 mov r0, r5 80145ee: 47b8 blx r7 80145f0: 3001 adds r0, #1 80145f2: f43f af28 beq.w 8014446 <_printf_float+0xb6> 80145f6: f109 0901 add.w r9, r9, #1 80145fa: e7e8 b.n 80145ce <_printf_float+0x23e> 80145fc: 9b0d ldr r3, [sp, #52] @ 0x34 80145fe: 2b00 cmp r3, #0 8014600: dc38 bgt.n 8014674 <_printf_float+0x2e4> 8014602: 2301 movs r3, #1 8014604: 4631 mov r1, r6 8014606: 4628 mov r0, r5 8014608: 4a19 ldr r2, [pc, #100] @ (8014670 <_printf_float+0x2e0>) 801460a: 47b8 blx r7 801460c: 3001 adds r0, #1 801460e: f43f af1a beq.w 8014446 <_printf_float+0xb6> 8014612: e9dd 390d ldrd r3, r9, [sp, #52] @ 0x34 8014616: ea59 0303 orrs.w r3, r9, r3 801461a: d102 bne.n 8014622 <_printf_float+0x292> 801461c: 6823 ldr r3, [r4, #0] 801461e: 07d9 lsls r1, r3, #31 8014620: d5d7 bpl.n 80145d2 <_printf_float+0x242> 8014622: e9dd 2308 ldrd r2, r3, [sp, #32] 8014626: 4631 mov r1, r6 8014628: 4628 mov r0, r5 801462a: 47b8 blx r7 801462c: 3001 adds r0, #1 801462e: f43f af0a beq.w 8014446 <_printf_float+0xb6> 8014632: f04f 0a00 mov.w sl, #0 8014636: f104 0b1a add.w fp, r4, #26 801463a: 9b0d ldr r3, [sp, #52] @ 0x34 801463c: 425b negs r3, r3 801463e: 4553 cmp r3, sl 8014640: dc01 bgt.n 8014646 <_printf_float+0x2b6> 8014642: 464b mov r3, r9 8014644: e793 b.n 801456e <_printf_float+0x1de> 8014646: 2301 movs r3, #1 8014648: 465a mov r2, fp 801464a: 4631 mov r1, r6 801464c: 4628 mov r0, r5 801464e: 47b8 blx r7 8014650: 3001 adds r0, #1 8014652: f43f aef8 beq.w 8014446 <_printf_float+0xb6> 8014656: f10a 0a01 add.w sl, sl, #1 801465a: e7ee b.n 801463a <_printf_float+0x2aa> 801465c: 7fefffff .word 0x7fefffff 8014660: 080179c8 .word 0x080179c8 8014664: 080179c4 .word 0x080179c4 8014668: 080179d0 .word 0x080179d0 801466c: 080179cc .word 0x080179cc 8014670: 080179d4 .word 0x080179d4 8014674: 6da3 ldr r3, [r4, #88] @ 0x58 8014676: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 801467a: 4553 cmp r3, sl 801467c: bfa8 it ge 801467e: 4653 movge r3, sl 8014680: 2b00 cmp r3, #0 8014682: 4699 mov r9, r3 8014684: dc36 bgt.n 80146f4 <_printf_float+0x364> 8014686: f04f 0b00 mov.w fp, #0 801468a: ea29 79e9 bic.w r9, r9, r9, asr #31 801468e: f104 021a add.w r2, r4, #26 8014692: 6da3 ldr r3, [r4, #88] @ 0x58 8014694: 930a str r3, [sp, #40] @ 0x28 8014696: eba3 0309 sub.w r3, r3, r9 801469a: 455b cmp r3, fp 801469c: dc31 bgt.n 8014702 <_printf_float+0x372> 801469e: 9b0d ldr r3, [sp, #52] @ 0x34 80146a0: 459a cmp sl, r3 80146a2: dc3a bgt.n 801471a <_printf_float+0x38a> 80146a4: 6823 ldr r3, [r4, #0] 80146a6: 07da lsls r2, r3, #31 80146a8: d437 bmi.n 801471a <_printf_float+0x38a> 80146aa: 9b0d ldr r3, [sp, #52] @ 0x34 80146ac: ebaa 0903 sub.w r9, sl, r3 80146b0: 9b0a ldr r3, [sp, #40] @ 0x28 80146b2: ebaa 0303 sub.w r3, sl, r3 80146b6: 4599 cmp r9, r3 80146b8: bfa8 it ge 80146ba: 4699 movge r9, r3 80146bc: f1b9 0f00 cmp.w r9, #0 80146c0: dc33 bgt.n 801472a <_printf_float+0x39a> 80146c2: f04f 0800 mov.w r8, #0 80146c6: ea29 79e9 bic.w r9, r9, r9, asr #31 80146ca: f104 0b1a add.w fp, r4, #26 80146ce: 9b0d ldr r3, [sp, #52] @ 0x34 80146d0: ebaa 0303 sub.w r3, sl, r3 80146d4: eba3 0309 sub.w r3, r3, r9 80146d8: 4543 cmp r3, r8 80146da: f77f af7a ble.w 80145d2 <_printf_float+0x242> 80146de: 2301 movs r3, #1 80146e0: 465a mov r2, fp 80146e2: 4631 mov r1, r6 80146e4: 4628 mov r0, r5 80146e6: 47b8 blx r7 80146e8: 3001 adds r0, #1 80146ea: f43f aeac beq.w 8014446 <_printf_float+0xb6> 80146ee: f108 0801 add.w r8, r8, #1 80146f2: e7ec b.n 80146ce <_printf_float+0x33e> 80146f4: 4642 mov r2, r8 80146f6: 4631 mov r1, r6 80146f8: 4628 mov r0, r5 80146fa: 47b8 blx r7 80146fc: 3001 adds r0, #1 80146fe: d1c2 bne.n 8014686 <_printf_float+0x2f6> 8014700: e6a1 b.n 8014446 <_printf_float+0xb6> 8014702: 2301 movs r3, #1 8014704: 4631 mov r1, r6 8014706: 4628 mov r0, r5 8014708: 920a str r2, [sp, #40] @ 0x28 801470a: 47b8 blx r7 801470c: 3001 adds r0, #1 801470e: f43f ae9a beq.w 8014446 <_printf_float+0xb6> 8014712: 9a0a ldr r2, [sp, #40] @ 0x28 8014714: f10b 0b01 add.w fp, fp, #1 8014718: e7bb b.n 8014692 <_printf_float+0x302> 801471a: 4631 mov r1, r6 801471c: e9dd 2308 ldrd r2, r3, [sp, #32] 8014720: 4628 mov r0, r5 8014722: 47b8 blx r7 8014724: 3001 adds r0, #1 8014726: d1c0 bne.n 80146aa <_printf_float+0x31a> 8014728: e68d b.n 8014446 <_printf_float+0xb6> 801472a: 9a0a ldr r2, [sp, #40] @ 0x28 801472c: 464b mov r3, r9 801472e: 4631 mov r1, r6 8014730: 4628 mov r0, r5 8014732: 4442 add r2, r8 8014734: 47b8 blx r7 8014736: 3001 adds r0, #1 8014738: d1c3 bne.n 80146c2 <_printf_float+0x332> 801473a: e684 b.n 8014446 <_printf_float+0xb6> 801473c: f8dd a038 ldr.w sl, [sp, #56] @ 0x38 8014740: f1ba 0f01 cmp.w sl, #1 8014744: dc01 bgt.n 801474a <_printf_float+0x3ba> 8014746: 07db lsls r3, r3, #31 8014748: d536 bpl.n 80147b8 <_printf_float+0x428> 801474a: 2301 movs r3, #1 801474c: 4642 mov r2, r8 801474e: 4631 mov r1, r6 8014750: 4628 mov r0, r5 8014752: 47b8 blx r7 8014754: 3001 adds r0, #1 8014756: f43f ae76 beq.w 8014446 <_printf_float+0xb6> 801475a: e9dd 2308 ldrd r2, r3, [sp, #32] 801475e: 4631 mov r1, r6 8014760: 4628 mov r0, r5 8014762: 47b8 blx r7 8014764: 3001 adds r0, #1 8014766: f43f ae6e beq.w 8014446 <_printf_float+0xb6> 801476a: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 801476e: 2200 movs r2, #0 8014770: 2300 movs r3, #0 8014772: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff 8014776: f7f4 f983 bl 8008a80 <__aeabi_dcmpeq> 801477a: b9c0 cbnz r0, 80147ae <_printf_float+0x41e> 801477c: 4653 mov r3, sl 801477e: f108 0201 add.w r2, r8, #1 8014782: 4631 mov r1, r6 8014784: 4628 mov r0, r5 8014786: 47b8 blx r7 8014788: 3001 adds r0, #1 801478a: d10c bne.n 80147a6 <_printf_float+0x416> 801478c: e65b b.n 8014446 <_printf_float+0xb6> 801478e: 2301 movs r3, #1 8014790: 465a mov r2, fp 8014792: 4631 mov r1, r6 8014794: 4628 mov r0, r5 8014796: 47b8 blx r7 8014798: 3001 adds r0, #1 801479a: f43f ae54 beq.w 8014446 <_printf_float+0xb6> 801479e: f108 0801 add.w r8, r8, #1 80147a2: 45d0 cmp r8, sl 80147a4: dbf3 blt.n 801478e <_printf_float+0x3fe> 80147a6: 464b mov r3, r9 80147a8: f104 0250 add.w r2, r4, #80 @ 0x50 80147ac: e6e0 b.n 8014570 <_printf_float+0x1e0> 80147ae: f04f 0800 mov.w r8, #0 80147b2: f104 0b1a add.w fp, r4, #26 80147b6: e7f4 b.n 80147a2 <_printf_float+0x412> 80147b8: 2301 movs r3, #1 80147ba: 4642 mov r2, r8 80147bc: e7e1 b.n 8014782 <_printf_float+0x3f2> 80147be: 2301 movs r3, #1 80147c0: 464a mov r2, r9 80147c2: 4631 mov r1, r6 80147c4: 4628 mov r0, r5 80147c6: 47b8 blx r7 80147c8: 3001 adds r0, #1 80147ca: f43f ae3c beq.w 8014446 <_printf_float+0xb6> 80147ce: f108 0801 add.w r8, r8, #1 80147d2: 68e3 ldr r3, [r4, #12] 80147d4: 990f ldr r1, [sp, #60] @ 0x3c 80147d6: 1a5b subs r3, r3, r1 80147d8: 4543 cmp r3, r8 80147da: dcf0 bgt.n 80147be <_printf_float+0x42e> 80147dc: e6fd b.n 80145da <_printf_float+0x24a> 80147de: f04f 0800 mov.w r8, #0 80147e2: f104 0919 add.w r9, r4, #25 80147e6: e7f4 b.n 80147d2 <_printf_float+0x442> 080147e8 <_printf_common>: 80147e8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80147ec: 4616 mov r6, r2 80147ee: 4698 mov r8, r3 80147f0: 688a ldr r2, [r1, #8] 80147f2: 690b ldr r3, [r1, #16] 80147f4: 4607 mov r7, r0 80147f6: 4293 cmp r3, r2 80147f8: bfb8 it lt 80147fa: 4613 movlt r3, r2 80147fc: 6033 str r3, [r6, #0] 80147fe: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 8014802: 460c mov r4, r1 8014804: f8dd 9020 ldr.w r9, [sp, #32] 8014808: b10a cbz r2, 801480e <_printf_common+0x26> 801480a: 3301 adds r3, #1 801480c: 6033 str r3, [r6, #0] 801480e: 6823 ldr r3, [r4, #0] 8014810: 0699 lsls r1, r3, #26 8014812: bf42 ittt mi 8014814: 6833 ldrmi r3, [r6, #0] 8014816: 3302 addmi r3, #2 8014818: 6033 strmi r3, [r6, #0] 801481a: 6825 ldr r5, [r4, #0] 801481c: f015 0506 ands.w r5, r5, #6 8014820: d106 bne.n 8014830 <_printf_common+0x48> 8014822: f104 0a19 add.w sl, r4, #25 8014826: 68e3 ldr r3, [r4, #12] 8014828: 6832 ldr r2, [r6, #0] 801482a: 1a9b subs r3, r3, r2 801482c: 42ab cmp r3, r5 801482e: dc2b bgt.n 8014888 <_printf_common+0xa0> 8014830: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 8014834: 6822 ldr r2, [r4, #0] 8014836: 3b00 subs r3, #0 8014838: bf18 it ne 801483a: 2301 movne r3, #1 801483c: 0692 lsls r2, r2, #26 801483e: d430 bmi.n 80148a2 <_printf_common+0xba> 8014840: 4641 mov r1, r8 8014842: 4638 mov r0, r7 8014844: f104 0243 add.w r2, r4, #67 @ 0x43 8014848: 47c8 blx r9 801484a: 3001 adds r0, #1 801484c: d023 beq.n 8014896 <_printf_common+0xae> 801484e: 6823 ldr r3, [r4, #0] 8014850: 6922 ldr r2, [r4, #16] 8014852: f003 0306 and.w r3, r3, #6 8014856: 2b04 cmp r3, #4 8014858: bf14 ite ne 801485a: 2500 movne r5, #0 801485c: 6833 ldreq r3, [r6, #0] 801485e: f04f 0600 mov.w r6, #0 8014862: bf08 it eq 8014864: 68e5 ldreq r5, [r4, #12] 8014866: f104 041a add.w r4, r4, #26 801486a: bf08 it eq 801486c: 1aed subeq r5, r5, r3 801486e: f854 3c12 ldr.w r3, [r4, #-18] 8014872: bf08 it eq 8014874: ea25 75e5 biceq.w r5, r5, r5, asr #31 8014878: 4293 cmp r3, r2 801487a: bfc4 itt gt 801487c: 1a9b subgt r3, r3, r2 801487e: 18ed addgt r5, r5, r3 8014880: 42b5 cmp r5, r6 8014882: d11a bne.n 80148ba <_printf_common+0xd2> 8014884: 2000 movs r0, #0 8014886: e008 b.n 801489a <_printf_common+0xb2> 8014888: 2301 movs r3, #1 801488a: 4652 mov r2, sl 801488c: 4641 mov r1, r8 801488e: 4638 mov r0, r7 8014890: 47c8 blx r9 8014892: 3001 adds r0, #1 8014894: d103 bne.n 801489e <_printf_common+0xb6> 8014896: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801489a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801489e: 3501 adds r5, #1 80148a0: e7c1 b.n 8014826 <_printf_common+0x3e> 80148a2: 2030 movs r0, #48 @ 0x30 80148a4: 18e1 adds r1, r4, r3 80148a6: f881 0043 strb.w r0, [r1, #67] @ 0x43 80148aa: 1c5a adds r2, r3, #1 80148ac: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 80148b0: 4422 add r2, r4 80148b2: 3302 adds r3, #2 80148b4: f882 1043 strb.w r1, [r2, #67] @ 0x43 80148b8: e7c2 b.n 8014840 <_printf_common+0x58> 80148ba: 2301 movs r3, #1 80148bc: 4622 mov r2, r4 80148be: 4641 mov r1, r8 80148c0: 4638 mov r0, r7 80148c2: 47c8 blx r9 80148c4: 3001 adds r0, #1 80148c6: d0e6 beq.n 8014896 <_printf_common+0xae> 80148c8: 3601 adds r6, #1 80148ca: e7d9 b.n 8014880 <_printf_common+0x98> 080148cc <_printf_i>: 80148cc: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 80148d0: 7e0f ldrb r7, [r1, #24] 80148d2: 4691 mov r9, r2 80148d4: 2f78 cmp r7, #120 @ 0x78 80148d6: 4680 mov r8, r0 80148d8: 460c mov r4, r1 80148da: 469a mov sl, r3 80148dc: 9e0c ldr r6, [sp, #48] @ 0x30 80148de: f101 0243 add.w r2, r1, #67 @ 0x43 80148e2: d807 bhi.n 80148f4 <_printf_i+0x28> 80148e4: 2f62 cmp r7, #98 @ 0x62 80148e6: d80a bhi.n 80148fe <_printf_i+0x32> 80148e8: 2f00 cmp r7, #0 80148ea: f000 80d1 beq.w 8014a90 <_printf_i+0x1c4> 80148ee: 2f58 cmp r7, #88 @ 0x58 80148f0: f000 80b8 beq.w 8014a64 <_printf_i+0x198> 80148f4: f104 0642 add.w r6, r4, #66 @ 0x42 80148f8: f884 7042 strb.w r7, [r4, #66] @ 0x42 80148fc: e03a b.n 8014974 <_printf_i+0xa8> 80148fe: f1a7 0363 sub.w r3, r7, #99 @ 0x63 8014902: 2b15 cmp r3, #21 8014904: d8f6 bhi.n 80148f4 <_printf_i+0x28> 8014906: a101 add r1, pc, #4 @ (adr r1, 801490c <_printf_i+0x40>) 8014908: f851 f023 ldr.w pc, [r1, r3, lsl #2] 801490c: 08014965 .word 0x08014965 8014910: 08014979 .word 0x08014979 8014914: 080148f5 .word 0x080148f5 8014918: 080148f5 .word 0x080148f5 801491c: 080148f5 .word 0x080148f5 8014920: 080148f5 .word 0x080148f5 8014924: 08014979 .word 0x08014979 8014928: 080148f5 .word 0x080148f5 801492c: 080148f5 .word 0x080148f5 8014930: 080148f5 .word 0x080148f5 8014934: 080148f5 .word 0x080148f5 8014938: 08014a77 .word 0x08014a77 801493c: 080149a3 .word 0x080149a3 8014940: 08014a31 .word 0x08014a31 8014944: 080148f5 .word 0x080148f5 8014948: 080148f5 .word 0x080148f5 801494c: 08014a99 .word 0x08014a99 8014950: 080148f5 .word 0x080148f5 8014954: 080149a3 .word 0x080149a3 8014958: 080148f5 .word 0x080148f5 801495c: 080148f5 .word 0x080148f5 8014960: 08014a39 .word 0x08014a39 8014964: 6833 ldr r3, [r6, #0] 8014966: 1d1a adds r2, r3, #4 8014968: 681b ldr r3, [r3, #0] 801496a: 6032 str r2, [r6, #0] 801496c: f104 0642 add.w r6, r4, #66 @ 0x42 8014970: f884 3042 strb.w r3, [r4, #66] @ 0x42 8014974: 2301 movs r3, #1 8014976: e09c b.n 8014ab2 <_printf_i+0x1e6> 8014978: 6833 ldr r3, [r6, #0] 801497a: 6820 ldr r0, [r4, #0] 801497c: 1d19 adds r1, r3, #4 801497e: 6031 str r1, [r6, #0] 8014980: 0606 lsls r6, r0, #24 8014982: d501 bpl.n 8014988 <_printf_i+0xbc> 8014984: 681d ldr r5, [r3, #0] 8014986: e003 b.n 8014990 <_printf_i+0xc4> 8014988: 0645 lsls r5, r0, #25 801498a: d5fb bpl.n 8014984 <_printf_i+0xb8> 801498c: f9b3 5000 ldrsh.w r5, [r3] 8014990: 2d00 cmp r5, #0 8014992: da03 bge.n 801499c <_printf_i+0xd0> 8014994: 232d movs r3, #45 @ 0x2d 8014996: 426d negs r5, r5 8014998: f884 3043 strb.w r3, [r4, #67] @ 0x43 801499c: 230a movs r3, #10 801499e: 4858 ldr r0, [pc, #352] @ (8014b00 <_printf_i+0x234>) 80149a0: e011 b.n 80149c6 <_printf_i+0xfa> 80149a2: 6821 ldr r1, [r4, #0] 80149a4: 6833 ldr r3, [r6, #0] 80149a6: 0608 lsls r0, r1, #24 80149a8: f853 5b04 ldr.w r5, [r3], #4 80149ac: d402 bmi.n 80149b4 <_printf_i+0xe8> 80149ae: 0649 lsls r1, r1, #25 80149b0: bf48 it mi 80149b2: b2ad uxthmi r5, r5 80149b4: 2f6f cmp r7, #111 @ 0x6f 80149b6: 6033 str r3, [r6, #0] 80149b8: bf14 ite ne 80149ba: 230a movne r3, #10 80149bc: 2308 moveq r3, #8 80149be: 4850 ldr r0, [pc, #320] @ (8014b00 <_printf_i+0x234>) 80149c0: 2100 movs r1, #0 80149c2: f884 1043 strb.w r1, [r4, #67] @ 0x43 80149c6: 6866 ldr r6, [r4, #4] 80149c8: 2e00 cmp r6, #0 80149ca: 60a6 str r6, [r4, #8] 80149cc: db05 blt.n 80149da <_printf_i+0x10e> 80149ce: 6821 ldr r1, [r4, #0] 80149d0: 432e orrs r6, r5 80149d2: f021 0104 bic.w r1, r1, #4 80149d6: 6021 str r1, [r4, #0] 80149d8: d04b beq.n 8014a72 <_printf_i+0x1a6> 80149da: 4616 mov r6, r2 80149dc: fbb5 f1f3 udiv r1, r5, r3 80149e0: fb03 5711 mls r7, r3, r1, r5 80149e4: 5dc7 ldrb r7, [r0, r7] 80149e6: f806 7d01 strb.w r7, [r6, #-1]! 80149ea: 462f mov r7, r5 80149ec: 42bb cmp r3, r7 80149ee: 460d mov r5, r1 80149f0: d9f4 bls.n 80149dc <_printf_i+0x110> 80149f2: 2b08 cmp r3, #8 80149f4: d10b bne.n 8014a0e <_printf_i+0x142> 80149f6: 6823 ldr r3, [r4, #0] 80149f8: 07df lsls r7, r3, #31 80149fa: d508 bpl.n 8014a0e <_printf_i+0x142> 80149fc: 6923 ldr r3, [r4, #16] 80149fe: 6861 ldr r1, [r4, #4] 8014a00: 4299 cmp r1, r3 8014a02: bfde ittt le 8014a04: 2330 movle r3, #48 @ 0x30 8014a06: f806 3c01 strble.w r3, [r6, #-1] 8014a0a: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff 8014a0e: 1b92 subs r2, r2, r6 8014a10: 6122 str r2, [r4, #16] 8014a12: 464b mov r3, r9 8014a14: 4621 mov r1, r4 8014a16: 4640 mov r0, r8 8014a18: f8cd a000 str.w sl, [sp] 8014a1c: aa03 add r2, sp, #12 8014a1e: f7ff fee3 bl 80147e8 <_printf_common> 8014a22: 3001 adds r0, #1 8014a24: d14a bne.n 8014abc <_printf_i+0x1f0> 8014a26: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8014a2a: b004 add sp, #16 8014a2c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8014a30: 6823 ldr r3, [r4, #0] 8014a32: f043 0320 orr.w r3, r3, #32 8014a36: 6023 str r3, [r4, #0] 8014a38: 2778 movs r7, #120 @ 0x78 8014a3a: 4832 ldr r0, [pc, #200] @ (8014b04 <_printf_i+0x238>) 8014a3c: f884 7045 strb.w r7, [r4, #69] @ 0x45 8014a40: 6823 ldr r3, [r4, #0] 8014a42: 6831 ldr r1, [r6, #0] 8014a44: 061f lsls r7, r3, #24 8014a46: f851 5b04 ldr.w r5, [r1], #4 8014a4a: d402 bmi.n 8014a52 <_printf_i+0x186> 8014a4c: 065f lsls r7, r3, #25 8014a4e: bf48 it mi 8014a50: b2ad uxthmi r5, r5 8014a52: 6031 str r1, [r6, #0] 8014a54: 07d9 lsls r1, r3, #31 8014a56: bf44 itt mi 8014a58: f043 0320 orrmi.w r3, r3, #32 8014a5c: 6023 strmi r3, [r4, #0] 8014a5e: b11d cbz r5, 8014a68 <_printf_i+0x19c> 8014a60: 2310 movs r3, #16 8014a62: e7ad b.n 80149c0 <_printf_i+0xf4> 8014a64: 4826 ldr r0, [pc, #152] @ (8014b00 <_printf_i+0x234>) 8014a66: e7e9 b.n 8014a3c <_printf_i+0x170> 8014a68: 6823 ldr r3, [r4, #0] 8014a6a: f023 0320 bic.w r3, r3, #32 8014a6e: 6023 str r3, [r4, #0] 8014a70: e7f6 b.n 8014a60 <_printf_i+0x194> 8014a72: 4616 mov r6, r2 8014a74: e7bd b.n 80149f2 <_printf_i+0x126> 8014a76: 6833 ldr r3, [r6, #0] 8014a78: 6825 ldr r5, [r4, #0] 8014a7a: 1d18 adds r0, r3, #4 8014a7c: 6961 ldr r1, [r4, #20] 8014a7e: 6030 str r0, [r6, #0] 8014a80: 062e lsls r6, r5, #24 8014a82: 681b ldr r3, [r3, #0] 8014a84: d501 bpl.n 8014a8a <_printf_i+0x1be> 8014a86: 6019 str r1, [r3, #0] 8014a88: e002 b.n 8014a90 <_printf_i+0x1c4> 8014a8a: 0668 lsls r0, r5, #25 8014a8c: d5fb bpl.n 8014a86 <_printf_i+0x1ba> 8014a8e: 8019 strh r1, [r3, #0] 8014a90: 2300 movs r3, #0 8014a92: 4616 mov r6, r2 8014a94: 6123 str r3, [r4, #16] 8014a96: e7bc b.n 8014a12 <_printf_i+0x146> 8014a98: 6833 ldr r3, [r6, #0] 8014a9a: 2100 movs r1, #0 8014a9c: 1d1a adds r2, r3, #4 8014a9e: 6032 str r2, [r6, #0] 8014aa0: 681e ldr r6, [r3, #0] 8014aa2: 6862 ldr r2, [r4, #4] 8014aa4: 4630 mov r0, r6 8014aa6: f000 f967 bl 8014d78 8014aaa: b108 cbz r0, 8014ab0 <_printf_i+0x1e4> 8014aac: 1b80 subs r0, r0, r6 8014aae: 6060 str r0, [r4, #4] 8014ab0: 6863 ldr r3, [r4, #4] 8014ab2: 6123 str r3, [r4, #16] 8014ab4: 2300 movs r3, #0 8014ab6: f884 3043 strb.w r3, [r4, #67] @ 0x43 8014aba: e7aa b.n 8014a12 <_printf_i+0x146> 8014abc: 4632 mov r2, r6 8014abe: 4649 mov r1, r9 8014ac0: 4640 mov r0, r8 8014ac2: 6923 ldr r3, [r4, #16] 8014ac4: 47d0 blx sl 8014ac6: 3001 adds r0, #1 8014ac8: d0ad beq.n 8014a26 <_printf_i+0x15a> 8014aca: 6823 ldr r3, [r4, #0] 8014acc: 079b lsls r3, r3, #30 8014ace: d413 bmi.n 8014af8 <_printf_i+0x22c> 8014ad0: 68e0 ldr r0, [r4, #12] 8014ad2: 9b03 ldr r3, [sp, #12] 8014ad4: 4298 cmp r0, r3 8014ad6: bfb8 it lt 8014ad8: 4618 movlt r0, r3 8014ada: e7a6 b.n 8014a2a <_printf_i+0x15e> 8014adc: 2301 movs r3, #1 8014ade: 4632 mov r2, r6 8014ae0: 4649 mov r1, r9 8014ae2: 4640 mov r0, r8 8014ae4: 47d0 blx sl 8014ae6: 3001 adds r0, #1 8014ae8: d09d beq.n 8014a26 <_printf_i+0x15a> 8014aea: 3501 adds r5, #1 8014aec: 68e3 ldr r3, [r4, #12] 8014aee: 9903 ldr r1, [sp, #12] 8014af0: 1a5b subs r3, r3, r1 8014af2: 42ab cmp r3, r5 8014af4: dcf2 bgt.n 8014adc <_printf_i+0x210> 8014af6: e7eb b.n 8014ad0 <_printf_i+0x204> 8014af8: 2500 movs r5, #0 8014afa: f104 0619 add.w r6, r4, #25 8014afe: e7f5 b.n 8014aec <_printf_i+0x220> 8014b00: 080179d6 .word 0x080179d6 8014b04: 080179e7 .word 0x080179e7 08014b08 : 8014b08: 2300 movs r3, #0 8014b0a: b510 push {r4, lr} 8014b0c: 4604 mov r4, r0 8014b0e: e9c0 3300 strd r3, r3, [r0] 8014b12: e9c0 3304 strd r3, r3, [r0, #16] 8014b16: 6083 str r3, [r0, #8] 8014b18: 8181 strh r1, [r0, #12] 8014b1a: 6643 str r3, [r0, #100] @ 0x64 8014b1c: 81c2 strh r2, [r0, #14] 8014b1e: 6183 str r3, [r0, #24] 8014b20: 4619 mov r1, r3 8014b22: 2208 movs r2, #8 8014b24: 305c adds r0, #92 @ 0x5c 8014b26: f000 f8ed bl 8014d04 8014b2a: 4b0d ldr r3, [pc, #52] @ (8014b60 ) 8014b2c: 6224 str r4, [r4, #32] 8014b2e: 6263 str r3, [r4, #36] @ 0x24 8014b30: 4b0c ldr r3, [pc, #48] @ (8014b64 ) 8014b32: 62a3 str r3, [r4, #40] @ 0x28 8014b34: 4b0c ldr r3, [pc, #48] @ (8014b68 ) 8014b36: 62e3 str r3, [r4, #44] @ 0x2c 8014b38: 4b0c ldr r3, [pc, #48] @ (8014b6c ) 8014b3a: 6323 str r3, [r4, #48] @ 0x30 8014b3c: 4b0c ldr r3, [pc, #48] @ (8014b70 ) 8014b3e: 429c cmp r4, r3 8014b40: d006 beq.n 8014b50 8014b42: f103 0268 add.w r2, r3, #104 @ 0x68 8014b46: 4294 cmp r4, r2 8014b48: d002 beq.n 8014b50 8014b4a: 33d0 adds r3, #208 @ 0xd0 8014b4c: 429c cmp r4, r3 8014b4e: d105 bne.n 8014b5c 8014b50: f104 0058 add.w r0, r4, #88 @ 0x58 8014b54: e8bd 4010 ldmia.w sp!, {r4, lr} 8014b58: f000 b906 b.w 8014d68 <__retarget_lock_init_recursive> 8014b5c: bd10 pop {r4, pc} 8014b5e: bf00 nop 8014b60: 08016709 .word 0x08016709 8014b64: 0801672b .word 0x0801672b 8014b68: 08016763 .word 0x08016763 8014b6c: 08016787 .word 0x08016787 8014b70: 2000148c .word 0x2000148c 08014b74 : 8014b74: 4a02 ldr r2, [pc, #8] @ (8014b80 ) 8014b76: 4903 ldr r1, [pc, #12] @ (8014b84 ) 8014b78: 4803 ldr r0, [pc, #12] @ (8014b88 ) 8014b7a: f000 b8a5 b.w 8014cc8 <_fwalk_sglue> 8014b7e: bf00 nop 8014b80: 20000090 .word 0x20000090 8014b84: 08015fad .word 0x08015fad 8014b88: 200000a0 .word 0x200000a0 08014b8c : 8014b8c: 6841 ldr r1, [r0, #4] 8014b8e: 4b0c ldr r3, [pc, #48] @ (8014bc0 ) 8014b90: b510 push {r4, lr} 8014b92: 4299 cmp r1, r3 8014b94: 4604 mov r4, r0 8014b96: d001 beq.n 8014b9c 8014b98: f001 fa08 bl 8015fac <_fflush_r> 8014b9c: 68a1 ldr r1, [r4, #8] 8014b9e: 4b09 ldr r3, [pc, #36] @ (8014bc4 ) 8014ba0: 4299 cmp r1, r3 8014ba2: d002 beq.n 8014baa 8014ba4: 4620 mov r0, r4 8014ba6: f001 fa01 bl 8015fac <_fflush_r> 8014baa: 68e1 ldr r1, [r4, #12] 8014bac: 4b06 ldr r3, [pc, #24] @ (8014bc8 ) 8014bae: 4299 cmp r1, r3 8014bb0: d004 beq.n 8014bbc 8014bb2: 4620 mov r0, r4 8014bb4: e8bd 4010 ldmia.w sp!, {r4, lr} 8014bb8: f001 b9f8 b.w 8015fac <_fflush_r> 8014bbc: bd10 pop {r4, pc} 8014bbe: bf00 nop 8014bc0: 2000148c .word 0x2000148c 8014bc4: 200014f4 .word 0x200014f4 8014bc8: 2000155c .word 0x2000155c 08014bcc : 8014bcc: b510 push {r4, lr} 8014bce: 4b0b ldr r3, [pc, #44] @ (8014bfc ) 8014bd0: 4c0b ldr r4, [pc, #44] @ (8014c00 ) 8014bd2: 4a0c ldr r2, [pc, #48] @ (8014c04 ) 8014bd4: 4620 mov r0, r4 8014bd6: 601a str r2, [r3, #0] 8014bd8: 2104 movs r1, #4 8014bda: 2200 movs r2, #0 8014bdc: f7ff ff94 bl 8014b08 8014be0: f104 0068 add.w r0, r4, #104 @ 0x68 8014be4: 2201 movs r2, #1 8014be6: 2109 movs r1, #9 8014be8: f7ff ff8e bl 8014b08 8014bec: f104 00d0 add.w r0, r4, #208 @ 0xd0 8014bf0: 2202 movs r2, #2 8014bf2: e8bd 4010 ldmia.w sp!, {r4, lr} 8014bf6: 2112 movs r1, #18 8014bf8: f7ff bf86 b.w 8014b08 8014bfc: 200015c4 .word 0x200015c4 8014c00: 2000148c .word 0x2000148c 8014c04: 08014b75 .word 0x08014b75 08014c08 <__sfp_lock_acquire>: 8014c08: 4801 ldr r0, [pc, #4] @ (8014c10 <__sfp_lock_acquire+0x8>) 8014c0a: f000 b8ae b.w 8014d6a <__retarget_lock_acquire_recursive> 8014c0e: bf00 nop 8014c10: 200015c9 .word 0x200015c9 08014c14 <__sfp_lock_release>: 8014c14: 4801 ldr r0, [pc, #4] @ (8014c1c <__sfp_lock_release+0x8>) 8014c16: f000 b8a9 b.w 8014d6c <__retarget_lock_release_recursive> 8014c1a: bf00 nop 8014c1c: 200015c9 .word 0x200015c9 08014c20 <__sinit>: 8014c20: b510 push {r4, lr} 8014c22: 4604 mov r4, r0 8014c24: f7ff fff0 bl 8014c08 <__sfp_lock_acquire> 8014c28: 6a23 ldr r3, [r4, #32] 8014c2a: b11b cbz r3, 8014c34 <__sinit+0x14> 8014c2c: e8bd 4010 ldmia.w sp!, {r4, lr} 8014c30: f7ff bff0 b.w 8014c14 <__sfp_lock_release> 8014c34: 4b04 ldr r3, [pc, #16] @ (8014c48 <__sinit+0x28>) 8014c36: 6223 str r3, [r4, #32] 8014c38: 4b04 ldr r3, [pc, #16] @ (8014c4c <__sinit+0x2c>) 8014c3a: 681b ldr r3, [r3, #0] 8014c3c: 2b00 cmp r3, #0 8014c3e: d1f5 bne.n 8014c2c <__sinit+0xc> 8014c40: f7ff ffc4 bl 8014bcc 8014c44: e7f2 b.n 8014c2c <__sinit+0xc> 8014c46: bf00 nop 8014c48: 08014b8d .word 0x08014b8d 8014c4c: 200015c4 .word 0x200015c4 08014c50 <_vsniprintf_r>: 8014c50: b530 push {r4, r5, lr} 8014c52: 4614 mov r4, r2 8014c54: 2c00 cmp r4, #0 8014c56: 4605 mov r5, r0 8014c58: 461a mov r2, r3 8014c5a: b09b sub sp, #108 @ 0x6c 8014c5c: da05 bge.n 8014c6a <_vsniprintf_r+0x1a> 8014c5e: 238b movs r3, #139 @ 0x8b 8014c60: 6003 str r3, [r0, #0] 8014c62: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8014c66: b01b add sp, #108 @ 0x6c 8014c68: bd30 pop {r4, r5, pc} 8014c6a: f44f 7302 mov.w r3, #520 @ 0x208 8014c6e: f8ad 300c strh.w r3, [sp, #12] 8014c72: f04f 0300 mov.w r3, #0 8014c76: 9319 str r3, [sp, #100] @ 0x64 8014c78: bf0c ite eq 8014c7a: 4623 moveq r3, r4 8014c7c: f104 33ff addne.w r3, r4, #4294967295 @ 0xffffffff 8014c80: 9302 str r3, [sp, #8] 8014c82: 9305 str r3, [sp, #20] 8014c84: f64f 73ff movw r3, #65535 @ 0xffff 8014c88: 9100 str r1, [sp, #0] 8014c8a: 9104 str r1, [sp, #16] 8014c8c: f8ad 300e strh.w r3, [sp, #14] 8014c90: 4669 mov r1, sp 8014c92: 9b1e ldr r3, [sp, #120] @ 0x78 8014c94: f000 ff64 bl 8015b60 <_svfiprintf_r> 8014c98: 1c43 adds r3, r0, #1 8014c9a: bfbc itt lt 8014c9c: 238b movlt r3, #139 @ 0x8b 8014c9e: 602b strlt r3, [r5, #0] 8014ca0: 2c00 cmp r4, #0 8014ca2: d0e0 beq.n 8014c66 <_vsniprintf_r+0x16> 8014ca4: 2200 movs r2, #0 8014ca6: 9b00 ldr r3, [sp, #0] 8014ca8: 701a strb r2, [r3, #0] 8014caa: e7dc b.n 8014c66 <_vsniprintf_r+0x16> 08014cac : 8014cac: b507 push {r0, r1, r2, lr} 8014cae: 9300 str r3, [sp, #0] 8014cb0: 4613 mov r3, r2 8014cb2: 460a mov r2, r1 8014cb4: 4601 mov r1, r0 8014cb6: 4803 ldr r0, [pc, #12] @ (8014cc4 ) 8014cb8: 6800 ldr r0, [r0, #0] 8014cba: f7ff ffc9 bl 8014c50 <_vsniprintf_r> 8014cbe: b003 add sp, #12 8014cc0: f85d fb04 ldr.w pc, [sp], #4 8014cc4: 2000009c .word 0x2000009c 08014cc8 <_fwalk_sglue>: 8014cc8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8014ccc: 4607 mov r7, r0 8014cce: 4688 mov r8, r1 8014cd0: 4614 mov r4, r2 8014cd2: 2600 movs r6, #0 8014cd4: e9d4 9501 ldrd r9, r5, [r4, #4] 8014cd8: f1b9 0901 subs.w r9, r9, #1 8014cdc: d505 bpl.n 8014cea <_fwalk_sglue+0x22> 8014cde: 6824 ldr r4, [r4, #0] 8014ce0: 2c00 cmp r4, #0 8014ce2: d1f7 bne.n 8014cd4 <_fwalk_sglue+0xc> 8014ce4: 4630 mov r0, r6 8014ce6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8014cea: 89ab ldrh r3, [r5, #12] 8014cec: 2b01 cmp r3, #1 8014cee: d907 bls.n 8014d00 <_fwalk_sglue+0x38> 8014cf0: f9b5 300e ldrsh.w r3, [r5, #14] 8014cf4: 3301 adds r3, #1 8014cf6: d003 beq.n 8014d00 <_fwalk_sglue+0x38> 8014cf8: 4629 mov r1, r5 8014cfa: 4638 mov r0, r7 8014cfc: 47c0 blx r8 8014cfe: 4306 orrs r6, r0 8014d00: 3568 adds r5, #104 @ 0x68 8014d02: e7e9 b.n 8014cd8 <_fwalk_sglue+0x10> 08014d04 : 8014d04: 4603 mov r3, r0 8014d06: 4402 add r2, r0 8014d08: 4293 cmp r3, r2 8014d0a: d100 bne.n 8014d0e 8014d0c: 4770 bx lr 8014d0e: f803 1b01 strb.w r1, [r3], #1 8014d12: e7f9 b.n 8014d08 08014d14 <__errno>: 8014d14: 4b01 ldr r3, [pc, #4] @ (8014d1c <__errno+0x8>) 8014d16: 6818 ldr r0, [r3, #0] 8014d18: 4770 bx lr 8014d1a: bf00 nop 8014d1c: 2000009c .word 0x2000009c 08014d20 <__libc_init_array>: 8014d20: b570 push {r4, r5, r6, lr} 8014d22: 2600 movs r6, #0 8014d24: 4d0c ldr r5, [pc, #48] @ (8014d58 <__libc_init_array+0x38>) 8014d26: 4c0d ldr r4, [pc, #52] @ (8014d5c <__libc_init_array+0x3c>) 8014d28: 1b64 subs r4, r4, r5 8014d2a: 10a4 asrs r4, r4, #2 8014d2c: 42a6 cmp r6, r4 8014d2e: d109 bne.n 8014d44 <__libc_init_array+0x24> 8014d30: f002 f904 bl 8016f3c <_init> 8014d34: 2600 movs r6, #0 8014d36: 4d0a ldr r5, [pc, #40] @ (8014d60 <__libc_init_array+0x40>) 8014d38: 4c0a ldr r4, [pc, #40] @ (8014d64 <__libc_init_array+0x44>) 8014d3a: 1b64 subs r4, r4, r5 8014d3c: 10a4 asrs r4, r4, #2 8014d3e: 42a6 cmp r6, r4 8014d40: d105 bne.n 8014d4e <__libc_init_array+0x2e> 8014d42: bd70 pop {r4, r5, r6, pc} 8014d44: f855 3b04 ldr.w r3, [r5], #4 8014d48: 4798 blx r3 8014d4a: 3601 adds r6, #1 8014d4c: e7ee b.n 8014d2c <__libc_init_array+0xc> 8014d4e: f855 3b04 ldr.w r3, [r5], #4 8014d52: 4798 blx r3 8014d54: 3601 adds r6, #1 8014d56: e7f2 b.n 8014d3e <__libc_init_array+0x1e> 8014d58: 08017d44 .word 0x08017d44 8014d5c: 08017d44 .word 0x08017d44 8014d60: 08017d44 .word 0x08017d44 8014d64: 08017d48 .word 0x08017d48 08014d68 <__retarget_lock_init_recursive>: 8014d68: 4770 bx lr 08014d6a <__retarget_lock_acquire_recursive>: 8014d6a: 4770 bx lr 08014d6c <__retarget_lock_release_recursive>: 8014d6c: 4770 bx lr ... 08014d70 <_localeconv_r>: 8014d70: 4800 ldr r0, [pc, #0] @ (8014d74 <_localeconv_r+0x4>) 8014d72: 4770 bx lr 8014d74: 200001dc .word 0x200001dc 08014d78 : 8014d78: 4603 mov r3, r0 8014d7a: b510 push {r4, lr} 8014d7c: b2c9 uxtb r1, r1 8014d7e: 4402 add r2, r0 8014d80: 4293 cmp r3, r2 8014d82: 4618 mov r0, r3 8014d84: d101 bne.n 8014d8a 8014d86: 2000 movs r0, #0 8014d88: e003 b.n 8014d92 8014d8a: 7804 ldrb r4, [r0, #0] 8014d8c: 3301 adds r3, #1 8014d8e: 428c cmp r4, r1 8014d90: d1f6 bne.n 8014d80 8014d92: bd10 pop {r4, pc} 08014d94 : 8014d94: 440a add r2, r1 8014d96: 4291 cmp r1, r2 8014d98: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 8014d9c: d100 bne.n 8014da0 8014d9e: 4770 bx lr 8014da0: b510 push {r4, lr} 8014da2: f811 4b01 ldrb.w r4, [r1], #1 8014da6: 4291 cmp r1, r2 8014da8: f803 4f01 strb.w r4, [r3, #1]! 8014dac: d1f9 bne.n 8014da2 8014dae: bd10 pop {r4, pc} 08014db0 <__assert_func>: 8014db0: b51f push {r0, r1, r2, r3, r4, lr} 8014db2: 4614 mov r4, r2 8014db4: 461a mov r2, r3 8014db6: 4b09 ldr r3, [pc, #36] @ (8014ddc <__assert_func+0x2c>) 8014db8: 4605 mov r5, r0 8014dba: 681b ldr r3, [r3, #0] 8014dbc: 68d8 ldr r0, [r3, #12] 8014dbe: b14c cbz r4, 8014dd4 <__assert_func+0x24> 8014dc0: 4b07 ldr r3, [pc, #28] @ (8014de0 <__assert_func+0x30>) 8014dc2: e9cd 3401 strd r3, r4, [sp, #4] 8014dc6: 9100 str r1, [sp, #0] 8014dc8: 462b mov r3, r5 8014dca: 4906 ldr r1, [pc, #24] @ (8014de4 <__assert_func+0x34>) 8014dcc: f001 fce0 bl 8016790 8014dd0: f001 fd8e bl 80168f0 8014dd4: 4b04 ldr r3, [pc, #16] @ (8014de8 <__assert_func+0x38>) 8014dd6: 461c mov r4, r3 8014dd8: e7f3 b.n 8014dc2 <__assert_func+0x12> 8014dda: bf00 nop 8014ddc: 2000009c .word 0x2000009c 8014de0: 080179f8 .word 0x080179f8 8014de4: 08017a05 .word 0x08017a05 8014de8: 08017a33 .word 0x08017a33 08014dec : 8014dec: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8014df0: 6903 ldr r3, [r0, #16] 8014df2: 690c ldr r4, [r1, #16] 8014df4: 4607 mov r7, r0 8014df6: 42a3 cmp r3, r4 8014df8: db7e blt.n 8014ef8 8014dfa: 3c01 subs r4, #1 8014dfc: 00a3 lsls r3, r4, #2 8014dfe: f100 0514 add.w r5, r0, #20 8014e02: f101 0814 add.w r8, r1, #20 8014e06: 9300 str r3, [sp, #0] 8014e08: eb05 0384 add.w r3, r5, r4, lsl #2 8014e0c: 9301 str r3, [sp, #4] 8014e0e: f858 3024 ldr.w r3, [r8, r4, lsl #2] 8014e12: f855 2024 ldr.w r2, [r5, r4, lsl #2] 8014e16: 3301 adds r3, #1 8014e18: 429a cmp r2, r3 8014e1a: fbb2 f6f3 udiv r6, r2, r3 8014e1e: eb08 0984 add.w r9, r8, r4, lsl #2 8014e22: d32e bcc.n 8014e82 8014e24: f04f 0a00 mov.w sl, #0 8014e28: 46c4 mov ip, r8 8014e2a: 46ae mov lr, r5 8014e2c: 46d3 mov fp, sl 8014e2e: f85c 3b04 ldr.w r3, [ip], #4 8014e32: b298 uxth r0, r3 8014e34: fb06 a000 mla r0, r6, r0, sl 8014e38: 0c1b lsrs r3, r3, #16 8014e3a: 0c02 lsrs r2, r0, #16 8014e3c: fb06 2303 mla r3, r6, r3, r2 8014e40: f8de 2000 ldr.w r2, [lr] 8014e44: b280 uxth r0, r0 8014e46: b292 uxth r2, r2 8014e48: 1a12 subs r2, r2, r0 8014e4a: 445a add r2, fp 8014e4c: f8de 0000 ldr.w r0, [lr] 8014e50: ea4f 4a13 mov.w sl, r3, lsr #16 8014e54: b29b uxth r3, r3 8014e56: ebc3 4322 rsb r3, r3, r2, asr #16 8014e5a: eb03 4310 add.w r3, r3, r0, lsr #16 8014e5e: b292 uxth r2, r2 8014e60: ea42 4203 orr.w r2, r2, r3, lsl #16 8014e64: 45e1 cmp r9, ip 8014e66: ea4f 4b23 mov.w fp, r3, asr #16 8014e6a: f84e 2b04 str.w r2, [lr], #4 8014e6e: d2de bcs.n 8014e2e 8014e70: 9b00 ldr r3, [sp, #0] 8014e72: 58eb ldr r3, [r5, r3] 8014e74: b92b cbnz r3, 8014e82 8014e76: 9b01 ldr r3, [sp, #4] 8014e78: 3b04 subs r3, #4 8014e7a: 429d cmp r5, r3 8014e7c: 461a mov r2, r3 8014e7e: d32f bcc.n 8014ee0 8014e80: 613c str r4, [r7, #16] 8014e82: 4638 mov r0, r7 8014e84: f001 fb38 bl 80164f8 <__mcmp> 8014e88: 2800 cmp r0, #0 8014e8a: db25 blt.n 8014ed8 8014e8c: 4629 mov r1, r5 8014e8e: 2000 movs r0, #0 8014e90: f858 2b04 ldr.w r2, [r8], #4 8014e94: f8d1 c000 ldr.w ip, [r1] 8014e98: fa1f fe82 uxth.w lr, r2 8014e9c: fa1f f38c uxth.w r3, ip 8014ea0: eba3 030e sub.w r3, r3, lr 8014ea4: 4403 add r3, r0 8014ea6: 0c12 lsrs r2, r2, #16 8014ea8: ebc2 4223 rsb r2, r2, r3, asr #16 8014eac: eb02 421c add.w r2, r2, ip, lsr #16 8014eb0: b29b uxth r3, r3 8014eb2: ea43 4302 orr.w r3, r3, r2, lsl #16 8014eb6: 45c1 cmp r9, r8 8014eb8: ea4f 4022 mov.w r0, r2, asr #16 8014ebc: f841 3b04 str.w r3, [r1], #4 8014ec0: d2e6 bcs.n 8014e90 8014ec2: f855 2024 ldr.w r2, [r5, r4, lsl #2] 8014ec6: eb05 0384 add.w r3, r5, r4, lsl #2 8014eca: b922 cbnz r2, 8014ed6 8014ecc: 3b04 subs r3, #4 8014ece: 429d cmp r5, r3 8014ed0: 461a mov r2, r3 8014ed2: d30b bcc.n 8014eec 8014ed4: 613c str r4, [r7, #16] 8014ed6: 3601 adds r6, #1 8014ed8: 4630 mov r0, r6 8014eda: b003 add sp, #12 8014edc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8014ee0: 6812 ldr r2, [r2, #0] 8014ee2: 3b04 subs r3, #4 8014ee4: 2a00 cmp r2, #0 8014ee6: d1cb bne.n 8014e80 8014ee8: 3c01 subs r4, #1 8014eea: e7c6 b.n 8014e7a 8014eec: 6812 ldr r2, [r2, #0] 8014eee: 3b04 subs r3, #4 8014ef0: 2a00 cmp r2, #0 8014ef2: d1ef bne.n 8014ed4 8014ef4: 3c01 subs r4, #1 8014ef6: e7ea b.n 8014ece 8014ef8: 2000 movs r0, #0 8014efa: e7ee b.n 8014eda 8014efc: 0000 movs r0, r0 ... 08014f00 <_dtoa_r>: 8014f00: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8014f04: 4614 mov r4, r2 8014f06: 461d mov r5, r3 8014f08: 69c7 ldr r7, [r0, #28] 8014f0a: b097 sub sp, #92 @ 0x5c 8014f0c: 4681 mov r9, r0 8014f0e: e9cd 4506 strd r4, r5, [sp, #24] 8014f12: 9e23 ldr r6, [sp, #140] @ 0x8c 8014f14: b97f cbnz r7, 8014f36 <_dtoa_r+0x36> 8014f16: 2010 movs r0, #16 8014f18: f000 ff1e bl 8015d58 8014f1c: 4602 mov r2, r0 8014f1e: f8c9 001c str.w r0, [r9, #28] 8014f22: b920 cbnz r0, 8014f2e <_dtoa_r+0x2e> 8014f24: 21ef movs r1, #239 @ 0xef 8014f26: 4bac ldr r3, [pc, #688] @ (80151d8 <_dtoa_r+0x2d8>) 8014f28: 48ac ldr r0, [pc, #688] @ (80151dc <_dtoa_r+0x2dc>) 8014f2a: f7ff ff41 bl 8014db0 <__assert_func> 8014f2e: e9c0 7701 strd r7, r7, [r0, #4] 8014f32: 6007 str r7, [r0, #0] 8014f34: 60c7 str r7, [r0, #12] 8014f36: f8d9 301c ldr.w r3, [r9, #28] 8014f3a: 6819 ldr r1, [r3, #0] 8014f3c: b159 cbz r1, 8014f56 <_dtoa_r+0x56> 8014f3e: 685a ldr r2, [r3, #4] 8014f40: 2301 movs r3, #1 8014f42: 4093 lsls r3, r2 8014f44: 604a str r2, [r1, #4] 8014f46: 608b str r3, [r1, #8] 8014f48: 4648 mov r0, r9 8014f4a: f001 f8a3 bl 8016094 <_Bfree> 8014f4e: 2200 movs r2, #0 8014f50: f8d9 301c ldr.w r3, [r9, #28] 8014f54: 601a str r2, [r3, #0] 8014f56: 1e2b subs r3, r5, #0 8014f58: bfaf iteee ge 8014f5a: 2300 movge r3, #0 8014f5c: 2201 movlt r2, #1 8014f5e: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000 8014f62: 9307 strlt r3, [sp, #28] 8014f64: bfa8 it ge 8014f66: 6033 strge r3, [r6, #0] 8014f68: f8dd 801c ldr.w r8, [sp, #28] 8014f6c: 4b9c ldr r3, [pc, #624] @ (80151e0 <_dtoa_r+0x2e0>) 8014f6e: bfb8 it lt 8014f70: 6032 strlt r2, [r6, #0] 8014f72: ea33 0308 bics.w r3, r3, r8 8014f76: d112 bne.n 8014f9e <_dtoa_r+0x9e> 8014f78: f242 730f movw r3, #9999 @ 0x270f 8014f7c: 9a22 ldr r2, [sp, #136] @ 0x88 8014f7e: 6013 str r3, [r2, #0] 8014f80: f3c8 0313 ubfx r3, r8, #0, #20 8014f84: 4323 orrs r3, r4 8014f86: f000 855e beq.w 8015a46 <_dtoa_r+0xb46> 8014f8a: 9b24 ldr r3, [sp, #144] @ 0x90 8014f8c: f8df a254 ldr.w sl, [pc, #596] @ 80151e4 <_dtoa_r+0x2e4> 8014f90: 2b00 cmp r3, #0 8014f92: f000 8560 beq.w 8015a56 <_dtoa_r+0xb56> 8014f96: f10a 0303 add.w r3, sl, #3 8014f9a: f000 bd5a b.w 8015a52 <_dtoa_r+0xb52> 8014f9e: e9dd 2306 ldrd r2, r3, [sp, #24] 8014fa2: e9cd 230c strd r2, r3, [sp, #48] @ 0x30 8014fa6: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8014faa: 2200 movs r2, #0 8014fac: 2300 movs r3, #0 8014fae: f7f3 fd67 bl 8008a80 <__aeabi_dcmpeq> 8014fb2: 4607 mov r7, r0 8014fb4: b158 cbz r0, 8014fce <_dtoa_r+0xce> 8014fb6: 2301 movs r3, #1 8014fb8: 9a22 ldr r2, [sp, #136] @ 0x88 8014fba: 6013 str r3, [r2, #0] 8014fbc: 9b24 ldr r3, [sp, #144] @ 0x90 8014fbe: b113 cbz r3, 8014fc6 <_dtoa_r+0xc6> 8014fc0: 4b89 ldr r3, [pc, #548] @ (80151e8 <_dtoa_r+0x2e8>) 8014fc2: 9a24 ldr r2, [sp, #144] @ 0x90 8014fc4: 6013 str r3, [r2, #0] 8014fc6: f8df a224 ldr.w sl, [pc, #548] @ 80151ec <_dtoa_r+0x2ec> 8014fca: f000 bd44 b.w 8015a56 <_dtoa_r+0xb56> 8014fce: ab14 add r3, sp, #80 @ 0x50 8014fd0: 9301 str r3, [sp, #4] 8014fd2: ab15 add r3, sp, #84 @ 0x54 8014fd4: 9300 str r3, [sp, #0] 8014fd6: 4648 mov r0, r9 8014fd8: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30 8014fdc: f001 fb3c bl 8016658 <__d2b> 8014fe0: f3c8 560a ubfx r6, r8, #20, #11 8014fe4: 9003 str r0, [sp, #12] 8014fe6: 2e00 cmp r6, #0 8014fe8: d078 beq.n 80150dc <_dtoa_r+0x1dc> 8014fea: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8014fee: 9b0d ldr r3, [sp, #52] @ 0x34 8014ff0: f2a6 36ff subw r6, r6, #1023 @ 0x3ff 8014ff4: f3c3 0313 ubfx r3, r3, #0, #20 8014ff8: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000 8014ffc: f443 1340 orr.w r3, r3, #3145728 @ 0x300000 8015000: 9712 str r7, [sp, #72] @ 0x48 8015002: 4619 mov r1, r3 8015004: 2200 movs r2, #0 8015006: 4b7a ldr r3, [pc, #488] @ (80151f0 <_dtoa_r+0x2f0>) 8015008: f7f3 f91a bl 8008240 <__aeabi_dsub> 801500c: a36c add r3, pc, #432 @ (adr r3, 80151c0 <_dtoa_r+0x2c0>) 801500e: e9d3 2300 ldrd r2, r3, [r3] 8015012: f7f3 facd bl 80085b0 <__aeabi_dmul> 8015016: a36c add r3, pc, #432 @ (adr r3, 80151c8 <_dtoa_r+0x2c8>) 8015018: e9d3 2300 ldrd r2, r3, [r3] 801501c: f7f3 f912 bl 8008244 <__adddf3> 8015020: 4604 mov r4, r0 8015022: 4630 mov r0, r6 8015024: 460d mov r5, r1 8015026: f7f3 fa59 bl 80084dc <__aeabi_i2d> 801502a: a369 add r3, pc, #420 @ (adr r3, 80151d0 <_dtoa_r+0x2d0>) 801502c: e9d3 2300 ldrd r2, r3, [r3] 8015030: f7f3 fabe bl 80085b0 <__aeabi_dmul> 8015034: 4602 mov r2, r0 8015036: 460b mov r3, r1 8015038: 4620 mov r0, r4 801503a: 4629 mov r1, r5 801503c: f7f3 f902 bl 8008244 <__adddf3> 8015040: 4604 mov r4, r0 8015042: 460d mov r5, r1 8015044: f7f3 fd64 bl 8008b10 <__aeabi_d2iz> 8015048: 2200 movs r2, #0 801504a: 4607 mov r7, r0 801504c: 2300 movs r3, #0 801504e: 4620 mov r0, r4 8015050: 4629 mov r1, r5 8015052: f7f3 fd1f bl 8008a94 <__aeabi_dcmplt> 8015056: b140 cbz r0, 801506a <_dtoa_r+0x16a> 8015058: 4638 mov r0, r7 801505a: f7f3 fa3f bl 80084dc <__aeabi_i2d> 801505e: 4622 mov r2, r4 8015060: 462b mov r3, r5 8015062: f7f3 fd0d bl 8008a80 <__aeabi_dcmpeq> 8015066: b900 cbnz r0, 801506a <_dtoa_r+0x16a> 8015068: 3f01 subs r7, #1 801506a: 2f16 cmp r7, #22 801506c: d854 bhi.n 8015118 <_dtoa_r+0x218> 801506e: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8015072: 4b60 ldr r3, [pc, #384] @ (80151f4 <_dtoa_r+0x2f4>) 8015074: eb03 03c7 add.w r3, r3, r7, lsl #3 8015078: e9d3 2300 ldrd r2, r3, [r3] 801507c: f7f3 fd0a bl 8008a94 <__aeabi_dcmplt> 8015080: 2800 cmp r0, #0 8015082: d04b beq.n 801511c <_dtoa_r+0x21c> 8015084: 2300 movs r3, #0 8015086: 3f01 subs r7, #1 8015088: 930f str r3, [sp, #60] @ 0x3c 801508a: 9b14 ldr r3, [sp, #80] @ 0x50 801508c: 1b9b subs r3, r3, r6 801508e: 1e5a subs r2, r3, #1 8015090: bf49 itett mi 8015092: f1c3 0301 rsbmi r3, r3, #1 8015096: 2300 movpl r3, #0 8015098: 9304 strmi r3, [sp, #16] 801509a: 2300 movmi r3, #0 801509c: 9209 str r2, [sp, #36] @ 0x24 801509e: bf54 ite pl 80150a0: 9304 strpl r3, [sp, #16] 80150a2: 9309 strmi r3, [sp, #36] @ 0x24 80150a4: 2f00 cmp r7, #0 80150a6: db3b blt.n 8015120 <_dtoa_r+0x220> 80150a8: 9b09 ldr r3, [sp, #36] @ 0x24 80150aa: 970e str r7, [sp, #56] @ 0x38 80150ac: 443b add r3, r7 80150ae: 9309 str r3, [sp, #36] @ 0x24 80150b0: 2300 movs r3, #0 80150b2: 930a str r3, [sp, #40] @ 0x28 80150b4: 9b20 ldr r3, [sp, #128] @ 0x80 80150b6: 2b09 cmp r3, #9 80150b8: d865 bhi.n 8015186 <_dtoa_r+0x286> 80150ba: 2b05 cmp r3, #5 80150bc: bfc4 itt gt 80150be: 3b04 subgt r3, #4 80150c0: 9320 strgt r3, [sp, #128] @ 0x80 80150c2: 9b20 ldr r3, [sp, #128] @ 0x80 80150c4: bfc8 it gt 80150c6: 2400 movgt r4, #0 80150c8: f1a3 0302 sub.w r3, r3, #2 80150cc: bfd8 it le 80150ce: 2401 movle r4, #1 80150d0: 2b03 cmp r3, #3 80150d2: d864 bhi.n 801519e <_dtoa_r+0x29e> 80150d4: e8df f003 tbb [pc, r3] 80150d8: 2c385553 .word 0x2c385553 80150dc: e9dd 6314 ldrd r6, r3, [sp, #80] @ 0x50 80150e0: 441e add r6, r3 80150e2: f206 4332 addw r3, r6, #1074 @ 0x432 80150e6: 2b20 cmp r3, #32 80150e8: bfc1 itttt gt 80150ea: f1c3 0340 rsbgt r3, r3, #64 @ 0x40 80150ee: fa08 f803 lslgt.w r8, r8, r3 80150f2: f206 4312 addwgt r3, r6, #1042 @ 0x412 80150f6: fa24 f303 lsrgt.w r3, r4, r3 80150fa: bfd6 itet le 80150fc: f1c3 0320 rsble r3, r3, #32 8015100: ea48 0003 orrgt.w r0, r8, r3 8015104: fa04 f003 lslle.w r0, r4, r3 8015108: f7f3 f9d8 bl 80084bc <__aeabi_ui2d> 801510c: 2201 movs r2, #1 801510e: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000 8015112: 3e01 subs r6, #1 8015114: 9212 str r2, [sp, #72] @ 0x48 8015116: e774 b.n 8015002 <_dtoa_r+0x102> 8015118: 2301 movs r3, #1 801511a: e7b5 b.n 8015088 <_dtoa_r+0x188> 801511c: 900f str r0, [sp, #60] @ 0x3c 801511e: e7b4 b.n 801508a <_dtoa_r+0x18a> 8015120: 9b04 ldr r3, [sp, #16] 8015122: 1bdb subs r3, r3, r7 8015124: 9304 str r3, [sp, #16] 8015126: 427b negs r3, r7 8015128: 930a str r3, [sp, #40] @ 0x28 801512a: 2300 movs r3, #0 801512c: 930e str r3, [sp, #56] @ 0x38 801512e: e7c1 b.n 80150b4 <_dtoa_r+0x1b4> 8015130: 2301 movs r3, #1 8015132: 930b str r3, [sp, #44] @ 0x2c 8015134: 9b21 ldr r3, [sp, #132] @ 0x84 8015136: eb07 0b03 add.w fp, r7, r3 801513a: f10b 0301 add.w r3, fp, #1 801513e: 2b01 cmp r3, #1 8015140: 9308 str r3, [sp, #32] 8015142: bfb8 it lt 8015144: 2301 movlt r3, #1 8015146: e006 b.n 8015156 <_dtoa_r+0x256> 8015148: 2301 movs r3, #1 801514a: 930b str r3, [sp, #44] @ 0x2c 801514c: 9b21 ldr r3, [sp, #132] @ 0x84 801514e: 2b00 cmp r3, #0 8015150: dd28 ble.n 80151a4 <_dtoa_r+0x2a4> 8015152: 469b mov fp, r3 8015154: 9308 str r3, [sp, #32] 8015156: 2100 movs r1, #0 8015158: 2204 movs r2, #4 801515a: f8d9 001c ldr.w r0, [r9, #28] 801515e: f102 0514 add.w r5, r2, #20 8015162: 429d cmp r5, r3 8015164: d926 bls.n 80151b4 <_dtoa_r+0x2b4> 8015166: 6041 str r1, [r0, #4] 8015168: 4648 mov r0, r9 801516a: f000 ff53 bl 8016014 <_Balloc> 801516e: 4682 mov sl, r0 8015170: 2800 cmp r0, #0 8015172: d143 bne.n 80151fc <_dtoa_r+0x2fc> 8015174: 4602 mov r2, r0 8015176: f240 11af movw r1, #431 @ 0x1af 801517a: 4b1f ldr r3, [pc, #124] @ (80151f8 <_dtoa_r+0x2f8>) 801517c: e6d4 b.n 8014f28 <_dtoa_r+0x28> 801517e: 2300 movs r3, #0 8015180: e7e3 b.n 801514a <_dtoa_r+0x24a> 8015182: 2300 movs r3, #0 8015184: e7d5 b.n 8015132 <_dtoa_r+0x232> 8015186: 2401 movs r4, #1 8015188: 2300 movs r3, #0 801518a: 940b str r4, [sp, #44] @ 0x2c 801518c: 9320 str r3, [sp, #128] @ 0x80 801518e: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff 8015192: 2200 movs r2, #0 8015194: 2312 movs r3, #18 8015196: f8cd b020 str.w fp, [sp, #32] 801519a: 9221 str r2, [sp, #132] @ 0x84 801519c: e7db b.n 8015156 <_dtoa_r+0x256> 801519e: 2301 movs r3, #1 80151a0: 930b str r3, [sp, #44] @ 0x2c 80151a2: e7f4 b.n 801518e <_dtoa_r+0x28e> 80151a4: f04f 0b01 mov.w fp, #1 80151a8: 465b mov r3, fp 80151aa: f8cd b020 str.w fp, [sp, #32] 80151ae: f8cd b084 str.w fp, [sp, #132] @ 0x84 80151b2: e7d0 b.n 8015156 <_dtoa_r+0x256> 80151b4: 3101 adds r1, #1 80151b6: 0052 lsls r2, r2, #1 80151b8: e7d1 b.n 801515e <_dtoa_r+0x25e> 80151ba: bf00 nop 80151bc: f3af 8000 nop.w 80151c0: 636f4361 .word 0x636f4361 80151c4: 3fd287a7 .word 0x3fd287a7 80151c8: 8b60c8b3 .word 0x8b60c8b3 80151cc: 3fc68a28 .word 0x3fc68a28 80151d0: 509f79fb .word 0x509f79fb 80151d4: 3fd34413 .word 0x3fd34413 80151d8: 08017a41 .word 0x08017a41 80151dc: 08017a58 .word 0x08017a58 80151e0: 7ff00000 .word 0x7ff00000 80151e4: 08017a3d .word 0x08017a3d 80151e8: 080179d5 .word 0x080179d5 80151ec: 080179d4 .word 0x080179d4 80151f0: 3ff80000 .word 0x3ff80000 80151f4: 08017b70 .word 0x08017b70 80151f8: 08017ab0 .word 0x08017ab0 80151fc: f8d9 301c ldr.w r3, [r9, #28] 8015200: 6018 str r0, [r3, #0] 8015202: 9b08 ldr r3, [sp, #32] 8015204: 2b0e cmp r3, #14 8015206: f200 80a1 bhi.w 801534c <_dtoa_r+0x44c> 801520a: 2c00 cmp r4, #0 801520c: f000 809e beq.w 801534c <_dtoa_r+0x44c> 8015210: 2f00 cmp r7, #0 8015212: dd33 ble.n 801527c <_dtoa_r+0x37c> 8015214: 4b9c ldr r3, [pc, #624] @ (8015488 <_dtoa_r+0x588>) 8015216: f007 020f and.w r2, r7, #15 801521a: eb03 03c2 add.w r3, r3, r2, lsl #3 801521e: 05f8 lsls r0, r7, #23 8015220: e9d3 3400 ldrd r3, r4, [r3] 8015224: e9cd 3410 strd r3, r4, [sp, #64] @ 0x40 8015228: ea4f 1427 mov.w r4, r7, asr #4 801522c: d516 bpl.n 801525c <_dtoa_r+0x35c> 801522e: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8015232: 4b96 ldr r3, [pc, #600] @ (801548c <_dtoa_r+0x58c>) 8015234: 2603 movs r6, #3 8015236: e9d3 2308 ldrd r2, r3, [r3, #32] 801523a: f7f3 fae3 bl 8008804 <__aeabi_ddiv> 801523e: e9cd 0106 strd r0, r1, [sp, #24] 8015242: f004 040f and.w r4, r4, #15 8015246: 4d91 ldr r5, [pc, #580] @ (801548c <_dtoa_r+0x58c>) 8015248: b954 cbnz r4, 8015260 <_dtoa_r+0x360> 801524a: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 801524e: e9dd 0106 ldrd r0, r1, [sp, #24] 8015252: f7f3 fad7 bl 8008804 <__aeabi_ddiv> 8015256: e9cd 0106 strd r0, r1, [sp, #24] 801525a: e028 b.n 80152ae <_dtoa_r+0x3ae> 801525c: 2602 movs r6, #2 801525e: e7f2 b.n 8015246 <_dtoa_r+0x346> 8015260: 07e1 lsls r1, r4, #31 8015262: d508 bpl.n 8015276 <_dtoa_r+0x376> 8015264: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 8015268: e9d5 2300 ldrd r2, r3, [r5] 801526c: f7f3 f9a0 bl 80085b0 <__aeabi_dmul> 8015270: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 8015274: 3601 adds r6, #1 8015276: 1064 asrs r4, r4, #1 8015278: 3508 adds r5, #8 801527a: e7e5 b.n 8015248 <_dtoa_r+0x348> 801527c: f000 80af beq.w 80153de <_dtoa_r+0x4de> 8015280: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 8015284: 427c negs r4, r7 8015286: 4b80 ldr r3, [pc, #512] @ (8015488 <_dtoa_r+0x588>) 8015288: f004 020f and.w r2, r4, #15 801528c: eb03 03c2 add.w r3, r3, r2, lsl #3 8015290: e9d3 2300 ldrd r2, r3, [r3] 8015294: f7f3 f98c bl 80085b0 <__aeabi_dmul> 8015298: 2602 movs r6, #2 801529a: 2300 movs r3, #0 801529c: e9cd 0106 strd r0, r1, [sp, #24] 80152a0: 4d7a ldr r5, [pc, #488] @ (801548c <_dtoa_r+0x58c>) 80152a2: 1124 asrs r4, r4, #4 80152a4: 2c00 cmp r4, #0 80152a6: f040 808f bne.w 80153c8 <_dtoa_r+0x4c8> 80152aa: 2b00 cmp r3, #0 80152ac: d1d3 bne.n 8015256 <_dtoa_r+0x356> 80152ae: e9dd 4506 ldrd r4, r5, [sp, #24] 80152b2: 9b0f ldr r3, [sp, #60] @ 0x3c 80152b4: 2b00 cmp r3, #0 80152b6: f000 8094 beq.w 80153e2 <_dtoa_r+0x4e2> 80152ba: 2200 movs r2, #0 80152bc: 4620 mov r0, r4 80152be: 4629 mov r1, r5 80152c0: 4b73 ldr r3, [pc, #460] @ (8015490 <_dtoa_r+0x590>) 80152c2: f7f3 fbe7 bl 8008a94 <__aeabi_dcmplt> 80152c6: 2800 cmp r0, #0 80152c8: f000 808b beq.w 80153e2 <_dtoa_r+0x4e2> 80152cc: 9b08 ldr r3, [sp, #32] 80152ce: 2b00 cmp r3, #0 80152d0: f000 8087 beq.w 80153e2 <_dtoa_r+0x4e2> 80152d4: f1bb 0f00 cmp.w fp, #0 80152d8: dd34 ble.n 8015344 <_dtoa_r+0x444> 80152da: 4620 mov r0, r4 80152dc: 2200 movs r2, #0 80152de: 4629 mov r1, r5 80152e0: 4b6c ldr r3, [pc, #432] @ (8015494 <_dtoa_r+0x594>) 80152e2: f7f3 f965 bl 80085b0 <__aeabi_dmul> 80152e6: 465c mov r4, fp 80152e8: e9cd 0106 strd r0, r1, [sp, #24] 80152ec: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff 80152f0: 3601 adds r6, #1 80152f2: 4630 mov r0, r6 80152f4: f7f3 f8f2 bl 80084dc <__aeabi_i2d> 80152f8: e9dd 2306 ldrd r2, r3, [sp, #24] 80152fc: f7f3 f958 bl 80085b0 <__aeabi_dmul> 8015300: 2200 movs r2, #0 8015302: 4b65 ldr r3, [pc, #404] @ (8015498 <_dtoa_r+0x598>) 8015304: f7f2 ff9e bl 8008244 <__adddf3> 8015308: 4605 mov r5, r0 801530a: f1a1 7650 sub.w r6, r1, #54525952 @ 0x3400000 801530e: 2c00 cmp r4, #0 8015310: d16a bne.n 80153e8 <_dtoa_r+0x4e8> 8015312: e9dd 0106 ldrd r0, r1, [sp, #24] 8015316: 2200 movs r2, #0 8015318: 4b60 ldr r3, [pc, #384] @ (801549c <_dtoa_r+0x59c>) 801531a: f7f2 ff91 bl 8008240 <__aeabi_dsub> 801531e: 4602 mov r2, r0 8015320: 460b mov r3, r1 8015322: e9cd 2306 strd r2, r3, [sp, #24] 8015326: 462a mov r2, r5 8015328: 4633 mov r3, r6 801532a: f7f3 fbd1 bl 8008ad0 <__aeabi_dcmpgt> 801532e: 2800 cmp r0, #0 8015330: f040 8298 bne.w 8015864 <_dtoa_r+0x964> 8015334: e9dd 0106 ldrd r0, r1, [sp, #24] 8015338: 462a mov r2, r5 801533a: f106 4300 add.w r3, r6, #2147483648 @ 0x80000000 801533e: f7f3 fba9 bl 8008a94 <__aeabi_dcmplt> 8015342: bb38 cbnz r0, 8015394 <_dtoa_r+0x494> 8015344: e9dd 340c ldrd r3, r4, [sp, #48] @ 0x30 8015348: e9cd 3406 strd r3, r4, [sp, #24] 801534c: 9b15 ldr r3, [sp, #84] @ 0x54 801534e: 2b00 cmp r3, #0 8015350: f2c0 8157 blt.w 8015602 <_dtoa_r+0x702> 8015354: 2f0e cmp r7, #14 8015356: f300 8154 bgt.w 8015602 <_dtoa_r+0x702> 801535a: 4b4b ldr r3, [pc, #300] @ (8015488 <_dtoa_r+0x588>) 801535c: eb03 03c7 add.w r3, r3, r7, lsl #3 8015360: e9d3 3400 ldrd r3, r4, [r3] 8015364: e9cd 3404 strd r3, r4, [sp, #16] 8015368: 9b21 ldr r3, [sp, #132] @ 0x84 801536a: 2b00 cmp r3, #0 801536c: f280 80e5 bge.w 801553a <_dtoa_r+0x63a> 8015370: 9b08 ldr r3, [sp, #32] 8015372: 2b00 cmp r3, #0 8015374: f300 80e1 bgt.w 801553a <_dtoa_r+0x63a> 8015378: d10c bne.n 8015394 <_dtoa_r+0x494> 801537a: e9dd 0104 ldrd r0, r1, [sp, #16] 801537e: 2200 movs r2, #0 8015380: 4b46 ldr r3, [pc, #280] @ (801549c <_dtoa_r+0x59c>) 8015382: f7f3 f915 bl 80085b0 <__aeabi_dmul> 8015386: e9dd 2306 ldrd r2, r3, [sp, #24] 801538a: f7f3 fb97 bl 8008abc <__aeabi_dcmpge> 801538e: 2800 cmp r0, #0 8015390: f000 8266 beq.w 8015860 <_dtoa_r+0x960> 8015394: 2400 movs r4, #0 8015396: 4625 mov r5, r4 8015398: 9b21 ldr r3, [sp, #132] @ 0x84 801539a: 4656 mov r6, sl 801539c: ea6f 0803 mvn.w r8, r3 80153a0: 2700 movs r7, #0 80153a2: 4621 mov r1, r4 80153a4: 4648 mov r0, r9 80153a6: f000 fe75 bl 8016094 <_Bfree> 80153aa: 2d00 cmp r5, #0 80153ac: f000 80bd beq.w 801552a <_dtoa_r+0x62a> 80153b0: b12f cbz r7, 80153be <_dtoa_r+0x4be> 80153b2: 42af cmp r7, r5 80153b4: d003 beq.n 80153be <_dtoa_r+0x4be> 80153b6: 4639 mov r1, r7 80153b8: 4648 mov r0, r9 80153ba: f000 fe6b bl 8016094 <_Bfree> 80153be: 4629 mov r1, r5 80153c0: 4648 mov r0, r9 80153c2: f000 fe67 bl 8016094 <_Bfree> 80153c6: e0b0 b.n 801552a <_dtoa_r+0x62a> 80153c8: 07e2 lsls r2, r4, #31 80153ca: d505 bpl.n 80153d8 <_dtoa_r+0x4d8> 80153cc: e9d5 2300 ldrd r2, r3, [r5] 80153d0: f7f3 f8ee bl 80085b0 <__aeabi_dmul> 80153d4: 2301 movs r3, #1 80153d6: 3601 adds r6, #1 80153d8: 1064 asrs r4, r4, #1 80153da: 3508 adds r5, #8 80153dc: e762 b.n 80152a4 <_dtoa_r+0x3a4> 80153de: 2602 movs r6, #2 80153e0: e765 b.n 80152ae <_dtoa_r+0x3ae> 80153e2: 46b8 mov r8, r7 80153e4: 9c08 ldr r4, [sp, #32] 80153e6: e784 b.n 80152f2 <_dtoa_r+0x3f2> 80153e8: 4b27 ldr r3, [pc, #156] @ (8015488 <_dtoa_r+0x588>) 80153ea: 990b ldr r1, [sp, #44] @ 0x2c 80153ec: eb03 03c4 add.w r3, r3, r4, lsl #3 80153f0: e953 2302 ldrd r2, r3, [r3, #-8] 80153f4: 4454 add r4, sl 80153f6: 2900 cmp r1, #0 80153f8: d054 beq.n 80154a4 <_dtoa_r+0x5a4> 80153fa: 2000 movs r0, #0 80153fc: 4928 ldr r1, [pc, #160] @ (80154a0 <_dtoa_r+0x5a0>) 80153fe: f7f3 fa01 bl 8008804 <__aeabi_ddiv> 8015402: 4633 mov r3, r6 8015404: 462a mov r2, r5 8015406: f7f2 ff1b bl 8008240 <__aeabi_dsub> 801540a: 4656 mov r6, sl 801540c: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 8015410: e9dd 0106 ldrd r0, r1, [sp, #24] 8015414: f7f3 fb7c bl 8008b10 <__aeabi_d2iz> 8015418: 4605 mov r5, r0 801541a: f7f3 f85f bl 80084dc <__aeabi_i2d> 801541e: 4602 mov r2, r0 8015420: 460b mov r3, r1 8015422: e9dd 0106 ldrd r0, r1, [sp, #24] 8015426: f7f2 ff0b bl 8008240 <__aeabi_dsub> 801542a: 4602 mov r2, r0 801542c: 460b mov r3, r1 801542e: 3530 adds r5, #48 @ 0x30 8015430: e9cd 2306 strd r2, r3, [sp, #24] 8015434: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 8015438: f806 5b01 strb.w r5, [r6], #1 801543c: f7f3 fb2a bl 8008a94 <__aeabi_dcmplt> 8015440: 2800 cmp r0, #0 8015442: d172 bne.n 801552a <_dtoa_r+0x62a> 8015444: e9dd 2306 ldrd r2, r3, [sp, #24] 8015448: 2000 movs r0, #0 801544a: 4911 ldr r1, [pc, #68] @ (8015490 <_dtoa_r+0x590>) 801544c: f7f2 fef8 bl 8008240 <__aeabi_dsub> 8015450: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 8015454: f7f3 fb1e bl 8008a94 <__aeabi_dcmplt> 8015458: 2800 cmp r0, #0 801545a: f040 80b4 bne.w 80155c6 <_dtoa_r+0x6c6> 801545e: 42a6 cmp r6, r4 8015460: f43f af70 beq.w 8015344 <_dtoa_r+0x444> 8015464: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 8015468: 2200 movs r2, #0 801546a: 4b0a ldr r3, [pc, #40] @ (8015494 <_dtoa_r+0x594>) 801546c: f7f3 f8a0 bl 80085b0 <__aeabi_dmul> 8015470: 2200 movs r2, #0 8015472: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 8015476: e9dd 0106 ldrd r0, r1, [sp, #24] 801547a: 4b06 ldr r3, [pc, #24] @ (8015494 <_dtoa_r+0x594>) 801547c: f7f3 f898 bl 80085b0 <__aeabi_dmul> 8015480: e9cd 0106 strd r0, r1, [sp, #24] 8015484: e7c4 b.n 8015410 <_dtoa_r+0x510> 8015486: bf00 nop 8015488: 08017b70 .word 0x08017b70 801548c: 08017b48 .word 0x08017b48 8015490: 3ff00000 .word 0x3ff00000 8015494: 40240000 .word 0x40240000 8015498: 401c0000 .word 0x401c0000 801549c: 40140000 .word 0x40140000 80154a0: 3fe00000 .word 0x3fe00000 80154a4: 4631 mov r1, r6 80154a6: 4628 mov r0, r5 80154a8: f7f3 f882 bl 80085b0 <__aeabi_dmul> 80154ac: 4656 mov r6, sl 80154ae: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 80154b2: 9413 str r4, [sp, #76] @ 0x4c 80154b4: e9dd 0106 ldrd r0, r1, [sp, #24] 80154b8: f7f3 fb2a bl 8008b10 <__aeabi_d2iz> 80154bc: 4605 mov r5, r0 80154be: f7f3 f80d bl 80084dc <__aeabi_i2d> 80154c2: 4602 mov r2, r0 80154c4: 460b mov r3, r1 80154c6: e9dd 0106 ldrd r0, r1, [sp, #24] 80154ca: f7f2 feb9 bl 8008240 <__aeabi_dsub> 80154ce: 4602 mov r2, r0 80154d0: 460b mov r3, r1 80154d2: 3530 adds r5, #48 @ 0x30 80154d4: f806 5b01 strb.w r5, [r6], #1 80154d8: 42a6 cmp r6, r4 80154da: e9cd 2306 strd r2, r3, [sp, #24] 80154de: f04f 0200 mov.w r2, #0 80154e2: d124 bne.n 801552e <_dtoa_r+0x62e> 80154e4: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 80154e8: 4bae ldr r3, [pc, #696] @ (80157a4 <_dtoa_r+0x8a4>) 80154ea: f7f2 feab bl 8008244 <__adddf3> 80154ee: 4602 mov r2, r0 80154f0: 460b mov r3, r1 80154f2: e9dd 0106 ldrd r0, r1, [sp, #24] 80154f6: f7f3 faeb bl 8008ad0 <__aeabi_dcmpgt> 80154fa: 2800 cmp r0, #0 80154fc: d163 bne.n 80155c6 <_dtoa_r+0x6c6> 80154fe: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 8015502: 2000 movs r0, #0 8015504: 49a7 ldr r1, [pc, #668] @ (80157a4 <_dtoa_r+0x8a4>) 8015506: f7f2 fe9b bl 8008240 <__aeabi_dsub> 801550a: 4602 mov r2, r0 801550c: 460b mov r3, r1 801550e: e9dd 0106 ldrd r0, r1, [sp, #24] 8015512: f7f3 fabf bl 8008a94 <__aeabi_dcmplt> 8015516: 2800 cmp r0, #0 8015518: f43f af14 beq.w 8015344 <_dtoa_r+0x444> 801551c: 9e13 ldr r6, [sp, #76] @ 0x4c 801551e: 1e73 subs r3, r6, #1 8015520: 9313 str r3, [sp, #76] @ 0x4c 8015522: f816 3c01 ldrb.w r3, [r6, #-1] 8015526: 2b30 cmp r3, #48 @ 0x30 8015528: d0f8 beq.n 801551c <_dtoa_r+0x61c> 801552a: 4647 mov r7, r8 801552c: e03b b.n 80155a6 <_dtoa_r+0x6a6> 801552e: 4b9e ldr r3, [pc, #632] @ (80157a8 <_dtoa_r+0x8a8>) 8015530: f7f3 f83e bl 80085b0 <__aeabi_dmul> 8015534: e9cd 0106 strd r0, r1, [sp, #24] 8015538: e7bc b.n 80154b4 <_dtoa_r+0x5b4> 801553a: 4656 mov r6, sl 801553c: e9dd 4506 ldrd r4, r5, [sp, #24] 8015540: e9dd 2304 ldrd r2, r3, [sp, #16] 8015544: 4620 mov r0, r4 8015546: 4629 mov r1, r5 8015548: f7f3 f95c bl 8008804 <__aeabi_ddiv> 801554c: f7f3 fae0 bl 8008b10 <__aeabi_d2iz> 8015550: 4680 mov r8, r0 8015552: f7f2 ffc3 bl 80084dc <__aeabi_i2d> 8015556: e9dd 2304 ldrd r2, r3, [sp, #16] 801555a: f7f3 f829 bl 80085b0 <__aeabi_dmul> 801555e: 4602 mov r2, r0 8015560: 460b mov r3, r1 8015562: 4620 mov r0, r4 8015564: 4629 mov r1, r5 8015566: f7f2 fe6b bl 8008240 <__aeabi_dsub> 801556a: f108 0430 add.w r4, r8, #48 @ 0x30 801556e: 9d08 ldr r5, [sp, #32] 8015570: f806 4b01 strb.w r4, [r6], #1 8015574: eba6 040a sub.w r4, r6, sl 8015578: 42a5 cmp r5, r4 801557a: 4602 mov r2, r0 801557c: 460b mov r3, r1 801557e: d133 bne.n 80155e8 <_dtoa_r+0x6e8> 8015580: f7f2 fe60 bl 8008244 <__adddf3> 8015584: e9dd 2304 ldrd r2, r3, [sp, #16] 8015588: 4604 mov r4, r0 801558a: 460d mov r5, r1 801558c: f7f3 faa0 bl 8008ad0 <__aeabi_dcmpgt> 8015590: b9c0 cbnz r0, 80155c4 <_dtoa_r+0x6c4> 8015592: e9dd 2304 ldrd r2, r3, [sp, #16] 8015596: 4620 mov r0, r4 8015598: 4629 mov r1, r5 801559a: f7f3 fa71 bl 8008a80 <__aeabi_dcmpeq> 801559e: b110 cbz r0, 80155a6 <_dtoa_r+0x6a6> 80155a0: f018 0f01 tst.w r8, #1 80155a4: d10e bne.n 80155c4 <_dtoa_r+0x6c4> 80155a6: 4648 mov r0, r9 80155a8: 9903 ldr r1, [sp, #12] 80155aa: f000 fd73 bl 8016094 <_Bfree> 80155ae: 2300 movs r3, #0 80155b0: 7033 strb r3, [r6, #0] 80155b2: 9b22 ldr r3, [sp, #136] @ 0x88 80155b4: 3701 adds r7, #1 80155b6: 601f str r7, [r3, #0] 80155b8: 9b24 ldr r3, [sp, #144] @ 0x90 80155ba: 2b00 cmp r3, #0 80155bc: f000 824b beq.w 8015a56 <_dtoa_r+0xb56> 80155c0: 601e str r6, [r3, #0] 80155c2: e248 b.n 8015a56 <_dtoa_r+0xb56> 80155c4: 46b8 mov r8, r7 80155c6: 4633 mov r3, r6 80155c8: 461e mov r6, r3 80155ca: f813 2d01 ldrb.w r2, [r3, #-1]! 80155ce: 2a39 cmp r2, #57 @ 0x39 80155d0: d106 bne.n 80155e0 <_dtoa_r+0x6e0> 80155d2: 459a cmp sl, r3 80155d4: d1f8 bne.n 80155c8 <_dtoa_r+0x6c8> 80155d6: 2230 movs r2, #48 @ 0x30 80155d8: f108 0801 add.w r8, r8, #1 80155dc: f88a 2000 strb.w r2, [sl] 80155e0: 781a ldrb r2, [r3, #0] 80155e2: 3201 adds r2, #1 80155e4: 701a strb r2, [r3, #0] 80155e6: e7a0 b.n 801552a <_dtoa_r+0x62a> 80155e8: 2200 movs r2, #0 80155ea: 4b6f ldr r3, [pc, #444] @ (80157a8 <_dtoa_r+0x8a8>) 80155ec: f7f2 ffe0 bl 80085b0 <__aeabi_dmul> 80155f0: 2200 movs r2, #0 80155f2: 2300 movs r3, #0 80155f4: 4604 mov r4, r0 80155f6: 460d mov r5, r1 80155f8: f7f3 fa42 bl 8008a80 <__aeabi_dcmpeq> 80155fc: 2800 cmp r0, #0 80155fe: d09f beq.n 8015540 <_dtoa_r+0x640> 8015600: e7d1 b.n 80155a6 <_dtoa_r+0x6a6> 8015602: 9a0b ldr r2, [sp, #44] @ 0x2c 8015604: 2a00 cmp r2, #0 8015606: f000 80ea beq.w 80157de <_dtoa_r+0x8de> 801560a: 9a20 ldr r2, [sp, #128] @ 0x80 801560c: 2a01 cmp r2, #1 801560e: f300 80cd bgt.w 80157ac <_dtoa_r+0x8ac> 8015612: 9a12 ldr r2, [sp, #72] @ 0x48 8015614: 2a00 cmp r2, #0 8015616: f000 80c1 beq.w 801579c <_dtoa_r+0x89c> 801561a: f203 4333 addw r3, r3, #1075 @ 0x433 801561e: 9c0a ldr r4, [sp, #40] @ 0x28 8015620: 9e04 ldr r6, [sp, #16] 8015622: 9a04 ldr r2, [sp, #16] 8015624: 2101 movs r1, #1 8015626: 441a add r2, r3 8015628: 9204 str r2, [sp, #16] 801562a: 9a09 ldr r2, [sp, #36] @ 0x24 801562c: 4648 mov r0, r9 801562e: 441a add r2, r3 8015630: 9209 str r2, [sp, #36] @ 0x24 8015632: f000 fde3 bl 80161fc <__i2b> 8015636: 4605 mov r5, r0 8015638: b166 cbz r6, 8015654 <_dtoa_r+0x754> 801563a: 9b09 ldr r3, [sp, #36] @ 0x24 801563c: 2b00 cmp r3, #0 801563e: dd09 ble.n 8015654 <_dtoa_r+0x754> 8015640: 42b3 cmp r3, r6 8015642: bfa8 it ge 8015644: 4633 movge r3, r6 8015646: 9a04 ldr r2, [sp, #16] 8015648: 1af6 subs r6, r6, r3 801564a: 1ad2 subs r2, r2, r3 801564c: 9204 str r2, [sp, #16] 801564e: 9a09 ldr r2, [sp, #36] @ 0x24 8015650: 1ad3 subs r3, r2, r3 8015652: 9309 str r3, [sp, #36] @ 0x24 8015654: 9b0a ldr r3, [sp, #40] @ 0x28 8015656: b30b cbz r3, 801569c <_dtoa_r+0x79c> 8015658: 9b0b ldr r3, [sp, #44] @ 0x2c 801565a: 2b00 cmp r3, #0 801565c: f000 80c6 beq.w 80157ec <_dtoa_r+0x8ec> 8015660: 2c00 cmp r4, #0 8015662: f000 80c0 beq.w 80157e6 <_dtoa_r+0x8e6> 8015666: 4629 mov r1, r5 8015668: 4622 mov r2, r4 801566a: 4648 mov r0, r9 801566c: f000 fe7e bl 801636c <__pow5mult> 8015670: 9a03 ldr r2, [sp, #12] 8015672: 4601 mov r1, r0 8015674: 4605 mov r5, r0 8015676: 4648 mov r0, r9 8015678: f000 fdd6 bl 8016228 <__multiply> 801567c: 9903 ldr r1, [sp, #12] 801567e: 4680 mov r8, r0 8015680: 4648 mov r0, r9 8015682: f000 fd07 bl 8016094 <_Bfree> 8015686: 9b0a ldr r3, [sp, #40] @ 0x28 8015688: 1b1b subs r3, r3, r4 801568a: 930a str r3, [sp, #40] @ 0x28 801568c: f000 80b1 beq.w 80157f2 <_dtoa_r+0x8f2> 8015690: 4641 mov r1, r8 8015692: 9a0a ldr r2, [sp, #40] @ 0x28 8015694: 4648 mov r0, r9 8015696: f000 fe69 bl 801636c <__pow5mult> 801569a: 9003 str r0, [sp, #12] 801569c: 2101 movs r1, #1 801569e: 4648 mov r0, r9 80156a0: f000 fdac bl 80161fc <__i2b> 80156a4: 9b0e ldr r3, [sp, #56] @ 0x38 80156a6: 4604 mov r4, r0 80156a8: 2b00 cmp r3, #0 80156aa: f000 81d8 beq.w 8015a5e <_dtoa_r+0xb5e> 80156ae: 461a mov r2, r3 80156b0: 4601 mov r1, r0 80156b2: 4648 mov r0, r9 80156b4: f000 fe5a bl 801636c <__pow5mult> 80156b8: 9b20 ldr r3, [sp, #128] @ 0x80 80156ba: 4604 mov r4, r0 80156bc: 2b01 cmp r3, #1 80156be: f300 809f bgt.w 8015800 <_dtoa_r+0x900> 80156c2: 9b06 ldr r3, [sp, #24] 80156c4: 2b00 cmp r3, #0 80156c6: f040 8097 bne.w 80157f8 <_dtoa_r+0x8f8> 80156ca: 9b07 ldr r3, [sp, #28] 80156cc: f3c3 0313 ubfx r3, r3, #0, #20 80156d0: 2b00 cmp r3, #0 80156d2: f040 8093 bne.w 80157fc <_dtoa_r+0x8fc> 80156d6: 9b07 ldr r3, [sp, #28] 80156d8: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 80156dc: 0d1b lsrs r3, r3, #20 80156de: 051b lsls r3, r3, #20 80156e0: b133 cbz r3, 80156f0 <_dtoa_r+0x7f0> 80156e2: 9b04 ldr r3, [sp, #16] 80156e4: 3301 adds r3, #1 80156e6: 9304 str r3, [sp, #16] 80156e8: 9b09 ldr r3, [sp, #36] @ 0x24 80156ea: 3301 adds r3, #1 80156ec: 9309 str r3, [sp, #36] @ 0x24 80156ee: 2301 movs r3, #1 80156f0: 930a str r3, [sp, #40] @ 0x28 80156f2: 9b0e ldr r3, [sp, #56] @ 0x38 80156f4: 2b00 cmp r3, #0 80156f6: f000 81b8 beq.w 8015a6a <_dtoa_r+0xb6a> 80156fa: 6923 ldr r3, [r4, #16] 80156fc: eb04 0383 add.w r3, r4, r3, lsl #2 8015700: 6918 ldr r0, [r3, #16] 8015702: f000 fd2f bl 8016164 <__hi0bits> 8015706: f1c0 0020 rsb r0, r0, #32 801570a: 9b09 ldr r3, [sp, #36] @ 0x24 801570c: 4418 add r0, r3 801570e: f010 001f ands.w r0, r0, #31 8015712: f000 8082 beq.w 801581a <_dtoa_r+0x91a> 8015716: f1c0 0320 rsb r3, r0, #32 801571a: 2b04 cmp r3, #4 801571c: dd73 ble.n 8015806 <_dtoa_r+0x906> 801571e: 9b04 ldr r3, [sp, #16] 8015720: f1c0 001c rsb r0, r0, #28 8015724: 4403 add r3, r0 8015726: 9304 str r3, [sp, #16] 8015728: 9b09 ldr r3, [sp, #36] @ 0x24 801572a: 4406 add r6, r0 801572c: 4403 add r3, r0 801572e: 9309 str r3, [sp, #36] @ 0x24 8015730: 9b04 ldr r3, [sp, #16] 8015732: 2b00 cmp r3, #0 8015734: dd05 ble.n 8015742 <_dtoa_r+0x842> 8015736: 461a mov r2, r3 8015738: 4648 mov r0, r9 801573a: 9903 ldr r1, [sp, #12] 801573c: f000 fe70 bl 8016420 <__lshift> 8015740: 9003 str r0, [sp, #12] 8015742: 9b09 ldr r3, [sp, #36] @ 0x24 8015744: 2b00 cmp r3, #0 8015746: dd05 ble.n 8015754 <_dtoa_r+0x854> 8015748: 4621 mov r1, r4 801574a: 461a mov r2, r3 801574c: 4648 mov r0, r9 801574e: f000 fe67 bl 8016420 <__lshift> 8015752: 4604 mov r4, r0 8015754: 9b0f ldr r3, [sp, #60] @ 0x3c 8015756: 2b00 cmp r3, #0 8015758: d061 beq.n 801581e <_dtoa_r+0x91e> 801575a: 4621 mov r1, r4 801575c: 9803 ldr r0, [sp, #12] 801575e: f000 fecb bl 80164f8 <__mcmp> 8015762: 2800 cmp r0, #0 8015764: da5b bge.n 801581e <_dtoa_r+0x91e> 8015766: 2300 movs r3, #0 8015768: 220a movs r2, #10 801576a: 4648 mov r0, r9 801576c: 9903 ldr r1, [sp, #12] 801576e: f000 fcb3 bl 80160d8 <__multadd> 8015772: 9b0b ldr r3, [sp, #44] @ 0x2c 8015774: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff 8015778: 9003 str r0, [sp, #12] 801577a: 2b00 cmp r3, #0 801577c: f000 8177 beq.w 8015a6e <_dtoa_r+0xb6e> 8015780: 4629 mov r1, r5 8015782: 2300 movs r3, #0 8015784: 220a movs r2, #10 8015786: 4648 mov r0, r9 8015788: f000 fca6 bl 80160d8 <__multadd> 801578c: f1bb 0f00 cmp.w fp, #0 8015790: 4605 mov r5, r0 8015792: dc6f bgt.n 8015874 <_dtoa_r+0x974> 8015794: 9b20 ldr r3, [sp, #128] @ 0x80 8015796: 2b02 cmp r3, #2 8015798: dc49 bgt.n 801582e <_dtoa_r+0x92e> 801579a: e06b b.n 8015874 <_dtoa_r+0x974> 801579c: 9b14 ldr r3, [sp, #80] @ 0x50 801579e: f1c3 0336 rsb r3, r3, #54 @ 0x36 80157a2: e73c b.n 801561e <_dtoa_r+0x71e> 80157a4: 3fe00000 .word 0x3fe00000 80157a8: 40240000 .word 0x40240000 80157ac: 9b08 ldr r3, [sp, #32] 80157ae: 1e5c subs r4, r3, #1 80157b0: 9b0a ldr r3, [sp, #40] @ 0x28 80157b2: 42a3 cmp r3, r4 80157b4: db09 blt.n 80157ca <_dtoa_r+0x8ca> 80157b6: 1b1c subs r4, r3, r4 80157b8: 9b08 ldr r3, [sp, #32] 80157ba: 2b00 cmp r3, #0 80157bc: f6bf af30 bge.w 8015620 <_dtoa_r+0x720> 80157c0: 9b04 ldr r3, [sp, #16] 80157c2: 9a08 ldr r2, [sp, #32] 80157c4: 1a9e subs r6, r3, r2 80157c6: 2300 movs r3, #0 80157c8: e72b b.n 8015622 <_dtoa_r+0x722> 80157ca: 9b0a ldr r3, [sp, #40] @ 0x28 80157cc: 9a0e ldr r2, [sp, #56] @ 0x38 80157ce: 1ae3 subs r3, r4, r3 80157d0: 441a add r2, r3 80157d2: 940a str r4, [sp, #40] @ 0x28 80157d4: 9e04 ldr r6, [sp, #16] 80157d6: 2400 movs r4, #0 80157d8: 9b08 ldr r3, [sp, #32] 80157da: 920e str r2, [sp, #56] @ 0x38 80157dc: e721 b.n 8015622 <_dtoa_r+0x722> 80157de: 9c0a ldr r4, [sp, #40] @ 0x28 80157e0: 9e04 ldr r6, [sp, #16] 80157e2: 9d0b ldr r5, [sp, #44] @ 0x2c 80157e4: e728 b.n 8015638 <_dtoa_r+0x738> 80157e6: f8dd 800c ldr.w r8, [sp, #12] 80157ea: e751 b.n 8015690 <_dtoa_r+0x790> 80157ec: 9a0a ldr r2, [sp, #40] @ 0x28 80157ee: 9903 ldr r1, [sp, #12] 80157f0: e750 b.n 8015694 <_dtoa_r+0x794> 80157f2: f8cd 800c str.w r8, [sp, #12] 80157f6: e751 b.n 801569c <_dtoa_r+0x79c> 80157f8: 2300 movs r3, #0 80157fa: e779 b.n 80156f0 <_dtoa_r+0x7f0> 80157fc: 9b06 ldr r3, [sp, #24] 80157fe: e777 b.n 80156f0 <_dtoa_r+0x7f0> 8015800: 2300 movs r3, #0 8015802: 930a str r3, [sp, #40] @ 0x28 8015804: e779 b.n 80156fa <_dtoa_r+0x7fa> 8015806: d093 beq.n 8015730 <_dtoa_r+0x830> 8015808: 9a04 ldr r2, [sp, #16] 801580a: 331c adds r3, #28 801580c: 441a add r2, r3 801580e: 9204 str r2, [sp, #16] 8015810: 9a09 ldr r2, [sp, #36] @ 0x24 8015812: 441e add r6, r3 8015814: 441a add r2, r3 8015816: 9209 str r2, [sp, #36] @ 0x24 8015818: e78a b.n 8015730 <_dtoa_r+0x830> 801581a: 4603 mov r3, r0 801581c: e7f4 b.n 8015808 <_dtoa_r+0x908> 801581e: 9b08 ldr r3, [sp, #32] 8015820: 46b8 mov r8, r7 8015822: 2b00 cmp r3, #0 8015824: dc20 bgt.n 8015868 <_dtoa_r+0x968> 8015826: 469b mov fp, r3 8015828: 9b20 ldr r3, [sp, #128] @ 0x80 801582a: 2b02 cmp r3, #2 801582c: dd1e ble.n 801586c <_dtoa_r+0x96c> 801582e: f1bb 0f00 cmp.w fp, #0 8015832: f47f adb1 bne.w 8015398 <_dtoa_r+0x498> 8015836: 4621 mov r1, r4 8015838: 465b mov r3, fp 801583a: 2205 movs r2, #5 801583c: 4648 mov r0, r9 801583e: f000 fc4b bl 80160d8 <__multadd> 8015842: 4601 mov r1, r0 8015844: 4604 mov r4, r0 8015846: 9803 ldr r0, [sp, #12] 8015848: f000 fe56 bl 80164f8 <__mcmp> 801584c: 2800 cmp r0, #0 801584e: f77f ada3 ble.w 8015398 <_dtoa_r+0x498> 8015852: 4656 mov r6, sl 8015854: 2331 movs r3, #49 @ 0x31 8015856: f108 0801 add.w r8, r8, #1 801585a: f806 3b01 strb.w r3, [r6], #1 801585e: e59f b.n 80153a0 <_dtoa_r+0x4a0> 8015860: 46b8 mov r8, r7 8015862: 9c08 ldr r4, [sp, #32] 8015864: 4625 mov r5, r4 8015866: e7f4 b.n 8015852 <_dtoa_r+0x952> 8015868: f8dd b020 ldr.w fp, [sp, #32] 801586c: 9b0b ldr r3, [sp, #44] @ 0x2c 801586e: 2b00 cmp r3, #0 8015870: f000 8101 beq.w 8015a76 <_dtoa_r+0xb76> 8015874: 2e00 cmp r6, #0 8015876: dd05 ble.n 8015884 <_dtoa_r+0x984> 8015878: 4629 mov r1, r5 801587a: 4632 mov r2, r6 801587c: 4648 mov r0, r9 801587e: f000 fdcf bl 8016420 <__lshift> 8015882: 4605 mov r5, r0 8015884: 9b0a ldr r3, [sp, #40] @ 0x28 8015886: 2b00 cmp r3, #0 8015888: d05c beq.n 8015944 <_dtoa_r+0xa44> 801588a: 4648 mov r0, r9 801588c: 6869 ldr r1, [r5, #4] 801588e: f000 fbc1 bl 8016014 <_Balloc> 8015892: 4606 mov r6, r0 8015894: b928 cbnz r0, 80158a2 <_dtoa_r+0x9a2> 8015896: 4602 mov r2, r0 8015898: f240 21ef movw r1, #751 @ 0x2ef 801589c: 4b80 ldr r3, [pc, #512] @ (8015aa0 <_dtoa_r+0xba0>) 801589e: f7ff bb43 b.w 8014f28 <_dtoa_r+0x28> 80158a2: 692a ldr r2, [r5, #16] 80158a4: f105 010c add.w r1, r5, #12 80158a8: 3202 adds r2, #2 80158aa: 0092 lsls r2, r2, #2 80158ac: 300c adds r0, #12 80158ae: f7ff fa71 bl 8014d94 80158b2: 2201 movs r2, #1 80158b4: 4631 mov r1, r6 80158b6: 4648 mov r0, r9 80158b8: f000 fdb2 bl 8016420 <__lshift> 80158bc: 462f mov r7, r5 80158be: 4605 mov r5, r0 80158c0: f10a 0301 add.w r3, sl, #1 80158c4: 9304 str r3, [sp, #16] 80158c6: eb0a 030b add.w r3, sl, fp 80158ca: 930a str r3, [sp, #40] @ 0x28 80158cc: 9b06 ldr r3, [sp, #24] 80158ce: f003 0301 and.w r3, r3, #1 80158d2: 9309 str r3, [sp, #36] @ 0x24 80158d4: 9b04 ldr r3, [sp, #16] 80158d6: 4621 mov r1, r4 80158d8: 9803 ldr r0, [sp, #12] 80158da: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff 80158de: f7ff fa85 bl 8014dec 80158e2: 4603 mov r3, r0 80158e4: 4639 mov r1, r7 80158e6: 3330 adds r3, #48 @ 0x30 80158e8: 9006 str r0, [sp, #24] 80158ea: 9803 ldr r0, [sp, #12] 80158ec: 930b str r3, [sp, #44] @ 0x2c 80158ee: f000 fe03 bl 80164f8 <__mcmp> 80158f2: 462a mov r2, r5 80158f4: 9008 str r0, [sp, #32] 80158f6: 4621 mov r1, r4 80158f8: 4648 mov r0, r9 80158fa: f000 fe19 bl 8016530 <__mdiff> 80158fe: 68c2 ldr r2, [r0, #12] 8015900: 4606 mov r6, r0 8015902: 9b0b ldr r3, [sp, #44] @ 0x2c 8015904: bb02 cbnz r2, 8015948 <_dtoa_r+0xa48> 8015906: 4601 mov r1, r0 8015908: 9803 ldr r0, [sp, #12] 801590a: f000 fdf5 bl 80164f8 <__mcmp> 801590e: 4602 mov r2, r0 8015910: 9b0b ldr r3, [sp, #44] @ 0x2c 8015912: 4631 mov r1, r6 8015914: 4648 mov r0, r9 8015916: e9cd 320b strd r3, r2, [sp, #44] @ 0x2c 801591a: f000 fbbb bl 8016094 <_Bfree> 801591e: 9b20 ldr r3, [sp, #128] @ 0x80 8015920: 9a0c ldr r2, [sp, #48] @ 0x30 8015922: 9e04 ldr r6, [sp, #16] 8015924: ea42 0103 orr.w r1, r2, r3 8015928: 9b09 ldr r3, [sp, #36] @ 0x24 801592a: 4319 orrs r1, r3 801592c: 9b0b ldr r3, [sp, #44] @ 0x2c 801592e: d10d bne.n 801594c <_dtoa_r+0xa4c> 8015930: 2b39 cmp r3, #57 @ 0x39 8015932: d027 beq.n 8015984 <_dtoa_r+0xa84> 8015934: 9a08 ldr r2, [sp, #32] 8015936: 2a00 cmp r2, #0 8015938: dd01 ble.n 801593e <_dtoa_r+0xa3e> 801593a: 9b06 ldr r3, [sp, #24] 801593c: 3331 adds r3, #49 @ 0x31 801593e: f88b 3000 strb.w r3, [fp] 8015942: e52e b.n 80153a2 <_dtoa_r+0x4a2> 8015944: 4628 mov r0, r5 8015946: e7b9 b.n 80158bc <_dtoa_r+0x9bc> 8015948: 2201 movs r2, #1 801594a: e7e2 b.n 8015912 <_dtoa_r+0xa12> 801594c: 9908 ldr r1, [sp, #32] 801594e: 2900 cmp r1, #0 8015950: db04 blt.n 801595c <_dtoa_r+0xa5c> 8015952: 9820 ldr r0, [sp, #128] @ 0x80 8015954: 4301 orrs r1, r0 8015956: 9809 ldr r0, [sp, #36] @ 0x24 8015958: 4301 orrs r1, r0 801595a: d120 bne.n 801599e <_dtoa_r+0xa9e> 801595c: 2a00 cmp r2, #0 801595e: ddee ble.n 801593e <_dtoa_r+0xa3e> 8015960: 2201 movs r2, #1 8015962: 9903 ldr r1, [sp, #12] 8015964: 4648 mov r0, r9 8015966: 9304 str r3, [sp, #16] 8015968: f000 fd5a bl 8016420 <__lshift> 801596c: 4621 mov r1, r4 801596e: 9003 str r0, [sp, #12] 8015970: f000 fdc2 bl 80164f8 <__mcmp> 8015974: 2800 cmp r0, #0 8015976: 9b04 ldr r3, [sp, #16] 8015978: dc02 bgt.n 8015980 <_dtoa_r+0xa80> 801597a: d1e0 bne.n 801593e <_dtoa_r+0xa3e> 801597c: 07da lsls r2, r3, #31 801597e: d5de bpl.n 801593e <_dtoa_r+0xa3e> 8015980: 2b39 cmp r3, #57 @ 0x39 8015982: d1da bne.n 801593a <_dtoa_r+0xa3a> 8015984: 2339 movs r3, #57 @ 0x39 8015986: f88b 3000 strb.w r3, [fp] 801598a: 4633 mov r3, r6 801598c: 461e mov r6, r3 801598e: f816 2c01 ldrb.w r2, [r6, #-1] 8015992: 3b01 subs r3, #1 8015994: 2a39 cmp r2, #57 @ 0x39 8015996: d04e beq.n 8015a36 <_dtoa_r+0xb36> 8015998: 3201 adds r2, #1 801599a: 701a strb r2, [r3, #0] 801599c: e501 b.n 80153a2 <_dtoa_r+0x4a2> 801599e: 2a00 cmp r2, #0 80159a0: dd03 ble.n 80159aa <_dtoa_r+0xaaa> 80159a2: 2b39 cmp r3, #57 @ 0x39 80159a4: d0ee beq.n 8015984 <_dtoa_r+0xa84> 80159a6: 3301 adds r3, #1 80159a8: e7c9 b.n 801593e <_dtoa_r+0xa3e> 80159aa: 9a04 ldr r2, [sp, #16] 80159ac: 990a ldr r1, [sp, #40] @ 0x28 80159ae: f802 3c01 strb.w r3, [r2, #-1] 80159b2: 428a cmp r2, r1 80159b4: d028 beq.n 8015a08 <_dtoa_r+0xb08> 80159b6: 2300 movs r3, #0 80159b8: 220a movs r2, #10 80159ba: 9903 ldr r1, [sp, #12] 80159bc: 4648 mov r0, r9 80159be: f000 fb8b bl 80160d8 <__multadd> 80159c2: 42af cmp r7, r5 80159c4: 9003 str r0, [sp, #12] 80159c6: f04f 0300 mov.w r3, #0 80159ca: f04f 020a mov.w r2, #10 80159ce: 4639 mov r1, r7 80159d0: 4648 mov r0, r9 80159d2: d107 bne.n 80159e4 <_dtoa_r+0xae4> 80159d4: f000 fb80 bl 80160d8 <__multadd> 80159d8: 4607 mov r7, r0 80159da: 4605 mov r5, r0 80159dc: 9b04 ldr r3, [sp, #16] 80159de: 3301 adds r3, #1 80159e0: 9304 str r3, [sp, #16] 80159e2: e777 b.n 80158d4 <_dtoa_r+0x9d4> 80159e4: f000 fb78 bl 80160d8 <__multadd> 80159e8: 4629 mov r1, r5 80159ea: 4607 mov r7, r0 80159ec: 2300 movs r3, #0 80159ee: 220a movs r2, #10 80159f0: 4648 mov r0, r9 80159f2: f000 fb71 bl 80160d8 <__multadd> 80159f6: 4605 mov r5, r0 80159f8: e7f0 b.n 80159dc <_dtoa_r+0xadc> 80159fa: f1bb 0f00 cmp.w fp, #0 80159fe: bfcc ite gt 8015a00: 465e movgt r6, fp 8015a02: 2601 movle r6, #1 8015a04: 2700 movs r7, #0 8015a06: 4456 add r6, sl 8015a08: 2201 movs r2, #1 8015a0a: 9903 ldr r1, [sp, #12] 8015a0c: 4648 mov r0, r9 8015a0e: 9304 str r3, [sp, #16] 8015a10: f000 fd06 bl 8016420 <__lshift> 8015a14: 4621 mov r1, r4 8015a16: 9003 str r0, [sp, #12] 8015a18: f000 fd6e bl 80164f8 <__mcmp> 8015a1c: 2800 cmp r0, #0 8015a1e: dcb4 bgt.n 801598a <_dtoa_r+0xa8a> 8015a20: d102 bne.n 8015a28 <_dtoa_r+0xb28> 8015a22: 9b04 ldr r3, [sp, #16] 8015a24: 07db lsls r3, r3, #31 8015a26: d4b0 bmi.n 801598a <_dtoa_r+0xa8a> 8015a28: 4633 mov r3, r6 8015a2a: 461e mov r6, r3 8015a2c: f813 2d01 ldrb.w r2, [r3, #-1]! 8015a30: 2a30 cmp r2, #48 @ 0x30 8015a32: d0fa beq.n 8015a2a <_dtoa_r+0xb2a> 8015a34: e4b5 b.n 80153a2 <_dtoa_r+0x4a2> 8015a36: 459a cmp sl, r3 8015a38: d1a8 bne.n 801598c <_dtoa_r+0xa8c> 8015a3a: 2331 movs r3, #49 @ 0x31 8015a3c: f108 0801 add.w r8, r8, #1 8015a40: f88a 3000 strb.w r3, [sl] 8015a44: e4ad b.n 80153a2 <_dtoa_r+0x4a2> 8015a46: 9b24 ldr r3, [sp, #144] @ 0x90 8015a48: f8df a058 ldr.w sl, [pc, #88] @ 8015aa4 <_dtoa_r+0xba4> 8015a4c: b11b cbz r3, 8015a56 <_dtoa_r+0xb56> 8015a4e: f10a 0308 add.w r3, sl, #8 8015a52: 9a24 ldr r2, [sp, #144] @ 0x90 8015a54: 6013 str r3, [r2, #0] 8015a56: 4650 mov r0, sl 8015a58: b017 add sp, #92 @ 0x5c 8015a5a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8015a5e: 9b20 ldr r3, [sp, #128] @ 0x80 8015a60: 2b01 cmp r3, #1 8015a62: f77f ae2e ble.w 80156c2 <_dtoa_r+0x7c2> 8015a66: 9b0e ldr r3, [sp, #56] @ 0x38 8015a68: 930a str r3, [sp, #40] @ 0x28 8015a6a: 2001 movs r0, #1 8015a6c: e64d b.n 801570a <_dtoa_r+0x80a> 8015a6e: f1bb 0f00 cmp.w fp, #0 8015a72: f77f aed9 ble.w 8015828 <_dtoa_r+0x928> 8015a76: 4656 mov r6, sl 8015a78: 4621 mov r1, r4 8015a7a: 9803 ldr r0, [sp, #12] 8015a7c: f7ff f9b6 bl 8014dec 8015a80: f100 0330 add.w r3, r0, #48 @ 0x30 8015a84: f806 3b01 strb.w r3, [r6], #1 8015a88: eba6 020a sub.w r2, r6, sl 8015a8c: 4593 cmp fp, r2 8015a8e: ddb4 ble.n 80159fa <_dtoa_r+0xafa> 8015a90: 2300 movs r3, #0 8015a92: 220a movs r2, #10 8015a94: 4648 mov r0, r9 8015a96: 9903 ldr r1, [sp, #12] 8015a98: f000 fb1e bl 80160d8 <__multadd> 8015a9c: 9003 str r0, [sp, #12] 8015a9e: e7eb b.n 8015a78 <_dtoa_r+0xb78> 8015aa0: 08017ab0 .word 0x08017ab0 8015aa4: 08017a34 .word 0x08017a34 08015aa8 <__ssputs_r>: 8015aa8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8015aac: 461f mov r7, r3 8015aae: 688e ldr r6, [r1, #8] 8015ab0: 4682 mov sl, r0 8015ab2: 42be cmp r6, r7 8015ab4: 460c mov r4, r1 8015ab6: 4690 mov r8, r2 8015ab8: 680b ldr r3, [r1, #0] 8015aba: d82d bhi.n 8015b18 <__ssputs_r+0x70> 8015abc: f9b1 200c ldrsh.w r2, [r1, #12] 8015ac0: f412 6f90 tst.w r2, #1152 @ 0x480 8015ac4: d026 beq.n 8015b14 <__ssputs_r+0x6c> 8015ac6: 6965 ldr r5, [r4, #20] 8015ac8: 6909 ldr r1, [r1, #16] 8015aca: eb05 0545 add.w r5, r5, r5, lsl #1 8015ace: eba3 0901 sub.w r9, r3, r1 8015ad2: eb05 75d5 add.w r5, r5, r5, lsr #31 8015ad6: 1c7b adds r3, r7, #1 8015ad8: 444b add r3, r9 8015ada: 106d asrs r5, r5, #1 8015adc: 429d cmp r5, r3 8015ade: bf38 it cc 8015ae0: 461d movcc r5, r3 8015ae2: 0553 lsls r3, r2, #21 8015ae4: d527 bpl.n 8015b36 <__ssputs_r+0x8e> 8015ae6: 4629 mov r1, r5 8015ae8: f000 f960 bl 8015dac <_malloc_r> 8015aec: 4606 mov r6, r0 8015aee: b360 cbz r0, 8015b4a <__ssputs_r+0xa2> 8015af0: 464a mov r2, r9 8015af2: 6921 ldr r1, [r4, #16] 8015af4: f7ff f94e bl 8014d94 8015af8: 89a3 ldrh r3, [r4, #12] 8015afa: f423 6390 bic.w r3, r3, #1152 @ 0x480 8015afe: f043 0380 orr.w r3, r3, #128 @ 0x80 8015b02: 81a3 strh r3, [r4, #12] 8015b04: 6126 str r6, [r4, #16] 8015b06: 444e add r6, r9 8015b08: 6026 str r6, [r4, #0] 8015b0a: 463e mov r6, r7 8015b0c: 6165 str r5, [r4, #20] 8015b0e: eba5 0509 sub.w r5, r5, r9 8015b12: 60a5 str r5, [r4, #8] 8015b14: 42be cmp r6, r7 8015b16: d900 bls.n 8015b1a <__ssputs_r+0x72> 8015b18: 463e mov r6, r7 8015b1a: 4632 mov r2, r6 8015b1c: 4641 mov r1, r8 8015b1e: 6820 ldr r0, [r4, #0] 8015b20: f000 fe76 bl 8016810 8015b24: 2000 movs r0, #0 8015b26: 68a3 ldr r3, [r4, #8] 8015b28: 1b9b subs r3, r3, r6 8015b2a: 60a3 str r3, [r4, #8] 8015b2c: 6823 ldr r3, [r4, #0] 8015b2e: 4433 add r3, r6 8015b30: 6023 str r3, [r4, #0] 8015b32: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8015b36: 462a mov r2, r5 8015b38: f000 fe3c bl 80167b4 <_realloc_r> 8015b3c: 4606 mov r6, r0 8015b3e: 2800 cmp r0, #0 8015b40: d1e0 bne.n 8015b04 <__ssputs_r+0x5c> 8015b42: 4650 mov r0, sl 8015b44: 6921 ldr r1, [r4, #16] 8015b46: f000 feef bl 8016928 <_free_r> 8015b4a: 230c movs r3, #12 8015b4c: f8ca 3000 str.w r3, [sl] 8015b50: 89a3 ldrh r3, [r4, #12] 8015b52: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015b56: f043 0340 orr.w r3, r3, #64 @ 0x40 8015b5a: 81a3 strh r3, [r4, #12] 8015b5c: e7e9 b.n 8015b32 <__ssputs_r+0x8a> ... 08015b60 <_svfiprintf_r>: 8015b60: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8015b64: 4698 mov r8, r3 8015b66: 898b ldrh r3, [r1, #12] 8015b68: 4607 mov r7, r0 8015b6a: 061b lsls r3, r3, #24 8015b6c: 460d mov r5, r1 8015b6e: 4614 mov r4, r2 8015b70: b09d sub sp, #116 @ 0x74 8015b72: d510 bpl.n 8015b96 <_svfiprintf_r+0x36> 8015b74: 690b ldr r3, [r1, #16] 8015b76: b973 cbnz r3, 8015b96 <_svfiprintf_r+0x36> 8015b78: 2140 movs r1, #64 @ 0x40 8015b7a: f000 f917 bl 8015dac <_malloc_r> 8015b7e: 6028 str r0, [r5, #0] 8015b80: 6128 str r0, [r5, #16] 8015b82: b930 cbnz r0, 8015b92 <_svfiprintf_r+0x32> 8015b84: 230c movs r3, #12 8015b86: 603b str r3, [r7, #0] 8015b88: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015b8c: b01d add sp, #116 @ 0x74 8015b8e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8015b92: 2340 movs r3, #64 @ 0x40 8015b94: 616b str r3, [r5, #20] 8015b96: 2300 movs r3, #0 8015b98: 9309 str r3, [sp, #36] @ 0x24 8015b9a: 2320 movs r3, #32 8015b9c: f88d 3029 strb.w r3, [sp, #41] @ 0x29 8015ba0: 2330 movs r3, #48 @ 0x30 8015ba2: f04f 0901 mov.w r9, #1 8015ba6: f8cd 800c str.w r8, [sp, #12] 8015baa: f8df 8198 ldr.w r8, [pc, #408] @ 8015d44 <_svfiprintf_r+0x1e4> 8015bae: f88d 302a strb.w r3, [sp, #42] @ 0x2a 8015bb2: 4623 mov r3, r4 8015bb4: 469a mov sl, r3 8015bb6: f813 2b01 ldrb.w r2, [r3], #1 8015bba: b10a cbz r2, 8015bc0 <_svfiprintf_r+0x60> 8015bbc: 2a25 cmp r2, #37 @ 0x25 8015bbe: d1f9 bne.n 8015bb4 <_svfiprintf_r+0x54> 8015bc0: ebba 0b04 subs.w fp, sl, r4 8015bc4: d00b beq.n 8015bde <_svfiprintf_r+0x7e> 8015bc6: 465b mov r3, fp 8015bc8: 4622 mov r2, r4 8015bca: 4629 mov r1, r5 8015bcc: 4638 mov r0, r7 8015bce: f7ff ff6b bl 8015aa8 <__ssputs_r> 8015bd2: 3001 adds r0, #1 8015bd4: f000 80a7 beq.w 8015d26 <_svfiprintf_r+0x1c6> 8015bd8: 9a09 ldr r2, [sp, #36] @ 0x24 8015bda: 445a add r2, fp 8015bdc: 9209 str r2, [sp, #36] @ 0x24 8015bde: f89a 3000 ldrb.w r3, [sl] 8015be2: 2b00 cmp r3, #0 8015be4: f000 809f beq.w 8015d26 <_svfiprintf_r+0x1c6> 8015be8: 2300 movs r3, #0 8015bea: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8015bee: e9cd 2305 strd r2, r3, [sp, #20] 8015bf2: f10a 0a01 add.w sl, sl, #1 8015bf6: 9304 str r3, [sp, #16] 8015bf8: 9307 str r3, [sp, #28] 8015bfa: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8015bfe: 931a str r3, [sp, #104] @ 0x68 8015c00: 4654 mov r4, sl 8015c02: 2205 movs r2, #5 8015c04: f814 1b01 ldrb.w r1, [r4], #1 8015c08: 484e ldr r0, [pc, #312] @ (8015d44 <_svfiprintf_r+0x1e4>) 8015c0a: f7ff f8b5 bl 8014d78 8015c0e: 9a04 ldr r2, [sp, #16] 8015c10: b9d8 cbnz r0, 8015c4a <_svfiprintf_r+0xea> 8015c12: 06d0 lsls r0, r2, #27 8015c14: bf44 itt mi 8015c16: 2320 movmi r3, #32 8015c18: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8015c1c: 0711 lsls r1, r2, #28 8015c1e: bf44 itt mi 8015c20: 232b movmi r3, #43 @ 0x2b 8015c22: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8015c26: f89a 3000 ldrb.w r3, [sl] 8015c2a: 2b2a cmp r3, #42 @ 0x2a 8015c2c: d015 beq.n 8015c5a <_svfiprintf_r+0xfa> 8015c2e: 4654 mov r4, sl 8015c30: 2000 movs r0, #0 8015c32: f04f 0c0a mov.w ip, #10 8015c36: 9a07 ldr r2, [sp, #28] 8015c38: 4621 mov r1, r4 8015c3a: f811 3b01 ldrb.w r3, [r1], #1 8015c3e: 3b30 subs r3, #48 @ 0x30 8015c40: 2b09 cmp r3, #9 8015c42: d94b bls.n 8015cdc <_svfiprintf_r+0x17c> 8015c44: b1b0 cbz r0, 8015c74 <_svfiprintf_r+0x114> 8015c46: 9207 str r2, [sp, #28] 8015c48: e014 b.n 8015c74 <_svfiprintf_r+0x114> 8015c4a: eba0 0308 sub.w r3, r0, r8 8015c4e: fa09 f303 lsl.w r3, r9, r3 8015c52: 4313 orrs r3, r2 8015c54: 46a2 mov sl, r4 8015c56: 9304 str r3, [sp, #16] 8015c58: e7d2 b.n 8015c00 <_svfiprintf_r+0xa0> 8015c5a: 9b03 ldr r3, [sp, #12] 8015c5c: 1d19 adds r1, r3, #4 8015c5e: 681b ldr r3, [r3, #0] 8015c60: 9103 str r1, [sp, #12] 8015c62: 2b00 cmp r3, #0 8015c64: bfbb ittet lt 8015c66: 425b neglt r3, r3 8015c68: f042 0202 orrlt.w r2, r2, #2 8015c6c: 9307 strge r3, [sp, #28] 8015c6e: 9307 strlt r3, [sp, #28] 8015c70: bfb8 it lt 8015c72: 9204 strlt r2, [sp, #16] 8015c74: 7823 ldrb r3, [r4, #0] 8015c76: 2b2e cmp r3, #46 @ 0x2e 8015c78: d10a bne.n 8015c90 <_svfiprintf_r+0x130> 8015c7a: 7863 ldrb r3, [r4, #1] 8015c7c: 2b2a cmp r3, #42 @ 0x2a 8015c7e: d132 bne.n 8015ce6 <_svfiprintf_r+0x186> 8015c80: 9b03 ldr r3, [sp, #12] 8015c82: 3402 adds r4, #2 8015c84: 1d1a adds r2, r3, #4 8015c86: 681b ldr r3, [r3, #0] 8015c88: 9203 str r2, [sp, #12] 8015c8a: ea43 73e3 orr.w r3, r3, r3, asr #31 8015c8e: 9305 str r3, [sp, #20] 8015c90: f8df a0b4 ldr.w sl, [pc, #180] @ 8015d48 <_svfiprintf_r+0x1e8> 8015c94: 2203 movs r2, #3 8015c96: 4650 mov r0, sl 8015c98: 7821 ldrb r1, [r4, #0] 8015c9a: f7ff f86d bl 8014d78 8015c9e: b138 cbz r0, 8015cb0 <_svfiprintf_r+0x150> 8015ca0: 2240 movs r2, #64 @ 0x40 8015ca2: 9b04 ldr r3, [sp, #16] 8015ca4: eba0 000a sub.w r0, r0, sl 8015ca8: 4082 lsls r2, r0 8015caa: 4313 orrs r3, r2 8015cac: 3401 adds r4, #1 8015cae: 9304 str r3, [sp, #16] 8015cb0: f814 1b01 ldrb.w r1, [r4], #1 8015cb4: 2206 movs r2, #6 8015cb6: 4825 ldr r0, [pc, #148] @ (8015d4c <_svfiprintf_r+0x1ec>) 8015cb8: f88d 1028 strb.w r1, [sp, #40] @ 0x28 8015cbc: f7ff f85c bl 8014d78 8015cc0: 2800 cmp r0, #0 8015cc2: d036 beq.n 8015d32 <_svfiprintf_r+0x1d2> 8015cc4: 4b22 ldr r3, [pc, #136] @ (8015d50 <_svfiprintf_r+0x1f0>) 8015cc6: bb1b cbnz r3, 8015d10 <_svfiprintf_r+0x1b0> 8015cc8: 9b03 ldr r3, [sp, #12] 8015cca: 3307 adds r3, #7 8015ccc: f023 0307 bic.w r3, r3, #7 8015cd0: 3308 adds r3, #8 8015cd2: 9303 str r3, [sp, #12] 8015cd4: 9b09 ldr r3, [sp, #36] @ 0x24 8015cd6: 4433 add r3, r6 8015cd8: 9309 str r3, [sp, #36] @ 0x24 8015cda: e76a b.n 8015bb2 <_svfiprintf_r+0x52> 8015cdc: 460c mov r4, r1 8015cde: 2001 movs r0, #1 8015ce0: fb0c 3202 mla r2, ip, r2, r3 8015ce4: e7a8 b.n 8015c38 <_svfiprintf_r+0xd8> 8015ce6: 2300 movs r3, #0 8015ce8: f04f 0c0a mov.w ip, #10 8015cec: 4619 mov r1, r3 8015cee: 3401 adds r4, #1 8015cf0: 9305 str r3, [sp, #20] 8015cf2: 4620 mov r0, r4 8015cf4: f810 2b01 ldrb.w r2, [r0], #1 8015cf8: 3a30 subs r2, #48 @ 0x30 8015cfa: 2a09 cmp r2, #9 8015cfc: d903 bls.n 8015d06 <_svfiprintf_r+0x1a6> 8015cfe: 2b00 cmp r3, #0 8015d00: d0c6 beq.n 8015c90 <_svfiprintf_r+0x130> 8015d02: 9105 str r1, [sp, #20] 8015d04: e7c4 b.n 8015c90 <_svfiprintf_r+0x130> 8015d06: 4604 mov r4, r0 8015d08: 2301 movs r3, #1 8015d0a: fb0c 2101 mla r1, ip, r1, r2 8015d0e: e7f0 b.n 8015cf2 <_svfiprintf_r+0x192> 8015d10: ab03 add r3, sp, #12 8015d12: 9300 str r3, [sp, #0] 8015d14: 462a mov r2, r5 8015d16: 4638 mov r0, r7 8015d18: 4b0e ldr r3, [pc, #56] @ (8015d54 <_svfiprintf_r+0x1f4>) 8015d1a: a904 add r1, sp, #16 8015d1c: f7fe fb38 bl 8014390 <_printf_float> 8015d20: 1c42 adds r2, r0, #1 8015d22: 4606 mov r6, r0 8015d24: d1d6 bne.n 8015cd4 <_svfiprintf_r+0x174> 8015d26: 89ab ldrh r3, [r5, #12] 8015d28: 065b lsls r3, r3, #25 8015d2a: f53f af2d bmi.w 8015b88 <_svfiprintf_r+0x28> 8015d2e: 9809 ldr r0, [sp, #36] @ 0x24 8015d30: e72c b.n 8015b8c <_svfiprintf_r+0x2c> 8015d32: ab03 add r3, sp, #12 8015d34: 9300 str r3, [sp, #0] 8015d36: 462a mov r2, r5 8015d38: 4638 mov r0, r7 8015d3a: 4b06 ldr r3, [pc, #24] @ (8015d54 <_svfiprintf_r+0x1f4>) 8015d3c: a904 add r1, sp, #16 8015d3e: f7fe fdc5 bl 80148cc <_printf_i> 8015d42: e7ed b.n 8015d20 <_svfiprintf_r+0x1c0> 8015d44: 08017ac1 .word 0x08017ac1 8015d48: 08017ac7 .word 0x08017ac7 8015d4c: 08017acb .word 0x08017acb 8015d50: 08014391 .word 0x08014391 8015d54: 08015aa9 .word 0x08015aa9 08015d58 : 8015d58: 4b02 ldr r3, [pc, #8] @ (8015d64 ) 8015d5a: 4601 mov r1, r0 8015d5c: 6818 ldr r0, [r3, #0] 8015d5e: f000 b825 b.w 8015dac <_malloc_r> 8015d62: bf00 nop 8015d64: 2000009c .word 0x2000009c 08015d68 : 8015d68: b570 push {r4, r5, r6, lr} 8015d6a: 4e0f ldr r6, [pc, #60] @ (8015da8 ) 8015d6c: 460c mov r4, r1 8015d6e: 6831 ldr r1, [r6, #0] 8015d70: 4605 mov r5, r0 8015d72: b911 cbnz r1, 8015d7a 8015d74: f000 fd8a bl 801688c <_sbrk_r> 8015d78: 6030 str r0, [r6, #0] 8015d7a: 4621 mov r1, r4 8015d7c: 4628 mov r0, r5 8015d7e: f000 fd85 bl 801688c <_sbrk_r> 8015d82: 1c43 adds r3, r0, #1 8015d84: d103 bne.n 8015d8e 8015d86: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff 8015d8a: 4620 mov r0, r4 8015d8c: bd70 pop {r4, r5, r6, pc} 8015d8e: 1cc4 adds r4, r0, #3 8015d90: f024 0403 bic.w r4, r4, #3 8015d94: 42a0 cmp r0, r4 8015d96: d0f8 beq.n 8015d8a 8015d98: 1a21 subs r1, r4, r0 8015d9a: 4628 mov r0, r5 8015d9c: f000 fd76 bl 801688c <_sbrk_r> 8015da0: 3001 adds r0, #1 8015da2: d1f2 bne.n 8015d8a 8015da4: e7ef b.n 8015d86 8015da6: bf00 nop 8015da8: 200015cc .word 0x200015cc 08015dac <_malloc_r>: 8015dac: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8015db0: 1ccd adds r5, r1, #3 8015db2: f025 0503 bic.w r5, r5, #3 8015db6: 3508 adds r5, #8 8015db8: 2d0c cmp r5, #12 8015dba: bf38 it cc 8015dbc: 250c movcc r5, #12 8015dbe: 2d00 cmp r5, #0 8015dc0: 4606 mov r6, r0 8015dc2: db01 blt.n 8015dc8 <_malloc_r+0x1c> 8015dc4: 42a9 cmp r1, r5 8015dc6: d904 bls.n 8015dd2 <_malloc_r+0x26> 8015dc8: 230c movs r3, #12 8015dca: 6033 str r3, [r6, #0] 8015dcc: 2000 movs r0, #0 8015dce: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8015dd2: f8df 80d4 ldr.w r8, [pc, #212] @ 8015ea8 <_malloc_r+0xfc> 8015dd6: f000 f911 bl 8015ffc <__malloc_lock> 8015dda: f8d8 3000 ldr.w r3, [r8] 8015dde: 461c mov r4, r3 8015de0: bb44 cbnz r4, 8015e34 <_malloc_r+0x88> 8015de2: 4629 mov r1, r5 8015de4: 4630 mov r0, r6 8015de6: f7ff ffbf bl 8015d68 8015dea: 1c43 adds r3, r0, #1 8015dec: 4604 mov r4, r0 8015dee: d158 bne.n 8015ea2 <_malloc_r+0xf6> 8015df0: f8d8 4000 ldr.w r4, [r8] 8015df4: 4627 mov r7, r4 8015df6: 2f00 cmp r7, #0 8015df8: d143 bne.n 8015e82 <_malloc_r+0xd6> 8015dfa: 2c00 cmp r4, #0 8015dfc: d04b beq.n 8015e96 <_malloc_r+0xea> 8015dfe: 6823 ldr r3, [r4, #0] 8015e00: 4639 mov r1, r7 8015e02: 4630 mov r0, r6 8015e04: eb04 0903 add.w r9, r4, r3 8015e08: f000 fd40 bl 801688c <_sbrk_r> 8015e0c: 4581 cmp r9, r0 8015e0e: d142 bne.n 8015e96 <_malloc_r+0xea> 8015e10: 6821 ldr r1, [r4, #0] 8015e12: 4630 mov r0, r6 8015e14: 1a6d subs r5, r5, r1 8015e16: 4629 mov r1, r5 8015e18: f7ff ffa6 bl 8015d68 8015e1c: 3001 adds r0, #1 8015e1e: d03a beq.n 8015e96 <_malloc_r+0xea> 8015e20: 6823 ldr r3, [r4, #0] 8015e22: 442b add r3, r5 8015e24: 6023 str r3, [r4, #0] 8015e26: f8d8 3000 ldr.w r3, [r8] 8015e2a: 685a ldr r2, [r3, #4] 8015e2c: bb62 cbnz r2, 8015e88 <_malloc_r+0xdc> 8015e2e: f8c8 7000 str.w r7, [r8] 8015e32: e00f b.n 8015e54 <_malloc_r+0xa8> 8015e34: 6822 ldr r2, [r4, #0] 8015e36: 1b52 subs r2, r2, r5 8015e38: d420 bmi.n 8015e7c <_malloc_r+0xd0> 8015e3a: 2a0b cmp r2, #11 8015e3c: d917 bls.n 8015e6e <_malloc_r+0xc2> 8015e3e: 1961 adds r1, r4, r5 8015e40: 42a3 cmp r3, r4 8015e42: 6025 str r5, [r4, #0] 8015e44: bf18 it ne 8015e46: 6059 strne r1, [r3, #4] 8015e48: 6863 ldr r3, [r4, #4] 8015e4a: bf08 it eq 8015e4c: f8c8 1000 streq.w r1, [r8] 8015e50: 5162 str r2, [r4, r5] 8015e52: 604b str r3, [r1, #4] 8015e54: 4630 mov r0, r6 8015e56: f000 f8d7 bl 8016008 <__malloc_unlock> 8015e5a: f104 000b add.w r0, r4, #11 8015e5e: 1d23 adds r3, r4, #4 8015e60: f020 0007 bic.w r0, r0, #7 8015e64: 1ac2 subs r2, r0, r3 8015e66: bf1c itt ne 8015e68: 1a1b subne r3, r3, r0 8015e6a: 50a3 strne r3, [r4, r2] 8015e6c: e7af b.n 8015dce <_malloc_r+0x22> 8015e6e: 6862 ldr r2, [r4, #4] 8015e70: 42a3 cmp r3, r4 8015e72: bf0c ite eq 8015e74: f8c8 2000 streq.w r2, [r8] 8015e78: 605a strne r2, [r3, #4] 8015e7a: e7eb b.n 8015e54 <_malloc_r+0xa8> 8015e7c: 4623 mov r3, r4 8015e7e: 6864 ldr r4, [r4, #4] 8015e80: e7ae b.n 8015de0 <_malloc_r+0x34> 8015e82: 463c mov r4, r7 8015e84: 687f ldr r7, [r7, #4] 8015e86: e7b6 b.n 8015df6 <_malloc_r+0x4a> 8015e88: 461a mov r2, r3 8015e8a: 685b ldr r3, [r3, #4] 8015e8c: 42a3 cmp r3, r4 8015e8e: d1fb bne.n 8015e88 <_malloc_r+0xdc> 8015e90: 2300 movs r3, #0 8015e92: 6053 str r3, [r2, #4] 8015e94: e7de b.n 8015e54 <_malloc_r+0xa8> 8015e96: 230c movs r3, #12 8015e98: 4630 mov r0, r6 8015e9a: 6033 str r3, [r6, #0] 8015e9c: f000 f8b4 bl 8016008 <__malloc_unlock> 8015ea0: e794 b.n 8015dcc <_malloc_r+0x20> 8015ea2: 6005 str r5, [r0, #0] 8015ea4: e7d6 b.n 8015e54 <_malloc_r+0xa8> 8015ea6: bf00 nop 8015ea8: 200015d0 .word 0x200015d0 08015eac <__sflush_r>: 8015eac: f9b1 200c ldrsh.w r2, [r1, #12] 8015eb0: b5f8 push {r3, r4, r5, r6, r7, lr} 8015eb2: 0716 lsls r6, r2, #28 8015eb4: 4605 mov r5, r0 8015eb6: 460c mov r4, r1 8015eb8: d454 bmi.n 8015f64 <__sflush_r+0xb8> 8015eba: 684b ldr r3, [r1, #4] 8015ebc: 2b00 cmp r3, #0 8015ebe: dc02 bgt.n 8015ec6 <__sflush_r+0x1a> 8015ec0: 6c0b ldr r3, [r1, #64] @ 0x40 8015ec2: 2b00 cmp r3, #0 8015ec4: dd48 ble.n 8015f58 <__sflush_r+0xac> 8015ec6: 6ae6 ldr r6, [r4, #44] @ 0x2c 8015ec8: 2e00 cmp r6, #0 8015eca: d045 beq.n 8015f58 <__sflush_r+0xac> 8015ecc: 2300 movs r3, #0 8015ece: f412 5280 ands.w r2, r2, #4096 @ 0x1000 8015ed2: 682f ldr r7, [r5, #0] 8015ed4: 6a21 ldr r1, [r4, #32] 8015ed6: 602b str r3, [r5, #0] 8015ed8: d030 beq.n 8015f3c <__sflush_r+0x90> 8015eda: 6d62 ldr r2, [r4, #84] @ 0x54 8015edc: 89a3 ldrh r3, [r4, #12] 8015ede: 0759 lsls r1, r3, #29 8015ee0: d505 bpl.n 8015eee <__sflush_r+0x42> 8015ee2: 6863 ldr r3, [r4, #4] 8015ee4: 1ad2 subs r2, r2, r3 8015ee6: 6b63 ldr r3, [r4, #52] @ 0x34 8015ee8: b10b cbz r3, 8015eee <__sflush_r+0x42> 8015eea: 6c23 ldr r3, [r4, #64] @ 0x40 8015eec: 1ad2 subs r2, r2, r3 8015eee: 2300 movs r3, #0 8015ef0: 4628 mov r0, r5 8015ef2: 6ae6 ldr r6, [r4, #44] @ 0x2c 8015ef4: 6a21 ldr r1, [r4, #32] 8015ef6: 47b0 blx r6 8015ef8: 1c43 adds r3, r0, #1 8015efa: 89a3 ldrh r3, [r4, #12] 8015efc: d106 bne.n 8015f0c <__sflush_r+0x60> 8015efe: 6829 ldr r1, [r5, #0] 8015f00: 291d cmp r1, #29 8015f02: d82b bhi.n 8015f5c <__sflush_r+0xb0> 8015f04: 4a28 ldr r2, [pc, #160] @ (8015fa8 <__sflush_r+0xfc>) 8015f06: 40ca lsrs r2, r1 8015f08: 07d6 lsls r6, r2, #31 8015f0a: d527 bpl.n 8015f5c <__sflush_r+0xb0> 8015f0c: 2200 movs r2, #0 8015f0e: 6062 str r2, [r4, #4] 8015f10: 6922 ldr r2, [r4, #16] 8015f12: 04d9 lsls r1, r3, #19 8015f14: 6022 str r2, [r4, #0] 8015f16: d504 bpl.n 8015f22 <__sflush_r+0x76> 8015f18: 1c42 adds r2, r0, #1 8015f1a: d101 bne.n 8015f20 <__sflush_r+0x74> 8015f1c: 682b ldr r3, [r5, #0] 8015f1e: b903 cbnz r3, 8015f22 <__sflush_r+0x76> 8015f20: 6560 str r0, [r4, #84] @ 0x54 8015f22: 6b61 ldr r1, [r4, #52] @ 0x34 8015f24: 602f str r7, [r5, #0] 8015f26: b1b9 cbz r1, 8015f58 <__sflush_r+0xac> 8015f28: f104 0344 add.w r3, r4, #68 @ 0x44 8015f2c: 4299 cmp r1, r3 8015f2e: d002 beq.n 8015f36 <__sflush_r+0x8a> 8015f30: 4628 mov r0, r5 8015f32: f000 fcf9 bl 8016928 <_free_r> 8015f36: 2300 movs r3, #0 8015f38: 6363 str r3, [r4, #52] @ 0x34 8015f3a: e00d b.n 8015f58 <__sflush_r+0xac> 8015f3c: 2301 movs r3, #1 8015f3e: 4628 mov r0, r5 8015f40: 47b0 blx r6 8015f42: 4602 mov r2, r0 8015f44: 1c50 adds r0, r2, #1 8015f46: d1c9 bne.n 8015edc <__sflush_r+0x30> 8015f48: 682b ldr r3, [r5, #0] 8015f4a: 2b00 cmp r3, #0 8015f4c: d0c6 beq.n 8015edc <__sflush_r+0x30> 8015f4e: 2b1d cmp r3, #29 8015f50: d001 beq.n 8015f56 <__sflush_r+0xaa> 8015f52: 2b16 cmp r3, #22 8015f54: d11d bne.n 8015f92 <__sflush_r+0xe6> 8015f56: 602f str r7, [r5, #0] 8015f58: 2000 movs r0, #0 8015f5a: e021 b.n 8015fa0 <__sflush_r+0xf4> 8015f5c: f043 0340 orr.w r3, r3, #64 @ 0x40 8015f60: b21b sxth r3, r3 8015f62: e01a b.n 8015f9a <__sflush_r+0xee> 8015f64: 690f ldr r7, [r1, #16] 8015f66: 2f00 cmp r7, #0 8015f68: d0f6 beq.n 8015f58 <__sflush_r+0xac> 8015f6a: 0793 lsls r3, r2, #30 8015f6c: bf18 it ne 8015f6e: 2300 movne r3, #0 8015f70: 680e ldr r6, [r1, #0] 8015f72: bf08 it eq 8015f74: 694b ldreq r3, [r1, #20] 8015f76: 1bf6 subs r6, r6, r7 8015f78: 600f str r7, [r1, #0] 8015f7a: 608b str r3, [r1, #8] 8015f7c: 2e00 cmp r6, #0 8015f7e: ddeb ble.n 8015f58 <__sflush_r+0xac> 8015f80: 4633 mov r3, r6 8015f82: 463a mov r2, r7 8015f84: 4628 mov r0, r5 8015f86: 6a21 ldr r1, [r4, #32] 8015f88: f8d4 c028 ldr.w ip, [r4, #40] @ 0x28 8015f8c: 47e0 blx ip 8015f8e: 2800 cmp r0, #0 8015f90: dc07 bgt.n 8015fa2 <__sflush_r+0xf6> 8015f92: f9b4 300c ldrsh.w r3, [r4, #12] 8015f96: f043 0340 orr.w r3, r3, #64 @ 0x40 8015f9a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8015f9e: 81a3 strh r3, [r4, #12] 8015fa0: bdf8 pop {r3, r4, r5, r6, r7, pc} 8015fa2: 4407 add r7, r0 8015fa4: 1a36 subs r6, r6, r0 8015fa6: e7e9 b.n 8015f7c <__sflush_r+0xd0> 8015fa8: 20400001 .word 0x20400001 08015fac <_fflush_r>: 8015fac: b538 push {r3, r4, r5, lr} 8015fae: 690b ldr r3, [r1, #16] 8015fb0: 4605 mov r5, r0 8015fb2: 460c mov r4, r1 8015fb4: b913 cbnz r3, 8015fbc <_fflush_r+0x10> 8015fb6: 2500 movs r5, #0 8015fb8: 4628 mov r0, r5 8015fba: bd38 pop {r3, r4, r5, pc} 8015fbc: b118 cbz r0, 8015fc6 <_fflush_r+0x1a> 8015fbe: 6a03 ldr r3, [r0, #32] 8015fc0: b90b cbnz r3, 8015fc6 <_fflush_r+0x1a> 8015fc2: f7fe fe2d bl 8014c20 <__sinit> 8015fc6: f9b4 300c ldrsh.w r3, [r4, #12] 8015fca: 2b00 cmp r3, #0 8015fcc: d0f3 beq.n 8015fb6 <_fflush_r+0xa> 8015fce: 6e62 ldr r2, [r4, #100] @ 0x64 8015fd0: 07d0 lsls r0, r2, #31 8015fd2: d404 bmi.n 8015fde <_fflush_r+0x32> 8015fd4: 0599 lsls r1, r3, #22 8015fd6: d402 bmi.n 8015fde <_fflush_r+0x32> 8015fd8: 6da0 ldr r0, [r4, #88] @ 0x58 8015fda: f7fe fec6 bl 8014d6a <__retarget_lock_acquire_recursive> 8015fde: 4628 mov r0, r5 8015fe0: 4621 mov r1, r4 8015fe2: f7ff ff63 bl 8015eac <__sflush_r> 8015fe6: 6e63 ldr r3, [r4, #100] @ 0x64 8015fe8: 4605 mov r5, r0 8015fea: 07da lsls r2, r3, #31 8015fec: d4e4 bmi.n 8015fb8 <_fflush_r+0xc> 8015fee: 89a3 ldrh r3, [r4, #12] 8015ff0: 059b lsls r3, r3, #22 8015ff2: d4e1 bmi.n 8015fb8 <_fflush_r+0xc> 8015ff4: 6da0 ldr r0, [r4, #88] @ 0x58 8015ff6: f7fe feb9 bl 8014d6c <__retarget_lock_release_recursive> 8015ffa: e7dd b.n 8015fb8 <_fflush_r+0xc> 08015ffc <__malloc_lock>: 8015ffc: 4801 ldr r0, [pc, #4] @ (8016004 <__malloc_lock+0x8>) 8015ffe: f7fe beb4 b.w 8014d6a <__retarget_lock_acquire_recursive> 8016002: bf00 nop 8016004: 200015c8 .word 0x200015c8 08016008 <__malloc_unlock>: 8016008: 4801 ldr r0, [pc, #4] @ (8016010 <__malloc_unlock+0x8>) 801600a: f7fe beaf b.w 8014d6c <__retarget_lock_release_recursive> 801600e: bf00 nop 8016010: 200015c8 .word 0x200015c8 08016014 <_Balloc>: 8016014: b570 push {r4, r5, r6, lr} 8016016: 69c6 ldr r6, [r0, #28] 8016018: 4604 mov r4, r0 801601a: 460d mov r5, r1 801601c: b976 cbnz r6, 801603c <_Balloc+0x28> 801601e: 2010 movs r0, #16 8016020: f7ff fe9a bl 8015d58 8016024: 4602 mov r2, r0 8016026: 61e0 str r0, [r4, #28] 8016028: b920 cbnz r0, 8016034 <_Balloc+0x20> 801602a: 216b movs r1, #107 @ 0x6b 801602c: 4b17 ldr r3, [pc, #92] @ (801608c <_Balloc+0x78>) 801602e: 4818 ldr r0, [pc, #96] @ (8016090 <_Balloc+0x7c>) 8016030: f7fe febe bl 8014db0 <__assert_func> 8016034: e9c0 6601 strd r6, r6, [r0, #4] 8016038: 6006 str r6, [r0, #0] 801603a: 60c6 str r6, [r0, #12] 801603c: 69e6 ldr r6, [r4, #28] 801603e: 68f3 ldr r3, [r6, #12] 8016040: b183 cbz r3, 8016064 <_Balloc+0x50> 8016042: 69e3 ldr r3, [r4, #28] 8016044: 68db ldr r3, [r3, #12] 8016046: f853 0025 ldr.w r0, [r3, r5, lsl #2] 801604a: b9b8 cbnz r0, 801607c <_Balloc+0x68> 801604c: 2101 movs r1, #1 801604e: fa01 f605 lsl.w r6, r1, r5 8016052: 1d72 adds r2, r6, #5 8016054: 4620 mov r0, r4 8016056: 0092 lsls r2, r2, #2 8016058: f000 fc51 bl 80168fe <_calloc_r> 801605c: b160 cbz r0, 8016078 <_Balloc+0x64> 801605e: e9c0 5601 strd r5, r6, [r0, #4] 8016062: e00e b.n 8016082 <_Balloc+0x6e> 8016064: 2221 movs r2, #33 @ 0x21 8016066: 2104 movs r1, #4 8016068: 4620 mov r0, r4 801606a: f000 fc48 bl 80168fe <_calloc_r> 801606e: 69e3 ldr r3, [r4, #28] 8016070: 60f0 str r0, [r6, #12] 8016072: 68db ldr r3, [r3, #12] 8016074: 2b00 cmp r3, #0 8016076: d1e4 bne.n 8016042 <_Balloc+0x2e> 8016078: 2000 movs r0, #0 801607a: bd70 pop {r4, r5, r6, pc} 801607c: 6802 ldr r2, [r0, #0] 801607e: f843 2025 str.w r2, [r3, r5, lsl #2] 8016082: 2300 movs r3, #0 8016084: e9c0 3303 strd r3, r3, [r0, #12] 8016088: e7f7 b.n 801607a <_Balloc+0x66> 801608a: bf00 nop 801608c: 08017a41 .word 0x08017a41 8016090: 08017ad2 .word 0x08017ad2 08016094 <_Bfree>: 8016094: b570 push {r4, r5, r6, lr} 8016096: 69c6 ldr r6, [r0, #28] 8016098: 4605 mov r5, r0 801609a: 460c mov r4, r1 801609c: b976 cbnz r6, 80160bc <_Bfree+0x28> 801609e: 2010 movs r0, #16 80160a0: f7ff fe5a bl 8015d58 80160a4: 4602 mov r2, r0 80160a6: 61e8 str r0, [r5, #28] 80160a8: b920 cbnz r0, 80160b4 <_Bfree+0x20> 80160aa: 218f movs r1, #143 @ 0x8f 80160ac: 4b08 ldr r3, [pc, #32] @ (80160d0 <_Bfree+0x3c>) 80160ae: 4809 ldr r0, [pc, #36] @ (80160d4 <_Bfree+0x40>) 80160b0: f7fe fe7e bl 8014db0 <__assert_func> 80160b4: e9c0 6601 strd r6, r6, [r0, #4] 80160b8: 6006 str r6, [r0, #0] 80160ba: 60c6 str r6, [r0, #12] 80160bc: b13c cbz r4, 80160ce <_Bfree+0x3a> 80160be: 69eb ldr r3, [r5, #28] 80160c0: 6862 ldr r2, [r4, #4] 80160c2: 68db ldr r3, [r3, #12] 80160c4: f853 1022 ldr.w r1, [r3, r2, lsl #2] 80160c8: 6021 str r1, [r4, #0] 80160ca: f843 4022 str.w r4, [r3, r2, lsl #2] 80160ce: bd70 pop {r4, r5, r6, pc} 80160d0: 08017a41 .word 0x08017a41 80160d4: 08017ad2 .word 0x08017ad2 080160d8 <__multadd>: 80160d8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80160dc: 4607 mov r7, r0 80160de: 460c mov r4, r1 80160e0: 461e mov r6, r3 80160e2: 2000 movs r0, #0 80160e4: 690d ldr r5, [r1, #16] 80160e6: f101 0c14 add.w ip, r1, #20 80160ea: f8dc 3000 ldr.w r3, [ip] 80160ee: 3001 adds r0, #1 80160f0: b299 uxth r1, r3 80160f2: fb02 6101 mla r1, r2, r1, r6 80160f6: 0c1e lsrs r6, r3, #16 80160f8: 0c0b lsrs r3, r1, #16 80160fa: fb02 3306 mla r3, r2, r6, r3 80160fe: b289 uxth r1, r1 8016100: eb01 4103 add.w r1, r1, r3, lsl #16 8016104: 4285 cmp r5, r0 8016106: ea4f 4613 mov.w r6, r3, lsr #16 801610a: f84c 1b04 str.w r1, [ip], #4 801610e: dcec bgt.n 80160ea <__multadd+0x12> 8016110: b30e cbz r6, 8016156 <__multadd+0x7e> 8016112: 68a3 ldr r3, [r4, #8] 8016114: 42ab cmp r3, r5 8016116: dc19 bgt.n 801614c <__multadd+0x74> 8016118: 6861 ldr r1, [r4, #4] 801611a: 4638 mov r0, r7 801611c: 3101 adds r1, #1 801611e: f7ff ff79 bl 8016014 <_Balloc> 8016122: 4680 mov r8, r0 8016124: b928 cbnz r0, 8016132 <__multadd+0x5a> 8016126: 4602 mov r2, r0 8016128: 21ba movs r1, #186 @ 0xba 801612a: 4b0c ldr r3, [pc, #48] @ (801615c <__multadd+0x84>) 801612c: 480c ldr r0, [pc, #48] @ (8016160 <__multadd+0x88>) 801612e: f7fe fe3f bl 8014db0 <__assert_func> 8016132: 6922 ldr r2, [r4, #16] 8016134: f104 010c add.w r1, r4, #12 8016138: 3202 adds r2, #2 801613a: 0092 lsls r2, r2, #2 801613c: 300c adds r0, #12 801613e: f7fe fe29 bl 8014d94 8016142: 4621 mov r1, r4 8016144: 4638 mov r0, r7 8016146: f7ff ffa5 bl 8016094 <_Bfree> 801614a: 4644 mov r4, r8 801614c: eb04 0385 add.w r3, r4, r5, lsl #2 8016150: 3501 adds r5, #1 8016152: 615e str r6, [r3, #20] 8016154: 6125 str r5, [r4, #16] 8016156: 4620 mov r0, r4 8016158: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 801615c: 08017ab0 .word 0x08017ab0 8016160: 08017ad2 .word 0x08017ad2 08016164 <__hi0bits>: 8016164: 4603 mov r3, r0 8016166: f5b0 3f80 cmp.w r0, #65536 @ 0x10000 801616a: bf3a itte cc 801616c: 0403 lslcc r3, r0, #16 801616e: 2010 movcc r0, #16 8016170: 2000 movcs r0, #0 8016172: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8016176: bf3c itt cc 8016178: 021b lslcc r3, r3, #8 801617a: 3008 addcc r0, #8 801617c: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8016180: bf3c itt cc 8016182: 011b lslcc r3, r3, #4 8016184: 3004 addcc r0, #4 8016186: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 801618a: bf3c itt cc 801618c: 009b lslcc r3, r3, #2 801618e: 3002 addcc r0, #2 8016190: 2b00 cmp r3, #0 8016192: db05 blt.n 80161a0 <__hi0bits+0x3c> 8016194: f013 4f80 tst.w r3, #1073741824 @ 0x40000000 8016198: f100 0001 add.w r0, r0, #1 801619c: bf08 it eq 801619e: 2020 moveq r0, #32 80161a0: 4770 bx lr 080161a2 <__lo0bits>: 80161a2: 6803 ldr r3, [r0, #0] 80161a4: 4602 mov r2, r0 80161a6: f013 0007 ands.w r0, r3, #7 80161aa: d00b beq.n 80161c4 <__lo0bits+0x22> 80161ac: 07d9 lsls r1, r3, #31 80161ae: d421 bmi.n 80161f4 <__lo0bits+0x52> 80161b0: 0798 lsls r0, r3, #30 80161b2: bf49 itett mi 80161b4: 085b lsrmi r3, r3, #1 80161b6: 089b lsrpl r3, r3, #2 80161b8: 2001 movmi r0, #1 80161ba: 6013 strmi r3, [r2, #0] 80161bc: bf5c itt pl 80161be: 2002 movpl r0, #2 80161c0: 6013 strpl r3, [r2, #0] 80161c2: 4770 bx lr 80161c4: b299 uxth r1, r3 80161c6: b909 cbnz r1, 80161cc <__lo0bits+0x2a> 80161c8: 2010 movs r0, #16 80161ca: 0c1b lsrs r3, r3, #16 80161cc: b2d9 uxtb r1, r3 80161ce: b909 cbnz r1, 80161d4 <__lo0bits+0x32> 80161d0: 3008 adds r0, #8 80161d2: 0a1b lsrs r3, r3, #8 80161d4: 0719 lsls r1, r3, #28 80161d6: bf04 itt eq 80161d8: 091b lsreq r3, r3, #4 80161da: 3004 addeq r0, #4 80161dc: 0799 lsls r1, r3, #30 80161de: bf04 itt eq 80161e0: 089b lsreq r3, r3, #2 80161e2: 3002 addeq r0, #2 80161e4: 07d9 lsls r1, r3, #31 80161e6: d403 bmi.n 80161f0 <__lo0bits+0x4e> 80161e8: 085b lsrs r3, r3, #1 80161ea: f100 0001 add.w r0, r0, #1 80161ee: d003 beq.n 80161f8 <__lo0bits+0x56> 80161f0: 6013 str r3, [r2, #0] 80161f2: 4770 bx lr 80161f4: 2000 movs r0, #0 80161f6: 4770 bx lr 80161f8: 2020 movs r0, #32 80161fa: 4770 bx lr 080161fc <__i2b>: 80161fc: b510 push {r4, lr} 80161fe: 460c mov r4, r1 8016200: 2101 movs r1, #1 8016202: f7ff ff07 bl 8016014 <_Balloc> 8016206: 4602 mov r2, r0 8016208: b928 cbnz r0, 8016216 <__i2b+0x1a> 801620a: f240 1145 movw r1, #325 @ 0x145 801620e: 4b04 ldr r3, [pc, #16] @ (8016220 <__i2b+0x24>) 8016210: 4804 ldr r0, [pc, #16] @ (8016224 <__i2b+0x28>) 8016212: f7fe fdcd bl 8014db0 <__assert_func> 8016216: 2301 movs r3, #1 8016218: 6144 str r4, [r0, #20] 801621a: 6103 str r3, [r0, #16] 801621c: bd10 pop {r4, pc} 801621e: bf00 nop 8016220: 08017ab0 .word 0x08017ab0 8016224: 08017ad2 .word 0x08017ad2 08016228 <__multiply>: 8016228: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801622c: 4617 mov r7, r2 801622e: 690a ldr r2, [r1, #16] 8016230: 693b ldr r3, [r7, #16] 8016232: 4689 mov r9, r1 8016234: 429a cmp r2, r3 8016236: bfa2 ittt ge 8016238: 463b movge r3, r7 801623a: 460f movge r7, r1 801623c: 4699 movge r9, r3 801623e: 693d ldr r5, [r7, #16] 8016240: f8d9 a010 ldr.w sl, [r9, #16] 8016244: 68bb ldr r3, [r7, #8] 8016246: 6879 ldr r1, [r7, #4] 8016248: eb05 060a add.w r6, r5, sl 801624c: 42b3 cmp r3, r6 801624e: b085 sub sp, #20 8016250: bfb8 it lt 8016252: 3101 addlt r1, #1 8016254: f7ff fede bl 8016014 <_Balloc> 8016258: b930 cbnz r0, 8016268 <__multiply+0x40> 801625a: 4602 mov r2, r0 801625c: f44f 71b1 mov.w r1, #354 @ 0x162 8016260: 4b40 ldr r3, [pc, #256] @ (8016364 <__multiply+0x13c>) 8016262: 4841 ldr r0, [pc, #260] @ (8016368 <__multiply+0x140>) 8016264: f7fe fda4 bl 8014db0 <__assert_func> 8016268: f100 0414 add.w r4, r0, #20 801626c: 4623 mov r3, r4 801626e: 2200 movs r2, #0 8016270: eb04 0e86 add.w lr, r4, r6, lsl #2 8016274: 4573 cmp r3, lr 8016276: d320 bcc.n 80162ba <__multiply+0x92> 8016278: f107 0814 add.w r8, r7, #20 801627c: f109 0114 add.w r1, r9, #20 8016280: eb08 0585 add.w r5, r8, r5, lsl #2 8016284: eb01 038a add.w r3, r1, sl, lsl #2 8016288: 9302 str r3, [sp, #8] 801628a: 1beb subs r3, r5, r7 801628c: 3b15 subs r3, #21 801628e: f023 0303 bic.w r3, r3, #3 8016292: 3304 adds r3, #4 8016294: 3715 adds r7, #21 8016296: 42bd cmp r5, r7 8016298: bf38 it cc 801629a: 2304 movcc r3, #4 801629c: 9301 str r3, [sp, #4] 801629e: 9b02 ldr r3, [sp, #8] 80162a0: 9103 str r1, [sp, #12] 80162a2: 428b cmp r3, r1 80162a4: d80c bhi.n 80162c0 <__multiply+0x98> 80162a6: 2e00 cmp r6, #0 80162a8: dd03 ble.n 80162b2 <__multiply+0x8a> 80162aa: f85e 3d04 ldr.w r3, [lr, #-4]! 80162ae: 2b00 cmp r3, #0 80162b0: d055 beq.n 801635e <__multiply+0x136> 80162b2: 6106 str r6, [r0, #16] 80162b4: b005 add sp, #20 80162b6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80162ba: f843 2b04 str.w r2, [r3], #4 80162be: e7d9 b.n 8016274 <__multiply+0x4c> 80162c0: f8b1 a000 ldrh.w sl, [r1] 80162c4: f1ba 0f00 cmp.w sl, #0 80162c8: d01f beq.n 801630a <__multiply+0xe2> 80162ca: 46c4 mov ip, r8 80162cc: 46a1 mov r9, r4 80162ce: 2700 movs r7, #0 80162d0: f85c 2b04 ldr.w r2, [ip], #4 80162d4: f8d9 3000 ldr.w r3, [r9] 80162d8: fa1f fb82 uxth.w fp, r2 80162dc: b29b uxth r3, r3 80162de: fb0a 330b mla r3, sl, fp, r3 80162e2: 443b add r3, r7 80162e4: f8d9 7000 ldr.w r7, [r9] 80162e8: 0c12 lsrs r2, r2, #16 80162ea: 0c3f lsrs r7, r7, #16 80162ec: fb0a 7202 mla r2, sl, r2, r7 80162f0: eb02 4213 add.w r2, r2, r3, lsr #16 80162f4: b29b uxth r3, r3 80162f6: ea43 4302 orr.w r3, r3, r2, lsl #16 80162fa: 4565 cmp r5, ip 80162fc: ea4f 4712 mov.w r7, r2, lsr #16 8016300: f849 3b04 str.w r3, [r9], #4 8016304: d8e4 bhi.n 80162d0 <__multiply+0xa8> 8016306: 9b01 ldr r3, [sp, #4] 8016308: 50e7 str r7, [r4, r3] 801630a: 9b03 ldr r3, [sp, #12] 801630c: 3104 adds r1, #4 801630e: f8b3 9002 ldrh.w r9, [r3, #2] 8016312: f1b9 0f00 cmp.w r9, #0 8016316: d020 beq.n 801635a <__multiply+0x132> 8016318: 4647 mov r7, r8 801631a: 46a4 mov ip, r4 801631c: f04f 0a00 mov.w sl, #0 8016320: 6823 ldr r3, [r4, #0] 8016322: f8b7 b000 ldrh.w fp, [r7] 8016326: f8bc 2002 ldrh.w r2, [ip, #2] 801632a: b29b uxth r3, r3 801632c: fb09 220b mla r2, r9, fp, r2 8016330: 4452 add r2, sl 8016332: ea43 4302 orr.w r3, r3, r2, lsl #16 8016336: f84c 3b04 str.w r3, [ip], #4 801633a: f857 3b04 ldr.w r3, [r7], #4 801633e: ea4f 4a13 mov.w sl, r3, lsr #16 8016342: f8bc 3000 ldrh.w r3, [ip] 8016346: 42bd cmp r5, r7 8016348: fb09 330a mla r3, r9, sl, r3 801634c: eb03 4312 add.w r3, r3, r2, lsr #16 8016350: ea4f 4a13 mov.w sl, r3, lsr #16 8016354: d8e5 bhi.n 8016322 <__multiply+0xfa> 8016356: 9a01 ldr r2, [sp, #4] 8016358: 50a3 str r3, [r4, r2] 801635a: 3404 adds r4, #4 801635c: e79f b.n 801629e <__multiply+0x76> 801635e: 3e01 subs r6, #1 8016360: e7a1 b.n 80162a6 <__multiply+0x7e> 8016362: bf00 nop 8016364: 08017ab0 .word 0x08017ab0 8016368: 08017ad2 .word 0x08017ad2 0801636c <__pow5mult>: 801636c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8016370: 4615 mov r5, r2 8016372: f012 0203 ands.w r2, r2, #3 8016376: 4607 mov r7, r0 8016378: 460e mov r6, r1 801637a: d007 beq.n 801638c <__pow5mult+0x20> 801637c: 4c25 ldr r4, [pc, #148] @ (8016414 <__pow5mult+0xa8>) 801637e: 3a01 subs r2, #1 8016380: 2300 movs r3, #0 8016382: f854 2022 ldr.w r2, [r4, r2, lsl #2] 8016386: f7ff fea7 bl 80160d8 <__multadd> 801638a: 4606 mov r6, r0 801638c: 10ad asrs r5, r5, #2 801638e: d03d beq.n 801640c <__pow5mult+0xa0> 8016390: 69fc ldr r4, [r7, #28] 8016392: b97c cbnz r4, 80163b4 <__pow5mult+0x48> 8016394: 2010 movs r0, #16 8016396: f7ff fcdf bl 8015d58 801639a: 4602 mov r2, r0 801639c: 61f8 str r0, [r7, #28] 801639e: b928 cbnz r0, 80163ac <__pow5mult+0x40> 80163a0: f240 11b3 movw r1, #435 @ 0x1b3 80163a4: 4b1c ldr r3, [pc, #112] @ (8016418 <__pow5mult+0xac>) 80163a6: 481d ldr r0, [pc, #116] @ (801641c <__pow5mult+0xb0>) 80163a8: f7fe fd02 bl 8014db0 <__assert_func> 80163ac: e9c0 4401 strd r4, r4, [r0, #4] 80163b0: 6004 str r4, [r0, #0] 80163b2: 60c4 str r4, [r0, #12] 80163b4: f8d7 801c ldr.w r8, [r7, #28] 80163b8: f8d8 4008 ldr.w r4, [r8, #8] 80163bc: b94c cbnz r4, 80163d2 <__pow5mult+0x66> 80163be: f240 2171 movw r1, #625 @ 0x271 80163c2: 4638 mov r0, r7 80163c4: f7ff ff1a bl 80161fc <__i2b> 80163c8: 2300 movs r3, #0 80163ca: 4604 mov r4, r0 80163cc: f8c8 0008 str.w r0, [r8, #8] 80163d0: 6003 str r3, [r0, #0] 80163d2: f04f 0900 mov.w r9, #0 80163d6: 07eb lsls r3, r5, #31 80163d8: d50a bpl.n 80163f0 <__pow5mult+0x84> 80163da: 4631 mov r1, r6 80163dc: 4622 mov r2, r4 80163de: 4638 mov r0, r7 80163e0: f7ff ff22 bl 8016228 <__multiply> 80163e4: 4680 mov r8, r0 80163e6: 4631 mov r1, r6 80163e8: 4638 mov r0, r7 80163ea: f7ff fe53 bl 8016094 <_Bfree> 80163ee: 4646 mov r6, r8 80163f0: 106d asrs r5, r5, #1 80163f2: d00b beq.n 801640c <__pow5mult+0xa0> 80163f4: 6820 ldr r0, [r4, #0] 80163f6: b938 cbnz r0, 8016408 <__pow5mult+0x9c> 80163f8: 4622 mov r2, r4 80163fa: 4621 mov r1, r4 80163fc: 4638 mov r0, r7 80163fe: f7ff ff13 bl 8016228 <__multiply> 8016402: 6020 str r0, [r4, #0] 8016404: f8c0 9000 str.w r9, [r0] 8016408: 4604 mov r4, r0 801640a: e7e4 b.n 80163d6 <__pow5mult+0x6a> 801640c: 4630 mov r0, r6 801640e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8016412: bf00 nop 8016414: 08017b38 .word 0x08017b38 8016418: 08017a41 .word 0x08017a41 801641c: 08017ad2 .word 0x08017ad2 08016420 <__lshift>: 8016420: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8016424: 460c mov r4, r1 8016426: 4607 mov r7, r0 8016428: 4691 mov r9, r2 801642a: 6923 ldr r3, [r4, #16] 801642c: 6849 ldr r1, [r1, #4] 801642e: eb03 1862 add.w r8, r3, r2, asr #5 8016432: 68a3 ldr r3, [r4, #8] 8016434: ea4f 1a62 mov.w sl, r2, asr #5 8016438: f108 0601 add.w r6, r8, #1 801643c: 42b3 cmp r3, r6 801643e: db0b blt.n 8016458 <__lshift+0x38> 8016440: 4638 mov r0, r7 8016442: f7ff fde7 bl 8016014 <_Balloc> 8016446: 4605 mov r5, r0 8016448: b948 cbnz r0, 801645e <__lshift+0x3e> 801644a: 4602 mov r2, r0 801644c: f44f 71ef mov.w r1, #478 @ 0x1de 8016450: 4b27 ldr r3, [pc, #156] @ (80164f0 <__lshift+0xd0>) 8016452: 4828 ldr r0, [pc, #160] @ (80164f4 <__lshift+0xd4>) 8016454: f7fe fcac bl 8014db0 <__assert_func> 8016458: 3101 adds r1, #1 801645a: 005b lsls r3, r3, #1 801645c: e7ee b.n 801643c <__lshift+0x1c> 801645e: 2300 movs r3, #0 8016460: f100 0114 add.w r1, r0, #20 8016464: f100 0210 add.w r2, r0, #16 8016468: 4618 mov r0, r3 801646a: 4553 cmp r3, sl 801646c: db33 blt.n 80164d6 <__lshift+0xb6> 801646e: 6920 ldr r0, [r4, #16] 8016470: ea2a 7aea bic.w sl, sl, sl, asr #31 8016474: f104 0314 add.w r3, r4, #20 8016478: f019 091f ands.w r9, r9, #31 801647c: eb01 018a add.w r1, r1, sl, lsl #2 8016480: eb03 0c80 add.w ip, r3, r0, lsl #2 8016484: d02b beq.n 80164de <__lshift+0xbe> 8016486: 468a mov sl, r1 8016488: 2200 movs r2, #0 801648a: f1c9 0e20 rsb lr, r9, #32 801648e: 6818 ldr r0, [r3, #0] 8016490: fa00 f009 lsl.w r0, r0, r9 8016494: 4310 orrs r0, r2 8016496: f84a 0b04 str.w r0, [sl], #4 801649a: f853 2b04 ldr.w r2, [r3], #4 801649e: 459c cmp ip, r3 80164a0: fa22 f20e lsr.w r2, r2, lr 80164a4: d8f3 bhi.n 801648e <__lshift+0x6e> 80164a6: ebac 0304 sub.w r3, ip, r4 80164aa: 3b15 subs r3, #21 80164ac: f023 0303 bic.w r3, r3, #3 80164b0: 3304 adds r3, #4 80164b2: f104 0015 add.w r0, r4, #21 80164b6: 4560 cmp r0, ip 80164b8: bf88 it hi 80164ba: 2304 movhi r3, #4 80164bc: 50ca str r2, [r1, r3] 80164be: b10a cbz r2, 80164c4 <__lshift+0xa4> 80164c0: f108 0602 add.w r6, r8, #2 80164c4: 3e01 subs r6, #1 80164c6: 4638 mov r0, r7 80164c8: 4621 mov r1, r4 80164ca: 612e str r6, [r5, #16] 80164cc: f7ff fde2 bl 8016094 <_Bfree> 80164d0: 4628 mov r0, r5 80164d2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80164d6: f842 0f04 str.w r0, [r2, #4]! 80164da: 3301 adds r3, #1 80164dc: e7c5 b.n 801646a <__lshift+0x4a> 80164de: 3904 subs r1, #4 80164e0: f853 2b04 ldr.w r2, [r3], #4 80164e4: 459c cmp ip, r3 80164e6: f841 2f04 str.w r2, [r1, #4]! 80164ea: d8f9 bhi.n 80164e0 <__lshift+0xc0> 80164ec: e7ea b.n 80164c4 <__lshift+0xa4> 80164ee: bf00 nop 80164f0: 08017ab0 .word 0x08017ab0 80164f4: 08017ad2 .word 0x08017ad2 080164f8 <__mcmp>: 80164f8: 4603 mov r3, r0 80164fa: 690a ldr r2, [r1, #16] 80164fc: 6900 ldr r0, [r0, #16] 80164fe: b530 push {r4, r5, lr} 8016500: 1a80 subs r0, r0, r2 8016502: d10e bne.n 8016522 <__mcmp+0x2a> 8016504: 3314 adds r3, #20 8016506: 3114 adds r1, #20 8016508: eb03 0482 add.w r4, r3, r2, lsl #2 801650c: eb01 0182 add.w r1, r1, r2, lsl #2 8016510: f854 5d04 ldr.w r5, [r4, #-4]! 8016514: f851 2d04 ldr.w r2, [r1, #-4]! 8016518: 4295 cmp r5, r2 801651a: d003 beq.n 8016524 <__mcmp+0x2c> 801651c: d205 bcs.n 801652a <__mcmp+0x32> 801651e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016522: bd30 pop {r4, r5, pc} 8016524: 42a3 cmp r3, r4 8016526: d3f3 bcc.n 8016510 <__mcmp+0x18> 8016528: e7fb b.n 8016522 <__mcmp+0x2a> 801652a: 2001 movs r0, #1 801652c: e7f9 b.n 8016522 <__mcmp+0x2a> ... 08016530 <__mdiff>: 8016530: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8016534: 4689 mov r9, r1 8016536: 4606 mov r6, r0 8016538: 4611 mov r1, r2 801653a: 4648 mov r0, r9 801653c: 4614 mov r4, r2 801653e: f7ff ffdb bl 80164f8 <__mcmp> 8016542: 1e05 subs r5, r0, #0 8016544: d112 bne.n 801656c <__mdiff+0x3c> 8016546: 4629 mov r1, r5 8016548: 4630 mov r0, r6 801654a: f7ff fd63 bl 8016014 <_Balloc> 801654e: 4602 mov r2, r0 8016550: b928 cbnz r0, 801655e <__mdiff+0x2e> 8016552: f240 2137 movw r1, #567 @ 0x237 8016556: 4b3e ldr r3, [pc, #248] @ (8016650 <__mdiff+0x120>) 8016558: 483e ldr r0, [pc, #248] @ (8016654 <__mdiff+0x124>) 801655a: f7fe fc29 bl 8014db0 <__assert_func> 801655e: 2301 movs r3, #1 8016560: e9c0 3504 strd r3, r5, [r0, #16] 8016564: 4610 mov r0, r2 8016566: b003 add sp, #12 8016568: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801656c: bfbc itt lt 801656e: 464b movlt r3, r9 8016570: 46a1 movlt r9, r4 8016572: 4630 mov r0, r6 8016574: f8d9 1004 ldr.w r1, [r9, #4] 8016578: bfba itte lt 801657a: 461c movlt r4, r3 801657c: 2501 movlt r5, #1 801657e: 2500 movge r5, #0 8016580: f7ff fd48 bl 8016014 <_Balloc> 8016584: 4602 mov r2, r0 8016586: b918 cbnz r0, 8016590 <__mdiff+0x60> 8016588: f240 2145 movw r1, #581 @ 0x245 801658c: 4b30 ldr r3, [pc, #192] @ (8016650 <__mdiff+0x120>) 801658e: e7e3 b.n 8016558 <__mdiff+0x28> 8016590: f100 0b14 add.w fp, r0, #20 8016594: f8d9 7010 ldr.w r7, [r9, #16] 8016598: f109 0310 add.w r3, r9, #16 801659c: 60c5 str r5, [r0, #12] 801659e: f04f 0c00 mov.w ip, #0 80165a2: f109 0514 add.w r5, r9, #20 80165a6: 46d9 mov r9, fp 80165a8: 6926 ldr r6, [r4, #16] 80165aa: f104 0e14 add.w lr, r4, #20 80165ae: eb05 0887 add.w r8, r5, r7, lsl #2 80165b2: eb0e 0686 add.w r6, lr, r6, lsl #2 80165b6: 9301 str r3, [sp, #4] 80165b8: 9b01 ldr r3, [sp, #4] 80165ba: f85e 0b04 ldr.w r0, [lr], #4 80165be: f853 af04 ldr.w sl, [r3, #4]! 80165c2: b281 uxth r1, r0 80165c4: 9301 str r3, [sp, #4] 80165c6: fa1f f38a uxth.w r3, sl 80165ca: 1a5b subs r3, r3, r1 80165cc: 0c00 lsrs r0, r0, #16 80165ce: 4463 add r3, ip 80165d0: ebc0 401a rsb r0, r0, sl, lsr #16 80165d4: eb00 4023 add.w r0, r0, r3, asr #16 80165d8: b29b uxth r3, r3 80165da: ea43 4300 orr.w r3, r3, r0, lsl #16 80165de: 4576 cmp r6, lr 80165e0: ea4f 4c20 mov.w ip, r0, asr #16 80165e4: f849 3b04 str.w r3, [r9], #4 80165e8: d8e6 bhi.n 80165b8 <__mdiff+0x88> 80165ea: 1b33 subs r3, r6, r4 80165ec: 3b15 subs r3, #21 80165ee: f023 0303 bic.w r3, r3, #3 80165f2: 3415 adds r4, #21 80165f4: 3304 adds r3, #4 80165f6: 42a6 cmp r6, r4 80165f8: bf38 it cc 80165fa: 2304 movcc r3, #4 80165fc: 441d add r5, r3 80165fe: 445b add r3, fp 8016600: 461e mov r6, r3 8016602: 462c mov r4, r5 8016604: 4544 cmp r4, r8 8016606: d30e bcc.n 8016626 <__mdiff+0xf6> 8016608: f108 0103 add.w r1, r8, #3 801660c: 1b49 subs r1, r1, r5 801660e: f021 0103 bic.w r1, r1, #3 8016612: 3d03 subs r5, #3 8016614: 45a8 cmp r8, r5 8016616: bf38 it cc 8016618: 2100 movcc r1, #0 801661a: 440b add r3, r1 801661c: f853 1d04 ldr.w r1, [r3, #-4]! 8016620: b199 cbz r1, 801664a <__mdiff+0x11a> 8016622: 6117 str r7, [r2, #16] 8016624: e79e b.n 8016564 <__mdiff+0x34> 8016626: 46e6 mov lr, ip 8016628: f854 1b04 ldr.w r1, [r4], #4 801662c: fa1f fc81 uxth.w ip, r1 8016630: 44f4 add ip, lr 8016632: 0c08 lsrs r0, r1, #16 8016634: 4471 add r1, lr 8016636: eb00 402c add.w r0, r0, ip, asr #16 801663a: b289 uxth r1, r1 801663c: ea41 4100 orr.w r1, r1, r0, lsl #16 8016640: ea4f 4c20 mov.w ip, r0, asr #16 8016644: f846 1b04 str.w r1, [r6], #4 8016648: e7dc b.n 8016604 <__mdiff+0xd4> 801664a: 3f01 subs r7, #1 801664c: e7e6 b.n 801661c <__mdiff+0xec> 801664e: bf00 nop 8016650: 08017ab0 .word 0x08017ab0 8016654: 08017ad2 .word 0x08017ad2 08016658 <__d2b>: 8016658: e92d 4373 stmdb sp!, {r0, r1, r4, r5, r6, r8, r9, lr} 801665c: 2101 movs r1, #1 801665e: 4690 mov r8, r2 8016660: 4699 mov r9, r3 8016662: 9e08 ldr r6, [sp, #32] 8016664: f7ff fcd6 bl 8016014 <_Balloc> 8016668: 4604 mov r4, r0 801666a: b930 cbnz r0, 801667a <__d2b+0x22> 801666c: 4602 mov r2, r0 801666e: f240 310f movw r1, #783 @ 0x30f 8016672: 4b23 ldr r3, [pc, #140] @ (8016700 <__d2b+0xa8>) 8016674: 4823 ldr r0, [pc, #140] @ (8016704 <__d2b+0xac>) 8016676: f7fe fb9b bl 8014db0 <__assert_func> 801667a: f3c9 550a ubfx r5, r9, #20, #11 801667e: f3c9 0313 ubfx r3, r9, #0, #20 8016682: b10d cbz r5, 8016688 <__d2b+0x30> 8016684: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8016688: 9301 str r3, [sp, #4] 801668a: f1b8 0300 subs.w r3, r8, #0 801668e: d024 beq.n 80166da <__d2b+0x82> 8016690: 4668 mov r0, sp 8016692: 9300 str r3, [sp, #0] 8016694: f7ff fd85 bl 80161a2 <__lo0bits> 8016698: e9dd 1200 ldrd r1, r2, [sp] 801669c: b1d8 cbz r0, 80166d6 <__d2b+0x7e> 801669e: f1c0 0320 rsb r3, r0, #32 80166a2: fa02 f303 lsl.w r3, r2, r3 80166a6: 430b orrs r3, r1 80166a8: 40c2 lsrs r2, r0 80166aa: 6163 str r3, [r4, #20] 80166ac: 9201 str r2, [sp, #4] 80166ae: 9b01 ldr r3, [sp, #4] 80166b0: 2b00 cmp r3, #0 80166b2: bf0c ite eq 80166b4: 2201 moveq r2, #1 80166b6: 2202 movne r2, #2 80166b8: 61a3 str r3, [r4, #24] 80166ba: 6122 str r2, [r4, #16] 80166bc: b1ad cbz r5, 80166ea <__d2b+0x92> 80166be: f2a5 4533 subw r5, r5, #1075 @ 0x433 80166c2: 4405 add r5, r0 80166c4: 6035 str r5, [r6, #0] 80166c6: f1c0 0035 rsb r0, r0, #53 @ 0x35 80166ca: 9b09 ldr r3, [sp, #36] @ 0x24 80166cc: 6018 str r0, [r3, #0] 80166ce: 4620 mov r0, r4 80166d0: b002 add sp, #8 80166d2: e8bd 8370 ldmia.w sp!, {r4, r5, r6, r8, r9, pc} 80166d6: 6161 str r1, [r4, #20] 80166d8: e7e9 b.n 80166ae <__d2b+0x56> 80166da: a801 add r0, sp, #4 80166dc: f7ff fd61 bl 80161a2 <__lo0bits> 80166e0: 9b01 ldr r3, [sp, #4] 80166e2: 2201 movs r2, #1 80166e4: 6163 str r3, [r4, #20] 80166e6: 3020 adds r0, #32 80166e8: e7e7 b.n 80166ba <__d2b+0x62> 80166ea: f2a0 4032 subw r0, r0, #1074 @ 0x432 80166ee: eb04 0382 add.w r3, r4, r2, lsl #2 80166f2: 6030 str r0, [r6, #0] 80166f4: 6918 ldr r0, [r3, #16] 80166f6: f7ff fd35 bl 8016164 <__hi0bits> 80166fa: ebc0 1042 rsb r0, r0, r2, lsl #5 80166fe: e7e4 b.n 80166ca <__d2b+0x72> 8016700: 08017ab0 .word 0x08017ab0 8016704: 08017ad2 .word 0x08017ad2 08016708 <__sread>: 8016708: b510 push {r4, lr} 801670a: 460c mov r4, r1 801670c: f9b1 100e ldrsh.w r1, [r1, #14] 8016710: f000 f8aa bl 8016868 <_read_r> 8016714: 2800 cmp r0, #0 8016716: bfab itete ge 8016718: 6d63 ldrge r3, [r4, #84] @ 0x54 801671a: 89a3 ldrhlt r3, [r4, #12] 801671c: 181b addge r3, r3, r0 801671e: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 8016722: bfac ite ge 8016724: 6563 strge r3, [r4, #84] @ 0x54 8016726: 81a3 strhlt r3, [r4, #12] 8016728: bd10 pop {r4, pc} 0801672a <__swrite>: 801672a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 801672e: 461f mov r7, r3 8016730: 898b ldrh r3, [r1, #12] 8016732: 4605 mov r5, r0 8016734: 05db lsls r3, r3, #23 8016736: 460c mov r4, r1 8016738: 4616 mov r6, r2 801673a: d505 bpl.n 8016748 <__swrite+0x1e> 801673c: 2302 movs r3, #2 801673e: 2200 movs r2, #0 8016740: f9b1 100e ldrsh.w r1, [r1, #14] 8016744: f000 f87e bl 8016844 <_lseek_r> 8016748: 89a3 ldrh r3, [r4, #12] 801674a: 4632 mov r2, r6 801674c: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8016750: 81a3 strh r3, [r4, #12] 8016752: 4628 mov r0, r5 8016754: 463b mov r3, r7 8016756: f9b4 100e ldrsh.w r1, [r4, #14] 801675a: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 801675e: f000 b8a5 b.w 80168ac <_write_r> 08016762 <__sseek>: 8016762: b510 push {r4, lr} 8016764: 460c mov r4, r1 8016766: f9b1 100e ldrsh.w r1, [r1, #14] 801676a: f000 f86b bl 8016844 <_lseek_r> 801676e: 1c43 adds r3, r0, #1 8016770: 89a3 ldrh r3, [r4, #12] 8016772: bf15 itete ne 8016774: 6560 strne r0, [r4, #84] @ 0x54 8016776: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 801677a: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 801677e: 81a3 strheq r3, [r4, #12] 8016780: bf18 it ne 8016782: 81a3 strhne r3, [r4, #12] 8016784: bd10 pop {r4, pc} 08016786 <__sclose>: 8016786: f9b1 100e ldrsh.w r1, [r1, #14] 801678a: f000 b8a1 b.w 80168d0 <_close_r> ... 08016790 : 8016790: b40e push {r1, r2, r3} 8016792: b503 push {r0, r1, lr} 8016794: 4601 mov r1, r0 8016796: ab03 add r3, sp, #12 8016798: 4805 ldr r0, [pc, #20] @ (80167b0 ) 801679a: f853 2b04 ldr.w r2, [r3], #4 801679e: 6800 ldr r0, [r0, #0] 80167a0: 9301 str r3, [sp, #4] 80167a2: f000 f931 bl 8016a08 <_vfiprintf_r> 80167a6: b002 add sp, #8 80167a8: f85d eb04 ldr.w lr, [sp], #4 80167ac: b003 add sp, #12 80167ae: 4770 bx lr 80167b0: 2000009c .word 0x2000009c 080167b4 <_realloc_r>: 80167b4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80167b8: 4607 mov r7, r0 80167ba: 4614 mov r4, r2 80167bc: 460d mov r5, r1 80167be: b921 cbnz r1, 80167ca <_realloc_r+0x16> 80167c0: 4611 mov r1, r2 80167c2: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 80167c6: f7ff baf1 b.w 8015dac <_malloc_r> 80167ca: b92a cbnz r2, 80167d8 <_realloc_r+0x24> 80167cc: f000 f8ac bl 8016928 <_free_r> 80167d0: 4625 mov r5, r4 80167d2: 4628 mov r0, r5 80167d4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80167d8: f000 fa40 bl 8016c5c <_malloc_usable_size_r> 80167dc: 4284 cmp r4, r0 80167de: 4606 mov r6, r0 80167e0: d802 bhi.n 80167e8 <_realloc_r+0x34> 80167e2: ebb4 0f50 cmp.w r4, r0, lsr #1 80167e6: d8f4 bhi.n 80167d2 <_realloc_r+0x1e> 80167e8: 4621 mov r1, r4 80167ea: 4638 mov r0, r7 80167ec: f7ff fade bl 8015dac <_malloc_r> 80167f0: 4680 mov r8, r0 80167f2: b908 cbnz r0, 80167f8 <_realloc_r+0x44> 80167f4: 4645 mov r5, r8 80167f6: e7ec b.n 80167d2 <_realloc_r+0x1e> 80167f8: 42b4 cmp r4, r6 80167fa: 4622 mov r2, r4 80167fc: 4629 mov r1, r5 80167fe: bf28 it cs 8016800: 4632 movcs r2, r6 8016802: f7fe fac7 bl 8014d94 8016806: 4629 mov r1, r5 8016808: 4638 mov r0, r7 801680a: f000 f88d bl 8016928 <_free_r> 801680e: e7f1 b.n 80167f4 <_realloc_r+0x40> 08016810 : 8016810: 4288 cmp r0, r1 8016812: b510 push {r4, lr} 8016814: eb01 0402 add.w r4, r1, r2 8016818: d902 bls.n 8016820 801681a: 4284 cmp r4, r0 801681c: 4623 mov r3, r4 801681e: d807 bhi.n 8016830 8016820: 1e43 subs r3, r0, #1 8016822: 42a1 cmp r1, r4 8016824: d008 beq.n 8016838 8016826: f811 2b01 ldrb.w r2, [r1], #1 801682a: f803 2f01 strb.w r2, [r3, #1]! 801682e: e7f8 b.n 8016822 8016830: 4601 mov r1, r0 8016832: 4402 add r2, r0 8016834: 428a cmp r2, r1 8016836: d100 bne.n 801683a 8016838: bd10 pop {r4, pc} 801683a: f813 4d01 ldrb.w r4, [r3, #-1]! 801683e: f802 4d01 strb.w r4, [r2, #-1]! 8016842: e7f7 b.n 8016834 08016844 <_lseek_r>: 8016844: b538 push {r3, r4, r5, lr} 8016846: 4604 mov r4, r0 8016848: 4608 mov r0, r1 801684a: 4611 mov r1, r2 801684c: 2200 movs r2, #0 801684e: 4d05 ldr r5, [pc, #20] @ (8016864 <_lseek_r+0x20>) 8016850: 602a str r2, [r5, #0] 8016852: 461a mov r2, r3 8016854: f7f7 f875 bl 800d942 <_lseek> 8016858: 1c43 adds r3, r0, #1 801685a: d102 bne.n 8016862 <_lseek_r+0x1e> 801685c: 682b ldr r3, [r5, #0] 801685e: b103 cbz r3, 8016862 <_lseek_r+0x1e> 8016860: 6023 str r3, [r4, #0] 8016862: bd38 pop {r3, r4, r5, pc} 8016864: 200015d4 .word 0x200015d4 08016868 <_read_r>: 8016868: b538 push {r3, r4, r5, lr} 801686a: 4604 mov r4, r0 801686c: 4608 mov r0, r1 801686e: 4611 mov r1, r2 8016870: 2200 movs r2, #0 8016872: 4d05 ldr r5, [pc, #20] @ (8016888 <_read_r+0x20>) 8016874: 602a str r2, [r5, #0] 8016876: 461a mov r2, r3 8016878: f7f7 f822 bl 800d8c0 <_read> 801687c: 1c43 adds r3, r0, #1 801687e: d102 bne.n 8016886 <_read_r+0x1e> 8016880: 682b ldr r3, [r5, #0] 8016882: b103 cbz r3, 8016886 <_read_r+0x1e> 8016884: 6023 str r3, [r4, #0] 8016886: bd38 pop {r3, r4, r5, pc} 8016888: 200015d4 .word 0x200015d4 0801688c <_sbrk_r>: 801688c: b538 push {r3, r4, r5, lr} 801688e: 2300 movs r3, #0 8016890: 4d05 ldr r5, [pc, #20] @ (80168a8 <_sbrk_r+0x1c>) 8016892: 4604 mov r4, r0 8016894: 4608 mov r0, r1 8016896: 602b str r3, [r5, #0] 8016898: f7f7 f860 bl 800d95c <_sbrk> 801689c: 1c43 adds r3, r0, #1 801689e: d102 bne.n 80168a6 <_sbrk_r+0x1a> 80168a0: 682b ldr r3, [r5, #0] 80168a2: b103 cbz r3, 80168a6 <_sbrk_r+0x1a> 80168a4: 6023 str r3, [r4, #0] 80168a6: bd38 pop {r3, r4, r5, pc} 80168a8: 200015d4 .word 0x200015d4 080168ac <_write_r>: 80168ac: b538 push {r3, r4, r5, lr} 80168ae: 4604 mov r4, r0 80168b0: 4608 mov r0, r1 80168b2: 4611 mov r1, r2 80168b4: 2200 movs r2, #0 80168b6: 4d05 ldr r5, [pc, #20] @ (80168cc <_write_r+0x20>) 80168b8: 602a str r2, [r5, #0] 80168ba: 461a mov r2, r3 80168bc: f7f3 fd6e bl 800a39c <_write> 80168c0: 1c43 adds r3, r0, #1 80168c2: d102 bne.n 80168ca <_write_r+0x1e> 80168c4: 682b ldr r3, [r5, #0] 80168c6: b103 cbz r3, 80168ca <_write_r+0x1e> 80168c8: 6023 str r3, [r4, #0] 80168ca: bd38 pop {r3, r4, r5, pc} 80168cc: 200015d4 .word 0x200015d4 080168d0 <_close_r>: 80168d0: b538 push {r3, r4, r5, lr} 80168d2: 2300 movs r3, #0 80168d4: 4d05 ldr r5, [pc, #20] @ (80168ec <_close_r+0x1c>) 80168d6: 4604 mov r4, r0 80168d8: 4608 mov r0, r1 80168da: 602b str r3, [r5, #0] 80168dc: f7f7 f80d bl 800d8fa <_close> 80168e0: 1c43 adds r3, r0, #1 80168e2: d102 bne.n 80168ea <_close_r+0x1a> 80168e4: 682b ldr r3, [r5, #0] 80168e6: b103 cbz r3, 80168ea <_close_r+0x1a> 80168e8: 6023 str r3, [r4, #0] 80168ea: bd38 pop {r3, r4, r5, pc} 80168ec: 200015d4 .word 0x200015d4 080168f0 : 80168f0: 2006 movs r0, #6 80168f2: b508 push {r3, lr} 80168f4: f000 fae4 bl 8016ec0 80168f8: 2001 movs r0, #1 80168fa: f7f6 ffd6 bl 800d8aa <_exit> 080168fe <_calloc_r>: 80168fe: b570 push {r4, r5, r6, lr} 8016900: fba1 5402 umull r5, r4, r1, r2 8016904: b934 cbnz r4, 8016914 <_calloc_r+0x16> 8016906: 4629 mov r1, r5 8016908: f7ff fa50 bl 8015dac <_malloc_r> 801690c: 4606 mov r6, r0 801690e: b928 cbnz r0, 801691c <_calloc_r+0x1e> 8016910: 4630 mov r0, r6 8016912: bd70 pop {r4, r5, r6, pc} 8016914: 220c movs r2, #12 8016916: 2600 movs r6, #0 8016918: 6002 str r2, [r0, #0] 801691a: e7f9 b.n 8016910 <_calloc_r+0x12> 801691c: 462a mov r2, r5 801691e: 4621 mov r1, r4 8016920: f7fe f9f0 bl 8014d04 8016924: e7f4 b.n 8016910 <_calloc_r+0x12> ... 08016928 <_free_r>: 8016928: b538 push {r3, r4, r5, lr} 801692a: 4605 mov r5, r0 801692c: 2900 cmp r1, #0 801692e: d040 beq.n 80169b2 <_free_r+0x8a> 8016930: f851 3c04 ldr.w r3, [r1, #-4] 8016934: 1f0c subs r4, r1, #4 8016936: 2b00 cmp r3, #0 8016938: bfb8 it lt 801693a: 18e4 addlt r4, r4, r3 801693c: f7ff fb5e bl 8015ffc <__malloc_lock> 8016940: 4a1c ldr r2, [pc, #112] @ (80169b4 <_free_r+0x8c>) 8016942: 6813 ldr r3, [r2, #0] 8016944: b933 cbnz r3, 8016954 <_free_r+0x2c> 8016946: 6063 str r3, [r4, #4] 8016948: 6014 str r4, [r2, #0] 801694a: 4628 mov r0, r5 801694c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8016950: f7ff bb5a b.w 8016008 <__malloc_unlock> 8016954: 42a3 cmp r3, r4 8016956: d908 bls.n 801696a <_free_r+0x42> 8016958: 6820 ldr r0, [r4, #0] 801695a: 1821 adds r1, r4, r0 801695c: 428b cmp r3, r1 801695e: bf01 itttt eq 8016960: 6819 ldreq r1, [r3, #0] 8016962: 685b ldreq r3, [r3, #4] 8016964: 1809 addeq r1, r1, r0 8016966: 6021 streq r1, [r4, #0] 8016968: e7ed b.n 8016946 <_free_r+0x1e> 801696a: 461a mov r2, r3 801696c: 685b ldr r3, [r3, #4] 801696e: b10b cbz r3, 8016974 <_free_r+0x4c> 8016970: 42a3 cmp r3, r4 8016972: d9fa bls.n 801696a <_free_r+0x42> 8016974: 6811 ldr r1, [r2, #0] 8016976: 1850 adds r0, r2, r1 8016978: 42a0 cmp r0, r4 801697a: d10b bne.n 8016994 <_free_r+0x6c> 801697c: 6820 ldr r0, [r4, #0] 801697e: 4401 add r1, r0 8016980: 1850 adds r0, r2, r1 8016982: 4283 cmp r3, r0 8016984: 6011 str r1, [r2, #0] 8016986: d1e0 bne.n 801694a <_free_r+0x22> 8016988: 6818 ldr r0, [r3, #0] 801698a: 685b ldr r3, [r3, #4] 801698c: 4408 add r0, r1 801698e: 6010 str r0, [r2, #0] 8016990: 6053 str r3, [r2, #4] 8016992: e7da b.n 801694a <_free_r+0x22> 8016994: d902 bls.n 801699c <_free_r+0x74> 8016996: 230c movs r3, #12 8016998: 602b str r3, [r5, #0] 801699a: e7d6 b.n 801694a <_free_r+0x22> 801699c: 6820 ldr r0, [r4, #0] 801699e: 1821 adds r1, r4, r0 80169a0: 428b cmp r3, r1 80169a2: bf01 itttt eq 80169a4: 6819 ldreq r1, [r3, #0] 80169a6: 685b ldreq r3, [r3, #4] 80169a8: 1809 addeq r1, r1, r0 80169aa: 6021 streq r1, [r4, #0] 80169ac: 6063 str r3, [r4, #4] 80169ae: 6054 str r4, [r2, #4] 80169b0: e7cb b.n 801694a <_free_r+0x22> 80169b2: bd38 pop {r3, r4, r5, pc} 80169b4: 200015d0 .word 0x200015d0 080169b8 <__sfputc_r>: 80169b8: 6893 ldr r3, [r2, #8] 80169ba: b410 push {r4} 80169bc: 3b01 subs r3, #1 80169be: 2b00 cmp r3, #0 80169c0: 6093 str r3, [r2, #8] 80169c2: da07 bge.n 80169d4 <__sfputc_r+0x1c> 80169c4: 6994 ldr r4, [r2, #24] 80169c6: 42a3 cmp r3, r4 80169c8: db01 blt.n 80169ce <__sfputc_r+0x16> 80169ca: 290a cmp r1, #10 80169cc: d102 bne.n 80169d4 <__sfputc_r+0x1c> 80169ce: bc10 pop {r4} 80169d0: f000 b94c b.w 8016c6c <__swbuf_r> 80169d4: 6813 ldr r3, [r2, #0] 80169d6: 1c58 adds r0, r3, #1 80169d8: 6010 str r0, [r2, #0] 80169da: 7019 strb r1, [r3, #0] 80169dc: 4608 mov r0, r1 80169de: bc10 pop {r4} 80169e0: 4770 bx lr 080169e2 <__sfputs_r>: 80169e2: b5f8 push {r3, r4, r5, r6, r7, lr} 80169e4: 4606 mov r6, r0 80169e6: 460f mov r7, r1 80169e8: 4614 mov r4, r2 80169ea: 18d5 adds r5, r2, r3 80169ec: 42ac cmp r4, r5 80169ee: d101 bne.n 80169f4 <__sfputs_r+0x12> 80169f0: 2000 movs r0, #0 80169f2: e007 b.n 8016a04 <__sfputs_r+0x22> 80169f4: 463a mov r2, r7 80169f6: 4630 mov r0, r6 80169f8: f814 1b01 ldrb.w r1, [r4], #1 80169fc: f7ff ffdc bl 80169b8 <__sfputc_r> 8016a00: 1c43 adds r3, r0, #1 8016a02: d1f3 bne.n 80169ec <__sfputs_r+0xa> 8016a04: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 08016a08 <_vfiprintf_r>: 8016a08: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8016a0c: 460d mov r5, r1 8016a0e: 4614 mov r4, r2 8016a10: 4698 mov r8, r3 8016a12: 4606 mov r6, r0 8016a14: b09d sub sp, #116 @ 0x74 8016a16: b118 cbz r0, 8016a20 <_vfiprintf_r+0x18> 8016a18: 6a03 ldr r3, [r0, #32] 8016a1a: b90b cbnz r3, 8016a20 <_vfiprintf_r+0x18> 8016a1c: f7fe f900 bl 8014c20 <__sinit> 8016a20: 6e6b ldr r3, [r5, #100] @ 0x64 8016a22: 07d9 lsls r1, r3, #31 8016a24: d405 bmi.n 8016a32 <_vfiprintf_r+0x2a> 8016a26: 89ab ldrh r3, [r5, #12] 8016a28: 059a lsls r2, r3, #22 8016a2a: d402 bmi.n 8016a32 <_vfiprintf_r+0x2a> 8016a2c: 6da8 ldr r0, [r5, #88] @ 0x58 8016a2e: f7fe f99c bl 8014d6a <__retarget_lock_acquire_recursive> 8016a32: 89ab ldrh r3, [r5, #12] 8016a34: 071b lsls r3, r3, #28 8016a36: d501 bpl.n 8016a3c <_vfiprintf_r+0x34> 8016a38: 692b ldr r3, [r5, #16] 8016a3a: b99b cbnz r3, 8016a64 <_vfiprintf_r+0x5c> 8016a3c: 4629 mov r1, r5 8016a3e: 4630 mov r0, r6 8016a40: f000 f952 bl 8016ce8 <__swsetup_r> 8016a44: b170 cbz r0, 8016a64 <_vfiprintf_r+0x5c> 8016a46: 6e6b ldr r3, [r5, #100] @ 0x64 8016a48: 07dc lsls r4, r3, #31 8016a4a: d504 bpl.n 8016a56 <_vfiprintf_r+0x4e> 8016a4c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016a50: b01d add sp, #116 @ 0x74 8016a52: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8016a56: 89ab ldrh r3, [r5, #12] 8016a58: 0598 lsls r0, r3, #22 8016a5a: d4f7 bmi.n 8016a4c <_vfiprintf_r+0x44> 8016a5c: 6da8 ldr r0, [r5, #88] @ 0x58 8016a5e: f7fe f985 bl 8014d6c <__retarget_lock_release_recursive> 8016a62: e7f3 b.n 8016a4c <_vfiprintf_r+0x44> 8016a64: 2300 movs r3, #0 8016a66: 9309 str r3, [sp, #36] @ 0x24 8016a68: 2320 movs r3, #32 8016a6a: f88d 3029 strb.w r3, [sp, #41] @ 0x29 8016a6e: 2330 movs r3, #48 @ 0x30 8016a70: f04f 0901 mov.w r9, #1 8016a74: f8cd 800c str.w r8, [sp, #12] 8016a78: f8df 81a8 ldr.w r8, [pc, #424] @ 8016c24 <_vfiprintf_r+0x21c> 8016a7c: f88d 302a strb.w r3, [sp, #42] @ 0x2a 8016a80: 4623 mov r3, r4 8016a82: 469a mov sl, r3 8016a84: f813 2b01 ldrb.w r2, [r3], #1 8016a88: b10a cbz r2, 8016a8e <_vfiprintf_r+0x86> 8016a8a: 2a25 cmp r2, #37 @ 0x25 8016a8c: d1f9 bne.n 8016a82 <_vfiprintf_r+0x7a> 8016a8e: ebba 0b04 subs.w fp, sl, r4 8016a92: d00b beq.n 8016aac <_vfiprintf_r+0xa4> 8016a94: 465b mov r3, fp 8016a96: 4622 mov r2, r4 8016a98: 4629 mov r1, r5 8016a9a: 4630 mov r0, r6 8016a9c: f7ff ffa1 bl 80169e2 <__sfputs_r> 8016aa0: 3001 adds r0, #1 8016aa2: f000 80a7 beq.w 8016bf4 <_vfiprintf_r+0x1ec> 8016aa6: 9a09 ldr r2, [sp, #36] @ 0x24 8016aa8: 445a add r2, fp 8016aaa: 9209 str r2, [sp, #36] @ 0x24 8016aac: f89a 3000 ldrb.w r3, [sl] 8016ab0: 2b00 cmp r3, #0 8016ab2: f000 809f beq.w 8016bf4 <_vfiprintf_r+0x1ec> 8016ab6: 2300 movs r3, #0 8016ab8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8016abc: e9cd 2305 strd r2, r3, [sp, #20] 8016ac0: f10a 0a01 add.w sl, sl, #1 8016ac4: 9304 str r3, [sp, #16] 8016ac6: 9307 str r3, [sp, #28] 8016ac8: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8016acc: 931a str r3, [sp, #104] @ 0x68 8016ace: 4654 mov r4, sl 8016ad0: 2205 movs r2, #5 8016ad2: f814 1b01 ldrb.w r1, [r4], #1 8016ad6: 4853 ldr r0, [pc, #332] @ (8016c24 <_vfiprintf_r+0x21c>) 8016ad8: f7fe f94e bl 8014d78 8016adc: 9a04 ldr r2, [sp, #16] 8016ade: b9d8 cbnz r0, 8016b18 <_vfiprintf_r+0x110> 8016ae0: 06d1 lsls r1, r2, #27 8016ae2: bf44 itt mi 8016ae4: 2320 movmi r3, #32 8016ae6: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8016aea: 0713 lsls r3, r2, #28 8016aec: bf44 itt mi 8016aee: 232b movmi r3, #43 @ 0x2b 8016af0: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8016af4: f89a 3000 ldrb.w r3, [sl] 8016af8: 2b2a cmp r3, #42 @ 0x2a 8016afa: d015 beq.n 8016b28 <_vfiprintf_r+0x120> 8016afc: 4654 mov r4, sl 8016afe: 2000 movs r0, #0 8016b00: f04f 0c0a mov.w ip, #10 8016b04: 9a07 ldr r2, [sp, #28] 8016b06: 4621 mov r1, r4 8016b08: f811 3b01 ldrb.w r3, [r1], #1 8016b0c: 3b30 subs r3, #48 @ 0x30 8016b0e: 2b09 cmp r3, #9 8016b10: d94b bls.n 8016baa <_vfiprintf_r+0x1a2> 8016b12: b1b0 cbz r0, 8016b42 <_vfiprintf_r+0x13a> 8016b14: 9207 str r2, [sp, #28] 8016b16: e014 b.n 8016b42 <_vfiprintf_r+0x13a> 8016b18: eba0 0308 sub.w r3, r0, r8 8016b1c: fa09 f303 lsl.w r3, r9, r3 8016b20: 4313 orrs r3, r2 8016b22: 46a2 mov sl, r4 8016b24: 9304 str r3, [sp, #16] 8016b26: e7d2 b.n 8016ace <_vfiprintf_r+0xc6> 8016b28: 9b03 ldr r3, [sp, #12] 8016b2a: 1d19 adds r1, r3, #4 8016b2c: 681b ldr r3, [r3, #0] 8016b2e: 9103 str r1, [sp, #12] 8016b30: 2b00 cmp r3, #0 8016b32: bfbb ittet lt 8016b34: 425b neglt r3, r3 8016b36: f042 0202 orrlt.w r2, r2, #2 8016b3a: 9307 strge r3, [sp, #28] 8016b3c: 9307 strlt r3, [sp, #28] 8016b3e: bfb8 it lt 8016b40: 9204 strlt r2, [sp, #16] 8016b42: 7823 ldrb r3, [r4, #0] 8016b44: 2b2e cmp r3, #46 @ 0x2e 8016b46: d10a bne.n 8016b5e <_vfiprintf_r+0x156> 8016b48: 7863 ldrb r3, [r4, #1] 8016b4a: 2b2a cmp r3, #42 @ 0x2a 8016b4c: d132 bne.n 8016bb4 <_vfiprintf_r+0x1ac> 8016b4e: 9b03 ldr r3, [sp, #12] 8016b50: 3402 adds r4, #2 8016b52: 1d1a adds r2, r3, #4 8016b54: 681b ldr r3, [r3, #0] 8016b56: 9203 str r2, [sp, #12] 8016b58: ea43 73e3 orr.w r3, r3, r3, asr #31 8016b5c: 9305 str r3, [sp, #20] 8016b5e: f8df a0c8 ldr.w sl, [pc, #200] @ 8016c28 <_vfiprintf_r+0x220> 8016b62: 2203 movs r2, #3 8016b64: 4650 mov r0, sl 8016b66: 7821 ldrb r1, [r4, #0] 8016b68: f7fe f906 bl 8014d78 8016b6c: b138 cbz r0, 8016b7e <_vfiprintf_r+0x176> 8016b6e: 2240 movs r2, #64 @ 0x40 8016b70: 9b04 ldr r3, [sp, #16] 8016b72: eba0 000a sub.w r0, r0, sl 8016b76: 4082 lsls r2, r0 8016b78: 4313 orrs r3, r2 8016b7a: 3401 adds r4, #1 8016b7c: 9304 str r3, [sp, #16] 8016b7e: f814 1b01 ldrb.w r1, [r4], #1 8016b82: 2206 movs r2, #6 8016b84: 4829 ldr r0, [pc, #164] @ (8016c2c <_vfiprintf_r+0x224>) 8016b86: f88d 1028 strb.w r1, [sp, #40] @ 0x28 8016b8a: f7fe f8f5 bl 8014d78 8016b8e: 2800 cmp r0, #0 8016b90: d03f beq.n 8016c12 <_vfiprintf_r+0x20a> 8016b92: 4b27 ldr r3, [pc, #156] @ (8016c30 <_vfiprintf_r+0x228>) 8016b94: bb1b cbnz r3, 8016bde <_vfiprintf_r+0x1d6> 8016b96: 9b03 ldr r3, [sp, #12] 8016b98: 3307 adds r3, #7 8016b9a: f023 0307 bic.w r3, r3, #7 8016b9e: 3308 adds r3, #8 8016ba0: 9303 str r3, [sp, #12] 8016ba2: 9b09 ldr r3, [sp, #36] @ 0x24 8016ba4: 443b add r3, r7 8016ba6: 9309 str r3, [sp, #36] @ 0x24 8016ba8: e76a b.n 8016a80 <_vfiprintf_r+0x78> 8016baa: 460c mov r4, r1 8016bac: 2001 movs r0, #1 8016bae: fb0c 3202 mla r2, ip, r2, r3 8016bb2: e7a8 b.n 8016b06 <_vfiprintf_r+0xfe> 8016bb4: 2300 movs r3, #0 8016bb6: f04f 0c0a mov.w ip, #10 8016bba: 4619 mov r1, r3 8016bbc: 3401 adds r4, #1 8016bbe: 9305 str r3, [sp, #20] 8016bc0: 4620 mov r0, r4 8016bc2: f810 2b01 ldrb.w r2, [r0], #1 8016bc6: 3a30 subs r2, #48 @ 0x30 8016bc8: 2a09 cmp r2, #9 8016bca: d903 bls.n 8016bd4 <_vfiprintf_r+0x1cc> 8016bcc: 2b00 cmp r3, #0 8016bce: d0c6 beq.n 8016b5e <_vfiprintf_r+0x156> 8016bd0: 9105 str r1, [sp, #20] 8016bd2: e7c4 b.n 8016b5e <_vfiprintf_r+0x156> 8016bd4: 4604 mov r4, r0 8016bd6: 2301 movs r3, #1 8016bd8: fb0c 2101 mla r1, ip, r1, r2 8016bdc: e7f0 b.n 8016bc0 <_vfiprintf_r+0x1b8> 8016bde: ab03 add r3, sp, #12 8016be0: 9300 str r3, [sp, #0] 8016be2: 462a mov r2, r5 8016be4: 4630 mov r0, r6 8016be6: 4b13 ldr r3, [pc, #76] @ (8016c34 <_vfiprintf_r+0x22c>) 8016be8: a904 add r1, sp, #16 8016bea: f7fd fbd1 bl 8014390 <_printf_float> 8016bee: 4607 mov r7, r0 8016bf0: 1c78 adds r0, r7, #1 8016bf2: d1d6 bne.n 8016ba2 <_vfiprintf_r+0x19a> 8016bf4: 6e6b ldr r3, [r5, #100] @ 0x64 8016bf6: 07d9 lsls r1, r3, #31 8016bf8: d405 bmi.n 8016c06 <_vfiprintf_r+0x1fe> 8016bfa: 89ab ldrh r3, [r5, #12] 8016bfc: 059a lsls r2, r3, #22 8016bfe: d402 bmi.n 8016c06 <_vfiprintf_r+0x1fe> 8016c00: 6da8 ldr r0, [r5, #88] @ 0x58 8016c02: f7fe f8b3 bl 8014d6c <__retarget_lock_release_recursive> 8016c06: 89ab ldrh r3, [r5, #12] 8016c08: 065b lsls r3, r3, #25 8016c0a: f53f af1f bmi.w 8016a4c <_vfiprintf_r+0x44> 8016c0e: 9809 ldr r0, [sp, #36] @ 0x24 8016c10: e71e b.n 8016a50 <_vfiprintf_r+0x48> 8016c12: ab03 add r3, sp, #12 8016c14: 9300 str r3, [sp, #0] 8016c16: 462a mov r2, r5 8016c18: 4630 mov r0, r6 8016c1a: 4b06 ldr r3, [pc, #24] @ (8016c34 <_vfiprintf_r+0x22c>) 8016c1c: a904 add r1, sp, #16 8016c1e: f7fd fe55 bl 80148cc <_printf_i> 8016c22: e7e4 b.n 8016bee <_vfiprintf_r+0x1e6> 8016c24: 08017ac1 .word 0x08017ac1 8016c28: 08017ac7 .word 0x08017ac7 8016c2c: 08017acb .word 0x08017acb 8016c30: 08014391 .word 0x08014391 8016c34: 080169e3 .word 0x080169e3 08016c38 <__ascii_mbtowc>: 8016c38: b082 sub sp, #8 8016c3a: b901 cbnz r1, 8016c3e <__ascii_mbtowc+0x6> 8016c3c: a901 add r1, sp, #4 8016c3e: b142 cbz r2, 8016c52 <__ascii_mbtowc+0x1a> 8016c40: b14b cbz r3, 8016c56 <__ascii_mbtowc+0x1e> 8016c42: 7813 ldrb r3, [r2, #0] 8016c44: 600b str r3, [r1, #0] 8016c46: 7812 ldrb r2, [r2, #0] 8016c48: 1e10 subs r0, r2, #0 8016c4a: bf18 it ne 8016c4c: 2001 movne r0, #1 8016c4e: b002 add sp, #8 8016c50: 4770 bx lr 8016c52: 4610 mov r0, r2 8016c54: e7fb b.n 8016c4e <__ascii_mbtowc+0x16> 8016c56: f06f 0001 mvn.w r0, #1 8016c5a: e7f8 b.n 8016c4e <__ascii_mbtowc+0x16> 08016c5c <_malloc_usable_size_r>: 8016c5c: f851 3c04 ldr.w r3, [r1, #-4] 8016c60: 1f18 subs r0, r3, #4 8016c62: 2b00 cmp r3, #0 8016c64: bfbc itt lt 8016c66: 580b ldrlt r3, [r1, r0] 8016c68: 18c0 addlt r0, r0, r3 8016c6a: 4770 bx lr 08016c6c <__swbuf_r>: 8016c6c: b5f8 push {r3, r4, r5, r6, r7, lr} 8016c6e: 460e mov r6, r1 8016c70: 4614 mov r4, r2 8016c72: 4605 mov r5, r0 8016c74: b118 cbz r0, 8016c7e <__swbuf_r+0x12> 8016c76: 6a03 ldr r3, [r0, #32] 8016c78: b90b cbnz r3, 8016c7e <__swbuf_r+0x12> 8016c7a: f7fd ffd1 bl 8014c20 <__sinit> 8016c7e: 69a3 ldr r3, [r4, #24] 8016c80: 60a3 str r3, [r4, #8] 8016c82: 89a3 ldrh r3, [r4, #12] 8016c84: 071a lsls r2, r3, #28 8016c86: d501 bpl.n 8016c8c <__swbuf_r+0x20> 8016c88: 6923 ldr r3, [r4, #16] 8016c8a: b943 cbnz r3, 8016c9e <__swbuf_r+0x32> 8016c8c: 4621 mov r1, r4 8016c8e: 4628 mov r0, r5 8016c90: f000 f82a bl 8016ce8 <__swsetup_r> 8016c94: b118 cbz r0, 8016c9e <__swbuf_r+0x32> 8016c96: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff 8016c9a: 4638 mov r0, r7 8016c9c: bdf8 pop {r3, r4, r5, r6, r7, pc} 8016c9e: 6823 ldr r3, [r4, #0] 8016ca0: 6922 ldr r2, [r4, #16] 8016ca2: b2f6 uxtb r6, r6 8016ca4: 1a98 subs r0, r3, r2 8016ca6: 6963 ldr r3, [r4, #20] 8016ca8: 4637 mov r7, r6 8016caa: 4283 cmp r3, r0 8016cac: dc05 bgt.n 8016cba <__swbuf_r+0x4e> 8016cae: 4621 mov r1, r4 8016cb0: 4628 mov r0, r5 8016cb2: f7ff f97b bl 8015fac <_fflush_r> 8016cb6: 2800 cmp r0, #0 8016cb8: d1ed bne.n 8016c96 <__swbuf_r+0x2a> 8016cba: 68a3 ldr r3, [r4, #8] 8016cbc: 3b01 subs r3, #1 8016cbe: 60a3 str r3, [r4, #8] 8016cc0: 6823 ldr r3, [r4, #0] 8016cc2: 1c5a adds r2, r3, #1 8016cc4: 6022 str r2, [r4, #0] 8016cc6: 701e strb r6, [r3, #0] 8016cc8: 6962 ldr r2, [r4, #20] 8016cca: 1c43 adds r3, r0, #1 8016ccc: 429a cmp r2, r3 8016cce: d004 beq.n 8016cda <__swbuf_r+0x6e> 8016cd0: 89a3 ldrh r3, [r4, #12] 8016cd2: 07db lsls r3, r3, #31 8016cd4: d5e1 bpl.n 8016c9a <__swbuf_r+0x2e> 8016cd6: 2e0a cmp r6, #10 8016cd8: d1df bne.n 8016c9a <__swbuf_r+0x2e> 8016cda: 4621 mov r1, r4 8016cdc: 4628 mov r0, r5 8016cde: f7ff f965 bl 8015fac <_fflush_r> 8016ce2: 2800 cmp r0, #0 8016ce4: d0d9 beq.n 8016c9a <__swbuf_r+0x2e> 8016ce6: e7d6 b.n 8016c96 <__swbuf_r+0x2a> 08016ce8 <__swsetup_r>: 8016ce8: b538 push {r3, r4, r5, lr} 8016cea: 4b29 ldr r3, [pc, #164] @ (8016d90 <__swsetup_r+0xa8>) 8016cec: 4605 mov r5, r0 8016cee: 6818 ldr r0, [r3, #0] 8016cf0: 460c mov r4, r1 8016cf2: b118 cbz r0, 8016cfc <__swsetup_r+0x14> 8016cf4: 6a03 ldr r3, [r0, #32] 8016cf6: b90b cbnz r3, 8016cfc <__swsetup_r+0x14> 8016cf8: f7fd ff92 bl 8014c20 <__sinit> 8016cfc: f9b4 300c ldrsh.w r3, [r4, #12] 8016d00: 0719 lsls r1, r3, #28 8016d02: d422 bmi.n 8016d4a <__swsetup_r+0x62> 8016d04: 06da lsls r2, r3, #27 8016d06: d407 bmi.n 8016d18 <__swsetup_r+0x30> 8016d08: 2209 movs r2, #9 8016d0a: 602a str r2, [r5, #0] 8016d0c: f043 0340 orr.w r3, r3, #64 @ 0x40 8016d10: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016d14: 81a3 strh r3, [r4, #12] 8016d16: e033 b.n 8016d80 <__swsetup_r+0x98> 8016d18: 0758 lsls r0, r3, #29 8016d1a: d512 bpl.n 8016d42 <__swsetup_r+0x5a> 8016d1c: 6b61 ldr r1, [r4, #52] @ 0x34 8016d1e: b141 cbz r1, 8016d32 <__swsetup_r+0x4a> 8016d20: f104 0344 add.w r3, r4, #68 @ 0x44 8016d24: 4299 cmp r1, r3 8016d26: d002 beq.n 8016d2e <__swsetup_r+0x46> 8016d28: 4628 mov r0, r5 8016d2a: f7ff fdfd bl 8016928 <_free_r> 8016d2e: 2300 movs r3, #0 8016d30: 6363 str r3, [r4, #52] @ 0x34 8016d32: 89a3 ldrh r3, [r4, #12] 8016d34: f023 0324 bic.w r3, r3, #36 @ 0x24 8016d38: 81a3 strh r3, [r4, #12] 8016d3a: 2300 movs r3, #0 8016d3c: 6063 str r3, [r4, #4] 8016d3e: 6923 ldr r3, [r4, #16] 8016d40: 6023 str r3, [r4, #0] 8016d42: 89a3 ldrh r3, [r4, #12] 8016d44: f043 0308 orr.w r3, r3, #8 8016d48: 81a3 strh r3, [r4, #12] 8016d4a: 6923 ldr r3, [r4, #16] 8016d4c: b94b cbnz r3, 8016d62 <__swsetup_r+0x7a> 8016d4e: 89a3 ldrh r3, [r4, #12] 8016d50: f403 7320 and.w r3, r3, #640 @ 0x280 8016d54: f5b3 7f00 cmp.w r3, #512 @ 0x200 8016d58: d003 beq.n 8016d62 <__swsetup_r+0x7a> 8016d5a: 4621 mov r1, r4 8016d5c: 4628 mov r0, r5 8016d5e: f000 f84b bl 8016df8 <__smakebuf_r> 8016d62: f9b4 300c ldrsh.w r3, [r4, #12] 8016d66: f013 0201 ands.w r2, r3, #1 8016d6a: d00a beq.n 8016d82 <__swsetup_r+0x9a> 8016d6c: 2200 movs r2, #0 8016d6e: 60a2 str r2, [r4, #8] 8016d70: 6962 ldr r2, [r4, #20] 8016d72: 4252 negs r2, r2 8016d74: 61a2 str r2, [r4, #24] 8016d76: 6922 ldr r2, [r4, #16] 8016d78: b942 cbnz r2, 8016d8c <__swsetup_r+0xa4> 8016d7a: f013 0080 ands.w r0, r3, #128 @ 0x80 8016d7e: d1c5 bne.n 8016d0c <__swsetup_r+0x24> 8016d80: bd38 pop {r3, r4, r5, pc} 8016d82: 0799 lsls r1, r3, #30 8016d84: bf58 it pl 8016d86: 6962 ldrpl r2, [r4, #20] 8016d88: 60a2 str r2, [r4, #8] 8016d8a: e7f4 b.n 8016d76 <__swsetup_r+0x8e> 8016d8c: 2000 movs r0, #0 8016d8e: e7f7 b.n 8016d80 <__swsetup_r+0x98> 8016d90: 2000009c .word 0x2000009c 08016d94 <__ascii_wctomb>: 8016d94: 4603 mov r3, r0 8016d96: 4608 mov r0, r1 8016d98: b141 cbz r1, 8016dac <__ascii_wctomb+0x18> 8016d9a: 2aff cmp r2, #255 @ 0xff 8016d9c: d904 bls.n 8016da8 <__ascii_wctomb+0x14> 8016d9e: 228a movs r2, #138 @ 0x8a 8016da0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016da4: 601a str r2, [r3, #0] 8016da6: 4770 bx lr 8016da8: 2001 movs r0, #1 8016daa: 700a strb r2, [r1, #0] 8016dac: 4770 bx lr 08016dae <__swhatbuf_r>: 8016dae: b570 push {r4, r5, r6, lr} 8016db0: 460c mov r4, r1 8016db2: f9b1 100e ldrsh.w r1, [r1, #14] 8016db6: 4615 mov r5, r2 8016db8: 2900 cmp r1, #0 8016dba: 461e mov r6, r3 8016dbc: b096 sub sp, #88 @ 0x58 8016dbe: da0c bge.n 8016dda <__swhatbuf_r+0x2c> 8016dc0: 89a3 ldrh r3, [r4, #12] 8016dc2: 2100 movs r1, #0 8016dc4: f013 0f80 tst.w r3, #128 @ 0x80 8016dc8: bf14 ite ne 8016dca: 2340 movne r3, #64 @ 0x40 8016dcc: f44f 6380 moveq.w r3, #1024 @ 0x400 8016dd0: 2000 movs r0, #0 8016dd2: 6031 str r1, [r6, #0] 8016dd4: 602b str r3, [r5, #0] 8016dd6: b016 add sp, #88 @ 0x58 8016dd8: bd70 pop {r4, r5, r6, pc} 8016dda: 466a mov r2, sp 8016ddc: f000 f89c bl 8016f18 <_fstat_r> 8016de0: 2800 cmp r0, #0 8016de2: dbed blt.n 8016dc0 <__swhatbuf_r+0x12> 8016de4: 9901 ldr r1, [sp, #4] 8016de6: f401 4170 and.w r1, r1, #61440 @ 0xf000 8016dea: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 8016dee: 4259 negs r1, r3 8016df0: 4159 adcs r1, r3 8016df2: f44f 6380 mov.w r3, #1024 @ 0x400 8016df6: e7eb b.n 8016dd0 <__swhatbuf_r+0x22> 08016df8 <__smakebuf_r>: 8016df8: 898b ldrh r3, [r1, #12] 8016dfa: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8016dfc: 079d lsls r5, r3, #30 8016dfe: 4606 mov r6, r0 8016e00: 460c mov r4, r1 8016e02: d507 bpl.n 8016e14 <__smakebuf_r+0x1c> 8016e04: f104 0347 add.w r3, r4, #71 @ 0x47 8016e08: 6023 str r3, [r4, #0] 8016e0a: 6123 str r3, [r4, #16] 8016e0c: 2301 movs r3, #1 8016e0e: 6163 str r3, [r4, #20] 8016e10: b003 add sp, #12 8016e12: bdf0 pop {r4, r5, r6, r7, pc} 8016e14: 466a mov r2, sp 8016e16: ab01 add r3, sp, #4 8016e18: f7ff ffc9 bl 8016dae <__swhatbuf_r> 8016e1c: 9f00 ldr r7, [sp, #0] 8016e1e: 4605 mov r5, r0 8016e20: 4639 mov r1, r7 8016e22: 4630 mov r0, r6 8016e24: f7fe ffc2 bl 8015dac <_malloc_r> 8016e28: b948 cbnz r0, 8016e3e <__smakebuf_r+0x46> 8016e2a: f9b4 300c ldrsh.w r3, [r4, #12] 8016e2e: 059a lsls r2, r3, #22 8016e30: d4ee bmi.n 8016e10 <__smakebuf_r+0x18> 8016e32: f023 0303 bic.w r3, r3, #3 8016e36: f043 0302 orr.w r3, r3, #2 8016e3a: 81a3 strh r3, [r4, #12] 8016e3c: e7e2 b.n 8016e04 <__smakebuf_r+0xc> 8016e3e: 89a3 ldrh r3, [r4, #12] 8016e40: e9c4 0704 strd r0, r7, [r4, #16] 8016e44: f043 0380 orr.w r3, r3, #128 @ 0x80 8016e48: 81a3 strh r3, [r4, #12] 8016e4a: 9b01 ldr r3, [sp, #4] 8016e4c: 6020 str r0, [r4, #0] 8016e4e: b15b cbz r3, 8016e68 <__smakebuf_r+0x70> 8016e50: 4630 mov r0, r6 8016e52: f9b4 100e ldrsh.w r1, [r4, #14] 8016e56: f000 f83b bl 8016ed0 <_isatty_r> 8016e5a: b128 cbz r0, 8016e68 <__smakebuf_r+0x70> 8016e5c: 89a3 ldrh r3, [r4, #12] 8016e5e: f023 0303 bic.w r3, r3, #3 8016e62: f043 0301 orr.w r3, r3, #1 8016e66: 81a3 strh r3, [r4, #12] 8016e68: 89a3 ldrh r3, [r4, #12] 8016e6a: 431d orrs r5, r3 8016e6c: 81a5 strh r5, [r4, #12] 8016e6e: e7cf b.n 8016e10 <__smakebuf_r+0x18> 08016e70 <_raise_r>: 8016e70: 291f cmp r1, #31 8016e72: b538 push {r3, r4, r5, lr} 8016e74: 4605 mov r5, r0 8016e76: 460c mov r4, r1 8016e78: d904 bls.n 8016e84 <_raise_r+0x14> 8016e7a: 2316 movs r3, #22 8016e7c: 6003 str r3, [r0, #0] 8016e7e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8016e82: bd38 pop {r3, r4, r5, pc} 8016e84: 6bc2 ldr r2, [r0, #60] @ 0x3c 8016e86: b112 cbz r2, 8016e8e <_raise_r+0x1e> 8016e88: f852 3021 ldr.w r3, [r2, r1, lsl #2] 8016e8c: b94b cbnz r3, 8016ea2 <_raise_r+0x32> 8016e8e: 4628 mov r0, r5 8016e90: f000 f840 bl 8016f14 <_getpid_r> 8016e94: 4622 mov r2, r4 8016e96: 4601 mov r1, r0 8016e98: 4628 mov r0, r5 8016e9a: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8016e9e: f000 b827 b.w 8016ef0 <_kill_r> 8016ea2: 2b01 cmp r3, #1 8016ea4: d00a beq.n 8016ebc <_raise_r+0x4c> 8016ea6: 1c59 adds r1, r3, #1 8016ea8: d103 bne.n 8016eb2 <_raise_r+0x42> 8016eaa: 2316 movs r3, #22 8016eac: 6003 str r3, [r0, #0] 8016eae: 2001 movs r0, #1 8016eb0: e7e7 b.n 8016e82 <_raise_r+0x12> 8016eb2: 2100 movs r1, #0 8016eb4: 4620 mov r0, r4 8016eb6: f842 1024 str.w r1, [r2, r4, lsl #2] 8016eba: 4798 blx r3 8016ebc: 2000 movs r0, #0 8016ebe: e7e0 b.n 8016e82 <_raise_r+0x12> 08016ec0 : 8016ec0: 4b02 ldr r3, [pc, #8] @ (8016ecc ) 8016ec2: 4601 mov r1, r0 8016ec4: 6818 ldr r0, [r3, #0] 8016ec6: f7ff bfd3 b.w 8016e70 <_raise_r> 8016eca: bf00 nop 8016ecc: 2000009c .word 0x2000009c 08016ed0 <_isatty_r>: 8016ed0: b538 push {r3, r4, r5, lr} 8016ed2: 2300 movs r3, #0 8016ed4: 4d05 ldr r5, [pc, #20] @ (8016eec <_isatty_r+0x1c>) 8016ed6: 4604 mov r4, r0 8016ed8: 4608 mov r0, r1 8016eda: 602b str r3, [r5, #0] 8016edc: f7f6 fd27 bl 800d92e <_isatty> 8016ee0: 1c43 adds r3, r0, #1 8016ee2: d102 bne.n 8016eea <_isatty_r+0x1a> 8016ee4: 682b ldr r3, [r5, #0] 8016ee6: b103 cbz r3, 8016eea <_isatty_r+0x1a> 8016ee8: 6023 str r3, [r4, #0] 8016eea: bd38 pop {r3, r4, r5, pc} 8016eec: 200015d4 .word 0x200015d4 08016ef0 <_kill_r>: 8016ef0: b538 push {r3, r4, r5, lr} 8016ef2: 2300 movs r3, #0 8016ef4: 4d06 ldr r5, [pc, #24] @ (8016f10 <_kill_r+0x20>) 8016ef6: 4604 mov r4, r0 8016ef8: 4608 mov r0, r1 8016efa: 4611 mov r1, r2 8016efc: 602b str r3, [r5, #0] 8016efe: f7f6 fcc4 bl 800d88a <_kill> 8016f02: 1c43 adds r3, r0, #1 8016f04: d102 bne.n 8016f0c <_kill_r+0x1c> 8016f06: 682b ldr r3, [r5, #0] 8016f08: b103 cbz r3, 8016f0c <_kill_r+0x1c> 8016f0a: 6023 str r3, [r4, #0] 8016f0c: bd38 pop {r3, r4, r5, pc} 8016f0e: bf00 nop 8016f10: 200015d4 .word 0x200015d4 08016f14 <_getpid_r>: 8016f14: f7f6 bcb2 b.w 800d87c <_getpid> 08016f18 <_fstat_r>: 8016f18: b538 push {r3, r4, r5, lr} 8016f1a: 2300 movs r3, #0 8016f1c: 4d06 ldr r5, [pc, #24] @ (8016f38 <_fstat_r+0x20>) 8016f1e: 4604 mov r4, r0 8016f20: 4608 mov r0, r1 8016f22: 4611 mov r1, r2 8016f24: 602b str r3, [r5, #0] 8016f26: f7f6 fcf3 bl 800d910 <_fstat> 8016f2a: 1c43 adds r3, r0, #1 8016f2c: d102 bne.n 8016f34 <_fstat_r+0x1c> 8016f2e: 682b ldr r3, [r5, #0] 8016f30: b103 cbz r3, 8016f34 <_fstat_r+0x1c> 8016f32: 6023 str r3, [r4, #0] 8016f34: bd38 pop {r3, r4, r5, pc} 8016f36: bf00 nop 8016f38: 200015d4 .word 0x200015d4 08016f3c <_init>: 8016f3c: b5f8 push {r3, r4, r5, r6, r7, lr} 8016f3e: bf00 nop 8016f40: bcf8 pop {r3, r4, r5, r6, r7} 8016f42: bc08 pop {r3} 8016f44: 469e mov lr, r3 8016f46: 4770 bx lr 08016f48 <_fini>: 8016f48: b5f8 push {r3, r4, r5, r6, r7, lr} 8016f4a: bf00 nop 8016f4c: bcf8 pop {r3, r4, r5, r6, r7} 8016f4e: bc08 pop {r3} 8016f50: 469e mov lr, r3 8016f52: 4770 bx lr