GbTModuleSW.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001e4 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000087f8 080001e4 080001e4 000101e4 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000588 080089dc 080089dc 000189dc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08008f64 08008f64 00020070 2**0 CONTENTS 4 .ARM 00000008 08008f64 08008f64 00018f64 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 08008f6c 08008f6c 00020070 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08008f6c 08008f6c 00018f6c 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08008f70 08008f70 00018f70 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000070 20000000 08008f74 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00003118 20000070 08008fe4 00020070 2**2 ALLOC 10 ._user_heap_stack 00000600 20003188 08008fe4 00023188 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 00020070 2**0 CONTENTS, READONLY 12 .debug_info 0000f213 00000000 00000000 00020099 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00003561 00000000 00000000 0002f2ac 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000de0 00000000 00000000 00032810 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_ranges 00000c58 00000000 00000000 000335f0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 000228d6 00000000 00000000 00034248 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 00012c76 00000000 00000000 00056b1e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000bcad8 00000000 00000000 00069794 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000050 00000000 00000000 0012626c 2**0 CONTENTS, READONLY 20 .debug_frame 00004234 00000000 00000000 001262bc 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001e4 <__do_global_dtors_aux>: 80001e4: b510 push {r4, lr} 80001e6: 4c05 ldr r4, [pc, #20] ; (80001fc <__do_global_dtors_aux+0x18>) 80001e8: 7823 ldrb r3, [r4, #0] 80001ea: b933 cbnz r3, 80001fa <__do_global_dtors_aux+0x16> 80001ec: 4b04 ldr r3, [pc, #16] ; (8000200 <__do_global_dtors_aux+0x1c>) 80001ee: b113 cbz r3, 80001f6 <__do_global_dtors_aux+0x12> 80001f0: 4804 ldr r0, [pc, #16] ; (8000204 <__do_global_dtors_aux+0x20>) 80001f2: f3af 8000 nop.w 80001f6: 2301 movs r3, #1 80001f8: 7023 strb r3, [r4, #0] 80001fa: bd10 pop {r4, pc} 80001fc: 20000070 .word 0x20000070 8000200: 00000000 .word 0x00000000 8000204: 080089c4 .word 0x080089c4 08000208 : 8000208: b508 push {r3, lr} 800020a: 4b03 ldr r3, [pc, #12] ; (8000218 ) 800020c: b11b cbz r3, 8000216 800020e: 4903 ldr r1, [pc, #12] ; (800021c ) 8000210: 4803 ldr r0, [pc, #12] ; (8000220 ) 8000212: f3af 8000 nop.w 8000216: bd08 pop {r3, pc} 8000218: 00000000 .word 0x00000000 800021c: 20000074 .word 0x20000074 8000220: 080089c4 .word 0x080089c4 08000224 <__aeabi_drsub>: 8000224: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 8000228: e002 b.n 8000230 <__adddf3> 800022a: bf00 nop 0800022c <__aeabi_dsub>: 800022c: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 08000230 <__adddf3>: 8000230: b530 push {r4, r5, lr} 8000232: ea4f 0441 mov.w r4, r1, lsl #1 8000236: ea4f 0543 mov.w r5, r3, lsl #1 800023a: ea94 0f05 teq r4, r5 800023e: bf08 it eq 8000240: ea90 0f02 teqeq r0, r2 8000244: bf1f itttt ne 8000246: ea54 0c00 orrsne.w ip, r4, r0 800024a: ea55 0c02 orrsne.w ip, r5, r2 800024e: ea7f 5c64 mvnsne.w ip, r4, asr #21 8000252: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000256: f000 80e2 beq.w 800041e <__adddf3+0x1ee> 800025a: ea4f 5454 mov.w r4, r4, lsr #21 800025e: ebd4 5555 rsbs r5, r4, r5, lsr #21 8000262: bfb8 it lt 8000264: 426d neglt r5, r5 8000266: dd0c ble.n 8000282 <__adddf3+0x52> 8000268: 442c add r4, r5 800026a: ea80 0202 eor.w r2, r0, r2 800026e: ea81 0303 eor.w r3, r1, r3 8000272: ea82 0000 eor.w r0, r2, r0 8000276: ea83 0101 eor.w r1, r3, r1 800027a: ea80 0202 eor.w r2, r0, r2 800027e: ea81 0303 eor.w r3, r1, r3 8000282: 2d36 cmp r5, #54 ; 0x36 8000284: bf88 it hi 8000286: bd30 pophi {r4, r5, pc} 8000288: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 800028c: ea4f 3101 mov.w r1, r1, lsl #12 8000290: f44f 1c80 mov.w ip, #1048576 ; 0x100000 8000294: ea4c 3111 orr.w r1, ip, r1, lsr #12 8000298: d002 beq.n 80002a0 <__adddf3+0x70> 800029a: 4240 negs r0, r0 800029c: eb61 0141 sbc.w r1, r1, r1, lsl #1 80002a0: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 80002a4: ea4f 3303 mov.w r3, r3, lsl #12 80002a8: ea4c 3313 orr.w r3, ip, r3, lsr #12 80002ac: d002 beq.n 80002b4 <__adddf3+0x84> 80002ae: 4252 negs r2, r2 80002b0: eb63 0343 sbc.w r3, r3, r3, lsl #1 80002b4: ea94 0f05 teq r4, r5 80002b8: f000 80a7 beq.w 800040a <__adddf3+0x1da> 80002bc: f1a4 0401 sub.w r4, r4, #1 80002c0: f1d5 0e20 rsbs lr, r5, #32 80002c4: db0d blt.n 80002e2 <__adddf3+0xb2> 80002c6: fa02 fc0e lsl.w ip, r2, lr 80002ca: fa22 f205 lsr.w r2, r2, r5 80002ce: 1880 adds r0, r0, r2 80002d0: f141 0100 adc.w r1, r1, #0 80002d4: fa03 f20e lsl.w r2, r3, lr 80002d8: 1880 adds r0, r0, r2 80002da: fa43 f305 asr.w r3, r3, r5 80002de: 4159 adcs r1, r3 80002e0: e00e b.n 8000300 <__adddf3+0xd0> 80002e2: f1a5 0520 sub.w r5, r5, #32 80002e6: f10e 0e20 add.w lr, lr, #32 80002ea: 2a01 cmp r2, #1 80002ec: fa03 fc0e lsl.w ip, r3, lr 80002f0: bf28 it cs 80002f2: f04c 0c02 orrcs.w ip, ip, #2 80002f6: fa43 f305 asr.w r3, r3, r5 80002fa: 18c0 adds r0, r0, r3 80002fc: eb51 71e3 adcs.w r1, r1, r3, asr #31 8000300: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000304: d507 bpl.n 8000316 <__adddf3+0xe6> 8000306: f04f 0e00 mov.w lr, #0 800030a: f1dc 0c00 rsbs ip, ip, #0 800030e: eb7e 0000 sbcs.w r0, lr, r0 8000312: eb6e 0101 sbc.w r1, lr, r1 8000316: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 800031a: d31b bcc.n 8000354 <__adddf3+0x124> 800031c: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 8000320: d30c bcc.n 800033c <__adddf3+0x10c> 8000322: 0849 lsrs r1, r1, #1 8000324: ea5f 0030 movs.w r0, r0, rrx 8000328: ea4f 0c3c mov.w ip, ip, rrx 800032c: f104 0401 add.w r4, r4, #1 8000330: ea4f 5244 mov.w r2, r4, lsl #21 8000334: f512 0f80 cmn.w r2, #4194304 ; 0x400000 8000338: f080 809a bcs.w 8000470 <__adddf3+0x240> 800033c: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 8000340: bf08 it eq 8000342: ea5f 0c50 movseq.w ip, r0, lsr #1 8000346: f150 0000 adcs.w r0, r0, #0 800034a: eb41 5104 adc.w r1, r1, r4, lsl #20 800034e: ea41 0105 orr.w r1, r1, r5 8000352: bd30 pop {r4, r5, pc} 8000354: ea5f 0c4c movs.w ip, ip, lsl #1 8000358: 4140 adcs r0, r0 800035a: eb41 0101 adc.w r1, r1, r1 800035e: 3c01 subs r4, #1 8000360: bf28 it cs 8000362: f5b1 1f80 cmpcs.w r1, #1048576 ; 0x100000 8000366: d2e9 bcs.n 800033c <__adddf3+0x10c> 8000368: f091 0f00 teq r1, #0 800036c: bf04 itt eq 800036e: 4601 moveq r1, r0 8000370: 2000 moveq r0, #0 8000372: fab1 f381 clz r3, r1 8000376: bf08 it eq 8000378: 3320 addeq r3, #32 800037a: f1a3 030b sub.w r3, r3, #11 800037e: f1b3 0220 subs.w r2, r3, #32 8000382: da0c bge.n 800039e <__adddf3+0x16e> 8000384: 320c adds r2, #12 8000386: dd08 ble.n 800039a <__adddf3+0x16a> 8000388: f102 0c14 add.w ip, r2, #20 800038c: f1c2 020c rsb r2, r2, #12 8000390: fa01 f00c lsl.w r0, r1, ip 8000394: fa21 f102 lsr.w r1, r1, r2 8000398: e00c b.n 80003b4 <__adddf3+0x184> 800039a: f102 0214 add.w r2, r2, #20 800039e: bfd8 it le 80003a0: f1c2 0c20 rsble ip, r2, #32 80003a4: fa01 f102 lsl.w r1, r1, r2 80003a8: fa20 fc0c lsr.w ip, r0, ip 80003ac: bfdc itt le 80003ae: ea41 010c orrle.w r1, r1, ip 80003b2: 4090 lslle r0, r2 80003b4: 1ae4 subs r4, r4, r3 80003b6: bfa2 ittt ge 80003b8: eb01 5104 addge.w r1, r1, r4, lsl #20 80003bc: 4329 orrge r1, r5 80003be: bd30 popge {r4, r5, pc} 80003c0: ea6f 0404 mvn.w r4, r4 80003c4: 3c1f subs r4, #31 80003c6: da1c bge.n 8000402 <__adddf3+0x1d2> 80003c8: 340c adds r4, #12 80003ca: dc0e bgt.n 80003ea <__adddf3+0x1ba> 80003cc: f104 0414 add.w r4, r4, #20 80003d0: f1c4 0220 rsb r2, r4, #32 80003d4: fa20 f004 lsr.w r0, r0, r4 80003d8: fa01 f302 lsl.w r3, r1, r2 80003dc: ea40 0003 orr.w r0, r0, r3 80003e0: fa21 f304 lsr.w r3, r1, r4 80003e4: ea45 0103 orr.w r1, r5, r3 80003e8: bd30 pop {r4, r5, pc} 80003ea: f1c4 040c rsb r4, r4, #12 80003ee: f1c4 0220 rsb r2, r4, #32 80003f2: fa20 f002 lsr.w r0, r0, r2 80003f6: fa01 f304 lsl.w r3, r1, r4 80003fa: ea40 0003 orr.w r0, r0, r3 80003fe: 4629 mov r1, r5 8000400: bd30 pop {r4, r5, pc} 8000402: fa21 f004 lsr.w r0, r1, r4 8000406: 4629 mov r1, r5 8000408: bd30 pop {r4, r5, pc} 800040a: f094 0f00 teq r4, #0 800040e: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 8000412: bf06 itte eq 8000414: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 8000418: 3401 addeq r4, #1 800041a: 3d01 subne r5, #1 800041c: e74e b.n 80002bc <__adddf3+0x8c> 800041e: ea7f 5c64 mvns.w ip, r4, asr #21 8000422: bf18 it ne 8000424: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000428: d029 beq.n 800047e <__adddf3+0x24e> 800042a: ea94 0f05 teq r4, r5 800042e: bf08 it eq 8000430: ea90 0f02 teqeq r0, r2 8000434: d005 beq.n 8000442 <__adddf3+0x212> 8000436: ea54 0c00 orrs.w ip, r4, r0 800043a: bf04 itt eq 800043c: 4619 moveq r1, r3 800043e: 4610 moveq r0, r2 8000440: bd30 pop {r4, r5, pc} 8000442: ea91 0f03 teq r1, r3 8000446: bf1e ittt ne 8000448: 2100 movne r1, #0 800044a: 2000 movne r0, #0 800044c: bd30 popne {r4, r5, pc} 800044e: ea5f 5c54 movs.w ip, r4, lsr #21 8000452: d105 bne.n 8000460 <__adddf3+0x230> 8000454: 0040 lsls r0, r0, #1 8000456: 4149 adcs r1, r1 8000458: bf28 it cs 800045a: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 800045e: bd30 pop {r4, r5, pc} 8000460: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 8000464: bf3c itt cc 8000466: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 800046a: bd30 popcc {r4, r5, pc} 800046c: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000470: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 8000474: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 8000478: f04f 0000 mov.w r0, #0 800047c: bd30 pop {r4, r5, pc} 800047e: ea7f 5c64 mvns.w ip, r4, asr #21 8000482: bf1a itte ne 8000484: 4619 movne r1, r3 8000486: 4610 movne r0, r2 8000488: ea7f 5c65 mvnseq.w ip, r5, asr #21 800048c: bf1c itt ne 800048e: 460b movne r3, r1 8000490: 4602 movne r2, r0 8000492: ea50 3401 orrs.w r4, r0, r1, lsl #12 8000496: bf06 itte eq 8000498: ea52 3503 orrseq.w r5, r2, r3, lsl #12 800049c: ea91 0f03 teqeq r1, r3 80004a0: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 80004a4: bd30 pop {r4, r5, pc} 80004a6: bf00 nop 080004a8 <__aeabi_ui2d>: 80004a8: f090 0f00 teq r0, #0 80004ac: bf04 itt eq 80004ae: 2100 moveq r1, #0 80004b0: 4770 bxeq lr 80004b2: b530 push {r4, r5, lr} 80004b4: f44f 6480 mov.w r4, #1024 ; 0x400 80004b8: f104 0432 add.w r4, r4, #50 ; 0x32 80004bc: f04f 0500 mov.w r5, #0 80004c0: f04f 0100 mov.w r1, #0 80004c4: e750 b.n 8000368 <__adddf3+0x138> 80004c6: bf00 nop 080004c8 <__aeabi_i2d>: 80004c8: f090 0f00 teq r0, #0 80004cc: bf04 itt eq 80004ce: 2100 moveq r1, #0 80004d0: 4770 bxeq lr 80004d2: b530 push {r4, r5, lr} 80004d4: f44f 6480 mov.w r4, #1024 ; 0x400 80004d8: f104 0432 add.w r4, r4, #50 ; 0x32 80004dc: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 80004e0: bf48 it mi 80004e2: 4240 negmi r0, r0 80004e4: f04f 0100 mov.w r1, #0 80004e8: e73e b.n 8000368 <__adddf3+0x138> 80004ea: bf00 nop 080004ec <__aeabi_f2d>: 80004ec: 0042 lsls r2, r0, #1 80004ee: ea4f 01e2 mov.w r1, r2, asr #3 80004f2: ea4f 0131 mov.w r1, r1, rrx 80004f6: ea4f 7002 mov.w r0, r2, lsl #28 80004fa: bf1f itttt ne 80004fc: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 8000500: f093 4f7f teqne r3, #4278190080 ; 0xff000000 8000504: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 8000508: 4770 bxne lr 800050a: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 800050e: bf08 it eq 8000510: 4770 bxeq lr 8000512: f093 4f7f teq r3, #4278190080 ; 0xff000000 8000516: bf04 itt eq 8000518: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 800051c: 4770 bxeq lr 800051e: b530 push {r4, r5, lr} 8000520: f44f 7460 mov.w r4, #896 ; 0x380 8000524: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000528: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 800052c: e71c b.n 8000368 <__adddf3+0x138> 800052e: bf00 nop 08000530 <__aeabi_ul2d>: 8000530: ea50 0201 orrs.w r2, r0, r1 8000534: bf08 it eq 8000536: 4770 bxeq lr 8000538: b530 push {r4, r5, lr} 800053a: f04f 0500 mov.w r5, #0 800053e: e00a b.n 8000556 <__aeabi_l2d+0x16> 08000540 <__aeabi_l2d>: 8000540: ea50 0201 orrs.w r2, r0, r1 8000544: bf08 it eq 8000546: 4770 bxeq lr 8000548: b530 push {r4, r5, lr} 800054a: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 800054e: d502 bpl.n 8000556 <__aeabi_l2d+0x16> 8000550: 4240 negs r0, r0 8000552: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000556: f44f 6480 mov.w r4, #1024 ; 0x400 800055a: f104 0432 add.w r4, r4, #50 ; 0x32 800055e: ea5f 5c91 movs.w ip, r1, lsr #22 8000562: f43f aed8 beq.w 8000316 <__adddf3+0xe6> 8000566: f04f 0203 mov.w r2, #3 800056a: ea5f 0cdc movs.w ip, ip, lsr #3 800056e: bf18 it ne 8000570: 3203 addne r2, #3 8000572: ea5f 0cdc movs.w ip, ip, lsr #3 8000576: bf18 it ne 8000578: 3203 addne r2, #3 800057a: eb02 02dc add.w r2, r2, ip, lsr #3 800057e: f1c2 0320 rsb r3, r2, #32 8000582: fa00 fc03 lsl.w ip, r0, r3 8000586: fa20 f002 lsr.w r0, r0, r2 800058a: fa01 fe03 lsl.w lr, r1, r3 800058e: ea40 000e orr.w r0, r0, lr 8000592: fa21 f102 lsr.w r1, r1, r2 8000596: 4414 add r4, r2 8000598: e6bd b.n 8000316 <__adddf3+0xe6> 800059a: bf00 nop 0800059c <__aeabi_frsub>: 800059c: f080 4000 eor.w r0, r0, #2147483648 ; 0x80000000 80005a0: e002 b.n 80005a8 <__addsf3> 80005a2: bf00 nop 080005a4 <__aeabi_fsub>: 80005a4: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 080005a8 <__addsf3>: 80005a8: 0042 lsls r2, r0, #1 80005aa: bf1f itttt ne 80005ac: ea5f 0341 movsne.w r3, r1, lsl #1 80005b0: ea92 0f03 teqne r2, r3 80005b4: ea7f 6c22 mvnsne.w ip, r2, asr #24 80005b8: ea7f 6c23 mvnsne.w ip, r3, asr #24 80005bc: d06a beq.n 8000694 <__addsf3+0xec> 80005be: ea4f 6212 mov.w r2, r2, lsr #24 80005c2: ebd2 6313 rsbs r3, r2, r3, lsr #24 80005c6: bfc1 itttt gt 80005c8: 18d2 addgt r2, r2, r3 80005ca: 4041 eorgt r1, r0 80005cc: 4048 eorgt r0, r1 80005ce: 4041 eorgt r1, r0 80005d0: bfb8 it lt 80005d2: 425b neglt r3, r3 80005d4: 2b19 cmp r3, #25 80005d6: bf88 it hi 80005d8: 4770 bxhi lr 80005da: f010 4f00 tst.w r0, #2147483648 ; 0x80000000 80005de: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 80005e2: f020 407f bic.w r0, r0, #4278190080 ; 0xff000000 80005e6: bf18 it ne 80005e8: 4240 negne r0, r0 80005ea: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 80005ee: f441 0100 orr.w r1, r1, #8388608 ; 0x800000 80005f2: f021 417f bic.w r1, r1, #4278190080 ; 0xff000000 80005f6: bf18 it ne 80005f8: 4249 negne r1, r1 80005fa: ea92 0f03 teq r2, r3 80005fe: d03f beq.n 8000680 <__addsf3+0xd8> 8000600: f1a2 0201 sub.w r2, r2, #1 8000604: fa41 fc03 asr.w ip, r1, r3 8000608: eb10 000c adds.w r0, r0, ip 800060c: f1c3 0320 rsb r3, r3, #32 8000610: fa01 f103 lsl.w r1, r1, r3 8000614: f000 4300 and.w r3, r0, #2147483648 ; 0x80000000 8000618: d502 bpl.n 8000620 <__addsf3+0x78> 800061a: 4249 negs r1, r1 800061c: eb60 0040 sbc.w r0, r0, r0, lsl #1 8000620: f5b0 0f00 cmp.w r0, #8388608 ; 0x800000 8000624: d313 bcc.n 800064e <__addsf3+0xa6> 8000626: f1b0 7f80 cmp.w r0, #16777216 ; 0x1000000 800062a: d306 bcc.n 800063a <__addsf3+0x92> 800062c: 0840 lsrs r0, r0, #1 800062e: ea4f 0131 mov.w r1, r1, rrx 8000632: f102 0201 add.w r2, r2, #1 8000636: 2afe cmp r2, #254 ; 0xfe 8000638: d251 bcs.n 80006de <__addsf3+0x136> 800063a: f1b1 4f00 cmp.w r1, #2147483648 ; 0x80000000 800063e: eb40 50c2 adc.w r0, r0, r2, lsl #23 8000642: bf08 it eq 8000644: f020 0001 biceq.w r0, r0, #1 8000648: ea40 0003 orr.w r0, r0, r3 800064c: 4770 bx lr 800064e: 0049 lsls r1, r1, #1 8000650: eb40 0000 adc.w r0, r0, r0 8000654: 3a01 subs r2, #1 8000656: bf28 it cs 8000658: f5b0 0f00 cmpcs.w r0, #8388608 ; 0x800000 800065c: d2ed bcs.n 800063a <__addsf3+0x92> 800065e: fab0 fc80 clz ip, r0 8000662: f1ac 0c08 sub.w ip, ip, #8 8000666: ebb2 020c subs.w r2, r2, ip 800066a: fa00 f00c lsl.w r0, r0, ip 800066e: bfaa itet ge 8000670: eb00 50c2 addge.w r0, r0, r2, lsl #23 8000674: 4252 neglt r2, r2 8000676: 4318 orrge r0, r3 8000678: bfbc itt lt 800067a: 40d0 lsrlt r0, r2 800067c: 4318 orrlt r0, r3 800067e: 4770 bx lr 8000680: f092 0f00 teq r2, #0 8000684: f481 0100 eor.w r1, r1, #8388608 ; 0x800000 8000688: bf06 itte eq 800068a: f480 0000 eoreq.w r0, r0, #8388608 ; 0x800000 800068e: 3201 addeq r2, #1 8000690: 3b01 subne r3, #1 8000692: e7b5 b.n 8000600 <__addsf3+0x58> 8000694: ea4f 0341 mov.w r3, r1, lsl #1 8000698: ea7f 6c22 mvns.w ip, r2, asr #24 800069c: bf18 it ne 800069e: ea7f 6c23 mvnsne.w ip, r3, asr #24 80006a2: d021 beq.n 80006e8 <__addsf3+0x140> 80006a4: ea92 0f03 teq r2, r3 80006a8: d004 beq.n 80006b4 <__addsf3+0x10c> 80006aa: f092 0f00 teq r2, #0 80006ae: bf08 it eq 80006b0: 4608 moveq r0, r1 80006b2: 4770 bx lr 80006b4: ea90 0f01 teq r0, r1 80006b8: bf1c itt ne 80006ba: 2000 movne r0, #0 80006bc: 4770 bxne lr 80006be: f012 4f7f tst.w r2, #4278190080 ; 0xff000000 80006c2: d104 bne.n 80006ce <__addsf3+0x126> 80006c4: 0040 lsls r0, r0, #1 80006c6: bf28 it cs 80006c8: f040 4000 orrcs.w r0, r0, #2147483648 ; 0x80000000 80006cc: 4770 bx lr 80006ce: f112 7200 adds.w r2, r2, #33554432 ; 0x2000000 80006d2: bf3c itt cc 80006d4: f500 0000 addcc.w r0, r0, #8388608 ; 0x800000 80006d8: 4770 bxcc lr 80006da: f000 4300 and.w r3, r0, #2147483648 ; 0x80000000 80006de: f043 40fe orr.w r0, r3, #2130706432 ; 0x7f000000 80006e2: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 80006e6: 4770 bx lr 80006e8: ea7f 6222 mvns.w r2, r2, asr #24 80006ec: bf16 itet ne 80006ee: 4608 movne r0, r1 80006f0: ea7f 6323 mvnseq.w r3, r3, asr #24 80006f4: 4601 movne r1, r0 80006f6: 0242 lsls r2, r0, #9 80006f8: bf06 itte eq 80006fa: ea5f 2341 movseq.w r3, r1, lsl #9 80006fe: ea90 0f01 teqeq r0, r1 8000702: f440 0080 orrne.w r0, r0, #4194304 ; 0x400000 8000706: 4770 bx lr 08000708 <__aeabi_ui2f>: 8000708: f04f 0300 mov.w r3, #0 800070c: e004 b.n 8000718 <__aeabi_i2f+0x8> 800070e: bf00 nop 08000710 <__aeabi_i2f>: 8000710: f010 4300 ands.w r3, r0, #2147483648 ; 0x80000000 8000714: bf48 it mi 8000716: 4240 negmi r0, r0 8000718: ea5f 0c00 movs.w ip, r0 800071c: bf08 it eq 800071e: 4770 bxeq lr 8000720: f043 4396 orr.w r3, r3, #1258291200 ; 0x4b000000 8000724: 4601 mov r1, r0 8000726: f04f 0000 mov.w r0, #0 800072a: e01c b.n 8000766 <__aeabi_l2f+0x2a> 0800072c <__aeabi_ul2f>: 800072c: ea50 0201 orrs.w r2, r0, r1 8000730: bf08 it eq 8000732: 4770 bxeq lr 8000734: f04f 0300 mov.w r3, #0 8000738: e00a b.n 8000750 <__aeabi_l2f+0x14> 800073a: bf00 nop 0800073c <__aeabi_l2f>: 800073c: ea50 0201 orrs.w r2, r0, r1 8000740: bf08 it eq 8000742: 4770 bxeq lr 8000744: f011 4300 ands.w r3, r1, #2147483648 ; 0x80000000 8000748: d502 bpl.n 8000750 <__aeabi_l2f+0x14> 800074a: 4240 negs r0, r0 800074c: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000750: ea5f 0c01 movs.w ip, r1 8000754: bf02 ittt eq 8000756: 4684 moveq ip, r0 8000758: 4601 moveq r1, r0 800075a: 2000 moveq r0, #0 800075c: f043 43b6 orr.w r3, r3, #1526726656 ; 0x5b000000 8000760: bf08 it eq 8000762: f1a3 5380 subeq.w r3, r3, #268435456 ; 0x10000000 8000766: f5a3 0300 sub.w r3, r3, #8388608 ; 0x800000 800076a: fabc f28c clz r2, ip 800076e: 3a08 subs r2, #8 8000770: eba3 53c2 sub.w r3, r3, r2, lsl #23 8000774: db10 blt.n 8000798 <__aeabi_l2f+0x5c> 8000776: fa01 fc02 lsl.w ip, r1, r2 800077a: 4463 add r3, ip 800077c: fa00 fc02 lsl.w ip, r0, r2 8000780: f1c2 0220 rsb r2, r2, #32 8000784: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 8000788: fa20 f202 lsr.w r2, r0, r2 800078c: eb43 0002 adc.w r0, r3, r2 8000790: bf08 it eq 8000792: f020 0001 biceq.w r0, r0, #1 8000796: 4770 bx lr 8000798: f102 0220 add.w r2, r2, #32 800079c: fa01 fc02 lsl.w ip, r1, r2 80007a0: f1c2 0220 rsb r2, r2, #32 80007a4: ea50 004c orrs.w r0, r0, ip, lsl #1 80007a8: fa21 f202 lsr.w r2, r1, r2 80007ac: eb43 0002 adc.w r0, r3, r2 80007b0: bf08 it eq 80007b2: ea20 70dc biceq.w r0, r0, ip, lsr #31 80007b6: 4770 bx lr 080007b8 <__aeabi_fmul>: 80007b8: f04f 0cff mov.w ip, #255 ; 0xff 80007bc: ea1c 52d0 ands.w r2, ip, r0, lsr #23 80007c0: bf1e ittt ne 80007c2: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 80007c6: ea92 0f0c teqne r2, ip 80007ca: ea93 0f0c teqne r3, ip 80007ce: d06f beq.n 80008b0 <__aeabi_fmul+0xf8> 80007d0: 441a add r2, r3 80007d2: ea80 0c01 eor.w ip, r0, r1 80007d6: 0240 lsls r0, r0, #9 80007d8: bf18 it ne 80007da: ea5f 2141 movsne.w r1, r1, lsl #9 80007de: d01e beq.n 800081e <__aeabi_fmul+0x66> 80007e0: f04f 6300 mov.w r3, #134217728 ; 0x8000000 80007e4: ea43 1050 orr.w r0, r3, r0, lsr #5 80007e8: ea43 1151 orr.w r1, r3, r1, lsr #5 80007ec: fba0 3101 umull r3, r1, r0, r1 80007f0: f00c 4000 and.w r0, ip, #2147483648 ; 0x80000000 80007f4: f5b1 0f00 cmp.w r1, #8388608 ; 0x800000 80007f8: bf3e ittt cc 80007fa: 0049 lslcc r1, r1, #1 80007fc: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 8000800: 005b lslcc r3, r3, #1 8000802: ea40 0001 orr.w r0, r0, r1 8000806: f162 027f sbc.w r2, r2, #127 ; 0x7f 800080a: 2afd cmp r2, #253 ; 0xfd 800080c: d81d bhi.n 800084a <__aeabi_fmul+0x92> 800080e: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 8000812: eb40 50c2 adc.w r0, r0, r2, lsl #23 8000816: bf08 it eq 8000818: f020 0001 biceq.w r0, r0, #1 800081c: 4770 bx lr 800081e: f090 0f00 teq r0, #0 8000822: f00c 4c00 and.w ip, ip, #2147483648 ; 0x80000000 8000826: bf08 it eq 8000828: 0249 lsleq r1, r1, #9 800082a: ea4c 2050 orr.w r0, ip, r0, lsr #9 800082e: ea40 2051 orr.w r0, r0, r1, lsr #9 8000832: 3a7f subs r2, #127 ; 0x7f 8000834: bfc2 ittt gt 8000836: f1d2 03ff rsbsgt r3, r2, #255 ; 0xff 800083a: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 800083e: 4770 bxgt lr 8000840: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000844: f04f 0300 mov.w r3, #0 8000848: 3a01 subs r2, #1 800084a: dc5d bgt.n 8000908 <__aeabi_fmul+0x150> 800084c: f112 0f19 cmn.w r2, #25 8000850: bfdc itt le 8000852: f000 4000 andle.w r0, r0, #2147483648 ; 0x80000000 8000856: 4770 bxle lr 8000858: f1c2 0200 rsb r2, r2, #0 800085c: 0041 lsls r1, r0, #1 800085e: fa21 f102 lsr.w r1, r1, r2 8000862: f1c2 0220 rsb r2, r2, #32 8000866: fa00 fc02 lsl.w ip, r0, r2 800086a: ea5f 0031 movs.w r0, r1, rrx 800086e: f140 0000 adc.w r0, r0, #0 8000872: ea53 034c orrs.w r3, r3, ip, lsl #1 8000876: bf08 it eq 8000878: ea20 70dc biceq.w r0, r0, ip, lsr #31 800087c: 4770 bx lr 800087e: f092 0f00 teq r2, #0 8000882: f000 4c00 and.w ip, r0, #2147483648 ; 0x80000000 8000886: bf02 ittt eq 8000888: 0040 lsleq r0, r0, #1 800088a: f410 0f00 tsteq.w r0, #8388608 ; 0x800000 800088e: 3a01 subeq r2, #1 8000890: d0f9 beq.n 8000886 <__aeabi_fmul+0xce> 8000892: ea40 000c orr.w r0, r0, ip 8000896: f093 0f00 teq r3, #0 800089a: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 800089e: bf02 ittt eq 80008a0: 0049 lsleq r1, r1, #1 80008a2: f411 0f00 tsteq.w r1, #8388608 ; 0x800000 80008a6: 3b01 subeq r3, #1 80008a8: d0f9 beq.n 800089e <__aeabi_fmul+0xe6> 80008aa: ea41 010c orr.w r1, r1, ip 80008ae: e78f b.n 80007d0 <__aeabi_fmul+0x18> 80008b0: ea0c 53d1 and.w r3, ip, r1, lsr #23 80008b4: ea92 0f0c teq r2, ip 80008b8: bf18 it ne 80008ba: ea93 0f0c teqne r3, ip 80008be: d00a beq.n 80008d6 <__aeabi_fmul+0x11e> 80008c0: f030 4c00 bics.w ip, r0, #2147483648 ; 0x80000000 80008c4: bf18 it ne 80008c6: f031 4c00 bicsne.w ip, r1, #2147483648 ; 0x80000000 80008ca: d1d8 bne.n 800087e <__aeabi_fmul+0xc6> 80008cc: ea80 0001 eor.w r0, r0, r1 80008d0: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000 80008d4: 4770 bx lr 80008d6: f090 0f00 teq r0, #0 80008da: bf17 itett ne 80008dc: f090 4f00 teqne r0, #2147483648 ; 0x80000000 80008e0: 4608 moveq r0, r1 80008e2: f091 0f00 teqne r1, #0 80008e6: f091 4f00 teqne r1, #2147483648 ; 0x80000000 80008ea: d014 beq.n 8000916 <__aeabi_fmul+0x15e> 80008ec: ea92 0f0c teq r2, ip 80008f0: d101 bne.n 80008f6 <__aeabi_fmul+0x13e> 80008f2: 0242 lsls r2, r0, #9 80008f4: d10f bne.n 8000916 <__aeabi_fmul+0x15e> 80008f6: ea93 0f0c teq r3, ip 80008fa: d103 bne.n 8000904 <__aeabi_fmul+0x14c> 80008fc: 024b lsls r3, r1, #9 80008fe: bf18 it ne 8000900: 4608 movne r0, r1 8000902: d108 bne.n 8000916 <__aeabi_fmul+0x15e> 8000904: ea80 0001 eor.w r0, r0, r1 8000908: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000 800090c: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 8000910: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000914: 4770 bx lr 8000916: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 800091a: f440 0040 orr.w r0, r0, #12582912 ; 0xc00000 800091e: 4770 bx lr 08000920 <__aeabi_fdiv>: 8000920: f04f 0cff mov.w ip, #255 ; 0xff 8000924: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8000928: bf1e ittt ne 800092a: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 800092e: ea92 0f0c teqne r2, ip 8000932: ea93 0f0c teqne r3, ip 8000936: d069 beq.n 8000a0c <__aeabi_fdiv+0xec> 8000938: eba2 0203 sub.w r2, r2, r3 800093c: ea80 0c01 eor.w ip, r0, r1 8000940: 0249 lsls r1, r1, #9 8000942: ea4f 2040 mov.w r0, r0, lsl #9 8000946: d037 beq.n 80009b8 <__aeabi_fdiv+0x98> 8000948: f04f 5380 mov.w r3, #268435456 ; 0x10000000 800094c: ea43 1111 orr.w r1, r3, r1, lsr #4 8000950: ea43 1310 orr.w r3, r3, r0, lsr #4 8000954: f00c 4000 and.w r0, ip, #2147483648 ; 0x80000000 8000958: 428b cmp r3, r1 800095a: bf38 it cc 800095c: 005b lslcc r3, r3, #1 800095e: f142 027d adc.w r2, r2, #125 ; 0x7d 8000962: f44f 0c00 mov.w ip, #8388608 ; 0x800000 8000966: 428b cmp r3, r1 8000968: bf24 itt cs 800096a: 1a5b subcs r3, r3, r1 800096c: ea40 000c orrcs.w r0, r0, ip 8000970: ebb3 0f51 cmp.w r3, r1, lsr #1 8000974: bf24 itt cs 8000976: eba3 0351 subcs.w r3, r3, r1, lsr #1 800097a: ea40 005c orrcs.w r0, r0, ip, lsr #1 800097e: ebb3 0f91 cmp.w r3, r1, lsr #2 8000982: bf24 itt cs 8000984: eba3 0391 subcs.w r3, r3, r1, lsr #2 8000988: ea40 009c orrcs.w r0, r0, ip, lsr #2 800098c: ebb3 0fd1 cmp.w r3, r1, lsr #3 8000990: bf24 itt cs 8000992: eba3 03d1 subcs.w r3, r3, r1, lsr #3 8000996: ea40 00dc orrcs.w r0, r0, ip, lsr #3 800099a: 011b lsls r3, r3, #4 800099c: bf18 it ne 800099e: ea5f 1c1c movsne.w ip, ip, lsr #4 80009a2: d1e0 bne.n 8000966 <__aeabi_fdiv+0x46> 80009a4: 2afd cmp r2, #253 ; 0xfd 80009a6: f63f af50 bhi.w 800084a <__aeabi_fmul+0x92> 80009aa: 428b cmp r3, r1 80009ac: eb40 50c2 adc.w r0, r0, r2, lsl #23 80009b0: bf08 it eq 80009b2: f020 0001 biceq.w r0, r0, #1 80009b6: 4770 bx lr 80009b8: f00c 4c00 and.w ip, ip, #2147483648 ; 0x80000000 80009bc: ea4c 2050 orr.w r0, ip, r0, lsr #9 80009c0: 327f adds r2, #127 ; 0x7f 80009c2: bfc2 ittt gt 80009c4: f1d2 03ff rsbsgt r3, r2, #255 ; 0xff 80009c8: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 80009cc: 4770 bxgt lr 80009ce: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 80009d2: f04f 0300 mov.w r3, #0 80009d6: 3a01 subs r2, #1 80009d8: e737 b.n 800084a <__aeabi_fmul+0x92> 80009da: f092 0f00 teq r2, #0 80009de: f000 4c00 and.w ip, r0, #2147483648 ; 0x80000000 80009e2: bf02 ittt eq 80009e4: 0040 lsleq r0, r0, #1 80009e6: f410 0f00 tsteq.w r0, #8388608 ; 0x800000 80009ea: 3a01 subeq r2, #1 80009ec: d0f9 beq.n 80009e2 <__aeabi_fdiv+0xc2> 80009ee: ea40 000c orr.w r0, r0, ip 80009f2: f093 0f00 teq r3, #0 80009f6: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 80009fa: bf02 ittt eq 80009fc: 0049 lsleq r1, r1, #1 80009fe: f411 0f00 tsteq.w r1, #8388608 ; 0x800000 8000a02: 3b01 subeq r3, #1 8000a04: d0f9 beq.n 80009fa <__aeabi_fdiv+0xda> 8000a06: ea41 010c orr.w r1, r1, ip 8000a0a: e795 b.n 8000938 <__aeabi_fdiv+0x18> 8000a0c: ea0c 53d1 and.w r3, ip, r1, lsr #23 8000a10: ea92 0f0c teq r2, ip 8000a14: d108 bne.n 8000a28 <__aeabi_fdiv+0x108> 8000a16: 0242 lsls r2, r0, #9 8000a18: f47f af7d bne.w 8000916 <__aeabi_fmul+0x15e> 8000a1c: ea93 0f0c teq r3, ip 8000a20: f47f af70 bne.w 8000904 <__aeabi_fmul+0x14c> 8000a24: 4608 mov r0, r1 8000a26: e776 b.n 8000916 <__aeabi_fmul+0x15e> 8000a28: ea93 0f0c teq r3, ip 8000a2c: d104 bne.n 8000a38 <__aeabi_fdiv+0x118> 8000a2e: 024b lsls r3, r1, #9 8000a30: f43f af4c beq.w 80008cc <__aeabi_fmul+0x114> 8000a34: 4608 mov r0, r1 8000a36: e76e b.n 8000916 <__aeabi_fmul+0x15e> 8000a38: f030 4c00 bics.w ip, r0, #2147483648 ; 0x80000000 8000a3c: bf18 it ne 8000a3e: f031 4c00 bicsne.w ip, r1, #2147483648 ; 0x80000000 8000a42: d1ca bne.n 80009da <__aeabi_fdiv+0xba> 8000a44: f030 4200 bics.w r2, r0, #2147483648 ; 0x80000000 8000a48: f47f af5c bne.w 8000904 <__aeabi_fmul+0x14c> 8000a4c: f031 4300 bics.w r3, r1, #2147483648 ; 0x80000000 8000a50: f47f af3c bne.w 80008cc <__aeabi_fmul+0x114> 8000a54: e75f b.n 8000916 <__aeabi_fmul+0x15e> 8000a56: bf00 nop 08000a58 <__gesf2>: 8000a58: f04f 3cff mov.w ip, #4294967295 ; 0xffffffff 8000a5c: e006 b.n 8000a6c <__cmpsf2+0x4> 8000a5e: bf00 nop 08000a60 <__lesf2>: 8000a60: f04f 0c01 mov.w ip, #1 8000a64: e002 b.n 8000a6c <__cmpsf2+0x4> 8000a66: bf00 nop 08000a68 <__cmpsf2>: 8000a68: f04f 0c01 mov.w ip, #1 8000a6c: f84d cd04 str.w ip, [sp, #-4]! 8000a70: ea4f 0240 mov.w r2, r0, lsl #1 8000a74: ea4f 0341 mov.w r3, r1, lsl #1 8000a78: ea7f 6c22 mvns.w ip, r2, asr #24 8000a7c: bf18 it ne 8000a7e: ea7f 6c23 mvnsne.w ip, r3, asr #24 8000a82: d011 beq.n 8000aa8 <__cmpsf2+0x40> 8000a84: b001 add sp, #4 8000a86: ea52 0c53 orrs.w ip, r2, r3, lsr #1 8000a8a: bf18 it ne 8000a8c: ea90 0f01 teqne r0, r1 8000a90: bf58 it pl 8000a92: ebb2 0003 subspl.w r0, r2, r3 8000a96: bf88 it hi 8000a98: 17c8 asrhi r0, r1, #31 8000a9a: bf38 it cc 8000a9c: ea6f 70e1 mvncc.w r0, r1, asr #31 8000aa0: bf18 it ne 8000aa2: f040 0001 orrne.w r0, r0, #1 8000aa6: 4770 bx lr 8000aa8: ea7f 6c22 mvns.w ip, r2, asr #24 8000aac: d102 bne.n 8000ab4 <__cmpsf2+0x4c> 8000aae: ea5f 2c40 movs.w ip, r0, lsl #9 8000ab2: d105 bne.n 8000ac0 <__cmpsf2+0x58> 8000ab4: ea7f 6c23 mvns.w ip, r3, asr #24 8000ab8: d1e4 bne.n 8000a84 <__cmpsf2+0x1c> 8000aba: ea5f 2c41 movs.w ip, r1, lsl #9 8000abe: d0e1 beq.n 8000a84 <__cmpsf2+0x1c> 8000ac0: f85d 0b04 ldr.w r0, [sp], #4 8000ac4: 4770 bx lr 8000ac6: bf00 nop 08000ac8 <__aeabi_cfrcmple>: 8000ac8: 4684 mov ip, r0 8000aca: 4608 mov r0, r1 8000acc: 4661 mov r1, ip 8000ace: e7ff b.n 8000ad0 <__aeabi_cfcmpeq> 08000ad0 <__aeabi_cfcmpeq>: 8000ad0: b50f push {r0, r1, r2, r3, lr} 8000ad2: f7ff ffc9 bl 8000a68 <__cmpsf2> 8000ad6: 2800 cmp r0, #0 8000ad8: bf48 it mi 8000ada: f110 0f00 cmnmi.w r0, #0 8000ade: bd0f pop {r0, r1, r2, r3, pc} 08000ae0 <__aeabi_fcmpeq>: 8000ae0: f84d ed08 str.w lr, [sp, #-8]! 8000ae4: f7ff fff4 bl 8000ad0 <__aeabi_cfcmpeq> 8000ae8: bf0c ite eq 8000aea: 2001 moveq r0, #1 8000aec: 2000 movne r0, #0 8000aee: f85d fb08 ldr.w pc, [sp], #8 8000af2: bf00 nop 08000af4 <__aeabi_fcmplt>: 8000af4: f84d ed08 str.w lr, [sp, #-8]! 8000af8: f7ff ffea bl 8000ad0 <__aeabi_cfcmpeq> 8000afc: bf34 ite cc 8000afe: 2001 movcc r0, #1 8000b00: 2000 movcs r0, #0 8000b02: f85d fb08 ldr.w pc, [sp], #8 8000b06: bf00 nop 08000b08 <__aeabi_fcmple>: 8000b08: f84d ed08 str.w lr, [sp, #-8]! 8000b0c: f7ff ffe0 bl 8000ad0 <__aeabi_cfcmpeq> 8000b10: bf94 ite ls 8000b12: 2001 movls r0, #1 8000b14: 2000 movhi r0, #0 8000b16: f85d fb08 ldr.w pc, [sp], #8 8000b1a: bf00 nop 08000b1c <__aeabi_fcmpge>: 8000b1c: f84d ed08 str.w lr, [sp, #-8]! 8000b20: f7ff ffd2 bl 8000ac8 <__aeabi_cfrcmple> 8000b24: bf94 ite ls 8000b26: 2001 movls r0, #1 8000b28: 2000 movhi r0, #0 8000b2a: f85d fb08 ldr.w pc, [sp], #8 8000b2e: bf00 nop 08000b30 <__aeabi_fcmpgt>: 8000b30: f84d ed08 str.w lr, [sp, #-8]! 8000b34: f7ff ffc8 bl 8000ac8 <__aeabi_cfrcmple> 8000b38: bf34 ite cc 8000b3a: 2001 movcc r0, #1 8000b3c: 2000 movcs r0, #0 8000b3e: f85d fb08 ldr.w pc, [sp], #8 8000b42: bf00 nop 08000b44 <__aeabi_ldivmod>: 8000b44: b97b cbnz r3, 8000b66 <__aeabi_ldivmod+0x22> 8000b46: b972 cbnz r2, 8000b66 <__aeabi_ldivmod+0x22> 8000b48: 2900 cmp r1, #0 8000b4a: bfbe ittt lt 8000b4c: 2000 movlt r0, #0 8000b4e: f04f 4100 movlt.w r1, #2147483648 ; 0x80000000 8000b52: e006 blt.n 8000b62 <__aeabi_ldivmod+0x1e> 8000b54: bf08 it eq 8000b56: 2800 cmpeq r0, #0 8000b58: bf1c itt ne 8000b5a: f06f 4100 mvnne.w r1, #2147483648 ; 0x80000000 8000b5e: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff 8000b62: f000 b9c1 b.w 8000ee8 <__aeabi_idiv0> 8000b66: f1ad 0c08 sub.w ip, sp, #8 8000b6a: e96d ce04 strd ip, lr, [sp, #-16]! 8000b6e: 2900 cmp r1, #0 8000b70: db09 blt.n 8000b86 <__aeabi_ldivmod+0x42> 8000b72: 2b00 cmp r3, #0 8000b74: db1a blt.n 8000bac <__aeabi_ldivmod+0x68> 8000b76: f000 f84d bl 8000c14 <__udivmoddi4> 8000b7a: f8dd e004 ldr.w lr, [sp, #4] 8000b7e: e9dd 2302 ldrd r2, r3, [sp, #8] 8000b82: b004 add sp, #16 8000b84: 4770 bx lr 8000b86: 4240 negs r0, r0 8000b88: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000b8c: 2b00 cmp r3, #0 8000b8e: db1b blt.n 8000bc8 <__aeabi_ldivmod+0x84> 8000b90: f000 f840 bl 8000c14 <__udivmoddi4> 8000b94: f8dd e004 ldr.w lr, [sp, #4] 8000b98: e9dd 2302 ldrd r2, r3, [sp, #8] 8000b9c: b004 add sp, #16 8000b9e: 4240 negs r0, r0 8000ba0: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000ba4: 4252 negs r2, r2 8000ba6: eb63 0343 sbc.w r3, r3, r3, lsl #1 8000baa: 4770 bx lr 8000bac: 4252 negs r2, r2 8000bae: eb63 0343 sbc.w r3, r3, r3, lsl #1 8000bb2: f000 f82f bl 8000c14 <__udivmoddi4> 8000bb6: f8dd e004 ldr.w lr, [sp, #4] 8000bba: e9dd 2302 ldrd r2, r3, [sp, #8] 8000bbe: b004 add sp, #16 8000bc0: 4240 negs r0, r0 8000bc2: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000bc6: 4770 bx lr 8000bc8: 4252 negs r2, r2 8000bca: eb63 0343 sbc.w r3, r3, r3, lsl #1 8000bce: f000 f821 bl 8000c14 <__udivmoddi4> 8000bd2: f8dd e004 ldr.w lr, [sp, #4] 8000bd6: e9dd 2302 ldrd r2, r3, [sp, #8] 8000bda: b004 add sp, #16 8000bdc: 4252 negs r2, r2 8000bde: eb63 0343 sbc.w r3, r3, r3, lsl #1 8000be2: 4770 bx lr 08000be4 <__aeabi_uldivmod>: 8000be4: b953 cbnz r3, 8000bfc <__aeabi_uldivmod+0x18> 8000be6: b94a cbnz r2, 8000bfc <__aeabi_uldivmod+0x18> 8000be8: 2900 cmp r1, #0 8000bea: bf08 it eq 8000bec: 2800 cmpeq r0, #0 8000bee: bf1c itt ne 8000bf0: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff 8000bf4: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff 8000bf8: f000 b976 b.w 8000ee8 <__aeabi_idiv0> 8000bfc: f1ad 0c08 sub.w ip, sp, #8 8000c00: e96d ce04 strd ip, lr, [sp, #-16]! 8000c04: f000 f806 bl 8000c14 <__udivmoddi4> 8000c08: f8dd e004 ldr.w lr, [sp, #4] 8000c0c: e9dd 2302 ldrd r2, r3, [sp, #8] 8000c10: b004 add sp, #16 8000c12: 4770 bx lr 08000c14 <__udivmoddi4>: 8000c14: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000c18: 9e08 ldr r6, [sp, #32] 8000c1a: 460d mov r5, r1 8000c1c: 4604 mov r4, r0 8000c1e: 4688 mov r8, r1 8000c20: 2b00 cmp r3, #0 8000c22: d14d bne.n 8000cc0 <__udivmoddi4+0xac> 8000c24: 428a cmp r2, r1 8000c26: 4694 mov ip, r2 8000c28: d968 bls.n 8000cfc <__udivmoddi4+0xe8> 8000c2a: fab2 f282 clz r2, r2 8000c2e: b152 cbz r2, 8000c46 <__udivmoddi4+0x32> 8000c30: fa01 f302 lsl.w r3, r1, r2 8000c34: f1c2 0120 rsb r1, r2, #32 8000c38: fa20 f101 lsr.w r1, r0, r1 8000c3c: fa0c fc02 lsl.w ip, ip, r2 8000c40: ea41 0803 orr.w r8, r1, r3 8000c44: 4094 lsls r4, r2 8000c46: ea4f 411c mov.w r1, ip, lsr #16 8000c4a: fbb8 f7f1 udiv r7, r8, r1 8000c4e: fa1f fe8c uxth.w lr, ip 8000c52: fb01 8817 mls r8, r1, r7, r8 8000c56: fb07 f00e mul.w r0, r7, lr 8000c5a: 0c23 lsrs r3, r4, #16 8000c5c: ea43 4308 orr.w r3, r3, r8, lsl #16 8000c60: 4298 cmp r0, r3 8000c62: d90a bls.n 8000c7a <__udivmoddi4+0x66> 8000c64: eb1c 0303 adds.w r3, ip, r3 8000c68: f107 35ff add.w r5, r7, #4294967295 ; 0xffffffff 8000c6c: f080 811e bcs.w 8000eac <__udivmoddi4+0x298> 8000c70: 4298 cmp r0, r3 8000c72: f240 811b bls.w 8000eac <__udivmoddi4+0x298> 8000c76: 3f02 subs r7, #2 8000c78: 4463 add r3, ip 8000c7a: 1a1b subs r3, r3, r0 8000c7c: fbb3 f0f1 udiv r0, r3, r1 8000c80: fb01 3310 mls r3, r1, r0, r3 8000c84: fb00 fe0e mul.w lr, r0, lr 8000c88: b2a4 uxth r4, r4 8000c8a: ea44 4403 orr.w r4, r4, r3, lsl #16 8000c8e: 45a6 cmp lr, r4 8000c90: d90a bls.n 8000ca8 <__udivmoddi4+0x94> 8000c92: eb1c 0404 adds.w r4, ip, r4 8000c96: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff 8000c9a: f080 8109 bcs.w 8000eb0 <__udivmoddi4+0x29c> 8000c9e: 45a6 cmp lr, r4 8000ca0: f240 8106 bls.w 8000eb0 <__udivmoddi4+0x29c> 8000ca4: 4464 add r4, ip 8000ca6: 3802 subs r0, #2 8000ca8: 2100 movs r1, #0 8000caa: eba4 040e sub.w r4, r4, lr 8000cae: ea40 4007 orr.w r0, r0, r7, lsl #16 8000cb2: b11e cbz r6, 8000cbc <__udivmoddi4+0xa8> 8000cb4: 2300 movs r3, #0 8000cb6: 40d4 lsrs r4, r2 8000cb8: e9c6 4300 strd r4, r3, [r6] 8000cbc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8000cc0: 428b cmp r3, r1 8000cc2: d908 bls.n 8000cd6 <__udivmoddi4+0xc2> 8000cc4: 2e00 cmp r6, #0 8000cc6: f000 80ee beq.w 8000ea6 <__udivmoddi4+0x292> 8000cca: 2100 movs r1, #0 8000ccc: e9c6 0500 strd r0, r5, [r6] 8000cd0: 4608 mov r0, r1 8000cd2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8000cd6: fab3 f183 clz r1, r3 8000cda: 2900 cmp r1, #0 8000cdc: d14a bne.n 8000d74 <__udivmoddi4+0x160> 8000cde: 42ab cmp r3, r5 8000ce0: d302 bcc.n 8000ce8 <__udivmoddi4+0xd4> 8000ce2: 4282 cmp r2, r0 8000ce4: f200 80fc bhi.w 8000ee0 <__udivmoddi4+0x2cc> 8000ce8: 1a84 subs r4, r0, r2 8000cea: eb65 0303 sbc.w r3, r5, r3 8000cee: 2001 movs r0, #1 8000cf0: 4698 mov r8, r3 8000cf2: 2e00 cmp r6, #0 8000cf4: d0e2 beq.n 8000cbc <__udivmoddi4+0xa8> 8000cf6: e9c6 4800 strd r4, r8, [r6] 8000cfa: e7df b.n 8000cbc <__udivmoddi4+0xa8> 8000cfc: b902 cbnz r2, 8000d00 <__udivmoddi4+0xec> 8000cfe: deff udf #255 ; 0xff 8000d00: fab2 f282 clz r2, r2 8000d04: 2a00 cmp r2, #0 8000d06: f040 8091 bne.w 8000e2c <__udivmoddi4+0x218> 8000d0a: eba1 000c sub.w r0, r1, ip 8000d0e: 2101 movs r1, #1 8000d10: ea4f 471c mov.w r7, ip, lsr #16 8000d14: fa1f fe8c uxth.w lr, ip 8000d18: fbb0 f3f7 udiv r3, r0, r7 8000d1c: fb07 0013 mls r0, r7, r3, r0 8000d20: 0c25 lsrs r5, r4, #16 8000d22: ea45 4500 orr.w r5, r5, r0, lsl #16 8000d26: fb0e f003 mul.w r0, lr, r3 8000d2a: 42a8 cmp r0, r5 8000d2c: d908 bls.n 8000d40 <__udivmoddi4+0x12c> 8000d2e: eb1c 0505 adds.w r5, ip, r5 8000d32: f103 38ff add.w r8, r3, #4294967295 ; 0xffffffff 8000d36: d202 bcs.n 8000d3e <__udivmoddi4+0x12a> 8000d38: 42a8 cmp r0, r5 8000d3a: f200 80ce bhi.w 8000eda <__udivmoddi4+0x2c6> 8000d3e: 4643 mov r3, r8 8000d40: 1a2d subs r5, r5, r0 8000d42: fbb5 f0f7 udiv r0, r5, r7 8000d46: fb07 5510 mls r5, r7, r0, r5 8000d4a: fb0e fe00 mul.w lr, lr, r0 8000d4e: b2a4 uxth r4, r4 8000d50: ea44 4405 orr.w r4, r4, r5, lsl #16 8000d54: 45a6 cmp lr, r4 8000d56: d908 bls.n 8000d6a <__udivmoddi4+0x156> 8000d58: eb1c 0404 adds.w r4, ip, r4 8000d5c: f100 35ff add.w r5, r0, #4294967295 ; 0xffffffff 8000d60: d202 bcs.n 8000d68 <__udivmoddi4+0x154> 8000d62: 45a6 cmp lr, r4 8000d64: f200 80b6 bhi.w 8000ed4 <__udivmoddi4+0x2c0> 8000d68: 4628 mov r0, r5 8000d6a: eba4 040e sub.w r4, r4, lr 8000d6e: ea40 4003 orr.w r0, r0, r3, lsl #16 8000d72: e79e b.n 8000cb2 <__udivmoddi4+0x9e> 8000d74: f1c1 0720 rsb r7, r1, #32 8000d78: 408b lsls r3, r1 8000d7a: fa22 fc07 lsr.w ip, r2, r7 8000d7e: ea4c 0c03 orr.w ip, ip, r3 8000d82: fa25 fa07 lsr.w sl, r5, r7 8000d86: ea4f 491c mov.w r9, ip, lsr #16 8000d8a: fbba f8f9 udiv r8, sl, r9 8000d8e: fa20 f307 lsr.w r3, r0, r7 8000d92: fb09 aa18 mls sl, r9, r8, sl 8000d96: 408d lsls r5, r1 8000d98: fa1f fe8c uxth.w lr, ip 8000d9c: 431d orrs r5, r3 8000d9e: fa00 f301 lsl.w r3, r0, r1 8000da2: fb08 f00e mul.w r0, r8, lr 8000da6: 0c2c lsrs r4, r5, #16 8000da8: ea44 440a orr.w r4, r4, sl, lsl #16 8000dac: 42a0 cmp r0, r4 8000dae: fa02 f201 lsl.w r2, r2, r1 8000db2: d90b bls.n 8000dcc <__udivmoddi4+0x1b8> 8000db4: eb1c 0404 adds.w r4, ip, r4 8000db8: f108 3aff add.w sl, r8, #4294967295 ; 0xffffffff 8000dbc: f080 8088 bcs.w 8000ed0 <__udivmoddi4+0x2bc> 8000dc0: 42a0 cmp r0, r4 8000dc2: f240 8085 bls.w 8000ed0 <__udivmoddi4+0x2bc> 8000dc6: f1a8 0802 sub.w r8, r8, #2 8000dca: 4464 add r4, ip 8000dcc: 1a24 subs r4, r4, r0 8000dce: fbb4 f0f9 udiv r0, r4, r9 8000dd2: fb09 4410 mls r4, r9, r0, r4 8000dd6: fb00 fe0e mul.w lr, r0, lr 8000dda: b2ad uxth r5, r5 8000ddc: ea45 4404 orr.w r4, r5, r4, lsl #16 8000de0: 45a6 cmp lr, r4 8000de2: d908 bls.n 8000df6 <__udivmoddi4+0x1e2> 8000de4: eb1c 0404 adds.w r4, ip, r4 8000de8: f100 35ff add.w r5, r0, #4294967295 ; 0xffffffff 8000dec: d26c bcs.n 8000ec8 <__udivmoddi4+0x2b4> 8000dee: 45a6 cmp lr, r4 8000df0: d96a bls.n 8000ec8 <__udivmoddi4+0x2b4> 8000df2: 3802 subs r0, #2 8000df4: 4464 add r4, ip 8000df6: ea40 4008 orr.w r0, r0, r8, lsl #16 8000dfa: fba0 9502 umull r9, r5, r0, r2 8000dfe: eba4 040e sub.w r4, r4, lr 8000e02: 42ac cmp r4, r5 8000e04: 46c8 mov r8, r9 8000e06: 46ae mov lr, r5 8000e08: d356 bcc.n 8000eb8 <__udivmoddi4+0x2a4> 8000e0a: d053 beq.n 8000eb4 <__udivmoddi4+0x2a0> 8000e0c: 2e00 cmp r6, #0 8000e0e: d069 beq.n 8000ee4 <__udivmoddi4+0x2d0> 8000e10: ebb3 0208 subs.w r2, r3, r8 8000e14: eb64 040e sbc.w r4, r4, lr 8000e18: fa22 f301 lsr.w r3, r2, r1 8000e1c: fa04 f707 lsl.w r7, r4, r7 8000e20: 431f orrs r7, r3 8000e22: 40cc lsrs r4, r1 8000e24: e9c6 7400 strd r7, r4, [r6] 8000e28: 2100 movs r1, #0 8000e2a: e747 b.n 8000cbc <__udivmoddi4+0xa8> 8000e2c: fa0c fc02 lsl.w ip, ip, r2 8000e30: f1c2 0120 rsb r1, r2, #32 8000e34: fa25 f301 lsr.w r3, r5, r1 8000e38: ea4f 471c mov.w r7, ip, lsr #16 8000e3c: fa20 f101 lsr.w r1, r0, r1 8000e40: 4095 lsls r5, r2 8000e42: 430d orrs r5, r1 8000e44: fbb3 f1f7 udiv r1, r3, r7 8000e48: fb07 3311 mls r3, r7, r1, r3 8000e4c: fa1f fe8c uxth.w lr, ip 8000e50: 0c28 lsrs r0, r5, #16 8000e52: ea40 4003 orr.w r0, r0, r3, lsl #16 8000e56: fb01 f30e mul.w r3, r1, lr 8000e5a: 4283 cmp r3, r0 8000e5c: fa04 f402 lsl.w r4, r4, r2 8000e60: d908 bls.n 8000e74 <__udivmoddi4+0x260> 8000e62: eb1c 0000 adds.w r0, ip, r0 8000e66: f101 38ff add.w r8, r1, #4294967295 ; 0xffffffff 8000e6a: d22f bcs.n 8000ecc <__udivmoddi4+0x2b8> 8000e6c: 4283 cmp r3, r0 8000e6e: d92d bls.n 8000ecc <__udivmoddi4+0x2b8> 8000e70: 3902 subs r1, #2 8000e72: 4460 add r0, ip 8000e74: 1ac0 subs r0, r0, r3 8000e76: fbb0 f3f7 udiv r3, r0, r7 8000e7a: fb07 0013 mls r0, r7, r3, r0 8000e7e: b2ad uxth r5, r5 8000e80: ea45 4500 orr.w r5, r5, r0, lsl #16 8000e84: fb03 f00e mul.w r0, r3, lr 8000e88: 42a8 cmp r0, r5 8000e8a: d908 bls.n 8000e9e <__udivmoddi4+0x28a> 8000e8c: eb1c 0505 adds.w r5, ip, r5 8000e90: f103 38ff add.w r8, r3, #4294967295 ; 0xffffffff 8000e94: d216 bcs.n 8000ec4 <__udivmoddi4+0x2b0> 8000e96: 42a8 cmp r0, r5 8000e98: d914 bls.n 8000ec4 <__udivmoddi4+0x2b0> 8000e9a: 3b02 subs r3, #2 8000e9c: 4465 add r5, ip 8000e9e: 1a28 subs r0, r5, r0 8000ea0: ea43 4101 orr.w r1, r3, r1, lsl #16 8000ea4: e738 b.n 8000d18 <__udivmoddi4+0x104> 8000ea6: 4631 mov r1, r6 8000ea8: 4630 mov r0, r6 8000eaa: e707 b.n 8000cbc <__udivmoddi4+0xa8> 8000eac: 462f mov r7, r5 8000eae: e6e4 b.n 8000c7a <__udivmoddi4+0x66> 8000eb0: 4618 mov r0, r3 8000eb2: e6f9 b.n 8000ca8 <__udivmoddi4+0x94> 8000eb4: 454b cmp r3, r9 8000eb6: d2a9 bcs.n 8000e0c <__udivmoddi4+0x1f8> 8000eb8: ebb9 0802 subs.w r8, r9, r2 8000ebc: eb65 0e0c sbc.w lr, r5, ip 8000ec0: 3801 subs r0, #1 8000ec2: e7a3 b.n 8000e0c <__udivmoddi4+0x1f8> 8000ec4: 4643 mov r3, r8 8000ec6: e7ea b.n 8000e9e <__udivmoddi4+0x28a> 8000ec8: 4628 mov r0, r5 8000eca: e794 b.n 8000df6 <__udivmoddi4+0x1e2> 8000ecc: 4641 mov r1, r8 8000ece: e7d1 b.n 8000e74 <__udivmoddi4+0x260> 8000ed0: 46d0 mov r8, sl 8000ed2: e77b b.n 8000dcc <__udivmoddi4+0x1b8> 8000ed4: 4464 add r4, ip 8000ed6: 3802 subs r0, #2 8000ed8: e747 b.n 8000d6a <__udivmoddi4+0x156> 8000eda: 3b02 subs r3, #2 8000edc: 4465 add r5, ip 8000ede: e72f b.n 8000d40 <__udivmoddi4+0x12c> 8000ee0: 4608 mov r0, r1 8000ee2: e706 b.n 8000cf2 <__udivmoddi4+0xde> 8000ee4: 4631 mov r1, r6 8000ee6: e6e9 b.n 8000cbc <__udivmoddi4+0xa8> 08000ee8 <__aeabi_idiv0>: 8000ee8: 4770 bx lr 8000eea: bf00 nop 08000eec : ADC_HandleTypeDef hadc1; /* ADC1 init function */ void MX_ADC1_Init(void) { 8000eec: b580 push {r7, lr} 8000eee: b084 sub sp, #16 8000ef0: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000ef2: 1d3b adds r3, r7, #4 8000ef4: 2200 movs r2, #0 8000ef6: 601a str r2, [r3, #0] 8000ef8: 605a str r2, [r3, #4] 8000efa: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 8000efc: 4b18 ldr r3, [pc, #96] ; (8000f60 ) 8000efe: 4a19 ldr r2, [pc, #100] ; (8000f64 ) 8000f00: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 8000f02: 4b17 ldr r3, [pc, #92] ; (8000f60 ) 8000f04: 2200 movs r2, #0 8000f06: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = DISABLE; 8000f08: 4b15 ldr r3, [pc, #84] ; (8000f60 ) 8000f0a: 2200 movs r2, #0 8000f0c: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 8000f0e: 4b14 ldr r3, [pc, #80] ; (8000f60 ) 8000f10: 2200 movs r2, #0 8000f12: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 8000f14: 4b12 ldr r3, [pc, #72] ; (8000f60 ) 8000f16: f44f 2260 mov.w r2, #917504 ; 0xe0000 8000f1a: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 8000f1c: 4b10 ldr r3, [pc, #64] ; (8000f60 ) 8000f1e: 2200 movs r2, #0 8000f20: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 1; 8000f22: 4b0f ldr r3, [pc, #60] ; (8000f60 ) 8000f24: 2201 movs r2, #1 8000f26: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 8000f28: 480d ldr r0, [pc, #52] ; (8000f60 ) 8000f2a: f002 fec7 bl 8003cbc 8000f2e: 4603 mov r3, r0 8000f30: 2b00 cmp r3, #0 8000f32: d001 beq.n 8000f38 { Error_Handler(); 8000f34: f002 fb44 bl 80035c0 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 8000f38: 2308 movs r3, #8 8000f3a: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8000f3c: 2301 movs r3, #1 8000f3e: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 8000f40: 2300 movs r3, #0 8000f42: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000f44: 1d3b adds r3, r7, #4 8000f46: 4619 mov r1, r3 8000f48: 4805 ldr r0, [pc, #20] ; (8000f60 ) 8000f4a: f003 f97b bl 8004244 8000f4e: 4603 mov r3, r0 8000f50: 2b00 cmp r3, #0 8000f52: d001 beq.n 8000f58 { Error_Handler(); 8000f54: f002 fb34 bl 80035c0 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 8000f58: bf00 nop 8000f5a: 3710 adds r7, #16 8000f5c: 46bd mov sp, r7 8000f5e: bd80 pop {r7, pc} 8000f60: 2000008c .word 0x2000008c 8000f64: 40012400 .word 0x40012400 08000f68 : void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 8000f68: b580 push {r7, lr} 8000f6a: b08a sub sp, #40 ; 0x28 8000f6c: af00 add r7, sp, #0 8000f6e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000f70: f107 0318 add.w r3, r7, #24 8000f74: 2200 movs r2, #0 8000f76: 601a str r2, [r3, #0] 8000f78: 605a str r2, [r3, #4] 8000f7a: 609a str r2, [r3, #8] 8000f7c: 60da str r2, [r3, #12] if(adcHandle->Instance==ADC1) 8000f7e: 687b ldr r3, [r7, #4] 8000f80: 681b ldr r3, [r3, #0] 8000f82: 4a1f ldr r2, [pc, #124] ; (8001000 ) 8000f84: 4293 cmp r3, r2 8000f86: d137 bne.n 8000ff8 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* ADC1 clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 8000f88: 4b1e ldr r3, [pc, #120] ; (8001004 ) 8000f8a: 699b ldr r3, [r3, #24] 8000f8c: 4a1d ldr r2, [pc, #116] ; (8001004 ) 8000f8e: f443 7300 orr.w r3, r3, #512 ; 0x200 8000f92: 6193 str r3, [r2, #24] 8000f94: 4b1b ldr r3, [pc, #108] ; (8001004 ) 8000f96: 699b ldr r3, [r3, #24] 8000f98: f403 7300 and.w r3, r3, #512 ; 0x200 8000f9c: 617b str r3, [r7, #20] 8000f9e: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000fa0: 4b18 ldr r3, [pc, #96] ; (8001004 ) 8000fa2: 699b ldr r3, [r3, #24] 8000fa4: 4a17 ldr r2, [pc, #92] ; (8001004 ) 8000fa6: f043 0304 orr.w r3, r3, #4 8000faa: 6193 str r3, [r2, #24] 8000fac: 4b15 ldr r3, [pc, #84] ; (8001004 ) 8000fae: 699b ldr r3, [r3, #24] 8000fb0: f003 0304 and.w r3, r3, #4 8000fb4: 613b str r3, [r7, #16] 8000fb6: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000fb8: 4b12 ldr r3, [pc, #72] ; (8001004 ) 8000fba: 699b ldr r3, [r3, #24] 8000fbc: 4a11 ldr r2, [pc, #68] ; (8001004 ) 8000fbe: f043 0308 orr.w r3, r3, #8 8000fc2: 6193 str r3, [r2, #24] 8000fc4: 4b0f ldr r3, [pc, #60] ; (8001004 ) 8000fc6: 699b ldr r3, [r3, #24] 8000fc8: f003 0308 and.w r3, r3, #8 8000fcc: 60fb str r3, [r7, #12] 8000fce: 68fb ldr r3, [r7, #12] /**ADC1 GPIO Configuration PA6 ------> ADC1_IN6 PB0 ------> ADC1_IN8 PB1 ------> ADC1_IN9 */ GPIO_InitStruct.Pin = ADC_CC1_Pin; 8000fd0: 2340 movs r3, #64 ; 0x40 8000fd2: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8000fd4: 2303 movs r3, #3 8000fd6: 61fb str r3, [r7, #28] HAL_GPIO_Init(ADC_CC1_GPIO_Port, &GPIO_InitStruct); 8000fd8: f107 0318 add.w r3, r7, #24 8000fdc: 4619 mov r1, r3 8000fde: 480a ldr r0, [pc, #40] ; (8001008 ) 8000fe0: f004 fc6c bl 80058bc GPIO_InitStruct.Pin = ADC_NTC1_Pin|ADC_NTC2_Pin; 8000fe4: 2303 movs r3, #3 8000fe6: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8000fe8: 2303 movs r3, #3 8000fea: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000fec: f107 0318 add.w r3, r7, #24 8000ff0: 4619 mov r1, r3 8000ff2: 4806 ldr r0, [pc, #24] ; (800100c ) 8000ff4: f004 fc62 bl 80058bc /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 8000ff8: bf00 nop 8000ffa: 3728 adds r7, #40 ; 0x28 8000ffc: 46bd mov sp, r7 8000ffe: bd80 pop {r7, pc} 8001000: 40012400 .word 0x40012400 8001004: 40021000 .word 0x40021000 8001008: 40010800 .word 0x40010800 800100c: 40010c00 .word 0x40010c00 08001010 : //TEMP READ //LOCK_FB //GBT_TEMP_SENSORS //USB void GBT_Lock(uint8_t state){ 8001010: b580 push {r7, lr} 8001012: b082 sub sp, #8 8001014: af00 add r7, sp, #0 8001016: 4603 mov r3, r0 8001018: 71fb strb r3, [r7, #7] if(state){//LOCK 800101a: 79fb ldrb r3, [r7, #7] 800101c: 2b00 cmp r3, #0 800101e: d00d beq.n 800103c HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 1); 8001020: 2201 movs r2, #1 8001022: 2110 movs r1, #16 8001024: 480e ldr r0, [pc, #56] ; (8001060 ) 8001026: f004 fde4 bl 8005bf2 HAL_Delay(50); 800102a: 2032 movs r0, #50 ; 0x32 800102c: f002 fe22 bl 8003c74 HAL_GPIO_WritePin(LOCK_A_GPIO_Port, LOCK_A_Pin, 0); 8001030: 2200 movs r2, #0 8001032: 2110 movs r1, #16 8001034: 480a ldr r0, [pc, #40] ; (8001060 ) 8001036: f004 fddc bl 8005bf2 }else{ //UNLOCK HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 1); HAL_Delay(50); HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 0); } } 800103a: e00c b.n 8001056 HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 1); 800103c: 2201 movs r2, #1 800103e: 2120 movs r1, #32 8001040: 4807 ldr r0, [pc, #28] ; (8001060 ) 8001042: f004 fdd6 bl 8005bf2 HAL_Delay(50); 8001046: 2032 movs r0, #50 ; 0x32 8001048: f002 fe14 bl 8003c74 HAL_GPIO_WritePin(LOCK_B_GPIO_Port, LOCK_B_Pin, 0); 800104c: 2200 movs r2, #0 800104e: 2120 movs r1, #32 8001050: 4803 ldr r0, [pc, #12] ; (8001060 ) 8001052: f004 fdce bl 8005bf2 } 8001056: bf00 nop 8001058: 3708 adds r7, #8 800105a: 46bd mov sp, r7 800105c: bd80 pop {r7, pc} 800105e: bf00 nop 8001060: 40011000 .word 0x40011000 08001064 : uint8_t GBT_LockGetState(){ 8001064: b580 push {r7, lr} 8001066: af00 add r7, sp, #0 return HAL_GPIO_ReadPin(LOCK_FB_GPIO_Port, LOCK_FB_Pin); 8001068: f44f 7100 mov.w r1, #512 ; 0x200 800106c: 4802 ldr r0, [pc, #8] ; (8001078 ) 800106e: f004 fda9 bl 8005bc4 8001072: 4603 mov r3, r0 } 8001074: 4618 mov r0, r3 8001076: bd80 pop {r7, pc} 8001078: 40011800 .word 0x40011800 0800107c : void RELAY_Write(relay_t num, uint8_t state){ 800107c: b580 push {r7, lr} 800107e: b082 sub sp, #8 8001080: af00 add r7, sp, #0 8001082: 4603 mov r3, r0 8001084: 460a mov r2, r1 8001086: 71fb strb r3, [r7, #7] 8001088: 4613 mov r3, r2 800108a: 71bb strb r3, [r7, #6] if(num==RELAY_AUX)HAL_GPIO_WritePin(RELAY_AUX_GPIO_Port, RELAY_AUX_Pin, state); 800108c: 79fb ldrb r3, [r7, #7] 800108e: 2b00 cmp r3, #0 8001090: d105 bne.n 800109e 8001092: 79bb ldrb r3, [r7, #6] 8001094: 461a mov r2, r3 8001096: 2110 movs r1, #16 8001098: 4808 ldr r0, [pc, #32] ; (80010bc ) 800109a: f004 fdaa bl 8005bf2 if(num==RELAY_CC)HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, state); 800109e: 79fb ldrb r3, [r7, #7] 80010a0: 2b01 cmp r3, #1 80010a2: d106 bne.n 80010b2 80010a4: 79bb ldrb r3, [r7, #6] 80010a6: 461a mov r2, r3 80010a8: f44f 4100 mov.w r1, #32768 ; 0x8000 80010ac: 4804 ldr r0, [pc, #16] ; (80010c0 ) 80010ae: f004 fda0 bl 8005bf2 } 80010b2: bf00 nop 80010b4: 3708 adds r7, #8 80010b6: 46bd mov sp, r7 80010b8: bd80 pop {r7, pc} 80010ba: bf00 nop 80010bc: 40010c00 .word 0x40010c00 80010c0: 40011800 .word 0x40011800 080010c4 : // // HAL_ADC_Stop(&hadc1); // stop adc return 0; } void Init_Peripheral(){ 80010c4: b580 push {r7, lr} 80010c6: af00 add r7, sp, #0 HAL_ADCEx_Calibration_Start(&hadc1); 80010c8: 4806 ldr r0, [pc, #24] ; (80010e4 ) 80010ca: f003 fa4f bl 800456c RELAY_Write(RELAY_AUX, 0); 80010ce: 2100 movs r1, #0 80010d0: 2000 movs r0, #0 80010d2: f7ff ffd3 bl 800107c RELAY_Write(RELAY_CC, 1); 80010d6: 2101 movs r1, #1 80010d8: 2001 movs r0, #1 80010da: f7ff ffcf bl 800107c } 80010de: bf00 nop 80010e0: bd80 pop {r7, pc} 80010e2: bf00 nop 80010e4: 2000008c .word 0x2000008c 080010e8 : uint8_t GBT_ReadTemp(){ //TODO return 0; } void ADC_Select_Channel(uint32_t ch) { 80010e8: b580 push {r7, lr} 80010ea: b086 sub sp, #24 80010ec: af00 add r7, sp, #0 80010ee: 6078 str r0, [r7, #4] ADC_ChannelConfTypeDef conf = { 80010f0: 687b ldr r3, [r7, #4] 80010f2: 60fb str r3, [r7, #12] 80010f4: 2301 movs r3, #1 80010f6: 613b str r3, [r7, #16] 80010f8: 2303 movs r3, #3 80010fa: 617b str r3, [r7, #20] .Channel = ch, .Rank = 1, .SamplingTime = ADC_SAMPLETIME_28CYCLES_5, }; if (HAL_ADC_ConfigChannel(&hadc1, &conf) != HAL_OK) { 80010fc: f107 030c add.w r3, r7, #12 8001100: 4619 mov r1, r3 8001102: 4806 ldr r0, [pc, #24] ; (800111c ) 8001104: f003 f89e bl 8004244 8001108: 4603 mov r3, r0 800110a: 2b00 cmp r3, #0 800110c: d001 beq.n 8001112 Error_Handler(); 800110e: f002 fa57 bl 80035c0 } } 8001112: bf00 nop 8001114: 3718 adds r7, #24 8001116: 46bd mov sp, r7 8001118: bd80 pop {r7, pc} 800111a: bf00 nop 800111c: 2000008c .word 0x2000008c 08001120 : CAN_HandleTypeDef hcan1; CAN_HandleTypeDef hcan2; /* CAN1 init function */ void MX_CAN1_Init(void) { 8001120: b580 push {r7, lr} 8001122: af00 add r7, sp, #0 /* USER CODE END CAN1_Init 0 */ /* USER CODE BEGIN CAN1_Init 1 */ /* USER CODE END CAN1_Init 1 */ hcan1.Instance = CAN1; 8001124: 4b17 ldr r3, [pc, #92] ; (8001184 ) 8001126: 4a18 ldr r2, [pc, #96] ; (8001188 ) 8001128: 601a str r2, [r3, #0] hcan1.Init.Prescaler = 8; 800112a: 4b16 ldr r3, [pc, #88] ; (8001184 ) 800112c: 2208 movs r2, #8 800112e: 605a str r2, [r3, #4] hcan1.Init.Mode = CAN_MODE_NORMAL; 8001130: 4b14 ldr r3, [pc, #80] ; (8001184 ) 8001132: 2200 movs r2, #0 8001134: 609a str r2, [r3, #8] hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; 8001136: 4b13 ldr r3, [pc, #76] ; (8001184 ) 8001138: 2200 movs r2, #0 800113a: 60da str r2, [r3, #12] hcan1.Init.TimeSeg1 = CAN_BS1_15TQ; 800113c: 4b11 ldr r3, [pc, #68] ; (8001184 ) 800113e: f44f 2260 mov.w r2, #917504 ; 0xe0000 8001142: 611a str r2, [r3, #16] hcan1.Init.TimeSeg2 = CAN_BS2_2TQ; 8001144: 4b0f ldr r3, [pc, #60] ; (8001184 ) 8001146: f44f 1280 mov.w r2, #1048576 ; 0x100000 800114a: 615a str r2, [r3, #20] hcan1.Init.TimeTriggeredMode = DISABLE; 800114c: 4b0d ldr r3, [pc, #52] ; (8001184 ) 800114e: 2200 movs r2, #0 8001150: 761a strb r2, [r3, #24] hcan1.Init.AutoBusOff = ENABLE; 8001152: 4b0c ldr r3, [pc, #48] ; (8001184 ) 8001154: 2201 movs r2, #1 8001156: 765a strb r2, [r3, #25] hcan1.Init.AutoWakeUp = ENABLE; 8001158: 4b0a ldr r3, [pc, #40] ; (8001184 ) 800115a: 2201 movs r2, #1 800115c: 769a strb r2, [r3, #26] hcan1.Init.AutoRetransmission = DISABLE; 800115e: 4b09 ldr r3, [pc, #36] ; (8001184 ) 8001160: 2200 movs r2, #0 8001162: 76da strb r2, [r3, #27] hcan1.Init.ReceiveFifoLocked = DISABLE; 8001164: 4b07 ldr r3, [pc, #28] ; (8001184 ) 8001166: 2200 movs r2, #0 8001168: 771a strb r2, [r3, #28] hcan1.Init.TransmitFifoPriority = ENABLE; 800116a: 4b06 ldr r3, [pc, #24] ; (8001184 ) 800116c: 2201 movs r2, #1 800116e: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan1) != HAL_OK) 8001170: 4804 ldr r0, [pc, #16] ; (8001184 ) 8001172: f003 faa7 bl 80046c4 8001176: 4603 mov r3, r0 8001178: 2b00 cmp r3, #0 800117a: d001 beq.n 8001180 { Error_Handler(); 800117c: f002 fa20 bl 80035c0 } /* USER CODE BEGIN CAN1_Init 2 */ /* USER CODE END CAN1_Init 2 */ } 8001180: bf00 nop 8001182: bd80 pop {r7, pc} 8001184: 200000bc .word 0x200000bc 8001188: 40006400 .word 0x40006400 0800118c : /* CAN2 init function */ void MX_CAN2_Init(void) { 800118c: b580 push {r7, lr} 800118e: af00 add r7, sp, #0 /* USER CODE END CAN2_Init 0 */ /* USER CODE BEGIN CAN2_Init 1 */ /* USER CODE END CAN2_Init 1 */ hcan2.Instance = CAN2; 8001190: 4b17 ldr r3, [pc, #92] ; (80011f0 ) 8001192: 4a18 ldr r2, [pc, #96] ; (80011f4 ) 8001194: 601a str r2, [r3, #0] hcan2.Init.Prescaler = 16; 8001196: 4b16 ldr r3, [pc, #88] ; (80011f0 ) 8001198: 2210 movs r2, #16 800119a: 605a str r2, [r3, #4] hcan2.Init.Mode = CAN_MODE_NORMAL; 800119c: 4b14 ldr r3, [pc, #80] ; (80011f0 ) 800119e: 2200 movs r2, #0 80011a0: 609a str r2, [r3, #8] hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; 80011a2: 4b13 ldr r3, [pc, #76] ; (80011f0 ) 80011a4: 2200 movs r2, #0 80011a6: 60da str r2, [r3, #12] hcan2.Init.TimeSeg1 = CAN_BS1_15TQ; 80011a8: 4b11 ldr r3, [pc, #68] ; (80011f0 ) 80011aa: f44f 2260 mov.w r2, #917504 ; 0xe0000 80011ae: 611a str r2, [r3, #16] hcan2.Init.TimeSeg2 = CAN_BS2_2TQ; 80011b0: 4b0f ldr r3, [pc, #60] ; (80011f0 ) 80011b2: f44f 1280 mov.w r2, #1048576 ; 0x100000 80011b6: 615a str r2, [r3, #20] hcan2.Init.TimeTriggeredMode = DISABLE; 80011b8: 4b0d ldr r3, [pc, #52] ; (80011f0 ) 80011ba: 2200 movs r2, #0 80011bc: 761a strb r2, [r3, #24] hcan2.Init.AutoBusOff = ENABLE; 80011be: 4b0c ldr r3, [pc, #48] ; (80011f0 ) 80011c0: 2201 movs r2, #1 80011c2: 765a strb r2, [r3, #25] hcan2.Init.AutoWakeUp = ENABLE; 80011c4: 4b0a ldr r3, [pc, #40] ; (80011f0 ) 80011c6: 2201 movs r2, #1 80011c8: 769a strb r2, [r3, #26] hcan2.Init.AutoRetransmission = DISABLE; 80011ca: 4b09 ldr r3, [pc, #36] ; (80011f0 ) 80011cc: 2200 movs r2, #0 80011ce: 76da strb r2, [r3, #27] hcan2.Init.ReceiveFifoLocked = DISABLE; 80011d0: 4b07 ldr r3, [pc, #28] ; (80011f0 ) 80011d2: 2200 movs r2, #0 80011d4: 771a strb r2, [r3, #28] hcan2.Init.TransmitFifoPriority = ENABLE; 80011d6: 4b06 ldr r3, [pc, #24] ; (80011f0 ) 80011d8: 2201 movs r2, #1 80011da: 775a strb r2, [r3, #29] if (HAL_CAN_Init(&hcan2) != HAL_OK) 80011dc: 4804 ldr r0, [pc, #16] ; (80011f0 ) 80011de: f003 fa71 bl 80046c4 80011e2: 4603 mov r3, r0 80011e4: 2b00 cmp r3, #0 80011e6: d001 beq.n 80011ec { Error_Handler(); 80011e8: f002 f9ea bl 80035c0 } /* USER CODE BEGIN CAN2_Init 2 */ /* USER CODE END CAN2_Init 2 */ } 80011ec: bf00 nop 80011ee: bd80 pop {r7, pc} 80011f0: 200000e4 .word 0x200000e4 80011f4: 40006800 .word 0x40006800 080011f8 : static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0; void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) { 80011f8: b580 push {r7, lr} 80011fa: b08e sub sp, #56 ; 0x38 80011fc: af00 add r7, sp, #0 80011fe: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001200: f107 0320 add.w r3, r7, #32 8001204: 2200 movs r2, #0 8001206: 601a str r2, [r3, #0] 8001208: 605a str r2, [r3, #4] 800120a: 609a str r2, [r3, #8] 800120c: 60da str r2, [r3, #12] if(canHandle->Instance==CAN1) 800120e: 687b ldr r3, [r7, #4] 8001210: 681b ldr r3, [r3, #0] 8001212: 4a61 ldr r2, [pc, #388] ; (8001398 ) 8001214: 4293 cmp r3, r2 8001216: d153 bne.n 80012c0 { /* USER CODE BEGIN CAN1_MspInit 0 */ /* USER CODE END CAN1_MspInit 0 */ /* CAN1 clock enable */ HAL_RCC_CAN1_CLK_ENABLED++; 8001218: 4b60 ldr r3, [pc, #384] ; (800139c ) 800121a: 681b ldr r3, [r3, #0] 800121c: 3301 adds r3, #1 800121e: 4a5f ldr r2, [pc, #380] ; (800139c ) 8001220: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 8001222: 4b5e ldr r3, [pc, #376] ; (800139c ) 8001224: 681b ldr r3, [r3, #0] 8001226: 2b01 cmp r3, #1 8001228: d10b bne.n 8001242 __HAL_RCC_CAN1_CLK_ENABLE(); 800122a: 4b5d ldr r3, [pc, #372] ; (80013a0 ) 800122c: 69db ldr r3, [r3, #28] 800122e: 4a5c ldr r2, [pc, #368] ; (80013a0 ) 8001230: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 8001234: 61d3 str r3, [r2, #28] 8001236: 4b5a ldr r3, [pc, #360] ; (80013a0 ) 8001238: 69db ldr r3, [r3, #28] 800123a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800123e: 61fb str r3, [r7, #28] 8001240: 69fb ldr r3, [r7, #28] } __HAL_RCC_GPIOD_CLK_ENABLE(); 8001242: 4b57 ldr r3, [pc, #348] ; (80013a0 ) 8001244: 699b ldr r3, [r3, #24] 8001246: 4a56 ldr r2, [pc, #344] ; (80013a0 ) 8001248: f043 0320 orr.w r3, r3, #32 800124c: 6193 str r3, [r2, #24] 800124e: 4b54 ldr r3, [pc, #336] ; (80013a0 ) 8001250: 699b ldr r3, [r3, #24] 8001252: f003 0320 and.w r3, r3, #32 8001256: 61bb str r3, [r7, #24] 8001258: 69bb ldr r3, [r7, #24] /**CAN1 GPIO Configuration PD0 ------> CAN1_RX PD1 ------> CAN1_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0; 800125a: 2301 movs r3, #1 800125c: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800125e: 2300 movs r3, #0 8001260: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001262: 2300 movs r3, #0 8001264: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001266: f107 0320 add.w r3, r7, #32 800126a: 4619 mov r1, r3 800126c: 484d ldr r0, [pc, #308] ; (80013a4 ) 800126e: f004 fb25 bl 80058bc GPIO_InitStruct.Pin = GPIO_PIN_1; 8001272: 2302 movs r3, #2 8001274: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001276: 2302 movs r3, #2 8001278: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800127a: 2303 movs r3, #3 800127c: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800127e: f107 0320 add.w r3, r7, #32 8001282: 4619 mov r1, r3 8001284: 4847 ldr r0, [pc, #284] ; (80013a4 ) 8001286: f004 fb19 bl 80058bc __HAL_AFIO_REMAP_CAN1_3(); 800128a: 4b47 ldr r3, [pc, #284] ; (80013a8 ) 800128c: 685b ldr r3, [r3, #4] 800128e: 633b str r3, [r7, #48] ; 0x30 8001290: 6b3b ldr r3, [r7, #48] ; 0x30 8001292: f423 43c0 bic.w r3, r3, #24576 ; 0x6000 8001296: 633b str r3, [r7, #48] ; 0x30 8001298: 6b3b ldr r3, [r7, #48] ; 0x30 800129a: f043 63e0 orr.w r3, r3, #117440512 ; 0x7000000 800129e: 633b str r3, [r7, #48] ; 0x30 80012a0: 6b3b ldr r3, [r7, #48] ; 0x30 80012a2: f443 43c0 orr.w r3, r3, #24576 ; 0x6000 80012a6: 633b str r3, [r7, #48] ; 0x30 80012a8: 4a3f ldr r2, [pc, #252] ; (80013a8 ) 80012aa: 6b3b ldr r3, [r7, #48] ; 0x30 80012ac: 6053 str r3, [r2, #4] /* CAN1 interrupt Init */ HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 0, 0); 80012ae: 2200 movs r2, #0 80012b0: 2100 movs r1, #0 80012b2: 2014 movs r0, #20 80012b4: f004 f989 bl 80055ca HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn); 80012b8: 2014 movs r0, #20 80012ba: f004 f9a2 bl 8005602 HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); /* USER CODE BEGIN CAN2_MspInit 1 */ /* USER CODE END CAN2_MspInit 1 */ } } 80012be: e067 b.n 8001390 else if(canHandle->Instance==CAN2) 80012c0: 687b ldr r3, [r7, #4] 80012c2: 681b ldr r3, [r3, #0] 80012c4: 4a39 ldr r2, [pc, #228] ; (80013ac ) 80012c6: 4293 cmp r3, r2 80012c8: d162 bne.n 8001390 __HAL_RCC_CAN2_CLK_ENABLE(); 80012ca: 4b35 ldr r3, [pc, #212] ; (80013a0 ) 80012cc: 69db ldr r3, [r3, #28] 80012ce: 4a34 ldr r2, [pc, #208] ; (80013a0 ) 80012d0: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 80012d4: 61d3 str r3, [r2, #28] 80012d6: 4b32 ldr r3, [pc, #200] ; (80013a0 ) 80012d8: 69db ldr r3, [r3, #28] 80012da: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 80012de: 617b str r3, [r7, #20] 80012e0: 697b ldr r3, [r7, #20] HAL_RCC_CAN1_CLK_ENABLED++; 80012e2: 4b2e ldr r3, [pc, #184] ; (800139c ) 80012e4: 681b ldr r3, [r3, #0] 80012e6: 3301 adds r3, #1 80012e8: 4a2c ldr r2, [pc, #176] ; (800139c ) 80012ea: 6013 str r3, [r2, #0] if(HAL_RCC_CAN1_CLK_ENABLED==1){ 80012ec: 4b2b ldr r3, [pc, #172] ; (800139c ) 80012ee: 681b ldr r3, [r3, #0] 80012f0: 2b01 cmp r3, #1 80012f2: d10b bne.n 800130c __HAL_RCC_CAN1_CLK_ENABLE(); 80012f4: 4b2a ldr r3, [pc, #168] ; (80013a0 ) 80012f6: 69db ldr r3, [r3, #28] 80012f8: 4a29 ldr r2, [pc, #164] ; (80013a0 ) 80012fa: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 80012fe: 61d3 str r3, [r2, #28] 8001300: 4b27 ldr r3, [pc, #156] ; (80013a0 ) 8001302: 69db ldr r3, [r3, #28] 8001304: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8001308: 613b str r3, [r7, #16] 800130a: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 800130c: 4b24 ldr r3, [pc, #144] ; (80013a0 ) 800130e: 699b ldr r3, [r3, #24] 8001310: 4a23 ldr r2, [pc, #140] ; (80013a0 ) 8001312: f043 0308 orr.w r3, r3, #8 8001316: 6193 str r3, [r2, #24] 8001318: 4b21 ldr r3, [pc, #132] ; (80013a0 ) 800131a: 699b ldr r3, [r3, #24] 800131c: f003 0308 and.w r3, r3, #8 8001320: 60fb str r3, [r7, #12] 8001322: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_5; 8001324: 2320 movs r3, #32 8001326: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001328: 2300 movs r3, #0 800132a: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 800132c: 2300 movs r3, #0 800132e: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001330: f107 0320 add.w r3, r7, #32 8001334: 4619 mov r1, r3 8001336: 481e ldr r0, [pc, #120] ; (80013b0 ) 8001338: f004 fac0 bl 80058bc GPIO_InitStruct.Pin = GPIO_PIN_6; 800133c: 2340 movs r3, #64 ; 0x40 800133e: 623b str r3, [r7, #32] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001340: 2302 movs r3, #2 8001342: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001344: 2303 movs r3, #3 8001346: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001348: f107 0320 add.w r3, r7, #32 800134c: 4619 mov r1, r3 800134e: 4818 ldr r0, [pc, #96] ; (80013b0 ) 8001350: f004 fab4 bl 80058bc __HAL_AFIO_REMAP_CAN2_ENABLE(); 8001354: 4b14 ldr r3, [pc, #80] ; (80013a8 ) 8001356: 685b ldr r3, [r3, #4] 8001358: 637b str r3, [r7, #52] ; 0x34 800135a: 6b7b ldr r3, [r7, #52] ; 0x34 800135c: f043 63e0 orr.w r3, r3, #117440512 ; 0x7000000 8001360: 637b str r3, [r7, #52] ; 0x34 8001362: 6b7b ldr r3, [r7, #52] ; 0x34 8001364: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 8001368: 637b str r3, [r7, #52] ; 0x34 800136a: 4a0f ldr r2, [pc, #60] ; (80013a8 ) 800136c: 6b7b ldr r3, [r7, #52] ; 0x34 800136e: 6053 str r3, [r2, #4] HAL_NVIC_SetPriority(CAN2_TX_IRQn, 0, 0); 8001370: 2200 movs r2, #0 8001372: 2100 movs r1, #0 8001374: 203f movs r0, #63 ; 0x3f 8001376: f004 f928 bl 80055ca HAL_NVIC_EnableIRQ(CAN2_TX_IRQn); 800137a: 203f movs r0, #63 ; 0x3f 800137c: f004 f941 bl 8005602 HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 0, 0); 8001380: 2200 movs r2, #0 8001382: 2100 movs r1, #0 8001384: 2041 movs r0, #65 ; 0x41 8001386: f004 f920 bl 80055ca HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); 800138a: 2041 movs r0, #65 ; 0x41 800138c: f004 f939 bl 8005602 } 8001390: bf00 nop 8001392: 3738 adds r7, #56 ; 0x38 8001394: 46bd mov sp, r7 8001396: bd80 pop {r7, pc} 8001398: 40006400 .word 0x40006400 800139c: 2000010c .word 0x2000010c 80013a0: 40021000 .word 0x40021000 80013a4: 40011400 .word 0x40011400 80013a8: 40010000 .word 0x40010000 80013ac: 40006800 .word 0x40006800 80013b0: 40010c00 .word 0x40010c00 080013b4 : uint8_t GBT_BRO; extern GBT_EDCAN_Output_t GBT_EDCAN_Output; void GBT_Init(){ 80013b4: b580 push {r7, lr} 80013b6: af00 add r7, sp, #0 GBT_State = GBT_DISABLED; 80013b8: 4b03 ldr r3, [pc, #12] ; (80013c8 ) 80013ba: 2200 movs r2, #0 80013bc: 701a strb r2, [r3, #0] GBT_Lock(0); 80013be: 2000 movs r0, #0 80013c0: f7ff fe26 bl 8001010 } 80013c4: bf00 nop 80013c6: bd80 pop {r7, pc} 80013c8: 20000110 .word 0x20000110 080013cc : uint8_t GBT_CC_GetState(){ 80013cc: b580 push {r7, lr} 80013ce: b082 sub sp, #8 80013d0: af00 add r7, sp, #0 //Vin*k= 1.09v //12vin = 1353 ADC //TODO: Filter 100ms uint32_t adc; float volt; ADC_Select_Channel(ADC_CHANNEL_6); 80013d2: 2006 movs r0, #6 80013d4: f7ff fe88 bl 80010e8 HAL_ADC_Start(&hadc1); 80013d8: 482e ldr r0, [pc, #184] ; (8001494 ) 80013da: f002 fd47 bl 8003e6c HAL_ADC_PollForConversion(&hadc1, 100); 80013de: 2164 movs r1, #100 ; 0x64 80013e0: 482c ldr r0, [pc, #176] ; (8001494 ) 80013e2: f002 fe1d bl 8004020 adc = HAL_ADC_GetValue(&hadc1); 80013e6: 482b ldr r0, [pc, #172] ; (8001494 ) 80013e8: f002 ff20 bl 800422c 80013ec: 6078 str r0, [r7, #4] HAL_ADC_Stop(&hadc1); 80013ee: 4829 ldr r0, [pc, #164] ; (8001494 ) 80013f0: f002 fdea bl 8003fc8 volt = (float)adc/113.4f; 80013f4: 6878 ldr r0, [r7, #4] 80013f6: f7ff f987 bl 8000708 <__aeabi_ui2f> 80013fa: 4603 mov r3, r0 80013fc: 4926 ldr r1, [pc, #152] ; (8001498 ) 80013fe: 4618 mov r0, r3 8001400: f7ff fa8e bl 8000920 <__aeabi_fdiv> 8001404: 4603 mov r3, r0 8001406: 603b str r3, [r7, #0] if((volt<12.6f) && (volt>11.4f)) return GBT_CC_12V; 8001408: 4924 ldr r1, [pc, #144] ; (800149c ) 800140a: 6838 ldr r0, [r7, #0] 800140c: f7ff fb72 bl 8000af4 <__aeabi_fcmplt> 8001410: 4603 mov r3, r0 8001412: 2b00 cmp r3, #0 8001414: d008 beq.n 8001428 8001416: 4922 ldr r1, [pc, #136] ; (80014a0 ) 8001418: 6838 ldr r0, [r7, #0] 800141a: f7ff fb89 bl 8000b30 <__aeabi_fcmpgt> 800141e: 4603 mov r3, r0 8001420: 2b00 cmp r3, #0 8001422: d001 beq.n 8001428 8001424: 2301 movs r3, #1 8001426: e030 b.n 800148a if((volt<6.8f) && (volt>5.2f)) return GBT_CC_6V; 8001428: 491e ldr r1, [pc, #120] ; (80014a4 ) 800142a: 6838 ldr r0, [r7, #0] 800142c: f7ff fb62 bl 8000af4 <__aeabi_fcmplt> 8001430: 4603 mov r3, r0 8001432: 2b00 cmp r3, #0 8001434: d008 beq.n 8001448 8001436: 491c ldr r1, [pc, #112] ; (80014a8 ) 8001438: 6838 ldr r0, [r7, #0] 800143a: f7ff fb79 bl 8000b30 <__aeabi_fcmpgt> 800143e: 4603 mov r3, r0 8001440: 2b00 cmp r3, #0 8001442: d001 beq.n 8001448 8001444: 2302 movs r3, #2 8001446: e020 b.n 800148a if((volt<4.8f) && (volt>3.2f)) return GBT_CC_4V; 8001448: 4918 ldr r1, [pc, #96] ; (80014ac ) 800144a: 6838 ldr r0, [r7, #0] 800144c: f7ff fb52 bl 8000af4 <__aeabi_fcmplt> 8001450: 4603 mov r3, r0 8001452: 2b00 cmp r3, #0 8001454: d008 beq.n 8001468 8001456: 4916 ldr r1, [pc, #88] ; (80014b0 ) 8001458: 6838 ldr r0, [r7, #0] 800145a: f7ff fb69 bl 8000b30 <__aeabi_fcmpgt> 800145e: 4603 mov r3, r0 8001460: 2b00 cmp r3, #0 8001462: d001 beq.n 8001468 8001464: 2303 movs r3, #3 8001466: e010 b.n 800148a if((volt<2.8f) && (volt>1.2f)) return GBT_CC_2V; 8001468: 4912 ldr r1, [pc, #72] ; (80014b4 ) 800146a: 6838 ldr r0, [r7, #0] 800146c: f7ff fb42 bl 8000af4 <__aeabi_fcmplt> 8001470: 4603 mov r3, r0 8001472: 2b00 cmp r3, #0 8001474: d008 beq.n 8001488 8001476: 4910 ldr r1, [pc, #64] ; (80014b8 ) 8001478: 6838 ldr r0, [r7, #0] 800147a: f7ff fb59 bl 8000b30 <__aeabi_fcmpgt> 800147e: 4603 mov r3, r0 8001480: 2b00 cmp r3, #0 8001482: d001 beq.n 8001488 8001484: 2304 movs r3, #4 8001486: e000 b.n 800148a return GBT_CC_UNKNOWN; 8001488: 2300 movs r3, #0 } 800148a: 4618 mov r0, r3 800148c: 3708 adds r7, #8 800148e: 46bd mov sp, r7 8001490: bd80 pop {r7, pc} 8001492: bf00 nop 8001494: 2000008c .word 0x2000008c 8001498: 42e2cccd .word 0x42e2cccd 800149c: 4149999a .word 0x4149999a 80014a0: 41366666 .word 0x41366666 80014a4: 40d9999a .word 0x40d9999a 80014a8: 40a66666 .word 0x40a66666 80014ac: 4099999a .word 0x4099999a 80014b0: 404ccccd .word 0x404ccccd 80014b4: 40333333 .word 0x40333333 80014b8: 3f99999a .word 0x3f99999a 080014bc : float GBT_CC_GetAdc(){ 80014bc: b580 push {r7, lr} 80014be: b082 sub sp, #8 80014c0: af00 add r7, sp, #0 //Vin*k= 1.09v //12vin = 1353 ADC uint32_t adc; float volt; ADC_Select_Channel(ADC_CHANNEL_6); 80014c2: 2006 movs r0, #6 80014c4: f7ff fe10 bl 80010e8 HAL_ADC_Start(&hadc1); 80014c8: 480e ldr r0, [pc, #56] ; (8001504 ) 80014ca: f002 fccf bl 8003e6c HAL_ADC_PollForConversion(&hadc1, 100); 80014ce: 2164 movs r1, #100 ; 0x64 80014d0: 480c ldr r0, [pc, #48] ; (8001504 ) 80014d2: f002 fda5 bl 8004020 adc = HAL_ADC_GetValue(&hadc1); 80014d6: 480b ldr r0, [pc, #44] ; (8001504 ) 80014d8: f002 fea8 bl 800422c 80014dc: 6078 str r0, [r7, #4] HAL_ADC_Stop(&hadc1); 80014de: 4809 ldr r0, [pc, #36] ; (8001504 ) 80014e0: f002 fd72 bl 8003fc8 volt = (float)adc/113.4f; 80014e4: 6878 ldr r0, [r7, #4] 80014e6: f7ff f90f bl 8000708 <__aeabi_ui2f> 80014ea: 4603 mov r3, r0 80014ec: 4906 ldr r1, [pc, #24] ; (8001508 ) 80014ee: 4618 mov r0, r3 80014f0: f7ff fa16 bl 8000920 <__aeabi_fdiv> 80014f4: 4603 mov r3, r0 80014f6: 603b str r3, [r7, #0] return volt; 80014f8: 683b ldr r3, [r7, #0] } 80014fa: 4618 mov r0, r3 80014fc: 3708 adds r7, #8 80014fe: 46bd mov sp, r7 8001500: bd80 pop {r7, pc} 8001502: bf00 nop 8001504: 2000008c .word 0x2000008c 8001508: 42e2cccd .word 0x42e2cccd 0800150c : void GBT_ChargerTask(){ 800150c: b5b0 push {r4, r5, r7, lr} 800150e: b082 sub sp, #8 8001510: af00 add r7, sp, #0 if(j_rx.state == 2){ 8001512: 4bae ldr r3, [pc, #696] ; (80017cc ) 8001514: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 8001518: 2b02 cmp r3, #2 800151a: f040 80b9 bne.w 8001690 switch (j_rx.PGN){ 800151e: 4bab ldr r3, [pc, #684] ; (80017cc ) 8001520: f8d3 3100 ldr.w r3, [r3, #256] ; 0x100 8001524: f5b3 5f1c cmp.w r3, #9984 ; 0x2700 8001528: d03c beq.n 80015a4 800152a: f5b3 5f1c cmp.w r3, #9984 ; 0x2700 800152e: f200 80ab bhi.w 8001688 8001532: f5b3 5fb8 cmp.w r3, #5888 ; 0x1700 8001536: f000 80a2 beq.w 800167e 800153a: f5b3 5fb8 cmp.w r3, #5888 ; 0x1700 800153e: f200 80a3 bhi.w 8001688 8001542: f5b3 5fb0 cmp.w r3, #5632 ; 0x1600 8001546: f000 809c beq.w 8001682 800154a: f5b3 5fb0 cmp.w r3, #5632 ; 0x1600 800154e: f200 809b bhi.w 8001688 8001552: f5b3 5fa8 cmp.w r3, #5376 ; 0x1500 8001556: f000 8096 beq.w 8001686 800155a: f5b3 5fa8 cmp.w r3, #5376 ; 0x1500 800155e: f200 8093 bhi.w 8001688 8001562: f5b3 5f98 cmp.w r3, #4864 ; 0x1300 8001566: d07f beq.n 8001668 8001568: f5b3 5f98 cmp.w r3, #4864 ; 0x1300 800156c: f200 808c bhi.w 8001688 8001570: f5b3 5f88 cmp.w r3, #4352 ; 0x1100 8001574: d061 beq.n 800163a 8001576: f5b3 5f88 cmp.w r3, #4352 ; 0x1100 800157a: f200 8085 bhi.w 8001688 800157e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8001582: d03e beq.n 8001602 8001584: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8001588: d87e bhi.n 8001688 800158a: f5b3 6f10 cmp.w r3, #2304 ; 0x900 800158e: d028 beq.n 80015e2 8001590: f5b3 6f10 cmp.w r3, #2304 ; 0x900 8001594: d878 bhi.n 8001688 8001596: f5b3 7f00 cmp.w r3, #512 ; 0x200 800159a: d008 beq.n 80015ae 800159c: f5b3 6fc0 cmp.w r3, #1536 ; 0x600 80015a0: d015 beq.n 80015ce 80015a2: e071 b.n 8001688 80015a4: 4b89 ldr r3, [pc, #548] ; (80017cc ) 80015a6: 881a ldrh r2, [r3, #0] case 0x2700: //PGN BHM memcpy (&GBT_MaxVoltage, j_rx.data, sizeof(GBT_MaxVoltage)); 80015a8: 4b89 ldr r3, [pc, #548] ; (80017d0 ) 80015aa: 801a strh r2, [r3, #0] break; 80015ac: e06c b.n 8001688 case 0x0200: //PGN BRM LONG GBT_BAT_INFO_recv = 1; 80015ae: 4b89 ldr r3, [pc, #548] ; (80017d4 ) 80015b0: 2201 movs r2, #1 80015b2: 701a strb r2, [r3, #0] memcpy (&GBT_EVInfo, j_rx.data, sizeof(GBT_EVInfo)); 80015b4: 4a88 ldr r2, [pc, #544] ; (80017d8 ) 80015b6: 4b85 ldr r3, [pc, #532] ; (80017cc ) 80015b8: 4614 mov r4, r2 80015ba: 461d mov r5, r3 80015bc: cd0f ldmia r5!, {r0, r1, r2, r3} 80015be: c40f stmia r4!, {r0, r1, r2, r3} 80015c0: cd0f ldmia r5!, {r0, r1, r2, r3} 80015c2: c40f stmia r4!, {r0, r1, r2, r3} 80015c4: cd0f ldmia r5!, {r0, r1, r2, r3} 80015c6: c40f stmia r4!, {r0, r1, r2, r3} 80015c8: 682b ldr r3, [r5, #0] 80015ca: 7023 strb r3, [r4, #0] break; 80015cc: e05c b.n 8001688 case 0x0600: //PGN BCP LONG GBT_BAT_STAT_recv = 1; 80015ce: 4b83 ldr r3, [pc, #524] ; (80017dc ) 80015d0: 2201 movs r2, #1 80015d2: 701a strb r2, [r3, #0] memcpy (&GBT_BATStat, j_rx.data, sizeof(GBT_BATStat)); 80015d4: 4a82 ldr r2, [pc, #520] ; (80017e0 ) 80015d6: 4b7d ldr r3, [pc, #500] ; (80017cc ) 80015d8: 4614 mov r4, r2 80015da: cb0f ldmia r3, {r0, r1, r2, r3} 80015dc: c407 stmia r4!, {r0, r1, r2} 80015de: 7023 strb r3, [r4, #0] break; 80015e0: e052 b.n 8001688 case 0x0900: //PGN BRO if(j_rx.data[0] == 0xAA) EV_ready = 1; 80015e2: 4b7a ldr r3, [pc, #488] ; (80017cc ) 80015e4: 781b ldrb r3, [r3, #0] 80015e6: 2baa cmp r3, #170 ; 0xaa 80015e8: d103 bne.n 80015f2 80015ea: 4b7e ldr r3, [pc, #504] ; (80017e4 ) 80015ec: 2201 movs r2, #1 80015ee: 701a strb r2, [r3, #0] 80015f0: e002 b.n 80015f8 else EV_ready = 0; 80015f2: 4b7c ldr r3, [pc, #496] ; (80017e4 ) 80015f4: 2200 movs r2, #0 80015f6: 701a strb r2, [r3, #0] GBT_BRO = j_rx.data[0]; 80015f8: 4b74 ldr r3, [pc, #464] ; (80017cc ) 80015fa: 781a ldrb r2, [r3, #0] 80015fc: 4b7a ldr r3, [pc, #488] ; (80017e8 ) 80015fe: 701a strb r2, [r3, #0] break; 8001600: e042 b.n 8001688 case 0x1000: //PGN BCL //TODO: power block memcpy (&GBT_ReqPower, j_rx.data, sizeof(GBT_ReqPower)); 8001602: 4b7a ldr r3, [pc, #488] ; (80017ec ) 8001604: 4a71 ldr r2, [pc, #452] ; (80017cc ) 8001606: e892 0003 ldmia.w r2, {r0, r1} 800160a: 6018 str r0, [r3, #0] 800160c: 3304 adds r3, #4 800160e: 7019 strb r1, [r3, #0] uint16_t volt=GBT_ReqPower.requestedVoltage/10; 8001610: 4b76 ldr r3, [pc, #472] ; (80017ec ) 8001612: 881b ldrh r3, [r3, #0] 8001614: 4a76 ldr r2, [pc, #472] ; (80017f0 ) 8001616: fba2 2303 umull r2, r3, r2, r3 800161a: 08db lsrs r3, r3, #3 800161c: 80fb strh r3, [r7, #6] GBT_EDCAN_Output.requestedVoltage = volt; 800161e: 4b75 ldr r3, [pc, #468] ; (80017f4 ) 8001620: 88fa ldrh r2, [r7, #6] 8001622: f8a3 2001 strh.w r2, [r3, #1] uint16_t curr=(4000-GBT_ReqPower.requestedCurrent); 8001626: 4b71 ldr r3, [pc, #452] ; (80017ec ) 8001628: 885b ldrh r3, [r3, #2] 800162a: f5c3 637a rsb r3, r3, #4000 ; 0xfa0 800162e: 80bb strh r3, [r7, #4] GBT_EDCAN_Output.requestedCurrent = curr; 8001630: 4b70 ldr r3, [pc, #448] ; (80017f4 ) 8001632: 88ba ldrh r2, [r7, #4] 8001634: f8a3 2003 strh.w r2, [r3, #3] break; 8001638: e026 b.n 8001688 case 0x1100: //PGN BCS //TODO memcpy (&GBT_ChargingStatus, j_rx.data, sizeof(GBT_ChargingStatus)); 800163a: 4b6f ldr r3, [pc, #444] ; (80017f8 ) 800163c: 4a63 ldr r2, [pc, #396] ; (80017cc ) 800163e: ca07 ldmia r2, {r0, r1, r2} 8001640: c303 stmia r3!, {r0, r1} 8001642: 801a strh r2, [r3, #0] 8001644: 3302 adds r3, #2 8001646: 0c12 lsrs r2, r2, #16 8001648: 701a strb r2, [r3, #0] GBT_EDCAN_Output.chargingRemainingTimeMin = GBT_ChargingStatus.estimatedRemainingChargingTime; 800164a: 4b6b ldr r3, [pc, #428] ; (80017f8 ) 800164c: f8b3 3009 ldrh.w r3, [r3, #9] 8001650: b29a uxth r2, r3 8001652: 4b68 ldr r3, [pc, #416] ; (80017f4 ) 8001654: f8a3 2007 strh.w r2, [r3, #7] GBT_EDCAN_Output.chargingPercentage = GBT_ChargingStatus.currentChargeState; 8001658: 4b67 ldr r3, [pc, #412] ; (80017f8 ) 800165a: f8b3 3007 ldrh.w r3, [r3, #7] 800165e: b29b uxth r3, r3 8001660: b2da uxtb r2, r3 8001662: 4b64 ldr r3, [pc, #400] ; (80017f4 ) 8001664: 719a strb r2, [r3, #6] break; 8001666: e00f b.n 8001688 case 0x1300: //PGN BSM //TODO memcpy (&GBT_BatteryStatus, j_rx.data, sizeof(GBT_BatteryStatus)); 8001668: 4b64 ldr r3, [pc, #400] ; (80017fc ) 800166a: 4a58 ldr r2, [pc, #352] ; (80017cc ) 800166c: e892 0003 ldmia.w r2, {r0, r1} 8001670: 6018 str r0, [r3, #0] 8001672: 3304 adds r3, #4 8001674: 8019 strh r1, [r3, #0] 8001676: 3302 adds r3, #2 8001678: 0c0a lsrs r2, r1, #16 800167a: 701a strb r2, [r3, #0] break; 800167c: e004 b.n 8001688 //TODO break; case 0x1700: //PGN BSP //TODO break; 800167e: bf00 nop 8001680: e002 b.n 8001688 break; 8001682: bf00 nop 8001684: e000 b.n 8001688 break; 8001686: bf00 nop //BSM BMV BMT BSP BST BSD BEM } j_rx.state = 0; 8001688: 4b50 ldr r3, [pc, #320] ; (80017cc ) 800168a: 2200 movs r2, #0 800168c: f883 210a strb.w r2, [r3, #266] ; 0x10a } if(GBT_delay>HAL_GetTick()){ 8001690: f002 fae6 bl 8003c60 8001694: 4602 mov r2, r0 8001696: 4b5a ldr r3, [pc, #360] ; (8001800 ) 8001698: 681b ldr r3, [r3, #0] 800169a: 429a cmp r2, r3 800169c: f0c0 8149 bcc.w 8001932 //waiting }else switch (GBT_State){ 80016a0: 4b58 ldr r3, [pc, #352] ; (8001804 ) 80016a2: 781b ldrb r3, [r3, #0] 80016a4: 2b0c cmp r3, #12 80016a6: f200 812f bhi.w 8001908 80016aa: a201 add r2, pc, #4 ; (adr r2, 80016b0 ) 80016ac: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80016b0: 08001911 .word 0x08001911 80016b4: 080016e5 .word 0x080016e5 80016b8: 08001701 .word 0x08001701 80016bc: 08001729 .word 0x08001729 80016c0: 08001741 .word 0x08001741 80016c4: 08001751 .word 0x08001751 80016c8: 0800177d .word 0x0800177d 80016cc: 080017a5 .word 0x080017a5 80016d0: 08001809 .word 0x08001809 80016d4: 08001841 .word 0x08001841 80016d8: 0800186d .word 0x0800186d 80016dc: 080018c1 .word 0x080018c1 80016e0: 080018d7 .word 0x080018d7 case GBT_DISABLED: break; case GBT_S0_UNCONNECTED: if(GBT_CC_GetState()==GBT_CC_4V){ 80016e4: f7ff fe72 bl 80013cc 80016e8: 4603 mov r3, r0 80016ea: 2b03 cmp r3, #3 80016ec: f040 8112 bne.w 8001914 GBT_SwitchState(GBT_S1_CONNECTED); 80016f0: 2002 movs r0, #2 80016f2: f000 f92d bl 8001950 GBT_Delay(500); 80016f6: f44f 70fa mov.w r0, #500 ; 0x1f4 80016fa: f000 f9c5 bl 8001a88 } break; 80016fe: e109 b.n 8001914 case GBT_S1_CONNECTED: if(GBT_CC_GetState()==GBT_CC_4V){ 8001700: f7ff fe64 bl 80013cc 8001704: 4603 mov r3, r0 8001706: 2b03 cmp r3, #3 8001708: d10a bne.n 8001720 GBT_Lock(1); 800170a: 2001 movs r0, #1 800170c: f7ff fc80 bl 8001010 GBT_SwitchState(GBT_S2_LOCKED); 8001710: 2003 movs r0, #3 8001712: f000 f91d bl 8001950 GBT_Delay(500); 8001716: f44f 70fa mov.w r0, #500 ; 0x1f4 800171a: f000 f9b5 bl 8001a88 }else{ GBT_SwitchState(GBT_S0_UNCONNECTED); } break; 800171e: e108 b.n 8001932 GBT_SwitchState(GBT_S0_UNCONNECTED); 8001720: 2001 movs r0, #1 8001722: f000 f915 bl 8001950 break; 8001726: e104 b.n 8001932 case GBT_S2_LOCKED: if(1){ //TODO: charge permission RELAY_Write(RELAY_AUX, 1); // 13.8V AUX ON 8001728: 2101 movs r1, #1 800172a: 2000 movs r0, #0 800172c: f7ff fca6 bl 800107c GBT_SwitchState(GBT_S3_STARTED); 8001730: 2004 movs r0, #4 8001732: f000 f90d bl 8001950 GBT_Delay(500); 8001736: f44f 70fa mov.w r0, #500 ; 0x1f4 800173a: f000 f9a5 bl 8001a88 } break; 800173e: e0f8 b.n 8001932 case GBT_S3_STARTED: GBT_SwitchState(GBT_S4_ISOTEST); 8001740: 2005 movs r0, #5 8001742: f000 f905 bl 8001950 GBT_Delay(500); 8001746: f44f 70fa mov.w r0, #500 ; 0x1f4 800174a: f000 f99d bl 8001a88 break; 800174e: e0f0 b.n 8001932 case GBT_S4_ISOTEST: if(j_rx.state == 0) GBT_SendCHM(); 8001750: 4b1e ldr r3, [pc, #120] ; (80017cc ) 8001752: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 8001756: 2b00 cmp r3, #0 8001758: d101 bne.n 800175e 800175a: f000 fef5 bl 8002548 GBT_Delay(250); 800175e: 20fa movs r0, #250 ; 0xfa 8001760: f000 f992 bl 8001a88 //TODO: Isolation test //TODO: Timeout if(GBT_StateTick()>1500){ 8001764: f000 f984 bl 8001a70 8001768: 4603 mov r3, r0 800176a: f240 52dc movw r2, #1500 ; 0x5dc 800176e: 4293 cmp r3, r2 8001770: f240 80d2 bls.w 8001918 //Isolation test finish GBT_SwitchState(GBT_S5_BAT_INFO); 8001774: 2006 movs r0, #6 8001776: f000 f8eb bl 8001950 } break; 800177a: e0cd b.n 8001918 case GBT_S5_BAT_INFO: if(j_rx.state == 0) GBT_SendCRM(0x00); 800177c: 4b13 ldr r3, [pc, #76] ; (80017cc ) 800177e: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 8001782: 2b00 cmp r3, #0 8001784: d102 bne.n 800178c 8001786: 2000 movs r0, #0 8001788: f000 fef2 bl 8002570 GBT_Delay(250); 800178c: 20fa movs r0, #250 ; 0xfa 800178e: f000 f97b bl 8001a88 if(GBT_BAT_INFO_recv){ 8001792: 4b10 ldr r3, [pc, #64] ; (80017d4 ) 8001794: 781b ldrb r3, [r3, #0] 8001796: 2b00 cmp r3, #0 8001798: f000 80c0 beq.w 800191c //Got battery info GBT_SwitchState(GBT_S6_BAT_STAT); 800179c: 2007 movs r0, #7 800179e: f000 f8d7 bl 8001950 } break; 80017a2: e0bb b.n 800191c case GBT_S6_BAT_STAT: if(j_rx.state == 0) GBT_SendCRM(0xAA); 80017a4: 4b09 ldr r3, [pc, #36] ; (80017cc ) 80017a6: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 80017aa: 2b00 cmp r3, #0 80017ac: d102 bne.n 80017b4 80017ae: 20aa movs r0, #170 ; 0xaa 80017b0: f000 fede bl 8002570 GBT_Delay(250); 80017b4: 20fa movs r0, #250 ; 0xfa 80017b6: f000 f967 bl 8001a88 if(GBT_BAT_STAT_recv){ 80017ba: 4b08 ldr r3, [pc, #32] ; (80017dc ) 80017bc: 781b ldrb r3, [r3, #0] 80017be: 2b00 cmp r3, #0 80017c0: f000 80ae beq.w 8001920 //Got battery status GBT_SwitchState(GBT_S7_BMS_WAIT); 80017c4: 2008 movs r0, #8 80017c6: f000 f8c3 bl 8001950 } break; 80017ca: e0a9 b.n 8001920 80017cc: 200002b8 .word 0x200002b8 80017d0: 20000120 .word 0x20000120 80017d4: 2000011c .word 0x2000011c 80017d8: 20000134 .word 0x20000134 80017dc: 2000011d .word 0x2000011d 80017e0: 20000168 .word 0x20000168 80017e4: 2000011e .word 0x2000011e 80017e8: 2000019c .word 0x2000019c 80017ec: 20000178 .word 0x20000178 80017f0: cccccccd .word 0xcccccccd 80017f4: 200002a4 .word 0x200002a4 80017f8: 20000180 .word 0x20000180 80017fc: 2000018c .word 0x2000018c 8001800: 20000118 .word 0x20000118 8001804: 20000110 .word 0x20000110 case GBT_S7_BMS_WAIT: if(j_rx.state == 0) GBT_SendCTS(); 8001808: 4b4c ldr r3, [pc, #304] ; (800193c ) 800180a: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 800180e: 2b00 cmp r3, #0 8001810: d101 bne.n 8001816 8001812: f000 fe75 bl 8002500 HAL_Delay(2); 8001816: 2002 movs r0, #2 8001818: f002 fa2c bl 8003c74 if(j_rx.state == 0) GBT_SendCML(); 800181c: 4b47 ldr r3, [pc, #284] ; (800193c ) 800181e: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 8001822: 2b00 cmp r3, #0 8001824: d101 bne.n 800182a 8001826: f000 fe81 bl 800252c GBT_Delay(250); 800182a: 20fa movs r0, #250 ; 0xfa 800182c: f000 f92c bl 8001a88 if(EV_ready){ 8001830: 4b43 ldr r3, [pc, #268] ; (8001940 ) 8001832: 781b ldrb r3, [r3, #0] 8001834: 2b00 cmp r3, #0 8001836: d075 beq.n 8001924 //EV ready (AA) GBT_SwitchState(GBT_S8_INIT_CHARGER); 8001838: 2009 movs r0, #9 800183a: f000 f889 bl 8001950 } break; 800183e: e071 b.n 8001924 case GBT_S8_INIT_CHARGER: if(j_rx.state == 0) GBT_SendCRO(0x00); 8001840: 4b3e ldr r3, [pc, #248] ; (800193c ) 8001842: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 8001846: 2b00 cmp r3, #0 8001848: d102 bne.n 8001850 800184a: 2000 movs r0, #0 800184c: f000 fea6 bl 800259c //TODO GBT_Delay(250); 8001850: 20fa movs r0, #250 ; 0xfa 8001852: f000 f919 bl 8001a88 if(GBT_StateTick()>1500){ 8001856: f000 f90b bl 8001a70 800185a: 4603 mov r3, r0 800185c: f240 52dc movw r2, #1500 ; 0x5dc 8001860: 4293 cmp r3, r2 8001862: d961 bls.n 8001928 //Power Modules initiated GBT_SwitchState(GBT_S9_WAIT_BCL); 8001864: 200a movs r0, #10 8001866: f000 f873 bl 8001950 } break; 800186a: e05d b.n 8001928 case GBT_S9_WAIT_BCL: if(j_rx.state == 0) GBT_SendCRO(0xAA); 800186c: 4b33 ldr r3, [pc, #204] ; (800193c ) 800186e: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 8001872: 2b00 cmp r3, #0 8001874: d102 bne.n 800187c 8001876: 20aa movs r0, #170 ; 0xaa 8001878: f000 fe90 bl 800259c GBT_Delay(250); 800187c: 20fa movs r0, #250 ; 0xfa 800187e: f000 f903 bl 8001a88 if(GBT_ReqPower.chargingMode != 0){ 8001882: 4b30 ldr r3, [pc, #192] ; (8001944 ) 8001884: 791b ldrb r3, [r3, #4] 8001886: 2b00 cmp r3, #0 8001888: d050 beq.n 800192c //BCL power requirements received //write power modules GBT_SwitchState(GBT_S10_CHARGING); 800188a: 200b movs r0, #11 800188c: f000 f860 bl 8001950 uint16_t curr=(4000-GBT_ReqPower.requestedCurrent); 8001890: 4b2c ldr r3, [pc, #176] ; (8001944 ) 8001892: 885b ldrh r3, [r3, #2] 8001894: f5c3 637a rsb r3, r3, #4000 ; 0xfa0 8001898: 807b strh r3, [r7, #2] uint16_t volt=GBT_ReqPower.requestedVoltage/10; 800189a: 4b2a ldr r3, [pc, #168] ; (8001944 ) 800189c: 881b ldrh r3, [r3, #0] 800189e: 4a2a ldr r2, [pc, #168] ; (8001948 ) 80018a0: fba2 2303 umull r2, r3, r2, r3 80018a4: 08db lsrs r3, r3, #3 80018a6: 803b strh r3, [r7, #0] //if ((curr10>0) && (curr10<500)); //PSU_SetVoltage(volt); //PSU_SetCurrent(curr); GBT_EDCAN_Output.requestedVoltage = volt; 80018a8: 4b28 ldr r3, [pc, #160] ; (800194c ) 80018aa: 883a ldrh r2, [r7, #0] 80018ac: f8a3 2001 strh.w r2, [r3, #1] GBT_EDCAN_Output.requestedCurrent = curr; 80018b0: 4b26 ldr r3, [pc, #152] ; (800194c ) 80018b2: 887a ldrh r2, [r7, #2] 80018b4: f8a3 2003 strh.w r2, [r3, #3] GBT_EDCAN_Output.enablePSU = 1; 80018b8: 4b24 ldr r3, [pc, #144] ; (800194c ) 80018ba: 2201 movs r2, #1 80018bc: 701a strb r2, [r3, #0] //смещение -400а //RELAY_Write(RELAY_3, 1); //PSU_Mode(0x0200); } break; 80018be: e035 b.n 800192c case GBT_S10_CHARGING: //CHARGING if(j_rx.state == 0) GBT_SendCCS(); 80018c0: 4b1e ldr r3, [pc, #120] ; (800193c ) 80018c2: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 80018c6: 2b00 cmp r3, #0 80018c8: d101 bne.n 80018ce 80018ca: f000 fe7b bl 80025c4 // //PSU_SetVoltage(volt); // //смещение -400а // } //// } GBT_Delay(50); 80018ce: 2032 movs r0, #50 ; 0x32 80018d0: f000 f8da bl 8001a88 break; 80018d4: e02d b.n 8001932 case GBT_STOP: //TODO: turn off power modules GBT_Delay(10); 80018d6: 200a movs r0, #10 80018d8: f000 f8d6 bl 8001a88 GBT_EDCAN_Output.enablePSU = 0; 80018dc: 4b1b ldr r3, [pc, #108] ; (800194c ) 80018de: 2200 movs r2, #0 80018e0: 701a strb r2, [r3, #0] GBT_SendCST(); 80018e2: f000 fe7d bl 80025e0 //RELAY_Write(RELAY_OUTPUT, 0); //GBT_SwitchState(GBT_DISABLED); if(GBT_StateTick()>1000){ 80018e6: f000 f8c3 bl 8001a70 80018ea: 4603 mov r3, r0 80018ec: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 80018f0: d91e bls.n 8001930 GBT_SwitchState(GBT_DISABLED); 80018f2: 2000 movs r0, #0 80018f4: f000 f82c bl 8001950 GBT_Lock(0); 80018f8: 2000 movs r0, #0 80018fa: f7ff fb89 bl 8001010 RELAY_Write(RELAY_AUX, 0); 80018fe: 2100 movs r1, #0 8001900: 2000 movs r0, #0 8001902: f7ff fbbb bl 800107c //PSU_Mode(0x0100); } break; 8001906: e013 b.n 8001930 default: GBT_SwitchState(GBT_DISABLED); 8001908: 2000 movs r0, #0 800190a: f000 f821 bl 8001950 } } 800190e: e010 b.n 8001932 break; 8001910: bf00 nop 8001912: e00e b.n 8001932 break; 8001914: bf00 nop 8001916: e00c b.n 8001932 break; 8001918: bf00 nop 800191a: e00a b.n 8001932 break; 800191c: bf00 nop 800191e: e008 b.n 8001932 break; 8001920: bf00 nop 8001922: e006 b.n 8001932 break; 8001924: bf00 nop 8001926: e004 b.n 8001932 break; 8001928: bf00 nop 800192a: e002 b.n 8001932 break; 800192c: bf00 nop 800192e: e000 b.n 8001932 break; 8001930: bf00 nop } 8001932: bf00 nop 8001934: 3708 adds r7, #8 8001936: 46bd mov sp, r7 8001938: bdb0 pop {r4, r5, r7, pc} 800193a: bf00 nop 800193c: 200002b8 .word 0x200002b8 8001940: 2000011e .word 0x2000011e 8001944: 20000178 .word 0x20000178 8001948: cccccccd .word 0xcccccccd 800194c: 200002a4 .word 0x200002a4 08001950 : void GBT_SwitchState(gbtState_t state){ 8001950: b580 push {r7, lr} 8001952: b082 sub sp, #8 8001954: af00 add r7, sp, #0 8001956: 4603 mov r3, r0 8001958: 71fb strb r3, [r7, #7] GBT_State = state; 800195a: 4a35 ldr r2, [pc, #212] ; (8001a30 ) 800195c: 79fb ldrb r3, [r7, #7] 800195e: 7013 strb r3, [r2, #0] ED_status = state; 8001960: 4a34 ldr r2, [pc, #208] ; (8001a34 ) 8001962: 79fb ldrb r3, [r7, #7] 8001964: 7013 strb r3, [r2, #0] GBT_state_tick = HAL_GetTick(); 8001966: f002 f97b bl 8003c60 800196a: 4603 mov r3, r0 800196c: 4a32 ldr r2, [pc, #200] ; (8001a38 ) 800196e: 6013 str r3, [r2, #0] if(GBT_State == GBT_DISABLED) printf ("GBT_DISABLED\n"); 8001970: 4b2f ldr r3, [pc, #188] ; (8001a30 ) 8001972: 781b ldrb r3, [r3, #0] 8001974: 2b00 cmp r3, #0 8001976: d102 bne.n 800197e 8001978: 4830 ldr r0, [pc, #192] ; (8001a3c ) 800197a: f006 f8eb bl 8007b54 if(GBT_State == GBT_S0_UNCONNECTED) printf ("GBT_S0_UNCONNECTED\n"); 800197e: 4b2c ldr r3, [pc, #176] ; (8001a30 ) 8001980: 781b ldrb r3, [r3, #0] 8001982: 2b01 cmp r3, #1 8001984: d102 bne.n 800198c 8001986: 482e ldr r0, [pc, #184] ; (8001a40 ) 8001988: f006 f8e4 bl 8007b54 if(GBT_State == GBT_S1_CONNECTED) printf ("GBT_S1_CONNECTED\n"); 800198c: 4b28 ldr r3, [pc, #160] ; (8001a30 ) 800198e: 781b ldrb r3, [r3, #0] 8001990: 2b02 cmp r3, #2 8001992: d102 bne.n 800199a 8001994: 482b ldr r0, [pc, #172] ; (8001a44 ) 8001996: f006 f8dd bl 8007b54 if(GBT_State == GBT_S2_LOCKED) printf ("GBT_S2_LOCKED\n"); 800199a: 4b25 ldr r3, [pc, #148] ; (8001a30 ) 800199c: 781b ldrb r3, [r3, #0] 800199e: 2b03 cmp r3, #3 80019a0: d102 bne.n 80019a8 80019a2: 4829 ldr r0, [pc, #164] ; (8001a48 ) 80019a4: f006 f8d6 bl 8007b54 if(GBT_State == GBT_S3_STARTED) printf ("GBT_S3_STARTED\n"); 80019a8: 4b21 ldr r3, [pc, #132] ; (8001a30 ) 80019aa: 781b ldrb r3, [r3, #0] 80019ac: 2b04 cmp r3, #4 80019ae: d102 bne.n 80019b6 80019b0: 4826 ldr r0, [pc, #152] ; (8001a4c ) 80019b2: f006 f8cf bl 8007b54 if(GBT_State == GBT_S4_ISOTEST) printf ("GBT_S4_ISOTEST\n"); 80019b6: 4b1e ldr r3, [pc, #120] ; (8001a30 ) 80019b8: 781b ldrb r3, [r3, #0] 80019ba: 2b05 cmp r3, #5 80019bc: d102 bne.n 80019c4 80019be: 4824 ldr r0, [pc, #144] ; (8001a50 ) 80019c0: f006 f8c8 bl 8007b54 if(GBT_State == GBT_S5_BAT_INFO) printf ("GBT_S5_BAT_INFO\n"); 80019c4: 4b1a ldr r3, [pc, #104] ; (8001a30 ) 80019c6: 781b ldrb r3, [r3, #0] 80019c8: 2b06 cmp r3, #6 80019ca: d102 bne.n 80019d2 80019cc: 4821 ldr r0, [pc, #132] ; (8001a54 ) 80019ce: f006 f8c1 bl 8007b54 if(GBT_State == GBT_S6_BAT_STAT) printf ("GBT_S6_BAT_STAT\n"); 80019d2: 4b17 ldr r3, [pc, #92] ; (8001a30 ) 80019d4: 781b ldrb r3, [r3, #0] 80019d6: 2b07 cmp r3, #7 80019d8: d102 bne.n 80019e0 80019da: 481f ldr r0, [pc, #124] ; (8001a58 ) 80019dc: f006 f8ba bl 8007b54 if(GBT_State == GBT_S7_BMS_WAIT) printf ("GBT_S7_BMS_WAIT\n"); 80019e0: 4b13 ldr r3, [pc, #76] ; (8001a30 ) 80019e2: 781b ldrb r3, [r3, #0] 80019e4: 2b08 cmp r3, #8 80019e6: d102 bne.n 80019ee 80019e8: 481c ldr r0, [pc, #112] ; (8001a5c ) 80019ea: f006 f8b3 bl 8007b54 if(GBT_State == GBT_S8_INIT_CHARGER)printf ("GBT_S8_INIT_CHARGER\n"); 80019ee: 4b10 ldr r3, [pc, #64] ; (8001a30 ) 80019f0: 781b ldrb r3, [r3, #0] 80019f2: 2b09 cmp r3, #9 80019f4: d102 bne.n 80019fc 80019f6: 481a ldr r0, [pc, #104] ; (8001a60 ) 80019f8: f006 f8ac bl 8007b54 if(GBT_State == GBT_S9_WAIT_BCL) printf ("GBT_S9_WAIT_BCL\n"); 80019fc: 4b0c ldr r3, [pc, #48] ; (8001a30 ) 80019fe: 781b ldrb r3, [r3, #0] 8001a00: 2b0a cmp r3, #10 8001a02: d102 bne.n 8001a0a 8001a04: 4817 ldr r0, [pc, #92] ; (8001a64 ) 8001a06: f006 f8a5 bl 8007b54 if(GBT_State == GBT_S10_CHARGING) printf ("GBT_S10_CHARGING\n"); 8001a0a: 4b09 ldr r3, [pc, #36] ; (8001a30 ) 8001a0c: 781b ldrb r3, [r3, #0] 8001a0e: 2b0b cmp r3, #11 8001a10: d102 bne.n 8001a18 8001a12: 4815 ldr r0, [pc, #84] ; (8001a68 ) 8001a14: f006 f89e bl 8007b54 if(GBT_State == GBT_STOP) printf ("GBT_STOP\n"); 8001a18: 4b05 ldr r3, [pc, #20] ; (8001a30 ) 8001a1a: 781b ldrb r3, [r3, #0] 8001a1c: 2b0c cmp r3, #12 8001a1e: d102 bne.n 8001a26 8001a20: 4812 ldr r0, [pc, #72] ; (8001a6c ) 8001a22: f006 f897 bl 8007b54 } 8001a26: bf00 nop 8001a28: 3708 adds r7, #8 8001a2a: 46bd mov sp, r7 8001a2c: bd80 pop {r7, pc} 8001a2e: bf00 nop 8001a30: 20000110 .word 0x20000110 8001a34: 2000311a .word 0x2000311a 8001a38: 20000114 .word 0x20000114 8001a3c: 080089dc .word 0x080089dc 8001a40: 080089ec .word 0x080089ec 8001a44: 08008a00 .word 0x08008a00 8001a48: 08008a14 .word 0x08008a14 8001a4c: 08008a24 .word 0x08008a24 8001a50: 08008a34 .word 0x08008a34 8001a54: 08008a44 .word 0x08008a44 8001a58: 08008a54 .word 0x08008a54 8001a5c: 08008a64 .word 0x08008a64 8001a60: 08008a74 .word 0x08008a74 8001a64: 08008a88 .word 0x08008a88 8001a68: 08008a98 .word 0x08008a98 8001a6c: 08008aac .word 0x08008aac 08001a70 : uint32_t GBT_StateTick(){ 8001a70: b580 push {r7, lr} 8001a72: af00 add r7, sp, #0 return HAL_GetTick() - GBT_state_tick; 8001a74: f002 f8f4 bl 8003c60 8001a78: 4602 mov r2, r0 8001a7a: 4b02 ldr r3, [pc, #8] ; (8001a84 ) 8001a7c: 681b ldr r3, [r3, #0] 8001a7e: 1ad3 subs r3, r2, r3 } 8001a80: 4618 mov r0, r3 8001a82: bd80 pop {r7, pc} 8001a84: 20000114 .word 0x20000114 08001a88 : void GBT_Delay(uint32_t delay){ 8001a88: b580 push {r7, lr} 8001a8a: b082 sub sp, #8 8001a8c: af00 add r7, sp, #0 8001a8e: 6078 str r0, [r7, #4] GBT_delay = HAL_GetTick()+delay; 8001a90: f002 f8e6 bl 8003c60 8001a94: 4602 mov r2, r0 8001a96: 687b ldr r3, [r7, #4] 8001a98: 4413 add r3, r2 8001a9a: 4a03 ldr r2, [pc, #12] ; (8001aa8 ) 8001a9c: 6013 str r3, [r2, #0] } 8001a9e: bf00 nop 8001aa0: 3708 adds r7, #8 8001aa2: 46bd mov sp, r7 8001aa4: bd80 pop {r7, pc} 8001aa6: bf00 nop 8001aa8: 20000118 .word 0x20000118 08001aac : void GBT_Stop(){ 8001aac: b580 push {r7, lr} 8001aae: af00 add r7, sp, #0 if(GBT_State != GBT_STOP) GBT_SwitchState(GBT_STOP); 8001ab0: 4b04 ldr r3, [pc, #16] ; (8001ac4 ) 8001ab2: 781b ldrb r3, [r3, #0] 8001ab4: 2b0c cmp r3, #12 8001ab6: d002 beq.n 8001abe 8001ab8: 200c movs r0, #12 8001aba: f7ff ff49 bl 8001950 } 8001abe: bf00 nop 8001ac0: bd80 pop {r7, pc} 8001ac2: bf00 nop 8001ac4: 20000110 .word 0x20000110 08001ac8 : void GBT_Stop1(){ 8001ac8: b580 push {r7, lr} 8001aca: af00 add r7, sp, #0 GBT_SwitchState(GBT_DISABLED); 8001acc: 2000 movs r0, #0 8001ace: f7ff ff3f bl 8001950 GBT_Lock(0); 8001ad2: 2000 movs r0, #0 8001ad4: f7ff fa9c bl 8001010 RELAY_Write(RELAY_AUX, 0); 8001ad8: 2100 movs r1, #0 8001ada: 2000 movs r0, #0 8001adc: f7ff face bl 800107c } 8001ae0: bf00 nop 8001ae2: bd80 pop {r7, pc} 08001ae4 : void GBT_Start(){ 8001ae4: b580 push {r7, lr} 8001ae6: af00 add r7, sp, #0 GBT_BAT_INFO_recv = 0; 8001ae8: 4b0e ldr r3, [pc, #56] ; (8001b24 ) 8001aea: 2200 movs r2, #0 8001aec: 701a strb r2, [r3, #0] GBT_BAT_STAT_recv = 0; 8001aee: 4b0e ldr r3, [pc, #56] ; (8001b28 ) 8001af0: 2200 movs r2, #0 8001af2: 701a strb r2, [r3, #0] EV_ready = 0; 8001af4: 4b0d ldr r3, [pc, #52] ; (8001b2c ) 8001af6: 2200 movs r2, #0 8001af8: 701a strb r2, [r3, #0] memset(&GBT_EVInfo, 0, sizeof (GBT_EVInfo)); 8001afa: 2231 movs r2, #49 ; 0x31 8001afc: 2100 movs r1, #0 8001afe: 480c ldr r0, [pc, #48] ; (8001b30 ) 8001b00: f005 febe bl 8007880 memset(&GBT_BATStat, 0, sizeof (GBT_BATStat)); 8001b04: 220d movs r2, #13 8001b06: 2100 movs r1, #0 8001b08: 480a ldr r0, [pc, #40] ; (8001b34 ) 8001b0a: f005 feb9 bl 8007880 memset(&GBT_ReqPower, 0, sizeof (GBT_ReqPower)); 8001b0e: 2205 movs r2, #5 8001b10: 2100 movs r1, #0 8001b12: 4809 ldr r0, [pc, #36] ; (8001b38 ) 8001b14: f005 feb4 bl 8007880 GBT_SwitchState(GBT_S0_UNCONNECTED); 8001b18: 2001 movs r0, #1 8001b1a: f7ff ff19 bl 8001950 } 8001b1e: bf00 nop 8001b20: bd80 pop {r7, pc} 8001b22: bf00 nop 8001b24: 2000011c .word 0x2000011c 8001b28: 2000011d .word 0x2000011d 8001b2c: 2000011e .word 0x2000011e 8001b30: 20000134 .word 0x20000134 8001b34: 20000168 .word 0x20000168 8001b38: 20000178 .word 0x20000178 08001b3c <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 8001b3c: b480 push {r7} 8001b3e: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 8001b40: f3bf 8f4f dsb sy } 8001b44: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 8001b46: 4b06 ldr r3, [pc, #24] ; (8001b60 <__NVIC_SystemReset+0x24>) 8001b48: 68db ldr r3, [r3, #12] 8001b4a: f403 62e0 and.w r2, r3, #1792 ; 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001b4e: 4904 ldr r1, [pc, #16] ; (8001b60 <__NVIC_SystemReset+0x24>) 8001b50: 4b04 ldr r3, [pc, #16] ; (8001b64 <__NVIC_SystemReset+0x28>) 8001b52: 4313 orrs r3, r2 8001b54: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 8001b56: f3bf 8f4f dsb sy } 8001b5a: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 8001b5c: bf00 nop 8001b5e: e7fd b.n 8001b5c <__NVIC_SystemReset+0x20> 8001b60: e000ed00 .word 0xe000ed00 8001b64: 05fa0004 .word 0x05fa0004 08001b68 <_write>: extern UART_HandleTypeDef huart2; #if defined(__GNUC__) int _write(int fd, char * ptr, int len) { 8001b68: b580 push {r7, lr} 8001b6a: b084 sub sp, #16 8001b6c: af00 add r7, sp, #0 8001b6e: 60f8 str r0, [r7, #12] 8001b70: 60b9 str r1, [r7, #8] 8001b72: 607a str r2, [r7, #4] HAL_UART_Transmit(&huart2, (uint8_t *) ptr, len, HAL_MAX_DELAY); 8001b74: 687b ldr r3, [r7, #4] 8001b76: b29a uxth r2, r3 8001b78: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff 8001b7c: 68b9 ldr r1, [r7, #8] 8001b7e: 4804 ldr r0, [pc, #16] ; (8001b90 <_write+0x28>) 8001b80: f005 f85f bl 8006c42 return len; 8001b84: 687b ldr r3, [r7, #4] } 8001b86: 4618 mov r0, r3 8001b88: 3710 adds r7, #16 8001b8a: 46bd mov sp, r7 8001b8c: bd80 pop {r7, pc} 8001b8e: bf00 nop 8001b90: 20003130 .word 0x20003130 08001b94 : debug_rx_buffer[Size] = '\0'; debug_rx_buffer_size = Size; debug_cmd_received = 1; } void debug_init(){ 8001b94: b580 push {r7, lr} 8001b96: af00 add r7, sp, #0 HAL_UARTEx_ReceiveToIdle_IT(&huart2,debug_rx_buffer,255); 8001b98: 22ff movs r2, #255 ; 0xff 8001b9a: 4903 ldr r1, [pc, #12] ; (8001ba8 ) 8001b9c: 4803 ldr r0, [pc, #12] ; (8001bac ) 8001b9e: f005 f8e2 bl 8006d66 // mm_schedule_write(0x02, 0x00FF, 0xFFFF); //for (int i=0;i<60;i++) // mm_schedule_write(0x02, 0x0000, 0xFF00); // mm_schedule_write(0x01, 0x0000, 0x0100); // mm_schedule_write(0x01, 0x0000, 0x0100); } 8001ba2: bf00 nop 8001ba4: bd80 pop {r7, pc} 8001ba6: bf00 nop 8001ba8: 200001a0 .word 0x200001a0 8001bac: 20003130 .word 0x20003130 08001bb0 : void parse_command(uint8_t* buffer, size_t length) { 8001bb0: b580 push {r7, lr} 8001bb2: b084 sub sp, #16 8001bb4: af00 add r7, sp, #0 8001bb6: 6078 str r0, [r7, #4] 8001bb8: 6039 str r1, [r7, #0] // ignore \r \n symbols size_t i = 0; 8001bba: 2300 movs r3, #0 8001bbc: 60fb str r3, [r7, #12] for (i = 0; i < length; i++) { 8001bbe: 2300 movs r3, #0 8001bc0: 60fb str r3, [r7, #12] 8001bc2: e016 b.n 8001bf2 if (buffer[i] == '\r' || buffer[i] == '\n') { 8001bc4: 687a ldr r2, [r7, #4] 8001bc6: 68fb ldr r3, [r7, #12] 8001bc8: 4413 add r3, r2 8001bca: 781b ldrb r3, [r3, #0] 8001bcc: 2b0d cmp r3, #13 8001bce: d005 beq.n 8001bdc 8001bd0: 687a ldr r2, [r7, #4] 8001bd2: 68fb ldr r3, [r7, #12] 8001bd4: 4413 add r3, r2 8001bd6: 781b ldrb r3, [r3, #0] 8001bd8: 2b0a cmp r3, #10 8001bda: d107 bne.n 8001bec buffer[i] = '\0'; 8001bdc: 687a ldr r2, [r7, #4] 8001bde: 68fb ldr r3, [r7, #12] 8001be0: 4413 add r3, r2 8001be2: 2200 movs r2, #0 8001be4: 701a strb r2, [r3, #0] length = i; 8001be6: 68fb ldr r3, [r7, #12] 8001be8: 603b str r3, [r7, #0] break; 8001bea: e006 b.n 8001bfa for (i = 0; i < length; i++) { 8001bec: 68fb ldr r3, [r7, #12] 8001bee: 3301 adds r3, #1 8001bf0: 60fb str r3, [r7, #12] 8001bf2: 68fa ldr r2, [r7, #12] 8001bf4: 683b ldr r3, [r7, #0] 8001bf6: 429a cmp r2, r3 8001bf8: d3e4 bcc.n 8001bc4 } } if (strncmp((const char*)buffer, "reset", length) == 0) { 8001bfa: 683a ldr r2, [r7, #0] 8001bfc: 49a4 ldr r1, [pc, #656] ; (8001e90 ) 8001bfe: 6878 ldr r0, [r7, #4] 8001c00: f005 ffc0 bl 8007b84 8001c04: 4603 mov r3, r0 8001c06: 2b00 cmp r3, #0 8001c08: d104 bne.n 8001c14 printf("Resetting...\n"); 8001c0a: 48a2 ldr r0, [pc, #648] ; (8001e94 ) 8001c0c: f005 ffa2 bl 8007b54 NVIC_SystemReset(); 8001c10: f7ff ff94 bl 8001b3c <__NVIC_SystemReset> } else if (strncmp((const char*)buffer, "relayaux", length) == 0) { 8001c14: 683a ldr r2, [r7, #0] 8001c16: 49a0 ldr r1, [pc, #640] ; (8001e98 ) 8001c18: 6878 ldr r0, [r7, #4] 8001c1a: f005 ffb3 bl 8007b84 8001c1e: 4603 mov r3, r0 8001c20: 2b00 cmp r3, #0 8001c22: d10e bne.n 8001c42 printf("Relaying...\n"); 8001c24: 489d ldr r0, [pc, #628] ; (8001e9c ) 8001c26: f005 ff95 bl 8007b54 RELAY_Write(RELAY_AUX, 1); 8001c2a: 2101 movs r1, #1 8001c2c: 2000 movs r0, #0 8001c2e: f7ff fa25 bl 800107c HAL_Delay(200); 8001c32: 20c8 movs r0, #200 ; 0xc8 8001c34: f002 f81e bl 8003c74 RELAY_Write(RELAY_AUX, 0); 8001c38: 2100 movs r1, #0 8001c3a: 2000 movs r0, #0 8001c3c: f7ff fa1e bl 800107c //TODO: info commands } else { printf("Unknown command\n"); } } 8001c40: e204 b.n 800204c } else if (strncmp((const char*)buffer, "relaycc", length) == 0) { 8001c42: 683a ldr r2, [r7, #0] 8001c44: 4996 ldr r1, [pc, #600] ; (8001ea0 ) 8001c46: 6878 ldr r0, [r7, #4] 8001c48: f005 ff9c bl 8007b84 8001c4c: 4603 mov r3, r0 8001c4e: 2b00 cmp r3, #0 8001c50: d10e bne.n 8001c70 printf("Relaying...\n"); 8001c52: 4892 ldr r0, [pc, #584] ; (8001e9c ) 8001c54: f005 ff7e bl 8007b54 RELAY_Write(RELAY_CC, 1); 8001c58: 2101 movs r1, #1 8001c5a: 2001 movs r0, #1 8001c5c: f7ff fa0e bl 800107c HAL_Delay(200); 8001c60: 20c8 movs r0, #200 ; 0xc8 8001c62: f002 f807 bl 8003c74 RELAY_Write(RELAY_CC, 0); 8001c66: 2100 movs r1, #0 8001c68: 2001 movs r0, #1 8001c6a: f7ff fa07 bl 800107c } 8001c6e: e1ed b.n 800204c } else if (strncmp((const char*)buffer, "adc", length) == 0) { 8001c70: 683a ldr r2, [r7, #0] 8001c72: 498c ldr r1, [pc, #560] ; (8001ea4 ) 8001c74: 6878 ldr r0, [r7, #4] 8001c76: f005 ff85 bl 8007b84 8001c7a: 4603 mov r3, r0 8001c7c: 2b00 cmp r3, #0 8001c7e: d10b bne.n 8001c98 printf("CC1=%.2f\n", GBT_CC_GetAdc()); 8001c80: f7ff fc1c bl 80014bc 8001c84: 4603 mov r3, r0 8001c86: 4618 mov r0, r3 8001c88: f7fe fc30 bl 80004ec <__aeabi_f2d> 8001c8c: 4602 mov r2, r0 8001c8e: 460b mov r3, r1 8001c90: 4885 ldr r0, [pc, #532] ; (8001ea8 ) 8001c92: f005 fed9 bl 8007a48 } 8001c96: e1d9 b.n 800204c } else if (strncmp((const char*)buffer, "lock_state", length) == 0) { 8001c98: 683a ldr r2, [r7, #0] 8001c9a: 4984 ldr r1, [pc, #528] ; (8001eac ) 8001c9c: 6878 ldr r0, [r7, #4] 8001c9e: f005 ff71 bl 8007b84 8001ca2: 4603 mov r3, r0 8001ca4: 2b00 cmp r3, #0 8001ca6: d107 bne.n 8001cb8 printf("Lock state=%d\n", GBT_LockGetState()); 8001ca8: f7ff f9dc bl 8001064 8001cac: 4603 mov r3, r0 8001cae: 4619 mov r1, r3 8001cb0: 487f ldr r0, [pc, #508] ; (8001eb0 ) 8001cb2: f005 fec9 bl 8007a48 } 8001cb6: e1c9 b.n 800204c } else if (strncmp((const char*)buffer, "lock_lock", length) == 0) { 8001cb8: 683a ldr r2, [r7, #0] 8001cba: 497e ldr r1, [pc, #504] ; (8001eb4 ) 8001cbc: 6878 ldr r0, [r7, #4] 8001cbe: f005 ff61 bl 8007b84 8001cc2: 4603 mov r3, r0 8001cc4: 2b00 cmp r3, #0 8001cc6: d106 bne.n 8001cd6 printf("Locked\n"); 8001cc8: 487b ldr r0, [pc, #492] ; (8001eb8 ) 8001cca: f005 ff43 bl 8007b54 GBT_Lock(1); 8001cce: 2001 movs r0, #1 8001cd0: f7ff f99e bl 8001010 } 8001cd4: e1ba b.n 800204c } else if (strncmp((const char*)buffer, "lock_unlock", length) == 0) { 8001cd6: 683a ldr r2, [r7, #0] 8001cd8: 4978 ldr r1, [pc, #480] ; (8001ebc ) 8001cda: 6878 ldr r0, [r7, #4] 8001cdc: f005 ff52 bl 8007b84 8001ce0: 4603 mov r3, r0 8001ce2: 2b00 cmp r3, #0 8001ce4: d106 bne.n 8001cf4 printf("Unlocked\n"); 8001ce6: 4876 ldr r0, [pc, #472] ; (8001ec0 ) 8001ce8: f005 ff34 bl 8007b54 GBT_Lock(0); 8001cec: 2000 movs r0, #0 8001cee: f7ff f98f bl 8001010 } 8001cf2: e1ab b.n 800204c } else if (strncmp((const char*)buffer, "start", length) == 0) { 8001cf4: 683a ldr r2, [r7, #0] 8001cf6: 4973 ldr r1, [pc, #460] ; (8001ec4 ) 8001cf8: 6878 ldr r0, [r7, #4] 8001cfa: f005 ff43 bl 8007b84 8001cfe: 4603 mov r3, r0 8001d00: 2b00 cmp r3, #0 8001d02: d105 bne.n 8001d10 printf("Started\n"); 8001d04: 4870 ldr r0, [pc, #448] ; (8001ec8 ) 8001d06: f005 ff25 bl 8007b54 GBT_Start(); 8001d0a: f7ff feeb bl 8001ae4 } 8001d0e: e19d b.n 800204c } else if (strncmp((const char*)buffer, "stop", length) == 0) { 8001d10: 683a ldr r2, [r7, #0] 8001d12: 496e ldr r1, [pc, #440] ; (8001ecc ) 8001d14: 6878 ldr r0, [r7, #4] 8001d16: f005 ff35 bl 8007b84 8001d1a: 4603 mov r3, r0 8001d1c: 2b00 cmp r3, #0 8001d1e: d105 bne.n 8001d2c printf("Stopped\n"); 8001d20: 486b ldr r0, [pc, #428] ; (8001ed0 ) 8001d22: f005 ff17 bl 8007b54 GBT_Stop(); 8001d26: f7ff fec1 bl 8001aac } 8001d2a: e18f b.n 800204c } else if (strncmp((const char*)buffer, "stop1", length) == 0) { 8001d2c: 683a ldr r2, [r7, #0] 8001d2e: 4969 ldr r1, [pc, #420] ; (8001ed4 ) 8001d30: 6878 ldr r0, [r7, #4] 8001d32: f005 ff27 bl 8007b84 8001d36: 4603 mov r3, r0 8001d38: 2b00 cmp r3, #0 8001d3a: d105 bne.n 8001d48 printf("Stopped\n"); 8001d3c: 4864 ldr r0, [pc, #400] ; (8001ed0 ) 8001d3e: f005 ff09 bl 8007b54 GBT_Stop1(); 8001d42: f7ff fec1 bl 8001ac8 } 8001d46: e181 b.n 800204c } else if (strncmp((const char*)buffer, "force", length) == 0) { 8001d48: 683a ldr r2, [r7, #0] 8001d4a: 4963 ldr r1, [pc, #396] ; (8001ed8 ) 8001d4c: 6878 ldr r0, [r7, #4] 8001d4e: f005 ff19 bl 8007b84 8001d52: 4603 mov r3, r0 8001d54: 2b00 cmp r3, #0 8001d56: d10d bne.n 8001d74 printf("Stopped\n"); 8001d58: 485d ldr r0, [pc, #372] ; (8001ed0 ) 8001d5a: f005 fefb bl 8007b54 GBT_Lock(1); 8001d5e: 2001 movs r0, #1 8001d60: f7ff f956 bl 8001010 GBT_SwitchState(GBT_S2_LOCKED); 8001d64: 2003 movs r0, #3 8001d66: f7ff fdf3 bl 8001950 GBT_Delay(500); 8001d6a: f44f 70fa mov.w r0, #500 ; 0x1f4 8001d6e: f7ff fe8b bl 8001a88 } 8001d72: e16b b.n 800204c } else if (strncmp((const char*)buffer, "cc_state", length) == 0) { 8001d74: 683a ldr r2, [r7, #0] 8001d76: 4959 ldr r1, [pc, #356] ; (8001edc ) 8001d78: 6878 ldr r0, [r7, #4] 8001d7a: f005 ff03 bl 8007b84 8001d7e: 4603 mov r3, r0 8001d80: 2b00 cmp r3, #0 8001d82: d127 bne.n 8001dd4 switch(GBT_CC_GetState()){ 8001d84: f7ff fb22 bl 80013cc 8001d88: 4603 mov r3, r0 8001d8a: 2b04 cmp r3, #4 8001d8c: f200 815e bhi.w 800204c 8001d90: a201 add r2, pc, #4 ; (adr r2, 8001d98 ) 8001d92: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8001d96: bf00 nop 8001d98: 08001dad .word 0x08001dad 8001d9c: 08001db5 .word 0x08001db5 8001da0: 08001dbd .word 0x08001dbd 8001da4: 08001dc5 .word 0x08001dc5 8001da8: 08001dcd .word 0x08001dcd printf("GBT_CC_UNKNOWN\n"); 8001dac: 484c ldr r0, [pc, #304] ; (8001ee0 ) 8001dae: f005 fed1 bl 8007b54 break; 8001db2: e14b b.n 800204c printf("GBT_CC_12V\n"); 8001db4: 484b ldr r0, [pc, #300] ; (8001ee4 ) 8001db6: f005 fecd bl 8007b54 break; 8001dba: e147 b.n 800204c printf("GBT_CC_6V\n"); 8001dbc: 484a ldr r0, [pc, #296] ; (8001ee8 ) 8001dbe: f005 fec9 bl 8007b54 break; 8001dc2: e143 b.n 800204c printf("GBT_CC_4V\n"); 8001dc4: 4849 ldr r0, [pc, #292] ; (8001eec ) 8001dc6: f005 fec5 bl 8007b54 break; 8001dca: e13f b.n 800204c printf("GBT_CC_2V\n"); 8001dcc: 4848 ldr r0, [pc, #288] ; (8001ef0 ) 8001dce: f005 fec1 bl 8007b54 break; 8001dd2: e13b b.n 800204c } else if (strncmp((const char*)buffer, "info1", length) == 0) { 8001dd4: 683a ldr r2, [r7, #0] 8001dd6: 4947 ldr r1, [pc, #284] ; (8001ef4 ) 8001dd8: 6878 ldr r0, [r7, #4] 8001dda: f005 fed3 bl 8007b84 8001dde: 4603 mov r3, r0 8001de0: 2b00 cmp r3, #0 8001de2: f040 809d bne.w 8001f20 printf("Battery info:\n"); 8001de6: 4844 ldr r0, [pc, #272] ; (8001ef8 ) 8001de8: f005 feb4 bl 8007b54 printf("maxCV %dV\n",GBT_BATStat.maxCellVoltage/100); // 0.01v/bit 8001dec: 4b43 ldr r3, [pc, #268] ; (8001efc ) 8001dee: 881b ldrh r3, [r3, #0] 8001df0: b29b uxth r3, r3 8001df2: 4a43 ldr r2, [pc, #268] ; (8001f00 ) 8001df4: fba2 2303 umull r2, r3, r2, r3 8001df8: 095b lsrs r3, r3, #5 8001dfa: b29b uxth r3, r3 8001dfc: 4619 mov r1, r3 8001dfe: 4841 ldr r0, [pc, #260] ; (8001f04 ) 8001e00: f005 fe22 bl 8007a48 printf("maxCC %dA\n",GBT_BATStat.maxChargingCurrent/10); // 0.1A/bit 8001e04: 4b3d ldr r3, [pc, #244] ; (8001efc ) 8001e06: 885b ldrh r3, [r3, #2] 8001e08: b29b uxth r3, r3 8001e0a: 4a3f ldr r2, [pc, #252] ; (8001f08 ) 8001e0c: fba2 2303 umull r2, r3, r2, r3 8001e10: 08db lsrs r3, r3, #3 8001e12: b29b uxth r3, r3 8001e14: 4619 mov r1, r3 8001e16: 483d ldr r0, [pc, #244] ; (8001f0c ) 8001e18: f005 fe16 bl 8007a48 printf("totE %dkWh\n",GBT_BATStat.totalEnergy/10); // 0.1kWh 8001e1c: 4b37 ldr r3, [pc, #220] ; (8001efc ) 8001e1e: 889b ldrh r3, [r3, #4] 8001e20: b29b uxth r3, r3 8001e22: 4a39 ldr r2, [pc, #228] ; (8001f08 ) 8001e24: fba2 2303 umull r2, r3, r2, r3 8001e28: 08db lsrs r3, r3, #3 8001e2a: b29b uxth r3, r3 8001e2c: 4619 mov r1, r3 8001e2e: 4838 ldr r0, [pc, #224] ; (8001f10 ) 8001e30: f005 fe0a bl 8007a48 printf("maxCV %dV\n",GBT_BATStat.maxChargingVoltage/10); // 0.1V/ bit 8001e34: 4b31 ldr r3, [pc, #196] ; (8001efc ) 8001e36: 88db ldrh r3, [r3, #6] 8001e38: b29b uxth r3, r3 8001e3a: 4a33 ldr r2, [pc, #204] ; (8001f08 ) 8001e3c: fba2 2303 umull r2, r3, r2, r3 8001e40: 08db lsrs r3, r3, #3 8001e42: b29b uxth r3, r3 8001e44: 4619 mov r1, r3 8001e46: 482f ldr r0, [pc, #188] ; (8001f04 ) 8001e48: f005 fdfe bl 8007a48 printf("maxT %dC\n",(int16_t)GBT_BATStat.maxTemp-50); // 1C/bit, -50C offset 8001e4c: 4b2b ldr r3, [pc, #172] ; (8001efc ) 8001e4e: 7a1b ldrb r3, [r3, #8] 8001e50: 3b32 subs r3, #50 ; 0x32 8001e52: 4619 mov r1, r3 8001e54: 482f ldr r0, [pc, #188] ; (8001f14 ) 8001e56: f005 fdf7 bl 8007a48 printf("SOC %dp\n",GBT_BATStat.SOC/10); // 0.1%/bit , 0..100% 8001e5a: 4b28 ldr r3, [pc, #160] ; (8001efc ) 8001e5c: f8b3 3009 ldrh.w r3, [r3, #9] 8001e60: b29b uxth r3, r3 8001e62: 4a29 ldr r2, [pc, #164] ; (8001f08 ) 8001e64: fba2 2303 umull r2, r3, r2, r3 8001e68: 08db lsrs r3, r3, #3 8001e6a: b29b uxth r3, r3 8001e6c: 4619 mov r1, r3 8001e6e: 482a ldr r0, [pc, #168] ; (8001f18 ) 8001e70: f005 fdea bl 8007a48 printf("Volt. %dV\n",GBT_BATStat.measVoltage/10); // 0.1V/bit 8001e74: 4b21 ldr r3, [pc, #132] ; (8001efc ) 8001e76: f8b3 300b ldrh.w r3, [r3, #11] 8001e7a: b29b uxth r3, r3 8001e7c: 4a22 ldr r2, [pc, #136] ; (8001f08 ) 8001e7e: fba2 2303 umull r2, r3, r2, r3 8001e82: 08db lsrs r3, r3, #3 8001e84: b29b uxth r3, r3 8001e86: 4619 mov r1, r3 8001e88: 4824 ldr r0, [pc, #144] ; (8001f1c ) 8001e8a: f005 fddd bl 8007a48 } 8001e8e: e0dd b.n 800204c 8001e90: 08008ab8 .word 0x08008ab8 8001e94: 08008ac0 .word 0x08008ac0 8001e98: 08008ad0 .word 0x08008ad0 8001e9c: 08008adc .word 0x08008adc 8001ea0: 08008ae8 .word 0x08008ae8 8001ea4: 08008af0 .word 0x08008af0 8001ea8: 08008af4 .word 0x08008af4 8001eac: 08008b00 .word 0x08008b00 8001eb0: 08008b0c .word 0x08008b0c 8001eb4: 08008b1c .word 0x08008b1c 8001eb8: 08008b28 .word 0x08008b28 8001ebc: 08008b30 .word 0x08008b30 8001ec0: 08008b3c .word 0x08008b3c 8001ec4: 08008b48 .word 0x08008b48 8001ec8: 08008b50 .word 0x08008b50 8001ecc: 08008b58 .word 0x08008b58 8001ed0: 08008b60 .word 0x08008b60 8001ed4: 08008b68 .word 0x08008b68 8001ed8: 08008b70 .word 0x08008b70 8001edc: 08008b78 .word 0x08008b78 8001ee0: 08008b84 .word 0x08008b84 8001ee4: 08008b94 .word 0x08008b94 8001ee8: 08008ba0 .word 0x08008ba0 8001eec: 08008bac .word 0x08008bac 8001ef0: 08008bb8 .word 0x08008bb8 8001ef4: 08008bc4 .word 0x08008bc4 8001ef8: 08008bcc .word 0x08008bcc 8001efc: 20000168 .word 0x20000168 8001f00: 51eb851f .word 0x51eb851f 8001f04: 08008bdc .word 0x08008bdc 8001f08: cccccccd .word 0xcccccccd 8001f0c: 08008be8 .word 0x08008be8 8001f10: 08008bf4 .word 0x08008bf4 8001f14: 08008c00 .word 0x08008c00 8001f18: 08008c0c .word 0x08008c0c 8001f1c: 08008c18 .word 0x08008c18 } else if (strncmp((const char*)buffer, "info2", length) == 0) { 8001f20: 683a ldr r2, [r7, #0] 8001f22: 494c ldr r1, [pc, #304] ; (8002054 ) 8001f24: 6878 ldr r0, [r7, #4] 8001f26: f005 fe2d bl 8007b84 8001f2a: 4603 mov r3, r0 8001f2c: 2b00 cmp r3, #0 8001f2e: d153 bne.n 8001fd8 printf("EV info:\n"); 8001f30: 4849 ldr r0, [pc, #292] ; (8002058 ) 8001f32: f005 fe0f bl 8007b54 printf("GBT_ver V%d.%d%d\n",GBT_EVInfo.version[0],GBT_EVInfo.version[1],GBT_EVInfo.version[2]); 8001f36: 4b49 ldr r3, [pc, #292] ; (800205c ) 8001f38: 781b ldrb r3, [r3, #0] 8001f3a: 4619 mov r1, r3 8001f3c: 4b47 ldr r3, [pc, #284] ; (800205c ) 8001f3e: 785b ldrb r3, [r3, #1] 8001f40: 461a mov r2, r3 8001f42: 4b46 ldr r3, [pc, #280] ; (800205c ) 8001f44: 789b ldrb r3, [r3, #2] 8001f46: 4846 ldr r0, [pc, #280] ; (8002060 ) 8001f48: f005 fd7e bl 8007a48 printf("Battery type: %d\n",GBT_EVInfo.batteryType); 8001f4c: 4b43 ldr r3, [pc, #268] ; (800205c ) 8001f4e: 78db ldrb r3, [r3, #3] 8001f50: 4619 mov r1, r3 8001f52: 4844 ldr r0, [pc, #272] ; (8002064 ) 8001f54: f005 fd78 bl 8007a48 printf("Battery capacity: %d\n", GBT_EVInfo.batteryCapacity); // 0.1Ah/bit 8001f58: 4b40 ldr r3, [pc, #256] ; (800205c ) 8001f5a: 889b ldrh r3, [r3, #4] 8001f5c: b29b uxth r3, r3 8001f5e: 4619 mov r1, r3 8001f60: 4841 ldr r0, [pc, #260] ; (8002068 ) 8001f62: f005 fd71 bl 8007a48 printf("Battery voltage: %d\n", GBT_EVInfo.batteryVoltage); // 0.1V/bit 8001f66: 4b3d ldr r3, [pc, #244] ; (800205c ) 8001f68: 88db ldrh r3, [r3, #6] 8001f6a: b29b uxth r3, r3 8001f6c: 4619 mov r1, r3 8001f6e: 483f ldr r0, [pc, #252] ; (800206c ) 8001f70: f005 fd6a bl 8007a48 printf("Battery vendor: %.4s\n", GBT_EVInfo.batteryVendor); // Battery vendor (ASCII string) 8001f74: 493e ldr r1, [pc, #248] ; (8002070 ) 8001f76: 483f ldr r0, [pc, #252] ; (8002074 ) 8001f78: f005 fd66 bl 8007a48 printf("Battery SN: %lu\n", GBT_EVInfo.batterySN); // int 8001f7c: 4b37 ldr r3, [pc, #220] ; (800205c ) 8001f7e: 68db ldr r3, [r3, #12] 8001f80: 4619 mov r1, r3 8001f82: 483d ldr r0, [pc, #244] ; (8002078 ) 8001f84: f005 fd60 bl 8007a48 printf("Battery manufacture date: %02d.%02d.%04d\n", GBT_EVInfo.batteryManuD, GBT_EVInfo.batteryManuM ,GBT_EVInfo.batteryManuY+1985); // year (offset 1985) 8001f88: 4b34 ldr r3, [pc, #208] ; (800205c ) 8001f8a: 7c9b ldrb r3, [r3, #18] 8001f8c: 4619 mov r1, r3 8001f8e: 4b33 ldr r3, [pc, #204] ; (800205c ) 8001f90: 7c5b ldrb r3, [r3, #17] 8001f92: 461a mov r2, r3 8001f94: 4b31 ldr r3, [pc, #196] ; (800205c ) 8001f96: 7c1b ldrb r3, [r3, #16] 8001f98: f203 73c1 addw r3, r3, #1985 ; 0x7c1 8001f9c: 4837 ldr r0, [pc, #220] ; (800207c ) 8001f9e: f005 fd53 bl 8007a48 printf("Battery cycles: %d\n", GBT_EVInfo.batteryCycleCount); //uint24_t 8001fa2: 4b2e ldr r3, [pc, #184] ; (800205c ) 8001fa4: 7cda ldrb r2, [r3, #19] 8001fa6: 7d19 ldrb r1, [r3, #20] 8001fa8: 0209 lsls r1, r1, #8 8001faa: 430a orrs r2, r1 8001fac: 7d5b ldrb r3, [r3, #21] 8001fae: 041b lsls r3, r3, #16 8001fb0: 4313 orrs r3, r2 8001fb2: 4619 mov r1, r3 8001fb4: 4832 ldr r0, [pc, #200] ; (8002080 ) 8001fb6: f005 fd47 bl 8007a48 printf("Own auto: %d\n", GBT_EVInfo.ownAuto); // 0 = lizing, 1 = own auto 8001fba: 4b28 ldr r3, [pc, #160] ; (800205c ) 8001fbc: 7d9b ldrb r3, [r3, #22] 8001fbe: 4619 mov r1, r3 8001fc0: 4830 ldr r0, [pc, #192] ; (8002084 ) 8001fc2: f005 fd41 bl 8007a48 printf("EVIN: %.17s\n", GBT_EVInfo.EVIN); //EVIN 8001fc6: 4930 ldr r1, [pc, #192] ; (8002088 ) 8001fc8: 4830 ldr r0, [pc, #192] ; (800208c ) 8001fca: f005 fd3d bl 8007a48 printf("EV_SW_VER: %.8s\n", GBT_EVInfo.EV_SW_VER); 8001fce: 4930 ldr r1, [pc, #192] ; (8002090 ) 8001fd0: 4830 ldr r0, [pc, #192] ; (8002094 ) 8001fd2: f005 fd39 bl 8007a48 } 8001fd6: e039 b.n 800204c } else if (strncmp((const char*)buffer, "help", length) == 0) { 8001fd8: 683a ldr r2, [r7, #0] 8001fda: 492f ldr r1, [pc, #188] ; (8002098 ) 8001fdc: 6878 ldr r0, [r7, #4] 8001fde: f005 fdd1 bl 8007b84 8001fe2: 4603 mov r3, r0 8001fe4: 2b00 cmp r3, #0 8001fe6: d12d bne.n 8002044 printf("Command list:\n"); 8001fe8: 482c ldr r0, [pc, #176] ; (800209c ) 8001fea: f005 fdb3 bl 8007b54 printf("reset\n"); 8001fee: 482c ldr r0, [pc, #176] ; (80020a0 ) 8001ff0: f005 fdb0 bl 8007b54 printf("help\n"); 8001ff4: 4828 ldr r0, [pc, #160] ; (8002098 ) 8001ff6: f005 fdad bl 8007b54 printf("cc_state\n"); 8001ffa: 482a ldr r0, [pc, #168] ; (80020a4 ) 8001ffc: f005 fdaa bl 8007b54 printf("lock_lock\n"); 8002000: 4829 ldr r0, [pc, #164] ; (80020a8 ) 8002002: f005 fda7 bl 8007b54 printf("lock_unlock\n"); 8002006: 4829 ldr r0, [pc, #164] ; (80020ac ) 8002008: f005 fda4 bl 8007b54 printf("lock_state\n"); 800200c: 4828 ldr r0, [pc, #160] ; (80020b0 ) 800200e: f005 fda1 bl 8007b54 printf("adc\n"); 8002012: 4828 ldr r0, [pc, #160] ; (80020b4 ) 8002014: f005 fd9e bl 8007b54 printf("relay(cc,aux)\n"); 8002018: 4827 ldr r0, [pc, #156] ; (80020b8 ) 800201a: f005 fd9b bl 8007b54 printf("start\n"); 800201e: 4827 ldr r0, [pc, #156] ; (80020bc ) 8002020: f005 fd98 bl 8007b54 printf("stop\n"); 8002024: 4826 ldr r0, [pc, #152] ; (80020c0 ) 8002026: f005 fd95 bl 8007b54 printf("stop1\n"); 800202a: 4826 ldr r0, [pc, #152] ; (80020c4 ) 800202c: f005 fd92 bl 8007b54 printf("force\n"); 8002030: 4825 ldr r0, [pc, #148] ; (80020c8 ) 8002032: f005 fd8f bl 8007b54 printf("info1\n"); 8002036: 4825 ldr r0, [pc, #148] ; (80020cc ) 8002038: f005 fd8c bl 8007b54 printf("info2\n"); 800203c: 4805 ldr r0, [pc, #20] ; (8002054 ) 800203e: f005 fd89 bl 8007b54 } 8002042: e003 b.n 800204c printf("Unknown command\n"); 8002044: 4822 ldr r0, [pc, #136] ; (80020d0 ) 8002046: f005 fd85 bl 8007b54 } 800204a: e7ff b.n 800204c 800204c: bf00 nop 800204e: 3710 adds r7, #16 8002050: 46bd mov sp, r7 8002052: bd80 pop {r7, pc} 8002054: 08008c24 .word 0x08008c24 8002058: 08008c2c .word 0x08008c2c 800205c: 20000134 .word 0x20000134 8002060: 08008c38 .word 0x08008c38 8002064: 08008c4c .word 0x08008c4c 8002068: 08008c60 .word 0x08008c60 800206c: 08008c78 .word 0x08008c78 8002070: 2000013c .word 0x2000013c 8002074: 08008c90 .word 0x08008c90 8002078: 08008ca8 .word 0x08008ca8 800207c: 08008cbc .word 0x08008cbc 8002080: 08008ce8 .word 0x08008ce8 8002084: 08008cfc .word 0x08008cfc 8002088: 2000014c .word 0x2000014c 800208c: 08008d0c .word 0x08008d0c 8002090: 2000015d .word 0x2000015d 8002094: 08008d1c .word 0x08008d1c 8002098: 08008d30 .word 0x08008d30 800209c: 08008d38 .word 0x08008d38 80020a0: 08008ab8 .word 0x08008ab8 80020a4: 08008b78 .word 0x08008b78 80020a8: 08008b1c .word 0x08008b1c 80020ac: 08008b30 .word 0x08008b30 80020b0: 08008b00 .word 0x08008b00 80020b4: 08008af0 .word 0x08008af0 80020b8: 08008d48 .word 0x08008d48 80020bc: 08008b48 .word 0x08008b48 80020c0: 08008b58 .word 0x08008b58 80020c4: 08008b68 .word 0x08008b68 80020c8: 08008b70 .word 0x08008b70 80020cc: 08008bc4 .word 0x08008bc4 80020d0: 08008d58 .word 0x08008d58 080020d4 : void debug_task(){ 80020d4: b580 push {r7, lr} 80020d6: af00 add r7, sp, #0 if(debug_cmd_received){ 80020d8: 4b09 ldr r3, [pc, #36] ; (8002100 ) 80020da: 781b ldrb r3, [r3, #0] 80020dc: 2b00 cmp r3, #0 80020de: d00d beq.n 80020fc parse_command(debug_rx_buffer, debug_rx_buffer_size); 80020e0: 4b08 ldr r3, [pc, #32] ; (8002104 ) 80020e2: 781b ldrb r3, [r3, #0] 80020e4: 4619 mov r1, r3 80020e6: 4808 ldr r0, [pc, #32] ; (8002108 ) 80020e8: f7ff fd62 bl 8001bb0 HAL_UARTEx_ReceiveToIdle_IT(&huart2,debug_rx_buffer,255); 80020ec: 22ff movs r2, #255 ; 0xff 80020ee: 4906 ldr r1, [pc, #24] ; (8002108 ) 80020f0: 4806 ldr r0, [pc, #24] ; (800210c ) 80020f2: f004 fe38 bl 8006d66 debug_cmd_received = 0; 80020f6: 4b02 ldr r3, [pc, #8] ; (8002100 ) 80020f8: 2200 movs r2, #0 80020fa: 701a strb r2, [r3, #0] } } 80020fc: bf00 nop 80020fe: bd80 pop {r7, pc} 8002100: 200002a0 .word 0x200002a0 8002104: 200002a1 .word 0x200002a1 8002108: 200001a0 .word 0x200001a0 800210c: 20003130 .word 0x20003130 08002110 : * DestinationID: Packet Destination ID * Addr: First register address in sequence * *data: pointer for data array * len: length of data (1..255) */ void EDCAN_ReadHandler(uint8_t SourceID, uint8_t DestinationID, uint16_t Addr, uint8_t *data, uint8_t len){ 8002110: b480 push {r7} 8002112: b085 sub sp, #20 8002114: af00 add r7, sp, #0 8002116: 603b str r3, [r7, #0] 8002118: 4603 mov r3, r0 800211a: 71fb strb r3, [r7, #7] 800211c: 460b mov r3, r1 800211e: 71bb strb r3, [r7, #6] 8002120: 4613 mov r3, r2 8002122: 80bb strh r3, [r7, #4] // printf("Destination ID = %d\n", DestinationID); // printf("Address = %d\n", Addr); // printf("Len = %d\n", len); // printf("\n"); for (uint16_t AddrOffset = 0; AddrOffset < len; AddrOffset++){ //по очереди перебираем все полученные регистры через Handler 8002124: 2300 movs r3, #0 8002126: 81fb strh r3, [r7, #14] 8002128: e002 b.n 8002130 800212a: 89fb ldrh r3, [r7, #14] 800212c: 3301 adds r3, #1 800212e: 81fb strh r3, [r7, #14] 8002130: 7e3b ldrb r3, [r7, #24] 8002132: b29b uxth r3, r3 8002134: 89fa ldrh r2, [r7, #14] 8002136: 429a cmp r2, r3 8002138: d3f7 bcc.n 800212a // } // } } // printf("\n"); } 800213a: bf00 nop 800213c: bf00 nop 800213e: 3714 adds r7, #20 8002140: 46bd mov sp, r7 8002142: bc80 pop {r7} 8002144: 4770 bx lr ... 08002148 : * DestinationID: Packet Destination ID * Addr: First register address in sequence * *data: pointer for data array * len: length of data (1..255) */ void EDCAN_WriteUserRegister(uint16_t addr, uint8_t value){ 8002148: b580 push {r7, lr} 800214a: b082 sub sp, #8 800214c: af00 add r7, sp, #0 800214e: 4603 mov r3, r0 8002150: 460a mov r2, r1 8002152: 80fb strh r3, [r7, #6] 8002154: 4613 mov r3, r2 8002156: 717b strb r3, [r7, #5] switch(addr){ 8002158: 88fb ldrh r3, [r7, #6] 800215a: f240 5285 movw r2, #1413 ; 0x585 800215e: 4293 cmp r3, r2 8002160: dc79 bgt.n 8002256 8002162: f5b3 6fb0 cmp.w r3, #1408 ; 0x580 8002166: da6e bge.n 8002246 8002168: f5b3 7f80 cmp.w r3, #256 ; 0x100 800216c: d042 beq.n 80021f4 800216e: f5b3 7f80 cmp.w r3, #256 ; 0x100 8002172: db70 blt.n 8002256 8002174: f5b3 7f0a cmp.w r3, #552 ; 0x228 8002178: dc6d bgt.n 8002256 800217a: f5b3 7f04 cmp.w r3, #528 ; 0x210 800217e: db6a blt.n 8002256 8002180: f5a3 7304 sub.w r3, r3, #528 ; 0x210 8002184: 2b18 cmp r3, #24 8002186: d866 bhi.n 8002256 8002188: a201 add r2, pc, #4 ; (adr r2, 8002190 ) 800218a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800218e: bf00 nop 8002190: 08002207 .word 0x08002207 8002194: 08002213 .word 0x08002213 8002198: 0800221f .word 0x0800221f 800219c: 0800222b .word 0x0800222b 80021a0: 08002257 .word 0x08002257 80021a4: 08002257 .word 0x08002257 80021a8: 08002257 .word 0x08002257 80021ac: 08002257 .word 0x08002257 80021b0: 08002257 .word 0x08002257 80021b4: 08002257 .word 0x08002257 80021b8: 08002257 .word 0x08002257 80021bc: 08002257 .word 0x08002257 80021c0: 08002257 .word 0x08002257 80021c4: 08002257 .word 0x08002257 80021c8: 08002257 .word 0x08002257 80021cc: 08002257 .word 0x08002257 80021d0: 08002237 .word 0x08002237 80021d4: 08002237 .word 0x08002237 80021d8: 08002237 .word 0x08002237 80021dc: 08002237 .word 0x08002237 80021e0: 08002237 .word 0x08002237 80021e4: 08002237 .word 0x08002237 80021e8: 08002237 .word 0x08002237 80021ec: 08002237 .word 0x08002237 80021f0: 08002237 .word 0x08002237 // case EDCAN_REG_K0: // printf ("K0 = %d\n", value); // HAL_GPIO_WritePin (K0_GPIO_Port, K0_Pin, (value == 0)); // break; case EDCAN_REG_CHARGER_ENABLE: if(value){ 80021f4: 797b ldrb r3, [r7, #5] 80021f6: 2b00 cmp r3, #0 80021f8: d002 beq.n 8002200 GBT_Start();//TODO IF protections 80021fa: f7ff fc73 bl 8001ae4 }else{ GBT_Stop(); } break; 80021fe: e02e b.n 800225e GBT_Stop(); 8002200: f7ff fc54 bl 8001aac break; 8002204: e02b b.n 800225e case EDCAN_REG_TIME_0: writeTimeReg(0, value); 8002206: 797b ldrb r3, [r7, #5] 8002208: 4619 mov r1, r3 800220a: 2000 movs r0, #0 800220c: f001 faa2 bl 8003754 break; 8002210: e025 b.n 800225e case EDCAN_REG_TIME_1: writeTimeReg(1, value); 8002212: 797b ldrb r3, [r7, #5] 8002214: 4619 mov r1, r3 8002216: 2001 movs r0, #1 8002218: f001 fa9c bl 8003754 break; 800221c: e01f b.n 800225e case EDCAN_REG_TIME_2: writeTimeReg(2, value); 800221e: 797b ldrb r3, [r7, #5] 8002220: 4619 mov r1, r3 8002222: 2002 movs r0, #2 8002224: f001 fa96 bl 8003754 break; 8002228: e019 b.n 800225e case EDCAN_REG_TIME_3: writeTimeReg(3, value); 800222a: 797b ldrb r3, [r7, #5] 800222c: 4619 mov r1, r3 800222e: 2003 movs r0, #3 8002230: f001 fa90 bl 8003754 break; 8002234: e013 b.n 800225e //0x220 case EDCAN_REG_MAX_LOAD ... (EDCAN_REG_MAX_LOAD+sizeof(GBT_CML_t)): ((uint8_t*)&GBT_MaxLoad)[addr - EDCAN_REG_MAX_LOAD] = value; 8002236: 88fb ldrh r3, [r7, #6] 8002238: f5a3 7308 sub.w r3, r3, #544 ; 0x220 800223c: 4a0a ldr r2, [pc, #40] ; (8002268 ) 800223e: 4413 add r3, r2 8002240: 797a ldrb r2, [r7, #5] 8002242: 701a strb r2, [r3, #0] break; 8002244: e00b b.n 800225e //0x580 case EDCAN_REG_INPUT ... (EDCAN_REG_INPUT+sizeof(GBT_EDCAN_Input_t)): ((uint8_t*)&GBT_EDCAN_Input)[addr - EDCAN_REG_INPUT] = value; 8002246: 88fb ldrh r3, [r7, #6] 8002248: f5a3 63b0 sub.w r3, r3, #1408 ; 0x580 800224c: 4a07 ldr r2, [pc, #28] ; (800226c ) 800224e: 4413 add r3, r2 8002250: 797a ldrb r2, [r7, #5] 8002252: 701a strb r2, [r3, #0] //TODO //GBT_EDCAN_Input.measuredCurrent; break; 8002254: e003 b.n 800225e default: printf ("Unknown register\n"); 8002256: 4806 ldr r0, [pc, #24] ; (8002270 ) 8002258: f005 fc7c bl 8007b54 } } 800225c: bf00 nop 800225e: bf00 nop 8002260: 3708 adds r7, #8 8002262: 46bd mov sp, r7 8002264: bd80 pop {r7, pc} 8002266: bf00 nop 8002268: 20000124 .word 0x20000124 800226c: 200002b0 .word 0x200002b0 8002270: 08008d68 .word 0x08008d68 08002274 : uint8_t EDCAN_GetUserRegisterValue(uint16_t addr){ 8002274: b580 push {r7, lr} 8002276: b082 sub sp, #8 8002278: af00 add r7, sp, #0 800227a: 4603 mov r3, r0 800227c: 80fb strh r3, [r7, #6] switch (addr){ 800227e: 88fb ldrh r3, [r7, #6] 8002280: f240 5285 movw r2, #1413 ; 0x585 8002284: 4293 cmp r3, r2 8002286: f300 8123 bgt.w 80024d0 800228a: f5b3 6fb0 cmp.w r3, #1408 ; 0x580 800228e: f280 8118 bge.w 80024c2 8002292: f240 520c movw r2, #1292 ; 0x50c 8002296: 4293 cmp r3, r2 8002298: f300 811a bgt.w 80024d0 800229c: f5b3 6fa0 cmp.w r3, #1280 ; 0x500 80022a0: f280 8108 bge.w 80024b4 80022a4: f5b3 7f62 cmp.w r3, #904 ; 0x388 80022a8: f280 8112 bge.w 80024d0 80022ac: f5b3 7f54 cmp.w r3, #848 ; 0x350 80022b0: da07 bge.n 80022c2 80022b2: f5b3 7f0a cmp.w r3, #552 ; 0x228 80022b6: f300 80b7 bgt.w 8002428 80022ba: f5b3 7f04 cmp.w r3, #528 ; 0x210 80022be: da79 bge.n 80023b4 80022c0: e106 b.n 80024d0 80022c2: f5a3 7354 sub.w r3, r3, #848 ; 0x350 80022c6: 2b37 cmp r3, #55 ; 0x37 80022c8: f200 8102 bhi.w 80024d0 80022cc: a201 add r2, pc, #4 ; (adr r2, 80022d4 ) 80022ce: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80022d2: bf00 nop 80022d4: 08002477 .word 0x08002477 80022d8: 08002477 .word 0x08002477 80022dc: 08002477 .word 0x08002477 80022e0: 08002477 .word 0x08002477 80022e4: 08002477 .word 0x08002477 80022e8: 08002477 .word 0x08002477 80022ec: 08002477 .word 0x08002477 80022f0: 08002477 .word 0x08002477 80022f4: 08002477 .word 0x08002477 80022f8: 08002477 .word 0x08002477 80022fc: 08002477 .word 0x08002477 8002300: 08002477 .word 0x08002477 8002304: 08002477 .word 0x08002477 8002308: 08002477 .word 0x08002477 800230c: 080024d1 .word 0x080024d1 8002310: 08002485 .word 0x08002485 8002314: 0800248b .word 0x0800248b 8002318: 0800248b .word 0x0800248b 800231c: 0800248b .word 0x0800248b 8002320: 0800248b .word 0x0800248b 8002324: 0800248b .word 0x0800248b 8002328: 0800248b .word 0x0800248b 800232c: 080024d1 .word 0x080024d1 8002330: 080024d1 .word 0x080024d1 8002334: 080024d1 .word 0x080024d1 8002338: 080024d1 .word 0x080024d1 800233c: 080024d1 .word 0x080024d1 8002340: 080024d1 .word 0x080024d1 8002344: 080024d1 .word 0x080024d1 8002348: 080024d1 .word 0x080024d1 800234c: 080024d1 .word 0x080024d1 8002350: 080024d1 .word 0x080024d1 8002354: 08002499 .word 0x08002499 8002358: 08002499 .word 0x08002499 800235c: 08002499 .word 0x08002499 8002360: 08002499 .word 0x08002499 8002364: 08002499 .word 0x08002499 8002368: 08002499 .word 0x08002499 800236c: 08002499 .word 0x08002499 8002370: 08002499 .word 0x08002499 8002374: 08002499 .word 0x08002499 8002378: 08002499 .word 0x08002499 800237c: 08002499 .word 0x08002499 8002380: 08002499 .word 0x08002499 8002384: 080024d1 .word 0x080024d1 8002388: 080024d1 .word 0x080024d1 800238c: 080024d1 .word 0x080024d1 8002390: 080024d1 .word 0x080024d1 8002394: 080024a7 .word 0x080024a7 8002398: 080024a7 .word 0x080024a7 800239c: 080024a7 .word 0x080024a7 80023a0: 080024a7 .word 0x080024a7 80023a4: 080024a7 .word 0x080024a7 80023a8: 080024a7 .word 0x080024a7 80023ac: 080024a7 .word 0x080024a7 80023b0: 080024a7 .word 0x080024a7 80023b4: f5a3 7304 sub.w r3, r3, #528 ; 0x210 80023b8: 2b18 cmp r3, #24 80023ba: f200 8089 bhi.w 80024d0 80023be: a201 add r2, pc, #4 ; (adr r2, 80023c4 ) 80023c0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80023c4: 08002433 .word 0x08002433 80023c8: 0800243d .word 0x0800243d 80023cc: 08002447 .word 0x08002447 80023d0: 08002451 .word 0x08002451 80023d4: 080024d1 .word 0x080024d1 80023d8: 080024d1 .word 0x080024d1 80023dc: 080024d1 .word 0x080024d1 80023e0: 080024d1 .word 0x080024d1 80023e4: 080024d1 .word 0x080024d1 80023e8: 080024d1 .word 0x080024d1 80023ec: 080024d1 .word 0x080024d1 80023f0: 080024d1 .word 0x080024d1 80023f4: 080024d1 .word 0x080024d1 80023f8: 080024d1 .word 0x080024d1 80023fc: 080024d1 .word 0x080024d1 8002400: 080024d1 .word 0x080024d1 8002404: 0800245b .word 0x0800245b 8002408: 0800245b .word 0x0800245b 800240c: 0800245b .word 0x0800245b 8002410: 0800245b .word 0x0800245b 8002414: 0800245b .word 0x0800245b 8002418: 0800245b .word 0x0800245b 800241c: 0800245b .word 0x0800245b 8002420: 0800245b .word 0x0800245b 8002424: 0800245b .word 0x0800245b 8002428: f5a3 7344 sub.w r3, r3, #784 ; 0x310 800242c: 2b30 cmp r3, #48 ; 0x30 800242e: d84f bhi.n 80024d0 8002430: e01a b.n 8002468 // /* регистры 256..2047 используются пользовательских нужд */ case EDCAN_REG_TIME_0: return getTimeReg(0); 8002432: 2000 movs r0, #0 8002434: f001 f9b6 bl 80037a4 8002438: 4603 mov r3, r0 800243a: e04a b.n 80024d2 break; case EDCAN_REG_TIME_1: return getTimeReg(1); 800243c: 2001 movs r0, #1 800243e: f001 f9b1 bl 80037a4 8002442: 4603 mov r3, r0 8002444: e045 b.n 80024d2 break; case EDCAN_REG_TIME_2: return getTimeReg(2); 8002446: 2002 movs r0, #2 8002448: f001 f9ac bl 80037a4 800244c: 4603 mov r3, r0 800244e: e040 b.n 80024d2 break; case EDCAN_REG_TIME_3: return getTimeReg(3); 8002450: 2003 movs r0, #3 8002452: f001 f9a7 bl 80037a4 8002456: 4603 mov r3, r0 8002458: e03b b.n 80024d2 break; //0x220 case EDCAN_REG_MAX_LOAD ... (EDCAN_REG_MAX_LOAD+sizeof(GBT_CML_t)): return ((uint8_t*)&GBT_MaxLoad)[addr - EDCAN_REG_MAX_LOAD]; 800245a: 88fb ldrh r3, [r7, #6] 800245c: f5a3 7308 sub.w r3, r3, #544 ; 0x220 8002460: 4a1e ldr r2, [pc, #120] ; (80024dc ) 8002462: 4413 add r3, r2 8002464: 781b ldrb r3, [r3, #0] 8002466: e034 b.n 80024d2 //0x310 case EDCAN_REG_BRM ... (EDCAN_REG_BRM+sizeof(GBT_BRM_t)-1): return ((uint8_t*)&GBT_EVInfo)[addr - EDCAN_REG_BRM]; 8002468: 88fb ldrh r3, [r7, #6] 800246a: f5a3 7344 sub.w r3, r3, #784 ; 0x310 800246e: 4a1c ldr r2, [pc, #112] ; (80024e0 ) 8002470: 4413 add r3, r2 8002472: 781b ldrb r3, [r3, #0] 8002474: e02d b.n 80024d2 //0x340 case EDCAN_REG_BCP ... (EDCAN_REG_BCP+sizeof(GBT_BCP_t)): return ((uint8_t*)&GBT_BATStat)[addr - EDCAN_REG_BCP]; 8002476: 88fb ldrh r3, [r7, #6] 8002478: f5a3 7354 sub.w r3, r3, #848 ; 0x350 800247c: 4a19 ldr r2, [pc, #100] ; (80024e4 ) 800247e: 4413 add r3, r2 8002480: 781b ldrb r3, [r3, #0] 8002482: e026 b.n 80024d2 //0x34F case EDCAN_REG_BRO: return GBT_BRO; 8002484: 4b18 ldr r3, [pc, #96] ; (80024e8 ) 8002486: 781b ldrb r3, [r3, #0] 8002488: e023 b.n 80024d2 //0x350 case EDCAN_REG_BCL ... (EDCAN_REG_BCL+sizeof(GBT_BCL_t)): return ((uint8_t*)&GBT_ReqPower)[addr - EDCAN_REG_BCL]; 800248a: 88fb ldrh r3, [r7, #6] 800248c: f5a3 7358 sub.w r3, r3, #864 ; 0x360 8002490: 4a16 ldr r2, [pc, #88] ; (80024ec ) 8002492: 4413 add r3, r2 8002494: 781b ldrb r3, [r3, #0] 8002496: e01c b.n 80024d2 //0x360 case EDCAN_REG_BCS ... (EDCAN_REG_BCS+sizeof(GBT_BCS_t)): return ((uint8_t*)&GBT_ChargingStatus)[addr - EDCAN_REG_BCS]; 8002498: 88fb ldrh r3, [r7, #6] 800249a: f5a3 735c sub.w r3, r3, #880 ; 0x370 800249e: 4a14 ldr r2, [pc, #80] ; (80024f0 ) 80024a0: 4413 add r3, r2 80024a2: 781b ldrb r3, [r3, #0] 80024a4: e015 b.n 80024d2 //0x370 case EDCAN_REG_BSM ... (EDCAN_REG_BSM+sizeof(GBT_BSM_t)): return ((uint8_t*)&GBT_BatteryStatus)[addr - EDCAN_REG_BSM]; 80024a6: 88fb ldrh r3, [r7, #6] 80024a8: f5a3 7360 sub.w r3, r3, #896 ; 0x380 80024ac: 4a11 ldr r2, [pc, #68] ; (80024f4 ) 80024ae: 4413 add r3, r2 80024b0: 781b ldrb r3, [r3, #0] 80024b2: e00e b.n 80024d2 //0x500 case EDCAN_REG_OUTPUT ... (EDCAN_REG_OUTPUT+sizeof(GBT_EDCAN_Output_t)): return ((uint8_t*)&GBT_EDCAN_Output)[addr - EDCAN_REG_OUTPUT]; 80024b4: 88fb ldrh r3, [r7, #6] 80024b6: f5a3 63a0 sub.w r3, r3, #1280 ; 0x500 80024ba: 4a0f ldr r2, [pc, #60] ; (80024f8 ) 80024bc: 4413 add r3, r2 80024be: 781b ldrb r3, [r3, #0] 80024c0: e007 b.n 80024d2 //0x580 case EDCAN_REG_INPUT ... (EDCAN_REG_INPUT+sizeof(GBT_EDCAN_Input_t)): return ((uint8_t*)&GBT_EDCAN_Input)[addr - EDCAN_REG_INPUT]; 80024c2: 88fb ldrh r3, [r7, #6] 80024c4: f5a3 63b0 sub.w r3, r3, #1408 ; 0x580 80024c8: 4a0c ldr r2, [pc, #48] ; (80024fc ) 80024ca: 4413 add r3, r2 80024cc: 781b ldrb r3, [r3, #0] 80024ce: e000 b.n 80024d2 default: return 0x00; 80024d0: 2300 movs r3, #0 } } 80024d2: 4618 mov r0, r3 80024d4: 3708 adds r7, #8 80024d6: 46bd mov sp, r7 80024d8: bd80 pop {r7, pc} 80024da: bf00 nop 80024dc: 20000124 .word 0x20000124 80024e0: 20000134 .word 0x20000134 80024e4: 20000168 .word 0x20000168 80024e8: 2000019c .word 0x2000019c 80024ec: 20000178 .word 0x20000178 80024f0: 20000180 .word 0x20000180 80024f4: 2000018c .word 0x2000018c 80024f8: 200002a4 .word 0x200002a4 80024fc: 200002b0 .word 0x200002b0 08002500 : // GB/T Time Synchronization Packet #include "main.h" #include "soft_rtc.h" #include "charger_gbt.h" void GBT_SendCTS(){ 8002500: b580 push {r7, lr} 8002502: b082 sub sp, #8 8002504: af00 add r7, sp, #0 uint8_t data[7]; unix_to_bcd(get_Current_Time(), data); 8002506: f001 f861 bl 80035cc 800250a: 4602 mov r2, r0 800250c: 463b mov r3, r7 800250e: 4619 mov r1, r3 8002510: 4610 mov r0, r2 8002512: f001 f8b3 bl 800367c // data[3] = 0x05; //days // data[4] = 0x05; //month // data[5] = 0x24; //years // data[6] = 0x20; //centuries J_SendPacket(0x000700, 6, 7, data); 8002516: 463b mov r3, r7 8002518: 2207 movs r2, #7 800251a: 2106 movs r1, #6 800251c: f44f 60e0 mov.w r0, #1792 ; 0x700 8002520: f000 fa6c bl 80029fc } 8002524: bf00 nop 8002526: 3708 adds r7, #8 8002528: 46bd mov sp, r7 800252a: bd80 pop {r7, pc} 0800252c : //TODO //GB/T Max Load Packet void GBT_SendCML(){ 800252c: b580 push {r7, lr} 800252e: af00 add r7, sp, #0 // data[4] = 0xC4; //-150A maximum output current // data[5] = 0x09; // // data[6] = 0x8C; //-2A minimum output current // data[7] = 0x0F; // J_SendPacket(0x000800, 6, 8, (uint8_t*)&GBT_MaxLoad); 8002530: 4b04 ldr r3, [pc, #16] ; (8002544 ) 8002532: 2208 movs r2, #8 8002534: 2106 movs r1, #6 8002536: f44f 6000 mov.w r0, #2048 ; 0x800 800253a: f000 fa5f bl 80029fc } 800253e: bf00 nop 8002540: bd80 pop {r7, pc} 8002542: bf00 nop 8002544: 20000124 .word 0x20000124 08002548 : //GB/T Version packet void GBT_SendCHM(){ 8002548: b580 push {r7, lr} 800254a: b082 sub sp, #8 800254c: af00 add r7, sp, #0 uint8_t data[3]; data[0] = 0x01; 800254e: 2301 movs r3, #1 8002550: 713b strb r3, [r7, #4] data[1] = 0x01; 8002552: 2301 movs r3, #1 8002554: 717b strb r3, [r7, #5] data[2] = 0x00; 8002556: 2300 movs r3, #0 8002558: 71bb strb r3, [r7, #6] J_SendPacket(0x2600, 6, 3, data); 800255a: 1d3b adds r3, r7, #4 800255c: 2203 movs r2, #3 800255e: 2106 movs r1, #6 8002560: f44f 5018 mov.w r0, #9728 ; 0x2600 8002564: f000 fa4a bl 80029fc } 8002568: bf00 nop 800256a: 3708 adds r7, #8 800256c: 46bd mov sp, r7 800256e: bd80 pop {r7, pc} 08002570 : //TODO //GB/T CRM Packet (state=BMS identified) void GBT_SendCRM(uint8_t state){ 8002570: b580 push {r7, lr} 8002572: b082 sub sp, #8 8002574: af00 add r7, sp, #0 8002576: 4603 mov r3, r0 8002578: 71fb strb r3, [r7, #7] // data[3] = 0x01; // data[4] = 0x00; // data[5] = 0x42; //TODO: location BFG // data[6] = 0x46; // data[7] = 0x47; GBT_ChargerInfo.bmsIdentified = state; 800257a: 4a07 ldr r2, [pc, #28] ; (8002598 ) 800257c: 79fb ldrb r3, [r7, #7] 800257e: 7013 strb r3, [r2, #0] J_SendPacket(0x100, 6, 8, (uint8_t *)&GBT_ChargerInfo); 8002580: 4b05 ldr r3, [pc, #20] ; (8002598 ) 8002582: 2208 movs r2, #8 8002584: 2106 movs r1, #6 8002586: f44f 7080 mov.w r0, #256 ; 0x100 800258a: f000 fa37 bl 80029fc } 800258e: bf00 nop 8002590: 3708 adds r7, #8 8002592: 46bd mov sp, r7 8002594: bd80 pop {r7, pc} 8002596: bf00 nop 8002598: 2000012c .word 0x2000012c 0800259c : //GB/T CRO packet (Charger ready) void GBT_SendCRO(uint8_t state){ 800259c: b580 push {r7, lr} 800259e: b084 sub sp, #16 80025a0: af00 add r7, sp, #0 80025a2: 4603 mov r3, r0 80025a4: 71fb strb r3, [r7, #7] uint8_t data[1]; data[0] = state; 80025a6: 79fb ldrb r3, [r7, #7] 80025a8: 733b strb r3, [r7, #12] J_SendPacket(0xA00, 4, 1, data); 80025aa: f107 030c add.w r3, r7, #12 80025ae: 2201 movs r2, #1 80025b0: 2104 movs r1, #4 80025b2: f44f 6020 mov.w r0, #2560 ; 0xa00 80025b6: f000 fa21 bl 80029fc } 80025ba: bf00 nop 80025bc: 3710 adds r7, #16 80025be: 46bd mov sp, r7 80025c0: bd80 pop {r7, pc} ... 080025c4 : //TODO: Send measured voltage current //GB/T CCS packet (Charger current status) void GBT_SendCCS(){ 80025c4: b580 push {r7, lr} 80025c6: af00 add r7, sp, #0 // data[3] = GBT_CurrPower.requestedCurrent>>8; //TODO: current // data[4] = GBT_StateTick()/60000; //charging time (min) // data[5] = 0; //TODO: 255 min+ // data[6] = 0b11111101; //charging not permitted // data[7] = 0xFF; J_SendPacket(0x1200, 6, 8, (uint8_t *)&GBT_ChargerCurrentStatus); 80025c8: 4b04 ldr r3, [pc, #16] ; (80025dc ) 80025ca: 2208 movs r2, #8 80025cc: 2106 movs r1, #6 80025ce: f44f 5090 mov.w r0, #4608 ; 0x1200 80025d2: f000 fa13 bl 80029fc } 80025d6: bf00 nop 80025d8: bd80 pop {r7, pc} 80025da: bf00 nop 80025dc: 20000194 .word 0x20000194 080025e0 : //TODO: stop cause // GB/T Charging Stop packet void GBT_SendCST(){ 80025e0: b580 push {r7, lr} 80025e2: b082 sub sp, #8 80025e4: af00 add r7, sp, #0 uint8_t data[8]; data[0] = 0x04; // Artificially stop charging 80025e6: 2304 movs r3, #4 80025e8: 703b strb r3, [r7, #0] data[1] = 0x00; //TODO: Cause stop 80025ea: 2300 movs r3, #0 80025ec: 707b strb r3, [r7, #1] data[2] = 0xF0; // 80025ee: 23f0 movs r3, #240 ; 0xf0 80025f0: 70bb strb r3, [r7, #2] data[3] = 0xF0; // 80025f2: 23f0 movs r3, #240 ; 0xf0 80025f4: 70fb strb r3, [r7, #3] J_SendPacket(0x1A00, 4, 4, data); 80025f6: 463b mov r3, r7 80025f8: 2204 movs r2, #4 80025fa: 2104 movs r1, #4 80025fc: f44f 50d0 mov.w r0, #6656 ; 0x1a00 8002600: f000 f9fc bl 80029fc } 8002604: bf00 nop 8002606: 3708 adds r7, #8 8002608: 46bd mov sp, r7 800260a: bd80 pop {r7, pc} 0800260c : * Output * EVENT_OUT * EXTI */ void MX_GPIO_Init(void) { 800260c: b580 push {r7, lr} 800260e: b08a sub sp, #40 ; 0x28 8002610: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002612: f107 0318 add.w r3, r7, #24 8002616: 2200 movs r2, #0 8002618: 601a str r2, [r3, #0] 800261a: 605a str r2, [r3, #4] 800261c: 609a str r2, [r3, #8] 800261e: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8002620: 4b53 ldr r3, [pc, #332] ; (8002770 ) 8002622: 699b ldr r3, [r3, #24] 8002624: 4a52 ldr r2, [pc, #328] ; (8002770 ) 8002626: f043 0310 orr.w r3, r3, #16 800262a: 6193 str r3, [r2, #24] 800262c: 4b50 ldr r3, [pc, #320] ; (8002770 ) 800262e: 699b ldr r3, [r3, #24] 8002630: f003 0310 and.w r3, r3, #16 8002634: 617b str r3, [r7, #20] 8002636: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8002638: 4b4d ldr r3, [pc, #308] ; (8002770 ) 800263a: 699b ldr r3, [r3, #24] 800263c: 4a4c ldr r2, [pc, #304] ; (8002770 ) 800263e: f043 0304 orr.w r3, r3, #4 8002642: 6193 str r3, [r2, #24] 8002644: 4b4a ldr r3, [pc, #296] ; (8002770 ) 8002646: 699b ldr r3, [r3, #24] 8002648: f003 0304 and.w r3, r3, #4 800264c: 613b str r3, [r7, #16] 800264e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8002650: 4b47 ldr r3, [pc, #284] ; (8002770 ) 8002652: 699b ldr r3, [r3, #24] 8002654: 4a46 ldr r2, [pc, #280] ; (8002770 ) 8002656: f043 0308 orr.w r3, r3, #8 800265a: 6193 str r3, [r2, #24] 800265c: 4b44 ldr r3, [pc, #272] ; (8002770 ) 800265e: 699b ldr r3, [r3, #24] 8002660: f003 0308 and.w r3, r3, #8 8002664: 60fb str r3, [r7, #12] 8002666: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 8002668: 4b41 ldr r3, [pc, #260] ; (8002770 ) 800266a: 699b ldr r3, [r3, #24] 800266c: 4a40 ldr r2, [pc, #256] ; (8002770 ) 800266e: f043 0340 orr.w r3, r3, #64 ; 0x40 8002672: 6193 str r3, [r2, #24] 8002674: 4b3e ldr r3, [pc, #248] ; (8002770 ) 8002676: 699b ldr r3, [r3, #24] 8002678: f003 0340 and.w r3, r3, #64 ; 0x40 800267c: 60bb str r3, [r7, #8] 800267e: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 8002680: 4b3b ldr r3, [pc, #236] ; (8002770 ) 8002682: 699b ldr r3, [r3, #24] 8002684: 4a3a ldr r2, [pc, #232] ; (8002770 ) 8002686: f043 0320 orr.w r3, r3, #32 800268a: 6193 str r3, [r2, #24] 800268c: 4b38 ldr r3, [pc, #224] ; (8002770 ) 800268e: 699b ldr r3, [r3, #24] 8002690: f003 0320 and.w r3, r3, #32 8002694: 607b str r3, [r7, #4] 8002696: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, LOCK_A_Pin|LOCK_B_Pin, GPIO_PIN_RESET); 8002698: 2200 movs r2, #0 800269a: 2130 movs r1, #48 ; 0x30 800269c: 4835 ldr r0, [pc, #212] ; (8002774 ) 800269e: f003 faa8 bl 8005bf2 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(RELAY_CC_GPIO_Port, RELAY_CC_Pin, GPIO_PIN_RESET); 80026a2: 2200 movs r2, #0 80026a4: f44f 4100 mov.w r1, #32768 ; 0x8000 80026a8: 4833 ldr r0, [pc, #204] ; (8002778 ) 80026aa: f003 faa2 bl 8005bf2 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(USART2_DIR_GPIO_Port, USART2_DIR_Pin, GPIO_PIN_RESET); 80026ae: 2200 movs r2, #0 80026b0: 2110 movs r1, #16 80026b2: 4832 ldr r0, [pc, #200] ; (800277c ) 80026b4: f003 fa9d bl 8005bf2 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(RELAY_AUX_GPIO_Port, RELAY_AUX_Pin, GPIO_PIN_RESET); 80026b8: 2200 movs r2, #0 80026ba: 2110 movs r1, #16 80026bc: 4830 ldr r0, [pc, #192] ; (8002780 ) 80026be: f003 fa98 bl 8005bf2 /*Configure GPIO pins : PCPin PCPin */ GPIO_InitStruct.Pin = LOCK_A_Pin|LOCK_B_Pin; 80026c2: 2330 movs r3, #48 ; 0x30 80026c4: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80026c6: 2301 movs r3, #1 80026c8: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80026ca: 2300 movs r3, #0 80026cc: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80026ce: 2302 movs r3, #2 80026d0: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80026d2: f107 0318 add.w r3, r7, #24 80026d6: 4619 mov r1, r3 80026d8: 4826 ldr r0, [pc, #152] ; (8002774 ) 80026da: f003 f8ef bl 80058bc /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = LOCK_FB_Pin; 80026de: f44f 7300 mov.w r3, #512 ; 0x200 80026e2: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80026e4: 2300 movs r3, #0 80026e6: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80026e8: 2300 movs r3, #0 80026ea: 623b str r3, [r7, #32] HAL_GPIO_Init(LOCK_FB_GPIO_Port, &GPIO_InitStruct); 80026ec: f107 0318 add.w r3, r7, #24 80026f0: 4619 mov r1, r3 80026f2: 4821 ldr r0, [pc, #132] ; (8002778 ) 80026f4: f003 f8e2 bl 80058bc /*Configure GPIO pins : PEPin PEPin */ GPIO_InitStruct.Pin = ADDR_0_Pin|ADDR_1_Pin; 80026f8: f44f 6340 mov.w r3, #3072 ; 0xc00 80026fc: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80026fe: 2300 movs r3, #0 8002700: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_PULLUP; 8002702: 2301 movs r3, #1 8002704: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8002706: f107 0318 add.w r3, r7, #24 800270a: 4619 mov r1, r3 800270c: 481a ldr r0, [pc, #104] ; (8002778 ) 800270e: f003 f8d5 bl 80058bc /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = RELAY_CC_Pin; 8002712: f44f 4300 mov.w r3, #32768 ; 0x8000 8002716: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8002718: 2301 movs r3, #1 800271a: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 800271c: 2300 movs r3, #0 800271e: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002720: 2302 movs r3, #2 8002722: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(RELAY_CC_GPIO_Port, &GPIO_InitStruct); 8002724: f107 0318 add.w r3, r7, #24 8002728: 4619 mov r1, r3 800272a: 4813 ldr r0, [pc, #76] ; (8002778 ) 800272c: f003 f8c6 bl 80058bc /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = USART2_DIR_Pin; 8002730: 2310 movs r3, #16 8002732: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8002734: 2301 movs r3, #1 8002736: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8002738: 2300 movs r3, #0 800273a: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800273c: 2302 movs r3, #2 800273e: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(USART2_DIR_GPIO_Port, &GPIO_InitStruct); 8002740: f107 0318 add.w r3, r7, #24 8002744: 4619 mov r1, r3 8002746: 480d ldr r0, [pc, #52] ; (800277c ) 8002748: f003 f8b8 bl 80058bc /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = RELAY_AUX_Pin; 800274c: 2310 movs r3, #16 800274e: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8002750: 2301 movs r3, #1 8002752: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8002754: 2300 movs r3, #0 8002756: 623b str r3, [r7, #32] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002758: 2302 movs r3, #2 800275a: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(RELAY_AUX_GPIO_Port, &GPIO_InitStruct); 800275c: f107 0318 add.w r3, r7, #24 8002760: 4619 mov r1, r3 8002762: 4807 ldr r0, [pc, #28] ; (8002780 ) 8002764: f003 f8aa bl 80058bc } 8002768: bf00 nop 800276a: 3728 adds r7, #40 ; 0x28 800276c: 46bd mov sp, r7 800276e: bd80 pop {r7, pc} 8002770: 40021000 .word 0x40021000 8002774: 40011000 .word 0x40011000 8002778: 40011800 .word 0x40011800 800277c: 40011400 .word 0x40011400 8002780: 40010c00 .word 0x40010c00 08002784 : extern GBT_BCL_t GBT_CurrPower; j_receive_t j_rx; void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) { 8002784: b590 push {r4, r7, lr} 8002786: b0cd sub sp, #308 ; 0x134 8002788: af40 add r7, sp, #256 ; 0x100 800278a: 6078 str r0, [r7, #4] CAN_RxHeaderTypeDef RxHeader; uint8_t RxData[8] = {0,}; 800278c: 2300 movs r3, #0 800278e: 60fb str r3, [r7, #12] 8002790: 2300 movs r3, #0 8002792: 613b str r3, [r7, #16] if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &RxHeader, RxData) == HAL_OK) 8002794: f107 030c add.w r3, r7, #12 8002798: f107 0214 add.w r2, r7, #20 800279c: 2100 movs r1, #0 800279e: 6878 ldr r0, [r7, #4] 80027a0: f002 fb07 bl 8004db2 80027a4: 4603 mov r3, r0 80027a6: 2b00 cmp r3, #0 80027a8: f040 8110 bne.w 80029cc { if((RxHeader.ExtId & 0x00FFFF) == ((J_ID_SE << 8) | J_ID_EV)){ // SA, DA match 80027ac: 69bb ldr r3, [r7, #24] 80027ae: b29b uxth r3, r3 80027b0: f245 62f4 movw r2, #22260 ; 0x56f4 80027b4: 4293 cmp r3, r2 80027b6: f040 8109 bne.w 80029cc switch ((RxHeader.ExtId>>8) & 0x00FF00){ 80027ba: 69bb ldr r3, [r7, #24] 80027bc: 0a1b lsrs r3, r3, #8 80027be: f403 437f and.w r3, r3, #65280 ; 0xff00 80027c2: f5b3 4f6c cmp.w r3, #60416 ; 0xec00 80027c6: d013 beq.n 80027f0 80027c8: f5b3 4f6c cmp.w r3, #60416 ; 0xec00 80027cc: f200 80c9 bhi.w 8002962 80027d0: f5b3 4f6b cmp.w r3, #60160 ; 0xeb00 80027d4: d056 beq.n 8002884 80027d6: f5b3 4f6b cmp.w r3, #60160 ; 0xeb00 80027da: f200 80c2 bhi.w 8002962 80027de: f5b3 5fc8 cmp.w r3, #6400 ; 0x1900 80027e2: f000 80bb beq.w 800295c 80027e6: f5b3 5ff0 cmp.w r3, #7680 ; 0x1e00 80027ea: f000 80b4 beq.w 8002956 80027ee: e0b8 b.n 8002962 case 0xEC00: //PGN Connection Management Message if(RxData[0] == 16){ //Request to Send 80027f0: 7b3b ldrb r3, [r7, #12] 80027f2: 2b10 cmp r3, #16 80027f4: d13d bne.n 8002872 /* Set the RTS values */ j_rx.size = RxData[1] | (RxData[2]<<8); 80027f6: 7b7b ldrb r3, [r7, #13] 80027f8: b21a sxth r2, r3 80027fa: 7bbb ldrb r3, [r7, #14] 80027fc: 021b lsls r3, r3, #8 80027fe: b21b sxth r3, r3 8002800: 4313 orrs r3, r2 8002802: b21b sxth r3, r3 8002804: b29a uxth r2, r3 8002806: 4b73 ldr r3, [pc, #460] ; (80029d4 ) 8002808: f8a3 2104 strh.w r2, [r3, #260] ; 0x104 j_rx.packet = 1; 800280c: 4b71 ldr r3, [pc, #452] ; (80029d4 ) 800280e: 2201 movs r2, #1 8002810: f883 2107 strb.w r2, [r3, #263] ; 0x107 j_rx.packets = RxData[3]; 8002814: 7bfa ldrb r2, [r7, #15] 8002816: 4b6f ldr r3, [pc, #444] ; (80029d4 ) 8002818: f883 2106 strb.w r2, [r3, #262] ; 0x106 j_rx.step = 2; //TODO 800281c: 4b6d ldr r3, [pc, #436] ; (80029d4 ) 800281e: 2202 movs r2, #2 8002820: f883 2108 strb.w r2, [r3, #264] ; 0x108 j_rx.step_cts_remain = j_rx.step; 8002824: 4b6b ldr r3, [pc, #428] ; (80029d4 ) 8002826: f893 2108 ldrb.w r2, [r3, #264] ; 0x108 800282a: 4b6a ldr r3, [pc, #424] ; (80029d4 ) 800282c: f883 2109 strb.w r2, [r3, #265] ; 0x109 j_rx.PGN = (RxData[7] << 16) | (RxData[6] << 8) | RxData[5]; 8002830: 7cfb ldrb r3, [r7, #19] 8002832: 041a lsls r2, r3, #16 8002834: 7cbb ldrb r3, [r7, #18] 8002836: 021b lsls r3, r3, #8 8002838: 4313 orrs r3, r2 800283a: 7c7a ldrb r2, [r7, #17] 800283c: 4313 orrs r3, r2 800283e: 461a mov r2, r3 8002840: 4b64 ldr r3, [pc, #400] ; (80029d4 ) 8002842: f8c3 2100 str.w r2, [r3, #256] ; 0x100 if(j_rx.size<256) { //TODO: valid check 8002846: 4b63 ldr r3, [pc, #396] ; (80029d4 ) 8002848: f8b3 3104 ldrh.w r3, [r3, #260] ; 0x104 800284c: 2bff cmp r3, #255 ; 0xff 800284e: d810 bhi.n 8002872 J_SendCTS(j_rx); 8002850: 4c60 ldr r4, [pc, #384] ; (80029d4 ) 8002852: 4668 mov r0, sp 8002854: f104 0310 add.w r3, r4, #16 8002858: f44f 7280 mov.w r2, #256 ; 0x100 800285c: 4619 mov r1, r3 800285e: f005 f801 bl 8007864 8002862: e894 000f ldmia.w r4, {r0, r1, r2, r3} 8002866: f000 f8f1 bl 8002a4c j_rx.state = 1; 800286a: 4b5a ldr r3, [pc, #360] ; (80029d4 ) 800286c: 2201 movs r2, #1 800286e: f883 210a strb.w r2, [r3, #266] ; 0x10a } } if(RxData[0] == 255){ //Connection Abort 8002872: 7b3b ldrb r3, [r7, #12] 8002874: 2bff cmp r3, #255 ; 0xff 8002876: f040 80a4 bne.w 80029c2 j_rx.state = 0; 800287a: 4b56 ldr r3, [pc, #344] ; (80029d4 ) 800287c: 2200 movs r2, #0 800287e: f883 210a strb.w r2, [r3, #266] ; 0x10a * 1CECF456 11 02 01 FF FF 00 02 00 * 1CEB56F4 01 01 01 00 03 46 05 40 * 1CEC56F4 FF FF FF FF FF 00 00 00 */ break; 8002882: e09e b.n 80029c2 case 0xEB00: //PGN Data Message if(j_rx.state != 1) break; 8002884: 4b53 ldr r3, [pc, #332] ; (80029d4 ) 8002886: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 800288a: 2b01 cmp r3, #1 800288c: f040 809b bne.w 80029c6 if((RxData[0]>0) && (RxData[0]<35)){ //Array limit check 8002890: 7b3b ldrb r3, [r7, #12] 8002892: 2b00 cmp r3, #0 8002894: f000 8099 beq.w 80029ca 8002898: 7b3b ldrb r3, [r7, #12] 800289a: 2b22 cmp r3, #34 ; 0x22 800289c: f200 8095 bhi.w 80029ca if(j_rx.packet == RxData[0]){ //step check 80028a0: 4b4c ldr r3, [pc, #304] ; (80029d4 ) 80028a2: f893 2107 ldrb.w r2, [r3, #263] ; 0x107 80028a6: 7b3b ldrb r3, [r7, #12] 80028a8: 429a cmp r2, r3 80028aa: f040 808e bne.w 80029ca memcpy (&j_rx.data[(RxData[0]-1)*7], &RxData[1],7); 80028ae: 7b3b ldrb r3, [r7, #12] 80028b0: 1e5a subs r2, r3, #1 80028b2: 4613 mov r3, r2 80028b4: 00db lsls r3, r3, #3 80028b6: 1a9b subs r3, r3, r2 80028b8: 4a46 ldr r2, [pc, #280] ; (80029d4 ) 80028ba: 1898 adds r0, r3, r2 80028bc: f107 030c add.w r3, r7, #12 80028c0: 3301 adds r3, #1 80028c2: 2207 movs r2, #7 80028c4: 4619 mov r1, r3 80028c6: f004 ffcd bl 8007864 j_rx.packet++; 80028ca: 4b42 ldr r3, [pc, #264] ; (80029d4 ) 80028cc: f893 3107 ldrb.w r3, [r3, #263] ; 0x107 80028d0: 3301 adds r3, #1 80028d2: b2da uxtb r2, r3 80028d4: 4b3f ldr r3, [pc, #252] ; (80029d4 ) 80028d6: f883 2107 strb.w r2, [r3, #263] ; 0x107 if(j_rx.packet > j_rx.packets){ 80028da: 4b3e ldr r3, [pc, #248] ; (80029d4 ) 80028dc: f893 2107 ldrb.w r2, [r3, #263] ; 0x107 80028e0: 4b3c ldr r3, [pc, #240] ; (80029d4 ) 80028e2: f893 3106 ldrb.w r3, [r3, #262] ; 0x106 80028e6: 429a cmp r2, r3 80028e8: d911 bls.n 800290e //End of transmission J_SendACK(j_rx); 80028ea: 4c3a ldr r4, [pc, #232] ; (80029d4 ) 80028ec: 4668 mov r0, sp 80028ee: f104 0310 add.w r3, r4, #16 80028f2: f44f 7280 mov.w r2, #256 ; 0x100 80028f6: 4619 mov r1, r3 80028f8: f004 ffb4 bl 8007864 80028fc: e894 000f ldmia.w r4, {r0, r1, r2, r3} 8002900: f000 f8ea bl 8002ad8 j_rx.state = 2; 8002904: 4b33 ldr r3, [pc, #204] ; (80029d4 ) 8002906: 2202 movs r2, #2 8002908: f883 210a strb.w r2, [r3, #266] ; 0x10a j_rx.step_cts_remain = 2; } } } } break; 800290c: e05d b.n 80029ca if(j_rx.step_cts_remain > 0) j_rx.step_cts_remain--; 800290e: 4b31 ldr r3, [pc, #196] ; (80029d4 ) 8002910: f893 3109 ldrb.w r3, [r3, #265] ; 0x109 8002914: 2b00 cmp r3, #0 8002916: d007 beq.n 8002928 8002918: 4b2e ldr r3, [pc, #184] ; (80029d4 ) 800291a: f893 3109 ldrb.w r3, [r3, #265] ; 0x109 800291e: 3b01 subs r3, #1 8002920: b2da uxtb r2, r3 8002922: 4b2c ldr r3, [pc, #176] ; (80029d4 ) 8002924: f883 2109 strb.w r2, [r3, #265] ; 0x109 if(j_rx.step_cts_remain == 0){ 8002928: 4b2a ldr r3, [pc, #168] ; (80029d4 ) 800292a: f893 3109 ldrb.w r3, [r3, #265] ; 0x109 800292e: 2b00 cmp r3, #0 8002930: d14b bne.n 80029ca J_SendCTS(j_rx); 8002932: 4c28 ldr r4, [pc, #160] ; (80029d4 ) 8002934: 4668 mov r0, sp 8002936: f104 0310 add.w r3, r4, #16 800293a: f44f 7280 mov.w r2, #256 ; 0x100 800293e: 4619 mov r1, r3 8002940: f004 ff90 bl 8007864 8002944: e894 000f ldmia.w r4, {r0, r1, r2, r3} 8002948: f000 f880 bl 8002a4c j_rx.step_cts_remain = 2; 800294c: 4b21 ldr r3, [pc, #132] ; (80029d4 ) 800294e: 2202 movs r2, #2 8002950: f883 2109 strb.w r2, [r3, #265] ; 0x109 break; 8002954: e039 b.n 80029ca case 0x1E00: //PGN BEM (ERROR) GBT_Stop(); 8002956: f7ff f8a9 bl 8001aac break; 800295a: e037 b.n 80029cc case 0x1900: //PGN BST (STOP) GBT_Stop(); 800295c: f7ff f8a6 bl 8001aac break; 8002960: e034 b.n 80029cc default: if(j_rx.state == 0){//TODO protections 8002962: 4b1c ldr r3, [pc, #112] ; (80029d4 ) 8002964: f893 310a ldrb.w r3, [r3, #266] ; 0x10a 8002968: 2b00 cmp r3, #0 800296a: d12f bne.n 80029cc //Short packet j_rx.size = RxHeader.DLC; 800296c: 6a7b ldr r3, [r7, #36] ; 0x24 800296e: b29a uxth r2, r3 8002970: 4b18 ldr r3, [pc, #96] ; (80029d4 ) 8002972: f8a3 2104 strh.w r2, [r3, #260] ; 0x104 j_rx.packet = 1; 8002976: 4b17 ldr r3, [pc, #92] ; (80029d4 ) 8002978: 2201 movs r2, #1 800297a: f883 2107 strb.w r2, [r3, #263] ; 0x107 j_rx.packets = 1; 800297e: 4b15 ldr r3, [pc, #84] ; (80029d4 ) 8002980: 2201 movs r2, #1 8002982: f883 2106 strb.w r2, [r3, #262] ; 0x106 j_rx.step = 1; 8002986: 4b13 ldr r3, [pc, #76] ; (80029d4 ) 8002988: 2201 movs r2, #1 800298a: f883 2108 strb.w r2, [r3, #264] ; 0x108 j_rx.step_cts_remain = 0; 800298e: 4b11 ldr r3, [pc, #68] ; (80029d4 ) 8002990: 2200 movs r2, #0 8002992: f883 2109 strb.w r2, [r3, #265] ; 0x109 j_rx.PGN = (RxHeader.ExtId>>8) & 0x00FF00; 8002996: 69bb ldr r3, [r7, #24] 8002998: 0a1b lsrs r3, r3, #8 800299a: f403 437f and.w r3, r3, #65280 ; 0xff00 800299e: 4a0d ldr r2, [pc, #52] ; (80029d4 ) 80029a0: f8c2 3100 str.w r3, [r2, #256] ; 0x100 j_rx.state = 2; 80029a4: 4b0b ldr r3, [pc, #44] ; (80029d4 ) 80029a6: 2202 movs r2, #2 80029a8: f883 210a strb.w r2, [r3, #266] ; 0x10a memcpy (j_rx.data, RxData, j_rx.size); 80029ac: 4b09 ldr r3, [pc, #36] ; (80029d4 ) 80029ae: f8b3 3104 ldrh.w r3, [r3, #260] ; 0x104 80029b2: 461a mov r2, r3 80029b4: f107 030c add.w r3, r7, #12 80029b8: 4619 mov r1, r3 80029ba: 4806 ldr r0, [pc, #24] ; (80029d4 ) 80029bc: f004 ff52 bl 8007864 } } } } } 80029c0: e004 b.n 80029cc break; 80029c2: bf00 nop 80029c4: e002 b.n 80029cc if(j_rx.state != 1) break; 80029c6: bf00 nop 80029c8: e000 b.n 80029cc break; 80029ca: bf00 nop } 80029cc: bf00 nop 80029ce: 3734 adds r7, #52 ; 0x34 80029d0: 46bd mov sp, r7 80029d2: bd90 pop {r4, r7, pc} 80029d4: 200002b8 .word 0x200002b8 080029d8 : void GBT_CAN_ReInit(){ 80029d8: b580 push {r7, lr} 80029da: af00 add r7, sp, #0 HAL_CAN_Stop(&hcan1); 80029dc: 4806 ldr r0, [pc, #24] ; (80029f8 ) 80029de: f002 f891 bl 8004b04 MX_CAN1_Init(); 80029e2: f7fe fb9d bl 8001120 HAL_CAN_Start(&hcan1); 80029e6: 4804 ldr r0, [pc, #16] ; (80029f8 ) 80029e8: f002 f848 bl 8004a7c HAL_CAN_ActivateNotification(&hcan1, CAN_IT_RX_FIFO0_MSG_PENDING); 80029ec: 2102 movs r1, #2 80029ee: 4802 ldr r0, [pc, #8] ; (80029f8 ) 80029f0: f002 faf0 bl 8004fd4 } 80029f4: bf00 nop 80029f6: bd80 pop {r7, pc} 80029f8: 200000bc .word 0x200000bc 080029fc : void J_SendPacket(uint32_t PGN, uint8_t pri, uint8_t DLC, uint8_t *data){ 80029fc: b580 push {r7, lr} 80029fe: b08c sub sp, #48 ; 0x30 8002a00: af00 add r7, sp, #0 8002a02: 60f8 str r0, [r7, #12] 8002a04: 607b str r3, [r7, #4] 8002a06: 460b mov r3, r1 8002a08: 72fb strb r3, [r7, #11] 8002a0a: 4613 mov r3, r2 8002a0c: 72bb strb r3, [r7, #10] CAN_TxHeaderTypeDef tx_header; uint32_t tx_mailbox; tx_header.ExtId = (pri << 26) | (PGN << 8) | (J_ID_EV << 8) | J_ID_SE; 8002a0e: 7afb ldrb r3, [r7, #11] 8002a10: 069b lsls r3, r3, #26 8002a12: 461a mov r2, r3 8002a14: 68fb ldr r3, [r7, #12] 8002a16: 021b lsls r3, r3, #8 8002a18: 4313 orrs r3, r2 8002a1a: f443 4374 orr.w r3, r3, #62464 ; 0xf400 8002a1e: f043 0356 orr.w r3, r3, #86 ; 0x56 8002a22: 61fb str r3, [r7, #28] tx_header.RTR = CAN_RTR_DATA; 8002a24: 2300 movs r3, #0 8002a26: 627b str r3, [r7, #36] ; 0x24 tx_header.IDE = CAN_ID_EXT; 8002a28: 2304 movs r3, #4 8002a2a: 623b str r3, [r7, #32] tx_header.DLC = DLC; 8002a2c: 7abb ldrb r3, [r7, #10] 8002a2e: 62bb str r3, [r7, #40] ; 0x28 HAL_CAN_AddTxMessage(&hcan1, &tx_header, data, &tx_mailbox); 8002a30: f107 0314 add.w r3, r7, #20 8002a34: f107 0118 add.w r1, r7, #24 8002a38: 687a ldr r2, [r7, #4] 8002a3a: 4803 ldr r0, [pc, #12] ; (8002a48 ) 8002a3c: f002 f8ab bl 8004b96 //HAL_Delay(2); } 8002a40: bf00 nop 8002a42: 3730 adds r7, #48 ; 0x30 8002a44: 46bd mov sp, r7 8002a46: bd80 pop {r7, pc} 8002a48: 200000bc .word 0x200000bc 08002a4c : //void J_SendPacketLong(){ // //TODO (no need) //} // J1939 sequence Clear To Send packet void J_SendCTS(j_receive_t rx){ 8002a4c: b084 sub sp, #16 8002a4e: b580 push {r7, lr} 8002a50: b082 sub sp, #8 8002a52: af00 add r7, sp, #0 8002a54: f107 0c10 add.w ip, r7, #16 8002a58: e88c 000f stmia.w ip, {r0, r1, r2, r3} //if(rx.packets <= rx.packet) return; TODO uint8_t data[8]; data[0] = 17; //CONTROL_BYTE_TP_CM_CTS 8002a5c: 2311 movs r3, #17 8002a5e: 703b strb r3, [r7, #0] data[1] = rx.step;//total_number_of_packages_transmitted 8002a60: f897 3118 ldrb.w r3, [r7, #280] ; 0x118 8002a64: 707b strb r3, [r7, #1] if (rx.step > (rx.packets - rx.packet+1)) data[1] = rx.packets - rx.packet+1; 8002a66: f897 3118 ldrb.w r3, [r7, #280] ; 0x118 8002a6a: 461a mov r2, r3 8002a6c: f897 3116 ldrb.w r3, [r7, #278] ; 0x116 8002a70: 4619 mov r1, r3 8002a72: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8002a76: 1acb subs r3, r1, r3 8002a78: 3301 adds r3, #1 8002a7a: 429a cmp r2, r3 8002a7c: dd08 ble.n 8002a90 8002a7e: f897 2116 ldrb.w r2, [r7, #278] ; 0x116 8002a82: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8002a86: 1ad3 subs r3, r2, r3 8002a88: b2db uxtb r3, r3 8002a8a: 3301 adds r3, #1 8002a8c: b2db uxtb r3, r3 8002a8e: 707b strb r3, [r7, #1] data[2] = rx.packet;//next_packet_number_transmitted 8002a90: f897 3117 ldrb.w r3, [r7, #279] ; 0x117 8002a94: 70bb strb r3, [r7, #2] data[3] = 0xFF; /* Reserved */ 8002a96: 23ff movs r3, #255 ; 0xff 8002a98: 70fb strb r3, [r7, #3] data[4] = 0xFF; 8002a9a: 23ff movs r3, #255 ; 0xff 8002a9c: 713b strb r3, [r7, #4] data[5] = rx.PGN; 8002a9e: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 8002aa2: b2db uxtb r3, r3 8002aa4: 717b strb r3, [r7, #5] data[6] = rx.PGN >> 8; 8002aa6: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 8002aaa: 0a1b lsrs r3, r3, #8 8002aac: b2db uxtb r3, r3 8002aae: 71bb strb r3, [r7, #6] data[7] = rx.PGN >> 16; 8002ab0: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 8002ab4: 0c1b lsrs r3, r3, #16 8002ab6: b2db uxtb r3, r3 8002ab8: 71fb strb r3, [r7, #7] J_SendPacket(0x00EC00, 7, 8, data); 8002aba: 463b mov r3, r7 8002abc: 2208 movs r2, #8 8002abe: 2107 movs r1, #7 8002ac0: f44f 406c mov.w r0, #60416 ; 0xec00 8002ac4: f7ff ff9a bl 80029fc } 8002ac8: bf00 nop 8002aca: 3708 adds r7, #8 8002acc: 46bd mov sp, r7 8002ace: e8bd 4080 ldmia.w sp!, {r7, lr} 8002ad2: b004 add sp, #16 8002ad4: 4770 bx lr ... 08002ad8 : // J1939 sequence ACK packet void J_SendACK(j_receive_t rx){//uint32_t PGN, uint8_t step, uint8_t packet){ 8002ad8: b084 sub sp, #16 8002ada: b580 push {r7, lr} 8002adc: b082 sub sp, #8 8002ade: af00 add r7, sp, #0 8002ae0: f107 0c10 add.w ip, r7, #16 8002ae4: e88c 000f stmia.w ip, {r0, r1, r2, r3} uint8_t data[8]; data[0] = 19; //CONTROL_BYTE_TP_CM_ACK 8002ae8: 2313 movs r3, #19 8002aea: 703b strb r3, [r7, #0] data[1] = j_rx.size; 8002aec: 4b16 ldr r3, [pc, #88] ; (8002b48 ) 8002aee: f8b3 3104 ldrh.w r3, [r3, #260] ; 0x104 8002af2: b2db uxtb r3, r3 8002af4: 707b strb r3, [r7, #1] data[2] = j_rx.size>>8; 8002af6: 4b14 ldr r3, [pc, #80] ; (8002b48 ) 8002af8: f8b3 3104 ldrh.w r3, [r3, #260] ; 0x104 8002afc: 0a1b lsrs r3, r3, #8 8002afe: b29b uxth r3, r3 8002b00: b2db uxtb r3, r3 8002b02: 70bb strb r3, [r7, #2] data[3] = j_rx.packets; 8002b04: 4b10 ldr r3, [pc, #64] ; (8002b48 ) 8002b06: f893 3106 ldrb.w r3, [r3, #262] ; 0x106 8002b0a: 70fb strb r3, [r7, #3] data[4] = 0xFF;//TODO 8002b0c: 23ff movs r3, #255 ; 0xff 8002b0e: 713b strb r3, [r7, #4] data[5] = rx.PGN; 8002b10: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 8002b14: b2db uxtb r3, r3 8002b16: 717b strb r3, [r7, #5] data[6] = rx.PGN >> 8; 8002b18: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 8002b1c: 0a1b lsrs r3, r3, #8 8002b1e: b2db uxtb r3, r3 8002b20: 71bb strb r3, [r7, #6] data[7] = rx.PGN >> 16; 8002b22: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 8002b26: 0c1b lsrs r3, r3, #16 8002b28: b2db uxtb r3, r3 8002b2a: 71fb strb r3, [r7, #7] J_SendPacket(0x00EC00, 7, 8, data); 8002b2c: 463b mov r3, r7 8002b2e: 2208 movs r2, #8 8002b30: 2107 movs r1, #7 8002b32: f44f 406c mov.w r0, #60416 ; 0xec00 8002b36: f7ff ff61 bl 80029fc } 8002b3a: bf00 nop 8002b3c: 3708 adds r7, #8 8002b3e: 46bd mov sp, r7 8002b40: e8bd 4080 ldmia.w sp!, {r7, lr} 8002b44: b004 add sp, #16 8002b46: 4770 bx lr 8002b48: 200002b8 .word 0x200002b8 08002b4c : #define ED_CAN_INSTANCE hcan2 /** * @brief CAN Interrupt Handler for EDCAN (CAN2) * */ void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan){ 8002b4c: b580 push {r7, lr} 8002b4e: b082 sub sp, #8 8002b50: af00 add r7, sp, #0 8002b52: 6078 str r0, [r7, #4] if(HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO1, &RxHeader, RxData) == HAL_OK) 8002b54: 4b18 ldr r3, [pc, #96] ; (8002bb8 ) 8002b56: 4a19 ldr r2, [pc, #100] ; (8002bbc ) 8002b58: 2101 movs r1, #1 8002b5a: 6878 ldr r0, [r7, #4] 8002b5c: f002 f929 bl 8004db2 8002b60: 4603 mov r3, r0 8002b62: 2b00 cmp r3, #0 8002b64: d123 bne.n 8002bae 8002b66: 4b15 ldr r3, [pc, #84] ; (8002bbc ) 8002b68: 685b ldr r3, [r3, #4] { memcpy(&RxFrame.ExtID, &RxHeader.ExtId, sizeof(RxFrame.ExtID)); 8002b6a: 4a15 ldr r2, [pc, #84] ; (8002bc0 ) 8002b6c: 6013 str r3, [r2, #0] RxFrame.DLC = RxHeader.DLC; 8002b6e: 4b13 ldr r3, [pc, #76] ; (8002bbc ) 8002b70: 691b ldr r3, [r3, #16] 8002b72: b2da uxtb r2, r3 8002b74: 4b12 ldr r3, [pc, #72] ; (8002bc0 ) 8002b76: 731a strb r2, [r3, #12] memcpy(RxFrame.data, RxData, RxHeader.DLC); 8002b78: 4b10 ldr r3, [pc, #64] ; (8002bbc ) 8002b7a: 691b ldr r3, [r3, #16] 8002b7c: 461a mov r2, r3 8002b7e: 490e ldr r1, [pc, #56] ; (8002bb8 ) 8002b80: 4810 ldr r0, [pc, #64] ; (8002bc4 ) 8002b82: f004 fe6f bl 8007864 if((RxFrame.ExtID.DestinationID == ED_OwnID) || (RxFrame.ExtID.DestinationID == 0xFF)){ 8002b86: 4b0e ldr r3, [pc, #56] ; (8002bc0 ) 8002b88: 781a ldrb r2, [r3, #0] 8002b8a: 4b0f ldr r3, [pc, #60] ; (8002bc8 ) 8002b8c: 781b ldrb r3, [r3, #0] 8002b8e: 429a cmp r2, r3 8002b90: d003 beq.n 8002b9a 8002b92: 4b0b ldr r3, [pc, #44] ; (8002bc0 ) 8002b94: 781b ldrb r3, [r3, #0] 8002b96: 2bff cmp r3, #255 ; 0xff 8002b98: d109 bne.n 8002bae //Выходим из Silent Mode сразу после получения любого пакета if(silentmode_enable) EDCAN_EnterSilentMode(0); 8002b9a: 4b0c ldr r3, [pc, #48] ; (8002bcc ) 8002b9c: 681b ldr r3, [r3, #0] 8002b9e: 2b00 cmp r3, #0 8002ba0: d002 beq.n 8002ba8 8002ba2: 2000 movs r0, #0 8002ba4: f000 f930 bl 8002e08 EDCAN_RxBufferAdd (&RxFrame); 8002ba8: 4805 ldr r0, [pc, #20] ; (8002bc0 ) 8002baa: f000 fa63 bl 8003074 // EDCAN_ExchangeRxBuffer(); } } } 8002bae: bf00 nop 8002bb0: 3708 adds r7, #8 8002bb2: 46bd mov sp, r7 8002bb4: bd80 pop {r7, pc} 8002bb6: bf00 nop 8002bb8: 200003cc .word 0x200003cc 8002bbc: 200003d4 .word 0x200003d4 8002bc0: 200003f0 .word 0x200003f0 8002bc4: 200003f4 .word 0x200003f4 8002bc8: 200003c8 .word 0x200003c8 8002bcc: 20000404 .word 0x20000404 08002bd0 : #endif void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan){ 8002bd0: b580 push {r7, lr} 8002bd2: b082 sub sp, #8 8002bd4: af00 add r7, sp, #0 8002bd6: 6078 str r0, [r7, #4] if (hcan == &ED_CAN_INSTANCE){ 8002bd8: 687b ldr r3, [r7, #4] 8002bda: 4a04 ldr r2, [pc, #16] ; (8002bec ) 8002bdc: 4293 cmp r3, r2 8002bde: d101 bne.n 8002be4 EDCAN_ExchangeTxBuffer(); 8002be0: f000 f966 bl 8002eb0 } } 8002be4: bf00 nop 8002be6: 3708 adds r7, #8 8002be8: 46bd mov sp, r7 8002bea: bd80 pop {r7, pc} 8002bec: 200000e4 .word 0x200000e4 08002bf0 : void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan){ 8002bf0: b580 push {r7, lr} 8002bf2: b082 sub sp, #8 8002bf4: af00 add r7, sp, #0 8002bf6: 6078 str r0, [r7, #4] if (hcan == &ED_CAN_INSTANCE){ 8002bf8: 687b ldr r3, [r7, #4] 8002bfa: 4a04 ldr r2, [pc, #16] ; (8002c0c ) 8002bfc: 4293 cmp r3, r2 8002bfe: d101 bne.n 8002c04 EDCAN_ExchangeTxBuffer(); 8002c00: f000 f956 bl 8002eb0 } } 8002c04: bf00 nop 8002c06: 3708 adds r7, #8 8002c08: 46bd mov sp, r7 8002c0a: bd80 pop {r7, pc} 8002c0c: 200000e4 .word 0x200000e4 08002c10 : void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan){ 8002c10: b580 push {r7, lr} 8002c12: b082 sub sp, #8 8002c14: af00 add r7, sp, #0 8002c16: 6078 str r0, [r7, #4] if (hcan == &ED_CAN_INSTANCE){ 8002c18: 687b ldr r3, [r7, #4] 8002c1a: 4a04 ldr r2, [pc, #16] ; (8002c2c ) 8002c1c: 4293 cmp r3, r2 8002c1e: d101 bne.n 8002c24 EDCAN_ExchangeTxBuffer(); 8002c20: f000 f946 bl 8002eb0 } } 8002c24: bf00 nop 8002c26: 3708 adds r7, #8 8002c28: 46bd mov sp, r7 8002c2a: bd80 pop {r7, pc} 8002c2c: 200000e4 .word 0x200000e4 08002c30 : /** * @brief EDCAN Initialization function * * @param _OwnID: EDCAN Device ID */ void EDCAN_Init(uint8_t _OwnID){ 8002c30: b480 push {r7} 8002c32: b083 sub sp, #12 8002c34: af00 add r7, sp, #0 8002c36: 4603 mov r3, r0 8002c38: 71fb strb r3, [r7, #7] ED_OwnID = _OwnID; 8002c3a: 4a04 ldr r2, [pc, #16] ; (8002c4c ) 8002c3c: 79fb ldrb r3, [r7, #7] 8002c3e: 7013 strb r3, [r2, #0] }; 8002c40: bf00 nop 8002c42: 370c adds r7, #12 8002c44: 46bd mov sp, r7 8002c46: bc80 pop {r7} 8002c48: 4770 bx lr 8002c4a: bf00 nop 8002c4c: 200003c8 .word 0x200003c8 08002c50 : /** * @brief CAN Reinitialization function * * */ void CAN_ReInit(){ 8002c50: b580 push {r7, lr} 8002c52: af00 add r7, sp, #0 HAL_CAN_Stop(&ED_CAN_INSTANCE); 8002c54: 4807 ldr r0, [pc, #28] ; (8002c74 ) 8002c56: f001 ff55 bl 8004b04 #ifdef ED_CAN1 MX_CAN1_Init(); #endif #ifdef ED_CAN2 MX_CAN2_Init(); 8002c5a: f7fe fa97 bl 800118c #endif EDCAN_FilterInit(); 8002c5e: f000 f80b bl 8002c78 HAL_CAN_Start(&ED_CAN_INSTANCE); 8002c62: 4804 ldr r0, [pc, #16] ; (8002c74 ) 8002c64: f001 ff0a bl 8004a7c #ifdef ED_CAN1 HAL_CAN_ActivateNotification(&ED_CAN_INSTANCE, CAN_IT_RX_FIFO0_MSG_PENDING | /*CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE |*/ CAN_IT_TX_MAILBOX_EMPTY); #endif #ifdef ED_CAN2 HAL_CAN_ActivateNotification(&ED_CAN_INSTANCE, CAN_IT_RX_FIFO1_MSG_PENDING | /*CAN_IT_ERROR | CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE |*/ CAN_IT_TX_MAILBOX_EMPTY); 8002c68: 2111 movs r1, #17 8002c6a: 4802 ldr r0, [pc, #8] ; (8002c74 ) 8002c6c: f002 f9b2 bl 8004fd4 #endif } 8002c70: bf00 nop 8002c72: bd80 pop {r7, pc} 8002c74: 200000e4 .word 0x200000e4 08002c78 : * * @param _OwnID: EDCAN Device ID * * @retval HAL status */ void EDCAN_FilterInit(){ 8002c78: b580 push {r7, lr} 8002c7a: b08a sub sp, #40 ; 0x28 8002c7c: af00 add r7, sp, #0 CAN_FilterTypeDef sFilterConfig; //Filter for Own ID sFilterConfig.FilterBank = 0; 8002c7e: 2300 movs r3, #0 8002c80: 617b str r3, [r7, #20] sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; 8002c82: 2300 movs r3, #0 8002c84: 61bb str r3, [r7, #24] sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; 8002c86: 2301 movs r3, #1 8002c88: 61fb str r3, [r7, #28] sFilterConfig.FilterIdHigh = 0x0000; 8002c8a: 2300 movs r3, #0 8002c8c: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = (uint16_t)(ED_OwnID<<3)|0b100; 8002c8e: 4b21 ldr r3, [pc, #132] ; (8002d14 ) 8002c90: 781b ldrb r3, [r3, #0] 8002c92: b29b uxth r3, r3 8002c94: 00db lsls r3, r3, #3 8002c96: b29b uxth r3, r3 8002c98: f043 0304 orr.w r3, r3, #4 8002c9c: b29b uxth r3, r3 8002c9e: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 8002ca0: 2300 movs r3, #0 8002ca2: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = (uint16_t)(0xFF<<3)|0b100; 8002ca4: f240 73fc movw r3, #2044 ; 0x7fc 8002ca8: 60fb str r3, [r7, #12] sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; 8002caa: 2300 movs r3, #0 8002cac: 613b str r3, [r7, #16] sFilterConfig.FilterActivation = ENABLE; 8002cae: 2301 movs r3, #1 8002cb0: 623b str r3, [r7, #32] #ifdef ED_CAN2 sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; 8002cb2: 2301 movs r3, #1 8002cb4: 613b str r3, [r7, #16] sFilterConfig.SlaveStartFilterBank = 14; 8002cb6: 230e movs r3, #14 8002cb8: 627b str r3, [r7, #36] ; 0x24 sFilterConfig.FilterBank = 14; 8002cba: 230e movs r3, #14 8002cbc: 617b str r3, [r7, #20] #endif if(HAL_CAN_ConfigFilter(&ED_CAN_INSTANCE, &sFilterConfig) != HAL_OK){ 8002cbe: 463b mov r3, r7 8002cc0: 4619 mov r1, r3 8002cc2: 4815 ldr r0, [pc, #84] ; (8002d18 ) 8002cc4: f001 fdfa bl 80048bc 8002cc8: 4603 mov r3, r0 8002cca: 2b00 cmp r3, #0 8002ccc: d001 beq.n 8002cd2 Error_Handler(); 8002cce: f000 fc77 bl 80035c0 } // Filter for broadcast ID sFilterConfig.FilterBank = 1; 8002cd2: 2301 movs r3, #1 8002cd4: 617b str r3, [r7, #20] sFilterConfig.FilterIdHigh = 0x0000; 8002cd6: 2300 movs r3, #0 8002cd8: 603b str r3, [r7, #0] sFilterConfig.FilterIdLow = (uint16_t)(0xFF<<3)|0b100; 8002cda: f240 73fc movw r3, #2044 ; 0x7fc 8002cde: 607b str r3, [r7, #4] sFilterConfig.FilterMaskIdHigh = 0x0000; 8002ce0: 2300 movs r3, #0 8002ce2: 60bb str r3, [r7, #8] sFilterConfig.FilterMaskIdLow = (uint16_t)(0xFF<<3)|0b100; 8002ce4: f240 73fc movw r3, #2044 ; 0x7fc 8002ce8: 60fb str r3, [r7, #12] #ifdef ED_CAN2 sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO1; 8002cea: 2301 movs r3, #1 8002cec: 613b str r3, [r7, #16] sFilterConfig.SlaveStartFilterBank = 14; 8002cee: 230e movs r3, #14 8002cf0: 627b str r3, [r7, #36] ; 0x24 sFilterConfig.FilterBank = 15; 8002cf2: 230f movs r3, #15 8002cf4: 617b str r3, [r7, #20] #endif if(HAL_CAN_ConfigFilter(&ED_CAN_INSTANCE, &sFilterConfig) != HAL_OK) 8002cf6: 463b mov r3, r7 8002cf8: 4619 mov r1, r3 8002cfa: 4807 ldr r0, [pc, #28] ; (8002d18 ) 8002cfc: f001 fdde bl 80048bc 8002d00: 4603 mov r3, r0 8002d02: 2b00 cmp r3, #0 8002d04: d001 beq.n 8002d0a { Error_Handler(); 8002d06: f000 fc5b bl 80035c0 } } 8002d0a: bf00 nop 8002d0c: 3728 adds r7, #40 ; 0x28 8002d0e: 46bd mov sp, r7 8002d10: bd80 pop {r7, pc} 8002d12: bf00 nop 8002d14: 200003c8 .word 0x200003c8 8002d18: 200000e4 .word 0x200000e4 08002d1c : * @param DestinationID: Packet Destination ID * @param RegAddr: First register address in sequence * @param *data: pointer to data array to be send * @param len: length of data (1..8) */ void EDCAN_SendPacketRead(uint8_t DestinationID, uint16_t RegAddr, uint8_t *data, uint8_t len){ 8002d1c: b580 push {r7, lr} 8002d1e: b08c sub sp, #48 ; 0x30 8002d20: af00 add r7, sp, #0 8002d22: 603a str r2, [r7, #0] 8002d24: 461a mov r2, r3 8002d26: 4603 mov r3, r0 8002d28: 71fb strb r3, [r7, #7] 8002d2a: 460b mov r3, r1 8002d2c: 80bb strh r3, [r7, #4] 8002d2e: 4613 mov r3, r2 8002d30: 71bb strb r3, [r7, #6] EDCAN_TxFrame_t tx_frame; EDCAN_frameId_t ExtID; //CAN_TxHeaderTypeDef tx_header; //uint32_t tx_mailbox; ExtID.DestinationID = DestinationID; 8002d32: 79fb ldrb r3, [r7, #7] 8002d34: 733b strb r3, [r7, #12] ExtID.SourceID = ED_OwnID; 8002d36: 4b15 ldr r3, [pc, #84] ; (8002d8c ) 8002d38: 781b ldrb r3, [r3, #0] 8002d3a: 737b strb r3, [r7, #13] ExtID.RegisterAddress = RegAddr; 8002d3c: 88bb ldrh r3, [r7, #4] 8002d3e: f3c3 030a ubfx r3, r3, #0, #11 8002d42: b29a uxth r2, r3 8002d44: 89fb ldrh r3, [r7, #14] 8002d46: f362 030a bfi r3, r2, #0, #11 8002d4a: 81fb strh r3, [r7, #14] ExtID.PacketType = ED_READ; 8002d4c: 7bfb ldrb r3, [r7, #15] 8002d4e: 2202 movs r2, #2 8002d50: f362 03c4 bfi r3, r2, #3, #2 8002d54: 73fb strb r3, [r7, #15] 8002d56: 68fb ldr r3, [r7, #12] memcpy(&tx_frame.tx_header.ExtId, &ExtID, sizeof(ExtID)); 8002d58: 617b str r3, [r7, #20] tx_frame.tx_header.RTR = CAN_RTR_DATA; 8002d5a: 2300 movs r3, #0 8002d5c: 61fb str r3, [r7, #28] tx_frame.tx_header.IDE = CAN_ID_EXT; 8002d5e: 2304 movs r3, #4 8002d60: 61bb str r3, [r7, #24] tx_frame.tx_header.DLC = len; 8002d62: 79bb ldrb r3, [r7, #6] 8002d64: 623b str r3, [r7, #32] memcpy(&tx_frame.data, data, len); 8002d66: 79ba ldrb r2, [r7, #6] 8002d68: f107 0310 add.w r3, r7, #16 8002d6c: 3318 adds r3, #24 8002d6e: 6839 ldr r1, [r7, #0] 8002d70: 4618 mov r0, r3 8002d72: f004 fd77 bl 8007864 //EDCAN_AddTxMessage(&ED_CAN_INSTANCE, &tx_header, data, &tx_mailbox); //Добавление пакета в буфер EDCAN_TxBufferAdd(&tx_frame); 8002d76: f107 0310 add.w r3, r7, #16 8002d7a: 4618 mov r0, r3 8002d7c: f000 f8de bl 8002f3c //Также, попытаемся сразу перенести пакет в CAN (если там есть свободное место) //Если свободного места нету, то пакет перенесется в CAN позже по прерыванию освобождения буфера EDCAN_ExchangeTxBuffer(); 8002d80: f000 f896 bl 8002eb0 } 8002d84: bf00 nop 8002d86: 3730 adds r7, #48 ; 0x30 8002d88: 46bd mov sp, r7 8002d8a: bd80 pop {r7, pc} 8002d8c: 200003c8 .word 0x200003c8 08002d90 : /** * @brief EDCAN loop function * Функция для управления буферами, должна быть в while(1) * */ void EDCAN_Loop(){ 8002d90: b580 push {r7, lr} 8002d92: af00 add r7, sp, #0 //Функция переинициализации пока что не используется // if(can_error){ // CAN_ReInit(); // can_error=0; // } if(silentmode_enable){ 8002d94: 4b19 ldr r3, [pc, #100] ; (8002dfc ) 8002d96: 681b ldr r3, [r3, #0] 8002d98: 2b00 cmp r3, #0 8002d9a: d00c beq.n 8002db6 if(silentmode_time < HAL_GetTick()){ 8002d9c: f000 ff60 bl 8003c60 8002da0: 4602 mov r2, r0 8002da2: 4b17 ldr r3, [pc, #92] ; (8002e00 ) 8002da4: 681b ldr r3, [r3, #0] 8002da6: 429a cmp r2, r3 8002da8: d905 bls.n 8002db6 silentmode_enable = 0; 8002daa: 4b14 ldr r3, [pc, #80] ; (8002dfc ) 8002dac: 2200 movs r2, #0 8002dae: 601a str r2, [r3, #0] EDCAN_SetSilentMode(0); 8002db0: 2000 movs r0, #0 8002db2: f000 f857 bl 8002e64 } } //every 2ms exchange buffer if (HAL_GetTick() > lasttxexchangetime){ 8002db6: f000 ff53 bl 8003c60 8002dba: 4602 mov r2, r0 8002dbc: 4b11 ldr r3, [pc, #68] ; (8002e04 ) 8002dbe: 681b ldr r3, [r3, #0] 8002dc0: 429a cmp r2, r3 8002dc2: d90c bls.n 8002dde if(EDCAN_getTxBufferElementCount()>0){ 8002dc4: f000 f900 bl 8002fc8 8002dc8: 4603 mov r3, r0 8002dca: 2b00 cmp r3, #0 8002dcc: d007 beq.n 8002dde lasttxexchangetime = HAL_GetTick() + 1; 8002dce: f000 ff47 bl 8003c60 8002dd2: 4603 mov r3, r0 8002dd4: 3301 adds r3, #1 8002dd6: 4a0b ldr r2, [pc, #44] ; (8002e04 ) 8002dd8: 6013 str r3, [r2, #0] EDCAN_ExchangeTxBuffer(); 8002dda: f000 f869 bl 8002eb0 } } //exchange buffer // if (HAL_GetTick() > lastrxexchangetime){ if((EDCAN_getRxBufferElementCount()>0)&&(EDCAN_getTxBufferElementCount()<200)){ 8002dde: f000 f9c5 bl 800316c 8002de2: 4603 mov r3, r0 8002de4: 2b00 cmp r3, #0 8002de6: d006 beq.n 8002df6 8002de8: f000 f8ee bl 8002fc8 8002dec: 4603 mov r3, r0 8002dee: 2bc7 cmp r3, #199 ; 0xc7 8002df0: d801 bhi.n 8002df6 // lastrxexchangetime = HAL_GetTick() + 1; EDCAN_ExchangeRxBuffer(); 8002df2: f000 f9c7 bl 8003184 } // } } 8002df6: bf00 nop 8002df8: bd80 pop {r7, pc} 8002dfa: bf00 nop 8002dfc: 20000404 .word 0x20000404 8002e00: 20000400 .word 0x20000400 8002e04: 20000408 .word 0x20000408 08002e08 : //функция установки таймера для входа в Silent режим //По истечении времени time выход из режима silent //если time = 0, выход из режима silent и сброс таймера void EDCAN_EnterSilentMode(uint8_t time){ 8002e08: b580 push {r7, lr} 8002e0a: b082 sub sp, #8 8002e0c: af00 add r7, sp, #0 8002e0e: 4603 mov r3, r0 8002e10: 71fb strb r3, [r7, #7] if(time==0){ 8002e12: 79fb ldrb r3, [r7, #7] 8002e14: 2b00 cmp r3, #0 8002e16: d10b bne.n 8002e30 EDCAN_SetSilentMode(0); 8002e18: 2000 movs r0, #0 8002e1a: f000 f823 bl 8002e64 silentmode_time = HAL_GetTick(); 8002e1e: f000 ff1f bl 8003c60 8002e22: 4603 mov r3, r0 8002e24: 4a0d ldr r2, [pc, #52] ; (8002e5c ) 8002e26: 6013 str r3, [r2, #0] silentmode_enable = 0; 8002e28: 4b0d ldr r3, [pc, #52] ; (8002e60 ) 8002e2a: 2200 movs r2, #0 8002e2c: 601a str r2, [r3, #0] }else{ EDCAN_SetSilentMode(1); silentmode_time = HAL_GetTick()+((uint32_t)time * 1000); silentmode_enable = 1; } } 8002e2e: e010 b.n 8002e52 EDCAN_SetSilentMode(1); 8002e30: 2001 movs r0, #1 8002e32: f000 f817 bl 8002e64 silentmode_time = HAL_GetTick()+((uint32_t)time * 1000); 8002e36: f000 ff13 bl 8003c60 8002e3a: 4602 mov r2, r0 8002e3c: 79fb ldrb r3, [r7, #7] 8002e3e: f44f 717a mov.w r1, #1000 ; 0x3e8 8002e42: fb01 f303 mul.w r3, r1, r3 8002e46: 4413 add r3, r2 8002e48: 4a04 ldr r2, [pc, #16] ; (8002e5c ) 8002e4a: 6013 str r3, [r2, #0] silentmode_enable = 1; 8002e4c: 4b04 ldr r3, [pc, #16] ; (8002e60 ) 8002e4e: 2201 movs r2, #1 8002e50: 601a str r2, [r3, #0] } 8002e52: bf00 nop 8002e54: 3708 adds r7, #8 8002e56: 46bd mov sp, r7 8002e58: bd80 pop {r7, pc} 8002e5a: bf00 nop 8002e5c: 20000400 .word 0x20000400 8002e60: 20000404 .word 0x20000404 08002e64 : //Функция входа в Silent Режим void EDCAN_SetSilentMode(uint8_t state){ 8002e64: b580 push {r7, lr} 8002e66: b082 sub sp, #8 8002e68: af00 add r7, sp, #0 8002e6a: 4603 mov r3, r0 8002e6c: 71fb strb r3, [r7, #7] HAL_CAN_Stop(&ED_CAN_INSTANCE); 8002e6e: 480f ldr r0, [pc, #60] ; (8002eac ) 8002e70: f001 fe48 bl 8004b04 if(state){ 8002e74: 79fb ldrb r3, [r7, #7] 8002e76: 2b00 cmp r3, #0 8002e78: d008 beq.n 8002e8c ED_CAN_INSTANCE.Instance->BTR |= CAN_MODE_SILENT; 8002e7a: 4b0c ldr r3, [pc, #48] ; (8002eac ) 8002e7c: 681b ldr r3, [r3, #0] 8002e7e: 69da ldr r2, [r3, #28] 8002e80: 4b0a ldr r3, [pc, #40] ; (8002eac ) 8002e82: 681b ldr r3, [r3, #0] 8002e84: f042 4200 orr.w r2, r2, #2147483648 ; 0x80000000 8002e88: 61da str r2, [r3, #28] 8002e8a: e007 b.n 8002e9c }else{ ED_CAN_INSTANCE.Instance->BTR &= ~CAN_MODE_SILENT; 8002e8c: 4b07 ldr r3, [pc, #28] ; (8002eac ) 8002e8e: 681b ldr r3, [r3, #0] 8002e90: 69da ldr r2, [r3, #28] 8002e92: 4b06 ldr r3, [pc, #24] ; (8002eac ) 8002e94: 681b ldr r3, [r3, #0] 8002e96: f022 4200 bic.w r2, r2, #2147483648 ; 0x80000000 8002e9a: 61da str r2, [r3, #28] } HAL_CAN_Start(&ED_CAN_INSTANCE); 8002e9c: 4803 ldr r0, [pc, #12] ; (8002eac ) 8002e9e: f001 fded bl 8004a7c } 8002ea2: bf00 nop 8002ea4: 3708 adds r7, #8 8002ea6: 46bd mov sp, r7 8002ea8: bd80 pop {r7, pc} 8002eaa: bf00 nop 8002eac: 200000e4 .word 0x200000e4 08002eb0 : // Инициализация глобальных буферов TxCircularBuffer_t txBuffer = { .head = 0, .tail = 0, .count = 0 }; RxCircularBuffer_t rxBuffer = { .head = 0, .tail = 0, .count = 0 }; //Функция для передачи данных из буфера в mailbox CAN шины void EDCAN_ExchangeTxBuffer(){ 8002eb0: b580 push {r7, lr} 8002eb2: b08a sub sp, #40 ; 0x28 8002eb4: af00 add r7, sp, #0 EDCAN_TxFrame_t TxFrame; uint32_t tx_mailbox; HAL_StatusTypeDef CAN_result; //если в буфере что-то есть и есть свободные Mailbox if((EDCAN_getTxBufferElementCount()>0) && (HAL_CAN_GetTxMailboxesFreeLevel(&ED_CAN_INSTANCE) > 0)){ 8002eb6: f000 f887 bl 8002fc8 8002eba: 4603 mov r3, r0 8002ebc: 2b00 cmp r3, #0 8002ebe: d034 beq.n 8002f2a 8002ec0: 481b ldr r0, [pc, #108] ; (8002f30 ) 8002ec2: f001 ff42 bl 8004d4a 8002ec6: 4603 mov r3, r0 8002ec8: 2b00 cmp r3, #0 8002eca: d02e beq.n 8002f2a EDCAN_TxBufferPeekFirst(&TxFrame); //Извлечь первый элемент буфера 8002ecc: 1d3b adds r3, r7, #4 8002ece: 4618 mov r0, r3 8002ed0: f000 f886 bl 8002fe0 /* отправка сообщения */ CAN_result = HAL_CAN_AddTxMessage(&ED_CAN_INSTANCE, &TxFrame.tx_header, TxFrame.data, &tx_mailbox); 8002ed4: 4638 mov r0, r7 8002ed6: 1d3b adds r3, r7, #4 8002ed8: f103 0218 add.w r2, r3, #24 8002edc: 1d39 adds r1, r7, #4 8002ede: 4603 mov r3, r0 8002ee0: 4813 ldr r0, [pc, #76] ; (8002f30 ) 8002ee2: f001 fe58 bl 8004b96 8002ee6: 4603 mov r3, r0 8002ee8: f887 3027 strb.w r3, [r7, #39] ; 0x27 /* если отправка удалась, выход */ if(CAN_result == HAL_OK) { 8002eec: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 8002ef0: 2b00 cmp r3, #0 8002ef2: d102 bne.n 8002efa //Удаление элемента буфера в случае успешной передачи EDCAN_TxBufferRemoveFirst(); 8002ef4: f000 f894 bl 8003020 8002ef8: e017 b.n 8002f2a //TODO: retry counter management //HAL_Delay(1); //retry_counter--; /* если ошибка, обработка ошибки */ if(CAN_result == HAL_ERROR) { 8002efa: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 8002efe: 2b01 cmp r3, #1 8002f00: d113 bne.n 8002f2a if(ED_CAN_INSTANCE.ErrorCode & HAL_CAN_ERROR_NOT_INITIALIZED) { 8002f02: 4b0b ldr r3, [pc, #44] ; (8002f30 ) 8002f04: 6a5b ldr r3, [r3, #36] ; 0x24 8002f06: f403 2380 and.w r3, r3, #262144 ; 0x40000 8002f0a: 2b00 cmp r3, #0 8002f0c: d004 beq.n 8002f18 CAN_ReInit(); //CAN не инициализирован, переинициализация 8002f0e: f7ff fe9f bl 8002c50 printf("CAN Reinit\n"); 8002f12: 4808 ldr r0, [pc, #32] ; (8002f34 ) 8002f14: f004 fe1e bl 8007b54 } //if(ED_CAN_INSTANCE.ErrorCode & HAL_CAN_ERROR_PARAM) printf("tx full\n"); printf("CAN.ErrorCode = %d\n",(int)ED_CAN_INSTANCE.ErrorCode); 8002f18: 4b05 ldr r3, [pc, #20] ; (8002f30 ) 8002f1a: 6a5b ldr r3, [r3, #36] ; 0x24 8002f1c: 4619 mov r1, r3 8002f1e: 4806 ldr r0, [pc, #24] ; (8002f38 ) 8002f20: f004 fd92 bl 8007a48 ED_CAN_INSTANCE.ErrorCode = 0; //Clear errors 8002f24: 4b02 ldr r3, [pc, #8] ; (8002f30 ) 8002f26: 2200 movs r2, #0 8002f28: 625a str r2, [r3, #36] ; 0x24 } } } 8002f2a: 3728 adds r7, #40 ; 0x28 8002f2c: 46bd mov sp, r7 8002f2e: bd80 pop {r7, pc} 8002f30: 200000e4 .word 0x200000e4 8002f34: 08008d7c .word 0x08008d7c 8002f38: 08008d88 .word 0x08008d88 08002f3c : // Добавление элемента в буфер void EDCAN_TxBufferAdd(EDCAN_TxFrame_t *frame) { 8002f3c: b580 push {r7, lr} 8002f3e: b082 sub sp, #8 8002f40: af00 add r7, sp, #0 8002f42: 6078 str r0, [r7, #4] memcpy(&txBuffer.buffer[txBuffer.head], frame, sizeof(EDCAN_TxFrame_t)); 8002f44: 4b1f ldr r3, [pc, #124] ; (8002fc4 ) 8002f46: f503 5300 add.w r3, r3, #8192 ; 0x2000 8002f4a: 881b ldrh r3, [r3, #0] 8002f4c: 015b lsls r3, r3, #5 8002f4e: 4a1d ldr r2, [pc, #116] ; (8002fc4 ) 8002f50: 4413 add r3, r2 8002f52: 2220 movs r2, #32 8002f54: 6879 ldr r1, [r7, #4] 8002f56: 4618 mov r0, r3 8002f58: f004 fc84 bl 8007864 txBuffer.head = (txBuffer.head + 1) % BUFFER_SIZE; 8002f5c: 4b19 ldr r3, [pc, #100] ; (8002fc4 ) 8002f5e: f503 5300 add.w r3, r3, #8192 ; 0x2000 8002f62: 881b ldrh r3, [r3, #0] 8002f64: 3301 adds r3, #1 8002f66: 425a negs r2, r3 8002f68: b2db uxtb r3, r3 8002f6a: b2d2 uxtb r2, r2 8002f6c: bf58 it pl 8002f6e: 4253 negpl r3, r2 8002f70: b29a uxth r2, r3 8002f72: 4b14 ldr r3, [pc, #80] ; (8002fc4 ) 8002f74: f503 5300 add.w r3, r3, #8192 ; 0x2000 8002f78: 801a strh r2, [r3, #0] if (txBuffer.count == BUFFER_SIZE) { 8002f7a: 4b12 ldr r3, [pc, #72] ; (8002fc4 ) 8002f7c: f503 5300 add.w r3, r3, #8192 ; 0x2000 8002f80: 889b ldrh r3, [r3, #4] 8002f82: f5b3 7f80 cmp.w r3, #256 ; 0x100 8002f86: d10f bne.n 8002fa8 txBuffer.tail = (txBuffer.tail + 1) % BUFFER_SIZE; // Перезапись старых данных 8002f88: 4b0e ldr r3, [pc, #56] ; (8002fc4 ) 8002f8a: f503 5300 add.w r3, r3, #8192 ; 0x2000 8002f8e: 885b ldrh r3, [r3, #2] 8002f90: 3301 adds r3, #1 8002f92: 425a negs r2, r3 8002f94: b2db uxtb r3, r3 8002f96: b2d2 uxtb r2, r2 8002f98: bf58 it pl 8002f9a: 4253 negpl r3, r2 8002f9c: b29a uxth r2, r3 8002f9e: 4b09 ldr r3, [pc, #36] ; (8002fc4 ) 8002fa0: f503 5300 add.w r3, r3, #8192 ; 0x2000 8002fa4: 805a strh r2, [r3, #2] } else { txBuffer.count++; } } 8002fa6: e009 b.n 8002fbc txBuffer.count++; 8002fa8: 4b06 ldr r3, [pc, #24] ; (8002fc4 ) 8002faa: f503 5300 add.w r3, r3, #8192 ; 0x2000 8002fae: 889b ldrh r3, [r3, #4] 8002fb0: 3301 adds r3, #1 8002fb2: b29a uxth r2, r3 8002fb4: 4b03 ldr r3, [pc, #12] ; (8002fc4 ) 8002fb6: f503 5300 add.w r3, r3, #8192 ; 0x2000 8002fba: 809a strh r2, [r3, #4] } 8002fbc: bf00 nop 8002fbe: 3708 adds r7, #8 8002fc0: 46bd mov sp, r7 8002fc2: bd80 pop {r7, pc} 8002fc4: 2000040c .word 0x2000040c 08002fc8 : return false; } } //Количество элементов в буфере uint16_t EDCAN_getTxBufferElementCount() { 8002fc8: b480 push {r7} 8002fca: af00 add r7, sp, #0 return txBuffer.count; 8002fcc: 4b03 ldr r3, [pc, #12] ; (8002fdc ) 8002fce: f503 5300 add.w r3, r3, #8192 ; 0x2000 8002fd2: 889b ldrh r3, [r3, #4] } 8002fd4: 4618 mov r0, r3 8002fd6: 46bd mov sp, r7 8002fd8: bc80 pop {r7} 8002fda: 4770 bx lr 8002fdc: 2000040c .word 0x2000040c 08002fe0 : // функция для получения первого элемента без удаления его из буфера bool EDCAN_TxBufferPeekFirst(EDCAN_TxFrame_t *frame) { 8002fe0: b580 push {r7, lr} 8002fe2: b082 sub sp, #8 8002fe4: af00 add r7, sp, #0 8002fe6: 6078 str r0, [r7, #4] if (txBuffer.count > 0) { 8002fe8: 4b0c ldr r3, [pc, #48] ; (800301c ) 8002fea: f503 5300 add.w r3, r3, #8192 ; 0x2000 8002fee: 889b ldrh r3, [r3, #4] 8002ff0: 2b00 cmp r3, #0 8002ff2: d00d beq.n 8003010 memcpy(frame, &txBuffer.buffer[txBuffer.tail], sizeof(EDCAN_TxFrame_t)); 8002ff4: 4b09 ldr r3, [pc, #36] ; (800301c ) 8002ff6: f503 5300 add.w r3, r3, #8192 ; 0x2000 8002ffa: 885b ldrh r3, [r3, #2] 8002ffc: 015b lsls r3, r3, #5 8002ffe: 4a07 ldr r2, [pc, #28] ; (800301c ) 8003000: 4413 add r3, r2 8003002: 2220 movs r2, #32 8003004: 4619 mov r1, r3 8003006: 6878 ldr r0, [r7, #4] 8003008: f004 fc2c bl 8007864 return true; 800300c: 2301 movs r3, #1 800300e: e000 b.n 8003012 } else { // Буфер пуст, можно добавить обработку ошибки return false; 8003010: 2300 movs r3, #0 } } 8003012: 4618 mov r0, r3 8003014: 3708 adds r7, #8 8003016: 46bd mov sp, r7 8003018: bd80 pop {r7, pc} 800301a: bf00 nop 800301c: 2000040c .word 0x2000040c 08003020 : // функция для удаления первого элемента из буфера bool EDCAN_TxBufferRemoveFirst() { 8003020: b480 push {r7} 8003022: af00 add r7, sp, #0 if (txBuffer.count > 0) { 8003024: 4b12 ldr r3, [pc, #72] ; (8003070 ) 8003026: f503 5300 add.w r3, r3, #8192 ; 0x2000 800302a: 889b ldrh r3, [r3, #4] 800302c: 2b00 cmp r3, #0 800302e: d01a beq.n 8003066 txBuffer.tail = (txBuffer.tail + 1) % BUFFER_SIZE; 8003030: 4b0f ldr r3, [pc, #60] ; (8003070 ) 8003032: f503 5300 add.w r3, r3, #8192 ; 0x2000 8003036: 885b ldrh r3, [r3, #2] 8003038: 3301 adds r3, #1 800303a: 425a negs r2, r3 800303c: b2db uxtb r3, r3 800303e: b2d2 uxtb r2, r2 8003040: bf58 it pl 8003042: 4253 negpl r3, r2 8003044: b29a uxth r2, r3 8003046: 4b0a ldr r3, [pc, #40] ; (8003070 ) 8003048: f503 5300 add.w r3, r3, #8192 ; 0x2000 800304c: 805a strh r2, [r3, #2] txBuffer.count--; 800304e: 4b08 ldr r3, [pc, #32] ; (8003070 ) 8003050: f503 5300 add.w r3, r3, #8192 ; 0x2000 8003054: 889b ldrh r3, [r3, #4] 8003056: 3b01 subs r3, #1 8003058: b29a uxth r2, r3 800305a: 4b05 ldr r3, [pc, #20] ; (8003070 ) 800305c: f503 5300 add.w r3, r3, #8192 ; 0x2000 8003060: 809a strh r2, [r3, #4] return true; 8003062: 2301 movs r3, #1 8003064: e000 b.n 8003068 } else { // Буфер пуст, можно добавить обработку ошибки return false; 8003066: 2300 movs r3, #0 } } 8003068: 4618 mov r0, r3 800306a: 46bd mov sp, r7 800306c: bc80 pop {r7} 800306e: 4770 bx lr 8003070: 2000040c .word 0x2000040c 08003074 : // Функции работы с Rx буфером void EDCAN_RxBufferAdd(EDCAN_RxFrame_t *frame) { 8003074: b580 push {r7, lr} 8003076: b082 sub sp, #8 8003078: af00 add r7, sp, #0 800307a: 6078 str r0, [r7, #4] memcpy(&rxBuffer.buffer[rxBuffer.head], frame, sizeof(EDCAN_RxFrame_t)); 800307c: 4b1e ldr r3, [pc, #120] ; (80030f8 ) 800307e: f8b3 3d00 ldrh.w r3, [r3, #3328] ; 0xd00 8003082: 461a mov r2, r3 8003084: 4613 mov r3, r2 8003086: 005b lsls r3, r3, #1 8003088: 4413 add r3, r2 800308a: 009b lsls r3, r3, #2 800308c: 4413 add r3, r2 800308e: 4a1a ldr r2, [pc, #104] ; (80030f8 ) 8003090: 4413 add r3, r2 8003092: 220d movs r2, #13 8003094: 6879 ldr r1, [r7, #4] 8003096: 4618 mov r0, r3 8003098: f004 fbe4 bl 8007864 rxBuffer.head = (rxBuffer.head + 1) % BUFFER_SIZE; 800309c: 4b16 ldr r3, [pc, #88] ; (80030f8 ) 800309e: f8b3 3d00 ldrh.w r3, [r3, #3328] ; 0xd00 80030a2: 3301 adds r3, #1 80030a4: 425a negs r2, r3 80030a6: b2db uxtb r3, r3 80030a8: b2d2 uxtb r2, r2 80030aa: bf58 it pl 80030ac: 4253 negpl r3, r2 80030ae: b29a uxth r2, r3 80030b0: 4b11 ldr r3, [pc, #68] ; (80030f8 ) 80030b2: f8a3 2d00 strh.w r2, [r3, #3328] ; 0xd00 if (rxBuffer.count == BUFFER_SIZE) { 80030b6: 4b10 ldr r3, [pc, #64] ; (80030f8 ) 80030b8: f8b3 3d04 ldrh.w r3, [r3, #3332] ; 0xd04 80030bc: f5b3 7f80 cmp.w r3, #256 ; 0x100 80030c0: d10d bne.n 80030de rxBuffer.tail = (rxBuffer.tail + 1) % BUFFER_SIZE; // Перезапись старых данных 80030c2: 4b0d ldr r3, [pc, #52] ; (80030f8 ) 80030c4: f8b3 3d02 ldrh.w r3, [r3, #3330] ; 0xd02 80030c8: 3301 adds r3, #1 80030ca: 425a negs r2, r3 80030cc: b2db uxtb r3, r3 80030ce: b2d2 uxtb r2, r2 80030d0: bf58 it pl 80030d2: 4253 negpl r3, r2 80030d4: b29a uxth r2, r3 80030d6: 4b08 ldr r3, [pc, #32] ; (80030f8 ) 80030d8: f8a3 2d02 strh.w r2, [r3, #3330] ; 0xd02 } else { rxBuffer.count++; } } 80030dc: e007 b.n 80030ee rxBuffer.count++; 80030de: 4b06 ldr r3, [pc, #24] ; (80030f8 ) 80030e0: f8b3 3d04 ldrh.w r3, [r3, #3332] ; 0xd04 80030e4: 3301 adds r3, #1 80030e6: b29a uxth r2, r3 80030e8: 4b03 ldr r3, [pc, #12] ; (80030f8 ) 80030ea: f8a3 2d04 strh.w r2, [r3, #3332] ; 0xd04 } 80030ee: bf00 nop 80030f0: 3708 adds r7, #8 80030f2: 46bd mov sp, r7 80030f4: bd80 pop {r7, pc} 80030f6: bf00 nop 80030f8: 20002414 .word 0x20002414 080030fc : //Извлечь и удалить первый элемент буфера bool EDCAN_RxBufferGet(EDCAN_RxFrame_t *frame) { 80030fc: b580 push {r7, lr} 80030fe: b082 sub sp, #8 8003100: af00 add r7, sp, #0 8003102: 6078 str r0, [r7, #4] if (rxBuffer.count > 0) { 8003104: 4b18 ldr r3, [pc, #96] ; (8003168 ) 8003106: f8b3 3d04 ldrh.w r3, [r3, #3332] ; 0xd04 800310a: 2b00 cmp r3, #0 800310c: d026 beq.n 800315c memcpy(frame, &rxBuffer.buffer[rxBuffer.tail], sizeof(EDCAN_RxFrame_t)); 800310e: 4b16 ldr r3, [pc, #88] ; (8003168 ) 8003110: f8b3 3d02 ldrh.w r3, [r3, #3330] ; 0xd02 8003114: 461a mov r2, r3 8003116: 4613 mov r3, r2 8003118: 005b lsls r3, r3, #1 800311a: 4413 add r3, r2 800311c: 009b lsls r3, r3, #2 800311e: 4413 add r3, r2 8003120: 4a11 ldr r2, [pc, #68] ; (8003168 ) 8003122: 4413 add r3, r2 8003124: 220d movs r2, #13 8003126: 4619 mov r1, r3 8003128: 6878 ldr r0, [r7, #4] 800312a: f004 fb9b bl 8007864 rxBuffer.tail = (rxBuffer.tail + 1) % BUFFER_SIZE; 800312e: 4b0e ldr r3, [pc, #56] ; (8003168 ) 8003130: f8b3 3d02 ldrh.w r3, [r3, #3330] ; 0xd02 8003134: 3301 adds r3, #1 8003136: 425a negs r2, r3 8003138: b2db uxtb r3, r3 800313a: b2d2 uxtb r2, r2 800313c: bf58 it pl 800313e: 4253 negpl r3, r2 8003140: b29a uxth r2, r3 8003142: 4b09 ldr r3, [pc, #36] ; (8003168 ) 8003144: f8a3 2d02 strh.w r2, [r3, #3330] ; 0xd02 rxBuffer.count--; 8003148: 4b07 ldr r3, [pc, #28] ; (8003168 ) 800314a: f8b3 3d04 ldrh.w r3, [r3, #3332] ; 0xd04 800314e: 3b01 subs r3, #1 8003150: b29a uxth r2, r3 8003152: 4b05 ldr r3, [pc, #20] ; (8003168 ) 8003154: f8a3 2d04 strh.w r2, [r3, #3332] ; 0xd04 return true; 8003158: 2301 movs r3, #1 800315a: e000 b.n 800315e } else { // Буфер пуст, можно добавить обработку ошибки return false; 800315c: 2300 movs r3, #0 } } 800315e: 4618 mov r0, r3 8003160: 3708 adds r7, #8 8003162: 46bd mov sp, r7 8003164: bd80 pop {r7, pc} 8003166: bf00 nop 8003168: 20002414 .word 0x20002414 0800316c : //Количество элементов в буфере uint16_t EDCAN_getRxBufferElementCount() { 800316c: b480 push {r7} 800316e: af00 add r7, sp, #0 return rxBuffer.count; 8003170: 4b03 ldr r3, [pc, #12] ; (8003180 ) 8003172: f8b3 3d04 ldrh.w r3, [r3, #3332] ; 0xd04 } 8003176: 4618 mov r0, r3 8003178: 46bd mov sp, r7 800317a: bc80 pop {r7} 800317c: 4770 bx lr 800317e: bf00 nop 8003180: 20002414 .word 0x20002414 08003184 : return false; } } //Функция для обработки входящих пакетов из буфера void EDCAN_ExchangeRxBuffer(){ 8003184: b590 push {r4, r7, lr} 8003186: b087 sub sp, #28 8003188: af02 add r7, sp, #8 EDCAN_RxFrame_t Rxframe; if(EDCAN_getRxBufferElementCount()>0){ 800318a: f7ff ffef bl 800316c 800318e: 4603 mov r3, r0 8003190: 2b00 cmp r3, #0 8003192: d040 beq.n 8003216 if (EDCAN_RxBufferGet(&Rxframe)){ 8003194: 463b mov r3, r7 8003196: 4618 mov r0, r3 8003198: f7ff ffb0 bl 80030fc 800319c: 4603 mov r3, r0 800319e: 2b00 cmp r3, #0 80031a0: d039 beq.n 8003216 if(Rxframe.ExtID.PacketType == ED_WRITE){ 80031a2: 78fb ldrb r3, [r7, #3] 80031a4: f003 0318 and.w r3, r3, #24 80031a8: b2db uxtb r3, r3 80031aa: 2b00 cmp r3, #0 80031ac: d10e bne.n 80031cc EDCAN_WriteHandler(Rxframe.ExtID.SourceID, Rxframe.ExtID.DestinationID, Rxframe.ExtID.RegisterAddress, Rxframe.data, Rxframe.DLC); 80031ae: 7878 ldrb r0, [r7, #1] 80031b0: 7839 ldrb r1, [r7, #0] 80031b2: 887b ldrh r3, [r7, #2] 80031b4: f3c3 030a ubfx r3, r3, #0, #11 80031b8: b29b uxth r3, r3 80031ba: 461c mov r4, r3 80031bc: 7b3b ldrb r3, [r7, #12] 80031be: 463a mov r2, r7 80031c0: 3204 adds r2, #4 80031c2: 9300 str r3, [sp, #0] 80031c4: 4613 mov r3, r2 80031c6: 4622 mov r2, r4 80031c8: f000 f829 bl 800321e } if(Rxframe.ExtID.PacketType == ED_READREQ){ 80031cc: 78fb ldrb r3, [r7, #3] 80031ce: f003 0318 and.w r3, r3, #24 80031d2: b2db uxtb r3, r3 80031d4: 2b08 cmp r3, #8 80031d6: d109 bne.n 80031ec EDCAN_ReadRequestHandler(Rxframe.ExtID.SourceID, Rxframe.ExtID.DestinationID, Rxframe.ExtID.RegisterAddress, Rxframe.data[0]); 80031d8: 7878 ldrb r0, [r7, #1] 80031da: 7839 ldrb r1, [r7, #0] 80031dc: 887b ldrh r3, [r7, #2] 80031de: f3c3 030a ubfx r3, r3, #0, #11 80031e2: b29b uxth r3, r3 80031e4: 461a mov r2, r3 80031e6: 793b ldrb r3, [r7, #4] 80031e8: f000 f8df bl 80033aa } if(Rxframe.ExtID.PacketType == ED_READ){ 80031ec: 78fb ldrb r3, [r7, #3] 80031ee: f003 0318 and.w r3, r3, #24 80031f2: b2db uxtb r3, r3 80031f4: 2b10 cmp r3, #16 80031f6: d10e bne.n 8003216 EDCAN_ReadHandler(Rxframe.ExtID.SourceID, Rxframe.ExtID.DestinationID, Rxframe.ExtID.RegisterAddress, Rxframe.data, Rxframe.DLC); 80031f8: 7878 ldrb r0, [r7, #1] 80031fa: 7839 ldrb r1, [r7, #0] 80031fc: 887b ldrh r3, [r7, #2] 80031fe: f3c3 030a ubfx r3, r3, #0, #11 8003202: b29b uxth r3, r3 8003204: 461c mov r4, r3 8003206: 7b3b ldrb r3, [r7, #12] 8003208: 463a mov r2, r7 800320a: 3204 adds r2, #4 800320c: 9300 str r3, [sp, #0] 800320e: 4613 mov r3, r2 8003210: 4622 mov r2, r4 8003212: f7fe ff7d bl 8002110 } } } } 8003216: bf00 nop 8003218: 3714 adds r7, #20 800321a: 46bd mov sp, r7 800321c: bd90 pop {r4, r7, pc} 0800321e : * DestinationID: Packet Destination ID * Addr: First register address in sequence * *data: pointer for data array * len: length of data (1..255) */ void EDCAN_WriteHandler(uint8_t SourceID, uint8_t DestinationID, uint16_t Addr, uint8_t *data, uint8_t len){ 800321e: b580 push {r7, lr} 8003220: b084 sub sp, #16 8003222: af00 add r7, sp, #0 8003224: 603b str r3, [r7, #0] 8003226: 4603 mov r3, r0 8003228: 71fb strb r3, [r7, #7] 800322a: 460b mov r3, r1 800322c: 71bb strb r3, [r7, #6] 800322e: 4613 mov r3, r2 8003230: 80bb strh r3, [r7, #4] // printf("Destination ID = %d\n", DestinationID); // printf("Address = %d\n", Addr); // printf("Len = %d\n", len); // printf("\n"); for (uint16_t AddrOffset = 0; AddrOffset < len; AddrOffset++){ //по очереди перебираем все полученные регистры через Handler 8003232: 2300 movs r3, #0 8003234: 81fb strh r3, [r7, #14] 8003236: e01e b.n 8003276 // printf ("register[%d] = %d\n", Addr+AddrOffset, data[AddrOffset]); if((Addr+AddrOffset)>=256){ 8003238: 88ba ldrh r2, [r7, #4] 800323a: 89fb ldrh r3, [r7, #14] 800323c: 4413 add r3, r2 800323e: 2bff cmp r3, #255 ; 0xff 8003240: dd0b ble.n 800325a EDCAN_WriteUserRegister(Addr+AddrOffset, data[AddrOffset]); 8003242: 88ba ldrh r2, [r7, #4] 8003244: 89fb ldrh r3, [r7, #14] 8003246: 4413 add r3, r2 8003248: b298 uxth r0, r3 800324a: 89fb ldrh r3, [r7, #14] 800324c: 683a ldr r2, [r7, #0] 800324e: 4413 add r3, r2 8003250: 781b ldrb r3, [r3, #0] 8003252: 4619 mov r1, r3 8003254: f7fe ff78 bl 8002148 8003258: e00a b.n 8003270 }else{ EDCAN_WriteSystemRegister(Addr+AddrOffset, data[AddrOffset]); 800325a: 88ba ldrh r2, [r7, #4] 800325c: 89fb ldrh r3, [r7, #14] 800325e: 4413 add r3, r2 8003260: b298 uxth r0, r3 8003262: 89fb ldrh r3, [r7, #14] 8003264: 683a ldr r2, [r7, #0] 8003266: 4413 add r3, r2 8003268: 781b ldrb r3, [r3, #0] 800326a: 4619 mov r1, r3 800326c: f000 f80d bl 800328a for (uint16_t AddrOffset = 0; AddrOffset < len; AddrOffset++){ //по очереди перебираем все полученные регистры через Handler 8003270: 89fb ldrh r3, [r7, #14] 8003272: 3301 adds r3, #1 8003274: 81fb strh r3, [r7, #14] 8003276: 7e3b ldrb r3, [r7, #24] 8003278: b29b uxth r3, r3 800327a: 89fa ldrh r2, [r7, #14] 800327c: 429a cmp r2, r3 800327e: d3db bcc.n 8003238 } } } 8003280: bf00 nop 8003282: bf00 nop 8003284: 3710 adds r7, #16 8003286: 46bd mov sp, r7 8003288: bd80 pop {r7, pc} 0800328a : void EDCAN_WriteSystemRegister(uint16_t addr, uint8_t value){ 800328a: b580 push {r7, lr} 800328c: b082 sub sp, #8 800328e: af00 add r7, sp, #0 8003290: 4603 mov r3, r0 8003292: 460a mov r2, r1 8003294: 80fb strh r3, [r7, #6] 8003296: 4613 mov r3, r2 8003298: 717b strb r3, [r7, #5] switch(addr){ 800329a: 88fb ldrh r3, [r7, #6] 800329c: 2b20 cmp r3, #32 800329e: d104 bne.n 80032aa case EDCAN_REG_SILENT: EDCAN_EnterSilentMode(value); 80032a0: 797b ldrb r3, [r7, #5] 80032a2: 4618 mov r0, r3 80032a4: f7ff fdb0 bl 8002e08 break; 80032a8: bf00 nop //default: // printf ("Unknown register\n"); } } 80032aa: bf00 nop 80032ac: 3708 adds r7, #8 80032ae: 46bd mov sp, r7 80032b0: bd80 pop {r7, pc} ... 080032b4 : * @brief Handler to get System register values (0..255) * * @param addr: register address * @retval register value (uint8_t) */ uint8_t EDCAN_GetSystemRegisterValue(uint16_t addr){ 80032b4: b580 push {r7, lr} 80032b6: b082 sub sp, #8 80032b8: af00 add r7, sp, #0 80032ba: 4603 mov r3, r0 80032bc: 80fb strh r3, [r7, #6] static uint32_t uptime_buffer; switch (addr){ 80032be: 88fb ldrh r3, [r7, #6] 80032c0: 2b17 cmp r3, #23 80032c2: d852 bhi.n 800336a 80032c4: a201 add r2, pc, #4 ; (adr r2, 80032cc ) 80032c6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80032ca: bf00 nop 80032cc: 0800332d .word 0x0800332d 80032d0: 08003337 .word 0x08003337 80032d4: 08003333 .word 0x08003333 80032d8: 0800336b .word 0x0800336b 80032dc: 0800336b .word 0x0800336b 80032e0: 0800336b .word 0x0800336b 80032e4: 0800336b .word 0x0800336b 80032e8: 0800336b .word 0x0800336b 80032ec: 0800336b .word 0x0800336b 80032f0: 0800336b .word 0x0800336b 80032f4: 0800336b .word 0x0800336b 80032f8: 0800336b .word 0x0800336b 80032fc: 0800336b .word 0x0800336b 8003300: 0800336b .word 0x0800336b 8003304: 0800336b .word 0x0800336b 8003308: 0800336b .word 0x0800336b 800330c: 0800336b .word 0x0800336b 8003310: 0800336b .word 0x0800336b 8003314: 0800336b .word 0x0800336b 8003318: 0800336b .word 0x0800336b 800331c: 0800333b .word 0x0800333b 8003320: 0800334d .word 0x0800334d 8003324: 08003357 .word 0x08003357 8003328: 08003361 .word 0x08003361 /* регистры 0..255 используются для Системных регистров*/ case EDCAN_REG_SYS_STATUS: return ED_status; 800332c: 4b11 ldr r3, [pc, #68] ; (8003374 ) 800332e: 781b ldrb r3, [r3, #0] 8003330: e01c b.n 800336c break; case EDCAN_REG_SYS_FWVER: return FWVER; 8003332: 2301 movs r3, #1 8003334: e01a b.n 800336c break; case EDCAN_REG_SYS_DEVICEID: return DEVICE_ID; 8003336: 2320 movs r3, #32 8003338: e018 b.n 800336c break; case EDCAN_REG_SYS_UPTIME0: uptime_buffer = HAL_GetTick(); 800333a: f000 fc91 bl 8003c60 800333e: 4603 mov r3, r0 8003340: 4a0d ldr r2, [pc, #52] ; (8003378 ) 8003342: 6013 str r3, [r2, #0] return uptime_buffer & 0xFF; 8003344: 4b0c ldr r3, [pc, #48] ; (8003378 ) 8003346: 681b ldr r3, [r3, #0] 8003348: b2db uxtb r3, r3 800334a: e00f b.n 800336c break; case EDCAN_REG_SYS_UPTIME1: return (uptime_buffer>>8) & 0xFF; 800334c: 4b0a ldr r3, [pc, #40] ; (8003378 ) 800334e: 681b ldr r3, [r3, #0] 8003350: 0a1b lsrs r3, r3, #8 8003352: b2db uxtb r3, r3 8003354: e00a b.n 800336c break; case EDCAN_REG_SYS_UPTIME2: return (uptime_buffer>>16) & 0xFF; 8003356: 4b08 ldr r3, [pc, #32] ; (8003378 ) 8003358: 681b ldr r3, [r3, #0] 800335a: 0c1b lsrs r3, r3, #16 800335c: b2db uxtb r3, r3 800335e: e005 b.n 800336c break; case EDCAN_REG_SYS_UPTIME3: return (uptime_buffer>>24) & 0xFF; 8003360: 4b05 ldr r3, [pc, #20] ; (8003378 ) 8003362: 681b ldr r3, [r3, #0] 8003364: 0e1b lsrs r3, r3, #24 8003366: b2db uxtb r3, r3 8003368: e000 b.n 800336c break; default: return 0x00; 800336a: 2300 movs r3, #0 } } 800336c: 4618 mov r0, r3 800336e: 3708 adds r7, #8 8003370: 46bd mov sp, r7 8003372: bd80 pop {r7, pc} 8003374: 2000311a .word 0x2000311a 8003378: 2000311c .word 0x2000311c 0800337c : * @brief Handler to get own register values * * @param addr: register address * @retval register value (uint8_t) */ uint8_t EDCAN_GetOwnRegisterValue (uint16_t addr){ 800337c: b580 push {r7, lr} 800337e: b082 sub sp, #8 8003380: af00 add r7, sp, #0 8003382: 4603 mov r3, r0 8003384: 80fb strh r3, [r7, #6] if(addr<256){ 8003386: 88fb ldrh r3, [r7, #6] 8003388: 2bff cmp r3, #255 ; 0xff 800338a: d805 bhi.n 8003398 return EDCAN_GetSystemRegisterValue(addr); // 0..255 800338c: 88fb ldrh r3, [r7, #6] 800338e: 4618 mov r0, r3 8003390: f7ff ff90 bl 80032b4 8003394: 4603 mov r3, r0 8003396: e004 b.n 80033a2 }else { return EDCAN_GetUserRegisterValue(addr); // 256..2047 8003398: 88fb ldrh r3, [r7, #6] 800339a: 4618 mov r0, r3 800339c: f7fe ff6a bl 8002274 80033a0: 4603 mov r3, r0 } } 80033a2: 4618 mov r0, r3 80033a4: 3708 adds r7, #8 80033a6: 46bd mov sp, r7 80033a8: bd80 pop {r7, pc} 080033aa : * DestinationID: Packet Destination ID * Addr: First register address in sequence * *data: pointer for data array * len: length of data (1..255) */ void EDCAN_ReadRequestHandler(uint8_t SourceID, uint8_t DestinationID, uint16_t Addr, uint8_t len){ 80033aa: b590 push {r4, r7, lr} 80033ac: b087 sub sp, #28 80033ae: af00 add r7, sp, #0 80033b0: 4604 mov r4, r0 80033b2: 4608 mov r0, r1 80033b4: 4611 mov r1, r2 80033b6: 461a mov r2, r3 80033b8: 4623 mov r3, r4 80033ba: 71fb strb r3, [r7, #7] 80033bc: 4603 mov r3, r0 80033be: 71bb strb r3, [r7, #6] 80033c0: 460b mov r3, r1 80033c2: 80bb strh r3, [r7, #4] 80033c4: 4613 mov r3, r2 80033c6: 70fb strb r3, [r7, #3] //Получили пакет Read (запрошенное значение регистров) uint8_t TxData[8]; uint16_t AddrOffset = Addr; 80033c8: 88bb ldrh r3, [r7, #4] 80033ca: 82fb strh r3, [r7, #22] // printf("Destination ID = %d\n", DestinationID); // printf("Address = %d\n", Addr); // printf("Len = %d\n", len); // printf("\n"); while (len>0){ //по очереди перебираем все полученные регистры через Handler 80033cc: e051 b.n 8003472 if(len>=8){ //если количество регистров больше 8, отправляем 8 и разбиваем на несколько пакетов 80033ce: 78fb ldrb r3, [r7, #3] 80033d0: 2b07 cmp r3, #7 80033d2: d926 bls.n 8003422 for(uint8_t n = 0; n < 8; n++){ 80033d4: 2300 movs r3, #0 80033d6: 757b strb r3, [r7, #21] 80033d8: e012 b.n 8003400 TxData[n] = EDCAN_GetOwnRegisterValue(n+AddrOffset); 80033da: 7d7b ldrb r3, [r7, #21] 80033dc: b29a uxth r2, r3 80033de: 8afb ldrh r3, [r7, #22] 80033e0: 4413 add r3, r2 80033e2: b29b uxth r3, r3 80033e4: 7d7c ldrb r4, [r7, #21] 80033e6: 4618 mov r0, r3 80033e8: f7ff ffc8 bl 800337c 80033ec: 4603 mov r3, r0 80033ee: 461a mov r2, r3 80033f0: f104 0318 add.w r3, r4, #24 80033f4: 443b add r3, r7 80033f6: f803 2c0c strb.w r2, [r3, #-12] for(uint8_t n = 0; n < 8; n++){ 80033fa: 7d7b ldrb r3, [r7, #21] 80033fc: 3301 adds r3, #1 80033fe: 757b strb r3, [r7, #21] 8003400: 7d7b ldrb r3, [r7, #21] 8003402: 2b07 cmp r3, #7 8003404: d9e9 bls.n 80033da //printf ("register[%d] = %d\n", n+AddrOffset, TxData[n]); } EDCAN_SendPacketRead(SourceID, AddrOffset, TxData, 8); /* отправляем ответный пакет со значениями собственных регистров */ 8003406: f107 020c add.w r2, r7, #12 800340a: 8af9 ldrh r1, [r7, #22] 800340c: 79f8 ldrb r0, [r7, #7] 800340e: 2308 movs r3, #8 8003410: f7ff fc84 bl 8002d1c //printf ("sent%d, %d\n", AddrOffset, len); AddrOffset +=8; 8003414: 8afb ldrh r3, [r7, #22] 8003416: 3308 adds r3, #8 8003418: 82fb strh r3, [r7, #22] len -=8; 800341a: 78fb ldrb r3, [r7, #3] 800341c: 3b08 subs r3, #8 800341e: 70fb strb r3, [r7, #3] 8003420: e027 b.n 8003472 }else{ for(uint8_t n = 0; n < len; n++){ 8003422: 2300 movs r3, #0 8003424: 753b strb r3, [r7, #20] 8003426: e012 b.n 800344e TxData[n] = EDCAN_GetOwnRegisterValue(n+AddrOffset); 8003428: 7d3b ldrb r3, [r7, #20] 800342a: b29a uxth r2, r3 800342c: 8afb ldrh r3, [r7, #22] 800342e: 4413 add r3, r2 8003430: b29b uxth r3, r3 8003432: 7d3c ldrb r4, [r7, #20] 8003434: 4618 mov r0, r3 8003436: f7ff ffa1 bl 800337c 800343a: 4603 mov r3, r0 800343c: 461a mov r2, r3 800343e: f104 0318 add.w r3, r4, #24 8003442: 443b add r3, r7 8003444: f803 2c0c strb.w r2, [r3, #-12] for(uint8_t n = 0; n < len; n++){ 8003448: 7d3b ldrb r3, [r7, #20] 800344a: 3301 adds r3, #1 800344c: 753b strb r3, [r7, #20] 800344e: 7d3a ldrb r2, [r7, #20] 8003450: 78fb ldrb r3, [r7, #3] 8003452: 429a cmp r2, r3 8003454: d3e8 bcc.n 8003428 //printf ("register[%d] = %d\n", n+AddrOffset, TxData[n]); } EDCAN_SendPacketRead(SourceID, AddrOffset, TxData, len); /* отправляем ответный пакет со значениями собственных регистров */ 8003456: 78fb ldrb r3, [r7, #3] 8003458: f107 020c add.w r2, r7, #12 800345c: 8af9 ldrh r1, [r7, #22] 800345e: 79f8 ldrb r0, [r7, #7] 8003460: f7ff fc5c bl 8002d1c //printf ("sent%d, %d\n", AddrOffset, len); AddrOffset +=len; 8003464: 78fb ldrb r3, [r7, #3] 8003466: b29a uxth r2, r3 8003468: 8afb ldrh r3, [r7, #22] 800346a: 4413 add r3, r2 800346c: 82fb strh r3, [r7, #22] len = 0; 800346e: 2300 movs r3, #0 8003470: 70fb strb r3, [r7, #3] while (len>0){ //по очереди перебираем все полученные регистры через Handler 8003472: 78fb ldrb r3, [r7, #3] 8003474: 2b00 cmp r3, #0 8003476: d1aa bne.n 80033ce } } // printf("\n"); } 8003478: bf00 nop 800347a: bf00 nop 800347c: 371c adds r7, #28 800347e: 46bd mov sp, r7 8003480: bd90 pop {r4, r7, pc} ... 08003484
: /** * @brief The application entry point. * @retval int */ int main(void) { 8003484: b580 push {r7, lr} 8003486: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8003488: f000 fb92 bl 8003bb0 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800348c: f000 f82e bl 80034ec /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8003490: f7ff f8bc bl 800260c MX_ADC1_Init(); 8003494: f7fd fd2a bl 8000eec MX_CAN1_Init(); 8003498: f7fd fe42 bl 8001120 MX_CAN2_Init(); 800349c: f7fd fe76 bl 800118c MX_USART2_UART_Init(); 80034a0: f000 fad4 bl 8003a4c /* USER CODE BEGIN 2 */ CAN_ReInit(); 80034a4: f7ff fbd4 bl 8002c50 Init_Peripheral(); 80034a8: f7fd fe0c bl 80010c4 HAL_Delay(300); 80034ac: f44f 7096 mov.w r0, #300 ; 0x12c 80034b0: f000 fbe0 bl 8003c74 GBT_Init(); 80034b4: f7fd ff7e bl 80013b4 set_Time(1721651966); //2024-07-22T12:39:26+00:00 80034b8: 480a ldr r0, [pc, #40] ; (80034e4 ) 80034ba: f000 f899 bl 80035f0 printf("Startup (type \'help\' for command list)\n"); 80034be: 480a ldr r0, [pc, #40] ; (80034e8 ) 80034c0: f004 fb48 bl 8007b54 debug_init(); 80034c4: f7fe fb66 bl 8001b94 //EDCAN_Init(SW_GetAddr()); //0x20..0x23 EDCAN_Init(0x20); //Адрес EDCAN 80034c8: 2020 movs r0, #32 80034ca: f7ff fbb1 bl 8002c30 CAN_ReInit(); 80034ce: f7ff fbbf bl 8002c50 GBT_CAN_ReInit(); 80034d2: f7ff fa81 bl 80029d8 { /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ // HAL_Delay(1); EDCAN_Loop(); 80034d6: f7ff fc5b bl 8002d90 // can_task(); debug_task(); 80034da: f7fe fdfb bl 80020d4 GBT_ChargerTask(); 80034de: f7fe f815 bl 800150c EDCAN_Loop(); 80034e2: e7f8 b.n 80034d6 80034e4: 669e52fe .word 0x669e52fe 80034e8: 08008d9c .word 0x08008d9c 080034ec : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80034ec: b580 push {r7, lr} 80034ee: b09c sub sp, #112 ; 0x70 80034f0: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 80034f2: f107 0338 add.w r3, r7, #56 ; 0x38 80034f6: 2238 movs r2, #56 ; 0x38 80034f8: 2100 movs r1, #0 80034fa: 4618 mov r0, r3 80034fc: f004 f9c0 bl 8007880 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8003500: f107 0324 add.w r3, r7, #36 ; 0x24 8003504: 2200 movs r2, #0 8003506: 601a str r2, [r3, #0] 8003508: 605a str r2, [r3, #4] 800350a: 609a str r2, [r3, #8] 800350c: 60da str r2, [r3, #12] 800350e: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8003510: 1d3b adds r3, r7, #4 8003512: 2220 movs r2, #32 8003514: 2100 movs r1, #0 8003516: 4618 mov r0, r3 8003518: f004 f9b2 bl 8007880 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 800351c: 2301 movs r3, #1 800351e: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8003520: f44f 3380 mov.w r3, #65536 ; 0x10000 8003524: 643b str r3, [r7, #64] ; 0x40 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV5; 8003526: 2304 movs r3, #4 8003528: 647b str r3, [r7, #68] ; 0x44 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800352a: 2301 movs r3, #1 800352c: 64fb str r3, [r7, #76] ; 0x4c RCC_OscInitStruct.Prediv1Source = RCC_PREDIV1_SOURCE_PLL2; 800352e: f44f 3380 mov.w r3, #65536 ; 0x10000 8003532: 63fb str r3, [r7, #60] ; 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8003534: 2302 movs r3, #2 8003536: 65bb str r3, [r7, #88] ; 0x58 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8003538: f44f 3380 mov.w r3, #65536 ; 0x10000 800353c: 65fb str r3, [r7, #92] ; 0x5c RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 800353e: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000 8003542: 663b str r3, [r7, #96] ; 0x60 RCC_OscInitStruct.PLL2.PLL2State = RCC_PLL2_ON; 8003544: 2302 movs r3, #2 8003546: 667b str r3, [r7, #100] ; 0x64 RCC_OscInitStruct.PLL2.PLL2MUL = RCC_PLL2_MUL8; 8003548: f44f 63c0 mov.w r3, #1536 ; 0x600 800354c: 66bb str r3, [r7, #104] ; 0x68 RCC_OscInitStruct.PLL2.HSEPrediv2Value = RCC_HSE_PREDIV2_DIV5; 800354e: 2340 movs r3, #64 ; 0x40 8003550: 66fb str r3, [r7, #108] ; 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8003552: f107 0338 add.w r3, r7, #56 ; 0x38 8003556: 4618 mov r0, r3 8003558: f002 fb64 bl 8005c24 800355c: 4603 mov r3, r0 800355e: 2b00 cmp r3, #0 8003560: d001 beq.n 8003566 { Error_Handler(); 8003562: f000 f82d bl 80035c0 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8003566: 230f movs r3, #15 8003568: 627b str r3, [r7, #36] ; 0x24 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800356a: 2302 movs r3, #2 800356c: 62bb str r3, [r7, #40] ; 0x28 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800356e: 2300 movs r3, #0 8003570: 62fb str r3, [r7, #44] ; 0x2c RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8003572: f44f 6380 mov.w r3, #1024 ; 0x400 8003576: 633b str r3, [r7, #48] ; 0x30 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8003578: 2300 movs r3, #0 800357a: 637b str r3, [r7, #52] ; 0x34 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800357c: f107 0324 add.w r3, r7, #36 ; 0x24 8003580: 2102 movs r1, #2 8003582: 4618 mov r0, r3 8003584: f002 fe64 bl 8006250 8003588: 4603 mov r3, r0 800358a: 2b00 cmp r3, #0 800358c: d001 beq.n 8003592 { Error_Handler(); 800358e: f000 f817 bl 80035c0 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; 8003592: 2302 movs r3, #2 8003594: 607b str r3, [r7, #4] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 8003596: f44f 4300 mov.w r3, #32768 ; 0x8000 800359a: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 800359c: 1d3b adds r3, r7, #4 800359e: 4618 mov r0, r3 80035a0: f003 f86e bl 8006680 80035a4: 4603 mov r3, r0 80035a6: 2b00 cmp r3, #0 80035a8: d001 beq.n 80035ae { Error_Handler(); 80035aa: f000 f809 bl 80035c0 } /** Configure the Systick interrupt time */ __HAL_RCC_PLLI2S_ENABLE(); 80035ae: 4b03 ldr r3, [pc, #12] ; (80035bc ) 80035b0: 2201 movs r2, #1 80035b2: 601a str r2, [r3, #0] } 80035b4: bf00 nop 80035b6: 3770 adds r7, #112 ; 0x70 80035b8: 46bd mov sp, r7 80035ba: bd80 pop {r7, pc} 80035bc: 42420070 .word 0x42420070 080035c0 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 80035c0: b480 push {r7} 80035c2: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 80035c4: b672 cpsid i } 80035c6: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 80035c8: e7fe b.n 80035c8 ... 080035cc : uint32_t GBT_time_offset; //current time = offset+HAL_GetTick()/1000; uint8_t tmp_time[4]; uint8_t tmp_time32; uint32_t get_Current_Time(){ 80035cc: b580 push {r7, lr} 80035ce: af00 add r7, sp, #0 return GBT_time_offset + (HAL_GetTick()/1000); 80035d0: f000 fb46 bl 8003c60 80035d4: 4603 mov r3, r0 80035d6: 4a04 ldr r2, [pc, #16] ; (80035e8 ) 80035d8: fba2 2303 umull r2, r3, r2, r3 80035dc: 099a lsrs r2, r3, #6 80035de: 4b03 ldr r3, [pc, #12] ; (80035ec ) 80035e0: 681b ldr r3, [r3, #0] 80035e2: 4413 add r3, r2 } 80035e4: 4618 mov r0, r3 80035e6: bd80 pop {r7, pc} 80035e8: 10624dd3 .word 0x10624dd3 80035ec: 20003120 .word 0x20003120 080035f0 : void set_Time(uint32_t unix_time){ 80035f0: b580 push {r7, lr} 80035f2: b082 sub sp, #8 80035f4: af00 add r7, sp, #0 80035f6: 6078 str r0, [r7, #4] if(unix_time <= (HAL_GetTick()/1000)) return; //invalid time 80035f8: f000 fb32 bl 8003c60 80035fc: 4603 mov r3, r0 80035fe: 4a0b ldr r2, [pc, #44] ; (800362c ) 8003600: fba2 2303 umull r2, r3, r2, r3 8003604: 099b lsrs r3, r3, #6 8003606: 687a ldr r2, [r7, #4] 8003608: 429a cmp r2, r3 800360a: d90b bls.n 8003624 GBT_time_offset = unix_time - (HAL_GetTick()/1000); 800360c: f000 fb28 bl 8003c60 8003610: 4603 mov r3, r0 8003612: 4a06 ldr r2, [pc, #24] ; (800362c ) 8003614: fba2 2303 umull r2, r3, r2, r3 8003618: 099b lsrs r3, r3, #6 800361a: 687a ldr r2, [r7, #4] 800361c: 1ad3 subs r3, r2, r3 800361e: 4a04 ldr r2, [pc, #16] ; (8003630 ) 8003620: 6013 str r3, [r2, #0] 8003622: e000 b.n 8003626 if(unix_time <= (HAL_GetTick()/1000)) return; //invalid time 8003624: bf00 nop } 8003626: 3708 adds r7, #8 8003628: 46bd mov sp, r7 800362a: bd80 pop {r7, pc} 800362c: 10624dd3 .word 0x10624dd3 8003630: 20003120 .word 0x20003120 08003634 : uint8_t to_bcd(int value) { 8003634: b480 push {r7} 8003636: b083 sub sp, #12 8003638: af00 add r7, sp, #0 800363a: 6078 str r0, [r7, #4] return ((value / 10) << 4) | (value % 10); 800363c: 687b ldr r3, [r7, #4] 800363e: 4a0e ldr r2, [pc, #56] ; (8003678 ) 8003640: fb82 1203 smull r1, r2, r2, r3 8003644: 1092 asrs r2, r2, #2 8003646: 17db asrs r3, r3, #31 8003648: 1ad3 subs r3, r2, r3 800364a: 011b lsls r3, r3, #4 800364c: b258 sxtb r0, r3 800364e: 687a ldr r2, [r7, #4] 8003650: 4b09 ldr r3, [pc, #36] ; (8003678 ) 8003652: fb83 1302 smull r1, r3, r3, r2 8003656: 1099 asrs r1, r3, #2 8003658: 17d3 asrs r3, r2, #31 800365a: 1ac9 subs r1, r1, r3 800365c: 460b mov r3, r1 800365e: 009b lsls r3, r3, #2 8003660: 440b add r3, r1 8003662: 005b lsls r3, r3, #1 8003664: 1ad1 subs r1, r2, r3 8003666: b24b sxtb r3, r1 8003668: 4303 orrs r3, r0 800366a: b25b sxtb r3, r3 800366c: b2db uxtb r3, r3 } 800366e: 4618 mov r0, r3 8003670: 370c adds r7, #12 8003672: 46bd mov sp, r7 8003674: bc80 pop {r7} 8003676: 4770 bx lr 8003678: 66666667 .word 0x66666667 0800367c : void unix_to_bcd(uint32_t unix_time, uint8_t *time) { 800367c: b590 push {r4, r7, lr} 800367e: b087 sub sp, #28 8003680: af00 add r7, sp, #0 8003682: 6078 str r0, [r7, #4] 8003684: 6039 str r1, [r7, #0] struct tm *tm_info; time_t raw_time = (time_t)unix_time; 8003686: 6879 ldr r1, [r7, #4] 8003688: 2000 movs r0, #0 800368a: 460a mov r2, r1 800368c: 4603 mov r3, r0 800368e: e9c7 2302 strd r2, r3, [r7, #8] tm_info = gmtime(&raw_time); 8003692: f107 0308 add.w r3, r7, #8 8003696: 4618 mov r0, r3 8003698: f003 ffec bl 8007674 800369c: 6178 str r0, [r7, #20] time[0] = to_bcd(tm_info->tm_sec); 800369e: 697b ldr r3, [r7, #20] 80036a0: 681b ldr r3, [r3, #0] 80036a2: 4618 mov r0, r3 80036a4: f7ff ffc6 bl 8003634 80036a8: 4603 mov r3, r0 80036aa: 461a mov r2, r3 80036ac: 683b ldr r3, [r7, #0] 80036ae: 701a strb r2, [r3, #0] time[1] = to_bcd(tm_info->tm_min); 80036b0: 697b ldr r3, [r7, #20] 80036b2: 685a ldr r2, [r3, #4] 80036b4: 683b ldr r3, [r7, #0] 80036b6: 1c5c adds r4, r3, #1 80036b8: 4610 mov r0, r2 80036ba: f7ff ffbb bl 8003634 80036be: 4603 mov r3, r0 80036c0: 7023 strb r3, [r4, #0] time[2] = to_bcd(tm_info->tm_hour); 80036c2: 697b ldr r3, [r7, #20] 80036c4: 689a ldr r2, [r3, #8] 80036c6: 683b ldr r3, [r7, #0] 80036c8: 1c9c adds r4, r3, #2 80036ca: 4610 mov r0, r2 80036cc: f7ff ffb2 bl 8003634 80036d0: 4603 mov r3, r0 80036d2: 7023 strb r3, [r4, #0] time[3] = to_bcd(tm_info->tm_mday); 80036d4: 697b ldr r3, [r7, #20] 80036d6: 68da ldr r2, [r3, #12] 80036d8: 683b ldr r3, [r7, #0] 80036da: 1cdc adds r4, r3, #3 80036dc: 4610 mov r0, r2 80036de: f7ff ffa9 bl 8003634 80036e2: 4603 mov r3, r0 80036e4: 7023 strb r3, [r4, #0] time[4] = to_bcd(tm_info->tm_mon + 1); // tm_mon is 0-11 80036e6: 697b ldr r3, [r7, #20] 80036e8: 691b ldr r3, [r3, #16] 80036ea: 1c5a adds r2, r3, #1 80036ec: 683b ldr r3, [r7, #0] 80036ee: 1d1c adds r4, r3, #4 80036f0: 4610 mov r0, r2 80036f2: f7ff ff9f bl 8003634 80036f6: 4603 mov r3, r0 80036f8: 7023 strb r3, [r4, #0] time[5] = to_bcd((tm_info->tm_year + 1900) % 100); // Year in 2 digits 80036fa: 697b ldr r3, [r7, #20] 80036fc: 695b ldr r3, [r3, #20] 80036fe: f203 736c addw r3, r3, #1900 ; 0x76c 8003702: 4a13 ldr r2, [pc, #76] ; (8003750 ) 8003704: fb82 1203 smull r1, r2, r2, r3 8003708: 1151 asrs r1, r2, #5 800370a: 17da asrs r2, r3, #31 800370c: 1a8a subs r2, r1, r2 800370e: 2164 movs r1, #100 ; 0x64 8003710: fb01 f202 mul.w r2, r1, r2 8003714: 1a9a subs r2, r3, r2 8003716: 683b ldr r3, [r7, #0] 8003718: 1d5c adds r4, r3, #5 800371a: 4610 mov r0, r2 800371c: f7ff ff8a bl 8003634 8003720: 4603 mov r3, r0 8003722: 7023 strb r3, [r4, #0] time[6] = to_bcd((tm_info->tm_year + 1900) / 100); // Century in 2 digits 8003724: 697b ldr r3, [r7, #20] 8003726: 695b ldr r3, [r3, #20] 8003728: f203 736c addw r3, r3, #1900 ; 0x76c 800372c: 4a08 ldr r2, [pc, #32] ; (8003750 ) 800372e: fb82 1203 smull r1, r2, r2, r3 8003732: 1152 asrs r2, r2, #5 8003734: 17db asrs r3, r3, #31 8003736: 1ad2 subs r2, r2, r3 8003738: 683b ldr r3, [r7, #0] 800373a: 1d9c adds r4, r3, #6 800373c: 4610 mov r0, r2 800373e: f7ff ff79 bl 8003634 8003742: 4603 mov r3, r0 8003744: 7023 strb r3, [r4, #0] } 8003746: bf00 nop 8003748: 371c adds r7, #28 800374a: 46bd mov sp, r7 800374c: bd90 pop {r4, r7, pc} 800374e: bf00 nop 8003750: 51eb851f .word 0x51eb851f 08003754 : void writeTimeReg(uint8_t reg_number, uint8_t value){ 8003754: b580 push {r7, lr} 8003756: b082 sub sp, #8 8003758: af00 add r7, sp, #0 800375a: 4603 mov r3, r0 800375c: 460a mov r2, r1 800375e: 71fb strb r3, [r7, #7] 8003760: 4613 mov r3, r2 8003762: 71bb strb r3, [r7, #6] tmp_time[reg_number] = value; 8003764: 79fb ldrb r3, [r7, #7] 8003766: 490e ldr r1, [pc, #56] ; (80037a0 ) 8003768: 79ba ldrb r2, [r7, #6] 800376a: 54ca strb r2, [r1, r3] if(reg_number == 3) set_Time((tmp_time[0])+(tmp_time[1]<<8)+(tmp_time[2]<<16)+(tmp_time[3]<<24)); 800376c: 79fb ldrb r3, [r7, #7] 800376e: 2b03 cmp r3, #3 8003770: d111 bne.n 8003796 8003772: 4b0b ldr r3, [pc, #44] ; (80037a0 ) 8003774: 781b ldrb r3, [r3, #0] 8003776: 461a mov r2, r3 8003778: 4b09 ldr r3, [pc, #36] ; (80037a0 ) 800377a: 785b ldrb r3, [r3, #1] 800377c: 021b lsls r3, r3, #8 800377e: 441a add r2, r3 8003780: 4b07 ldr r3, [pc, #28] ; (80037a0 ) 8003782: 789b ldrb r3, [r3, #2] 8003784: 041b lsls r3, r3, #16 8003786: 441a add r2, r3 8003788: 4b05 ldr r3, [pc, #20] ; (80037a0 ) 800378a: 78db ldrb r3, [r3, #3] 800378c: 061b lsls r3, r3, #24 800378e: 4413 add r3, r2 8003790: 4618 mov r0, r3 8003792: f7ff ff2d bl 80035f0 }; 8003796: bf00 nop 8003798: 3708 adds r7, #8 800379a: 46bd mov sp, r7 800379c: bd80 pop {r7, pc} 800379e: bf00 nop 80037a0: 20003124 .word 0x20003124 080037a4 : uint8_t getTimeReg(uint8_t reg_number){ 80037a4: b580 push {r7, lr} 80037a6: b082 sub sp, #8 80037a8: af00 add r7, sp, #0 80037aa: 4603 mov r3, r0 80037ac: 71fb strb r3, [r7, #7] if(reg_number == 0){ 80037ae: 79fb ldrb r3, [r7, #7] 80037b0: 2b00 cmp r3, #0 80037b2: d108 bne.n 80037c6 tmp_time32 = get_Current_Time(); 80037b4: f7ff ff0a bl 80035cc 80037b8: 4603 mov r3, r0 80037ba: b2da uxtb r2, r3 80037bc: 4b0c ldr r3, [pc, #48] ; (80037f0 ) 80037be: 701a strb r2, [r3, #0] return tmp_time32 & 0xFF; 80037c0: 4b0b ldr r3, [pc, #44] ; (80037f0 ) 80037c2: 781b ldrb r3, [r3, #0] 80037c4: e00f b.n 80037e6 }else if(reg_number == 1){ 80037c6: 79fb ldrb r3, [r7, #7] 80037c8: 2b01 cmp r3, #1 80037ca: d101 bne.n 80037d0 return (tmp_time32>>8) & 0xFF; 80037cc: 2300 movs r3, #0 80037ce: e00a b.n 80037e6 }else if(reg_number == 2){ 80037d0: 79fb ldrb r3, [r7, #7] 80037d2: 2b02 cmp r3, #2 80037d4: d101 bne.n 80037da return (tmp_time32>>16) & 0xFF; 80037d6: 2300 movs r3, #0 80037d8: e005 b.n 80037e6 }else if(reg_number == 3){ 80037da: 79fb ldrb r3, [r7, #7] 80037dc: 2b03 cmp r3, #3 80037de: d101 bne.n 80037e4 return (tmp_time32>>24) & 0xFF; 80037e0: 2300 movs r3, #0 80037e2: e000 b.n 80037e6 }else{ return 0x00; 80037e4: 2300 movs r3, #0 } }; 80037e6: 4618 mov r0, r3 80037e8: 3708 adds r7, #8 80037ea: 46bd mov sp, r7 80037ec: bd80 pop {r7, pc} 80037ee: bf00 nop 80037f0: 20003128 .word 0x20003128 080037f4 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 80037f4: b480 push {r7} 80037f6: b085 sub sp, #20 80037f8: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 80037fa: 4b15 ldr r3, [pc, #84] ; (8003850 ) 80037fc: 699b ldr r3, [r3, #24] 80037fe: 4a14 ldr r2, [pc, #80] ; (8003850 ) 8003800: f043 0301 orr.w r3, r3, #1 8003804: 6193 str r3, [r2, #24] 8003806: 4b12 ldr r3, [pc, #72] ; (8003850 ) 8003808: 699b ldr r3, [r3, #24] 800380a: f003 0301 and.w r3, r3, #1 800380e: 60bb str r3, [r7, #8] 8003810: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 8003812: 4b0f ldr r3, [pc, #60] ; (8003850 ) 8003814: 69db ldr r3, [r3, #28] 8003816: 4a0e ldr r2, [pc, #56] ; (8003850 ) 8003818: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 800381c: 61d3 str r3, [r2, #28] 800381e: 4b0c ldr r3, [pc, #48] ; (8003850 ) 8003820: 69db ldr r3, [r3, #28] 8003822: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003826: 607b str r3, [r7, #4] 8003828: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 800382a: 4b0a ldr r3, [pc, #40] ; (8003854 ) 800382c: 685b ldr r3, [r3, #4] 800382e: 60fb str r3, [r7, #12] 8003830: 68fb ldr r3, [r7, #12] 8003832: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 8003836: 60fb str r3, [r7, #12] 8003838: 68fb ldr r3, [r7, #12] 800383a: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 800383e: 60fb str r3, [r7, #12] 8003840: 4a04 ldr r2, [pc, #16] ; (8003854 ) 8003842: 68fb ldr r3, [r7, #12] 8003844: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8003846: bf00 nop 8003848: 3714 adds r7, #20 800384a: 46bd mov sp, r7 800384c: bc80 pop {r7} 800384e: 4770 bx lr 8003850: 40021000 .word 0x40021000 8003854: 40010000 .word 0x40010000 08003858 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8003858: b480 push {r7} 800385a: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800385c: e7fe b.n 800385c 0800385e : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800385e: b480 push {r7} 8003860: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8003862: e7fe b.n 8003862 08003864 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8003864: b480 push {r7} 8003866: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8003868: e7fe b.n 8003868 0800386a : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 800386a: b480 push {r7} 800386c: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800386e: e7fe b.n 800386e 08003870 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8003870: b480 push {r7} 8003872: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8003874: e7fe b.n 8003874 08003876 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8003876: b480 push {r7} 8003878: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800387a: bf00 nop 800387c: 46bd mov sp, r7 800387e: bc80 pop {r7} 8003880: 4770 bx lr 08003882 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8003882: b480 push {r7} 8003884: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8003886: bf00 nop 8003888: 46bd mov sp, r7 800388a: bc80 pop {r7} 800388c: 4770 bx lr 0800388e : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800388e: b480 push {r7} 8003890: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8003892: bf00 nop 8003894: 46bd mov sp, r7 8003896: bc80 pop {r7} 8003898: 4770 bx lr 0800389a : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800389a: b580 push {r7, lr} 800389c: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800389e: f000 f9cd bl 8003c3c /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 80038a2: bf00 nop 80038a4: bd80 pop {r7, pc} ... 080038a8 : /** * @brief This function handles CAN1 RX0 interrupt. */ void CAN1_RX0_IRQHandler(void) { 80038a8: b580 push {r7, lr} 80038aa: af00 add r7, sp, #0 /* USER CODE BEGIN CAN1_RX0_IRQn 0 */ /* USER CODE END CAN1_RX0_IRQn 0 */ HAL_CAN_IRQHandler(&hcan1); 80038ac: 4802 ldr r0, [pc, #8] ; (80038b8 ) 80038ae: f001 fbb6 bl 800501e /* USER CODE BEGIN CAN1_RX0_IRQn 1 */ /* USER CODE END CAN1_RX0_IRQn 1 */ } 80038b2: bf00 nop 80038b4: bd80 pop {r7, pc} 80038b6: bf00 nop 80038b8: 200000bc .word 0x200000bc 080038bc : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 80038bc: b580 push {r7, lr} 80038be: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 80038c0: 4802 ldr r0, [pc, #8] ; (80038cc ) 80038c2: f003 fa9f bl 8006e04 /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 80038c6: bf00 nop 80038c8: bd80 pop {r7, pc} 80038ca: bf00 nop 80038cc: 20003130 .word 0x20003130 080038d0 : /** * @brief This function handles CAN2 TX interrupt. */ void CAN2_TX_IRQHandler(void) { 80038d0: b580 push {r7, lr} 80038d2: af00 add r7, sp, #0 /* USER CODE BEGIN CAN2_TX_IRQn 0 */ /* USER CODE END CAN2_TX_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 80038d4: 4802 ldr r0, [pc, #8] ; (80038e0 ) 80038d6: f001 fba2 bl 800501e /* USER CODE BEGIN CAN2_TX_IRQn 1 */ /* USER CODE END CAN2_TX_IRQn 1 */ } 80038da: bf00 nop 80038dc: bd80 pop {r7, pc} 80038de: bf00 nop 80038e0: 200000e4 .word 0x200000e4 080038e4 : /** * @brief This function handles CAN2 RX1 interrupt. */ void CAN2_RX1_IRQHandler(void) { 80038e4: b580 push {r7, lr} 80038e6: af00 add r7, sp, #0 /* USER CODE BEGIN CAN2_RX1_IRQn 0 */ /* USER CODE END CAN2_RX1_IRQn 0 */ HAL_CAN_IRQHandler(&hcan2); 80038e8: 4802 ldr r0, [pc, #8] ; (80038f4 ) 80038ea: f001 fb98 bl 800501e /* USER CODE BEGIN CAN2_RX1_IRQn 1 */ /* USER CODE END CAN2_RX1_IRQn 1 */ } 80038ee: bf00 nop 80038f0: bd80 pop {r7, pc} 80038f2: bf00 nop 80038f4: 200000e4 .word 0x200000e4 080038f8 <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 80038f8: b480 push {r7} 80038fa: af00 add r7, sp, #0 return 1; 80038fc: 2301 movs r3, #1 } 80038fe: 4618 mov r0, r3 8003900: 46bd mov sp, r7 8003902: bc80 pop {r7} 8003904: 4770 bx lr 08003906 <_kill>: int _kill(int pid, int sig) { 8003906: b580 push {r7, lr} 8003908: b082 sub sp, #8 800390a: af00 add r7, sp, #0 800390c: 6078 str r0, [r7, #4] 800390e: 6039 str r1, [r7, #0] (void)pid; (void)sig; errno = EINVAL; 8003910: f003 feaa bl 8007668 <__errno> 8003914: 4603 mov r3, r0 8003916: 2216 movs r2, #22 8003918: 601a str r2, [r3, #0] return -1; 800391a: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 800391e: 4618 mov r0, r3 8003920: 3708 adds r7, #8 8003922: 46bd mov sp, r7 8003924: bd80 pop {r7, pc} 08003926 <_exit>: void _exit (int status) { 8003926: b580 push {r7, lr} 8003928: b082 sub sp, #8 800392a: af00 add r7, sp, #0 800392c: 6078 str r0, [r7, #4] _kill(status, -1); 800392e: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8003932: 6878 ldr r0, [r7, #4] 8003934: f7ff ffe7 bl 8003906 <_kill> while (1) {} /* Make sure we hang here */ 8003938: e7fe b.n 8003938 <_exit+0x12> 0800393a <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 800393a: b580 push {r7, lr} 800393c: b086 sub sp, #24 800393e: af00 add r7, sp, #0 8003940: 60f8 str r0, [r7, #12] 8003942: 60b9 str r1, [r7, #8] 8003944: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8003946: 2300 movs r3, #0 8003948: 617b str r3, [r7, #20] 800394a: e00a b.n 8003962 <_read+0x28> { *ptr++ = __io_getchar(); 800394c: f3af 8000 nop.w 8003950: 4601 mov r1, r0 8003952: 68bb ldr r3, [r7, #8] 8003954: 1c5a adds r2, r3, #1 8003956: 60ba str r2, [r7, #8] 8003958: b2ca uxtb r2, r1 800395a: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 800395c: 697b ldr r3, [r7, #20] 800395e: 3301 adds r3, #1 8003960: 617b str r3, [r7, #20] 8003962: 697a ldr r2, [r7, #20] 8003964: 687b ldr r3, [r7, #4] 8003966: 429a cmp r2, r3 8003968: dbf0 blt.n 800394c <_read+0x12> } return len; 800396a: 687b ldr r3, [r7, #4] } 800396c: 4618 mov r0, r3 800396e: 3718 adds r7, #24 8003970: 46bd mov sp, r7 8003972: bd80 pop {r7, pc} 08003974 <_close>: } return len; } int _close(int file) { 8003974: b480 push {r7} 8003976: b083 sub sp, #12 8003978: af00 add r7, sp, #0 800397a: 6078 str r0, [r7, #4] (void)file; return -1; 800397c: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff } 8003980: 4618 mov r0, r3 8003982: 370c adds r7, #12 8003984: 46bd mov sp, r7 8003986: bc80 pop {r7} 8003988: 4770 bx lr 0800398a <_fstat>: int _fstat(int file, struct stat *st) { 800398a: b480 push {r7} 800398c: b083 sub sp, #12 800398e: af00 add r7, sp, #0 8003990: 6078 str r0, [r7, #4] 8003992: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 8003994: 683b ldr r3, [r7, #0] 8003996: f44f 5200 mov.w r2, #8192 ; 0x2000 800399a: 605a str r2, [r3, #4] return 0; 800399c: 2300 movs r3, #0 } 800399e: 4618 mov r0, r3 80039a0: 370c adds r7, #12 80039a2: 46bd mov sp, r7 80039a4: bc80 pop {r7} 80039a6: 4770 bx lr 080039a8 <_isatty>: int _isatty(int file) { 80039a8: b480 push {r7} 80039aa: b083 sub sp, #12 80039ac: af00 add r7, sp, #0 80039ae: 6078 str r0, [r7, #4] (void)file; return 1; 80039b0: 2301 movs r3, #1 } 80039b2: 4618 mov r0, r3 80039b4: 370c adds r7, #12 80039b6: 46bd mov sp, r7 80039b8: bc80 pop {r7} 80039ba: 4770 bx lr 080039bc <_lseek>: int _lseek(int file, int ptr, int dir) { 80039bc: b480 push {r7} 80039be: b085 sub sp, #20 80039c0: af00 add r7, sp, #0 80039c2: 60f8 str r0, [r7, #12] 80039c4: 60b9 str r1, [r7, #8] 80039c6: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 80039c8: 2300 movs r3, #0 } 80039ca: 4618 mov r0, r3 80039cc: 3714 adds r7, #20 80039ce: 46bd mov sp, r7 80039d0: bc80 pop {r7} 80039d2: 4770 bx lr 080039d4 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 80039d4: b580 push {r7, lr} 80039d6: b086 sub sp, #24 80039d8: af00 add r7, sp, #0 80039da: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 80039dc: 4a14 ldr r2, [pc, #80] ; (8003a30 <_sbrk+0x5c>) 80039de: 4b15 ldr r3, [pc, #84] ; (8003a34 <_sbrk+0x60>) 80039e0: 1ad3 subs r3, r2, r3 80039e2: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 80039e4: 697b ldr r3, [r7, #20] 80039e6: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 80039e8: 4b13 ldr r3, [pc, #76] ; (8003a38 <_sbrk+0x64>) 80039ea: 681b ldr r3, [r3, #0] 80039ec: 2b00 cmp r3, #0 80039ee: d102 bne.n 80039f6 <_sbrk+0x22> { __sbrk_heap_end = &_end; 80039f0: 4b11 ldr r3, [pc, #68] ; (8003a38 <_sbrk+0x64>) 80039f2: 4a12 ldr r2, [pc, #72] ; (8003a3c <_sbrk+0x68>) 80039f4: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 80039f6: 4b10 ldr r3, [pc, #64] ; (8003a38 <_sbrk+0x64>) 80039f8: 681a ldr r2, [r3, #0] 80039fa: 687b ldr r3, [r7, #4] 80039fc: 4413 add r3, r2 80039fe: 693a ldr r2, [r7, #16] 8003a00: 429a cmp r2, r3 8003a02: d207 bcs.n 8003a14 <_sbrk+0x40> { errno = ENOMEM; 8003a04: f003 fe30 bl 8007668 <__errno> 8003a08: 4603 mov r3, r0 8003a0a: 220c movs r2, #12 8003a0c: 601a str r2, [r3, #0] return (void *)-1; 8003a0e: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff 8003a12: e009 b.n 8003a28 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 8003a14: 4b08 ldr r3, [pc, #32] ; (8003a38 <_sbrk+0x64>) 8003a16: 681b ldr r3, [r3, #0] 8003a18: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 8003a1a: 4b07 ldr r3, [pc, #28] ; (8003a38 <_sbrk+0x64>) 8003a1c: 681a ldr r2, [r3, #0] 8003a1e: 687b ldr r3, [r7, #4] 8003a20: 4413 add r3, r2 8003a22: 4a05 ldr r2, [pc, #20] ; (8003a38 <_sbrk+0x64>) 8003a24: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 8003a26: 68fb ldr r3, [r7, #12] } 8003a28: 4618 mov r0, r3 8003a2a: 3718 adds r7, #24 8003a2c: 46bd mov sp, r7 8003a2e: bd80 pop {r7, pc} 8003a30: 20010000 .word 0x20010000 8003a34: 00000400 .word 0x00000400 8003a38: 2000312c .word 0x2000312c 8003a3c: 20003188 .word 0x20003188 08003a40 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 8003a40: b480 push {r7} 8003a42: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 8003a44: bf00 nop 8003a46: 46bd mov sp, r7 8003a48: bc80 pop {r7} 8003a4a: 4770 bx lr 08003a4c : UART_HandleTypeDef huart2; /* USART2 init function */ void MX_USART2_UART_Init(void) { 8003a4c: b580 push {r7, lr} 8003a4e: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 8003a50: 4b11 ldr r3, [pc, #68] ; (8003a98 ) 8003a52: 4a12 ldr r2, [pc, #72] ; (8003a9c ) 8003a54: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 8003a56: 4b10 ldr r3, [pc, #64] ; (8003a98 ) 8003a58: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8003a5c: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 8003a5e: 4b0e ldr r3, [pc, #56] ; (8003a98 ) 8003a60: 2200 movs r2, #0 8003a62: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 8003a64: 4b0c ldr r3, [pc, #48] ; (8003a98 ) 8003a66: 2200 movs r2, #0 8003a68: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 8003a6a: 4b0b ldr r3, [pc, #44] ; (8003a98 ) 8003a6c: 2200 movs r2, #0 8003a6e: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 8003a70: 4b09 ldr r3, [pc, #36] ; (8003a98 ) 8003a72: 220c movs r2, #12 8003a74: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8003a76: 4b08 ldr r3, [pc, #32] ; (8003a98 ) 8003a78: 2200 movs r2, #0 8003a7a: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 8003a7c: 4b06 ldr r3, [pc, #24] ; (8003a98 ) 8003a7e: 2200 movs r2, #0 8003a80: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 8003a82: 4805 ldr r0, [pc, #20] ; (8003a98 ) 8003a84: f003 f890 bl 8006ba8 8003a88: 4603 mov r3, r0 8003a8a: 2b00 cmp r3, #0 8003a8c: d001 beq.n 8003a92 { Error_Handler(); 8003a8e: f7ff fd97 bl 80035c0 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 8003a92: bf00 nop 8003a94: bd80 pop {r7, pc} 8003a96: bf00 nop 8003a98: 20003130 .word 0x20003130 8003a9c: 40004400 .word 0x40004400 08003aa0 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 8003aa0: b580 push {r7, lr} 8003aa2: b08a sub sp, #40 ; 0x28 8003aa4: af00 add r7, sp, #0 8003aa6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003aa8: f107 0314 add.w r3, r7, #20 8003aac: 2200 movs r2, #0 8003aae: 601a str r2, [r3, #0] 8003ab0: 605a str r2, [r3, #4] 8003ab2: 609a str r2, [r3, #8] 8003ab4: 60da str r2, [r3, #12] if(uartHandle->Instance==USART2) 8003ab6: 687b ldr r3, [r7, #4] 8003ab8: 681b ldr r3, [r3, #0] 8003aba: 4a26 ldr r2, [pc, #152] ; (8003b54 ) 8003abc: 4293 cmp r3, r2 8003abe: d145 bne.n 8003b4c { /* USER CODE BEGIN USART2_MspInit 0 */ /* USER CODE END USART2_MspInit 0 */ /* USART2 clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); 8003ac0: 4b25 ldr r3, [pc, #148] ; (8003b58 ) 8003ac2: 69db ldr r3, [r3, #28] 8003ac4: 4a24 ldr r2, [pc, #144] ; (8003b58 ) 8003ac6: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8003aca: 61d3 str r3, [r2, #28] 8003acc: 4b22 ldr r3, [pc, #136] ; (8003b58 ) 8003ace: 69db ldr r3, [r3, #28] 8003ad0: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003ad4: 613b str r3, [r7, #16] 8003ad6: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOD_CLK_ENABLE(); 8003ad8: 4b1f ldr r3, [pc, #124] ; (8003b58 ) 8003ada: 699b ldr r3, [r3, #24] 8003adc: 4a1e ldr r2, [pc, #120] ; (8003b58 ) 8003ade: f043 0320 orr.w r3, r3, #32 8003ae2: 6193 str r3, [r2, #24] 8003ae4: 4b1c ldr r3, [pc, #112] ; (8003b58 ) 8003ae6: 699b ldr r3, [r3, #24] 8003ae8: f003 0320 and.w r3, r3, #32 8003aec: 60fb str r3, [r7, #12] 8003aee: 68fb ldr r3, [r7, #12] /**USART2 GPIO Configuration PD5 ------> USART2_TX PD6 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_5; 8003af0: 2320 movs r3, #32 8003af2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003af4: 2302 movs r3, #2 8003af6: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8003af8: 2303 movs r3, #3 8003afa: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8003afc: f107 0314 add.w r3, r7, #20 8003b00: 4619 mov r1, r3 8003b02: 4816 ldr r0, [pc, #88] ; (8003b5c ) 8003b04: f001 feda bl 80058bc GPIO_InitStruct.Pin = GPIO_PIN_6; 8003b08: 2340 movs r3, #64 ; 0x40 8003b0a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8003b0c: 2300 movs r3, #0 8003b0e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003b10: 2300 movs r3, #0 8003b12: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8003b14: f107 0314 add.w r3, r7, #20 8003b18: 4619 mov r1, r3 8003b1a: 4810 ldr r0, [pc, #64] ; (8003b5c ) 8003b1c: f001 fece bl 80058bc __HAL_AFIO_REMAP_USART2_ENABLE(); 8003b20: 4b0f ldr r3, [pc, #60] ; (8003b60 ) 8003b22: 685b ldr r3, [r3, #4] 8003b24: 627b str r3, [r7, #36] ; 0x24 8003b26: 6a7b ldr r3, [r7, #36] ; 0x24 8003b28: f043 63e0 orr.w r3, r3, #117440512 ; 0x7000000 8003b2c: 627b str r3, [r7, #36] ; 0x24 8003b2e: 6a7b ldr r3, [r7, #36] ; 0x24 8003b30: f043 0308 orr.w r3, r3, #8 8003b34: 627b str r3, [r7, #36] ; 0x24 8003b36: 4a0a ldr r2, [pc, #40] ; (8003b60 ) 8003b38: 6a7b ldr r3, [r7, #36] ; 0x24 8003b3a: 6053 str r3, [r2, #4] /* USART2 interrupt Init */ HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); 8003b3c: 2200 movs r2, #0 8003b3e: 2100 movs r1, #0 8003b40: 2026 movs r0, #38 ; 0x26 8003b42: f001 fd42 bl 80055ca HAL_NVIC_EnableIRQ(USART2_IRQn); 8003b46: 2026 movs r0, #38 ; 0x26 8003b48: f001 fd5b bl 8005602 /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 8003b4c: bf00 nop 8003b4e: 3728 adds r7, #40 ; 0x28 8003b50: 46bd mov sp, r7 8003b52: bd80 pop {r7, pc} 8003b54: 40004400 .word 0x40004400 8003b58: 40021000 .word 0x40021000 8003b5c: 40011400 .word 0x40011400 8003b60: 40010000 .word 0x40010000 08003b64 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 8003b64: f7ff ff6c bl 8003a40 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8003b68: 480b ldr r0, [pc, #44] ; (8003b98 ) ldr r1, =_edata 8003b6a: 490c ldr r1, [pc, #48] ; (8003b9c ) ldr r2, =_sidata 8003b6c: 4a0c ldr r2, [pc, #48] ; (8003ba0 ) movs r3, #0 8003b6e: 2300 movs r3, #0 b LoopCopyDataInit 8003b70: e002 b.n 8003b78 08003b72 : CopyDataInit: ldr r4, [r2, r3] 8003b72: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8003b74: 50c4 str r4, [r0, r3] adds r3, r3, #4 8003b76: 3304 adds r3, #4 08003b78 : LoopCopyDataInit: adds r4, r0, r3 8003b78: 18c4 adds r4, r0, r3 cmp r4, r1 8003b7a: 428c cmp r4, r1 bcc CopyDataInit 8003b7c: d3f9 bcc.n 8003b72 /* Zero fill the bss segment. */ ldr r2, =_sbss 8003b7e: 4a09 ldr r2, [pc, #36] ; (8003ba4 ) ldr r4, =_ebss 8003b80: 4c09 ldr r4, [pc, #36] ; (8003ba8 ) movs r3, #0 8003b82: 2300 movs r3, #0 b LoopFillZerobss 8003b84: e001 b.n 8003b8a 08003b86 : FillZerobss: str r3, [r2] 8003b86: 6013 str r3, [r2, #0] adds r2, r2, #4 8003b88: 3204 adds r2, #4 08003b8a : LoopFillZerobss: cmp r2, r4 8003b8a: 42a2 cmp r2, r4 bcc FillZerobss 8003b8c: d3fb bcc.n 8003b86 /* Call static constructors */ bl __libc_init_array 8003b8e: f003 fe3d bl 800780c <__libc_init_array> /* Call the application's entry point.*/ bl main 8003b92: f7ff fc77 bl 8003484
bx lr 8003b96: 4770 bx lr ldr r0, =_sdata 8003b98: 20000000 .word 0x20000000 ldr r1, =_edata 8003b9c: 20000070 .word 0x20000070 ldr r2, =_sidata 8003ba0: 08008f74 .word 0x08008f74 ldr r2, =_sbss 8003ba4: 20000070 .word 0x20000070 ldr r4, =_ebss 8003ba8: 20003188 .word 0x20003188 08003bac : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8003bac: e7fe b.n 8003bac ... 08003bb0 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8003bb0: b580 push {r7, lr} 8003bb2: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8003bb4: 4b08 ldr r3, [pc, #32] ; (8003bd8 ) 8003bb6: 681b ldr r3, [r3, #0] 8003bb8: 4a07 ldr r2, [pc, #28] ; (8003bd8 ) 8003bba: f043 0310 orr.w r3, r3, #16 8003bbe: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8003bc0: 2003 movs r0, #3 8003bc2: f001 fcf7 bl 80055b4 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8003bc6: 200f movs r0, #15 8003bc8: f000 f808 bl 8003bdc /* Init the low level hardware */ HAL_MspInit(); 8003bcc: f7ff fe12 bl 80037f4 /* Return function status */ return HAL_OK; 8003bd0: 2300 movs r3, #0 } 8003bd2: 4618 mov r0, r3 8003bd4: bd80 pop {r7, pc} 8003bd6: bf00 nop 8003bd8: 40022000 .word 0x40022000 08003bdc : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8003bdc: b580 push {r7, lr} 8003bde: b082 sub sp, #8 8003be0: af00 add r7, sp, #0 8003be2: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8003be4: 4b12 ldr r3, [pc, #72] ; (8003c30 ) 8003be6: 681a ldr r2, [r3, #0] 8003be8: 4b12 ldr r3, [pc, #72] ; (8003c34 ) 8003bea: 781b ldrb r3, [r3, #0] 8003bec: 4619 mov r1, r3 8003bee: f44f 737a mov.w r3, #1000 ; 0x3e8 8003bf2: fbb3 f3f1 udiv r3, r3, r1 8003bf6: fbb2 f3f3 udiv r3, r2, r3 8003bfa: 4618 mov r0, r3 8003bfc: f001 fd0f bl 800561e 8003c00: 4603 mov r3, r0 8003c02: 2b00 cmp r3, #0 8003c04: d001 beq.n 8003c0a { return HAL_ERROR; 8003c06: 2301 movs r3, #1 8003c08: e00e b.n 8003c28 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8003c0a: 687b ldr r3, [r7, #4] 8003c0c: 2b0f cmp r3, #15 8003c0e: d80a bhi.n 8003c26 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8003c10: 2200 movs r2, #0 8003c12: 6879 ldr r1, [r7, #4] 8003c14: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8003c18: f001 fcd7 bl 80055ca uwTickPrio = TickPriority; 8003c1c: 4a06 ldr r2, [pc, #24] ; (8003c38 ) 8003c1e: 687b ldr r3, [r7, #4] 8003c20: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8003c22: 2300 movs r3, #0 8003c24: e000 b.n 8003c28 return HAL_ERROR; 8003c26: 2301 movs r3, #1 } 8003c28: 4618 mov r0, r3 8003c2a: 3708 adds r7, #8 8003c2c: 46bd mov sp, r7 8003c2e: bd80 pop {r7, pc} 8003c30: 20000000 .word 0x20000000 8003c34: 20000008 .word 0x20000008 8003c38: 20000004 .word 0x20000004 08003c3c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8003c3c: b480 push {r7} 8003c3e: af00 add r7, sp, #0 uwTick += uwTickFreq; 8003c40: 4b05 ldr r3, [pc, #20] ; (8003c58 ) 8003c42: 781b ldrb r3, [r3, #0] 8003c44: 461a mov r2, r3 8003c46: 4b05 ldr r3, [pc, #20] ; (8003c5c ) 8003c48: 681b ldr r3, [r3, #0] 8003c4a: 4413 add r3, r2 8003c4c: 4a03 ldr r2, [pc, #12] ; (8003c5c ) 8003c4e: 6013 str r3, [r2, #0] } 8003c50: bf00 nop 8003c52: 46bd mov sp, r7 8003c54: bc80 pop {r7} 8003c56: 4770 bx lr 8003c58: 20000008 .word 0x20000008 8003c5c: 20003174 .word 0x20003174 08003c60 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8003c60: b480 push {r7} 8003c62: af00 add r7, sp, #0 return uwTick; 8003c64: 4b02 ldr r3, [pc, #8] ; (8003c70 ) 8003c66: 681b ldr r3, [r3, #0] } 8003c68: 4618 mov r0, r3 8003c6a: 46bd mov sp, r7 8003c6c: bc80 pop {r7} 8003c6e: 4770 bx lr 8003c70: 20003174 .word 0x20003174 08003c74 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8003c74: b580 push {r7, lr} 8003c76: b084 sub sp, #16 8003c78: af00 add r7, sp, #0 8003c7a: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8003c7c: f7ff fff0 bl 8003c60 8003c80: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8003c82: 687b ldr r3, [r7, #4] 8003c84: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8003c86: 68fb ldr r3, [r7, #12] 8003c88: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 8003c8c: d005 beq.n 8003c9a { wait += (uint32_t)(uwTickFreq); 8003c8e: 4b0a ldr r3, [pc, #40] ; (8003cb8 ) 8003c90: 781b ldrb r3, [r3, #0] 8003c92: 461a mov r2, r3 8003c94: 68fb ldr r3, [r7, #12] 8003c96: 4413 add r3, r2 8003c98: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 8003c9a: bf00 nop 8003c9c: f7ff ffe0 bl 8003c60 8003ca0: 4602 mov r2, r0 8003ca2: 68bb ldr r3, [r7, #8] 8003ca4: 1ad3 subs r3, r2, r3 8003ca6: 68fa ldr r2, [r7, #12] 8003ca8: 429a cmp r2, r3 8003caa: d8f7 bhi.n 8003c9c { } } 8003cac: bf00 nop 8003cae: bf00 nop 8003cb0: 3710 adds r7, #16 8003cb2: 46bd mov sp, r7 8003cb4: bd80 pop {r7, pc} 8003cb6: bf00 nop 8003cb8: 20000008 .word 0x20000008 08003cbc : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 8003cbc: b580 push {r7, lr} 8003cbe: b086 sub sp, #24 8003cc0: af00 add r7, sp, #0 8003cc2: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8003cc4: 2300 movs r3, #0 8003cc6: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 8003cc8: 2300 movs r3, #0 8003cca: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 8003ccc: 2300 movs r3, #0 8003cce: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 8003cd0: 2300 movs r3, #0 8003cd2: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 8003cd4: 687b ldr r3, [r7, #4] 8003cd6: 2b00 cmp r3, #0 8003cd8: d101 bne.n 8003cde { return HAL_ERROR; 8003cda: 2301 movs r3, #1 8003cdc: e0be b.n 8003e5c assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 8003cde: 687b ldr r3, [r7, #4] 8003ce0: 689b ldr r3, [r3, #8] 8003ce2: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8003ce4: 687b ldr r3, [r7, #4] 8003ce6: 6a9b ldr r3, [r3, #40] ; 0x28 8003ce8: 2b00 cmp r3, #0 8003cea: d109 bne.n 8003d00 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 8003cec: 687b ldr r3, [r7, #4] 8003cee: 2200 movs r2, #0 8003cf0: 62da str r2, [r3, #44] ; 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 8003cf2: 687b ldr r3, [r7, #4] 8003cf4: 2200 movs r2, #0 8003cf6: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8003cfa: 6878 ldr r0, [r7, #4] 8003cfc: f7fd f934 bl 8000f68 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 8003d00: 6878 ldr r0, [r7, #4] 8003d02: f000 fbf1 bl 80044e8 8003d06: 4603 mov r3, r0 8003d08: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 8003d0a: 687b ldr r3, [r7, #4] 8003d0c: 6a9b ldr r3, [r3, #40] ; 0x28 8003d0e: f003 0310 and.w r3, r3, #16 8003d12: 2b00 cmp r3, #0 8003d14: f040 8099 bne.w 8003e4a 8003d18: 7dfb ldrb r3, [r7, #23] 8003d1a: 2b00 cmp r3, #0 8003d1c: f040 8095 bne.w 8003e4a (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8003d20: 687b ldr r3, [r7, #4] 8003d22: 6a9b ldr r3, [r3, #40] ; 0x28 8003d24: f423 5388 bic.w r3, r3, #4352 ; 0x1100 8003d28: f023 0302 bic.w r3, r3, #2 8003d2c: f043 0202 orr.w r2, r3, #2 8003d30: 687b ldr r3, [r7, #4] 8003d32: 629a str r2, [r3, #40] ; 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 8003d34: 687b ldr r3, [r7, #4] 8003d36: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8003d38: 687b ldr r3, [r7, #4] 8003d3a: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 8003d3c: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 8003d3e: 687b ldr r3, [r7, #4] 8003d40: 7b1b ldrb r3, [r3, #12] 8003d42: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8003d44: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 8003d46: 68ba ldr r2, [r7, #8] 8003d48: 4313 orrs r3, r2 8003d4a: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 8003d4c: 687b ldr r3, [r7, #4] 8003d4e: 689b ldr r3, [r3, #8] 8003d50: f5b3 7f80 cmp.w r3, #256 ; 0x100 8003d54: d003 beq.n 8003d5e 8003d56: 687b ldr r3, [r7, #4] 8003d58: 689b ldr r3, [r3, #8] 8003d5a: 2b01 cmp r3, #1 8003d5c: d102 bne.n 8003d64 8003d5e: f44f 7380 mov.w r3, #256 ; 0x100 8003d62: e000 b.n 8003d66 8003d64: 2300 movs r3, #0 8003d66: 693a ldr r2, [r7, #16] 8003d68: 4313 orrs r3, r2 8003d6a: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 8003d6c: 687b ldr r3, [r7, #4] 8003d6e: 7d1b ldrb r3, [r3, #20] 8003d70: 2b01 cmp r3, #1 8003d72: d119 bne.n 8003da8 { if (hadc->Init.ContinuousConvMode == DISABLE) 8003d74: 687b ldr r3, [r7, #4] 8003d76: 7b1b ldrb r3, [r3, #12] 8003d78: 2b00 cmp r3, #0 8003d7a: d109 bne.n 8003d90 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 8003d7c: 687b ldr r3, [r7, #4] 8003d7e: 699b ldr r3, [r3, #24] 8003d80: 3b01 subs r3, #1 8003d82: 035a lsls r2, r3, #13 8003d84: 693b ldr r3, [r7, #16] 8003d86: 4313 orrs r3, r2 8003d88: f443 6300 orr.w r3, r3, #2048 ; 0x800 8003d8c: 613b str r3, [r7, #16] 8003d8e: e00b b.n 8003da8 { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8003d90: 687b ldr r3, [r7, #4] 8003d92: 6a9b ldr r3, [r3, #40] ; 0x28 8003d94: f043 0220 orr.w r2, r3, #32 8003d98: 687b ldr r3, [r7, #4] 8003d9a: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8003d9c: 687b ldr r3, [r7, #4] 8003d9e: 6adb ldr r3, [r3, #44] ; 0x2c 8003da0: f043 0201 orr.w r2, r3, #1 8003da4: 687b ldr r3, [r7, #4] 8003da6: 62da str r2, [r3, #44] ; 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 8003da8: 687b ldr r3, [r7, #4] 8003daa: 681b ldr r3, [r3, #0] 8003dac: 685b ldr r3, [r3, #4] 8003dae: f423 4169 bic.w r1, r3, #59648 ; 0xe900 8003db2: 687b ldr r3, [r7, #4] 8003db4: 681b ldr r3, [r3, #0] 8003db6: 693a ldr r2, [r7, #16] 8003db8: 430a orrs r2, r1 8003dba: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 8003dbc: 687b ldr r3, [r7, #4] 8003dbe: 681b ldr r3, [r3, #0] 8003dc0: 689a ldr r2, [r3, #8] 8003dc2: 4b28 ldr r3, [pc, #160] ; (8003e64 ) 8003dc4: 4013 ands r3, r2 8003dc6: 687a ldr r2, [r7, #4] 8003dc8: 6812 ldr r2, [r2, #0] 8003dca: 68b9 ldr r1, [r7, #8] 8003dcc: 430b orrs r3, r1 8003dce: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 8003dd0: 687b ldr r3, [r7, #4] 8003dd2: 689b ldr r3, [r3, #8] 8003dd4: f5b3 7f80 cmp.w r3, #256 ; 0x100 8003dd8: d003 beq.n 8003de2 8003dda: 687b ldr r3, [r7, #4] 8003ddc: 689b ldr r3, [r3, #8] 8003dde: 2b01 cmp r3, #1 8003de0: d104 bne.n 8003dec { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 8003de2: 687b ldr r3, [r7, #4] 8003de4: 691b ldr r3, [r3, #16] 8003de6: 3b01 subs r3, #1 8003de8: 051b lsls r3, r3, #20 8003dea: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 8003dec: 687b ldr r3, [r7, #4] 8003dee: 681b ldr r3, [r3, #0] 8003df0: 6adb ldr r3, [r3, #44] ; 0x2c 8003df2: f423 0170 bic.w r1, r3, #15728640 ; 0xf00000 8003df6: 687b ldr r3, [r7, #4] 8003df8: 681b ldr r3, [r3, #0] 8003dfa: 68fa ldr r2, [r7, #12] 8003dfc: 430a orrs r2, r1 8003dfe: 62da str r2, [r3, #44] ; 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8003e00: 687b ldr r3, [r7, #4] 8003e02: 681b ldr r3, [r3, #0] 8003e04: 689a ldr r2, [r3, #8] 8003e06: 4b18 ldr r3, [pc, #96] ; (8003e68 ) 8003e08: 4013 ands r3, r2 8003e0a: 68ba ldr r2, [r7, #8] 8003e0c: 429a cmp r2, r3 8003e0e: d10b bne.n 8003e28 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8003e10: 687b ldr r3, [r7, #4] 8003e12: 2200 movs r2, #0 8003e14: 62da str r2, [r3, #44] ; 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 8003e16: 687b ldr r3, [r7, #4] 8003e18: 6a9b ldr r3, [r3, #40] ; 0x28 8003e1a: f023 0303 bic.w r3, r3, #3 8003e1e: f043 0201 orr.w r2, r3, #1 8003e22: 687b ldr r3, [r7, #4] 8003e24: 629a str r2, [r3, #40] ; 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8003e26: e018 b.n 8003e5a HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8003e28: 687b ldr r3, [r7, #4] 8003e2a: 6a9b ldr r3, [r3, #40] ; 0x28 8003e2c: f023 0312 bic.w r3, r3, #18 8003e30: f043 0210 orr.w r2, r3, #16 8003e34: 687b ldr r3, [r7, #4] 8003e36: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8003e38: 687b ldr r3, [r7, #4] 8003e3a: 6adb ldr r3, [r3, #44] ; 0x2c 8003e3c: f043 0201 orr.w r2, r3, #1 8003e40: 687b ldr r3, [r7, #4] 8003e42: 62da str r2, [r3, #44] ; 0x2c tmp_hal_status = HAL_ERROR; 8003e44: 2301 movs r3, #1 8003e46: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8003e48: e007 b.n 8003e5a } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8003e4a: 687b ldr r3, [r7, #4] 8003e4c: 6a9b ldr r3, [r3, #40] ; 0x28 8003e4e: f043 0210 orr.w r2, r3, #16 8003e52: 687b ldr r3, [r7, #4] 8003e54: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 8003e56: 2301 movs r3, #1 8003e58: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 8003e5a: 7dfb ldrb r3, [r7, #23] } 8003e5c: 4618 mov r0, r3 8003e5e: 3718 adds r7, #24 8003e60: 46bd mov sp, r7 8003e62: bd80 pop {r7, pc} 8003e64: ffe1f7fd .word 0xffe1f7fd 8003e68: ff1f0efe .word 0xff1f0efe 08003e6c : * Interruptions enabled in this function: None. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { 8003e6c: b580 push {r7, lr} 8003e6e: b084 sub sp, #16 8003e70: af00 add r7, sp, #0 8003e72: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8003e74: 2300 movs r3, #0 8003e76: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 8003e78: 687b ldr r3, [r7, #4] 8003e7a: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8003e7e: 2b01 cmp r3, #1 8003e80: d101 bne.n 8003e86 8003e82: 2302 movs r3, #2 8003e84: e098 b.n 8003fb8 8003e86: 687b ldr r3, [r7, #4] 8003e88: 2201 movs r2, #1 8003e8a: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 8003e8e: 6878 ldr r0, [r7, #4] 8003e90: f000 fad0 bl 8004434 8003e94: 4603 mov r3, r0 8003e96: 73fb strb r3, [r7, #15] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 8003e98: 7bfb ldrb r3, [r7, #15] 8003e9a: 2b00 cmp r3, #0 8003e9c: f040 8087 bne.w 8003fae { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8003ea0: 687b ldr r3, [r7, #4] 8003ea2: 6a9b ldr r3, [r3, #40] ; 0x28 8003ea4: f423 7340 bic.w r3, r3, #768 ; 0x300 8003ea8: f023 0301 bic.w r3, r3, #1 8003eac: f443 7280 orr.w r2, r3, #256 ; 0x100 8003eb0: 687b ldr r3, [r7, #4] 8003eb2: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 8003eb4: 687b ldr r3, [r7, #4] 8003eb6: 681b ldr r3, [r3, #0] 8003eb8: 4a41 ldr r2, [pc, #260] ; (8003fc0 ) 8003eba: 4293 cmp r3, r2 8003ebc: d105 bne.n 8003eca 8003ebe: 4b41 ldr r3, [pc, #260] ; (8003fc4 ) 8003ec0: 685b ldr r3, [r3, #4] 8003ec2: f403 2370 and.w r3, r3, #983040 ; 0xf0000 8003ec6: 2b00 cmp r3, #0 8003ec8: d115 bne.n 8003ef6 { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8003eca: 687b ldr r3, [r7, #4] 8003ecc: 6a9b ldr r3, [r3, #40] ; 0x28 8003ece: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 8003ed2: 687b ldr r3, [r7, #4] 8003ed4: 629a str r2, [r3, #40] ; 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 8003ed6: 687b ldr r3, [r7, #4] 8003ed8: 681b ldr r3, [r3, #0] 8003eda: 685b ldr r3, [r3, #4] 8003edc: f403 6380 and.w r3, r3, #1024 ; 0x400 8003ee0: 2b00 cmp r3, #0 8003ee2: d026 beq.n 8003f32 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8003ee4: 687b ldr r3, [r7, #4] 8003ee6: 6a9b ldr r3, [r3, #40] ; 0x28 8003ee8: f423 5340 bic.w r3, r3, #12288 ; 0x3000 8003eec: f443 5280 orr.w r2, r3, #4096 ; 0x1000 8003ef0: 687b ldr r3, [r7, #4] 8003ef2: 629a str r2, [r3, #40] ; 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 8003ef4: e01d b.n 8003f32 } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8003ef6: 687b ldr r3, [r7, #4] 8003ef8: 6a9b ldr r3, [r3, #40] ; 0x28 8003efa: f443 1280 orr.w r2, r3, #1048576 ; 0x100000 8003efe: 687b ldr r3, [r7, #4] 8003f00: 629a str r2, [r3, #40] ; 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 8003f02: 687b ldr r3, [r7, #4] 8003f04: 681b ldr r3, [r3, #0] 8003f06: 4a2f ldr r2, [pc, #188] ; (8003fc4 ) 8003f08: 4293 cmp r3, r2 8003f0a: d004 beq.n 8003f16 8003f0c: 687b ldr r3, [r7, #4] 8003f0e: 681b ldr r3, [r3, #0] 8003f10: 4a2b ldr r2, [pc, #172] ; (8003fc0 ) 8003f12: 4293 cmp r3, r2 8003f14: d10d bne.n 8003f32 8003f16: 4b2b ldr r3, [pc, #172] ; (8003fc4 ) 8003f18: 685b ldr r3, [r3, #4] 8003f1a: f403 6380 and.w r3, r3, #1024 ; 0x400 8003f1e: 2b00 cmp r3, #0 8003f20: d007 beq.n 8003f32 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8003f22: 687b ldr r3, [r7, #4] 8003f24: 6a9b ldr r3, [r3, #40] ; 0x28 8003f26: f423 5340 bic.w r3, r3, #12288 ; 0x3000 8003f2a: f443 5280 orr.w r2, r3, #4096 ; 0x1000 8003f2e: 687b ldr r3, [r7, #4] 8003f30: 629a str r2, [r3, #40] ; 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8003f32: 687b ldr r3, [r7, #4] 8003f34: 6a9b ldr r3, [r3, #40] ; 0x28 8003f36: f403 5380 and.w r3, r3, #4096 ; 0x1000 8003f3a: 2b00 cmp r3, #0 8003f3c: d006 beq.n 8003f4c { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8003f3e: 687b ldr r3, [r7, #4] 8003f40: 6adb ldr r3, [r3, #44] ; 0x2c 8003f42: f023 0206 bic.w r2, r3, #6 8003f46: 687b ldr r3, [r7, #4] 8003f48: 62da str r2, [r3, #44] ; 0x2c 8003f4a: e002 b.n 8003f52 } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 8003f4c: 687b ldr r3, [r7, #4] 8003f4e: 2200 movs r2, #0 8003f50: 62da str r2, [r3, #44] ; 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8003f52: 687b ldr r3, [r7, #4] 8003f54: 2200 movs r2, #0 8003f56: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Clear regular group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 8003f5a: 687b ldr r3, [r7, #4] 8003f5c: 681b ldr r3, [r3, #0] 8003f5e: f06f 0202 mvn.w r2, #2 8003f62: 601a str r2, [r3, #0] /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ /* If ADC is master, ADC is enabled and conversion is started. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8003f64: 687b ldr r3, [r7, #4] 8003f66: 681b ldr r3, [r3, #0] 8003f68: 689b ldr r3, [r3, #8] 8003f6a: f403 2360 and.w r3, r3, #917504 ; 0xe0000 8003f6e: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 8003f72: d113 bne.n 8003f9c ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 8003f74: 687b ldr r3, [r7, #4] 8003f76: 681b ldr r3, [r3, #0] if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8003f78: 4a11 ldr r2, [pc, #68] ; (8003fc0 ) 8003f7a: 4293 cmp r3, r2 8003f7c: d105 bne.n 8003f8a ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 8003f7e: 4b11 ldr r3, [pc, #68] ; (8003fc4 ) 8003f80: 685b ldr r3, [r3, #4] 8003f82: f403 2370 and.w r3, r3, #983040 ; 0xf0000 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8003f86: 2b00 cmp r3, #0 8003f88: d108 bne.n 8003f9c { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 8003f8a: 687b ldr r3, [r7, #4] 8003f8c: 681b ldr r3, [r3, #0] 8003f8e: 689a ldr r2, [r3, #8] 8003f90: 687b ldr r3, [r7, #4] 8003f92: 681b ldr r3, [r3, #0] 8003f94: f442 02a0 orr.w r2, r2, #5242880 ; 0x500000 8003f98: 609a str r2, [r3, #8] 8003f9a: e00c b.n 8003fb6 } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 8003f9c: 687b ldr r3, [r7, #4] 8003f9e: 681b ldr r3, [r3, #0] 8003fa0: 689a ldr r2, [r3, #8] 8003fa2: 687b ldr r3, [r7, #4] 8003fa4: 681b ldr r3, [r3, #0] 8003fa6: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 8003faa: 609a str r2, [r3, #8] 8003fac: e003 b.n 8003fb6 } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 8003fae: 687b ldr r3, [r7, #4] 8003fb0: 2200 movs r2, #0 8003fb2: f883 2024 strb.w r2, [r3, #36] ; 0x24 } /* Return function status */ return tmp_hal_status; 8003fb6: 7bfb ldrb r3, [r7, #15] } 8003fb8: 4618 mov r0, r3 8003fba: 3710 adds r7, #16 8003fbc: 46bd mov sp, r7 8003fbe: bd80 pop {r7, pc} 8003fc0: 40012800 .word 0x40012800 8003fc4: 40012400 .word 0x40012400 08003fc8 : * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { 8003fc8: b580 push {r7, lr} 8003fca: b084 sub sp, #16 8003fcc: af00 add r7, sp, #0 8003fce: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8003fd0: 2300 movs r3, #0 8003fd2: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 8003fd4: 687b ldr r3, [r7, #4] 8003fd6: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8003fda: 2b01 cmp r3, #1 8003fdc: d101 bne.n 8003fe2 8003fde: 2302 movs r3, #2 8003fe0: e01a b.n 8004018 8003fe2: 687b ldr r3, [r7, #4] 8003fe4: 2201 movs r2, #1 8003fe6: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 8003fea: 6878 ldr r0, [r7, #4] 8003fec: f000 fa7c bl 80044e8 8003ff0: 4603 mov r3, r0 8003ff2: 73fb strb r3, [r7, #15] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8003ff4: 7bfb ldrb r3, [r7, #15] 8003ff6: 2b00 cmp r3, #0 8003ff8: d109 bne.n 800400e { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8003ffa: 687b ldr r3, [r7, #4] 8003ffc: 6a9b ldr r3, [r3, #40] ; 0x28 8003ffe: f423 5388 bic.w r3, r3, #4352 ; 0x1100 8004002: f023 0301 bic.w r3, r3, #1 8004006: f043 0201 orr.w r2, r3, #1 800400a: 687b ldr r3, [r7, #4] 800400c: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 800400e: 687b ldr r3, [r7, #4] 8004010: 2200 movs r2, #0 8004012: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 8004016: 7bfb ldrb r3, [r7, #15] } 8004018: 4618 mov r0, r3 800401a: 3710 adds r7, #16 800401c: 46bd mov sp, r7 800401e: bd80 pop {r7, pc} 08004020 : * @param hadc: ADC handle * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { 8004020: b590 push {r4, r7, lr} 8004022: b087 sub sp, #28 8004024: af00 add r7, sp, #0 8004026: 6078 str r0, [r7, #4] 8004028: 6039 str r1, [r7, #0] uint32_t tickstart = 0U; 800402a: 2300 movs r3, #0 800402c: 617b str r3, [r7, #20] /* Variables for polling in case of scan mode enabled and polling for each */ /* conversion. */ __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; 800402e: 2300 movs r3, #0 8004030: 60fb str r3, [r7, #12] uint32_t Conversion_Timeout_CPU_cycles_max = 0U; 8004032: 2300 movs r3, #0 8004034: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Get tick count */ tickstart = HAL_GetTick(); 8004036: f7ff fe13 bl 8003c60 800403a: 6178 str r0, [r7, #20] /* Verification that ADC configuration is compliant with polling for */ /* each conversion: */ /* Particular case is ADC configured in DMA mode */ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) 800403c: 687b ldr r3, [r7, #4] 800403e: 681b ldr r3, [r3, #0] 8004040: 689b ldr r3, [r3, #8] 8004042: f403 7380 and.w r3, r3, #256 ; 0x100 8004046: 2b00 cmp r3, #0 8004048: d00b beq.n 8004062 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800404a: 687b ldr r3, [r7, #4] 800404c: 6a9b ldr r3, [r3, #40] ; 0x28 800404e: f043 0220 orr.w r2, r3, #32 8004052: 687b ldr r3, [r7, #4] 8004054: 629a str r2, [r3, #40] ; 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 8004056: 687b ldr r3, [r7, #4] 8004058: 2200 movs r2, #0 800405a: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 800405e: 2301 movs r3, #1 8004060: e0d3 b.n 800420a /* from ADC conversion time (selected sampling time + conversion time of */ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ /* As flag EOC is not set after each conversion, no timeout status can */ /* be set. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 8004062: 687b ldr r3, [r7, #4] 8004064: 681b ldr r3, [r3, #0] 8004066: 685b ldr r3, [r3, #4] 8004068: f403 7380 and.w r3, r3, #256 ; 0x100 800406c: 2b00 cmp r3, #0 800406e: d131 bne.n 80040d4 HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ) 8004070: 687b ldr r3, [r7, #4] 8004072: 681b ldr r3, [r3, #0] 8004074: 6adb ldr r3, [r3, #44] ; 0x2c 8004076: f403 0370 and.w r3, r3, #15728640 ; 0xf00000 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 800407a: 2b00 cmp r3, #0 800407c: d12a bne.n 80040d4 { /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 800407e: e021 b.n 80040c4 { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 8004080: 683b ldr r3, [r7, #0] 8004082: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 8004086: d01d beq.n 80040c4 { if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) 8004088: 683b ldr r3, [r7, #0] 800408a: 2b00 cmp r3, #0 800408c: d007 beq.n 800409e 800408e: f7ff fde7 bl 8003c60 8004092: 4602 mov r2, r0 8004094: 697b ldr r3, [r7, #20] 8004096: 1ad3 subs r3, r2, r3 8004098: 683a ldr r2, [r7, #0] 800409a: 429a cmp r2, r3 800409c: d212 bcs.n 80040c4 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 800409e: 687b ldr r3, [r7, #4] 80040a0: 681b ldr r3, [r3, #0] 80040a2: 681b ldr r3, [r3, #0] 80040a4: f003 0302 and.w r3, r3, #2 80040a8: 2b00 cmp r3, #0 80040aa: d10b bne.n 80040c4 { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 80040ac: 687b ldr r3, [r7, #4] 80040ae: 6a9b ldr r3, [r3, #40] ; 0x28 80040b0: f043 0204 orr.w r2, r3, #4 80040b4: 687b ldr r3, [r7, #4] 80040b6: 629a str r2, [r3, #40] ; 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 80040b8: 687b ldr r3, [r7, #4] 80040ba: 2200 movs r2, #0 80040bc: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_TIMEOUT; 80040c0: 2303 movs r3, #3 80040c2: e0a2 b.n 800420a while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) 80040c4: 687b ldr r3, [r7, #4] 80040c6: 681b ldr r3, [r3, #0] 80040c8: 681b ldr r3, [r3, #0] 80040ca: f003 0302 and.w r3, r3, #2 80040ce: 2b00 cmp r3, #0 80040d0: d0d6 beq.n 8004080 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && 80040d2: e070 b.n 80041b6 /* Replace polling by wait for maximum conversion time */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ /* and ADC maximum conversion cycles on all channels. */ /* - Wait for the expected ADC clock cycles delay */ Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 80040d4: 4b4f ldr r3, [pc, #316] ; (8004214 ) 80040d6: 681c ldr r4, [r3, #0] 80040d8: 2002 movs r0, #2 80040da: f002 fc03 bl 80068e4 80040de: 4603 mov r3, r0 80040e0: fbb4 f2f3 udiv r2, r4, r3 * ADC_CONVCYCLES_MAX_RANGE(hadc) ); 80040e4: 687b ldr r3, [r7, #4] 80040e6: 681b ldr r3, [r3, #0] 80040e8: 6919 ldr r1, [r3, #16] 80040ea: 4b4b ldr r3, [pc, #300] ; (8004218 ) 80040ec: 400b ands r3, r1 80040ee: 2b00 cmp r3, #0 80040f0: d118 bne.n 8004124 80040f2: 687b ldr r3, [r7, #4] 80040f4: 681b ldr r3, [r3, #0] 80040f6: 68d9 ldr r1, [r3, #12] 80040f8: 4b48 ldr r3, [pc, #288] ; (800421c ) 80040fa: 400b ands r3, r1 80040fc: 2b00 cmp r3, #0 80040fe: d111 bne.n 8004124 8004100: 687b ldr r3, [r7, #4] 8004102: 681b ldr r3, [r3, #0] 8004104: 6919 ldr r1, [r3, #16] 8004106: 4b46 ldr r3, [pc, #280] ; (8004220 ) 8004108: 400b ands r3, r1 800410a: 2b00 cmp r3, #0 800410c: d108 bne.n 8004120 800410e: 687b ldr r3, [r7, #4] 8004110: 681b ldr r3, [r3, #0] 8004112: 68d9 ldr r1, [r3, #12] 8004114: 4b43 ldr r3, [pc, #268] ; (8004224 ) 8004116: 400b ands r3, r1 8004118: 2b00 cmp r3, #0 800411a: d101 bne.n 8004120 800411c: 2314 movs r3, #20 800411e: e020 b.n 8004162 8004120: 2329 movs r3, #41 ; 0x29 8004122: e01e b.n 8004162 8004124: 687b ldr r3, [r7, #4] 8004126: 681b ldr r3, [r3, #0] 8004128: 6919 ldr r1, [r3, #16] 800412a: 4b3d ldr r3, [pc, #244] ; (8004220 ) 800412c: 400b ands r3, r1 800412e: 2b00 cmp r3, #0 8004130: d106 bne.n 8004140 8004132: 687b ldr r3, [r7, #4] 8004134: 681b ldr r3, [r3, #0] 8004136: 68d9 ldr r1, [r3, #12] 8004138: 4b3a ldr r3, [pc, #232] ; (8004224 ) 800413a: 400b ands r3, r1 800413c: 2b00 cmp r3, #0 800413e: d00d beq.n 800415c 8004140: 687b ldr r3, [r7, #4] 8004142: 681b ldr r3, [r3, #0] 8004144: 6919 ldr r1, [r3, #16] 8004146: 4b38 ldr r3, [pc, #224] ; (8004228 ) 8004148: 400b ands r3, r1 800414a: 2b00 cmp r3, #0 800414c: d108 bne.n 8004160 800414e: 687b ldr r3, [r7, #4] 8004150: 681b ldr r3, [r3, #0] 8004152: 68d9 ldr r1, [r3, #12] 8004154: 4b34 ldr r3, [pc, #208] ; (8004228 ) 8004156: 400b ands r3, r1 8004158: 2b00 cmp r3, #0 800415a: d101 bne.n 8004160 800415c: 2354 movs r3, #84 ; 0x54 800415e: e000 b.n 8004162 8004160: 23fc movs r3, #252 ; 0xfc Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock 8004162: fb02 f303 mul.w r3, r2, r3 8004166: 613b str r3, [r7, #16] while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 8004168: e021 b.n 80041ae { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) 800416a: 683b ldr r3, [r7, #0] 800416c: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 8004170: d01a beq.n 80041a8 { if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) 8004172: 683b ldr r3, [r7, #0] 8004174: 2b00 cmp r3, #0 8004176: d007 beq.n 8004188 8004178: f7ff fd72 bl 8003c60 800417c: 4602 mov r2, r0 800417e: 697b ldr r3, [r7, #20] 8004180: 1ad3 subs r3, r2, r3 8004182: 683a ldr r2, [r7, #0] 8004184: 429a cmp r2, r3 8004186: d20f bcs.n 80041a8 { /* New check to avoid false timeout detection in case of preemption */ if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 8004188: 68fb ldr r3, [r7, #12] 800418a: 693a ldr r2, [r7, #16] 800418c: 429a cmp r2, r3 800418e: d90b bls.n 80041a8 { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 8004190: 687b ldr r3, [r7, #4] 8004192: 6a9b ldr r3, [r3, #40] ; 0x28 8004194: f043 0204 orr.w r2, r3, #4 8004198: 687b ldr r3, [r7, #4] 800419a: 629a str r2, [r3, #40] ; 0x28 /* Process unlocked */ __HAL_UNLOCK(hadc); 800419c: 687b ldr r3, [r7, #4] 800419e: 2200 movs r2, #0 80041a0: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_TIMEOUT; 80041a4: 2303 movs r3, #3 80041a6: e030 b.n 800420a } } } Conversion_Timeout_CPU_cycles ++; 80041a8: 68fb ldr r3, [r7, #12] 80041aa: 3301 adds r3, #1 80041ac: 60fb str r3, [r7, #12] while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 80041ae: 68fb ldr r3, [r7, #12] 80041b0: 693a ldr r2, [r7, #16] 80041b2: 429a cmp r2, r3 80041b4: d8d9 bhi.n 800416a } } /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 80041b6: 687b ldr r3, [r7, #4] 80041b8: 681b ldr r3, [r3, #0] 80041ba: f06f 0212 mvn.w r2, #18 80041be: 601a str r2, [r3, #0] /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 80041c0: 687b ldr r3, [r7, #4] 80041c2: 6a9b ldr r3, [r3, #40] ; 0x28 80041c4: f443 7200 orr.w r2, r3, #512 ; 0x200 80041c8: 687b ldr r3, [r7, #4] 80041ca: 629a str r2, [r3, #40] ; 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80041cc: 687b ldr r3, [r7, #4] 80041ce: 681b ldr r3, [r3, #0] 80041d0: 689b ldr r3, [r3, #8] 80041d2: f403 2360 and.w r3, r3, #917504 ; 0xe0000 80041d6: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 80041da: d115 bne.n 8004208 (hadc->Init.ContinuousConvMode == DISABLE) ) 80041dc: 687b ldr r3, [r7, #4] 80041de: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80041e0: 2b00 cmp r3, #0 80041e2: d111 bne.n 8004208 { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 80041e4: 687b ldr r3, [r7, #4] 80041e6: 6a9b ldr r3, [r3, #40] ; 0x28 80041e8: f423 7280 bic.w r2, r3, #256 ; 0x100 80041ec: 687b ldr r3, [r7, #4] 80041ee: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 80041f0: 687b ldr r3, [r7, #4] 80041f2: 6a9b ldr r3, [r3, #40] ; 0x28 80041f4: f403 5380 and.w r3, r3, #4096 ; 0x1000 80041f8: 2b00 cmp r3, #0 80041fa: d105 bne.n 8004208 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 80041fc: 687b ldr r3, [r7, #4] 80041fe: 6a9b ldr r3, [r3, #40] ; 0x28 8004200: f043 0201 orr.w r2, r3, #1 8004204: 687b ldr r3, [r7, #4] 8004206: 629a str r2, [r3, #40] ; 0x28 } } /* Return ADC state */ return HAL_OK; 8004208: 2300 movs r3, #0 } 800420a: 4618 mov r0, r3 800420c: 371c adds r7, #28 800420e: 46bd mov sp, r7 8004210: bd90 pop {r4, r7, pc} 8004212: bf00 nop 8004214: 20000000 .word 0x20000000 8004218: 24924924 .word 0x24924924 800421c: 00924924 .word 0x00924924 8004220: 12492492 .word 0x12492492 8004224: 00492492 .word 0x00492492 8004228: 00249249 .word 0x00249249 0800422c : * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc: ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { 800422c: b480 push {r7} 800422e: b083 sub sp, #12 8004230: af00 add r7, sp, #0 8004232: 6078 str r0, [r7, #4] /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; 8004234: 687b ldr r3, [r7, #4] 8004236: 681b ldr r3, [r3, #0] 8004238: 6cdb ldr r3, [r3, #76] ; 0x4c } 800423a: 4618 mov r0, r3 800423c: 370c adds r7, #12 800423e: 46bd mov sp, r7 8004240: bc80 pop {r7} 8004242: 4770 bx lr 08004244 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8004244: b480 push {r7} 8004246: b085 sub sp, #20 8004248: af00 add r7, sp, #0 800424a: 6078 str r0, [r7, #4] 800424c: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800424e: 2300 movs r3, #0 8004250: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 8004252: 2300 movs r3, #0 8004254: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 8004256: 687b ldr r3, [r7, #4] 8004258: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 800425c: 2b01 cmp r3, #1 800425e: d101 bne.n 8004264 8004260: 2302 movs r3, #2 8004262: e0dc b.n 800441e 8004264: 687b ldr r3, [r7, #4] 8004266: 2201 movs r2, #1 8004268: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 800426c: 683b ldr r3, [r7, #0] 800426e: 685b ldr r3, [r3, #4] 8004270: 2b06 cmp r3, #6 8004272: d81c bhi.n 80042ae { MODIFY_REG(hadc->Instance->SQR3 , 8004274: 687b ldr r3, [r7, #4] 8004276: 681b ldr r3, [r3, #0] 8004278: 6b59 ldr r1, [r3, #52] ; 0x34 800427a: 683b ldr r3, [r7, #0] 800427c: 685a ldr r2, [r3, #4] 800427e: 4613 mov r3, r2 8004280: 009b lsls r3, r3, #2 8004282: 4413 add r3, r2 8004284: 3b05 subs r3, #5 8004286: 221f movs r2, #31 8004288: fa02 f303 lsl.w r3, r2, r3 800428c: 43db mvns r3, r3 800428e: 4019 ands r1, r3 8004290: 683b ldr r3, [r7, #0] 8004292: 6818 ldr r0, [r3, #0] 8004294: 683b ldr r3, [r7, #0] 8004296: 685a ldr r2, [r3, #4] 8004298: 4613 mov r3, r2 800429a: 009b lsls r3, r3, #2 800429c: 4413 add r3, r2 800429e: 3b05 subs r3, #5 80042a0: fa00 f203 lsl.w r2, r0, r3 80042a4: 687b ldr r3, [r7, #4] 80042a6: 681b ldr r3, [r3, #0] 80042a8: 430a orrs r2, r1 80042aa: 635a str r2, [r3, #52] ; 0x34 80042ac: e03c b.n 8004328 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 80042ae: 683b ldr r3, [r7, #0] 80042b0: 685b ldr r3, [r3, #4] 80042b2: 2b0c cmp r3, #12 80042b4: d81c bhi.n 80042f0 { MODIFY_REG(hadc->Instance->SQR2 , 80042b6: 687b ldr r3, [r7, #4] 80042b8: 681b ldr r3, [r3, #0] 80042ba: 6b19 ldr r1, [r3, #48] ; 0x30 80042bc: 683b ldr r3, [r7, #0] 80042be: 685a ldr r2, [r3, #4] 80042c0: 4613 mov r3, r2 80042c2: 009b lsls r3, r3, #2 80042c4: 4413 add r3, r2 80042c6: 3b23 subs r3, #35 ; 0x23 80042c8: 221f movs r2, #31 80042ca: fa02 f303 lsl.w r3, r2, r3 80042ce: 43db mvns r3, r3 80042d0: 4019 ands r1, r3 80042d2: 683b ldr r3, [r7, #0] 80042d4: 6818 ldr r0, [r3, #0] 80042d6: 683b ldr r3, [r7, #0] 80042d8: 685a ldr r2, [r3, #4] 80042da: 4613 mov r3, r2 80042dc: 009b lsls r3, r3, #2 80042de: 4413 add r3, r2 80042e0: 3b23 subs r3, #35 ; 0x23 80042e2: fa00 f203 lsl.w r2, r0, r3 80042e6: 687b ldr r3, [r7, #4] 80042e8: 681b ldr r3, [r3, #0] 80042ea: 430a orrs r2, r1 80042ec: 631a str r2, [r3, #48] ; 0x30 80042ee: e01b b.n 8004328 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 80042f0: 687b ldr r3, [r7, #4] 80042f2: 681b ldr r3, [r3, #0] 80042f4: 6ad9 ldr r1, [r3, #44] ; 0x2c 80042f6: 683b ldr r3, [r7, #0] 80042f8: 685a ldr r2, [r3, #4] 80042fa: 4613 mov r3, r2 80042fc: 009b lsls r3, r3, #2 80042fe: 4413 add r3, r2 8004300: 3b41 subs r3, #65 ; 0x41 8004302: 221f movs r2, #31 8004304: fa02 f303 lsl.w r3, r2, r3 8004308: 43db mvns r3, r3 800430a: 4019 ands r1, r3 800430c: 683b ldr r3, [r7, #0] 800430e: 6818 ldr r0, [r3, #0] 8004310: 683b ldr r3, [r7, #0] 8004312: 685a ldr r2, [r3, #4] 8004314: 4613 mov r3, r2 8004316: 009b lsls r3, r3, #2 8004318: 4413 add r3, r2 800431a: 3b41 subs r3, #65 ; 0x41 800431c: fa00 f203 lsl.w r2, r0, r3 8004320: 687b ldr r3, [r7, #4] 8004322: 681b ldr r3, [r3, #0] 8004324: 430a orrs r2, r1 8004326: 62da str r2, [r3, #44] ; 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 8004328: 683b ldr r3, [r7, #0] 800432a: 681b ldr r3, [r3, #0] 800432c: 2b09 cmp r3, #9 800432e: d91c bls.n 800436a { MODIFY_REG(hadc->Instance->SMPR1 , 8004330: 687b ldr r3, [r7, #4] 8004332: 681b ldr r3, [r3, #0] 8004334: 68d9 ldr r1, [r3, #12] 8004336: 683b ldr r3, [r7, #0] 8004338: 681a ldr r2, [r3, #0] 800433a: 4613 mov r3, r2 800433c: 005b lsls r3, r3, #1 800433e: 4413 add r3, r2 8004340: 3b1e subs r3, #30 8004342: 2207 movs r2, #7 8004344: fa02 f303 lsl.w r3, r2, r3 8004348: 43db mvns r3, r3 800434a: 4019 ands r1, r3 800434c: 683b ldr r3, [r7, #0] 800434e: 6898 ldr r0, [r3, #8] 8004350: 683b ldr r3, [r7, #0] 8004352: 681a ldr r2, [r3, #0] 8004354: 4613 mov r3, r2 8004356: 005b lsls r3, r3, #1 8004358: 4413 add r3, r2 800435a: 3b1e subs r3, #30 800435c: fa00 f203 lsl.w r2, r0, r3 8004360: 687b ldr r3, [r7, #4] 8004362: 681b ldr r3, [r3, #0] 8004364: 430a orrs r2, r1 8004366: 60da str r2, [r3, #12] 8004368: e019 b.n 800439e ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 800436a: 687b ldr r3, [r7, #4] 800436c: 681b ldr r3, [r3, #0] 800436e: 6919 ldr r1, [r3, #16] 8004370: 683b ldr r3, [r7, #0] 8004372: 681a ldr r2, [r3, #0] 8004374: 4613 mov r3, r2 8004376: 005b lsls r3, r3, #1 8004378: 4413 add r3, r2 800437a: 2207 movs r2, #7 800437c: fa02 f303 lsl.w r3, r2, r3 8004380: 43db mvns r3, r3 8004382: 4019 ands r1, r3 8004384: 683b ldr r3, [r7, #0] 8004386: 6898 ldr r0, [r3, #8] 8004388: 683b ldr r3, [r7, #0] 800438a: 681a ldr r2, [r3, #0] 800438c: 4613 mov r3, r2 800438e: 005b lsls r3, r3, #1 8004390: 4413 add r3, r2 8004392: fa00 f203 lsl.w r2, r0, r3 8004396: 687b ldr r3, [r7, #4] 8004398: 681b ldr r3, [r3, #0] 800439a: 430a orrs r2, r1 800439c: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800439e: 683b ldr r3, [r7, #0] 80043a0: 681b ldr r3, [r3, #0] 80043a2: 2b10 cmp r3, #16 80043a4: d003 beq.n 80043ae (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 80043a6: 683b ldr r3, [r7, #0] 80043a8: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 80043aa: 2b11 cmp r3, #17 80043ac: d132 bne.n 8004414 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 80043ae: 687b ldr r3, [r7, #4] 80043b0: 681b ldr r3, [r3, #0] 80043b2: 4a1d ldr r2, [pc, #116] ; (8004428 ) 80043b4: 4293 cmp r3, r2 80043b6: d125 bne.n 8004404 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 80043b8: 687b ldr r3, [r7, #4] 80043ba: 681b ldr r3, [r3, #0] 80043bc: 689b ldr r3, [r3, #8] 80043be: f403 0300 and.w r3, r3, #8388608 ; 0x800000 80043c2: 2b00 cmp r3, #0 80043c4: d126 bne.n 8004414 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 80043c6: 687b ldr r3, [r7, #4] 80043c8: 681b ldr r3, [r3, #0] 80043ca: 689a ldr r2, [r3, #8] 80043cc: 687b ldr r3, [r7, #4] 80043ce: 681b ldr r3, [r3, #0] 80043d0: f442 0200 orr.w r2, r2, #8388608 ; 0x800000 80043d4: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 80043d6: 683b ldr r3, [r7, #0] 80043d8: 681b ldr r3, [r3, #0] 80043da: 2b10 cmp r3, #16 80043dc: d11a bne.n 8004414 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 80043de: 4b13 ldr r3, [pc, #76] ; (800442c ) 80043e0: 681b ldr r3, [r3, #0] 80043e2: 4a13 ldr r2, [pc, #76] ; (8004430 ) 80043e4: fba2 2303 umull r2, r3, r2, r3 80043e8: 0c9a lsrs r2, r3, #18 80043ea: 4613 mov r3, r2 80043ec: 009b lsls r3, r3, #2 80043ee: 4413 add r3, r2 80043f0: 005b lsls r3, r3, #1 80043f2: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80043f4: e002 b.n 80043fc { wait_loop_index--; 80043f6: 68bb ldr r3, [r7, #8] 80043f8: 3b01 subs r3, #1 80043fa: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80043fc: 68bb ldr r3, [r7, #8] 80043fe: 2b00 cmp r3, #0 8004400: d1f9 bne.n 80043f6 8004402: e007 b.n 8004414 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8004404: 687b ldr r3, [r7, #4] 8004406: 6a9b ldr r3, [r3, #40] ; 0x28 8004408: f043 0220 orr.w r2, r3, #32 800440c: 687b ldr r3, [r7, #4] 800440e: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 8004410: 2301 movs r3, #1 8004412: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8004414: 687b ldr r3, [r7, #4] 8004416: 2200 movs r2, #0 8004418: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 800441c: 7bfb ldrb r3, [r7, #15] } 800441e: 4618 mov r0, r3 8004420: 3714 adds r7, #20 8004422: 46bd mov sp, r7 8004424: bc80 pop {r7} 8004426: 4770 bx lr 8004428: 40012400 .word 0x40012400 800442c: 20000000 .word 0x20000000 8004430: 431bde83 .word 0x431bde83 08004434 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 8004434: b580 push {r7, lr} 8004436: b084 sub sp, #16 8004438: af00 add r7, sp, #0 800443a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800443c: 2300 movs r3, #0 800443e: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 8004440: 2300 movs r3, #0 8004442: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 8004444: 687b ldr r3, [r7, #4] 8004446: 681b ldr r3, [r3, #0] 8004448: 689b ldr r3, [r3, #8] 800444a: f003 0301 and.w r3, r3, #1 800444e: 2b01 cmp r3, #1 8004450: d040 beq.n 80044d4 { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 8004452: 687b ldr r3, [r7, #4] 8004454: 681b ldr r3, [r3, #0] 8004456: 689a ldr r2, [r3, #8] 8004458: 687b ldr r3, [r7, #4] 800445a: 681b ldr r3, [r3, #0] 800445c: f042 0201 orr.w r2, r2, #1 8004460: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 8004462: 4b1f ldr r3, [pc, #124] ; (80044e0 ) 8004464: 681b ldr r3, [r3, #0] 8004466: 4a1f ldr r2, [pc, #124] ; (80044e4 ) 8004468: fba2 2303 umull r2, r3, r2, r3 800446c: 0c9b lsrs r3, r3, #18 800446e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8004470: e002 b.n 8004478 { wait_loop_index--; 8004472: 68bb ldr r3, [r7, #8] 8004474: 3b01 subs r3, #1 8004476: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8004478: 68bb ldr r3, [r7, #8] 800447a: 2b00 cmp r3, #0 800447c: d1f9 bne.n 8004472 } /* Get tick count */ tickstart = HAL_GetTick(); 800447e: f7ff fbef bl 8003c60 8004482: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 8004484: e01f b.n 80044c6 { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8004486: f7ff fbeb bl 8003c60 800448a: 4602 mov r2, r0 800448c: 68fb ldr r3, [r7, #12] 800448e: 1ad3 subs r3, r2, r3 8004490: 2b02 cmp r3, #2 8004492: d918 bls.n 80044c6 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) 8004494: 687b ldr r3, [r7, #4] 8004496: 681b ldr r3, [r3, #0] 8004498: 689b ldr r3, [r3, #8] 800449a: f003 0301 and.w r3, r3, #1 800449e: 2b01 cmp r3, #1 80044a0: d011 beq.n 80044c6 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80044a2: 687b ldr r3, [r7, #4] 80044a4: 6a9b ldr r3, [r3, #40] ; 0x28 80044a6: f043 0210 orr.w r2, r3, #16 80044aa: 687b ldr r3, [r7, #4] 80044ac: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80044ae: 687b ldr r3, [r7, #4] 80044b0: 6adb ldr r3, [r3, #44] ; 0x2c 80044b2: f043 0201 orr.w r2, r3, #1 80044b6: 687b ldr r3, [r7, #4] 80044b8: 62da str r2, [r3, #44] ; 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 80044ba: 687b ldr r3, [r7, #4] 80044bc: 2200 movs r2, #0 80044be: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 80044c2: 2301 movs r3, #1 80044c4: e007 b.n 80044d6 while(ADC_IS_ENABLE(hadc) == RESET) 80044c6: 687b ldr r3, [r7, #4] 80044c8: 681b ldr r3, [r3, #0] 80044ca: 689b ldr r3, [r3, #8] 80044cc: f003 0301 and.w r3, r3, #1 80044d0: 2b01 cmp r3, #1 80044d2: d1d8 bne.n 8004486 } } } /* Return HAL status */ return HAL_OK; 80044d4: 2300 movs r3, #0 } 80044d6: 4618 mov r0, r3 80044d8: 3710 adds r7, #16 80044da: 46bd mov sp, r7 80044dc: bd80 pop {r7, pc} 80044de: bf00 nop 80044e0: 20000000 .word 0x20000000 80044e4: 431bde83 .word 0x431bde83 080044e8 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 80044e8: b580 push {r7, lr} 80044ea: b084 sub sp, #16 80044ec: af00 add r7, sp, #0 80044ee: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80044f0: 2300 movs r3, #0 80044f2: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 80044f4: 687b ldr r3, [r7, #4] 80044f6: 681b ldr r3, [r3, #0] 80044f8: 689b ldr r3, [r3, #8] 80044fa: f003 0301 and.w r3, r3, #1 80044fe: 2b01 cmp r3, #1 8004500: d12e bne.n 8004560 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 8004502: 687b ldr r3, [r7, #4] 8004504: 681b ldr r3, [r3, #0] 8004506: 689a ldr r2, [r3, #8] 8004508: 687b ldr r3, [r7, #4] 800450a: 681b ldr r3, [r3, #0] 800450c: f022 0201 bic.w r2, r2, #1 8004510: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 8004512: f7ff fba5 bl 8003c60 8004516: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 8004518: e01b b.n 8004552 { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800451a: f7ff fba1 bl 8003c60 800451e: 4602 mov r2, r0 8004520: 68fb ldr r3, [r7, #12] 8004522: 1ad3 subs r3, r2, r3 8004524: 2b02 cmp r3, #2 8004526: d914 bls.n 8004552 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 8004528: 687b ldr r3, [r7, #4] 800452a: 681b ldr r3, [r3, #0] 800452c: 689b ldr r3, [r3, #8] 800452e: f003 0301 and.w r3, r3, #1 8004532: 2b01 cmp r3, #1 8004534: d10d bne.n 8004552 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8004536: 687b ldr r3, [r7, #4] 8004538: 6a9b ldr r3, [r3, #40] ; 0x28 800453a: f043 0210 orr.w r2, r3, #16 800453e: 687b ldr r3, [r7, #4] 8004540: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8004542: 687b ldr r3, [r7, #4] 8004544: 6adb ldr r3, [r3, #44] ; 0x2c 8004546: f043 0201 orr.w r2, r3, #1 800454a: 687b ldr r3, [r7, #4] 800454c: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 800454e: 2301 movs r3, #1 8004550: e007 b.n 8004562 while(ADC_IS_ENABLE(hadc) != RESET) 8004552: 687b ldr r3, [r7, #4] 8004554: 681b ldr r3, [r3, #0] 8004556: 689b ldr r3, [r3, #8] 8004558: f003 0301 and.w r3, r3, #1 800455c: 2b01 cmp r3, #1 800455e: d0dc beq.n 800451a } } } /* Return HAL status */ return HAL_OK; 8004560: 2300 movs r3, #0 } 8004562: 4618 mov r0, r3 8004564: 3710 adds r7, #16 8004566: 46bd mov sp, r7 8004568: bd80 pop {r7, pc} ... 0800456c : * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { 800456c: b590 push {r4, r7, lr} 800456e: b087 sub sp, #28 8004570: af00 add r7, sp, #0 8004572: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8004574: 2300 movs r3, #0 8004576: 75fb strb r3, [r7, #23] uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; 8004578: 2300 movs r3, #0 800457a: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 800457c: 687b ldr r3, [r7, #4] 800457e: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8004582: 2b01 cmp r3, #1 8004584: d101 bne.n 800458a 8004586: 2302 movs r3, #2 8004588: e095 b.n 80046b6 800458a: 687b ldr r3, [r7, #4] 800458c: 2201 movs r2, #1 800458e: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* 1. Calibration prerequisite: */ /* - ADC must be disabled for at least two ADC clock cycles in disable */ /* mode before ADC enable */ /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 8004592: 6878 ldr r0, [r7, #4] 8004594: f7ff ffa8 bl 80044e8 8004598: 4603 mov r3, r0 800459a: 75fb strb r3, [r7, #23] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 800459c: 7dfb ldrb r3, [r7, #23] 800459e: 2b00 cmp r3, #0 80045a0: f040 8084 bne.w 80046ac { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80045a4: 687b ldr r3, [r7, #4] 80045a6: 6a9b ldr r3, [r3, #40] ; 0x28 80045a8: f423 5388 bic.w r3, r3, #4352 ; 0x1100 80045ac: f023 0302 bic.w r3, r3, #2 80045b0: f043 0202 orr.w r2, r3, #2 80045b4: 687b ldr r3, [r7, #4] 80045b6: 629a str r2, [r3, #40] ; 0x28 /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 80045b8: 4b41 ldr r3, [pc, #260] ; (80046c0 ) 80045ba: 681c ldr r4, [r3, #0] 80045bc: 2002 movs r0, #2 80045be: f002 f991 bl 80068e4 80045c2: 4603 mov r3, r0 80045c4: fbb4 f3f3 udiv r3, r4, r3 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); 80045c8: 005b lsls r3, r3, #1 wait_loop_index = ((SystemCoreClock 80045ca: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 80045cc: e002 b.n 80045d4 { wait_loop_index--; 80045ce: 68fb ldr r3, [r7, #12] 80045d0: 3b01 subs r3, #1 80045d2: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 80045d4: 68fb ldr r3, [r7, #12] 80045d6: 2b00 cmp r3, #0 80045d8: d1f9 bne.n 80045ce } /* 2. Enable the ADC peripheral */ ADC_Enable(hadc); 80045da: 6878 ldr r0, [r7, #4] 80045dc: f7ff ff2a bl 8004434 /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); 80045e0: 687b ldr r3, [r7, #4] 80045e2: 681b ldr r3, [r3, #0] 80045e4: 689a ldr r2, [r3, #8] 80045e6: 687b ldr r3, [r7, #4] 80045e8: 681b ldr r3, [r3, #0] 80045ea: f042 0208 orr.w r2, r2, #8 80045ee: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 80045f0: f7ff fb36 bl 8003c60 80045f4: 6138 str r0, [r7, #16] /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 80045f6: e01b b.n 8004630 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 80045f8: f7ff fb32 bl 8003c60 80045fc: 4602 mov r2, r0 80045fe: 693b ldr r3, [r7, #16] 8004600: 1ad3 subs r3, r2, r3 8004602: 2b0a cmp r3, #10 8004604: d914 bls.n 8004630 { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 8004606: 687b ldr r3, [r7, #4] 8004608: 681b ldr r3, [r3, #0] 800460a: 689b ldr r3, [r3, #8] 800460c: f003 0308 and.w r3, r3, #8 8004610: 2b00 cmp r3, #0 8004612: d00d beq.n 8004630 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8004614: 687b ldr r3, [r7, #4] 8004616: 6a9b ldr r3, [r3, #40] ; 0x28 8004618: f023 0312 bic.w r3, r3, #18 800461c: f043 0210 orr.w r2, r3, #16 8004620: 687b ldr r3, [r7, #4] 8004622: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 8004624: 687b ldr r3, [r7, #4] 8004626: 2200 movs r2, #0 8004628: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 800462c: 2301 movs r3, #1 800462e: e042 b.n 80046b6 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 8004630: 687b ldr r3, [r7, #4] 8004632: 681b ldr r3, [r3, #0] 8004634: 689b ldr r3, [r3, #8] 8004636: f003 0308 and.w r3, r3, #8 800463a: 2b00 cmp r3, #0 800463c: d1dc bne.n 80045f8 } } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); 800463e: 687b ldr r3, [r7, #4] 8004640: 681b ldr r3, [r3, #0] 8004642: 689a ldr r2, [r3, #8] 8004644: 687b ldr r3, [r7, #4] 8004646: 681b ldr r3, [r3, #0] 8004648: f042 0204 orr.w r2, r2, #4 800464c: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800464e: f7ff fb07 bl 8003c60 8004652: 6138 str r0, [r7, #16] /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 8004654: e01b b.n 800468e { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 8004656: f7ff fb03 bl 8003c60 800465a: 4602 mov r2, r0 800465c: 693b ldr r3, [r7, #16] 800465e: 1ad3 subs r3, r2, r3 8004660: 2b0a cmp r3, #10 8004662: d914 bls.n 800468e { /* New check to avoid false timeout detection in case of preemption */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 8004664: 687b ldr r3, [r7, #4] 8004666: 681b ldr r3, [r3, #0] 8004668: 689b ldr r3, [r3, #8] 800466a: f003 0304 and.w r3, r3, #4 800466e: 2b00 cmp r3, #0 8004670: d00d beq.n 800468e { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8004672: 687b ldr r3, [r7, #4] 8004674: 6a9b ldr r3, [r3, #40] ; 0x28 8004676: f023 0312 bic.w r3, r3, #18 800467a: f043 0210 orr.w r2, r3, #16 800467e: 687b ldr r3, [r7, #4] 8004680: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 8004682: 687b ldr r3, [r7, #4] 8004684: 2200 movs r2, #0 8004686: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 800468a: 2301 movs r3, #1 800468c: e013 b.n 80046b6 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800468e: 687b ldr r3, [r7, #4] 8004690: 681b ldr r3, [r3, #0] 8004692: 689b ldr r3, [r3, #8] 8004694: f003 0304 and.w r3, r3, #4 8004698: 2b00 cmp r3, #0 800469a: d1dc bne.n 8004656 } } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800469c: 687b ldr r3, [r7, #4] 800469e: 6a9b ldr r3, [r3, #40] ; 0x28 80046a0: f023 0303 bic.w r3, r3, #3 80046a4: f043 0201 orr.w r2, r3, #1 80046a8: 687b ldr r3, [r7, #4] 80046aa: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 80046ac: 687b ldr r3, [r7, #4] 80046ae: 2200 movs r2, #0 80046b0: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 80046b4: 7dfb ldrb r3, [r7, #23] } 80046b6: 4618 mov r0, r3 80046b8: 371c adds r7, #28 80046ba: 46bd mov sp, r7 80046bc: bd90 pop {r4, r7, pc} 80046be: bf00 nop 80046c0: 20000000 .word 0x20000000 080046c4 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { 80046c4: b580 push {r7, lr} 80046c6: b084 sub sp, #16 80046c8: af00 add r7, sp, #0 80046ca: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) 80046cc: 687b ldr r3, [r7, #4] 80046ce: 2b00 cmp r3, #0 80046d0: d101 bne.n 80046d6 { return HAL_ERROR; 80046d2: 2301 movs r3, #1 80046d4: e0ed b.n 80048b2 /* Init the low level hardware: CLOCK, NVIC */ hcan->MspInitCallback(hcan); } #else if (hcan->State == HAL_CAN_STATE_RESET) 80046d6: 687b ldr r3, [r7, #4] 80046d8: f893 3020 ldrb.w r3, [r3, #32] 80046dc: b2db uxtb r3, r3 80046de: 2b00 cmp r3, #0 80046e0: d102 bne.n 80046e8 { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); 80046e2: 6878 ldr r0, [r7, #4] 80046e4: f7fc fd88 bl 80011f8 } #endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 80046e8: 687b ldr r3, [r7, #4] 80046ea: 681b ldr r3, [r3, #0] 80046ec: 681a ldr r2, [r3, #0] 80046ee: 687b ldr r3, [r7, #4] 80046f0: 681b ldr r3, [r3, #0] 80046f2: f042 0201 orr.w r2, r2, #1 80046f6: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 80046f8: f7ff fab2 bl 8003c60 80046fc: 60f8 str r0, [r7, #12] /* Wait initialisation acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 80046fe: e012 b.n 8004726 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 8004700: f7ff faae bl 8003c60 8004704: 4602 mov r2, r0 8004706: 68fb ldr r3, [r7, #12] 8004708: 1ad3 subs r3, r2, r3 800470a: 2b0a cmp r3, #10 800470c: d90b bls.n 8004726 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800470e: 687b ldr r3, [r7, #4] 8004710: 6a5b ldr r3, [r3, #36] ; 0x24 8004712: f443 3200 orr.w r2, r3, #131072 ; 0x20000 8004716: 687b ldr r3, [r7, #4] 8004718: 625a str r2, [r3, #36] ; 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 800471a: 687b ldr r3, [r7, #4] 800471c: 2205 movs r2, #5 800471e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8004722: 2301 movs r3, #1 8004724: e0c5 b.n 80048b2 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 8004726: 687b ldr r3, [r7, #4] 8004728: 681b ldr r3, [r3, #0] 800472a: 685b ldr r3, [r3, #4] 800472c: f003 0301 and.w r3, r3, #1 8004730: 2b00 cmp r3, #0 8004732: d0e5 beq.n 8004700 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 8004734: 687b ldr r3, [r7, #4] 8004736: 681b ldr r3, [r3, #0] 8004738: 681a ldr r2, [r3, #0] 800473a: 687b ldr r3, [r7, #4] 800473c: 681b ldr r3, [r3, #0] 800473e: f022 0202 bic.w r2, r2, #2 8004742: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004744: f7ff fa8c bl 8003c60 8004748: 60f8 str r0, [r7, #12] /* Check Sleep mode leave acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 800474a: e012 b.n 8004772 { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 800474c: f7ff fa88 bl 8003c60 8004750: 4602 mov r2, r0 8004752: 68fb ldr r3, [r7, #12] 8004754: 1ad3 subs r3, r2, r3 8004756: 2b0a cmp r3, #10 8004758: d90b bls.n 8004772 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 800475a: 687b ldr r3, [r7, #4] 800475c: 6a5b ldr r3, [r3, #36] ; 0x24 800475e: f443 3200 orr.w r2, r3, #131072 ; 0x20000 8004762: 687b ldr r3, [r7, #4] 8004764: 625a str r2, [r3, #36] ; 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 8004766: 687b ldr r3, [r7, #4] 8004768: 2205 movs r2, #5 800476a: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800476e: 2301 movs r3, #1 8004770: e09f b.n 80048b2 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) 8004772: 687b ldr r3, [r7, #4] 8004774: 681b ldr r3, [r3, #0] 8004776: 685b ldr r3, [r3, #4] 8004778: f003 0302 and.w r3, r3, #2 800477c: 2b00 cmp r3, #0 800477e: d1e5 bne.n 800474c } } /* Set the time triggered communication mode */ if (hcan->Init.TimeTriggeredMode == ENABLE) 8004780: 687b ldr r3, [r7, #4] 8004782: 7e1b ldrb r3, [r3, #24] 8004784: 2b01 cmp r3, #1 8004786: d108 bne.n 800479a { SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 8004788: 687b ldr r3, [r7, #4] 800478a: 681b ldr r3, [r3, #0] 800478c: 681a ldr r2, [r3, #0] 800478e: 687b ldr r3, [r7, #4] 8004790: 681b ldr r3, [r3, #0] 8004792: f042 0280 orr.w r2, r2, #128 ; 0x80 8004796: 601a str r2, [r3, #0] 8004798: e007 b.n 80047aa } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); 800479a: 687b ldr r3, [r7, #4] 800479c: 681b ldr r3, [r3, #0] 800479e: 681a ldr r2, [r3, #0] 80047a0: 687b ldr r3, [r7, #4] 80047a2: 681b ldr r3, [r3, #0] 80047a4: f022 0280 bic.w r2, r2, #128 ; 0x80 80047a8: 601a str r2, [r3, #0] } /* Set the automatic bus-off management */ if (hcan->Init.AutoBusOff == ENABLE) 80047aa: 687b ldr r3, [r7, #4] 80047ac: 7e5b ldrb r3, [r3, #25] 80047ae: 2b01 cmp r3, #1 80047b0: d108 bne.n 80047c4 { SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 80047b2: 687b ldr r3, [r7, #4] 80047b4: 681b ldr r3, [r3, #0] 80047b6: 681a ldr r2, [r3, #0] 80047b8: 687b ldr r3, [r7, #4] 80047ba: 681b ldr r3, [r3, #0] 80047bc: f042 0240 orr.w r2, r2, #64 ; 0x40 80047c0: 601a str r2, [r3, #0] 80047c2: e007 b.n 80047d4 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); 80047c4: 687b ldr r3, [r7, #4] 80047c6: 681b ldr r3, [r3, #0] 80047c8: 681a ldr r2, [r3, #0] 80047ca: 687b ldr r3, [r7, #4] 80047cc: 681b ldr r3, [r3, #0] 80047ce: f022 0240 bic.w r2, r2, #64 ; 0x40 80047d2: 601a str r2, [r3, #0] } /* Set the automatic wake-up mode */ if (hcan->Init.AutoWakeUp == ENABLE) 80047d4: 687b ldr r3, [r7, #4] 80047d6: 7e9b ldrb r3, [r3, #26] 80047d8: 2b01 cmp r3, #1 80047da: d108 bne.n 80047ee { SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 80047dc: 687b ldr r3, [r7, #4] 80047de: 681b ldr r3, [r3, #0] 80047e0: 681a ldr r2, [r3, #0] 80047e2: 687b ldr r3, [r7, #4] 80047e4: 681b ldr r3, [r3, #0] 80047e6: f042 0220 orr.w r2, r2, #32 80047ea: 601a str r2, [r3, #0] 80047ec: e007 b.n 80047fe } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); 80047ee: 687b ldr r3, [r7, #4] 80047f0: 681b ldr r3, [r3, #0] 80047f2: 681a ldr r2, [r3, #0] 80047f4: 687b ldr r3, [r7, #4] 80047f6: 681b ldr r3, [r3, #0] 80047f8: f022 0220 bic.w r2, r2, #32 80047fc: 601a str r2, [r3, #0] } /* Set the automatic retransmission */ if (hcan->Init.AutoRetransmission == ENABLE) 80047fe: 687b ldr r3, [r7, #4] 8004800: 7edb ldrb r3, [r3, #27] 8004802: 2b01 cmp r3, #1 8004804: d108 bne.n 8004818 { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); 8004806: 687b ldr r3, [r7, #4] 8004808: 681b ldr r3, [r3, #0] 800480a: 681a ldr r2, [r3, #0] 800480c: 687b ldr r3, [r7, #4] 800480e: 681b ldr r3, [r3, #0] 8004810: f022 0210 bic.w r2, r2, #16 8004814: 601a str r2, [r3, #0] 8004816: e007 b.n 8004828 } else { SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); 8004818: 687b ldr r3, [r7, #4] 800481a: 681b ldr r3, [r3, #0] 800481c: 681a ldr r2, [r3, #0] 800481e: 687b ldr r3, [r7, #4] 8004820: 681b ldr r3, [r3, #0] 8004822: f042 0210 orr.w r2, r2, #16 8004826: 601a str r2, [r3, #0] } /* Set the receive FIFO locked mode */ if (hcan->Init.ReceiveFifoLocked == ENABLE) 8004828: 687b ldr r3, [r7, #4] 800482a: 7f1b ldrb r3, [r3, #28] 800482c: 2b01 cmp r3, #1 800482e: d108 bne.n 8004842 { SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 8004830: 687b ldr r3, [r7, #4] 8004832: 681b ldr r3, [r3, #0] 8004834: 681a ldr r2, [r3, #0] 8004836: 687b ldr r3, [r7, #4] 8004838: 681b ldr r3, [r3, #0] 800483a: f042 0208 orr.w r2, r2, #8 800483e: 601a str r2, [r3, #0] 8004840: e007 b.n 8004852 } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); 8004842: 687b ldr r3, [r7, #4] 8004844: 681b ldr r3, [r3, #0] 8004846: 681a ldr r2, [r3, #0] 8004848: 687b ldr r3, [r7, #4] 800484a: 681b ldr r3, [r3, #0] 800484c: f022 0208 bic.w r2, r2, #8 8004850: 601a str r2, [r3, #0] } /* Set the transmit FIFO priority */ if (hcan->Init.TransmitFifoPriority == ENABLE) 8004852: 687b ldr r3, [r7, #4] 8004854: 7f5b ldrb r3, [r3, #29] 8004856: 2b01 cmp r3, #1 8004858: d108 bne.n 800486c { SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800485a: 687b ldr r3, [r7, #4] 800485c: 681b ldr r3, [r3, #0] 800485e: 681a ldr r2, [r3, #0] 8004860: 687b ldr r3, [r7, #4] 8004862: 681b ldr r3, [r3, #0] 8004864: f042 0204 orr.w r2, r2, #4 8004868: 601a str r2, [r3, #0] 800486a: e007 b.n 800487c } else { CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); 800486c: 687b ldr r3, [r7, #4] 800486e: 681b ldr r3, [r3, #0] 8004870: 681a ldr r2, [r3, #0] 8004872: 687b ldr r3, [r7, #4] 8004874: 681b ldr r3, [r3, #0] 8004876: f022 0204 bic.w r2, r2, #4 800487a: 601a str r2, [r3, #0] } /* Set the bit timing register */ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | 800487c: 687b ldr r3, [r7, #4] 800487e: 689a ldr r2, [r3, #8] 8004880: 687b ldr r3, [r7, #4] 8004882: 68db ldr r3, [r3, #12] 8004884: 431a orrs r2, r3 8004886: 687b ldr r3, [r7, #4] 8004888: 691b ldr r3, [r3, #16] 800488a: 431a orrs r2, r3 800488c: 687b ldr r3, [r7, #4] 800488e: 695b ldr r3, [r3, #20] 8004890: ea42 0103 orr.w r1, r2, r3 8004894: 687b ldr r3, [r7, #4] 8004896: 685b ldr r3, [r3, #4] 8004898: 1e5a subs r2, r3, #1 800489a: 687b ldr r3, [r7, #4] 800489c: 681b ldr r3, [r3, #0] 800489e: 430a orrs r2, r1 80048a0: 61da str r2, [r3, #28] hcan->Init.TimeSeg1 | hcan->Init.TimeSeg2 | (hcan->Init.Prescaler - 1U))); /* Initialize the error code */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 80048a2: 687b ldr r3, [r7, #4] 80048a4: 2200 movs r2, #0 80048a6: 625a str r2, [r3, #36] ; 0x24 /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; 80048a8: 687b ldr r3, [r7, #4] 80048aa: 2201 movs r2, #1 80048ac: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 80048b0: 2300 movs r3, #0 } 80048b2: 4618 mov r0, r3 80048b4: 3710 adds r7, #16 80048b6: 46bd mov sp, r7 80048b8: bd80 pop {r7, pc} ... 080048bc : * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) { 80048bc: b480 push {r7} 80048be: b087 sub sp, #28 80048c0: af00 add r7, sp, #0 80048c2: 6078 str r0, [r7, #4] 80048c4: 6039 str r1, [r7, #0] uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; 80048c6: 687b ldr r3, [r7, #4] 80048c8: 681b ldr r3, [r3, #0] 80048ca: 617b str r3, [r7, #20] HAL_CAN_StateTypeDef state = hcan->State; 80048cc: 687b ldr r3, [r7, #4] 80048ce: f893 3020 ldrb.w r3, [r3, #32] 80048d2: 74fb strb r3, [r7, #19] if ((state == HAL_CAN_STATE_READY) || 80048d4: 7cfb ldrb r3, [r7, #19] 80048d6: 2b01 cmp r3, #1 80048d8: d003 beq.n 80048e2 80048da: 7cfb ldrb r3, [r7, #19] 80048dc: 2b02 cmp r3, #2 80048de: f040 80be bne.w 8004a5e assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); #if defined(CAN2) /* CAN1 and CAN2 are dual instances with 28 common filters banks */ /* Select master instance to access the filter banks */ can_ip = CAN1; 80048e2: 4b65 ldr r3, [pc, #404] ; (8004a78 ) 80048e4: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); #endif /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); 80048e6: 697b ldr r3, [r7, #20] 80048e8: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 80048ec: f043 0201 orr.w r2, r3, #1 80048f0: 697b ldr r3, [r7, #20] 80048f2: f8c3 2200 str.w r2, [r3, #512] ; 0x200 #if defined(CAN2) /* Select the start filter number of CAN2 slave instance */ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); 80048f6: 697b ldr r3, [r7, #20] 80048f8: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 80048fc: f423 527c bic.w r2, r3, #16128 ; 0x3f00 8004900: 697b ldr r3, [r7, #20] 8004902: f8c3 2200 str.w r2, [r3, #512] ; 0x200 SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); 8004906: 697b ldr r3, [r7, #20] 8004908: f8d3 2200 ldr.w r2, [r3, #512] ; 0x200 800490c: 683b ldr r3, [r7, #0] 800490e: 6a5b ldr r3, [r3, #36] ; 0x24 8004910: 021b lsls r3, r3, #8 8004912: 431a orrs r2, r3 8004914: 697b ldr r3, [r7, #20] 8004916: f8c3 2200 str.w r2, [r3, #512] ; 0x200 #endif /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); 800491a: 683b ldr r3, [r7, #0] 800491c: 695b ldr r3, [r3, #20] 800491e: f003 031f and.w r3, r3, #31 8004922: 2201 movs r2, #1 8004924: fa02 f303 lsl.w r3, r2, r3 8004928: 60fb str r3, [r7, #12] /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); 800492a: 697b ldr r3, [r7, #20] 800492c: f8d3 221c ldr.w r2, [r3, #540] ; 0x21c 8004930: 68fb ldr r3, [r7, #12] 8004932: 43db mvns r3, r3 8004934: 401a ands r2, r3 8004936: 697b ldr r3, [r7, #20] 8004938: f8c3 221c str.w r2, [r3, #540] ; 0x21c /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) 800493c: 683b ldr r3, [r7, #0] 800493e: 69db ldr r3, [r3, #28] 8004940: 2b00 cmp r3, #0 8004942: d123 bne.n 800498c { /* 16-bit scale for the filter */ CLEAR_BIT(can_ip->FS1R, filternbrbitpos); 8004944: 697b ldr r3, [r7, #20] 8004946: f8d3 220c ldr.w r2, [r3, #524] ; 0x20c 800494a: 68fb ldr r3, [r7, #12] 800494c: 43db mvns r3, r3 800494e: 401a ands r2, r3 8004950: 697b ldr r3, [r7, #20] 8004952: f8c3 220c str.w r2, [r3, #524] ; 0x20c /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 8004956: 683b ldr r3, [r7, #0] 8004958: 68db ldr r3, [r3, #12] 800495a: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 800495c: 683b ldr r3, [r7, #0] 800495e: 685b ldr r3, [r3, #4] 8004960: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 8004962: 683a ldr r2, [r7, #0] 8004964: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | 8004966: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 8004968: 697b ldr r3, [r7, #20] 800496a: 3248 adds r2, #72 ; 0x48 800496c: f843 1032 str.w r1, [r3, r2, lsl #3] /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 8004970: 683b ldr r3, [r7, #0] 8004972: 689b ldr r3, [r3, #8] 8004974: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); 8004976: 683b ldr r3, [r7, #0] 8004978: 681b ldr r3, [r3, #0] 800497a: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 800497c: 683b ldr r3, [r7, #0] 800497e: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 8004980: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 8004982: 6979 ldr r1, [r7, #20] 8004984: 3348 adds r3, #72 ; 0x48 8004986: 00db lsls r3, r3, #3 8004988: 440b add r3, r1 800498a: 605a str r2, [r3, #4] } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) 800498c: 683b ldr r3, [r7, #0] 800498e: 69db ldr r3, [r3, #28] 8004990: 2b01 cmp r3, #1 8004992: d122 bne.n 80049da { /* 32-bit scale for the filter */ SET_BIT(can_ip->FS1R, filternbrbitpos); 8004994: 697b ldr r3, [r7, #20] 8004996: f8d3 220c ldr.w r2, [r3, #524] ; 0x20c 800499a: 68fb ldr r3, [r7, #12] 800499c: 431a orrs r2, r3 800499e: 697b ldr r3, [r7, #20] 80049a0: f8c3 220c str.w r2, [r3, #524] ; 0x20c /* 32-bit identifier or First 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 80049a4: 683b ldr r3, [r7, #0] 80049a6: 681b ldr r3, [r3, #0] 80049a8: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); 80049aa: 683b ldr r3, [r7, #0] 80049ac: 685b ldr r3, [r3, #4] 80049ae: b29b uxth r3, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 80049b0: 683a ldr r2, [r7, #0] 80049b2: 6952 ldr r2, [r2, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | 80049b4: 4319 orrs r1, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = 80049b6: 697b ldr r3, [r7, #20] 80049b8: 3248 adds r2, #72 ; 0x48 80049ba: f843 1032 str.w r1, [r3, r2, lsl #3] /* 32-bit mask or Second 32-bit identifier */ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 80049be: 683b ldr r3, [r7, #0] 80049c0: 689b ldr r3, [r3, #8] 80049c2: 0419 lsls r1, r3, #16 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); 80049c4: 683b ldr r3, [r7, #0] 80049c6: 68db ldr r3, [r3, #12] 80049c8: b29a uxth r2, r3 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 80049ca: 683b ldr r3, [r7, #0] 80049cc: 695b ldr r3, [r3, #20] ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | 80049ce: 430a orrs r2, r1 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = 80049d0: 6979 ldr r1, [r7, #20] 80049d2: 3348 adds r3, #72 ; 0x48 80049d4: 00db lsls r3, r3, #3 80049d6: 440b add r3, r1 80049d8: 605a str r2, [r3, #4] } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) 80049da: 683b ldr r3, [r7, #0] 80049dc: 699b ldr r3, [r3, #24] 80049de: 2b00 cmp r3, #0 80049e0: d109 bne.n 80049f6 { /* Id/Mask mode for the filter*/ CLEAR_BIT(can_ip->FM1R, filternbrbitpos); 80049e2: 697b ldr r3, [r7, #20] 80049e4: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 80049e8: 68fb ldr r3, [r7, #12] 80049ea: 43db mvns r3, r3 80049ec: 401a ands r2, r3 80049ee: 697b ldr r3, [r7, #20] 80049f0: f8c3 2204 str.w r2, [r3, #516] ; 0x204 80049f4: e007 b.n 8004a06 } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /* Identifier list mode for the filter*/ SET_BIT(can_ip->FM1R, filternbrbitpos); 80049f6: 697b ldr r3, [r7, #20] 80049f8: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 80049fc: 68fb ldr r3, [r7, #12] 80049fe: 431a orrs r2, r3 8004a00: 697b ldr r3, [r7, #20] 8004a02: f8c3 2204 str.w r2, [r3, #516] ; 0x204 } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) 8004a06: 683b ldr r3, [r7, #0] 8004a08: 691b ldr r3, [r3, #16] 8004a0a: 2b00 cmp r3, #0 8004a0c: d109 bne.n 8004a22 { /* FIFO 0 assignation for the filter */ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); 8004a0e: 697b ldr r3, [r7, #20] 8004a10: f8d3 2214 ldr.w r2, [r3, #532] ; 0x214 8004a14: 68fb ldr r3, [r7, #12] 8004a16: 43db mvns r3, r3 8004a18: 401a ands r2, r3 8004a1a: 697b ldr r3, [r7, #20] 8004a1c: f8c3 2214 str.w r2, [r3, #532] ; 0x214 8004a20: e007 b.n 8004a32 } else { /* FIFO 1 assignation for the filter */ SET_BIT(can_ip->FFA1R, filternbrbitpos); 8004a22: 697b ldr r3, [r7, #20] 8004a24: f8d3 2214 ldr.w r2, [r3, #532] ; 0x214 8004a28: 68fb ldr r3, [r7, #12] 8004a2a: 431a orrs r2, r3 8004a2c: 697b ldr r3, [r7, #20] 8004a2e: f8c3 2214 str.w r2, [r3, #532] ; 0x214 } /* Filter activation */ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) 8004a32: 683b ldr r3, [r7, #0] 8004a34: 6a1b ldr r3, [r3, #32] 8004a36: 2b01 cmp r3, #1 8004a38: d107 bne.n 8004a4a { SET_BIT(can_ip->FA1R, filternbrbitpos); 8004a3a: 697b ldr r3, [r7, #20] 8004a3c: f8d3 221c ldr.w r2, [r3, #540] ; 0x21c 8004a40: 68fb ldr r3, [r7, #12] 8004a42: 431a orrs r2, r3 8004a44: 697b ldr r3, [r7, #20] 8004a46: f8c3 221c str.w r2, [r3, #540] ; 0x21c } /* Leave the initialisation mode for the filter */ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); 8004a4a: 697b ldr r3, [r7, #20] 8004a4c: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 8004a50: f023 0201 bic.w r2, r3, #1 8004a54: 697b ldr r3, [r7, #20] 8004a56: f8c3 2200 str.w r2, [r3, #512] ; 0x200 /* Return function status */ return HAL_OK; 8004a5a: 2300 movs r3, #0 8004a5c: e006 b.n 8004a6c } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8004a5e: 687b ldr r3, [r7, #4] 8004a60: 6a5b ldr r3, [r3, #36] ; 0x24 8004a62: f443 2280 orr.w r2, r3, #262144 ; 0x40000 8004a66: 687b ldr r3, [r7, #4] 8004a68: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8004a6a: 2301 movs r3, #1 } } 8004a6c: 4618 mov r0, r3 8004a6e: 371c adds r7, #28 8004a70: 46bd mov sp, r7 8004a72: bc80 pop {r7} 8004a74: 4770 bx lr 8004a76: bf00 nop 8004a78: 40006400 .word 0x40006400 08004a7c : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { 8004a7c: b580 push {r7, lr} 8004a7e: b084 sub sp, #16 8004a80: af00 add r7, sp, #0 8004a82: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) 8004a84: 687b ldr r3, [r7, #4] 8004a86: f893 3020 ldrb.w r3, [r3, #32] 8004a8a: b2db uxtb r3, r3 8004a8c: 2b01 cmp r3, #1 8004a8e: d12e bne.n 8004aee { /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_LISTENING; 8004a90: 687b ldr r3, [r7, #4] 8004a92: 2202 movs r2, #2 8004a94: f883 2020 strb.w r2, [r3, #32] /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 8004a98: 687b ldr r3, [r7, #4] 8004a9a: 681b ldr r3, [r3, #0] 8004a9c: 681a ldr r2, [r3, #0] 8004a9e: 687b ldr r3, [r7, #4] 8004aa0: 681b ldr r3, [r3, #0] 8004aa2: f022 0201 bic.w r2, r2, #1 8004aa6: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004aa8: f7ff f8da bl 8003c60 8004aac: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 8004aae: e012 b.n 8004ad6 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 8004ab0: f7ff f8d6 bl 8003c60 8004ab4: 4602 mov r2, r0 8004ab6: 68fb ldr r3, [r7, #12] 8004ab8: 1ad3 subs r3, r2, r3 8004aba: 2b0a cmp r3, #10 8004abc: d90b bls.n 8004ad6 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 8004abe: 687b ldr r3, [r7, #4] 8004ac0: 6a5b ldr r3, [r3, #36] ; 0x24 8004ac2: f443 3200 orr.w r2, r3, #131072 ; 0x20000 8004ac6: 687b ldr r3, [r7, #4] 8004ac8: 625a str r2, [r3, #36] ; 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 8004aca: 687b ldr r3, [r7, #4] 8004acc: 2205 movs r2, #5 8004ace: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8004ad2: 2301 movs r3, #1 8004ad4: e012 b.n 8004afc while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) 8004ad6: 687b ldr r3, [r7, #4] 8004ad8: 681b ldr r3, [r3, #0] 8004ada: 685b ldr r3, [r3, #4] 8004adc: f003 0301 and.w r3, r3, #1 8004ae0: 2b00 cmp r3, #0 8004ae2: d1e5 bne.n 8004ab0 } } /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; 8004ae4: 687b ldr r3, [r7, #4] 8004ae6: 2200 movs r2, #0 8004ae8: 625a str r2, [r3, #36] ; 0x24 /* Return function status */ return HAL_OK; 8004aea: 2300 movs r3, #0 8004aec: e006 b.n 8004afc } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; 8004aee: 687b ldr r3, [r7, #4] 8004af0: 6a5b ldr r3, [r3, #36] ; 0x24 8004af2: f443 2200 orr.w r2, r3, #524288 ; 0x80000 8004af6: 687b ldr r3, [r7, #4] 8004af8: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8004afa: 2301 movs r3, #1 } } 8004afc: 4618 mov r0, r3 8004afe: 3710 adds r7, #16 8004b00: 46bd mov sp, r7 8004b02: bd80 pop {r7, pc} 08004b04 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { 8004b04: b580 push {r7, lr} 8004b06: b084 sub sp, #16 8004b08: af00 add r7, sp, #0 8004b0a: 6078 str r0, [r7, #4] uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_LISTENING) 8004b0c: 687b ldr r3, [r7, #4] 8004b0e: f893 3020 ldrb.w r3, [r3, #32] 8004b12: b2db uxtb r3, r3 8004b14: 2b02 cmp r3, #2 8004b16: d133 bne.n 8004b80 { /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); 8004b18: 687b ldr r3, [r7, #4] 8004b1a: 681b ldr r3, [r3, #0] 8004b1c: 681a ldr r2, [r3, #0] 8004b1e: 687b ldr r3, [r7, #4] 8004b20: 681b ldr r3, [r3, #0] 8004b22: f042 0201 orr.w r2, r2, #1 8004b26: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004b28: f7ff f89a bl 8003c60 8004b2c: 60f8 str r0, [r7, #12] /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 8004b2e: e012 b.n 8004b56 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) 8004b30: f7ff f896 bl 8003c60 8004b34: 4602 mov r2, r0 8004b36: 68fb ldr r3, [r7, #12] 8004b38: 1ad3 subs r3, r2, r3 8004b3a: 2b0a cmp r3, #10 8004b3c: d90b bls.n 8004b56 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; 8004b3e: 687b ldr r3, [r7, #4] 8004b40: 6a5b ldr r3, [r3, #36] ; 0x24 8004b42: f443 3200 orr.w r2, r3, #131072 ; 0x20000 8004b46: 687b ldr r3, [r7, #4] 8004b48: 625a str r2, [r3, #36] ; 0x24 /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; 8004b4a: 687b ldr r3, [r7, #4] 8004b4c: 2205 movs r2, #5 8004b4e: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 8004b52: 2301 movs r3, #1 8004b54: e01b b.n 8004b8e while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) 8004b56: 687b ldr r3, [r7, #4] 8004b58: 681b ldr r3, [r3, #0] 8004b5a: 685b ldr r3, [r3, #4] 8004b5c: f003 0301 and.w r3, r3, #1 8004b60: 2b00 cmp r3, #0 8004b62: d0e5 beq.n 8004b30 } } /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); 8004b64: 687b ldr r3, [r7, #4] 8004b66: 681b ldr r3, [r3, #0] 8004b68: 681a ldr r2, [r3, #0] 8004b6a: 687b ldr r3, [r7, #4] 8004b6c: 681b ldr r3, [r3, #0] 8004b6e: f022 0202 bic.w r2, r2, #2 8004b72: 601a str r2, [r3, #0] /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_READY; 8004b74: 687b ldr r3, [r7, #4] 8004b76: 2201 movs r2, #1 8004b78: f883 2020 strb.w r2, [r3, #32] /* Return function status */ return HAL_OK; 8004b7c: 2300 movs r3, #0 8004b7e: e006 b.n 8004b8e } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; 8004b80: 687b ldr r3, [r7, #4] 8004b82: 6a5b ldr r3, [r3, #36] ; 0x24 8004b84: f443 1280 orr.w r2, r3, #1048576 ; 0x100000 8004b88: 687b ldr r3, [r7, #4] 8004b8a: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8004b8c: 2301 movs r3, #1 } } 8004b8e: 4618 mov r0, r3 8004b90: 3710 adds r7, #16 8004b92: 46bd mov sp, r7 8004b94: bd80 pop {r7, pc} 08004b96 : * the TxMailbox used to store the Tx message. * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) { 8004b96: b480 push {r7} 8004b98: b089 sub sp, #36 ; 0x24 8004b9a: af00 add r7, sp, #0 8004b9c: 60f8 str r0, [r7, #12] 8004b9e: 60b9 str r1, [r7, #8] 8004ba0: 607a str r2, [r7, #4] 8004ba2: 603b str r3, [r7, #0] uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; 8004ba4: 68fb ldr r3, [r7, #12] 8004ba6: f893 3020 ldrb.w r3, [r3, #32] 8004baa: 77fb strb r3, [r7, #31] uint32_t tsr = READ_REG(hcan->Instance->TSR); 8004bac: 68fb ldr r3, [r7, #12] 8004bae: 681b ldr r3, [r3, #0] 8004bb0: 689b ldr r3, [r3, #8] 8004bb2: 61bb str r3, [r7, #24] { assert_param(IS_CAN_EXTID(pHeader->ExtId)); } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); if ((state == HAL_CAN_STATE_READY) || 8004bb4: 7ffb ldrb r3, [r7, #31] 8004bb6: 2b01 cmp r3, #1 8004bb8: d003 beq.n 8004bc2 8004bba: 7ffb ldrb r3, [r7, #31] 8004bbc: 2b02 cmp r3, #2 8004bbe: f040 80b8 bne.w 8004d32 (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ if (((tsr & CAN_TSR_TME0) != 0U) || 8004bc2: 69bb ldr r3, [r7, #24] 8004bc4: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 8004bc8: 2b00 cmp r3, #0 8004bca: d10a bne.n 8004be2 ((tsr & CAN_TSR_TME1) != 0U) || 8004bcc: 69bb ldr r3, [r7, #24] 8004bce: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 if (((tsr & CAN_TSR_TME0) != 0U) || 8004bd2: 2b00 cmp r3, #0 8004bd4: d105 bne.n 8004be2 ((tsr & CAN_TSR_TME2) != 0U)) 8004bd6: 69bb ldr r3, [r7, #24] 8004bd8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 ((tsr & CAN_TSR_TME1) != 0U) || 8004bdc: 2b00 cmp r3, #0 8004bde: f000 80a0 beq.w 8004d22 { /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; 8004be2: 69bb ldr r3, [r7, #24] 8004be4: 0e1b lsrs r3, r3, #24 8004be6: f003 0303 and.w r3, r3, #3 8004bea: 617b str r3, [r7, #20] /* Check transmit mailbox value */ if (transmitmailbox > 2U) 8004bec: 697b ldr r3, [r7, #20] 8004bee: 2b02 cmp r3, #2 8004bf0: d907 bls.n 8004c02 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL; 8004bf2: 68fb ldr r3, [r7, #12] 8004bf4: 6a5b ldr r3, [r3, #36] ; 0x24 8004bf6: f443 0200 orr.w r2, r3, #8388608 ; 0x800000 8004bfa: 68fb ldr r3, [r7, #12] 8004bfc: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8004bfe: 2301 movs r3, #1 8004c00: e09e b.n 8004d40 } /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; 8004c02: 2201 movs r2, #1 8004c04: 697b ldr r3, [r7, #20] 8004c06: 409a lsls r2, r3 8004c08: 683b ldr r3, [r7, #0] 8004c0a: 601a str r2, [r3, #0] /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) 8004c0c: 68bb ldr r3, [r7, #8] 8004c0e: 689b ldr r3, [r3, #8] 8004c10: 2b00 cmp r3, #0 8004c12: d10d bne.n 8004c30 { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 8004c14: 68bb ldr r3, [r7, #8] 8004c16: 681b ldr r3, [r3, #0] 8004c18: 055a lsls r2, r3, #21 pHeader->RTR); 8004c1a: 68bb ldr r3, [r7, #8] 8004c1c: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | 8004c1e: 68f9 ldr r1, [r7, #12] 8004c20: 6809 ldr r1, [r1, #0] 8004c22: 431a orrs r2, r3 8004c24: 697b ldr r3, [r7, #20] 8004c26: 3318 adds r3, #24 8004c28: 011b lsls r3, r3, #4 8004c2a: 440b add r3, r1 8004c2c: 601a str r2, [r3, #0] 8004c2e: e00f b.n 8004c50 } else { hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8004c30: 68bb ldr r3, [r7, #8] 8004c32: 685b ldr r3, [r3, #4] 8004c34: 00da lsls r2, r3, #3 pHeader->IDE | 8004c36: 68bb ldr r3, [r7, #8] 8004c38: 689b ldr r3, [r3, #8] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8004c3a: 431a orrs r2, r3 pHeader->RTR); 8004c3c: 68bb ldr r3, [r7, #8] 8004c3e: 68db ldr r3, [r3, #12] hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8004c40: 68f9 ldr r1, [r7, #12] 8004c42: 6809 ldr r1, [r1, #0] pHeader->IDE | 8004c44: 431a orrs r2, r3 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | 8004c46: 697b ldr r3, [r7, #20] 8004c48: 3318 adds r3, #24 8004c4a: 011b lsls r3, r3, #4 8004c4c: 440b add r3, r1 8004c4e: 601a str r2, [r3, #0] } /* Set up the DLC */ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); 8004c50: 68fb ldr r3, [r7, #12] 8004c52: 6819 ldr r1, [r3, #0] 8004c54: 68bb ldr r3, [r7, #8] 8004c56: 691a ldr r2, [r3, #16] 8004c58: 697b ldr r3, [r7, #20] 8004c5a: 3318 adds r3, #24 8004c5c: 011b lsls r3, r3, #4 8004c5e: 440b add r3, r1 8004c60: 3304 adds r3, #4 8004c62: 601a str r2, [r3, #0] /* Set up the Transmit Global Time mode */ if (pHeader->TransmitGlobalTime == ENABLE) 8004c64: 68bb ldr r3, [r7, #8] 8004c66: 7d1b ldrb r3, [r3, #20] 8004c68: 2b01 cmp r3, #1 8004c6a: d111 bne.n 8004c90 { SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); 8004c6c: 68fb ldr r3, [r7, #12] 8004c6e: 681a ldr r2, [r3, #0] 8004c70: 697b ldr r3, [r7, #20] 8004c72: 3318 adds r3, #24 8004c74: 011b lsls r3, r3, #4 8004c76: 4413 add r3, r2 8004c78: 3304 adds r3, #4 8004c7a: 681b ldr r3, [r3, #0] 8004c7c: 68fa ldr r2, [r7, #12] 8004c7e: 6811 ldr r1, [r2, #0] 8004c80: f443 7280 orr.w r2, r3, #256 ; 0x100 8004c84: 697b ldr r3, [r7, #20] 8004c86: 3318 adds r3, #24 8004c88: 011b lsls r3, r3, #4 8004c8a: 440b add r3, r1 8004c8c: 3304 adds r3, #4 8004c8e: 601a str r2, [r3, #0] } /* Set up the data field */ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, 8004c90: 687b ldr r3, [r7, #4] 8004c92: 3307 adds r3, #7 8004c94: 781b ldrb r3, [r3, #0] 8004c96: 061a lsls r2, r3, #24 8004c98: 687b ldr r3, [r7, #4] 8004c9a: 3306 adds r3, #6 8004c9c: 781b ldrb r3, [r3, #0] 8004c9e: 041b lsls r3, r3, #16 8004ca0: 431a orrs r2, r3 8004ca2: 687b ldr r3, [r7, #4] 8004ca4: 3305 adds r3, #5 8004ca6: 781b ldrb r3, [r3, #0] 8004ca8: 021b lsls r3, r3, #8 8004caa: 4313 orrs r3, r2 8004cac: 687a ldr r2, [r7, #4] 8004cae: 3204 adds r2, #4 8004cb0: 7812 ldrb r2, [r2, #0] 8004cb2: 4610 mov r0, r2 8004cb4: 68fa ldr r2, [r7, #12] 8004cb6: 6811 ldr r1, [r2, #0] 8004cb8: ea43 0200 orr.w r2, r3, r0 8004cbc: 697b ldr r3, [r7, #20] 8004cbe: 011b lsls r3, r3, #4 8004cc0: 440b add r3, r1 8004cc2: f503 73c6 add.w r3, r3, #396 ; 0x18c 8004cc6: 601a str r2, [r3, #0] ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, 8004cc8: 687b ldr r3, [r7, #4] 8004cca: 3303 adds r3, #3 8004ccc: 781b ldrb r3, [r3, #0] 8004cce: 061a lsls r2, r3, #24 8004cd0: 687b ldr r3, [r7, #4] 8004cd2: 3302 adds r3, #2 8004cd4: 781b ldrb r3, [r3, #0] 8004cd6: 041b lsls r3, r3, #16 8004cd8: 431a orrs r2, r3 8004cda: 687b ldr r3, [r7, #4] 8004cdc: 3301 adds r3, #1 8004cde: 781b ldrb r3, [r3, #0] 8004ce0: 021b lsls r3, r3, #8 8004ce2: 4313 orrs r3, r2 8004ce4: 687a ldr r2, [r7, #4] 8004ce6: 7812 ldrb r2, [r2, #0] 8004ce8: 4610 mov r0, r2 8004cea: 68fa ldr r2, [r7, #12] 8004cec: 6811 ldr r1, [r2, #0] 8004cee: ea43 0200 orr.w r2, r3, r0 8004cf2: 697b ldr r3, [r7, #20] 8004cf4: 011b lsls r3, r3, #4 8004cf6: 440b add r3, r1 8004cf8: f503 73c4 add.w r3, r3, #392 ; 0x188 8004cfc: 601a str r2, [r3, #0] ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); 8004cfe: 68fb ldr r3, [r7, #12] 8004d00: 681a ldr r2, [r3, #0] 8004d02: 697b ldr r3, [r7, #20] 8004d04: 3318 adds r3, #24 8004d06: 011b lsls r3, r3, #4 8004d08: 4413 add r3, r2 8004d0a: 681b ldr r3, [r3, #0] 8004d0c: 68fa ldr r2, [r7, #12] 8004d0e: 6811 ldr r1, [r2, #0] 8004d10: f043 0201 orr.w r2, r3, #1 8004d14: 697b ldr r3, [r7, #20] 8004d16: 3318 adds r3, #24 8004d18: 011b lsls r3, r3, #4 8004d1a: 440b add r3, r1 8004d1c: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 8004d1e: 2300 movs r3, #0 8004d20: e00e b.n 8004d40 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 8004d22: 68fb ldr r3, [r7, #12] 8004d24: 6a5b ldr r3, [r3, #36] ; 0x24 8004d26: f443 1200 orr.w r2, r3, #2097152 ; 0x200000 8004d2a: 68fb ldr r3, [r7, #12] 8004d2c: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8004d2e: 2301 movs r3, #1 8004d30: e006 b.n 8004d40 } } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8004d32: 68fb ldr r3, [r7, #12] 8004d34: 6a5b ldr r3, [r3, #36] ; 0x24 8004d36: f443 2280 orr.w r2, r3, #262144 ; 0x40000 8004d3a: 68fb ldr r3, [r7, #12] 8004d3c: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8004d3e: 2301 movs r3, #1 } } 8004d40: 4618 mov r0, r3 8004d42: 3724 adds r7, #36 ; 0x24 8004d44: 46bd mov sp, r7 8004d46: bc80 pop {r7} 8004d48: 4770 bx lr 08004d4a : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval Number of free Tx Mailboxes. */ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) { 8004d4a: b480 push {r7} 8004d4c: b085 sub sp, #20 8004d4e: af00 add r7, sp, #0 8004d50: 6078 str r0, [r7, #4] uint32_t freelevel = 0U; 8004d52: 2300 movs r3, #0 8004d54: 60fb str r3, [r7, #12] HAL_CAN_StateTypeDef state = hcan->State; 8004d56: 687b ldr r3, [r7, #4] 8004d58: f893 3020 ldrb.w r3, [r3, #32] 8004d5c: 72fb strb r3, [r7, #11] if ((state == HAL_CAN_STATE_READY) || 8004d5e: 7afb ldrb r3, [r7, #11] 8004d60: 2b01 cmp r3, #1 8004d62: d002 beq.n 8004d6a 8004d64: 7afb ldrb r3, [r7, #11] 8004d66: 2b02 cmp r3, #2 8004d68: d11d bne.n 8004da6 (state == HAL_CAN_STATE_LISTENING)) { /* Check Tx Mailbox 0 status */ if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) 8004d6a: 687b ldr r3, [r7, #4] 8004d6c: 681b ldr r3, [r3, #0] 8004d6e: 689b ldr r3, [r3, #8] 8004d70: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 8004d74: 2b00 cmp r3, #0 8004d76: d002 beq.n 8004d7e { freelevel++; 8004d78: 68fb ldr r3, [r7, #12] 8004d7a: 3301 adds r3, #1 8004d7c: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 1 status */ if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) 8004d7e: 687b ldr r3, [r7, #4] 8004d80: 681b ldr r3, [r3, #0] 8004d82: 689b ldr r3, [r3, #8] 8004d84: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8004d88: 2b00 cmp r3, #0 8004d8a: d002 beq.n 8004d92 { freelevel++; 8004d8c: 68fb ldr r3, [r7, #12] 8004d8e: 3301 adds r3, #1 8004d90: 60fb str r3, [r7, #12] } /* Check Tx Mailbox 2 status */ if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) 8004d92: 687b ldr r3, [r7, #4] 8004d94: 681b ldr r3, [r3, #0] 8004d96: 689b ldr r3, [r3, #8] 8004d98: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8004d9c: 2b00 cmp r3, #0 8004d9e: d002 beq.n 8004da6 { freelevel++; 8004da0: 68fb ldr r3, [r7, #12] 8004da2: 3301 adds r3, #1 8004da4: 60fb str r3, [r7, #12] } } /* Return Tx Mailboxes free level */ return freelevel; 8004da6: 68fb ldr r3, [r7, #12] } 8004da8: 4618 mov r0, r3 8004daa: 3714 adds r7, #20 8004dac: 46bd mov sp, r7 8004dae: bc80 pop {r7} 8004db0: 4770 bx lr 08004db2 : * of the Rx frame will be stored. * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { 8004db2: b480 push {r7} 8004db4: b087 sub sp, #28 8004db6: af00 add r7, sp, #0 8004db8: 60f8 str r0, [r7, #12] 8004dba: 60b9 str r1, [r7, #8] 8004dbc: 607a str r2, [r7, #4] 8004dbe: 603b str r3, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 8004dc0: 68fb ldr r3, [r7, #12] 8004dc2: f893 3020 ldrb.w r3, [r3, #32] 8004dc6: 75fb strb r3, [r7, #23] assert_param(IS_CAN_RX_FIFO(RxFifo)); if ((state == HAL_CAN_STATE_READY) || 8004dc8: 7dfb ldrb r3, [r7, #23] 8004dca: 2b01 cmp r3, #1 8004dcc: d003 beq.n 8004dd6 8004dce: 7dfb ldrb r3, [r7, #23] 8004dd0: 2b02 cmp r3, #2 8004dd2: f040 80f3 bne.w 8004fbc (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 8004dd6: 68bb ldr r3, [r7, #8] 8004dd8: 2b00 cmp r3, #0 8004dda: d10e bne.n 8004dfa { /* Check that the Rx FIFO 0 is not empty */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) 8004ddc: 68fb ldr r3, [r7, #12] 8004dde: 681b ldr r3, [r3, #0] 8004de0: 68db ldr r3, [r3, #12] 8004de2: f003 0303 and.w r3, r3, #3 8004de6: 2b00 cmp r3, #0 8004de8: d116 bne.n 8004e18 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 8004dea: 68fb ldr r3, [r7, #12] 8004dec: 6a5b ldr r3, [r3, #36] ; 0x24 8004dee: f443 1200 orr.w r2, r3, #2097152 ; 0x200000 8004df2: 68fb ldr r3, [r7, #12] 8004df4: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8004df6: 2301 movs r3, #1 8004df8: e0e7 b.n 8004fca } } else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) 8004dfa: 68fb ldr r3, [r7, #12] 8004dfc: 681b ldr r3, [r3, #0] 8004dfe: 691b ldr r3, [r3, #16] 8004e00: f003 0303 and.w r3, r3, #3 8004e04: 2b00 cmp r3, #0 8004e06: d107 bne.n 8004e18 { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; 8004e08: 68fb ldr r3, [r7, #12] 8004e0a: 6a5b ldr r3, [r3, #36] ; 0x24 8004e0c: f443 1200 orr.w r2, r3, #2097152 ; 0x200000 8004e10: 68fb ldr r3, [r7, #12] 8004e12: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8004e14: 2301 movs r3, #1 8004e16: e0d8 b.n 8004fca } } /* Get the header */ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; 8004e18: 68fb ldr r3, [r7, #12] 8004e1a: 681a ldr r2, [r3, #0] 8004e1c: 68bb ldr r3, [r7, #8] 8004e1e: 331b adds r3, #27 8004e20: 011b lsls r3, r3, #4 8004e22: 4413 add r3, r2 8004e24: 681b ldr r3, [r3, #0] 8004e26: f003 0204 and.w r2, r3, #4 8004e2a: 687b ldr r3, [r7, #4] 8004e2c: 609a str r2, [r3, #8] if (pHeader->IDE == CAN_ID_STD) 8004e2e: 687b ldr r3, [r7, #4] 8004e30: 689b ldr r3, [r3, #8] 8004e32: 2b00 cmp r3, #0 8004e34: d10c bne.n 8004e50 { pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; 8004e36: 68fb ldr r3, [r7, #12] 8004e38: 681a ldr r2, [r3, #0] 8004e3a: 68bb ldr r3, [r7, #8] 8004e3c: 331b adds r3, #27 8004e3e: 011b lsls r3, r3, #4 8004e40: 4413 add r3, r2 8004e42: 681b ldr r3, [r3, #0] 8004e44: 0d5b lsrs r3, r3, #21 8004e46: f3c3 020a ubfx r2, r3, #0, #11 8004e4a: 687b ldr r3, [r7, #4] 8004e4c: 601a str r2, [r3, #0] 8004e4e: e00b b.n 8004e68 } else { pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; 8004e50: 68fb ldr r3, [r7, #12] 8004e52: 681a ldr r2, [r3, #0] 8004e54: 68bb ldr r3, [r7, #8] 8004e56: 331b adds r3, #27 8004e58: 011b lsls r3, r3, #4 8004e5a: 4413 add r3, r2 8004e5c: 681b ldr r3, [r3, #0] 8004e5e: 08db lsrs r3, r3, #3 8004e60: f023 4260 bic.w r2, r3, #3758096384 ; 0xe0000000 8004e64: 687b ldr r3, [r7, #4] 8004e66: 605a str r2, [r3, #4] } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); 8004e68: 68fb ldr r3, [r7, #12] 8004e6a: 681a ldr r2, [r3, #0] 8004e6c: 68bb ldr r3, [r7, #8] 8004e6e: 331b adds r3, #27 8004e70: 011b lsls r3, r3, #4 8004e72: 4413 add r3, r2 8004e74: 681b ldr r3, [r3, #0] 8004e76: f003 0202 and.w r2, r3, #2 8004e7a: 687b ldr r3, [r7, #4] 8004e7c: 60da str r2, [r3, #12] pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; 8004e7e: 68fb ldr r3, [r7, #12] 8004e80: 681a ldr r2, [r3, #0] 8004e82: 68bb ldr r3, [r7, #8] 8004e84: 331b adds r3, #27 8004e86: 011b lsls r3, r3, #4 8004e88: 4413 add r3, r2 8004e8a: 3304 adds r3, #4 8004e8c: 681b ldr r3, [r3, #0] 8004e8e: f003 020f and.w r2, r3, #15 8004e92: 687b ldr r3, [r7, #4] 8004e94: 611a str r2, [r3, #16] pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; 8004e96: 68fb ldr r3, [r7, #12] 8004e98: 681a ldr r2, [r3, #0] 8004e9a: 68bb ldr r3, [r7, #8] 8004e9c: 331b adds r3, #27 8004e9e: 011b lsls r3, r3, #4 8004ea0: 4413 add r3, r2 8004ea2: 3304 adds r3, #4 8004ea4: 681b ldr r3, [r3, #0] 8004ea6: 0a1b lsrs r3, r3, #8 8004ea8: b2da uxtb r2, r3 8004eaa: 687b ldr r3, [r7, #4] 8004eac: 619a str r2, [r3, #24] pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; 8004eae: 68fb ldr r3, [r7, #12] 8004eb0: 681a ldr r2, [r3, #0] 8004eb2: 68bb ldr r3, [r7, #8] 8004eb4: 331b adds r3, #27 8004eb6: 011b lsls r3, r3, #4 8004eb8: 4413 add r3, r2 8004eba: 3304 adds r3, #4 8004ebc: 681b ldr r3, [r3, #0] 8004ebe: 0c1b lsrs r3, r3, #16 8004ec0: b29a uxth r2, r3 8004ec2: 687b ldr r3, [r7, #4] 8004ec4: 615a str r2, [r3, #20] /* Get the data */ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); 8004ec6: 68fb ldr r3, [r7, #12] 8004ec8: 681a ldr r2, [r3, #0] 8004eca: 68bb ldr r3, [r7, #8] 8004ecc: 011b lsls r3, r3, #4 8004ece: 4413 add r3, r2 8004ed0: f503 73dc add.w r3, r3, #440 ; 0x1b8 8004ed4: 681b ldr r3, [r3, #0] 8004ed6: b2da uxtb r2, r3 8004ed8: 683b ldr r3, [r7, #0] 8004eda: 701a strb r2, [r3, #0] aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); 8004edc: 68fb ldr r3, [r7, #12] 8004ede: 681a ldr r2, [r3, #0] 8004ee0: 68bb ldr r3, [r7, #8] 8004ee2: 011b lsls r3, r3, #4 8004ee4: 4413 add r3, r2 8004ee6: f503 73dc add.w r3, r3, #440 ; 0x1b8 8004eea: 681b ldr r3, [r3, #0] 8004eec: 0a1a lsrs r2, r3, #8 8004eee: 683b ldr r3, [r7, #0] 8004ef0: 3301 adds r3, #1 8004ef2: b2d2 uxtb r2, r2 8004ef4: 701a strb r2, [r3, #0] aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); 8004ef6: 68fb ldr r3, [r7, #12] 8004ef8: 681a ldr r2, [r3, #0] 8004efa: 68bb ldr r3, [r7, #8] 8004efc: 011b lsls r3, r3, #4 8004efe: 4413 add r3, r2 8004f00: f503 73dc add.w r3, r3, #440 ; 0x1b8 8004f04: 681b ldr r3, [r3, #0] 8004f06: 0c1a lsrs r2, r3, #16 8004f08: 683b ldr r3, [r7, #0] 8004f0a: 3302 adds r3, #2 8004f0c: b2d2 uxtb r2, r2 8004f0e: 701a strb r2, [r3, #0] aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); 8004f10: 68fb ldr r3, [r7, #12] 8004f12: 681a ldr r2, [r3, #0] 8004f14: 68bb ldr r3, [r7, #8] 8004f16: 011b lsls r3, r3, #4 8004f18: 4413 add r3, r2 8004f1a: f503 73dc add.w r3, r3, #440 ; 0x1b8 8004f1e: 681b ldr r3, [r3, #0] 8004f20: 0e1a lsrs r2, r3, #24 8004f22: 683b ldr r3, [r7, #0] 8004f24: 3303 adds r3, #3 8004f26: b2d2 uxtb r2, r2 8004f28: 701a strb r2, [r3, #0] aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); 8004f2a: 68fb ldr r3, [r7, #12] 8004f2c: 681a ldr r2, [r3, #0] 8004f2e: 68bb ldr r3, [r7, #8] 8004f30: 011b lsls r3, r3, #4 8004f32: 4413 add r3, r2 8004f34: f503 73de add.w r3, r3, #444 ; 0x1bc 8004f38: 681a ldr r2, [r3, #0] 8004f3a: 683b ldr r3, [r7, #0] 8004f3c: 3304 adds r3, #4 8004f3e: b2d2 uxtb r2, r2 8004f40: 701a strb r2, [r3, #0] aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); 8004f42: 68fb ldr r3, [r7, #12] 8004f44: 681a ldr r2, [r3, #0] 8004f46: 68bb ldr r3, [r7, #8] 8004f48: 011b lsls r3, r3, #4 8004f4a: 4413 add r3, r2 8004f4c: f503 73de add.w r3, r3, #444 ; 0x1bc 8004f50: 681b ldr r3, [r3, #0] 8004f52: 0a1a lsrs r2, r3, #8 8004f54: 683b ldr r3, [r7, #0] 8004f56: 3305 adds r3, #5 8004f58: b2d2 uxtb r2, r2 8004f5a: 701a strb r2, [r3, #0] aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); 8004f5c: 68fb ldr r3, [r7, #12] 8004f5e: 681a ldr r2, [r3, #0] 8004f60: 68bb ldr r3, [r7, #8] 8004f62: 011b lsls r3, r3, #4 8004f64: 4413 add r3, r2 8004f66: f503 73de add.w r3, r3, #444 ; 0x1bc 8004f6a: 681b ldr r3, [r3, #0] 8004f6c: 0c1a lsrs r2, r3, #16 8004f6e: 683b ldr r3, [r7, #0] 8004f70: 3306 adds r3, #6 8004f72: b2d2 uxtb r2, r2 8004f74: 701a strb r2, [r3, #0] aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); 8004f76: 68fb ldr r3, [r7, #12] 8004f78: 681a ldr r2, [r3, #0] 8004f7a: 68bb ldr r3, [r7, #8] 8004f7c: 011b lsls r3, r3, #4 8004f7e: 4413 add r3, r2 8004f80: f503 73de add.w r3, r3, #444 ; 0x1bc 8004f84: 681b ldr r3, [r3, #0] 8004f86: 0e1a lsrs r2, r3, #24 8004f88: 683b ldr r3, [r7, #0] 8004f8a: 3307 adds r3, #7 8004f8c: b2d2 uxtb r2, r2 8004f8e: 701a strb r2, [r3, #0] /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ 8004f90: 68bb ldr r3, [r7, #8] 8004f92: 2b00 cmp r3, #0 8004f94: d108 bne.n 8004fa8 { /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); 8004f96: 68fb ldr r3, [r7, #12] 8004f98: 681b ldr r3, [r3, #0] 8004f9a: 68da ldr r2, [r3, #12] 8004f9c: 68fb ldr r3, [r7, #12] 8004f9e: 681b ldr r3, [r3, #0] 8004fa0: f042 0220 orr.w r2, r2, #32 8004fa4: 60da str r2, [r3, #12] 8004fa6: e007 b.n 8004fb8 } else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); 8004fa8: 68fb ldr r3, [r7, #12] 8004faa: 681b ldr r3, [r3, #0] 8004fac: 691a ldr r2, [r3, #16] 8004fae: 68fb ldr r3, [r7, #12] 8004fb0: 681b ldr r3, [r3, #0] 8004fb2: f042 0220 orr.w r2, r2, #32 8004fb6: 611a str r2, [r3, #16] } /* Return function status */ return HAL_OK; 8004fb8: 2300 movs r3, #0 8004fba: e006 b.n 8004fca } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8004fbc: 68fb ldr r3, [r7, #12] 8004fbe: 6a5b ldr r3, [r3, #36] ; 0x24 8004fc0: f443 2280 orr.w r2, r3, #262144 ; 0x40000 8004fc4: 68fb ldr r3, [r7, #12] 8004fc6: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8004fc8: 2301 movs r3, #1 } } 8004fca: 4618 mov r0, r3 8004fcc: 371c adds r7, #28 8004fce: 46bd mov sp, r7 8004fd0: bc80 pop {r7} 8004fd2: 4770 bx lr 08004fd4 : * @param ActiveITs indicates which interrupts will be enabled. * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { 8004fd4: b480 push {r7} 8004fd6: b085 sub sp, #20 8004fd8: af00 add r7, sp, #0 8004fda: 6078 str r0, [r7, #4] 8004fdc: 6039 str r1, [r7, #0] HAL_CAN_StateTypeDef state = hcan->State; 8004fde: 687b ldr r3, [r7, #4] 8004fe0: f893 3020 ldrb.w r3, [r3, #32] 8004fe4: 73fb strb r3, [r7, #15] /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); if ((state == HAL_CAN_STATE_READY) || 8004fe6: 7bfb ldrb r3, [r7, #15] 8004fe8: 2b01 cmp r3, #1 8004fea: d002 beq.n 8004ff2 8004fec: 7bfb ldrb r3, [r7, #15] 8004fee: 2b02 cmp r3, #2 8004ff0: d109 bne.n 8005006 (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); 8004ff2: 687b ldr r3, [r7, #4] 8004ff4: 681b ldr r3, [r3, #0] 8004ff6: 6959 ldr r1, [r3, #20] 8004ff8: 687b ldr r3, [r7, #4] 8004ffa: 681b ldr r3, [r3, #0] 8004ffc: 683a ldr r2, [r7, #0] 8004ffe: 430a orrs r2, r1 8005000: 615a str r2, [r3, #20] /* Return function status */ return HAL_OK; 8005002: 2300 movs r3, #0 8005004: e006 b.n 8005014 } else { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; 8005006: 687b ldr r3, [r7, #4] 8005008: 6a5b ldr r3, [r3, #36] ; 0x24 800500a: f443 2280 orr.w r2, r3, #262144 ; 0x40000 800500e: 687b ldr r3, [r7, #4] 8005010: 625a str r2, [r3, #36] ; 0x24 return HAL_ERROR; 8005012: 2301 movs r3, #1 } } 8005014: 4618 mov r0, r3 8005016: 3714 adds r7, #20 8005018: 46bd mov sp, r7 800501a: bc80 pop {r7} 800501c: 4770 bx lr 0800501e : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { 800501e: b580 push {r7, lr} 8005020: b08a sub sp, #40 ; 0x28 8005022: af00 add r7, sp, #0 8005024: 6078 str r0, [r7, #4] uint32_t errorcode = HAL_CAN_ERROR_NONE; 8005026: 2300 movs r3, #0 8005028: 627b str r3, [r7, #36] ; 0x24 uint32_t interrupts = READ_REG(hcan->Instance->IER); 800502a: 687b ldr r3, [r7, #4] 800502c: 681b ldr r3, [r3, #0] 800502e: 695b ldr r3, [r3, #20] 8005030: 623b str r3, [r7, #32] uint32_t msrflags = READ_REG(hcan->Instance->MSR); 8005032: 687b ldr r3, [r7, #4] 8005034: 681b ldr r3, [r3, #0] 8005036: 685b ldr r3, [r3, #4] 8005038: 61fb str r3, [r7, #28] uint32_t tsrflags = READ_REG(hcan->Instance->TSR); 800503a: 687b ldr r3, [r7, #4] 800503c: 681b ldr r3, [r3, #0] 800503e: 689b ldr r3, [r3, #8] 8005040: 61bb str r3, [r7, #24] uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); 8005042: 687b ldr r3, [r7, #4] 8005044: 681b ldr r3, [r3, #0] 8005046: 68db ldr r3, [r3, #12] 8005048: 617b str r3, [r7, #20] uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); 800504a: 687b ldr r3, [r7, #4] 800504c: 681b ldr r3, [r3, #0] 800504e: 691b ldr r3, [r3, #16] 8005050: 613b str r3, [r7, #16] uint32_t esrflags = READ_REG(hcan->Instance->ESR); 8005052: 687b ldr r3, [r7, #4] 8005054: 681b ldr r3, [r3, #0] 8005056: 699b ldr r3, [r3, #24] 8005058: 60fb str r3, [r7, #12] /* Transmit Mailbox empty interrupt management *****************************/ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) 800505a: 6a3b ldr r3, [r7, #32] 800505c: f003 0301 and.w r3, r3, #1 8005060: 2b00 cmp r3, #0 8005062: d07c beq.n 800515e { /* Transmit Mailbox 0 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP0) != 0U) 8005064: 69bb ldr r3, [r7, #24] 8005066: f003 0301 and.w r3, r3, #1 800506a: 2b00 cmp r3, #0 800506c: d023 beq.n 80050b6 { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); 800506e: 687b ldr r3, [r7, #4] 8005070: 681b ldr r3, [r3, #0] 8005072: 2201 movs r2, #1 8005074: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK0) != 0U) 8005076: 69bb ldr r3, [r7, #24] 8005078: f003 0302 and.w r3, r3, #2 800507c: 2b00 cmp r3, #0 800507e: d003 beq.n 8005088 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); 8005080: 6878 ldr r0, [r7, #4] 8005082: f7fd fda5 bl 8002bd0 8005086: e016 b.n 80050b6 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST0) != 0U) 8005088: 69bb ldr r3, [r7, #24] 800508a: f003 0304 and.w r3, r3, #4 800508e: 2b00 cmp r3, #0 8005090: d004 beq.n 800509c { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; 8005092: 6a7b ldr r3, [r7, #36] ; 0x24 8005094: f443 6300 orr.w r3, r3, #2048 ; 0x800 8005098: 627b str r3, [r7, #36] ; 0x24 800509a: e00c b.n 80050b6 } else if ((tsrflags & CAN_TSR_TERR0) != 0U) 800509c: 69bb ldr r3, [r7, #24] 800509e: f003 0308 and.w r3, r3, #8 80050a2: 2b00 cmp r3, #0 80050a4: d004 beq.n 80050b0 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; 80050a6: 6a7b ldr r3, [r7, #36] ; 0x24 80050a8: f443 5380 orr.w r3, r3, #4096 ; 0x1000 80050ac: 627b str r3, [r7, #36] ; 0x24 80050ae: e002 b.n 80050b6 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox0AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); 80050b0: 6878 ldr r0, [r7, #4] 80050b2: f000 f96b bl 800538c } } } /* Transmit Mailbox 1 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP1) != 0U) 80050b6: 69bb ldr r3, [r7, #24] 80050b8: f403 7380 and.w r3, r3, #256 ; 0x100 80050bc: 2b00 cmp r3, #0 80050be: d024 beq.n 800510a { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); 80050c0: 687b ldr r3, [r7, #4] 80050c2: 681b ldr r3, [r3, #0] 80050c4: f44f 7280 mov.w r2, #256 ; 0x100 80050c8: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK1) != 0U) 80050ca: 69bb ldr r3, [r7, #24] 80050cc: f403 7300 and.w r3, r3, #512 ; 0x200 80050d0: 2b00 cmp r3, #0 80050d2: d003 beq.n 80050dc #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); 80050d4: 6878 ldr r0, [r7, #4] 80050d6: f7fd fd8b bl 8002bf0 80050da: e016 b.n 800510a #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST1) != 0U) 80050dc: 69bb ldr r3, [r7, #24] 80050de: f403 6380 and.w r3, r3, #1024 ; 0x400 80050e2: 2b00 cmp r3, #0 80050e4: d004 beq.n 80050f0 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; 80050e6: 6a7b ldr r3, [r7, #36] ; 0x24 80050e8: f443 5300 orr.w r3, r3, #8192 ; 0x2000 80050ec: 627b str r3, [r7, #36] ; 0x24 80050ee: e00c b.n 800510a } else if ((tsrflags & CAN_TSR_TERR1) != 0U) 80050f0: 69bb ldr r3, [r7, #24] 80050f2: f403 6300 and.w r3, r3, #2048 ; 0x800 80050f6: 2b00 cmp r3, #0 80050f8: d004 beq.n 8005104 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; 80050fa: 6a7b ldr r3, [r7, #36] ; 0x24 80050fc: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8005100: 627b str r3, [r7, #36] ; 0x24 8005102: e002 b.n 800510a #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox1AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); 8005104: 6878 ldr r0, [r7, #4] 8005106: f000 f94a bl 800539e } } } /* Transmit Mailbox 2 management *****************************************/ if ((tsrflags & CAN_TSR_RQCP2) != 0U) 800510a: 69bb ldr r3, [r7, #24] 800510c: f403 3380 and.w r3, r3, #65536 ; 0x10000 8005110: 2b00 cmp r3, #0 8005112: d024 beq.n 800515e { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); 8005114: 687b ldr r3, [r7, #4] 8005116: 681b ldr r3, [r3, #0] 8005118: f44f 3280 mov.w r2, #65536 ; 0x10000 800511c: 609a str r2, [r3, #8] if ((tsrflags & CAN_TSR_TXOK2) != 0U) 800511e: 69bb ldr r3, [r7, #24] 8005120: f403 3300 and.w r3, r3, #131072 ; 0x20000 8005124: 2b00 cmp r3, #0 8005126: d003 beq.n 8005130 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2CompleteCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); 8005128: 6878 ldr r0, [r7, #4] 800512a: f7fd fd71 bl 8002c10 800512e: e016 b.n 800515e #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { if ((tsrflags & CAN_TSR_ALST2) != 0U) 8005130: 69bb ldr r3, [r7, #24] 8005132: f403 2380 and.w r3, r3, #262144 ; 0x40000 8005136: 2b00 cmp r3, #0 8005138: d004 beq.n 8005144 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; 800513a: 6a7b ldr r3, [r7, #36] ; 0x24 800513c: f443 4300 orr.w r3, r3, #32768 ; 0x8000 8005140: 627b str r3, [r7, #36] ; 0x24 8005142: e00c b.n 800515e } else if ((tsrflags & CAN_TSR_TERR2) != 0U) 8005144: 69bb ldr r3, [r7, #24] 8005146: f403 2300 and.w r3, r3, #524288 ; 0x80000 800514a: 2b00 cmp r3, #0 800514c: d004 beq.n 8005158 { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; 800514e: 6a7b ldr r3, [r7, #36] ; 0x24 8005150: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8005154: 627b str r3, [r7, #36] ; 0x24 8005156: e002 b.n 800515e #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->TxMailbox2AbortCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); 8005158: 6878 ldr r0, [r7, #4] 800515a: f000 f929 bl 80053b0 } } } /* Receive FIFO 0 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) 800515e: 6a3b ldr r3, [r7, #32] 8005160: f003 0308 and.w r3, r3, #8 8005164: 2b00 cmp r3, #0 8005166: d00c beq.n 8005182 { if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) 8005168: 697b ldr r3, [r7, #20] 800516a: f003 0310 and.w r3, r3, #16 800516e: 2b00 cmp r3, #0 8005170: d007 beq.n 8005182 { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; 8005172: 6a7b ldr r3, [r7, #36] ; 0x24 8005174: f443 7300 orr.w r3, r3, #512 ; 0x200 8005178: 627b str r3, [r7, #36] ; 0x24 /* Clear FIFO0 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); 800517a: 687b ldr r3, [r7, #4] 800517c: 681b ldr r3, [r3, #0] 800517e: 2210 movs r2, #16 8005180: 60da str r2, [r3, #12] } } /* Receive FIFO 0 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) 8005182: 6a3b ldr r3, [r7, #32] 8005184: f003 0304 and.w r3, r3, #4 8005188: 2b00 cmp r3, #0 800518a: d00b beq.n 80051a4 { if ((rf0rflags & CAN_RF0R_FULL0) != 0U) 800518c: 697b ldr r3, [r7, #20] 800518e: f003 0308 and.w r3, r3, #8 8005192: 2b00 cmp r3, #0 8005194: d006 beq.n 80051a4 { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); 8005196: 687b ldr r3, [r7, #4] 8005198: 681b ldr r3, [r3, #0] 800519a: 2208 movs r2, #8 800519c: 60da str r2, [r3, #12] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); 800519e: 6878 ldr r0, [r7, #4] 80051a0: f000 f90f bl 80053c2 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) 80051a4: 6a3b ldr r3, [r7, #32] 80051a6: f003 0302 and.w r3, r3, #2 80051aa: 2b00 cmp r3, #0 80051ac: d009 beq.n 80051c2 { /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) 80051ae: 687b ldr r3, [r7, #4] 80051b0: 681b ldr r3, [r3, #0] 80051b2: 68db ldr r3, [r3, #12] 80051b4: f003 0303 and.w r3, r3, #3 80051b8: 2b00 cmp r3, #0 80051ba: d002 beq.n 80051c2 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); 80051bc: 6878 ldr r0, [r7, #4] 80051be: f7fd fae1 bl 8002784 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) 80051c2: 6a3b ldr r3, [r7, #32] 80051c4: f003 0340 and.w r3, r3, #64 ; 0x40 80051c8: 2b00 cmp r3, #0 80051ca: d00c beq.n 80051e6 { if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) 80051cc: 693b ldr r3, [r7, #16] 80051ce: f003 0310 and.w r3, r3, #16 80051d2: 2b00 cmp r3, #0 80051d4: d007 beq.n 80051e6 { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; 80051d6: 6a7b ldr r3, [r7, #36] ; 0x24 80051d8: f443 6380 orr.w r3, r3, #1024 ; 0x400 80051dc: 627b str r3, [r7, #36] ; 0x24 /* Clear FIFO1 Overrun Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); 80051de: 687b ldr r3, [r7, #4] 80051e0: 681b ldr r3, [r3, #0] 80051e2: 2210 movs r2, #16 80051e4: 611a str r2, [r3, #16] } } /* Receive FIFO 1 full interrupt management ********************************/ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) 80051e6: 6a3b ldr r3, [r7, #32] 80051e8: f003 0320 and.w r3, r3, #32 80051ec: 2b00 cmp r3, #0 80051ee: d00b beq.n 8005208 { if ((rf1rflags & CAN_RF1R_FULL1) != 0U) 80051f0: 693b ldr r3, [r7, #16] 80051f2: f003 0308 and.w r3, r3, #8 80051f6: 2b00 cmp r3, #0 80051f8: d006 beq.n 8005208 { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); 80051fa: 687b ldr r3, [r7, #4] 80051fc: 681b ldr r3, [r3, #0] 80051fe: 2208 movs r2, #8 8005200: 611a str r2, [r3, #16] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1FullCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); 8005202: 6878 ldr r0, [r7, #4] 8005204: f000 f8e6 bl 80053d4 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) 8005208: 6a3b ldr r3, [r7, #32] 800520a: f003 0310 and.w r3, r3, #16 800520e: 2b00 cmp r3, #0 8005210: d009 beq.n 8005226 { /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) 8005212: 687b ldr r3, [r7, #4] 8005214: 681b ldr r3, [r3, #0] 8005216: 691b ldr r3, [r3, #16] 8005218: f003 0303 and.w r3, r3, #3 800521c: 2b00 cmp r3, #0 800521e: d002 beq.n 8005226 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); 8005220: 6878 ldr r0, [r7, #4] 8005222: f7fd fc93 bl 8002b4c #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) 8005226: 6a3b ldr r3, [r7, #32] 8005228: f403 3300 and.w r3, r3, #131072 ; 0x20000 800522c: 2b00 cmp r3, #0 800522e: d00b beq.n 8005248 { if ((msrflags & CAN_MSR_SLAKI) != 0U) 8005230: 69fb ldr r3, [r7, #28] 8005232: f003 0310 and.w r3, r3, #16 8005236: 2b00 cmp r3, #0 8005238: d006 beq.n 8005248 { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); 800523a: 687b ldr r3, [r7, #4] 800523c: 681b ldr r3, [r3, #0] 800523e: 2210 movs r2, #16 8005240: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->SleepCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); 8005242: 6878 ldr r0, [r7, #4] 8005244: f000 f8cf bl 80053e6 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ if ((interrupts & CAN_IT_WAKEUP) != 0U) 8005248: 6a3b ldr r3, [r7, #32] 800524a: f403 3380 and.w r3, r3, #65536 ; 0x10000 800524e: 2b00 cmp r3, #0 8005250: d00b beq.n 800526a { if ((msrflags & CAN_MSR_WKUI) != 0U) 8005252: 69fb ldr r3, [r7, #28] 8005254: f003 0308 and.w r3, r3, #8 8005258: 2b00 cmp r3, #0 800525a: d006 beq.n 800526a { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); 800525c: 687b ldr r3, [r7, #4] 800525e: 681b ldr r3, [r3, #0] 8005260: 2208 movs r2, #8 8005262: 605a str r2, [r3, #4] #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->WakeUpFromRxMsgCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); 8005264: 6878 ldr r0, [r7, #4] 8005266: f000 f8c7 bl 80053f8 #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ if ((interrupts & CAN_IT_ERROR) != 0U) 800526a: 6a3b ldr r3, [r7, #32] 800526c: f403 4300 and.w r3, r3, #32768 ; 0x8000 8005270: 2b00 cmp r3, #0 8005272: d07b beq.n 800536c { if ((msrflags & CAN_MSR_ERRI) != 0U) 8005274: 69fb ldr r3, [r7, #28] 8005276: f003 0304 and.w r3, r3, #4 800527a: 2b00 cmp r3, #0 800527c: d072 beq.n 8005364 { /* Check Error Warning Flag */ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800527e: 6a3b ldr r3, [r7, #32] 8005280: f403 7380 and.w r3, r3, #256 ; 0x100 8005284: 2b00 cmp r3, #0 8005286: d008 beq.n 800529a ((esrflags & CAN_ESR_EWGF) != 0U)) 8005288: 68fb ldr r3, [r7, #12] 800528a: f003 0301 and.w r3, r3, #1 if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && 800528e: 2b00 cmp r3, #0 8005290: d003 beq.n 800529a { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; 8005292: 6a7b ldr r3, [r7, #36] ; 0x24 8005294: f043 0301 orr.w r3, r3, #1 8005298: 627b str r3, [r7, #36] ; 0x24 /* No need for clear of Error Warning Flag as read-only */ } /* Check Error Passive Flag */ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 800529a: 6a3b ldr r3, [r7, #32] 800529c: f403 7300 and.w r3, r3, #512 ; 0x200 80052a0: 2b00 cmp r3, #0 80052a2: d008 beq.n 80052b6 ((esrflags & CAN_ESR_EPVF) != 0U)) 80052a4: 68fb ldr r3, [r7, #12] 80052a6: f003 0302 and.w r3, r3, #2 if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && 80052aa: 2b00 cmp r3, #0 80052ac: d003 beq.n 80052b6 { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; 80052ae: 6a7b ldr r3, [r7, #36] ; 0x24 80052b0: f043 0302 orr.w r3, r3, #2 80052b4: 627b str r3, [r7, #36] ; 0x24 /* No need for clear of Error Passive Flag as read-only */ } /* Check Bus-off Flag */ if (((interrupts & CAN_IT_BUSOFF) != 0U) && 80052b6: 6a3b ldr r3, [r7, #32] 80052b8: f403 6380 and.w r3, r3, #1024 ; 0x400 80052bc: 2b00 cmp r3, #0 80052be: d008 beq.n 80052d2 ((esrflags & CAN_ESR_BOFF) != 0U)) 80052c0: 68fb ldr r3, [r7, #12] 80052c2: f003 0304 and.w r3, r3, #4 if (((interrupts & CAN_IT_BUSOFF) != 0U) && 80052c6: 2b00 cmp r3, #0 80052c8: d003 beq.n 80052d2 { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; 80052ca: 6a7b ldr r3, [r7, #36] ; 0x24 80052cc: f043 0304 orr.w r3, r3, #4 80052d0: 627b str r3, [r7, #36] ; 0x24 /* No need for clear of Error Bus-Off as read-only */ } /* Check Last Error Code Flag */ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 80052d2: 6a3b ldr r3, [r7, #32] 80052d4: f403 6300 and.w r3, r3, #2048 ; 0x800 80052d8: 2b00 cmp r3, #0 80052da: d043 beq.n 8005364 ((esrflags & CAN_ESR_LEC) != 0U)) 80052dc: 68fb ldr r3, [r7, #12] 80052de: f003 0370 and.w r3, r3, #112 ; 0x70 if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && 80052e2: 2b00 cmp r3, #0 80052e4: d03e beq.n 8005364 { switch (esrflags & CAN_ESR_LEC) 80052e6: 68fb ldr r3, [r7, #12] 80052e8: f003 0370 and.w r3, r3, #112 ; 0x70 80052ec: 2b60 cmp r3, #96 ; 0x60 80052ee: d02b beq.n 8005348 80052f0: 2b60 cmp r3, #96 ; 0x60 80052f2: d82e bhi.n 8005352 80052f4: 2b50 cmp r3, #80 ; 0x50 80052f6: d022 beq.n 800533e 80052f8: 2b50 cmp r3, #80 ; 0x50 80052fa: d82a bhi.n 8005352 80052fc: 2b40 cmp r3, #64 ; 0x40 80052fe: d019 beq.n 8005334 8005300: 2b40 cmp r3, #64 ; 0x40 8005302: d826 bhi.n 8005352 8005304: 2b30 cmp r3, #48 ; 0x30 8005306: d010 beq.n 800532a 8005308: 2b30 cmp r3, #48 ; 0x30 800530a: d822 bhi.n 8005352 800530c: 2b10 cmp r3, #16 800530e: d002 beq.n 8005316 8005310: 2b20 cmp r3, #32 8005312: d005 beq.n 8005320 case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): /* Set CAN error code to CRC error */ errorcode |= HAL_CAN_ERROR_CRC; break; default: break; 8005314: e01d b.n 8005352 errorcode |= HAL_CAN_ERROR_STF; 8005316: 6a7b ldr r3, [r7, #36] ; 0x24 8005318: f043 0308 orr.w r3, r3, #8 800531c: 627b str r3, [r7, #36] ; 0x24 break; 800531e: e019 b.n 8005354 errorcode |= HAL_CAN_ERROR_FOR; 8005320: 6a7b ldr r3, [r7, #36] ; 0x24 8005322: f043 0310 orr.w r3, r3, #16 8005326: 627b str r3, [r7, #36] ; 0x24 break; 8005328: e014 b.n 8005354 errorcode |= HAL_CAN_ERROR_ACK; 800532a: 6a7b ldr r3, [r7, #36] ; 0x24 800532c: f043 0320 orr.w r3, r3, #32 8005330: 627b str r3, [r7, #36] ; 0x24 break; 8005332: e00f b.n 8005354 errorcode |= HAL_CAN_ERROR_BR; 8005334: 6a7b ldr r3, [r7, #36] ; 0x24 8005336: f043 0340 orr.w r3, r3, #64 ; 0x40 800533a: 627b str r3, [r7, #36] ; 0x24 break; 800533c: e00a b.n 8005354 errorcode |= HAL_CAN_ERROR_BD; 800533e: 6a7b ldr r3, [r7, #36] ; 0x24 8005340: f043 0380 orr.w r3, r3, #128 ; 0x80 8005344: 627b str r3, [r7, #36] ; 0x24 break; 8005346: e005 b.n 8005354 errorcode |= HAL_CAN_ERROR_CRC; 8005348: 6a7b ldr r3, [r7, #36] ; 0x24 800534a: f443 7380 orr.w r3, r3, #256 ; 0x100 800534e: 627b str r3, [r7, #36] ; 0x24 break; 8005350: e000 b.n 8005354 break; 8005352: bf00 nop } /* Clear Last error code Flag */ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); 8005354: 687b ldr r3, [r7, #4] 8005356: 681b ldr r3, [r3, #0] 8005358: 699a ldr r2, [r3, #24] 800535a: 687b ldr r3, [r7, #4] 800535c: 681b ldr r3, [r3, #0] 800535e: f022 0270 bic.w r2, r2, #112 ; 0x70 8005362: 619a str r2, [r3, #24] } } /* Clear ERRI Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); 8005364: 687b ldr r3, [r7, #4] 8005366: 681b ldr r3, [r3, #0] 8005368: 2204 movs r2, #4 800536a: 605a str r2, [r3, #4] } /* Call the Error call Back in case of Errors */ if (errorcode != HAL_CAN_ERROR_NONE) 800536c: 6a7b ldr r3, [r7, #36] ; 0x24 800536e: 2b00 cmp r3, #0 8005370: d008 beq.n 8005384 { /* Update error code in handle */ hcan->ErrorCode |= errorcode; 8005372: 687b ldr r3, [r7, #4] 8005374: 6a5a ldr r2, [r3, #36] ; 0x24 8005376: 6a7b ldr r3, [r7, #36] ; 0x24 8005378: 431a orrs r2, r3 800537a: 687b ldr r3, [r7, #4] 800537c: 625a str r2, [r3, #36] ; 0x24 #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->ErrorCallback(hcan); #else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); 800537e: 6878 ldr r0, [r7, #4] 8005380: f000 f843 bl 800540a #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } 8005384: bf00 nop 8005386: 3728 adds r7, #40 ; 0x28 8005388: 46bd mov sp, r7 800538a: bd80 pop {r7, pc} 0800538c : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { 800538c: b480 push {r7} 800538e: b083 sub sp, #12 8005390: af00 add r7, sp, #0 8005392: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox0AbortCallback could be implemented in the user file */ } 8005394: bf00 nop 8005396: 370c adds r7, #12 8005398: 46bd mov sp, r7 800539a: bc80 pop {r7} 800539c: 4770 bx lr 0800539e : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { 800539e: b480 push {r7} 80053a0: b083 sub sp, #12 80053a2: af00 add r7, sp, #0 80053a4: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox1AbortCallback could be implemented in the user file */ } 80053a6: bf00 nop 80053a8: 370c adds r7, #12 80053aa: 46bd mov sp, r7 80053ac: bc80 pop {r7} 80053ae: 4770 bx lr 080053b0 : * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { 80053b0: b480 push {r7} 80053b2: b083 sub sp, #12 80053b4: af00 add r7, sp, #0 80053b6: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_TxMailbox2AbortCallback could be implemented in the user file */ } 80053b8: bf00 nop 80053ba: 370c adds r7, #12 80053bc: 46bd mov sp, r7 80053be: bc80 pop {r7} 80053c0: 4770 bx lr 080053c2 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { 80053c2: b480 push {r7} 80053c4: b083 sub sp, #12 80053c6: af00 add r7, sp, #0 80053c8: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo0FullCallback could be implemented in the user file */ } 80053ca: bf00 nop 80053cc: 370c adds r7, #12 80053ce: 46bd mov sp, r7 80053d0: bc80 pop {r7} 80053d2: 4770 bx lr 080053d4 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { 80053d4: b480 push {r7} 80053d6: b083 sub sp, #12 80053d8: af00 add r7, sp, #0 80053da: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_RxFifo1FullCallback could be implemented in the user file */ } 80053dc: bf00 nop 80053de: 370c adds r7, #12 80053e0: 46bd mov sp, r7 80053e2: bc80 pop {r7} 80053e4: 4770 bx lr 080053e6 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { 80053e6: b480 push {r7} 80053e8: b083 sub sp, #12 80053ea: af00 add r7, sp, #0 80053ec: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_SleepCallback could be implemented in the user file */ } 80053ee: bf00 nop 80053f0: 370c adds r7, #12 80053f2: 46bd mov sp, r7 80053f4: bc80 pop {r7} 80053f6: 4770 bx lr 080053f8 : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { 80053f8: b480 push {r7} 80053fa: b083 sub sp, #12 80053fc: af00 add r7, sp, #0 80053fe: 6078 str r0, [r7, #4] /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the user file */ } 8005400: bf00 nop 8005402: 370c adds r7, #12 8005404: 46bd mov sp, r7 8005406: bc80 pop {r7} 8005408: 4770 bx lr 0800540a : * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { 800540a: b480 push {r7} 800540c: b083 sub sp, #12 800540e: af00 add r7, sp, #0 8005410: 6078 str r0, [r7, #4] UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } 8005412: bf00 nop 8005414: 370c adds r7, #12 8005416: 46bd mov sp, r7 8005418: bc80 pop {r7} 800541a: 4770 bx lr 0800541c <__NVIC_SetPriorityGrouping>: { 800541c: b480 push {r7} 800541e: b085 sub sp, #20 8005420: af00 add r7, sp, #0 8005422: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8005424: 687b ldr r3, [r7, #4] 8005426: f003 0307 and.w r3, r3, #7 800542a: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 800542c: 4b0c ldr r3, [pc, #48] ; (8005460 <__NVIC_SetPriorityGrouping+0x44>) 800542e: 68db ldr r3, [r3, #12] 8005430: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8005432: 68ba ldr r2, [r7, #8] 8005434: f64f 03ff movw r3, #63743 ; 0xf8ff 8005438: 4013 ands r3, r2 800543a: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 800543c: 68fb ldr r3, [r7, #12] 800543e: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8005440: 68bb ldr r3, [r7, #8] 8005442: 4313 orrs r3, r2 reg_value = (reg_value | 8005444: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 8005448: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800544c: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800544e: 4a04 ldr r2, [pc, #16] ; (8005460 <__NVIC_SetPriorityGrouping+0x44>) 8005450: 68bb ldr r3, [r7, #8] 8005452: 60d3 str r3, [r2, #12] } 8005454: bf00 nop 8005456: 3714 adds r7, #20 8005458: 46bd mov sp, r7 800545a: bc80 pop {r7} 800545c: 4770 bx lr 800545e: bf00 nop 8005460: e000ed00 .word 0xe000ed00 08005464 <__NVIC_GetPriorityGrouping>: { 8005464: b480 push {r7} 8005466: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8005468: 4b04 ldr r3, [pc, #16] ; (800547c <__NVIC_GetPriorityGrouping+0x18>) 800546a: 68db ldr r3, [r3, #12] 800546c: 0a1b lsrs r3, r3, #8 800546e: f003 0307 and.w r3, r3, #7 } 8005472: 4618 mov r0, r3 8005474: 46bd mov sp, r7 8005476: bc80 pop {r7} 8005478: 4770 bx lr 800547a: bf00 nop 800547c: e000ed00 .word 0xe000ed00 08005480 <__NVIC_EnableIRQ>: { 8005480: b480 push {r7} 8005482: b083 sub sp, #12 8005484: af00 add r7, sp, #0 8005486: 4603 mov r3, r0 8005488: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800548a: f997 3007 ldrsb.w r3, [r7, #7] 800548e: 2b00 cmp r3, #0 8005490: db0b blt.n 80054aa <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8005492: 79fb ldrb r3, [r7, #7] 8005494: f003 021f and.w r2, r3, #31 8005498: 4906 ldr r1, [pc, #24] ; (80054b4 <__NVIC_EnableIRQ+0x34>) 800549a: f997 3007 ldrsb.w r3, [r7, #7] 800549e: 095b lsrs r3, r3, #5 80054a0: 2001 movs r0, #1 80054a2: fa00 f202 lsl.w r2, r0, r2 80054a6: f841 2023 str.w r2, [r1, r3, lsl #2] } 80054aa: bf00 nop 80054ac: 370c adds r7, #12 80054ae: 46bd mov sp, r7 80054b0: bc80 pop {r7} 80054b2: 4770 bx lr 80054b4: e000e100 .word 0xe000e100 080054b8 <__NVIC_SetPriority>: { 80054b8: b480 push {r7} 80054ba: b083 sub sp, #12 80054bc: af00 add r7, sp, #0 80054be: 4603 mov r3, r0 80054c0: 6039 str r1, [r7, #0] 80054c2: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80054c4: f997 3007 ldrsb.w r3, [r7, #7] 80054c8: 2b00 cmp r3, #0 80054ca: db0a blt.n 80054e2 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80054cc: 683b ldr r3, [r7, #0] 80054ce: b2da uxtb r2, r3 80054d0: 490c ldr r1, [pc, #48] ; (8005504 <__NVIC_SetPriority+0x4c>) 80054d2: f997 3007 ldrsb.w r3, [r7, #7] 80054d6: 0112 lsls r2, r2, #4 80054d8: b2d2 uxtb r2, r2 80054da: 440b add r3, r1 80054dc: f883 2300 strb.w r2, [r3, #768] ; 0x300 } 80054e0: e00a b.n 80054f8 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80054e2: 683b ldr r3, [r7, #0] 80054e4: b2da uxtb r2, r3 80054e6: 4908 ldr r1, [pc, #32] ; (8005508 <__NVIC_SetPriority+0x50>) 80054e8: 79fb ldrb r3, [r7, #7] 80054ea: f003 030f and.w r3, r3, #15 80054ee: 3b04 subs r3, #4 80054f0: 0112 lsls r2, r2, #4 80054f2: b2d2 uxtb r2, r2 80054f4: 440b add r3, r1 80054f6: 761a strb r2, [r3, #24] } 80054f8: bf00 nop 80054fa: 370c adds r7, #12 80054fc: 46bd mov sp, r7 80054fe: bc80 pop {r7} 8005500: 4770 bx lr 8005502: bf00 nop 8005504: e000e100 .word 0xe000e100 8005508: e000ed00 .word 0xe000ed00 0800550c : { 800550c: b480 push {r7} 800550e: b089 sub sp, #36 ; 0x24 8005510: af00 add r7, sp, #0 8005512: 60f8 str r0, [r7, #12] 8005514: 60b9 str r1, [r7, #8] 8005516: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8005518: 68fb ldr r3, [r7, #12] 800551a: f003 0307 and.w r3, r3, #7 800551e: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8005520: 69fb ldr r3, [r7, #28] 8005522: f1c3 0307 rsb r3, r3, #7 8005526: 2b04 cmp r3, #4 8005528: bf28 it cs 800552a: 2304 movcs r3, #4 800552c: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800552e: 69fb ldr r3, [r7, #28] 8005530: 3304 adds r3, #4 8005532: 2b06 cmp r3, #6 8005534: d902 bls.n 800553c 8005536: 69fb ldr r3, [r7, #28] 8005538: 3b03 subs r3, #3 800553a: e000 b.n 800553e 800553c: 2300 movs r3, #0 800553e: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8005540: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 8005544: 69bb ldr r3, [r7, #24] 8005546: fa02 f303 lsl.w r3, r2, r3 800554a: 43da mvns r2, r3 800554c: 68bb ldr r3, [r7, #8] 800554e: 401a ands r2, r3 8005550: 697b ldr r3, [r7, #20] 8005552: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8005554: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8005558: 697b ldr r3, [r7, #20] 800555a: fa01 f303 lsl.w r3, r1, r3 800555e: 43d9 mvns r1, r3 8005560: 687b ldr r3, [r7, #4] 8005562: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8005564: 4313 orrs r3, r2 } 8005566: 4618 mov r0, r3 8005568: 3724 adds r7, #36 ; 0x24 800556a: 46bd mov sp, r7 800556c: bc80 pop {r7} 800556e: 4770 bx lr 08005570 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8005570: b580 push {r7, lr} 8005572: b082 sub sp, #8 8005574: af00 add r7, sp, #0 8005576: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8005578: 687b ldr r3, [r7, #4] 800557a: 3b01 subs r3, #1 800557c: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8005580: d301 bcc.n 8005586 { return (1UL); /* Reload value impossible */ 8005582: 2301 movs r3, #1 8005584: e00f b.n 80055a6 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8005586: 4a0a ldr r2, [pc, #40] ; (80055b0 ) 8005588: 687b ldr r3, [r7, #4] 800558a: 3b01 subs r3, #1 800558c: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800558e: 210f movs r1, #15 8005590: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8005594: f7ff ff90 bl 80054b8 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8005598: 4b05 ldr r3, [pc, #20] ; (80055b0 ) 800559a: 2200 movs r2, #0 800559c: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800559e: 4b04 ldr r3, [pc, #16] ; (80055b0 ) 80055a0: 2207 movs r2, #7 80055a2: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 80055a4: 2300 movs r3, #0 } 80055a6: 4618 mov r0, r3 80055a8: 3708 adds r7, #8 80055aa: 46bd mov sp, r7 80055ac: bd80 pop {r7, pc} 80055ae: bf00 nop 80055b0: e000e010 .word 0xe000e010 080055b4 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80055b4: b580 push {r7, lr} 80055b6: b082 sub sp, #8 80055b8: af00 add r7, sp, #0 80055ba: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80055bc: 6878 ldr r0, [r7, #4] 80055be: f7ff ff2d bl 800541c <__NVIC_SetPriorityGrouping> } 80055c2: bf00 nop 80055c4: 3708 adds r7, #8 80055c6: 46bd mov sp, r7 80055c8: bd80 pop {r7, pc} 080055ca : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80055ca: b580 push {r7, lr} 80055cc: b086 sub sp, #24 80055ce: af00 add r7, sp, #0 80055d0: 4603 mov r3, r0 80055d2: 60b9 str r1, [r7, #8] 80055d4: 607a str r2, [r7, #4] 80055d6: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 80055d8: 2300 movs r3, #0 80055da: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 80055dc: f7ff ff42 bl 8005464 <__NVIC_GetPriorityGrouping> 80055e0: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 80055e2: 687a ldr r2, [r7, #4] 80055e4: 68b9 ldr r1, [r7, #8] 80055e6: 6978 ldr r0, [r7, #20] 80055e8: f7ff ff90 bl 800550c 80055ec: 4602 mov r2, r0 80055ee: f997 300f ldrsb.w r3, [r7, #15] 80055f2: 4611 mov r1, r2 80055f4: 4618 mov r0, r3 80055f6: f7ff ff5f bl 80054b8 <__NVIC_SetPriority> } 80055fa: bf00 nop 80055fc: 3718 adds r7, #24 80055fe: 46bd mov sp, r7 8005600: bd80 pop {r7, pc} 08005602 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8005602: b580 push {r7, lr} 8005604: b082 sub sp, #8 8005606: af00 add r7, sp, #0 8005608: 4603 mov r3, r0 800560a: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800560c: f997 3007 ldrsb.w r3, [r7, #7] 8005610: 4618 mov r0, r3 8005612: f7ff ff35 bl 8005480 <__NVIC_EnableIRQ> } 8005616: bf00 nop 8005618: 3708 adds r7, #8 800561a: 46bd mov sp, r7 800561c: bd80 pop {r7, pc} 0800561e : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800561e: b580 push {r7, lr} 8005620: b082 sub sp, #8 8005622: af00 add r7, sp, #0 8005624: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8005626: 6878 ldr r0, [r7, #4] 8005628: f7ff ffa2 bl 8005570 800562c: 4603 mov r3, r0 } 800562e: 4618 mov r0, r3 8005630: 3708 adds r7, #8 8005632: 46bd mov sp, r7 8005634: bd80 pop {r7, pc} 08005636 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8005636: b480 push {r7} 8005638: b085 sub sp, #20 800563a: af00 add r7, sp, #0 800563c: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800563e: 2300 movs r3, #0 8005640: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 8005642: 687b ldr r3, [r7, #4] 8005644: f893 3021 ldrb.w r3, [r3, #33] ; 0x21 8005648: 2b02 cmp r3, #2 800564a: d008 beq.n 800565e { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800564c: 687b ldr r3, [r7, #4] 800564e: 2204 movs r2, #4 8005650: 639a str r2, [r3, #56] ; 0x38 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8005652: 687b ldr r3, [r7, #4] 8005654: 2200 movs r2, #0 8005656: f883 2020 strb.w r2, [r3, #32] return HAL_ERROR; 800565a: 2301 movs r3, #1 800565c: e020 b.n 80056a0 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800565e: 687b ldr r3, [r7, #4] 8005660: 681b ldr r3, [r3, #0] 8005662: 681a ldr r2, [r3, #0] 8005664: 687b ldr r3, [r7, #4] 8005666: 681b ldr r3, [r3, #0] 8005668: f022 020e bic.w r2, r2, #14 800566c: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800566e: 687b ldr r3, [r7, #4] 8005670: 681b ldr r3, [r3, #0] 8005672: 681a ldr r2, [r3, #0] 8005674: 687b ldr r3, [r7, #4] 8005676: 681b ldr r3, [r3, #0] 8005678: f022 0201 bic.w r2, r2, #1 800567c: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 800567e: 687b ldr r3, [r7, #4] 8005680: 6c1a ldr r2, [r3, #64] ; 0x40 8005682: 687b ldr r3, [r7, #4] 8005684: 6bdb ldr r3, [r3, #60] ; 0x3c 8005686: 2101 movs r1, #1 8005688: fa01 f202 lsl.w r2, r1, r2 800568c: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800568e: 687b ldr r3, [r7, #4] 8005690: 2201 movs r2, #1 8005692: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8005696: 687b ldr r3, [r7, #4] 8005698: 2200 movs r2, #0 800569a: f883 2020 strb.w r2, [r3, #32] return status; 800569e: 7bfb ldrb r3, [r7, #15] } 80056a0: 4618 mov r0, r3 80056a2: 3714 adds r7, #20 80056a4: 46bd mov sp, r7 80056a6: bc80 pop {r7} 80056a8: 4770 bx lr ... 080056ac : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 80056ac: b580 push {r7, lr} 80056ae: b084 sub sp, #16 80056b0: af00 add r7, sp, #0 80056b2: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80056b4: 2300 movs r3, #0 80056b6: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 80056b8: 687b ldr r3, [r7, #4] 80056ba: f893 3021 ldrb.w r3, [r3, #33] ; 0x21 80056be: 2b02 cmp r3, #2 80056c0: d005 beq.n 80056ce { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80056c2: 687b ldr r3, [r7, #4] 80056c4: 2204 movs r2, #4 80056c6: 639a str r2, [r3, #56] ; 0x38 status = HAL_ERROR; 80056c8: 2301 movs r3, #1 80056ca: 73fb strb r3, [r7, #15] 80056cc: e0d6 b.n 800587c } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80056ce: 687b ldr r3, [r7, #4] 80056d0: 681b ldr r3, [r3, #0] 80056d2: 681a ldr r2, [r3, #0] 80056d4: 687b ldr r3, [r7, #4] 80056d6: 681b ldr r3, [r3, #0] 80056d8: f022 020e bic.w r2, r2, #14 80056dc: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 80056de: 687b ldr r3, [r7, #4] 80056e0: 681b ldr r3, [r3, #0] 80056e2: 681a ldr r2, [r3, #0] 80056e4: 687b ldr r3, [r7, #4] 80056e6: 681b ldr r3, [r3, #0] 80056e8: f022 0201 bic.w r2, r2, #1 80056ec: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 80056ee: 687b ldr r3, [r7, #4] 80056f0: 681b ldr r3, [r3, #0] 80056f2: 461a mov r2, r3 80056f4: 4b64 ldr r3, [pc, #400] ; (8005888 ) 80056f6: 429a cmp r2, r3 80056f8: d958 bls.n 80057ac 80056fa: 687b ldr r3, [r7, #4] 80056fc: 681b ldr r3, [r3, #0] 80056fe: 4a63 ldr r2, [pc, #396] ; (800588c ) 8005700: 4293 cmp r3, r2 8005702: d04f beq.n 80057a4 8005704: 687b ldr r3, [r7, #4] 8005706: 681b ldr r3, [r3, #0] 8005708: 4a61 ldr r2, [pc, #388] ; (8005890 ) 800570a: 4293 cmp r3, r2 800570c: d048 beq.n 80057a0 800570e: 687b ldr r3, [r7, #4] 8005710: 681b ldr r3, [r3, #0] 8005712: 4a60 ldr r2, [pc, #384] ; (8005894 ) 8005714: 4293 cmp r3, r2 8005716: d040 beq.n 800579a 8005718: 687b ldr r3, [r7, #4] 800571a: 681b ldr r3, [r3, #0] 800571c: 4a5e ldr r2, [pc, #376] ; (8005898 ) 800571e: 4293 cmp r3, r2 8005720: d038 beq.n 8005794 8005722: 687b ldr r3, [r7, #4] 8005724: 681b ldr r3, [r3, #0] 8005726: 4a5d ldr r2, [pc, #372] ; (800589c ) 8005728: 4293 cmp r3, r2 800572a: d030 beq.n 800578e 800572c: 687b ldr r3, [r7, #4] 800572e: 681b ldr r3, [r3, #0] 8005730: 4a5b ldr r2, [pc, #364] ; (80058a0 ) 8005732: 4293 cmp r3, r2 8005734: d028 beq.n 8005788 8005736: 687b ldr r3, [r7, #4] 8005738: 681b ldr r3, [r3, #0] 800573a: 4a53 ldr r2, [pc, #332] ; (8005888 ) 800573c: 4293 cmp r3, r2 800573e: d020 beq.n 8005782 8005740: 687b ldr r3, [r7, #4] 8005742: 681b ldr r3, [r3, #0] 8005744: 4a57 ldr r2, [pc, #348] ; (80058a4 ) 8005746: 4293 cmp r3, r2 8005748: d019 beq.n 800577e 800574a: 687b ldr r3, [r7, #4] 800574c: 681b ldr r3, [r3, #0] 800574e: 4a56 ldr r2, [pc, #344] ; (80058a8 ) 8005750: 4293 cmp r3, r2 8005752: d012 beq.n 800577a 8005754: 687b ldr r3, [r7, #4] 8005756: 681b ldr r3, [r3, #0] 8005758: 4a54 ldr r2, [pc, #336] ; (80058ac ) 800575a: 4293 cmp r3, r2 800575c: d00a beq.n 8005774 800575e: 687b ldr r3, [r7, #4] 8005760: 681b ldr r3, [r3, #0] 8005762: 4a53 ldr r2, [pc, #332] ; (80058b0 ) 8005764: 4293 cmp r3, r2 8005766: d102 bne.n 800576e 8005768: f44f 5380 mov.w r3, #4096 ; 0x1000 800576c: e01b b.n 80057a6 800576e: f44f 3380 mov.w r3, #65536 ; 0x10000 8005772: e018 b.n 80057a6 8005774: f44f 7380 mov.w r3, #256 ; 0x100 8005778: e015 b.n 80057a6 800577a: 2310 movs r3, #16 800577c: e013 b.n 80057a6 800577e: 2301 movs r3, #1 8005780: e011 b.n 80057a6 8005782: f04f 7380 mov.w r3, #16777216 ; 0x1000000 8005786: e00e b.n 80057a6 8005788: f44f 1380 mov.w r3, #1048576 ; 0x100000 800578c: e00b b.n 80057a6 800578e: f44f 3380 mov.w r3, #65536 ; 0x10000 8005792: e008 b.n 80057a6 8005794: f44f 5380 mov.w r3, #4096 ; 0x1000 8005798: e005 b.n 80057a6 800579a: f44f 7380 mov.w r3, #256 ; 0x100 800579e: e002 b.n 80057a6 80057a0: 2310 movs r3, #16 80057a2: e000 b.n 80057a6 80057a4: 2301 movs r3, #1 80057a6: 4a43 ldr r2, [pc, #268] ; (80058b4 ) 80057a8: 6053 str r3, [r2, #4] 80057aa: e057 b.n 800585c 80057ac: 687b ldr r3, [r7, #4] 80057ae: 681b ldr r3, [r3, #0] 80057b0: 4a36 ldr r2, [pc, #216] ; (800588c ) 80057b2: 4293 cmp r3, r2 80057b4: d04f beq.n 8005856 80057b6: 687b ldr r3, [r7, #4] 80057b8: 681b ldr r3, [r3, #0] 80057ba: 4a35 ldr r2, [pc, #212] ; (8005890 ) 80057bc: 4293 cmp r3, r2 80057be: d048 beq.n 8005852 80057c0: 687b ldr r3, [r7, #4] 80057c2: 681b ldr r3, [r3, #0] 80057c4: 4a33 ldr r2, [pc, #204] ; (8005894 ) 80057c6: 4293 cmp r3, r2 80057c8: d040 beq.n 800584c 80057ca: 687b ldr r3, [r7, #4] 80057cc: 681b ldr r3, [r3, #0] 80057ce: 4a32 ldr r2, [pc, #200] ; (8005898 ) 80057d0: 4293 cmp r3, r2 80057d2: d038 beq.n 8005846 80057d4: 687b ldr r3, [r7, #4] 80057d6: 681b ldr r3, [r3, #0] 80057d8: 4a30 ldr r2, [pc, #192] ; (800589c ) 80057da: 4293 cmp r3, r2 80057dc: d030 beq.n 8005840 80057de: 687b ldr r3, [r7, #4] 80057e0: 681b ldr r3, [r3, #0] 80057e2: 4a2f ldr r2, [pc, #188] ; (80058a0 ) 80057e4: 4293 cmp r3, r2 80057e6: d028 beq.n 800583a 80057e8: 687b ldr r3, [r7, #4] 80057ea: 681b ldr r3, [r3, #0] 80057ec: 4a26 ldr r2, [pc, #152] ; (8005888 ) 80057ee: 4293 cmp r3, r2 80057f0: d020 beq.n 8005834 80057f2: 687b ldr r3, [r7, #4] 80057f4: 681b ldr r3, [r3, #0] 80057f6: 4a2b ldr r2, [pc, #172] ; (80058a4 ) 80057f8: 4293 cmp r3, r2 80057fa: d019 beq.n 8005830 80057fc: 687b ldr r3, [r7, #4] 80057fe: 681b ldr r3, [r3, #0] 8005800: 4a29 ldr r2, [pc, #164] ; (80058a8 ) 8005802: 4293 cmp r3, r2 8005804: d012 beq.n 800582c 8005806: 687b ldr r3, [r7, #4] 8005808: 681b ldr r3, [r3, #0] 800580a: 4a28 ldr r2, [pc, #160] ; (80058ac ) 800580c: 4293 cmp r3, r2 800580e: d00a beq.n 8005826 8005810: 687b ldr r3, [r7, #4] 8005812: 681b ldr r3, [r3, #0] 8005814: 4a26 ldr r2, [pc, #152] ; (80058b0 ) 8005816: 4293 cmp r3, r2 8005818: d102 bne.n 8005820 800581a: f44f 5380 mov.w r3, #4096 ; 0x1000 800581e: e01b b.n 8005858 8005820: f44f 3380 mov.w r3, #65536 ; 0x10000 8005824: e018 b.n 8005858 8005826: f44f 7380 mov.w r3, #256 ; 0x100 800582a: e015 b.n 8005858 800582c: 2310 movs r3, #16 800582e: e013 b.n 8005858 8005830: 2301 movs r3, #1 8005832: e011 b.n 8005858 8005834: f04f 7380 mov.w r3, #16777216 ; 0x1000000 8005838: e00e b.n 8005858 800583a: f44f 1380 mov.w r3, #1048576 ; 0x100000 800583e: e00b b.n 8005858 8005840: f44f 3380 mov.w r3, #65536 ; 0x10000 8005844: e008 b.n 8005858 8005846: f44f 5380 mov.w r3, #4096 ; 0x1000 800584a: e005 b.n 8005858 800584c: f44f 7380 mov.w r3, #256 ; 0x100 8005850: e002 b.n 8005858 8005852: 2310 movs r3, #16 8005854: e000 b.n 8005858 8005856: 2301 movs r3, #1 8005858: 4a17 ldr r2, [pc, #92] ; (80058b8 ) 800585a: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800585c: 687b ldr r3, [r7, #4] 800585e: 2201 movs r2, #1 8005860: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8005864: 687b ldr r3, [r7, #4] 8005866: 2200 movs r2, #0 8005868: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 800586c: 687b ldr r3, [r7, #4] 800586e: 6b5b ldr r3, [r3, #52] ; 0x34 8005870: 2b00 cmp r3, #0 8005872: d003 beq.n 800587c { hdma->XferAbortCallback(hdma); 8005874: 687b ldr r3, [r7, #4] 8005876: 6b5b ldr r3, [r3, #52] ; 0x34 8005878: 6878 ldr r0, [r7, #4] 800587a: 4798 blx r3 } } return status; 800587c: 7bfb ldrb r3, [r7, #15] } 800587e: 4618 mov r0, r3 8005880: 3710 adds r7, #16 8005882: 46bd mov sp, r7 8005884: bd80 pop {r7, pc} 8005886: bf00 nop 8005888: 40020080 .word 0x40020080 800588c: 40020008 .word 0x40020008 8005890: 4002001c .word 0x4002001c 8005894: 40020030 .word 0x40020030 8005898: 40020044 .word 0x40020044 800589c: 40020058 .word 0x40020058 80058a0: 4002006c .word 0x4002006c 80058a4: 40020408 .word 0x40020408 80058a8: 4002041c .word 0x4002041c 80058ac: 40020430 .word 0x40020430 80058b0: 40020444 .word 0x40020444 80058b4: 40020400 .word 0x40020400 80058b8: 40020000 .word 0x40020000 080058bc : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80058bc: b480 push {r7} 80058be: b08b sub sp, #44 ; 0x2c 80058c0: af00 add r7, sp, #0 80058c2: 6078 str r0, [r7, #4] 80058c4: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 80058c6: 2300 movs r3, #0 80058c8: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 80058ca: 2300 movs r3, #0 80058cc: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 80058ce: e169 b.n 8005ba4 { /* Get the IO position */ ioposition = (0x01uL << position); 80058d0: 2201 movs r2, #1 80058d2: 6a7b ldr r3, [r7, #36] ; 0x24 80058d4: fa02 f303 lsl.w r3, r2, r3 80058d8: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80058da: 683b ldr r3, [r7, #0] 80058dc: 681b ldr r3, [r3, #0] 80058de: 69fa ldr r2, [r7, #28] 80058e0: 4013 ands r3, r2 80058e2: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 80058e4: 69ba ldr r2, [r7, #24] 80058e6: 69fb ldr r3, [r7, #28] 80058e8: 429a cmp r2, r3 80058ea: f040 8158 bne.w 8005b9e { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 80058ee: 683b ldr r3, [r7, #0] 80058f0: 685b ldr r3, [r3, #4] 80058f2: 4a9a ldr r2, [pc, #616] ; (8005b5c ) 80058f4: 4293 cmp r3, r2 80058f6: d05e beq.n 80059b6 80058f8: 4a98 ldr r2, [pc, #608] ; (8005b5c ) 80058fa: 4293 cmp r3, r2 80058fc: d875 bhi.n 80059ea 80058fe: 4a98 ldr r2, [pc, #608] ; (8005b60 ) 8005900: 4293 cmp r3, r2 8005902: d058 beq.n 80059b6 8005904: 4a96 ldr r2, [pc, #600] ; (8005b60 ) 8005906: 4293 cmp r3, r2 8005908: d86f bhi.n 80059ea 800590a: 4a96 ldr r2, [pc, #600] ; (8005b64 ) 800590c: 4293 cmp r3, r2 800590e: d052 beq.n 80059b6 8005910: 4a94 ldr r2, [pc, #592] ; (8005b64 ) 8005912: 4293 cmp r3, r2 8005914: d869 bhi.n 80059ea 8005916: 4a94 ldr r2, [pc, #592] ; (8005b68 ) 8005918: 4293 cmp r3, r2 800591a: d04c beq.n 80059b6 800591c: 4a92 ldr r2, [pc, #584] ; (8005b68 ) 800591e: 4293 cmp r3, r2 8005920: d863 bhi.n 80059ea 8005922: 4a92 ldr r2, [pc, #584] ; (8005b6c ) 8005924: 4293 cmp r3, r2 8005926: d046 beq.n 80059b6 8005928: 4a90 ldr r2, [pc, #576] ; (8005b6c ) 800592a: 4293 cmp r3, r2 800592c: d85d bhi.n 80059ea 800592e: 2b12 cmp r3, #18 8005930: d82a bhi.n 8005988 8005932: 2b12 cmp r3, #18 8005934: d859 bhi.n 80059ea 8005936: a201 add r2, pc, #4 ; (adr r2, 800593c ) 8005938: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800593c: 080059b7 .word 0x080059b7 8005940: 08005991 .word 0x08005991 8005944: 080059a3 .word 0x080059a3 8005948: 080059e5 .word 0x080059e5 800594c: 080059eb .word 0x080059eb 8005950: 080059eb .word 0x080059eb 8005954: 080059eb .word 0x080059eb 8005958: 080059eb .word 0x080059eb 800595c: 080059eb .word 0x080059eb 8005960: 080059eb .word 0x080059eb 8005964: 080059eb .word 0x080059eb 8005968: 080059eb .word 0x080059eb 800596c: 080059eb .word 0x080059eb 8005970: 080059eb .word 0x080059eb 8005974: 080059eb .word 0x080059eb 8005978: 080059eb .word 0x080059eb 800597c: 080059eb .word 0x080059eb 8005980: 08005999 .word 0x08005999 8005984: 080059ad .word 0x080059ad 8005988: 4a79 ldr r2, [pc, #484] ; (8005b70 ) 800598a: 4293 cmp r3, r2 800598c: d013 beq.n 80059b6 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 800598e: e02c b.n 80059ea config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8005990: 683b ldr r3, [r7, #0] 8005992: 68db ldr r3, [r3, #12] 8005994: 623b str r3, [r7, #32] break; 8005996: e029 b.n 80059ec config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8005998: 683b ldr r3, [r7, #0] 800599a: 68db ldr r3, [r3, #12] 800599c: 3304 adds r3, #4 800599e: 623b str r3, [r7, #32] break; 80059a0: e024 b.n 80059ec config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 80059a2: 683b ldr r3, [r7, #0] 80059a4: 68db ldr r3, [r3, #12] 80059a6: 3308 adds r3, #8 80059a8: 623b str r3, [r7, #32] break; 80059aa: e01f b.n 80059ec config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 80059ac: 683b ldr r3, [r7, #0] 80059ae: 68db ldr r3, [r3, #12] 80059b0: 330c adds r3, #12 80059b2: 623b str r3, [r7, #32] break; 80059b4: e01a b.n 80059ec if (GPIO_Init->Pull == GPIO_NOPULL) 80059b6: 683b ldr r3, [r7, #0] 80059b8: 689b ldr r3, [r3, #8] 80059ba: 2b00 cmp r3, #0 80059bc: d102 bne.n 80059c4 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 80059be: 2304 movs r3, #4 80059c0: 623b str r3, [r7, #32] break; 80059c2: e013 b.n 80059ec else if (GPIO_Init->Pull == GPIO_PULLUP) 80059c4: 683b ldr r3, [r7, #0] 80059c6: 689b ldr r3, [r3, #8] 80059c8: 2b01 cmp r3, #1 80059ca: d105 bne.n 80059d8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80059cc: 2308 movs r3, #8 80059ce: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 80059d0: 687b ldr r3, [r7, #4] 80059d2: 69fa ldr r2, [r7, #28] 80059d4: 611a str r2, [r3, #16] break; 80059d6: e009 b.n 80059ec config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80059d8: 2308 movs r3, #8 80059da: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 80059dc: 687b ldr r3, [r7, #4] 80059de: 69fa ldr r2, [r7, #28] 80059e0: 615a str r2, [r3, #20] break; 80059e2: e003 b.n 80059ec config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 80059e4: 2300 movs r3, #0 80059e6: 623b str r3, [r7, #32] break; 80059e8: e000 b.n 80059ec break; 80059ea: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 80059ec: 69bb ldr r3, [r7, #24] 80059ee: 2bff cmp r3, #255 ; 0xff 80059f0: d801 bhi.n 80059f6 80059f2: 687b ldr r3, [r7, #4] 80059f4: e001 b.n 80059fa 80059f6: 687b ldr r3, [r7, #4] 80059f8: 3304 adds r3, #4 80059fa: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 80059fc: 69bb ldr r3, [r7, #24] 80059fe: 2bff cmp r3, #255 ; 0xff 8005a00: d802 bhi.n 8005a08 8005a02: 6a7b ldr r3, [r7, #36] ; 0x24 8005a04: 009b lsls r3, r3, #2 8005a06: e002 b.n 8005a0e 8005a08: 6a7b ldr r3, [r7, #36] ; 0x24 8005a0a: 3b08 subs r3, #8 8005a0c: 009b lsls r3, r3, #2 8005a0e: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8005a10: 697b ldr r3, [r7, #20] 8005a12: 681a ldr r2, [r3, #0] 8005a14: 210f movs r1, #15 8005a16: 693b ldr r3, [r7, #16] 8005a18: fa01 f303 lsl.w r3, r1, r3 8005a1c: 43db mvns r3, r3 8005a1e: 401a ands r2, r3 8005a20: 6a39 ldr r1, [r7, #32] 8005a22: 693b ldr r3, [r7, #16] 8005a24: fa01 f303 lsl.w r3, r1, r3 8005a28: 431a orrs r2, r3 8005a2a: 697b ldr r3, [r7, #20] 8005a2c: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8005a2e: 683b ldr r3, [r7, #0] 8005a30: 685b ldr r3, [r3, #4] 8005a32: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8005a36: 2b00 cmp r3, #0 8005a38: f000 80b1 beq.w 8005b9e { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8005a3c: 4b4d ldr r3, [pc, #308] ; (8005b74 ) 8005a3e: 699b ldr r3, [r3, #24] 8005a40: 4a4c ldr r2, [pc, #304] ; (8005b74 ) 8005a42: f043 0301 orr.w r3, r3, #1 8005a46: 6193 str r3, [r2, #24] 8005a48: 4b4a ldr r3, [pc, #296] ; (8005b74 ) 8005a4a: 699b ldr r3, [r3, #24] 8005a4c: f003 0301 and.w r3, r3, #1 8005a50: 60bb str r3, [r7, #8] 8005a52: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8005a54: 4a48 ldr r2, [pc, #288] ; (8005b78 ) 8005a56: 6a7b ldr r3, [r7, #36] ; 0x24 8005a58: 089b lsrs r3, r3, #2 8005a5a: 3302 adds r3, #2 8005a5c: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8005a60: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8005a62: 6a7b ldr r3, [r7, #36] ; 0x24 8005a64: f003 0303 and.w r3, r3, #3 8005a68: 009b lsls r3, r3, #2 8005a6a: 220f movs r2, #15 8005a6c: fa02 f303 lsl.w r3, r2, r3 8005a70: 43db mvns r3, r3 8005a72: 68fa ldr r2, [r7, #12] 8005a74: 4013 ands r3, r2 8005a76: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8005a78: 687b ldr r3, [r7, #4] 8005a7a: 4a40 ldr r2, [pc, #256] ; (8005b7c ) 8005a7c: 4293 cmp r3, r2 8005a7e: d013 beq.n 8005aa8 8005a80: 687b ldr r3, [r7, #4] 8005a82: 4a3f ldr r2, [pc, #252] ; (8005b80 ) 8005a84: 4293 cmp r3, r2 8005a86: d00d beq.n 8005aa4 8005a88: 687b ldr r3, [r7, #4] 8005a8a: 4a3e ldr r2, [pc, #248] ; (8005b84 ) 8005a8c: 4293 cmp r3, r2 8005a8e: d007 beq.n 8005aa0 8005a90: 687b ldr r3, [r7, #4] 8005a92: 4a3d ldr r2, [pc, #244] ; (8005b88 ) 8005a94: 4293 cmp r3, r2 8005a96: d101 bne.n 8005a9c 8005a98: 2303 movs r3, #3 8005a9a: e006 b.n 8005aaa 8005a9c: 2304 movs r3, #4 8005a9e: e004 b.n 8005aaa 8005aa0: 2302 movs r3, #2 8005aa2: e002 b.n 8005aaa 8005aa4: 2301 movs r3, #1 8005aa6: e000 b.n 8005aaa 8005aa8: 2300 movs r3, #0 8005aaa: 6a7a ldr r2, [r7, #36] ; 0x24 8005aac: f002 0203 and.w r2, r2, #3 8005ab0: 0092 lsls r2, r2, #2 8005ab2: 4093 lsls r3, r2 8005ab4: 68fa ldr r2, [r7, #12] 8005ab6: 4313 orrs r3, r2 8005ab8: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 8005aba: 492f ldr r1, [pc, #188] ; (8005b78 ) 8005abc: 6a7b ldr r3, [r7, #36] ; 0x24 8005abe: 089b lsrs r3, r3, #2 8005ac0: 3302 adds r3, #2 8005ac2: 68fa ldr r2, [r7, #12] 8005ac4: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8005ac8: 683b ldr r3, [r7, #0] 8005aca: 685b ldr r3, [r3, #4] 8005acc: f403 3380 and.w r3, r3, #65536 ; 0x10000 8005ad0: 2b00 cmp r3, #0 8005ad2: d006 beq.n 8005ae2 { SET_BIT(EXTI->IMR, iocurrent); 8005ad4: 4b2d ldr r3, [pc, #180] ; (8005b8c ) 8005ad6: 681a ldr r2, [r3, #0] 8005ad8: 492c ldr r1, [pc, #176] ; (8005b8c ) 8005ada: 69bb ldr r3, [r7, #24] 8005adc: 4313 orrs r3, r2 8005ade: 600b str r3, [r1, #0] 8005ae0: e006 b.n 8005af0 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8005ae2: 4b2a ldr r3, [pc, #168] ; (8005b8c ) 8005ae4: 681a ldr r2, [r3, #0] 8005ae6: 69bb ldr r3, [r7, #24] 8005ae8: 43db mvns r3, r3 8005aea: 4928 ldr r1, [pc, #160] ; (8005b8c ) 8005aec: 4013 ands r3, r2 8005aee: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8005af0: 683b ldr r3, [r7, #0] 8005af2: 685b ldr r3, [r3, #4] 8005af4: f403 3300 and.w r3, r3, #131072 ; 0x20000 8005af8: 2b00 cmp r3, #0 8005afa: d006 beq.n 8005b0a { SET_BIT(EXTI->EMR, iocurrent); 8005afc: 4b23 ldr r3, [pc, #140] ; (8005b8c ) 8005afe: 685a ldr r2, [r3, #4] 8005b00: 4922 ldr r1, [pc, #136] ; (8005b8c ) 8005b02: 69bb ldr r3, [r7, #24] 8005b04: 4313 orrs r3, r2 8005b06: 604b str r3, [r1, #4] 8005b08: e006 b.n 8005b18 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 8005b0a: 4b20 ldr r3, [pc, #128] ; (8005b8c ) 8005b0c: 685a ldr r2, [r3, #4] 8005b0e: 69bb ldr r3, [r7, #24] 8005b10: 43db mvns r3, r3 8005b12: 491e ldr r1, [pc, #120] ; (8005b8c ) 8005b14: 4013 ands r3, r2 8005b16: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8005b18: 683b ldr r3, [r7, #0] 8005b1a: 685b ldr r3, [r3, #4] 8005b1c: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8005b20: 2b00 cmp r3, #0 8005b22: d006 beq.n 8005b32 { SET_BIT(EXTI->RTSR, iocurrent); 8005b24: 4b19 ldr r3, [pc, #100] ; (8005b8c ) 8005b26: 689a ldr r2, [r3, #8] 8005b28: 4918 ldr r1, [pc, #96] ; (8005b8c ) 8005b2a: 69bb ldr r3, [r7, #24] 8005b2c: 4313 orrs r3, r2 8005b2e: 608b str r3, [r1, #8] 8005b30: e006 b.n 8005b40 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8005b32: 4b16 ldr r3, [pc, #88] ; (8005b8c ) 8005b34: 689a ldr r2, [r3, #8] 8005b36: 69bb ldr r3, [r7, #24] 8005b38: 43db mvns r3, r3 8005b3a: 4914 ldr r1, [pc, #80] ; (8005b8c ) 8005b3c: 4013 ands r3, r2 8005b3e: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8005b40: 683b ldr r3, [r7, #0] 8005b42: 685b ldr r3, [r3, #4] 8005b44: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8005b48: 2b00 cmp r3, #0 8005b4a: d021 beq.n 8005b90 { SET_BIT(EXTI->FTSR, iocurrent); 8005b4c: 4b0f ldr r3, [pc, #60] ; (8005b8c ) 8005b4e: 68da ldr r2, [r3, #12] 8005b50: 490e ldr r1, [pc, #56] ; (8005b8c ) 8005b52: 69bb ldr r3, [r7, #24] 8005b54: 4313 orrs r3, r2 8005b56: 60cb str r3, [r1, #12] 8005b58: e021 b.n 8005b9e 8005b5a: bf00 nop 8005b5c: 10320000 .word 0x10320000 8005b60: 10310000 .word 0x10310000 8005b64: 10220000 .word 0x10220000 8005b68: 10210000 .word 0x10210000 8005b6c: 10120000 .word 0x10120000 8005b70: 10110000 .word 0x10110000 8005b74: 40021000 .word 0x40021000 8005b78: 40010000 .word 0x40010000 8005b7c: 40010800 .word 0x40010800 8005b80: 40010c00 .word 0x40010c00 8005b84: 40011000 .word 0x40011000 8005b88: 40011400 .word 0x40011400 8005b8c: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8005b90: 4b0b ldr r3, [pc, #44] ; (8005bc0 ) 8005b92: 68da ldr r2, [r3, #12] 8005b94: 69bb ldr r3, [r7, #24] 8005b96: 43db mvns r3, r3 8005b98: 4909 ldr r1, [pc, #36] ; (8005bc0 ) 8005b9a: 4013 ands r3, r2 8005b9c: 60cb str r3, [r1, #12] } } } position++; 8005b9e: 6a7b ldr r3, [r7, #36] ; 0x24 8005ba0: 3301 adds r3, #1 8005ba2: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8005ba4: 683b ldr r3, [r7, #0] 8005ba6: 681a ldr r2, [r3, #0] 8005ba8: 6a7b ldr r3, [r7, #36] ; 0x24 8005baa: fa22 f303 lsr.w r3, r2, r3 8005bae: 2b00 cmp r3, #0 8005bb0: f47f ae8e bne.w 80058d0 } } 8005bb4: bf00 nop 8005bb6: bf00 nop 8005bb8: 372c adds r7, #44 ; 0x2c 8005bba: 46bd mov sp, r7 8005bbc: bc80 pop {r7} 8005bbe: 4770 bx lr 8005bc0: 40010400 .word 0x40010400 08005bc4 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8005bc4: b480 push {r7} 8005bc6: b085 sub sp, #20 8005bc8: af00 add r7, sp, #0 8005bca: 6078 str r0, [r7, #4] 8005bcc: 460b mov r3, r1 8005bce: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8005bd0: 687b ldr r3, [r7, #4] 8005bd2: 689a ldr r2, [r3, #8] 8005bd4: 887b ldrh r3, [r7, #2] 8005bd6: 4013 ands r3, r2 8005bd8: 2b00 cmp r3, #0 8005bda: d002 beq.n 8005be2 { bitstatus = GPIO_PIN_SET; 8005bdc: 2301 movs r3, #1 8005bde: 73fb strb r3, [r7, #15] 8005be0: e001 b.n 8005be6 } else { bitstatus = GPIO_PIN_RESET; 8005be2: 2300 movs r3, #0 8005be4: 73fb strb r3, [r7, #15] } return bitstatus; 8005be6: 7bfb ldrb r3, [r7, #15] } 8005be8: 4618 mov r0, r3 8005bea: 3714 adds r7, #20 8005bec: 46bd mov sp, r7 8005bee: bc80 pop {r7} 8005bf0: 4770 bx lr 08005bf2 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8005bf2: b480 push {r7} 8005bf4: b083 sub sp, #12 8005bf6: af00 add r7, sp, #0 8005bf8: 6078 str r0, [r7, #4] 8005bfa: 460b mov r3, r1 8005bfc: 807b strh r3, [r7, #2] 8005bfe: 4613 mov r3, r2 8005c00: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8005c02: 787b ldrb r3, [r7, #1] 8005c04: 2b00 cmp r3, #0 8005c06: d003 beq.n 8005c10 { GPIOx->BSRR = GPIO_Pin; 8005c08: 887a ldrh r2, [r7, #2] 8005c0a: 687b ldr r3, [r7, #4] 8005c0c: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 8005c0e: e003 b.n 8005c18 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 8005c10: 887b ldrh r3, [r7, #2] 8005c12: 041a lsls r2, r3, #16 8005c14: 687b ldr r3, [r7, #4] 8005c16: 611a str r2, [r3, #16] } 8005c18: bf00 nop 8005c1a: 370c adds r7, #12 8005c1c: 46bd mov sp, r7 8005c1e: bc80 pop {r7} 8005c20: 4770 bx lr ... 08005c24 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8005c24: b580 push {r7, lr} 8005c26: b086 sub sp, #24 8005c28: af00 add r7, sp, #0 8005c2a: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8005c2c: 687b ldr r3, [r7, #4] 8005c2e: 2b00 cmp r3, #0 8005c30: d101 bne.n 8005c36 { return HAL_ERROR; 8005c32: 2301 movs r3, #1 8005c34: e304 b.n 8006240 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8005c36: 687b ldr r3, [r7, #4] 8005c38: 681b ldr r3, [r3, #0] 8005c3a: f003 0301 and.w r3, r3, #1 8005c3e: 2b00 cmp r3, #0 8005c40: f000 8087 beq.w 8005d52 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8005c44: 4b92 ldr r3, [pc, #584] ; (8005e90 ) 8005c46: 685b ldr r3, [r3, #4] 8005c48: f003 030c and.w r3, r3, #12 8005c4c: 2b04 cmp r3, #4 8005c4e: d00c beq.n 8005c6a || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8005c50: 4b8f ldr r3, [pc, #572] ; (8005e90 ) 8005c52: 685b ldr r3, [r3, #4] 8005c54: f003 030c and.w r3, r3, #12 8005c58: 2b08 cmp r3, #8 8005c5a: d112 bne.n 8005c82 8005c5c: 4b8c ldr r3, [pc, #560] ; (8005e90 ) 8005c5e: 685b ldr r3, [r3, #4] 8005c60: f403 3380 and.w r3, r3, #65536 ; 0x10000 8005c64: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8005c68: d10b bne.n 8005c82 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8005c6a: 4b89 ldr r3, [pc, #548] ; (8005e90 ) 8005c6c: 681b ldr r3, [r3, #0] 8005c6e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8005c72: 2b00 cmp r3, #0 8005c74: d06c beq.n 8005d50 8005c76: 687b ldr r3, [r7, #4] 8005c78: 689b ldr r3, [r3, #8] 8005c7a: 2b00 cmp r3, #0 8005c7c: d168 bne.n 8005d50 { return HAL_ERROR; 8005c7e: 2301 movs r3, #1 8005c80: e2de b.n 8006240 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8005c82: 687b ldr r3, [r7, #4] 8005c84: 689b ldr r3, [r3, #8] 8005c86: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8005c8a: d106 bne.n 8005c9a 8005c8c: 4b80 ldr r3, [pc, #512] ; (8005e90 ) 8005c8e: 681b ldr r3, [r3, #0] 8005c90: 4a7f ldr r2, [pc, #508] ; (8005e90 ) 8005c92: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8005c96: 6013 str r3, [r2, #0] 8005c98: e02e b.n 8005cf8 8005c9a: 687b ldr r3, [r7, #4] 8005c9c: 689b ldr r3, [r3, #8] 8005c9e: 2b00 cmp r3, #0 8005ca0: d10c bne.n 8005cbc 8005ca2: 4b7b ldr r3, [pc, #492] ; (8005e90 ) 8005ca4: 681b ldr r3, [r3, #0] 8005ca6: 4a7a ldr r2, [pc, #488] ; (8005e90 ) 8005ca8: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8005cac: 6013 str r3, [r2, #0] 8005cae: 4b78 ldr r3, [pc, #480] ; (8005e90 ) 8005cb0: 681b ldr r3, [r3, #0] 8005cb2: 4a77 ldr r2, [pc, #476] ; (8005e90 ) 8005cb4: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8005cb8: 6013 str r3, [r2, #0] 8005cba: e01d b.n 8005cf8 8005cbc: 687b ldr r3, [r7, #4] 8005cbe: 689b ldr r3, [r3, #8] 8005cc0: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8005cc4: d10c bne.n 8005ce0 8005cc6: 4b72 ldr r3, [pc, #456] ; (8005e90 ) 8005cc8: 681b ldr r3, [r3, #0] 8005cca: 4a71 ldr r2, [pc, #452] ; (8005e90 ) 8005ccc: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8005cd0: 6013 str r3, [r2, #0] 8005cd2: 4b6f ldr r3, [pc, #444] ; (8005e90 ) 8005cd4: 681b ldr r3, [r3, #0] 8005cd6: 4a6e ldr r2, [pc, #440] ; (8005e90 ) 8005cd8: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8005cdc: 6013 str r3, [r2, #0] 8005cde: e00b b.n 8005cf8 8005ce0: 4b6b ldr r3, [pc, #428] ; (8005e90 ) 8005ce2: 681b ldr r3, [r3, #0] 8005ce4: 4a6a ldr r2, [pc, #424] ; (8005e90 ) 8005ce6: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8005cea: 6013 str r3, [r2, #0] 8005cec: 4b68 ldr r3, [pc, #416] ; (8005e90 ) 8005cee: 681b ldr r3, [r3, #0] 8005cf0: 4a67 ldr r2, [pc, #412] ; (8005e90 ) 8005cf2: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8005cf6: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8005cf8: 687b ldr r3, [r7, #4] 8005cfa: 689b ldr r3, [r3, #8] 8005cfc: 2b00 cmp r3, #0 8005cfe: d013 beq.n 8005d28 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8005d00: f7fd ffae bl 8003c60 8005d04: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8005d06: e008 b.n 8005d1a { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8005d08: f7fd ffaa bl 8003c60 8005d0c: 4602 mov r2, r0 8005d0e: 693b ldr r3, [r7, #16] 8005d10: 1ad3 subs r3, r2, r3 8005d12: 2b64 cmp r3, #100 ; 0x64 8005d14: d901 bls.n 8005d1a { return HAL_TIMEOUT; 8005d16: 2303 movs r3, #3 8005d18: e292 b.n 8006240 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8005d1a: 4b5d ldr r3, [pc, #372] ; (8005e90 ) 8005d1c: 681b ldr r3, [r3, #0] 8005d1e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8005d22: 2b00 cmp r3, #0 8005d24: d0f0 beq.n 8005d08 8005d26: e014 b.n 8005d52 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8005d28: f7fd ff9a bl 8003c60 8005d2c: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8005d2e: e008 b.n 8005d42 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8005d30: f7fd ff96 bl 8003c60 8005d34: 4602 mov r2, r0 8005d36: 693b ldr r3, [r7, #16] 8005d38: 1ad3 subs r3, r2, r3 8005d3a: 2b64 cmp r3, #100 ; 0x64 8005d3c: d901 bls.n 8005d42 { return HAL_TIMEOUT; 8005d3e: 2303 movs r3, #3 8005d40: e27e b.n 8006240 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8005d42: 4b53 ldr r3, [pc, #332] ; (8005e90 ) 8005d44: 681b ldr r3, [r3, #0] 8005d46: f403 3300 and.w r3, r3, #131072 ; 0x20000 8005d4a: 2b00 cmp r3, #0 8005d4c: d1f0 bne.n 8005d30 8005d4e: e000 b.n 8005d52 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8005d50: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8005d52: 687b ldr r3, [r7, #4] 8005d54: 681b ldr r3, [r3, #0] 8005d56: f003 0302 and.w r3, r3, #2 8005d5a: 2b00 cmp r3, #0 8005d5c: d063 beq.n 8005e26 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8005d5e: 4b4c ldr r3, [pc, #304] ; (8005e90 ) 8005d60: 685b ldr r3, [r3, #4] 8005d62: f003 030c and.w r3, r3, #12 8005d66: 2b00 cmp r3, #0 8005d68: d00b beq.n 8005d82 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 8005d6a: 4b49 ldr r3, [pc, #292] ; (8005e90 ) 8005d6c: 685b ldr r3, [r3, #4] 8005d6e: f003 030c and.w r3, r3, #12 8005d72: 2b08 cmp r3, #8 8005d74: d11c bne.n 8005db0 8005d76: 4b46 ldr r3, [pc, #280] ; (8005e90 ) 8005d78: 685b ldr r3, [r3, #4] 8005d7a: f403 3380 and.w r3, r3, #65536 ; 0x10000 8005d7e: 2b00 cmp r3, #0 8005d80: d116 bne.n 8005db0 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8005d82: 4b43 ldr r3, [pc, #268] ; (8005e90 ) 8005d84: 681b ldr r3, [r3, #0] 8005d86: f003 0302 and.w r3, r3, #2 8005d8a: 2b00 cmp r3, #0 8005d8c: d005 beq.n 8005d9a 8005d8e: 687b ldr r3, [r7, #4] 8005d90: 695b ldr r3, [r3, #20] 8005d92: 2b01 cmp r3, #1 8005d94: d001 beq.n 8005d9a { return HAL_ERROR; 8005d96: 2301 movs r3, #1 8005d98: e252 b.n 8006240 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8005d9a: 4b3d ldr r3, [pc, #244] ; (8005e90 ) 8005d9c: 681b ldr r3, [r3, #0] 8005d9e: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8005da2: 687b ldr r3, [r7, #4] 8005da4: 699b ldr r3, [r3, #24] 8005da6: 00db lsls r3, r3, #3 8005da8: 4939 ldr r1, [pc, #228] ; (8005e90 ) 8005daa: 4313 orrs r3, r2 8005dac: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8005dae: e03a b.n 8005e26 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8005db0: 687b ldr r3, [r7, #4] 8005db2: 695b ldr r3, [r3, #20] 8005db4: 2b00 cmp r3, #0 8005db6: d020 beq.n 8005dfa { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8005db8: 4b36 ldr r3, [pc, #216] ; (8005e94 ) 8005dba: 2201 movs r2, #1 8005dbc: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8005dbe: f7fd ff4f bl 8003c60 8005dc2: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8005dc4: e008 b.n 8005dd8 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8005dc6: f7fd ff4b bl 8003c60 8005dca: 4602 mov r2, r0 8005dcc: 693b ldr r3, [r7, #16] 8005dce: 1ad3 subs r3, r2, r3 8005dd0: 2b02 cmp r3, #2 8005dd2: d901 bls.n 8005dd8 { return HAL_TIMEOUT; 8005dd4: 2303 movs r3, #3 8005dd6: e233 b.n 8006240 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8005dd8: 4b2d ldr r3, [pc, #180] ; (8005e90 ) 8005dda: 681b ldr r3, [r3, #0] 8005ddc: f003 0302 and.w r3, r3, #2 8005de0: 2b00 cmp r3, #0 8005de2: d0f0 beq.n 8005dc6 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8005de4: 4b2a ldr r3, [pc, #168] ; (8005e90 ) 8005de6: 681b ldr r3, [r3, #0] 8005de8: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8005dec: 687b ldr r3, [r7, #4] 8005dee: 699b ldr r3, [r3, #24] 8005df0: 00db lsls r3, r3, #3 8005df2: 4927 ldr r1, [pc, #156] ; (8005e90 ) 8005df4: 4313 orrs r3, r2 8005df6: 600b str r3, [r1, #0] 8005df8: e015 b.n 8005e26 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8005dfa: 4b26 ldr r3, [pc, #152] ; (8005e94 ) 8005dfc: 2200 movs r2, #0 8005dfe: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8005e00: f7fd ff2e bl 8003c60 8005e04: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8005e06: e008 b.n 8005e1a { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8005e08: f7fd ff2a bl 8003c60 8005e0c: 4602 mov r2, r0 8005e0e: 693b ldr r3, [r7, #16] 8005e10: 1ad3 subs r3, r2, r3 8005e12: 2b02 cmp r3, #2 8005e14: d901 bls.n 8005e1a { return HAL_TIMEOUT; 8005e16: 2303 movs r3, #3 8005e18: e212 b.n 8006240 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8005e1a: 4b1d ldr r3, [pc, #116] ; (8005e90 ) 8005e1c: 681b ldr r3, [r3, #0] 8005e1e: f003 0302 and.w r3, r3, #2 8005e22: 2b00 cmp r3, #0 8005e24: d1f0 bne.n 8005e08 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8005e26: 687b ldr r3, [r7, #4] 8005e28: 681b ldr r3, [r3, #0] 8005e2a: f003 0308 and.w r3, r3, #8 8005e2e: 2b00 cmp r3, #0 8005e30: d03a beq.n 8005ea8 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8005e32: 687b ldr r3, [r7, #4] 8005e34: 69db ldr r3, [r3, #28] 8005e36: 2b00 cmp r3, #0 8005e38: d019 beq.n 8005e6e { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8005e3a: 4b17 ldr r3, [pc, #92] ; (8005e98 ) 8005e3c: 2201 movs r2, #1 8005e3e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8005e40: f7fd ff0e bl 8003c60 8005e44: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8005e46: e008 b.n 8005e5a { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8005e48: f7fd ff0a bl 8003c60 8005e4c: 4602 mov r2, r0 8005e4e: 693b ldr r3, [r7, #16] 8005e50: 1ad3 subs r3, r2, r3 8005e52: 2b02 cmp r3, #2 8005e54: d901 bls.n 8005e5a { return HAL_TIMEOUT; 8005e56: 2303 movs r3, #3 8005e58: e1f2 b.n 8006240 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8005e5a: 4b0d ldr r3, [pc, #52] ; (8005e90 ) 8005e5c: 6a5b ldr r3, [r3, #36] ; 0x24 8005e5e: f003 0302 and.w r3, r3, #2 8005e62: 2b00 cmp r3, #0 8005e64: d0f0 beq.n 8005e48 } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 8005e66: 2001 movs r0, #1 8005e68: f000 fbec bl 8006644 8005e6c: e01c b.n 8005ea8 } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8005e6e: 4b0a ldr r3, [pc, #40] ; (8005e98 ) 8005e70: 2200 movs r2, #0 8005e72: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8005e74: f7fd fef4 bl 8003c60 8005e78: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8005e7a: e00f b.n 8005e9c { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8005e7c: f7fd fef0 bl 8003c60 8005e80: 4602 mov r2, r0 8005e82: 693b ldr r3, [r7, #16] 8005e84: 1ad3 subs r3, r2, r3 8005e86: 2b02 cmp r3, #2 8005e88: d908 bls.n 8005e9c { return HAL_TIMEOUT; 8005e8a: 2303 movs r3, #3 8005e8c: e1d8 b.n 8006240 8005e8e: bf00 nop 8005e90: 40021000 .word 0x40021000 8005e94: 42420000 .word 0x42420000 8005e98: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8005e9c: 4b9b ldr r3, [pc, #620] ; (800610c ) 8005e9e: 6a5b ldr r3, [r3, #36] ; 0x24 8005ea0: f003 0302 and.w r3, r3, #2 8005ea4: 2b00 cmp r3, #0 8005ea6: d1e9 bne.n 8005e7c } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8005ea8: 687b ldr r3, [r7, #4] 8005eaa: 681b ldr r3, [r3, #0] 8005eac: f003 0304 and.w r3, r3, #4 8005eb0: 2b00 cmp r3, #0 8005eb2: f000 80a6 beq.w 8006002 { FlagStatus pwrclkchanged = RESET; 8005eb6: 2300 movs r3, #0 8005eb8: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8005eba: 4b94 ldr r3, [pc, #592] ; (800610c ) 8005ebc: 69db ldr r3, [r3, #28] 8005ebe: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8005ec2: 2b00 cmp r3, #0 8005ec4: d10d bne.n 8005ee2 { __HAL_RCC_PWR_CLK_ENABLE(); 8005ec6: 4b91 ldr r3, [pc, #580] ; (800610c ) 8005ec8: 69db ldr r3, [r3, #28] 8005eca: 4a90 ldr r2, [pc, #576] ; (800610c ) 8005ecc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8005ed0: 61d3 str r3, [r2, #28] 8005ed2: 4b8e ldr r3, [pc, #568] ; (800610c ) 8005ed4: 69db ldr r3, [r3, #28] 8005ed6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8005eda: 60bb str r3, [r7, #8] 8005edc: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8005ede: 2301 movs r3, #1 8005ee0: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8005ee2: 4b8b ldr r3, [pc, #556] ; (8006110 ) 8005ee4: 681b ldr r3, [r3, #0] 8005ee6: f403 7380 and.w r3, r3, #256 ; 0x100 8005eea: 2b00 cmp r3, #0 8005eec: d118 bne.n 8005f20 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8005eee: 4b88 ldr r3, [pc, #544] ; (8006110 ) 8005ef0: 681b ldr r3, [r3, #0] 8005ef2: 4a87 ldr r2, [pc, #540] ; (8006110 ) 8005ef4: f443 7380 orr.w r3, r3, #256 ; 0x100 8005ef8: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8005efa: f7fd feb1 bl 8003c60 8005efe: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8005f00: e008 b.n 8005f14 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8005f02: f7fd fead bl 8003c60 8005f06: 4602 mov r2, r0 8005f08: 693b ldr r3, [r7, #16] 8005f0a: 1ad3 subs r3, r2, r3 8005f0c: 2b64 cmp r3, #100 ; 0x64 8005f0e: d901 bls.n 8005f14 { return HAL_TIMEOUT; 8005f10: 2303 movs r3, #3 8005f12: e195 b.n 8006240 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8005f14: 4b7e ldr r3, [pc, #504] ; (8006110 ) 8005f16: 681b ldr r3, [r3, #0] 8005f18: f403 7380 and.w r3, r3, #256 ; 0x100 8005f1c: 2b00 cmp r3, #0 8005f1e: d0f0 beq.n 8005f02 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8005f20: 687b ldr r3, [r7, #4] 8005f22: 691b ldr r3, [r3, #16] 8005f24: 2b01 cmp r3, #1 8005f26: d106 bne.n 8005f36 8005f28: 4b78 ldr r3, [pc, #480] ; (800610c ) 8005f2a: 6a1b ldr r3, [r3, #32] 8005f2c: 4a77 ldr r2, [pc, #476] ; (800610c ) 8005f2e: f043 0301 orr.w r3, r3, #1 8005f32: 6213 str r3, [r2, #32] 8005f34: e02d b.n 8005f92 8005f36: 687b ldr r3, [r7, #4] 8005f38: 691b ldr r3, [r3, #16] 8005f3a: 2b00 cmp r3, #0 8005f3c: d10c bne.n 8005f58 8005f3e: 4b73 ldr r3, [pc, #460] ; (800610c ) 8005f40: 6a1b ldr r3, [r3, #32] 8005f42: 4a72 ldr r2, [pc, #456] ; (800610c ) 8005f44: f023 0301 bic.w r3, r3, #1 8005f48: 6213 str r3, [r2, #32] 8005f4a: 4b70 ldr r3, [pc, #448] ; (800610c ) 8005f4c: 6a1b ldr r3, [r3, #32] 8005f4e: 4a6f ldr r2, [pc, #444] ; (800610c ) 8005f50: f023 0304 bic.w r3, r3, #4 8005f54: 6213 str r3, [r2, #32] 8005f56: e01c b.n 8005f92 8005f58: 687b ldr r3, [r7, #4] 8005f5a: 691b ldr r3, [r3, #16] 8005f5c: 2b05 cmp r3, #5 8005f5e: d10c bne.n 8005f7a 8005f60: 4b6a ldr r3, [pc, #424] ; (800610c ) 8005f62: 6a1b ldr r3, [r3, #32] 8005f64: 4a69 ldr r2, [pc, #420] ; (800610c ) 8005f66: f043 0304 orr.w r3, r3, #4 8005f6a: 6213 str r3, [r2, #32] 8005f6c: 4b67 ldr r3, [pc, #412] ; (800610c ) 8005f6e: 6a1b ldr r3, [r3, #32] 8005f70: 4a66 ldr r2, [pc, #408] ; (800610c ) 8005f72: f043 0301 orr.w r3, r3, #1 8005f76: 6213 str r3, [r2, #32] 8005f78: e00b b.n 8005f92 8005f7a: 4b64 ldr r3, [pc, #400] ; (800610c ) 8005f7c: 6a1b ldr r3, [r3, #32] 8005f7e: 4a63 ldr r2, [pc, #396] ; (800610c ) 8005f80: f023 0301 bic.w r3, r3, #1 8005f84: 6213 str r3, [r2, #32] 8005f86: 4b61 ldr r3, [pc, #388] ; (800610c ) 8005f88: 6a1b ldr r3, [r3, #32] 8005f8a: 4a60 ldr r2, [pc, #384] ; (800610c ) 8005f8c: f023 0304 bic.w r3, r3, #4 8005f90: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8005f92: 687b ldr r3, [r7, #4] 8005f94: 691b ldr r3, [r3, #16] 8005f96: 2b00 cmp r3, #0 8005f98: d015 beq.n 8005fc6 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8005f9a: f7fd fe61 bl 8003c60 8005f9e: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8005fa0: e00a b.n 8005fb8 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8005fa2: f7fd fe5d bl 8003c60 8005fa6: 4602 mov r2, r0 8005fa8: 693b ldr r3, [r7, #16] 8005faa: 1ad3 subs r3, r2, r3 8005fac: f241 3288 movw r2, #5000 ; 0x1388 8005fb0: 4293 cmp r3, r2 8005fb2: d901 bls.n 8005fb8 { return HAL_TIMEOUT; 8005fb4: 2303 movs r3, #3 8005fb6: e143 b.n 8006240 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8005fb8: 4b54 ldr r3, [pc, #336] ; (800610c ) 8005fba: 6a1b ldr r3, [r3, #32] 8005fbc: f003 0302 and.w r3, r3, #2 8005fc0: 2b00 cmp r3, #0 8005fc2: d0ee beq.n 8005fa2 8005fc4: e014 b.n 8005ff0 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8005fc6: f7fd fe4b bl 8003c60 8005fca: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8005fcc: e00a b.n 8005fe4 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8005fce: f7fd fe47 bl 8003c60 8005fd2: 4602 mov r2, r0 8005fd4: 693b ldr r3, [r7, #16] 8005fd6: 1ad3 subs r3, r2, r3 8005fd8: f241 3288 movw r2, #5000 ; 0x1388 8005fdc: 4293 cmp r3, r2 8005fde: d901 bls.n 8005fe4 { return HAL_TIMEOUT; 8005fe0: 2303 movs r3, #3 8005fe2: e12d b.n 8006240 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8005fe4: 4b49 ldr r3, [pc, #292] ; (800610c ) 8005fe6: 6a1b ldr r3, [r3, #32] 8005fe8: f003 0302 and.w r3, r3, #2 8005fec: 2b00 cmp r3, #0 8005fee: d1ee bne.n 8005fce } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8005ff0: 7dfb ldrb r3, [r7, #23] 8005ff2: 2b01 cmp r3, #1 8005ff4: d105 bne.n 8006002 { __HAL_RCC_PWR_CLK_DISABLE(); 8005ff6: 4b45 ldr r3, [pc, #276] ; (800610c ) 8005ff8: 69db ldr r3, [r3, #28] 8005ffa: 4a44 ldr r2, [pc, #272] ; (800610c ) 8005ffc: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8006000: 61d3 str r3, [r2, #28] #if defined(RCC_CR_PLL2ON) /*-------------------------------- PLL2 Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) 8006002: 687b ldr r3, [r7, #4] 8006004: 6adb ldr r3, [r3, #44] ; 0x2c 8006006: 2b00 cmp r3, #0 8006008: f000 808c beq.w 8006124 { /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 800600c: 4b3f ldr r3, [pc, #252] ; (800610c ) 800600e: 685b ldr r3, [r3, #4] 8006010: f403 3380 and.w r3, r3, #65536 ; 0x10000 8006014: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8006018: d10e bne.n 8006038 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 800601a: 4b3c ldr r3, [pc, #240] ; (800610c ) 800601c: 685b ldr r3, [r3, #4] 800601e: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ 8006022: 2b08 cmp r3, #8 8006024: d108 bne.n 8006038 ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) 8006026: 4b39 ldr r3, [pc, #228] ; (800610c ) 8006028: 6adb ldr r3, [r3, #44] ; 0x2c 800602a: f403 3380 and.w r3, r3, #65536 ; 0x10000 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ 800602e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8006032: d101 bne.n 8006038 { return HAL_ERROR; 8006034: 2301 movs r3, #1 8006036: e103 b.n 8006240 } else { if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) 8006038: 687b ldr r3, [r7, #4] 800603a: 6adb ldr r3, [r3, #44] ; 0x2c 800603c: 2b02 cmp r3, #2 800603e: d14e bne.n 80060de assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); /* Prediv2 can be written only when the PLLI2S is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 8006040: 4b32 ldr r3, [pc, #200] ; (800610c ) 8006042: 681b ldr r3, [r3, #0] 8006044: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8006048: 2b00 cmp r3, #0 800604a: d009 beq.n 8006060 (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) 800604c: 4b2f ldr r3, [pc, #188] ; (800610c ) 800604e: 6adb ldr r3, [r3, #44] ; 0x2c 8006050: f003 02f0 and.w r2, r3, #240 ; 0xf0 8006054: 687b ldr r3, [r7, #4] 8006056: 6b5b ldr r3, [r3, #52] ; 0x34 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ 8006058: 429a cmp r2, r3 800605a: d001 beq.n 8006060 { return HAL_ERROR; 800605c: 2301 movs r3, #1 800605e: e0ef b.n 8006240 } /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 8006060: 4b2c ldr r3, [pc, #176] ; (8006114 ) 8006062: 2200 movs r2, #0 8006064: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8006066: f7fd fdfb bl 8003c60 800606a: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 800606c: e008 b.n 8006080 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800606e: f7fd fdf7 bl 8003c60 8006072: 4602 mov r2, r0 8006074: 693b ldr r3, [r7, #16] 8006076: 1ad3 subs r3, r2, r3 8006078: 2b64 cmp r3, #100 ; 0x64 800607a: d901 bls.n 8006080 { return HAL_TIMEOUT; 800607c: 2303 movs r3, #3 800607e: e0df b.n 8006240 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8006080: 4b22 ldr r3, [pc, #136] ; (800610c ) 8006082: 681b ldr r3, [r3, #0] 8006084: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8006088: 2b00 cmp r3, #0 800608a: d1f0 bne.n 800606e } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); 800608c: 4b1f ldr r3, [pc, #124] ; (800610c ) 800608e: 6adb ldr r3, [r3, #44] ; 0x2c 8006090: f023 02f0 bic.w r2, r3, #240 ; 0xf0 8006094: 687b ldr r3, [r7, #4] 8006096: 6b5b ldr r3, [r3, #52] ; 0x34 8006098: 491c ldr r1, [pc, #112] ; (800610c ) 800609a: 4313 orrs r3, r2 800609c: 62cb str r3, [r1, #44] ; 0x2c /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); 800609e: 4b1b ldr r3, [pc, #108] ; (800610c ) 80060a0: 6adb ldr r3, [r3, #44] ; 0x2c 80060a2: f423 6270 bic.w r2, r3, #3840 ; 0xf00 80060a6: 687b ldr r3, [r7, #4] 80060a8: 6b1b ldr r3, [r3, #48] ; 0x30 80060aa: 4918 ldr r1, [pc, #96] ; (800610c ) 80060ac: 4313 orrs r3, r2 80060ae: 62cb str r3, [r1, #44] ; 0x2c /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); 80060b0: 4b18 ldr r3, [pc, #96] ; (8006114 ) 80060b2: 2201 movs r2, #1 80060b4: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80060b6: f7fd fdd3 bl 8003c60 80060ba: 6138 str r0, [r7, #16] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 80060bc: e008 b.n 80060d0 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 80060be: f7fd fdcf bl 8003c60 80060c2: 4602 mov r2, r0 80060c4: 693b ldr r3, [r7, #16] 80060c6: 1ad3 subs r3, r2, r3 80060c8: 2b64 cmp r3, #100 ; 0x64 80060ca: d901 bls.n 80060d0 { return HAL_TIMEOUT; 80060cc: 2303 movs r3, #3 80060ce: e0b7 b.n 8006240 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 80060d0: 4b0e ldr r3, [pc, #56] ; (800610c ) 80060d2: 681b ldr r3, [r3, #0] 80060d4: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 80060d8: 2b00 cmp r3, #0 80060da: d0f0 beq.n 80060be 80060dc: e022 b.n 8006124 } } else { /* Set PREDIV1 source to HSE */ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); 80060de: 4b0b ldr r3, [pc, #44] ; (800610c ) 80060e0: 6adb ldr r3, [r3, #44] ; 0x2c 80060e2: 4a0a ldr r2, [pc, #40] ; (800610c ) 80060e4: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80060e8: 62d3 str r3, [r2, #44] ; 0x2c /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); 80060ea: 4b0a ldr r3, [pc, #40] ; (8006114 ) 80060ec: 2200 movs r2, #0 80060ee: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80060f0: f7fd fdb6 bl 8003c60 80060f4: 6138 str r0, [r7, #16] /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 80060f6: e00f b.n 8006118 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 80060f8: f7fd fdb2 bl 8003c60 80060fc: 4602 mov r2, r0 80060fe: 693b ldr r3, [r7, #16] 8006100: 1ad3 subs r3, r2, r3 8006102: 2b64 cmp r3, #100 ; 0x64 8006104: d908 bls.n 8006118 { return HAL_TIMEOUT; 8006106: 2303 movs r3, #3 8006108: e09a b.n 8006240 800610a: bf00 nop 800610c: 40021000 .word 0x40021000 8006110: 40007000 .word 0x40007000 8006114: 42420068 .word 0x42420068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 8006118: 4b4b ldr r3, [pc, #300] ; (8006248 ) 800611a: 681b ldr r3, [r3, #0] 800611c: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8006120: 2b00 cmp r3, #0 8006122: d1e9 bne.n 80060f8 #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8006124: 687b ldr r3, [r7, #4] 8006126: 6a1b ldr r3, [r3, #32] 8006128: 2b00 cmp r3, #0 800612a: f000 8088 beq.w 800623e { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 800612e: 4b46 ldr r3, [pc, #280] ; (8006248 ) 8006130: 685b ldr r3, [r3, #4] 8006132: f003 030c and.w r3, r3, #12 8006136: 2b08 cmp r3, #8 8006138: d068 beq.n 800620c { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 800613a: 687b ldr r3, [r7, #4] 800613c: 6a1b ldr r3, [r3, #32] 800613e: 2b02 cmp r3, #2 8006140: d14d bne.n 80061de /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8006142: 4b42 ldr r3, [pc, #264] ; (800624c ) 8006144: 2200 movs r2, #0 8006146: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8006148: f7fd fd8a bl 8003c60 800614c: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800614e: e008 b.n 8006162 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8006150: f7fd fd86 bl 8003c60 8006154: 4602 mov r2, r0 8006156: 693b ldr r3, [r7, #16] 8006158: 1ad3 subs r3, r2, r3 800615a: 2b02 cmp r3, #2 800615c: d901 bls.n 8006162 { return HAL_TIMEOUT; 800615e: 2303 movs r3, #3 8006160: e06e b.n 8006240 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8006162: 4b39 ldr r3, [pc, #228] ; (8006248 ) 8006164: 681b ldr r3, [r3, #0] 8006166: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800616a: 2b00 cmp r3, #0 800616c: d1f0 bne.n 8006150 } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 800616e: 687b ldr r3, [r7, #4] 8006170: 6a5b ldr r3, [r3, #36] ; 0x24 8006172: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8006176: d10f bne.n 8006198 assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); #if defined(RCC_CFGR2_PREDIV1SRC) assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); 8006178: 4b33 ldr r3, [pc, #204] ; (8006248 ) 800617a: 6ada ldr r2, [r3, #44] ; 0x2c 800617c: 687b ldr r3, [r7, #4] 800617e: 685b ldr r3, [r3, #4] 8006180: 4931 ldr r1, [pc, #196] ; (8006248 ) 8006182: 4313 orrs r3, r2 8006184: 62cb str r3, [r1, #44] ; 0x2c #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 8006186: 4b30 ldr r3, [pc, #192] ; (8006248 ) 8006188: 6adb ldr r3, [r3, #44] ; 0x2c 800618a: f023 020f bic.w r2, r3, #15 800618e: 687b ldr r3, [r7, #4] 8006190: 68db ldr r3, [r3, #12] 8006192: 492d ldr r1, [pc, #180] ; (8006248 ) 8006194: 4313 orrs r3, r2 8006196: 62cb str r3, [r1, #44] ; 0x2c } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8006198: 4b2b ldr r3, [pc, #172] ; (8006248 ) 800619a: 685b ldr r3, [r3, #4] 800619c: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000 80061a0: 687b ldr r3, [r7, #4] 80061a2: 6a59 ldr r1, [r3, #36] ; 0x24 80061a4: 687b ldr r3, [r7, #4] 80061a6: 6a9b ldr r3, [r3, #40] ; 0x28 80061a8: 430b orrs r3, r1 80061aa: 4927 ldr r1, [pc, #156] ; (8006248 ) 80061ac: 4313 orrs r3, r2 80061ae: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 80061b0: 4b26 ldr r3, [pc, #152] ; (800624c ) 80061b2: 2201 movs r2, #1 80061b4: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80061b6: f7fd fd53 bl 8003c60 80061ba: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80061bc: e008 b.n 80061d0 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80061be: f7fd fd4f bl 8003c60 80061c2: 4602 mov r2, r0 80061c4: 693b ldr r3, [r7, #16] 80061c6: 1ad3 subs r3, r2, r3 80061c8: 2b02 cmp r3, #2 80061ca: d901 bls.n 80061d0 { return HAL_TIMEOUT; 80061cc: 2303 movs r3, #3 80061ce: e037 b.n 8006240 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80061d0: 4b1d ldr r3, [pc, #116] ; (8006248 ) 80061d2: 681b ldr r3, [r3, #0] 80061d4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80061d8: 2b00 cmp r3, #0 80061da: d0f0 beq.n 80061be 80061dc: e02f b.n 800623e } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80061de: 4b1b ldr r3, [pc, #108] ; (800624c ) 80061e0: 2200 movs r2, #0 80061e2: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80061e4: f7fd fd3c bl 8003c60 80061e8: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80061ea: e008 b.n 80061fe { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80061ec: f7fd fd38 bl 8003c60 80061f0: 4602 mov r2, r0 80061f2: 693b ldr r3, [r7, #16] 80061f4: 1ad3 subs r3, r2, r3 80061f6: 2b02 cmp r3, #2 80061f8: d901 bls.n 80061fe { return HAL_TIMEOUT; 80061fa: 2303 movs r3, #3 80061fc: e020 b.n 8006240 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80061fe: 4b12 ldr r3, [pc, #72] ; (8006248 ) 8006200: 681b ldr r3, [r3, #0] 8006202: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8006206: 2b00 cmp r3, #0 8006208: d1f0 bne.n 80061ec 800620a: e018 b.n 800623e } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 800620c: 687b ldr r3, [r7, #4] 800620e: 6a1b ldr r3, [r3, #32] 8006210: 2b01 cmp r3, #1 8006212: d101 bne.n 8006218 { return HAL_ERROR; 8006214: 2301 movs r3, #1 8006216: e013 b.n 8006240 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8006218: 4b0b ldr r3, [pc, #44] ; (8006248 ) 800621a: 685b ldr r3, [r3, #4] 800621c: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800621e: 68fb ldr r3, [r7, #12] 8006220: f403 3280 and.w r2, r3, #65536 ; 0x10000 8006224: 687b ldr r3, [r7, #4] 8006226: 6a5b ldr r3, [r3, #36] ; 0x24 8006228: 429a cmp r2, r3 800622a: d106 bne.n 800623a (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 800622c: 68fb ldr r3, [r7, #12] 800622e: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000 8006232: 687b ldr r3, [r7, #4] 8006234: 6a9b ldr r3, [r3, #40] ; 0x28 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8006236: 429a cmp r2, r3 8006238: d001 beq.n 800623e { return HAL_ERROR; 800623a: 2301 movs r3, #1 800623c: e000 b.n 8006240 } } } } return HAL_OK; 800623e: 2300 movs r3, #0 } 8006240: 4618 mov r0, r3 8006242: 3718 adds r7, #24 8006244: 46bd mov sp, r7 8006246: bd80 pop {r7, pc} 8006248: 40021000 .word 0x40021000 800624c: 42420060 .word 0x42420060 08006250 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8006250: b580 push {r7, lr} 8006252: b084 sub sp, #16 8006254: af00 add r7, sp, #0 8006256: 6078 str r0, [r7, #4] 8006258: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800625a: 687b ldr r3, [r7, #4] 800625c: 2b00 cmp r3, #0 800625e: d101 bne.n 8006264 { return HAL_ERROR; 8006260: 2301 movs r3, #1 8006262: e0d0 b.n 8006406 must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8006264: 4b6a ldr r3, [pc, #424] ; (8006410 ) 8006266: 681b ldr r3, [r3, #0] 8006268: f003 0307 and.w r3, r3, #7 800626c: 683a ldr r2, [r7, #0] 800626e: 429a cmp r2, r3 8006270: d910 bls.n 8006294 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8006272: 4b67 ldr r3, [pc, #412] ; (8006410 ) 8006274: 681b ldr r3, [r3, #0] 8006276: f023 0207 bic.w r2, r3, #7 800627a: 4965 ldr r1, [pc, #404] ; (8006410 ) 800627c: 683b ldr r3, [r7, #0] 800627e: 4313 orrs r3, r2 8006280: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8006282: 4b63 ldr r3, [pc, #396] ; (8006410 ) 8006284: 681b ldr r3, [r3, #0] 8006286: f003 0307 and.w r3, r3, #7 800628a: 683a ldr r2, [r7, #0] 800628c: 429a cmp r2, r3 800628e: d001 beq.n 8006294 { return HAL_ERROR; 8006290: 2301 movs r3, #1 8006292: e0b8 b.n 8006406 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8006294: 687b ldr r3, [r7, #4] 8006296: 681b ldr r3, [r3, #0] 8006298: f003 0302 and.w r3, r3, #2 800629c: 2b00 cmp r3, #0 800629e: d020 beq.n 80062e2 { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80062a0: 687b ldr r3, [r7, #4] 80062a2: 681b ldr r3, [r3, #0] 80062a4: f003 0304 and.w r3, r3, #4 80062a8: 2b00 cmp r3, #0 80062aa: d005 beq.n 80062b8 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 80062ac: 4b59 ldr r3, [pc, #356] ; (8006414 ) 80062ae: 685b ldr r3, [r3, #4] 80062b0: 4a58 ldr r2, [pc, #352] ; (8006414 ) 80062b2: f443 63e0 orr.w r3, r3, #1792 ; 0x700 80062b6: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80062b8: 687b ldr r3, [r7, #4] 80062ba: 681b ldr r3, [r3, #0] 80062bc: f003 0308 and.w r3, r3, #8 80062c0: 2b00 cmp r3, #0 80062c2: d005 beq.n 80062d0 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 80062c4: 4b53 ldr r3, [pc, #332] ; (8006414 ) 80062c6: 685b ldr r3, [r3, #4] 80062c8: 4a52 ldr r2, [pc, #328] ; (8006414 ) 80062ca: f443 5360 orr.w r3, r3, #14336 ; 0x3800 80062ce: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 80062d0: 4b50 ldr r3, [pc, #320] ; (8006414 ) 80062d2: 685b ldr r3, [r3, #4] 80062d4: f023 02f0 bic.w r2, r3, #240 ; 0xf0 80062d8: 687b ldr r3, [r7, #4] 80062da: 689b ldr r3, [r3, #8] 80062dc: 494d ldr r1, [pc, #308] ; (8006414 ) 80062de: 4313 orrs r3, r2 80062e0: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80062e2: 687b ldr r3, [r7, #4] 80062e4: 681b ldr r3, [r3, #0] 80062e6: f003 0301 and.w r3, r3, #1 80062ea: 2b00 cmp r3, #0 80062ec: d040 beq.n 8006370 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80062ee: 687b ldr r3, [r7, #4] 80062f0: 685b ldr r3, [r3, #4] 80062f2: 2b01 cmp r3, #1 80062f4: d107 bne.n 8006306 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80062f6: 4b47 ldr r3, [pc, #284] ; (8006414 ) 80062f8: 681b ldr r3, [r3, #0] 80062fa: f403 3300 and.w r3, r3, #131072 ; 0x20000 80062fe: 2b00 cmp r3, #0 8006300: d115 bne.n 800632e { return HAL_ERROR; 8006302: 2301 movs r3, #1 8006304: e07f b.n 8006406 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8006306: 687b ldr r3, [r7, #4] 8006308: 685b ldr r3, [r3, #4] 800630a: 2b02 cmp r3, #2 800630c: d107 bne.n 800631e { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800630e: 4b41 ldr r3, [pc, #260] ; (8006414 ) 8006310: 681b ldr r3, [r3, #0] 8006312: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8006316: 2b00 cmp r3, #0 8006318: d109 bne.n 800632e { return HAL_ERROR; 800631a: 2301 movs r3, #1 800631c: e073 b.n 8006406 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800631e: 4b3d ldr r3, [pc, #244] ; (8006414 ) 8006320: 681b ldr r3, [r3, #0] 8006322: f003 0302 and.w r3, r3, #2 8006326: 2b00 cmp r3, #0 8006328: d101 bne.n 800632e { return HAL_ERROR; 800632a: 2301 movs r3, #1 800632c: e06b b.n 8006406 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 800632e: 4b39 ldr r3, [pc, #228] ; (8006414 ) 8006330: 685b ldr r3, [r3, #4] 8006332: f023 0203 bic.w r2, r3, #3 8006336: 687b ldr r3, [r7, #4] 8006338: 685b ldr r3, [r3, #4] 800633a: 4936 ldr r1, [pc, #216] ; (8006414 ) 800633c: 4313 orrs r3, r2 800633e: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8006340: f7fd fc8e bl 8003c60 8006344: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8006346: e00a b.n 800635e { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8006348: f7fd fc8a bl 8003c60 800634c: 4602 mov r2, r0 800634e: 68fb ldr r3, [r7, #12] 8006350: 1ad3 subs r3, r2, r3 8006352: f241 3288 movw r2, #5000 ; 0x1388 8006356: 4293 cmp r3, r2 8006358: d901 bls.n 800635e { return HAL_TIMEOUT; 800635a: 2303 movs r3, #3 800635c: e053 b.n 8006406 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800635e: 4b2d ldr r3, [pc, #180] ; (8006414 ) 8006360: 685b ldr r3, [r3, #4] 8006362: f003 020c and.w r2, r3, #12 8006366: 687b ldr r3, [r7, #4] 8006368: 685b ldr r3, [r3, #4] 800636a: 009b lsls r3, r3, #2 800636c: 429a cmp r2, r3 800636e: d1eb bne.n 8006348 } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8006370: 4b27 ldr r3, [pc, #156] ; (8006410 ) 8006372: 681b ldr r3, [r3, #0] 8006374: f003 0307 and.w r3, r3, #7 8006378: 683a ldr r2, [r7, #0] 800637a: 429a cmp r2, r3 800637c: d210 bcs.n 80063a0 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800637e: 4b24 ldr r3, [pc, #144] ; (8006410 ) 8006380: 681b ldr r3, [r3, #0] 8006382: f023 0207 bic.w r2, r3, #7 8006386: 4922 ldr r1, [pc, #136] ; (8006410 ) 8006388: 683b ldr r3, [r7, #0] 800638a: 4313 orrs r3, r2 800638c: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800638e: 4b20 ldr r3, [pc, #128] ; (8006410 ) 8006390: 681b ldr r3, [r3, #0] 8006392: f003 0307 and.w r3, r3, #7 8006396: 683a ldr r2, [r7, #0] 8006398: 429a cmp r2, r3 800639a: d001 beq.n 80063a0 { return HAL_ERROR; 800639c: 2301 movs r3, #1 800639e: e032 b.n 8006406 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80063a0: 687b ldr r3, [r7, #4] 80063a2: 681b ldr r3, [r3, #0] 80063a4: f003 0304 and.w r3, r3, #4 80063a8: 2b00 cmp r3, #0 80063aa: d008 beq.n 80063be { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 80063ac: 4b19 ldr r3, [pc, #100] ; (8006414 ) 80063ae: 685b ldr r3, [r3, #4] 80063b0: f423 62e0 bic.w r2, r3, #1792 ; 0x700 80063b4: 687b ldr r3, [r7, #4] 80063b6: 68db ldr r3, [r3, #12] 80063b8: 4916 ldr r1, [pc, #88] ; (8006414 ) 80063ba: 4313 orrs r3, r2 80063bc: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80063be: 687b ldr r3, [r7, #4] 80063c0: 681b ldr r3, [r3, #0] 80063c2: f003 0308 and.w r3, r3, #8 80063c6: 2b00 cmp r3, #0 80063c8: d009 beq.n 80063de { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 80063ca: 4b12 ldr r3, [pc, #72] ; (8006414 ) 80063cc: 685b ldr r3, [r3, #4] 80063ce: f423 5260 bic.w r2, r3, #14336 ; 0x3800 80063d2: 687b ldr r3, [r7, #4] 80063d4: 691b ldr r3, [r3, #16] 80063d6: 00db lsls r3, r3, #3 80063d8: 490e ldr r1, [pc, #56] ; (8006414 ) 80063da: 4313 orrs r3, r2 80063dc: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 80063de: f000 f821 bl 8006424 80063e2: 4602 mov r2, r0 80063e4: 4b0b ldr r3, [pc, #44] ; (8006414 ) 80063e6: 685b ldr r3, [r3, #4] 80063e8: 091b lsrs r3, r3, #4 80063ea: f003 030f and.w r3, r3, #15 80063ee: 490a ldr r1, [pc, #40] ; (8006418 ) 80063f0: 5ccb ldrb r3, [r1, r3] 80063f2: fa22 f303 lsr.w r3, r2, r3 80063f6: 4a09 ldr r2, [pc, #36] ; (800641c ) 80063f8: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 80063fa: 4b09 ldr r3, [pc, #36] ; (8006420 ) 80063fc: 681b ldr r3, [r3, #0] 80063fe: 4618 mov r0, r3 8006400: f7fd fbec bl 8003bdc return HAL_OK; 8006404: 2300 movs r3, #0 } 8006406: 4618 mov r0, r3 8006408: 3710 adds r7, #16 800640a: 46bd mov sp, r7 800640c: bd80 pop {r7, pc} 800640e: bf00 nop 8006410: 40022000 .word 0x40022000 8006414: 40021000 .word 0x40021000 8006418: 08008e04 .word 0x08008e04 800641c: 20000000 .word 0x20000000 8006420: 20000004 .word 0x20000004 08006424 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8006424: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8006428: b099 sub sp, #100 ; 0x64 800642a: af00 add r7, sp, #0 #if defined(RCC_CFGR2_PREDIV1SRC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; 800642c: 4b66 ldr r3, [pc, #408] ; (80065c8 ) 800642e: f107 0434 add.w r4, r7, #52 ; 0x34 8006432: cb0f ldmia r3, {r0, r1, r2, r3} 8006434: c407 stmia r4!, {r0, r1, r2} 8006436: 8023 strh r3, [r4, #0] const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; 8006438: 4b64 ldr r3, [pc, #400] ; (80065cc ) 800643a: f107 0424 add.w r4, r7, #36 ; 0x24 800643e: cb0f ldmia r3, {r0, r1, r2, r3} 8006440: e884 000f stmia.w r4, {r0, r1, r2, r3} #else const uint8_t aPredivFactorTable[2] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8006444: 2300 movs r3, #0 8006446: 657b str r3, [r7, #84] ; 0x54 8006448: 2300 movs r3, #0 800644a: 653b str r3, [r7, #80] ; 0x50 800644c: 2300 movs r3, #0 800644e: 65fb str r3, [r7, #92] ; 0x5c 8006450: 2300 movs r3, #0 8006452: 64fb str r3, [r7, #76] ; 0x4c uint32_t sysclockfreq = 0U; 8006454: 2300 movs r3, #0 8006456: 65bb str r3, [r7, #88] ; 0x58 #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; 8006458: 2300 movs r3, #0 800645a: 64bb str r3, [r7, #72] ; 0x48 800645c: 2300 movs r3, #0 800645e: 647b str r3, [r7, #68] ; 0x44 #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 8006460: 4b5b ldr r3, [pc, #364] ; (80065d0 ) 8006462: 685b ldr r3, [r3, #4] 8006464: 657b str r3, [r7, #84] ; 0x54 /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8006466: 6d7b ldr r3, [r7, #84] ; 0x54 8006468: f003 030c and.w r3, r3, #12 800646c: 2b04 cmp r3, #4 800646e: d002 beq.n 8006476 8006470: 2b08 cmp r3, #8 8006472: d003 beq.n 800647c 8006474: e09f b.n 80065b6 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8006476: 4b57 ldr r3, [pc, #348] ; (80065d4 ) 8006478: 65bb str r3, [r7, #88] ; 0x58 break; 800647a: e09f b.n 80065bc } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 800647c: 6d7b ldr r3, [r7, #84] ; 0x54 800647e: 0c9b lsrs r3, r3, #18 8006480: f003 030f and.w r3, r3, #15 8006484: 3340 adds r3, #64 ; 0x40 8006486: f107 0220 add.w r2, r7, #32 800648a: 4413 add r3, r2 800648c: f813 3c2c ldrb.w r3, [r3, #-44] 8006490: 64fb str r3, [r7, #76] ; 0x4c if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8006492: 6d7b ldr r3, [r7, #84] ; 0x54 8006494: f403 3380 and.w r3, r3, #65536 ; 0x10000 8006498: 2b00 cmp r3, #0 800649a: f000 8084 beq.w 80065a6 { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 800649e: 4b4c ldr r3, [pc, #304] ; (80065d0 ) 80064a0: 6adb ldr r3, [r3, #44] ; 0x2c 80064a2: f003 030f and.w r3, r3, #15 80064a6: 3340 adds r3, #64 ; 0x40 80064a8: f107 0220 add.w r2, r7, #32 80064ac: 4413 add r3, r2 80064ae: f813 3c3c ldrb.w r3, [r3, #-60] 80064b2: 653b str r3, [r7, #80] ; 0x50 #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /*RCC_CFGR2_PREDIV1*/ #if defined(RCC_CFGR2_PREDIV1SRC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 80064b4: 4b46 ldr r3, [pc, #280] ; (80065d0 ) 80064b6: 6adb ldr r3, [r3, #44] ; 0x2c 80064b8: f403 3380 and.w r3, r3, #65536 ; 0x10000 80064bc: 2b00 cmp r3, #0 80064be: d060 beq.n 8006582 { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 80064c0: 4b43 ldr r3, [pc, #268] ; (80065d0 ) 80064c2: 6adb ldr r3, [r3, #44] ; 0x2c 80064c4: 091b lsrs r3, r3, #4 80064c6: f003 030f and.w r3, r3, #15 80064ca: 3301 adds r3, #1 80064cc: 64bb str r3, [r7, #72] ; 0x48 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 80064ce: 4b40 ldr r3, [pc, #256] ; (80065d0 ) 80064d0: 6adb ldr r3, [r3, #44] ; 0x2c 80064d2: 0a1b lsrs r3, r3, #8 80064d4: f003 030f and.w r3, r3, #15 80064d8: 3302 adds r3, #2 80064da: 647b str r3, [r7, #68] ; 0x44 pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); 80064dc: 6c7b ldr r3, [r7, #68] ; 0x44 80064de: 2200 movs r2, #0 80064e0: 613b str r3, [r7, #16] 80064e2: 617a str r2, [r7, #20] 80064e4: 6cfb ldr r3, [r7, #76] ; 0x4c 80064e6: 2200 movs r2, #0 80064e8: 61bb str r3, [r7, #24] 80064ea: 61fa str r2, [r7, #28] 80064ec: e9d7 3404 ldrd r3, r4, [r7, #16] 80064f0: 4622 mov r2, r4 80064f2: e9d7 0106 ldrd r0, r1, [r7, #24] 80064f6: 4684 mov ip, r0 80064f8: fb0c f202 mul.w r2, ip, r2 80064fc: e9c7 0106 strd r0, r1, [r7, #24] 8006500: 468c mov ip, r1 8006502: 4618 mov r0, r3 8006504: 4621 mov r1, r4 8006506: 4603 mov r3, r0 8006508: fb03 f30c mul.w r3, r3, ip 800650c: 4413 add r3, r2 800650e: 4602 mov r2, r0 8006510: 69b9 ldr r1, [r7, #24] 8006512: fba2 8901 umull r8, r9, r2, r1 8006516: 444b add r3, r9 8006518: 4699 mov r9, r3 800651a: 4b2e ldr r3, [pc, #184] ; (80065d4 ) 800651c: fb03 f209 mul.w r2, r3, r9 8006520: 2300 movs r3, #0 8006522: fb03 f308 mul.w r3, r3, r8 8006526: 4413 add r3, r2 8006528: 4a2a ldr r2, [pc, #168] ; (80065d4 ) 800652a: fba8 ab02 umull sl, fp, r8, r2 800652e: 445b add r3, fp 8006530: 469b mov fp, r3 8006532: 6cbb ldr r3, [r7, #72] ; 0x48 8006534: 2200 movs r2, #0 8006536: 60bb str r3, [r7, #8] 8006538: 60fa str r2, [r7, #12] 800653a: 6d3b ldr r3, [r7, #80] ; 0x50 800653c: 2200 movs r2, #0 800653e: 603b str r3, [r7, #0] 8006540: 607a str r2, [r7, #4] 8006542: e9d7 3402 ldrd r3, r4, [r7, #8] 8006546: 4622 mov r2, r4 8006548: e9d7 8900 ldrd r8, r9, [r7] 800654c: 4641 mov r1, r8 800654e: fb01 f202 mul.w r2, r1, r2 8006552: 46cc mov ip, r9 8006554: 4618 mov r0, r3 8006556: 4621 mov r1, r4 8006558: 4603 mov r3, r0 800655a: fb03 f30c mul.w r3, r3, ip 800655e: 4413 add r3, r2 8006560: 4602 mov r2, r0 8006562: 4641 mov r1, r8 8006564: fba2 5601 umull r5, r6, r2, r1 8006568: 4433 add r3, r6 800656a: 461e mov r6, r3 800656c: 462a mov r2, r5 800656e: 4633 mov r3, r6 8006570: 4650 mov r0, sl 8006572: 4659 mov r1, fp 8006574: f7fa fb36 bl 8000be4 <__aeabi_uldivmod> 8006578: 4602 mov r2, r0 800657a: 460b mov r3, r1 800657c: 4613 mov r3, r2 800657e: 65fb str r3, [r7, #92] ; 0x5c 8006580: e007 b.n 8006592 } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8006582: 6cfb ldr r3, [r7, #76] ; 0x4c 8006584: 4a13 ldr r2, [pc, #76] ; (80065d4 ) 8006586: fb03 f202 mul.w r2, r3, r2 800658a: 6d3b ldr r3, [r7, #80] ; 0x50 800658c: fbb2 f3f3 udiv r3, r2, r3 8006590: 65fb str r3, [r7, #92] ; 0x5c } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 8006592: f897 3041 ldrb.w r3, [r7, #65] ; 0x41 8006596: 461a mov r2, r3 8006598: 6cfb ldr r3, [r7, #76] ; 0x4c 800659a: 4293 cmp r3, r2 800659c: d108 bne.n 80065b0 { pllclk = pllclk / 2; 800659e: 6dfb ldr r3, [r7, #92] ; 0x5c 80065a0: 085b lsrs r3, r3, #1 80065a2: 65fb str r3, [r7, #92] ; 0x5c 80065a4: e004 b.n 80065b0 #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 80065a6: 6cfb ldr r3, [r7, #76] ; 0x4c 80065a8: 4a0b ldr r2, [pc, #44] ; (80065d8 ) 80065aa: fb02 f303 mul.w r3, r2, r3 80065ae: 65fb str r3, [r7, #92] ; 0x5c } sysclockfreq = pllclk; 80065b0: 6dfb ldr r3, [r7, #92] ; 0x5c 80065b2: 65bb str r3, [r7, #88] ; 0x58 break; 80065b4: e002 b.n 80065bc } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 80065b6: 4b09 ldr r3, [pc, #36] ; (80065dc ) 80065b8: 65bb str r3, [r7, #88] ; 0x58 break; 80065ba: bf00 nop } } return sysclockfreq; 80065bc: 6dbb ldr r3, [r7, #88] ; 0x58 } 80065be: 4618 mov r0, r3 80065c0: 3764 adds r7, #100 ; 0x64 80065c2: 46bd mov sp, r7 80065c4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80065c8: 08008dc4 .word 0x08008dc4 80065cc: 08008dd4 .word 0x08008dd4 80065d0: 40021000 .word 0x40021000 80065d4: 017d7840 .word 0x017d7840 80065d8: 003d0900 .word 0x003d0900 80065dc: 007a1200 .word 0x007a1200 080065e0 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 80065e0: b480 push {r7} 80065e2: af00 add r7, sp, #0 return SystemCoreClock; 80065e4: 4b02 ldr r3, [pc, #8] ; (80065f0 ) 80065e6: 681b ldr r3, [r3, #0] } 80065e8: 4618 mov r0, r3 80065ea: 46bd mov sp, r7 80065ec: bc80 pop {r7} 80065ee: 4770 bx lr 80065f0: 20000000 .word 0x20000000 080065f4 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 80065f4: b580 push {r7, lr} 80065f6: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 80065f8: f7ff fff2 bl 80065e0 80065fc: 4602 mov r2, r0 80065fe: 4b05 ldr r3, [pc, #20] ; (8006614 ) 8006600: 685b ldr r3, [r3, #4] 8006602: 0a1b lsrs r3, r3, #8 8006604: f003 0307 and.w r3, r3, #7 8006608: 4903 ldr r1, [pc, #12] ; (8006618 ) 800660a: 5ccb ldrb r3, [r1, r3] 800660c: fa22 f303 lsr.w r3, r2, r3 } 8006610: 4618 mov r0, r3 8006612: bd80 pop {r7, pc} 8006614: 40021000 .word 0x40021000 8006618: 08008e14 .word 0x08008e14 0800661c : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 800661c: b580 push {r7, lr} 800661e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8006620: f7ff ffde bl 80065e0 8006624: 4602 mov r2, r0 8006626: 4b05 ldr r3, [pc, #20] ; (800663c ) 8006628: 685b ldr r3, [r3, #4] 800662a: 0adb lsrs r3, r3, #11 800662c: f003 0307 and.w r3, r3, #7 8006630: 4903 ldr r1, [pc, #12] ; (8006640 ) 8006632: 5ccb ldrb r3, [r1, r3] 8006634: fa22 f303 lsr.w r3, r2, r3 } 8006638: 4618 mov r0, r3 800663a: bd80 pop {r7, pc} 800663c: 40021000 .word 0x40021000 8006640: 08008e14 .word 0x08008e14 08006644 : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 8006644: b480 push {r7} 8006646: b085 sub sp, #20 8006648: af00 add r7, sp, #0 800664a: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 800664c: 4b0a ldr r3, [pc, #40] ; (8006678 ) 800664e: 681b ldr r3, [r3, #0] 8006650: 4a0a ldr r2, [pc, #40] ; (800667c ) 8006652: fba2 2303 umull r2, r3, r2, r3 8006656: 0a5b lsrs r3, r3, #9 8006658: 687a ldr r2, [r7, #4] 800665a: fb02 f303 mul.w r3, r2, r3 800665e: 60fb str r3, [r7, #12] do { __NOP(); 8006660: bf00 nop } while (Delay --); 8006662: 68fb ldr r3, [r7, #12] 8006664: 1e5a subs r2, r3, #1 8006666: 60fa str r2, [r7, #12] 8006668: 2b00 cmp r3, #0 800666a: d1f9 bne.n 8006660 } 800666c: bf00 nop 800666e: bf00 nop 8006670: 3714 adds r7, #20 8006672: 46bd mov sp, r7 8006674: bc80 pop {r7} 8006676: 4770 bx lr 8006678: 20000000 .word 0x20000000 800667c: 10624dd3 .word 0x10624dd3 08006680 : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8006680: b580 push {r7, lr} 8006682: b088 sub sp, #32 8006684: af00 add r7, sp, #0 8006686: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 8006688: 2300 movs r3, #0 800668a: 617b str r3, [r7, #20] 800668c: 2300 movs r3, #0 800668e: 613b str r3, [r7, #16] #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t pllactive = 0U; 8006690: 2300 movs r3, #0 8006692: 61fb str r3, [r7, #28] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 8006694: 687b ldr r3, [r7, #4] 8006696: 681b ldr r3, [r3, #0] 8006698: f003 0301 and.w r3, r3, #1 800669c: 2b00 cmp r3, #0 800669e: d07d beq.n 800679c { FlagStatus pwrclkchanged = RESET; 80066a0: 2300 movs r3, #0 80066a2: 76fb strb r3, [r7, #27] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80066a4: 4b8b ldr r3, [pc, #556] ; (80068d4 ) 80066a6: 69db ldr r3, [r3, #28] 80066a8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80066ac: 2b00 cmp r3, #0 80066ae: d10d bne.n 80066cc { __HAL_RCC_PWR_CLK_ENABLE(); 80066b0: 4b88 ldr r3, [pc, #544] ; (80068d4 ) 80066b2: 69db ldr r3, [r3, #28] 80066b4: 4a87 ldr r2, [pc, #540] ; (80068d4 ) 80066b6: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80066ba: 61d3 str r3, [r2, #28] 80066bc: 4b85 ldr r3, [pc, #532] ; (80068d4 ) 80066be: 69db ldr r3, [r3, #28] 80066c0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80066c4: 60fb str r3, [r7, #12] 80066c6: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 80066c8: 2301 movs r3, #1 80066ca: 76fb strb r3, [r7, #27] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80066cc: 4b82 ldr r3, [pc, #520] ; (80068d8 ) 80066ce: 681b ldr r3, [r3, #0] 80066d0: f403 7380 and.w r3, r3, #256 ; 0x100 80066d4: 2b00 cmp r3, #0 80066d6: d118 bne.n 800670a { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 80066d8: 4b7f ldr r3, [pc, #508] ; (80068d8 ) 80066da: 681b ldr r3, [r3, #0] 80066dc: 4a7e ldr r2, [pc, #504] ; (80068d8 ) 80066de: f443 7380 orr.w r3, r3, #256 ; 0x100 80066e2: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80066e4: f7fd fabc bl 8003c60 80066e8: 6178 str r0, [r7, #20] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80066ea: e008 b.n 80066fe { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80066ec: f7fd fab8 bl 8003c60 80066f0: 4602 mov r2, r0 80066f2: 697b ldr r3, [r7, #20] 80066f4: 1ad3 subs r3, r2, r3 80066f6: 2b64 cmp r3, #100 ; 0x64 80066f8: d901 bls.n 80066fe { return HAL_TIMEOUT; 80066fa: 2303 movs r3, #3 80066fc: e0e5 b.n 80068ca while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80066fe: 4b76 ldr r3, [pc, #472] ; (80068d8 ) 8006700: 681b ldr r3, [r3, #0] 8006702: f403 7380 and.w r3, r3, #256 ; 0x100 8006706: 2b00 cmp r3, #0 8006708: d0f0 beq.n 80066ec } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 800670a: 4b72 ldr r3, [pc, #456] ; (80068d4 ) 800670c: 6a1b ldr r3, [r3, #32] 800670e: f403 7340 and.w r3, r3, #768 ; 0x300 8006712: 613b str r3, [r7, #16] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8006714: 693b ldr r3, [r7, #16] 8006716: 2b00 cmp r3, #0 8006718: d02e beq.n 8006778 800671a: 687b ldr r3, [r7, #4] 800671c: 685b ldr r3, [r3, #4] 800671e: f403 7340 and.w r3, r3, #768 ; 0x300 8006722: 693a ldr r2, [r7, #16] 8006724: 429a cmp r2, r3 8006726: d027 beq.n 8006778 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8006728: 4b6a ldr r3, [pc, #424] ; (80068d4 ) 800672a: 6a1b ldr r3, [r3, #32] 800672c: f423 7340 bic.w r3, r3, #768 ; 0x300 8006730: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8006732: 4b6a ldr r3, [pc, #424] ; (80068dc ) 8006734: 2201 movs r2, #1 8006736: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8006738: 4b68 ldr r3, [pc, #416] ; (80068dc ) 800673a: 2200 movs r2, #0 800673c: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 800673e: 4a65 ldr r2, [pc, #404] ; (80068d4 ) 8006740: 693b ldr r3, [r7, #16] 8006742: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8006744: 693b ldr r3, [r7, #16] 8006746: f003 0301 and.w r3, r3, #1 800674a: 2b00 cmp r3, #0 800674c: d014 beq.n 8006778 { /* Get Start Tick */ tickstart = HAL_GetTick(); 800674e: f7fd fa87 bl 8003c60 8006752: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8006754: e00a b.n 800676c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8006756: f7fd fa83 bl 8003c60 800675a: 4602 mov r2, r0 800675c: 697b ldr r3, [r7, #20] 800675e: 1ad3 subs r3, r2, r3 8006760: f241 3288 movw r2, #5000 ; 0x1388 8006764: 4293 cmp r3, r2 8006766: d901 bls.n 800676c { return HAL_TIMEOUT; 8006768: 2303 movs r3, #3 800676a: e0ae b.n 80068ca while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800676c: 4b59 ldr r3, [pc, #356] ; (80068d4 ) 800676e: 6a1b ldr r3, [r3, #32] 8006770: f003 0302 and.w r3, r3, #2 8006774: 2b00 cmp r3, #0 8006776: d0ee beq.n 8006756 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8006778: 4b56 ldr r3, [pc, #344] ; (80068d4 ) 800677a: 6a1b ldr r3, [r3, #32] 800677c: f423 7240 bic.w r2, r3, #768 ; 0x300 8006780: 687b ldr r3, [r7, #4] 8006782: 685b ldr r3, [r3, #4] 8006784: 4953 ldr r1, [pc, #332] ; (80068d4 ) 8006786: 4313 orrs r3, r2 8006788: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 800678a: 7efb ldrb r3, [r7, #27] 800678c: 2b01 cmp r3, #1 800678e: d105 bne.n 800679c { __HAL_RCC_PWR_CLK_DISABLE(); 8006790: 4b50 ldr r3, [pc, #320] ; (80068d4 ) 8006792: 69db ldr r3, [r3, #28] 8006794: 4a4f ldr r2, [pc, #316] ; (80068d4 ) 8006796: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 800679a: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 800679c: 687b ldr r3, [r7, #4] 800679e: 681b ldr r3, [r3, #0] 80067a0: f003 0302 and.w r3, r3, #2 80067a4: 2b00 cmp r3, #0 80067a6: d008 beq.n 80067ba { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 80067a8: 4b4a ldr r3, [pc, #296] ; (80068d4 ) 80067aa: 685b ldr r3, [r3, #4] 80067ac: f423 4240 bic.w r2, r3, #49152 ; 0xc000 80067b0: 687b ldr r3, [r7, #4] 80067b2: 689b ldr r3, [r3, #8] 80067b4: 4947 ldr r1, [pc, #284] ; (80068d4 ) 80067b6: 4313 orrs r3, r2 80067b8: 604b str r3, [r1, #4] } #if defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ I2S2 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) 80067ba: 687b ldr r3, [r7, #4] 80067bc: 681b ldr r3, [r3, #0] 80067be: f003 0304 and.w r3, r3, #4 80067c2: 2b00 cmp r3, #0 80067c4: d008 beq.n 80067d8 { /* Check the parameters */ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); /* Configure the I2S2 clock source */ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); 80067c6: 4b43 ldr r3, [pc, #268] ; (80068d4 ) 80067c8: 6adb ldr r3, [r3, #44] ; 0x2c 80067ca: f423 3200 bic.w r2, r3, #131072 ; 0x20000 80067ce: 687b ldr r3, [r7, #4] 80067d0: 68db ldr r3, [r3, #12] 80067d2: 4940 ldr r1, [pc, #256] ; (80068d4 ) 80067d4: 4313 orrs r3, r2 80067d6: 62cb str r3, [r1, #44] ; 0x2c } /*------------------------------ I2S3 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) 80067d8: 687b ldr r3, [r7, #4] 80067da: 681b ldr r3, [r3, #0] 80067dc: f003 0308 and.w r3, r3, #8 80067e0: 2b00 cmp r3, #0 80067e2: d008 beq.n 80067f6 { /* Check the parameters */ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); /* Configure the I2S3 clock source */ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); 80067e4: 4b3b ldr r3, [pc, #236] ; (80068d4 ) 80067e6: 6adb ldr r3, [r3, #44] ; 0x2c 80067e8: f423 2280 bic.w r2, r3, #262144 ; 0x40000 80067ec: 687b ldr r3, [r7, #4] 80067ee: 691b ldr r3, [r3, #16] 80067f0: 4938 ldr r1, [pc, #224] ; (80068d4 ) 80067f2: 4313 orrs r3, r2 80067f4: 62cb str r3, [r1, #44] ; 0x2c } /*------------------------------ PLL I2S Configuration ----------------------*/ /* Check that PLLI2S need to be enabled */ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) 80067f6: 4b37 ldr r3, [pc, #220] ; (80068d4 ) 80067f8: 6adb ldr r3, [r3, #44] ; 0x2c 80067fa: f403 3300 and.w r3, r3, #131072 ; 0x20000 80067fe: 2b00 cmp r3, #0 8006800: d105 bne.n 800680e 8006802: 4b34 ldr r3, [pc, #208] ; (80068d4 ) 8006804: 6adb ldr r3, [r3, #44] ; 0x2c 8006806: f403 2380 and.w r3, r3, #262144 ; 0x40000 800680a: 2b00 cmp r3, #0 800680c: d001 beq.n 8006812 { /* Update flag to indicate that PLL I2S should be active */ pllactive = 1; 800680e: 2301 movs r3, #1 8006810: 61fb str r3, [r7, #28] } /* Check if PLL I2S need to be enabled */ if (pllactive == 1) 8006812: 69fb ldr r3, [r7, #28] 8006814: 2b01 cmp r3, #1 8006816: d148 bne.n 80068aa { /* Enable PLL I2S only if not active */ if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) 8006818: 4b2e ldr r3, [pc, #184] ; (80068d4 ) 800681a: 681b ldr r3, [r3, #0] 800681c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8006820: 2b00 cmp r3, #0 8006822: d138 bne.n 8006896 assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); /* Prediv2 can be written only when the PLL2 is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 8006824: 4b2b ldr r3, [pc, #172] ; (80068d4 ) 8006826: 681b ldr r3, [r3, #0] 8006828: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 800682c: 2b00 cmp r3, #0 800682e: d009 beq.n 8006844 (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) 8006830: 4b28 ldr r3, [pc, #160] ; (80068d4 ) 8006832: 6adb ldr r3, [r3, #44] ; 0x2c 8006834: f003 02f0 and.w r2, r3, #240 ; 0xf0 8006838: 687b ldr r3, [r7, #4] 800683a: 699b ldr r3, [r3, #24] if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ 800683c: 429a cmp r2, r3 800683e: d001 beq.n 8006844 { return HAL_ERROR; 8006840: 2301 movs r3, #1 8006842: e042 b.n 80068ca } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); 8006844: 4b23 ldr r3, [pc, #140] ; (80068d4 ) 8006846: 6adb ldr r3, [r3, #44] ; 0x2c 8006848: f023 02f0 bic.w r2, r3, #240 ; 0xf0 800684c: 687b ldr r3, [r7, #4] 800684e: 699b ldr r3, [r3, #24] 8006850: 4920 ldr r1, [pc, #128] ; (80068d4 ) 8006852: 4313 orrs r3, r2 8006854: 62cb str r3, [r1, #44] ; 0x2c /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); 8006856: 4b1f ldr r3, [pc, #124] ; (80068d4 ) 8006858: 6adb ldr r3, [r3, #44] ; 0x2c 800685a: f423 4270 bic.w r2, r3, #61440 ; 0xf000 800685e: 687b ldr r3, [r7, #4] 8006860: 695b ldr r3, [r3, #20] 8006862: 491c ldr r1, [pc, #112] ; (80068d4 ) 8006864: 4313 orrs r3, r2 8006866: 62cb str r3, [r1, #44] ; 0x2c /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); 8006868: 4b1d ldr r3, [pc, #116] ; (80068e0 ) 800686a: 2201 movs r2, #1 800686c: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800686e: f7fd f9f7 bl 8003c60 8006872: 6178 str r0, [r7, #20] /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8006874: e008 b.n 8006888 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8006876: f7fd f9f3 bl 8003c60 800687a: 4602 mov r2, r0 800687c: 697b ldr r3, [r7, #20] 800687e: 1ad3 subs r3, r2, r3 8006880: 2b64 cmp r3, #100 ; 0x64 8006882: d901 bls.n 8006888 { return HAL_TIMEOUT; 8006884: 2303 movs r3, #3 8006886: e020 b.n 80068ca while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8006888: 4b12 ldr r3, [pc, #72] ; (80068d4 ) 800688a: 681b ldr r3, [r3, #0] 800688c: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8006890: 2b00 cmp r3, #0 8006892: d0f0 beq.n 8006876 8006894: e009 b.n 80068aa } } else { /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) 8006896: 4b0f ldr r3, [pc, #60] ; (80068d4 ) 8006898: 6adb ldr r3, [r3, #44] ; 0x2c 800689a: f403 4270 and.w r2, r3, #61440 ; 0xf000 800689e: 687b ldr r3, [r7, #4] 80068a0: 695b ldr r3, [r3, #20] 80068a2: 429a cmp r2, r3 80068a4: d001 beq.n 80068aa { return HAL_ERROR; 80068a6: 2301 movs r3, #1 80068a8: e00f b.n 80068ca #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 80068aa: 687b ldr r3, [r7, #4] 80068ac: 681b ldr r3, [r3, #0] 80068ae: f003 0310 and.w r3, r3, #16 80068b2: 2b00 cmp r3, #0 80068b4: d008 beq.n 80068c8 { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 80068b6: 4b07 ldr r3, [pc, #28] ; (80068d4 ) 80068b8: 685b ldr r3, [r3, #4] 80068ba: f423 0280 bic.w r2, r3, #4194304 ; 0x400000 80068be: 687b ldr r3, [r7, #4] 80068c0: 69db ldr r3, [r3, #28] 80068c2: 4904 ldr r1, [pc, #16] ; (80068d4 ) 80068c4: 4313 orrs r3, r2 80068c6: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 80068c8: 2300 movs r3, #0 } 80068ca: 4618 mov r0, r3 80068cc: 3720 adds r7, #32 80068ce: 46bd mov sp, r7 80068d0: bd80 pop {r7, pc} 80068d2: bf00 nop 80068d4: 40021000 .word 0x40021000 80068d8: 40007000 .word 0x40007000 80068dc: 42420440 .word 0x42420440 80068e0: 42420070 .word 0x42420070 080068e4 : * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 80068e4: b590 push {r4, r7, lr} 80068e6: b093 sub sp, #76 ; 0x4c 80068e8: af00 add r7, sp, #0 80068ea: 6078 str r0, [r7, #4] #if defined(STM32F105xC) || defined(STM32F107xC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; 80068ec: 4ba7 ldr r3, [pc, #668] ; (8006b8c ) 80068ee: f107 0418 add.w r4, r7, #24 80068f2: cb0f ldmia r3, {r0, r1, r2, r3} 80068f4: c407 stmia r4!, {r0, r1, r2} 80068f6: 8023 strh r3, [r4, #0] const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; 80068f8: 4ba5 ldr r3, [pc, #660] ; (8006b90 ) 80068fa: f107 0408 add.w r4, r7, #8 80068fe: cb0f ldmia r3, {r0, r1, r2, r3} 8006900: e884 000f stmia.w r4, {r0, r1, r2, r3} uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; 8006904: 2300 movs r3, #0 8006906: 63fb str r3, [r7, #60] ; 0x3c 8006908: 2300 movs r3, #0 800690a: 647b str r3, [r7, #68] ; 0x44 800690c: 2300 movs r3, #0 800690e: 63bb str r3, [r7, #56] ; 0x38 uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; 8006910: 2300 movs r3, #0 8006912: 637b str r3, [r7, #52] ; 0x34 8006914: 2300 movs r3, #0 8006916: 633b str r3, [r7, #48] ; 0x30 8006918: 2300 movs r3, #0 800691a: 62fb str r3, [r7, #44] ; 0x2c const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; const uint8_t aPredivFactorTable[2] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 800691c: 2300 movs r3, #0 800691e: 62bb str r3, [r7, #40] ; 0x28 8006920: 2300 movs r3, #0 8006922: 643b str r3, [r7, #64] ; 0x40 /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 8006924: 687b ldr r3, [r7, #4] 8006926: 3b01 subs r3, #1 8006928: 2b0f cmp r3, #15 800692a: f200 8121 bhi.w 8006b70 800692e: a201 add r2, pc, #4 ; (adr r2, 8006934 ) 8006930: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8006934: 08006af1 .word 0x08006af1 8006938: 08006b55 .word 0x08006b55 800693c: 08006b71 .word 0x08006b71 8006940: 08006a4f .word 0x08006a4f 8006944: 08006b71 .word 0x08006b71 8006948: 08006b71 .word 0x08006b71 800694c: 08006b71 .word 0x08006b71 8006950: 08006aa1 .word 0x08006aa1 8006954: 08006b71 .word 0x08006b71 8006958: 08006b71 .word 0x08006b71 800695c: 08006b71 .word 0x08006b71 8006960: 08006b71 .word 0x08006b71 8006964: 08006b71 .word 0x08006b71 8006968: 08006b71 .word 0x08006b71 800696c: 08006b71 .word 0x08006b71 8006970: 08006975 .word 0x08006975 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) case RCC_PERIPHCLK_USB: { /* Get RCC configuration ------------------------------------------------------*/ temp_reg = RCC->CFGR; 8006974: 4b87 ldr r3, [pc, #540] ; (8006b94 ) 8006976: 685b ldr r3, [r3, #4] 8006978: 62bb str r3, [r7, #40] ; 0x28 /* Check if PLL is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) 800697a: 4b86 ldr r3, [pc, #536] ; (8006b94 ) 800697c: 681b ldr r3, [r3, #0] 800697e: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 8006982: 2b00 cmp r3, #0 8006984: f000 80f6 beq.w 8006b74 { pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8006988: 6abb ldr r3, [r7, #40] ; 0x28 800698a: 0c9b lsrs r3, r3, #18 800698c: f003 030f and.w r3, r3, #15 8006990: 3348 adds r3, #72 ; 0x48 8006992: 443b add r3, r7 8006994: f813 3c30 ldrb.w r3, [r3, #-48] 8006998: 63bb str r3, [r7, #56] ; 0x38 if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 800699a: 6abb ldr r3, [r7, #40] ; 0x28 800699c: f403 3380 and.w r3, r3, #65536 ; 0x10000 80069a0: 2b00 cmp r3, #0 80069a2: d03d beq.n 8006a20 { #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ || defined(STM32F100xE) prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 80069a4: 4b7b ldr r3, [pc, #492] ; (8006b94 ) 80069a6: 6adb ldr r3, [r3, #44] ; 0x2c 80069a8: f003 030f and.w r3, r3, #15 80069ac: 3348 adds r3, #72 ; 0x48 80069ae: 443b add r3, r7 80069b0: f813 3c40 ldrb.w r3, [r3, #-64] 80069b4: 63fb str r3, [r7, #60] ; 0x3c #else prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) 80069b6: 4b77 ldr r3, [pc, #476] ; (8006b94 ) 80069b8: 6adb ldr r3, [r3, #44] ; 0x2c 80069ba: f403 3380 and.w r3, r3, #65536 ; 0x10000 80069be: 2b00 cmp r3, #0 80069c0: d01c beq.n 80069fc { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 80069c2: 4b74 ldr r3, [pc, #464] ; (8006b94 ) 80069c4: 6adb ldr r3, [r3, #44] ; 0x2c 80069c6: 091b lsrs r3, r3, #4 80069c8: f003 030f and.w r3, r3, #15 80069cc: 3301 adds r3, #1 80069ce: 62fb str r3, [r7, #44] ; 0x2c pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; 80069d0: 4b70 ldr r3, [pc, #448] ; (8006b94 ) 80069d2: 6adb ldr r3, [r3, #44] ; 0x2c 80069d4: 0a1b lsrs r3, r3, #8 80069d6: f003 030f and.w r3, r3, #15 80069da: 3302 adds r3, #2 80069dc: 637b str r3, [r7, #52] ; 0x34 pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); 80069de: 4a6e ldr r2, [pc, #440] ; (8006b98 ) 80069e0: 6afb ldr r3, [r7, #44] ; 0x2c 80069e2: fbb2 f3f3 udiv r3, r2, r3 80069e6: 6b7a ldr r2, [r7, #52] ; 0x34 80069e8: fb03 f202 mul.w r2, r3, r2 80069ec: 6bfb ldr r3, [r7, #60] ; 0x3c 80069ee: fbb2 f2f3 udiv r2, r2, r3 80069f2: 6bbb ldr r3, [r7, #56] ; 0x38 80069f4: fb02 f303 mul.w r3, r2, r3 80069f8: 647b str r3, [r7, #68] ; 0x44 80069fa: e007 b.n 8006a0c } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); 80069fc: 4a66 ldr r2, [pc, #408] ; (8006b98 ) 80069fe: 6bfb ldr r3, [r7, #60] ; 0x3c 8006a00: fbb2 f2f3 udiv r2, r2, r3 8006a04: 6bbb ldr r3, [r7, #56] ; 0x38 8006a06: fb02 f303 mul.w r3, r2, r3 8006a0a: 647b str r3, [r7, #68] ; 0x44 } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) 8006a0c: f897 3025 ldrb.w r3, [r7, #37] ; 0x25 8006a10: 461a mov r2, r3 8006a12: 6bbb ldr r3, [r7, #56] ; 0x38 8006a14: 4293 cmp r3, r2 8006a16: d108 bne.n 8006a2a { pllclk = pllclk / 2; 8006a18: 6c7b ldr r3, [r7, #68] ; 0x44 8006a1a: 085b lsrs r3, r3, #1 8006a1c: 647b str r3, [r7, #68] ; 0x44 8006a1e: e004 b.n 8006a2a #endif /* STM32F105xC || STM32F107xC */ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8006a20: 6bbb ldr r3, [r7, #56] ; 0x38 8006a22: 4a5e ldr r2, [pc, #376] ; (8006b9c ) 8006a24: fb02 f303 mul.w r3, r2, r3 8006a28: 647b str r3, [r7, #68] ; 0x44 } /* Calcul of the USB frequency*/ #if defined(STM32F105xC) || defined(STM32F107xC) /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) 8006a2a: 4b5a ldr r3, [pc, #360] ; (8006b94 ) 8006a2c: 685b ldr r3, [r3, #4] 8006a2e: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8006a32: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8006a36: d102 bne.n 8006a3e { /* Prescaler of 2 selected for USB */ frequency = pllclk; 8006a38: 6c7b ldr r3, [r7, #68] ; 0x44 8006a3a: 643b str r3, [r7, #64] ; 0x40 /* Prescaler of 1.5 selected for USB */ frequency = (pllclk * 2) / 3; } #endif } break; 8006a3c: e09a b.n 8006b74 frequency = (2 * pllclk) / 3; 8006a3e: 6c7b ldr r3, [r7, #68] ; 0x44 8006a40: 005b lsls r3, r3, #1 8006a42: 4a57 ldr r2, [pc, #348] ; (8006ba0 ) 8006a44: fba2 2303 umull r2, r3, r2, r3 8006a48: 085b lsrs r3, r3, #1 8006a4a: 643b str r3, [r7, #64] ; 0x40 break; 8006a4c: e092 b.n 8006b74 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) 8006a4e: 4b51 ldr r3, [pc, #324] ; (8006b94 ) 8006a50: 6adb ldr r3, [r3, #44] ; 0x2c 8006a52: f403 3300 and.w r3, r3, #131072 ; 0x20000 8006a56: 2b00 cmp r3, #0 8006a58: d103 bne.n 8006a62 { /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); 8006a5a: f7ff fce3 bl 8006424 8006a5e: 6438 str r0, [r7, #64] ; 0x40 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 8006a60: e08a b.n 8006b78 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8006a62: 4b4c ldr r3, [pc, #304] ; (8006b94 ) 8006a64: 681b ldr r3, [r3, #0] 8006a66: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8006a6a: 2b00 cmp r3, #0 8006a6c: f000 8084 beq.w 8006b78 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8006a70: 4b48 ldr r3, [pc, #288] ; (8006b94 ) 8006a72: 6adb ldr r3, [r3, #44] ; 0x2c 8006a74: 091b lsrs r3, r3, #4 8006a76: f003 030f and.w r3, r3, #15 8006a7a: 3301 adds r3, #1 8006a7c: 62fb str r3, [r7, #44] ; 0x2c pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 8006a7e: 4b45 ldr r3, [pc, #276] ; (8006b94 ) 8006a80: 6adb ldr r3, [r3, #44] ; 0x2c 8006a82: 0b1b lsrs r3, r3, #12 8006a84: f003 030f and.w r3, r3, #15 8006a88: 3302 adds r3, #2 8006a8a: 633b str r3, [r7, #48] ; 0x30 frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 8006a8c: 4a42 ldr r2, [pc, #264] ; (8006b98 ) 8006a8e: 6afb ldr r3, [r7, #44] ; 0x2c 8006a90: fbb2 f3f3 udiv r3, r2, r3 8006a94: 6b3a ldr r2, [r7, #48] ; 0x30 8006a96: fb02 f303 mul.w r3, r2, r3 8006a9a: 005b lsls r3, r3, #1 8006a9c: 643b str r3, [r7, #64] ; 0x40 break; 8006a9e: e06b b.n 8006b78 { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) 8006aa0: 4b3c ldr r3, [pc, #240] ; (8006b94 ) 8006aa2: 6adb ldr r3, [r3, #44] ; 0x2c 8006aa4: f403 2380 and.w r3, r3, #262144 ; 0x40000 8006aa8: 2b00 cmp r3, #0 8006aaa: d103 bne.n 8006ab4 { /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); 8006aac: f7ff fcba bl 8006424 8006ab0: 6438 str r0, [r7, #64] ; 0x40 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; 8006ab2: e063 b.n 8006b7c if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) 8006ab4: 4b37 ldr r3, [pc, #220] ; (8006b94 ) 8006ab6: 681b ldr r3, [r3, #0] 8006ab8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8006abc: 2b00 cmp r3, #0 8006abe: d05d beq.n 8006b7c prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; 8006ac0: 4b34 ldr r3, [pc, #208] ; (8006b94 ) 8006ac2: 6adb ldr r3, [r3, #44] ; 0x2c 8006ac4: 091b lsrs r3, r3, #4 8006ac6: f003 030f and.w r3, r3, #15 8006aca: 3301 adds r3, #1 8006acc: 62fb str r3, [r7, #44] ; 0x2c pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; 8006ace: 4b31 ldr r3, [pc, #196] ; (8006b94 ) 8006ad0: 6adb ldr r3, [r3, #44] ; 0x2c 8006ad2: 0b1b lsrs r3, r3, #12 8006ad4: f003 030f and.w r3, r3, #15 8006ad8: 3302 adds r3, #2 8006ada: 633b str r3, [r7, #48] ; 0x30 frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); 8006adc: 4a2e ldr r2, [pc, #184] ; (8006b98 ) 8006ade: 6afb ldr r3, [r7, #44] ; 0x2c 8006ae0: fbb2 f3f3 udiv r3, r2, r3 8006ae4: 6b3a ldr r2, [r7, #48] ; 0x30 8006ae6: fb02 f303 mul.w r3, r2, r3 8006aea: 005b lsls r3, r3, #1 8006aec: 643b str r3, [r7, #64] ; 0x40 break; 8006aee: e045 b.n 8006b7c } #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ case RCC_PERIPHCLK_RTC: { /* Get RCC BDCR configuration ------------------------------------------------------*/ temp_reg = RCC->BDCR; 8006af0: 4b28 ldr r3, [pc, #160] ; (8006b94 ) 8006af2: 6a1b ldr r3, [r3, #32] 8006af4: 62bb str r3, [r7, #40] ; 0x28 /* Check if LSE is ready if RTC clock selection is LSE */ if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 8006af6: 6abb ldr r3, [r7, #40] ; 0x28 8006af8: f403 7340 and.w r3, r3, #768 ; 0x300 8006afc: f5b3 7f80 cmp.w r3, #256 ; 0x100 8006b00: d108 bne.n 8006b14 8006b02: 6abb ldr r3, [r7, #40] ; 0x28 8006b04: f003 0302 and.w r3, r3, #2 8006b08: 2b00 cmp r3, #0 8006b0a: d003 beq.n 8006b14 { frequency = LSE_VALUE; 8006b0c: f44f 4300 mov.w r3, #32768 ; 0x8000 8006b10: 643b str r3, [r7, #64] ; 0x40 8006b12: e01e b.n 8006b52 } /* Check if LSI is ready if RTC clock selection is LSI */ else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 8006b14: 6abb ldr r3, [r7, #40] ; 0x28 8006b16: f403 7340 and.w r3, r3, #768 ; 0x300 8006b1a: f5b3 7f00 cmp.w r3, #512 ; 0x200 8006b1e: d109 bne.n 8006b34 8006b20: 4b1c ldr r3, [pc, #112] ; (8006b94 ) 8006b22: 6a5b ldr r3, [r3, #36] ; 0x24 8006b24: f003 0302 and.w r3, r3, #2 8006b28: 2b00 cmp r3, #0 8006b2a: d003 beq.n 8006b34 { frequency = LSI_VALUE; 8006b2c: f649 4340 movw r3, #40000 ; 0x9c40 8006b30: 643b str r3, [r7, #64] ; 0x40 8006b32: e00e b.n 8006b52 } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 8006b34: 6abb ldr r3, [r7, #40] ; 0x28 8006b36: f403 7340 and.w r3, r3, #768 ; 0x300 8006b3a: f5b3 7f40 cmp.w r3, #768 ; 0x300 8006b3e: d11f bne.n 8006b80 8006b40: 4b14 ldr r3, [pc, #80] ; (8006b94 ) 8006b42: 681b ldr r3, [r3, #0] 8006b44: f403 3300 and.w r3, r3, #131072 ; 0x20000 8006b48: 2b00 cmp r3, #0 8006b4a: d019 beq.n 8006b80 { frequency = HSE_VALUE / 128U; 8006b4c: 4b15 ldr r3, [pc, #84] ; (8006ba4 ) 8006b4e: 643b str r3, [r7, #64] ; 0x40 /* Clock not enabled for RTC*/ else { /* nothing to do: frequency already initialized to 0U */ } break; 8006b50: e016 b.n 8006b80 8006b52: e015 b.n 8006b80 } case RCC_PERIPHCLK_ADC: { frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 8006b54: f7ff fd62 bl 800661c 8006b58: 4602 mov r2, r0 8006b5a: 4b0e ldr r3, [pc, #56] ; (8006b94 ) 8006b5c: 685b ldr r3, [r3, #4] 8006b5e: 0b9b lsrs r3, r3, #14 8006b60: f003 0303 and.w r3, r3, #3 8006b64: 3301 adds r3, #1 8006b66: 005b lsls r3, r3, #1 8006b68: fbb2 f3f3 udiv r3, r2, r3 8006b6c: 643b str r3, [r7, #64] ; 0x40 break; 8006b6e: e008 b.n 8006b82 } default: { break; 8006b70: bf00 nop 8006b72: e006 b.n 8006b82 break; 8006b74: bf00 nop 8006b76: e004 b.n 8006b82 break; 8006b78: bf00 nop 8006b7a: e002 b.n 8006b82 break; 8006b7c: bf00 nop 8006b7e: e000 b.n 8006b82 break; 8006b80: bf00 nop } } return (frequency); 8006b82: 6c3b ldr r3, [r7, #64] ; 0x40 } 8006b84: 4618 mov r0, r3 8006b86: 374c adds r7, #76 ; 0x4c 8006b88: 46bd mov sp, r7 8006b8a: bd90 pop {r4, r7, pc} 8006b8c: 08008de4 .word 0x08008de4 8006b90: 08008df4 .word 0x08008df4 8006b94: 40021000 .word 0x40021000 8006b98: 017d7840 .word 0x017d7840 8006b9c: 003d0900 .word 0x003d0900 8006ba0: aaaaaaab .word 0xaaaaaaab 8006ba4: 0002faf0 .word 0x0002faf0 08006ba8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8006ba8: b580 push {r7, lr} 8006baa: b082 sub sp, #8 8006bac: af00 add r7, sp, #0 8006bae: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8006bb0: 687b ldr r3, [r7, #4] 8006bb2: 2b00 cmp r3, #0 8006bb4: d101 bne.n 8006bba { return HAL_ERROR; 8006bb6: 2301 movs r3, #1 8006bb8: e03f b.n 8006c3a assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 8006bba: 687b ldr r3, [r7, #4] 8006bbc: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8006bc0: b2db uxtb r3, r3 8006bc2: 2b00 cmp r3, #0 8006bc4: d106 bne.n 8006bd4 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8006bc6: 687b ldr r3, [r7, #4] 8006bc8: 2200 movs r2, #0 8006bca: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8006bce: 6878 ldr r0, [r7, #4] 8006bd0: f7fc ff66 bl 8003aa0 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8006bd4: 687b ldr r3, [r7, #4] 8006bd6: 2224 movs r2, #36 ; 0x24 8006bd8: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8006bdc: 687b ldr r3, [r7, #4] 8006bde: 681b ldr r3, [r3, #0] 8006be0: 68da ldr r2, [r3, #12] 8006be2: 687b ldr r3, [r7, #4] 8006be4: 681b ldr r3, [r3, #0] 8006be6: f422 5200 bic.w r2, r2, #8192 ; 0x2000 8006bea: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8006bec: 6878 ldr r0, [r7, #4] 8006bee: f000 fcad bl 800754c /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8006bf2: 687b ldr r3, [r7, #4] 8006bf4: 681b ldr r3, [r3, #0] 8006bf6: 691a ldr r2, [r3, #16] 8006bf8: 687b ldr r3, [r7, #4] 8006bfa: 681b ldr r3, [r3, #0] 8006bfc: f422 4290 bic.w r2, r2, #18432 ; 0x4800 8006c00: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8006c02: 687b ldr r3, [r7, #4] 8006c04: 681b ldr r3, [r3, #0] 8006c06: 695a ldr r2, [r3, #20] 8006c08: 687b ldr r3, [r7, #4] 8006c0a: 681b ldr r3, [r3, #0] 8006c0c: f022 022a bic.w r2, r2, #42 ; 0x2a 8006c10: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8006c12: 687b ldr r3, [r7, #4] 8006c14: 681b ldr r3, [r3, #0] 8006c16: 68da ldr r2, [r3, #12] 8006c18: 687b ldr r3, [r7, #4] 8006c1a: 681b ldr r3, [r3, #0] 8006c1c: f442 5200 orr.w r2, r2, #8192 ; 0x2000 8006c20: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8006c22: 687b ldr r3, [r7, #4] 8006c24: 2200 movs r2, #0 8006c26: 641a str r2, [r3, #64] ; 0x40 huart->gState = HAL_UART_STATE_READY; 8006c28: 687b ldr r3, [r7, #4] 8006c2a: 2220 movs r2, #32 8006c2c: f883 203d strb.w r2, [r3, #61] ; 0x3d huart->RxState = HAL_UART_STATE_READY; 8006c30: 687b ldr r3, [r7, #4] 8006c32: 2220 movs r2, #32 8006c34: f883 203e strb.w r2, [r3, #62] ; 0x3e return HAL_OK; 8006c38: 2300 movs r3, #0 } 8006c3a: 4618 mov r0, r3 8006c3c: 3708 adds r7, #8 8006c3e: 46bd mov sp, r7 8006c40: bd80 pop {r7, pc} 08006c42 : * @param Size Amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8006c42: b580 push {r7, lr} 8006c44: b08a sub sp, #40 ; 0x28 8006c46: af02 add r7, sp, #8 8006c48: 60f8 str r0, [r7, #12] 8006c4a: 60b9 str r1, [r7, #8] 8006c4c: 603b str r3, [r7, #0] 8006c4e: 4613 mov r3, r2 8006c50: 80fb strh r3, [r7, #6] uint8_t *pdata8bits; uint16_t *pdata16bits; uint32_t tickstart = 0U; 8006c52: 2300 movs r3, #0 8006c54: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8006c56: 68fb ldr r3, [r7, #12] 8006c58: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8006c5c: b2db uxtb r3, r3 8006c5e: 2b20 cmp r3, #32 8006c60: d17c bne.n 8006d5c { if ((pData == NULL) || (Size == 0U)) 8006c62: 68bb ldr r3, [r7, #8] 8006c64: 2b00 cmp r3, #0 8006c66: d002 beq.n 8006c6e 8006c68: 88fb ldrh r3, [r7, #6] 8006c6a: 2b00 cmp r3, #0 8006c6c: d101 bne.n 8006c72 { return HAL_ERROR; 8006c6e: 2301 movs r3, #1 8006c70: e075 b.n 8006d5e } /* Process Locked */ __HAL_LOCK(huart); 8006c72: 68fb ldr r3, [r7, #12] 8006c74: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8006c78: 2b01 cmp r3, #1 8006c7a: d101 bne.n 8006c80 8006c7c: 2302 movs r3, #2 8006c7e: e06e b.n 8006d5e 8006c80: 68fb ldr r3, [r7, #12] 8006c82: 2201 movs r2, #1 8006c84: f883 203c strb.w r2, [r3, #60] ; 0x3c huart->ErrorCode = HAL_UART_ERROR_NONE; 8006c88: 68fb ldr r3, [r7, #12] 8006c8a: 2200 movs r2, #0 8006c8c: 641a str r2, [r3, #64] ; 0x40 huart->gState = HAL_UART_STATE_BUSY_TX; 8006c8e: 68fb ldr r3, [r7, #12] 8006c90: 2221 movs r2, #33 ; 0x21 8006c92: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8006c96: f7fc ffe3 bl 8003c60 8006c9a: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 8006c9c: 68fb ldr r3, [r7, #12] 8006c9e: 88fa ldrh r2, [r7, #6] 8006ca0: 849a strh r2, [r3, #36] ; 0x24 huart->TxXferCount = Size; 8006ca2: 68fb ldr r3, [r7, #12] 8006ca4: 88fa ldrh r2, [r7, #6] 8006ca6: 84da strh r2, [r3, #38] ; 0x26 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8006ca8: 68fb ldr r3, [r7, #12] 8006caa: 689b ldr r3, [r3, #8] 8006cac: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8006cb0: d108 bne.n 8006cc4 8006cb2: 68fb ldr r3, [r7, #12] 8006cb4: 691b ldr r3, [r3, #16] 8006cb6: 2b00 cmp r3, #0 8006cb8: d104 bne.n 8006cc4 { pdata8bits = NULL; 8006cba: 2300 movs r3, #0 8006cbc: 61fb str r3, [r7, #28] pdata16bits = (uint16_t *) pData; 8006cbe: 68bb ldr r3, [r7, #8] 8006cc0: 61bb str r3, [r7, #24] 8006cc2: e003 b.n 8006ccc } else { pdata8bits = pData; 8006cc4: 68bb ldr r3, [r7, #8] 8006cc6: 61fb str r3, [r7, #28] pdata16bits = NULL; 8006cc8: 2300 movs r3, #0 8006cca: 61bb str r3, [r7, #24] } /* Process Unlocked */ __HAL_UNLOCK(huart); 8006ccc: 68fb ldr r3, [r7, #12] 8006cce: 2200 movs r2, #0 8006cd0: f883 203c strb.w r2, [r3, #60] ; 0x3c while (huart->TxXferCount > 0U) 8006cd4: e02a b.n 8006d2c { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8006cd6: 683b ldr r3, [r7, #0] 8006cd8: 9300 str r3, [sp, #0] 8006cda: 697b ldr r3, [r7, #20] 8006cdc: 2200 movs r2, #0 8006cde: 2180 movs r1, #128 ; 0x80 8006ce0: 68f8 ldr r0, [r7, #12] 8006ce2: f000 fa5f bl 80071a4 8006ce6: 4603 mov r3, r0 8006ce8: 2b00 cmp r3, #0 8006cea: d001 beq.n 8006cf0 { return HAL_TIMEOUT; 8006cec: 2303 movs r3, #3 8006cee: e036 b.n 8006d5e } if (pdata8bits == NULL) 8006cf0: 69fb ldr r3, [r7, #28] 8006cf2: 2b00 cmp r3, #0 8006cf4: d10b bne.n 8006d0e { huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); 8006cf6: 69bb ldr r3, [r7, #24] 8006cf8: 881b ldrh r3, [r3, #0] 8006cfa: 461a mov r2, r3 8006cfc: 68fb ldr r3, [r7, #12] 8006cfe: 681b ldr r3, [r3, #0] 8006d00: f3c2 0208 ubfx r2, r2, #0, #9 8006d04: 605a str r2, [r3, #4] pdata16bits++; 8006d06: 69bb ldr r3, [r7, #24] 8006d08: 3302 adds r3, #2 8006d0a: 61bb str r3, [r7, #24] 8006d0c: e007 b.n 8006d1e } else { huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); 8006d0e: 69fb ldr r3, [r7, #28] 8006d10: 781a ldrb r2, [r3, #0] 8006d12: 68fb ldr r3, [r7, #12] 8006d14: 681b ldr r3, [r3, #0] 8006d16: 605a str r2, [r3, #4] pdata8bits++; 8006d18: 69fb ldr r3, [r7, #28] 8006d1a: 3301 adds r3, #1 8006d1c: 61fb str r3, [r7, #28] } huart->TxXferCount--; 8006d1e: 68fb ldr r3, [r7, #12] 8006d20: 8cdb ldrh r3, [r3, #38] ; 0x26 8006d22: b29b uxth r3, r3 8006d24: 3b01 subs r3, #1 8006d26: b29a uxth r2, r3 8006d28: 68fb ldr r3, [r7, #12] 8006d2a: 84da strh r2, [r3, #38] ; 0x26 while (huart->TxXferCount > 0U) 8006d2c: 68fb ldr r3, [r7, #12] 8006d2e: 8cdb ldrh r3, [r3, #38] ; 0x26 8006d30: b29b uxth r3, r3 8006d32: 2b00 cmp r3, #0 8006d34: d1cf bne.n 8006cd6 } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 8006d36: 683b ldr r3, [r7, #0] 8006d38: 9300 str r3, [sp, #0] 8006d3a: 697b ldr r3, [r7, #20] 8006d3c: 2200 movs r2, #0 8006d3e: 2140 movs r1, #64 ; 0x40 8006d40: 68f8 ldr r0, [r7, #12] 8006d42: f000 fa2f bl 80071a4 8006d46: 4603 mov r3, r0 8006d48: 2b00 cmp r3, #0 8006d4a: d001 beq.n 8006d50 { return HAL_TIMEOUT; 8006d4c: 2303 movs r3, #3 8006d4e: e006 b.n 8006d5e } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8006d50: 68fb ldr r3, [r7, #12] 8006d52: 2220 movs r2, #32 8006d54: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 8006d58: 2300 movs r3, #0 8006d5a: e000 b.n 8006d5e } else { return HAL_BUSY; 8006d5c: 2302 movs r3, #2 } } 8006d5e: 4618 mov r0, r3 8006d60: 3720 adds r7, #32 8006d62: 46bd mov sp, r7 8006d64: bd80 pop {r7, pc} 08006d66 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8006d66: b580 push {r7, lr} 8006d68: b086 sub sp, #24 8006d6a: af00 add r7, sp, #0 8006d6c: 60f8 str r0, [r7, #12] 8006d6e: 60b9 str r1, [r7, #8] 8006d70: 4613 mov r3, r2 8006d72: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8006d74: 68fb ldr r3, [r7, #12] 8006d76: f893 303e ldrb.w r3, [r3, #62] ; 0x3e 8006d7a: b2db uxtb r3, r3 8006d7c: 2b20 cmp r3, #32 8006d7e: d13c bne.n 8006dfa { if ((pData == NULL) || (Size == 0U)) 8006d80: 68bb ldr r3, [r7, #8] 8006d82: 2b00 cmp r3, #0 8006d84: d002 beq.n 8006d8c 8006d86: 88fb ldrh r3, [r7, #6] 8006d88: 2b00 cmp r3, #0 8006d8a: d101 bne.n 8006d90 { return HAL_ERROR; 8006d8c: 2301 movs r3, #1 8006d8e: e035 b.n 8006dfc } __HAL_LOCK(huart); 8006d90: 68fb ldr r3, [r7, #12] 8006d92: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8006d96: 2b01 cmp r3, #1 8006d98: d101 bne.n 8006d9e 8006d9a: 2302 movs r3, #2 8006d9c: e02e b.n 8006dfc 8006d9e: 68fb ldr r3, [r7, #12] 8006da0: 2201 movs r2, #1 8006da2: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8006da6: 68fb ldr r3, [r7, #12] 8006da8: 2201 movs r2, #1 8006daa: 631a str r2, [r3, #48] ; 0x30 status = UART_Start_Receive_IT(huart, pData, Size); 8006dac: 88fb ldrh r3, [r7, #6] 8006dae: 461a mov r2, r3 8006db0: 68b9 ldr r1, [r7, #8] 8006db2: 68f8 ldr r0, [r7, #12] 8006db4: f000 fa40 bl 8007238 8006db8: 4603 mov r3, r0 8006dba: 75fb strb r3, [r7, #23] /* Check Rx process has been successfully started */ if (status == HAL_OK) 8006dbc: 7dfb ldrb r3, [r7, #23] 8006dbe: 2b00 cmp r3, #0 8006dc0: d119 bne.n 8006df6 { if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006dc2: 68fb ldr r3, [r7, #12] 8006dc4: 6b1b ldr r3, [r3, #48] ; 0x30 8006dc6: 2b01 cmp r3, #1 8006dc8: d113 bne.n 8006df2 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8006dca: 2300 movs r3, #0 8006dcc: 613b str r3, [r7, #16] 8006dce: 68fb ldr r3, [r7, #12] 8006dd0: 681b ldr r3, [r3, #0] 8006dd2: 681b ldr r3, [r3, #0] 8006dd4: 613b str r3, [r7, #16] 8006dd6: 68fb ldr r3, [r7, #12] 8006dd8: 681b ldr r3, [r3, #0] 8006dda: 685b ldr r3, [r3, #4] 8006ddc: 613b str r3, [r7, #16] 8006dde: 693b ldr r3, [r7, #16] SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006de0: 68fb ldr r3, [r7, #12] 8006de2: 681b ldr r3, [r3, #0] 8006de4: 68da ldr r2, [r3, #12] 8006de6: 68fb ldr r3, [r7, #12] 8006de8: 681b ldr r3, [r3, #0] 8006dea: f042 0210 orr.w r2, r2, #16 8006dee: 60da str r2, [r3, #12] 8006df0: e001 b.n 8006df6 { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8006df2: 2301 movs r3, #1 8006df4: 75fb strb r3, [r7, #23] } } return status; 8006df6: 7dfb ldrb r3, [r7, #23] 8006df8: e000 b.n 8006dfc } else { return HAL_BUSY; 8006dfa: 2302 movs r3, #2 } } 8006dfc: 4618 mov r0, r3 8006dfe: 3718 adds r7, #24 8006e00: 46bd mov sp, r7 8006e02: bd80 pop {r7, pc} 08006e04 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8006e04: b580 push {r7, lr} 8006e06: b08a sub sp, #40 ; 0x28 8006e08: af00 add r7, sp, #0 8006e0a: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 8006e0c: 687b ldr r3, [r7, #4] 8006e0e: 681b ldr r3, [r3, #0] 8006e10: 681b ldr r3, [r3, #0] 8006e12: 627b str r3, [r7, #36] ; 0x24 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8006e14: 687b ldr r3, [r7, #4] 8006e16: 681b ldr r3, [r3, #0] 8006e18: 68db ldr r3, [r3, #12] 8006e1a: 623b str r3, [r7, #32] uint32_t cr3its = READ_REG(huart->Instance->CR3); 8006e1c: 687b ldr r3, [r7, #4] 8006e1e: 681b ldr r3, [r3, #0] 8006e20: 695b ldr r3, [r3, #20] 8006e22: 61fb str r3, [r7, #28] uint32_t errorflags = 0x00U; 8006e24: 2300 movs r3, #0 8006e26: 61bb str r3, [r7, #24] uint32_t dmarequest = 0x00U; 8006e28: 2300 movs r3, #0 8006e2a: 617b str r3, [r7, #20] /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 8006e2c: 6a7b ldr r3, [r7, #36] ; 0x24 8006e2e: f003 030f and.w r3, r3, #15 8006e32: 61bb str r3, [r7, #24] if (errorflags == RESET) 8006e34: 69bb ldr r3, [r7, #24] 8006e36: 2b00 cmp r3, #0 8006e38: d10d bne.n 8006e56 { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8006e3a: 6a7b ldr r3, [r7, #36] ; 0x24 8006e3c: f003 0320 and.w r3, r3, #32 8006e40: 2b00 cmp r3, #0 8006e42: d008 beq.n 8006e56 8006e44: 6a3b ldr r3, [r7, #32] 8006e46: f003 0320 and.w r3, r3, #32 8006e4a: 2b00 cmp r3, #0 8006e4c: d003 beq.n 8006e56 { UART_Receive_IT(huart); 8006e4e: 6878 ldr r0, [r7, #4] 8006e50: f000 fad2 bl 80073f8 return; 8006e54: e17b b.n 800714e } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 8006e56: 69bb ldr r3, [r7, #24] 8006e58: 2b00 cmp r3, #0 8006e5a: f000 80b1 beq.w 8006fc0 8006e5e: 69fb ldr r3, [r7, #28] 8006e60: f003 0301 and.w r3, r3, #1 8006e64: 2b00 cmp r3, #0 8006e66: d105 bne.n 8006e74 8006e68: 6a3b ldr r3, [r7, #32] 8006e6a: f403 7390 and.w r3, r3, #288 ; 0x120 8006e6e: 2b00 cmp r3, #0 8006e70: f000 80a6 beq.w 8006fc0 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 8006e74: 6a7b ldr r3, [r7, #36] ; 0x24 8006e76: f003 0301 and.w r3, r3, #1 8006e7a: 2b00 cmp r3, #0 8006e7c: d00a beq.n 8006e94 8006e7e: 6a3b ldr r3, [r7, #32] 8006e80: f403 7380 and.w r3, r3, #256 ; 0x100 8006e84: 2b00 cmp r3, #0 8006e86: d005 beq.n 8006e94 { huart->ErrorCode |= HAL_UART_ERROR_PE; 8006e88: 687b ldr r3, [r7, #4] 8006e8a: 6c1b ldr r3, [r3, #64] ; 0x40 8006e8c: f043 0201 orr.w r2, r3, #1 8006e90: 687b ldr r3, [r7, #4] 8006e92: 641a str r2, [r3, #64] ; 0x40 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8006e94: 6a7b ldr r3, [r7, #36] ; 0x24 8006e96: f003 0304 and.w r3, r3, #4 8006e9a: 2b00 cmp r3, #0 8006e9c: d00a beq.n 8006eb4 8006e9e: 69fb ldr r3, [r7, #28] 8006ea0: f003 0301 and.w r3, r3, #1 8006ea4: 2b00 cmp r3, #0 8006ea6: d005 beq.n 8006eb4 { huart->ErrorCode |= HAL_UART_ERROR_NE; 8006ea8: 687b ldr r3, [r7, #4] 8006eaa: 6c1b ldr r3, [r3, #64] ; 0x40 8006eac: f043 0202 orr.w r2, r3, #2 8006eb0: 687b ldr r3, [r7, #4] 8006eb2: 641a str r2, [r3, #64] ; 0x40 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8006eb4: 6a7b ldr r3, [r7, #36] ; 0x24 8006eb6: f003 0302 and.w r3, r3, #2 8006eba: 2b00 cmp r3, #0 8006ebc: d00a beq.n 8006ed4 8006ebe: 69fb ldr r3, [r7, #28] 8006ec0: f003 0301 and.w r3, r3, #1 8006ec4: 2b00 cmp r3, #0 8006ec6: d005 beq.n 8006ed4 { huart->ErrorCode |= HAL_UART_ERROR_FE; 8006ec8: 687b ldr r3, [r7, #4] 8006eca: 6c1b ldr r3, [r3, #64] ; 0x40 8006ecc: f043 0204 orr.w r2, r3, #4 8006ed0: 687b ldr r3, [r7, #4] 8006ed2: 641a str r2, [r3, #64] ; 0x40 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) 8006ed4: 6a7b ldr r3, [r7, #36] ; 0x24 8006ed6: f003 0308 and.w r3, r3, #8 8006eda: 2b00 cmp r3, #0 8006edc: d00f beq.n 8006efe 8006ede: 6a3b ldr r3, [r7, #32] 8006ee0: f003 0320 and.w r3, r3, #32 8006ee4: 2b00 cmp r3, #0 8006ee6: d104 bne.n 8006ef2 8006ee8: 69fb ldr r3, [r7, #28] 8006eea: f003 0301 and.w r3, r3, #1 8006eee: 2b00 cmp r3, #0 8006ef0: d005 beq.n 8006efe { huart->ErrorCode |= HAL_UART_ERROR_ORE; 8006ef2: 687b ldr r3, [r7, #4] 8006ef4: 6c1b ldr r3, [r3, #64] ; 0x40 8006ef6: f043 0208 orr.w r2, r3, #8 8006efa: 687b ldr r3, [r7, #4] 8006efc: 641a str r2, [r3, #64] ; 0x40 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8006efe: 687b ldr r3, [r7, #4] 8006f00: 6c1b ldr r3, [r3, #64] ; 0x40 8006f02: 2b00 cmp r3, #0 8006f04: f000 811e beq.w 8007144 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8006f08: 6a7b ldr r3, [r7, #36] ; 0x24 8006f0a: f003 0320 and.w r3, r3, #32 8006f0e: 2b00 cmp r3, #0 8006f10: d007 beq.n 8006f22 8006f12: 6a3b ldr r3, [r7, #32] 8006f14: f003 0320 and.w r3, r3, #32 8006f18: 2b00 cmp r3, #0 8006f1a: d002 beq.n 8006f22 { UART_Receive_IT(huart); 8006f1c: 6878 ldr r0, [r7, #4] 8006f1e: f000 fa6b bl 80073f8 } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8006f22: 687b ldr r3, [r7, #4] 8006f24: 681b ldr r3, [r3, #0] 8006f26: 695b ldr r3, [r3, #20] 8006f28: f003 0340 and.w r3, r3, #64 ; 0x40 8006f2c: 2b00 cmp r3, #0 8006f2e: bf14 ite ne 8006f30: 2301 movne r3, #1 8006f32: 2300 moveq r3, #0 8006f34: b2db uxtb r3, r3 8006f36: 617b str r3, [r7, #20] if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 8006f38: 687b ldr r3, [r7, #4] 8006f3a: 6c1b ldr r3, [r3, #64] ; 0x40 8006f3c: f003 0308 and.w r3, r3, #8 8006f40: 2b00 cmp r3, #0 8006f42: d102 bne.n 8006f4a 8006f44: 697b ldr r3, [r7, #20] 8006f46: 2b00 cmp r3, #0 8006f48: d031 beq.n 8006fae { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8006f4a: 6878 ldr r0, [r7, #4] 8006f4c: f000 f9ad bl 80072aa /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006f50: 687b ldr r3, [r7, #4] 8006f52: 681b ldr r3, [r3, #0] 8006f54: 695b ldr r3, [r3, #20] 8006f56: f003 0340 and.w r3, r3, #64 ; 0x40 8006f5a: 2b00 cmp r3, #0 8006f5c: d023 beq.n 8006fa6 { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8006f5e: 687b ldr r3, [r7, #4] 8006f60: 681b ldr r3, [r3, #0] 8006f62: 695a ldr r2, [r3, #20] 8006f64: 687b ldr r3, [r7, #4] 8006f66: 681b ldr r3, [r3, #0] 8006f68: f022 0240 bic.w r2, r2, #64 ; 0x40 8006f6c: 615a str r2, [r3, #20] /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 8006f6e: 687b ldr r3, [r7, #4] 8006f70: 6b9b ldr r3, [r3, #56] ; 0x38 8006f72: 2b00 cmp r3, #0 8006f74: d013 beq.n 8006f9e { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8006f76: 687b ldr r3, [r7, #4] 8006f78: 6b9b ldr r3, [r3, #56] ; 0x38 8006f7a: 4a76 ldr r2, [pc, #472] ; (8007154 ) 8006f7c: 635a str r2, [r3, #52] ; 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8006f7e: 687b ldr r3, [r7, #4] 8006f80: 6b9b ldr r3, [r3, #56] ; 0x38 8006f82: 4618 mov r0, r3 8006f84: f7fe fb92 bl 80056ac 8006f88: 4603 mov r3, r0 8006f8a: 2b00 cmp r3, #0 8006f8c: d016 beq.n 8006fbc { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8006f8e: 687b ldr r3, [r7, #4] 8006f90: 6b9b ldr r3, [r3, #56] ; 0x38 8006f92: 6b5b ldr r3, [r3, #52] ; 0x34 8006f94: 687a ldr r2, [r7, #4] 8006f96: 6b92 ldr r2, [r2, #56] ; 0x38 8006f98: 4610 mov r0, r2 8006f9a: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006f9c: e00e b.n 8006fbc #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006f9e: 6878 ldr r0, [r7, #4] 8006fa0: f000 f8ec bl 800717c if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006fa4: e00a b.n 8006fbc #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006fa6: 6878 ldr r0, [r7, #4] 8006fa8: f000 f8e8 bl 800717c if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006fac: e006 b.n 8006fbc #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006fae: 6878 ldr r0, [r7, #4] 8006fb0: f000 f8e4 bl 800717c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8006fb4: 687b ldr r3, [r7, #4] 8006fb6: 2200 movs r2, #0 8006fb8: 641a str r2, [r3, #64] ; 0x40 } } return; 8006fba: e0c3 b.n 8007144 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006fbc: bf00 nop return; 8006fbe: e0c1 b.n 8007144 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006fc0: 687b ldr r3, [r7, #4] 8006fc2: 6b1b ldr r3, [r3, #48] ; 0x30 8006fc4: 2b01 cmp r3, #1 8006fc6: f040 80a1 bne.w 800710c &&((isrflags & USART_SR_IDLE) != 0U) 8006fca: 6a7b ldr r3, [r7, #36] ; 0x24 8006fcc: f003 0310 and.w r3, r3, #16 8006fd0: 2b00 cmp r3, #0 8006fd2: f000 809b beq.w 800710c &&((cr1its & USART_SR_IDLE) != 0U)) 8006fd6: 6a3b ldr r3, [r7, #32] 8006fd8: f003 0310 and.w r3, r3, #16 8006fdc: 2b00 cmp r3, #0 8006fde: f000 8095 beq.w 800710c { __HAL_UART_CLEAR_IDLEFLAG(huart); 8006fe2: 2300 movs r3, #0 8006fe4: 60fb str r3, [r7, #12] 8006fe6: 687b ldr r3, [r7, #4] 8006fe8: 681b ldr r3, [r3, #0] 8006fea: 681b ldr r3, [r3, #0] 8006fec: 60fb str r3, [r7, #12] 8006fee: 687b ldr r3, [r7, #4] 8006ff0: 681b ldr r3, [r3, #0] 8006ff2: 685b ldr r3, [r3, #4] 8006ff4: 60fb str r3, [r7, #12] 8006ff6: 68fb ldr r3, [r7, #12] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006ff8: 687b ldr r3, [r7, #4] 8006ffa: 681b ldr r3, [r3, #0] 8006ffc: 695b ldr r3, [r3, #20] 8006ffe: f003 0340 and.w r3, r3, #64 ; 0x40 8007002: 2b00 cmp r3, #0 8007004: d04e beq.n 80070a4 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8007006: 687b ldr r3, [r7, #4] 8007008: 6b9b ldr r3, [r3, #56] ; 0x38 800700a: 681b ldr r3, [r3, #0] 800700c: 685b ldr r3, [r3, #4] 800700e: 823b strh r3, [r7, #16] if ( (nb_remaining_rx_data > 0U) 8007010: 8a3b ldrh r3, [r7, #16] 8007012: 2b00 cmp r3, #0 8007014: f000 8098 beq.w 8007148 &&(nb_remaining_rx_data < huart->RxXferSize)) 8007018: 687b ldr r3, [r7, #4] 800701a: 8d9b ldrh r3, [r3, #44] ; 0x2c 800701c: 8a3a ldrh r2, [r7, #16] 800701e: 429a cmp r2, r3 8007020: f080 8092 bcs.w 8007148 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8007024: 687b ldr r3, [r7, #4] 8007026: 8a3a ldrh r2, [r7, #16] 8007028: 85da strh r2, [r3, #46] ; 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 800702a: 687b ldr r3, [r7, #4] 800702c: 6b9b ldr r3, [r3, #56] ; 0x38 800702e: 699b ldr r3, [r3, #24] 8007030: 2b20 cmp r3, #32 8007032: d02b beq.n 800708c { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8007034: 687b ldr r3, [r7, #4] 8007036: 681b ldr r3, [r3, #0] 8007038: 68da ldr r2, [r3, #12] 800703a: 687b ldr r3, [r7, #4] 800703c: 681b ldr r3, [r3, #0] 800703e: f422 7280 bic.w r2, r2, #256 ; 0x100 8007042: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8007044: 687b ldr r3, [r7, #4] 8007046: 681b ldr r3, [r3, #0] 8007048: 695a ldr r2, [r3, #20] 800704a: 687b ldr r3, [r7, #4] 800704c: 681b ldr r3, [r3, #0] 800704e: f022 0201 bic.w r2, r2, #1 8007052: 615a str r2, [r3, #20] /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8007054: 687b ldr r3, [r7, #4] 8007056: 681b ldr r3, [r3, #0] 8007058: 695a ldr r2, [r3, #20] 800705a: 687b ldr r3, [r7, #4] 800705c: 681b ldr r3, [r3, #0] 800705e: f022 0240 bic.w r2, r2, #64 ; 0x40 8007062: 615a str r2, [r3, #20] /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8007064: 687b ldr r3, [r7, #4] 8007066: 2220 movs r2, #32 8007068: f883 203e strb.w r2, [r3, #62] ; 0x3e huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800706c: 687b ldr r3, [r7, #4] 800706e: 2200 movs r2, #0 8007070: 631a str r2, [r3, #48] ; 0x30 CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8007072: 687b ldr r3, [r7, #4] 8007074: 681b ldr r3, [r3, #0] 8007076: 68da ldr r2, [r3, #12] 8007078: 687b ldr r3, [r7, #4] 800707a: 681b ldr r3, [r3, #0] 800707c: f022 0210 bic.w r2, r2, #16 8007080: 60da str r2, [r3, #12] /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8007082: 687b ldr r3, [r7, #4] 8007084: 6b9b ldr r3, [r3, #56] ; 0x38 8007086: 4618 mov r0, r3 8007088: f7fe fad5 bl 8005636 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 800708c: 687b ldr r3, [r7, #4] 800708e: 8d9a ldrh r2, [r3, #44] ; 0x2c 8007090: 687b ldr r3, [r7, #4] 8007092: 8ddb ldrh r3, [r3, #46] ; 0x2e 8007094: b29b uxth r3, r3 8007096: 1ad3 subs r3, r2, r3 8007098: b29b uxth r3, r3 800709a: 4619 mov r1, r3 800709c: 6878 ldr r0, [r7, #4] 800709e: f000 f876 bl 800718e #endif } return; 80070a2: e051 b.n 8007148 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 80070a4: 687b ldr r3, [r7, #4] 80070a6: 8d9a ldrh r2, [r3, #44] ; 0x2c 80070a8: 687b ldr r3, [r7, #4] 80070aa: 8ddb ldrh r3, [r3, #46] ; 0x2e 80070ac: b29b uxth r3, r3 80070ae: 1ad3 subs r3, r2, r3 80070b0: 827b strh r3, [r7, #18] if ( (huart->RxXferCount > 0U) 80070b2: 687b ldr r3, [r7, #4] 80070b4: 8ddb ldrh r3, [r3, #46] ; 0x2e 80070b6: b29b uxth r3, r3 80070b8: 2b00 cmp r3, #0 80070ba: d047 beq.n 800714c &&(nb_rx_data > 0U) ) 80070bc: 8a7b ldrh r3, [r7, #18] 80070be: 2b00 cmp r3, #0 80070c0: d044 beq.n 800714c { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 80070c2: 687b ldr r3, [r7, #4] 80070c4: 681b ldr r3, [r3, #0] 80070c6: 68da ldr r2, [r3, #12] 80070c8: 687b ldr r3, [r7, #4] 80070ca: 681b ldr r3, [r3, #0] 80070cc: f422 7290 bic.w r2, r2, #288 ; 0x120 80070d0: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80070d2: 687b ldr r3, [r7, #4] 80070d4: 681b ldr r3, [r3, #0] 80070d6: 695a ldr r2, [r3, #20] 80070d8: 687b ldr r3, [r7, #4] 80070da: 681b ldr r3, [r3, #0] 80070dc: f022 0201 bic.w r2, r2, #1 80070e0: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80070e2: 687b ldr r3, [r7, #4] 80070e4: 2220 movs r2, #32 80070e6: f883 203e strb.w r2, [r3, #62] ; 0x3e huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80070ea: 687b ldr r3, [r7, #4] 80070ec: 2200 movs r2, #0 80070ee: 631a str r2, [r3, #48] ; 0x30 CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80070f0: 687b ldr r3, [r7, #4] 80070f2: 681b ldr r3, [r3, #0] 80070f4: 68da ldr r2, [r3, #12] 80070f6: 687b ldr r3, [r7, #4] 80070f8: 681b ldr r3, [r3, #0] 80070fa: f022 0210 bic.w r2, r2, #16 80070fe: 60da str r2, [r3, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8007100: 8a7b ldrh r3, [r7, #18] 8007102: 4619 mov r1, r3 8007104: 6878 ldr r0, [r7, #4] 8007106: f000 f842 bl 800718e #endif } return; 800710a: e01f b.n 800714c } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 800710c: 6a7b ldr r3, [r7, #36] ; 0x24 800710e: f003 0380 and.w r3, r3, #128 ; 0x80 8007112: 2b00 cmp r3, #0 8007114: d008 beq.n 8007128 8007116: 6a3b ldr r3, [r7, #32] 8007118: f003 0380 and.w r3, r3, #128 ; 0x80 800711c: 2b00 cmp r3, #0 800711e: d003 beq.n 8007128 { UART_Transmit_IT(huart); 8007120: 6878 ldr r0, [r7, #4] 8007122: f000 f902 bl 800732a return; 8007126: e012 b.n 800714e } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8007128: 6a7b ldr r3, [r7, #36] ; 0x24 800712a: f003 0340 and.w r3, r3, #64 ; 0x40 800712e: 2b00 cmp r3, #0 8007130: d00d beq.n 800714e 8007132: 6a3b ldr r3, [r7, #32] 8007134: f003 0340 and.w r3, r3, #64 ; 0x40 8007138: 2b00 cmp r3, #0 800713a: d008 beq.n 800714e { UART_EndTransmit_IT(huart); 800713c: 6878 ldr r0, [r7, #4] 800713e: f000 f943 bl 80073c8 return; 8007142: e004 b.n 800714e return; 8007144: bf00 nop 8007146: e002 b.n 800714e return; 8007148: bf00 nop 800714a: e000 b.n 800714e return; 800714c: bf00 nop } } 800714e: 3728 adds r7, #40 ; 0x28 8007150: 46bd mov sp, r7 8007152: bd80 pop {r7, pc} 8007154: 08007303 .word 0x08007303 08007158 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 8007158: b480 push {r7} 800715a: b083 sub sp, #12 800715c: af00 add r7, sp, #0 800715e: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback could be implemented in the user file */ } 8007160: bf00 nop 8007162: 370c adds r7, #12 8007164: 46bd mov sp, r7 8007166: bc80 pop {r7} 8007168: 4770 bx lr 0800716a : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 800716a: b480 push {r7} 800716c: b083 sub sp, #12 800716e: af00 add r7, sp, #0 8007170: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback could be implemented in the user file */ } 8007172: bf00 nop 8007174: 370c adds r7, #12 8007176: 46bd mov sp, r7 8007178: bc80 pop {r7} 800717a: 4770 bx lr 0800717c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 800717c: b480 push {r7} 800717e: b083 sub sp, #12 8007180: af00 add r7, sp, #0 8007182: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback could be implemented in the user file */ } 8007184: bf00 nop 8007186: 370c adds r7, #12 8007188: 46bd mov sp, r7 800718a: bc80 pop {r7} 800718c: 4770 bx lr 0800718e : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800718e: b480 push {r7} 8007190: b083 sub sp, #12 8007192: af00 add r7, sp, #0 8007194: 6078 str r0, [r7, #4] 8007196: 460b mov r3, r1 8007198: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } 800719a: bf00 nop 800719c: 370c adds r7, #12 800719e: 46bd mov sp, r7 80071a0: bc80 pop {r7} 80071a2: 4770 bx lr 080071a4 : * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 80071a4: b580 push {r7, lr} 80071a6: b084 sub sp, #16 80071a8: af00 add r7, sp, #0 80071aa: 60f8 str r0, [r7, #12] 80071ac: 60b9 str r1, [r7, #8] 80071ae: 603b str r3, [r7, #0] 80071b0: 4613 mov r3, r2 80071b2: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 80071b4: e02c b.n 8007210 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 80071b6: 69bb ldr r3, [r7, #24] 80071b8: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 80071bc: d028 beq.n 8007210 { if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) 80071be: 69bb ldr r3, [r7, #24] 80071c0: 2b00 cmp r3, #0 80071c2: d007 beq.n 80071d4 80071c4: f7fc fd4c bl 8003c60 80071c8: 4602 mov r2, r0 80071ca: 683b ldr r3, [r7, #0] 80071cc: 1ad3 subs r3, r2, r3 80071ce: 69ba ldr r2, [r7, #24] 80071d0: 429a cmp r2, r3 80071d2: d21d bcs.n 8007210 { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); 80071d4: 68fb ldr r3, [r7, #12] 80071d6: 681b ldr r3, [r3, #0] 80071d8: 68da ldr r2, [r3, #12] 80071da: 68fb ldr r3, [r7, #12] 80071dc: 681b ldr r3, [r3, #0] 80071de: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 80071e2: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80071e4: 68fb ldr r3, [r7, #12] 80071e6: 681b ldr r3, [r3, #0] 80071e8: 695a ldr r2, [r3, #20] 80071ea: 68fb ldr r3, [r7, #12] 80071ec: 681b ldr r3, [r3, #0] 80071ee: f022 0201 bic.w r2, r2, #1 80071f2: 615a str r2, [r3, #20] huart->gState = HAL_UART_STATE_READY; 80071f4: 68fb ldr r3, [r7, #12] 80071f6: 2220 movs r2, #32 80071f8: f883 203d strb.w r2, [r3, #61] ; 0x3d huart->RxState = HAL_UART_STATE_READY; 80071fc: 68fb ldr r3, [r7, #12] 80071fe: 2220 movs r2, #32 8007200: f883 203e strb.w r2, [r3, #62] ; 0x3e /* Process Unlocked */ __HAL_UNLOCK(huart); 8007204: 68fb ldr r3, [r7, #12] 8007206: 2200 movs r2, #0 8007208: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_TIMEOUT; 800720c: 2303 movs r3, #3 800720e: e00f b.n 8007230 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8007210: 68fb ldr r3, [r7, #12] 8007212: 681b ldr r3, [r3, #0] 8007214: 681a ldr r2, [r3, #0] 8007216: 68bb ldr r3, [r7, #8] 8007218: 4013 ands r3, r2 800721a: 68ba ldr r2, [r7, #8] 800721c: 429a cmp r2, r3 800721e: bf0c ite eq 8007220: 2301 moveq r3, #1 8007222: 2300 movne r3, #0 8007224: b2db uxtb r3, r3 8007226: 461a mov r2, r3 8007228: 79fb ldrb r3, [r7, #7] 800722a: 429a cmp r2, r3 800722c: d0c3 beq.n 80071b6 } } } return HAL_OK; 800722e: 2300 movs r3, #0 } 8007230: 4618 mov r0, r3 8007232: 3710 adds r7, #16 8007234: 46bd mov sp, r7 8007236: bd80 pop {r7, pc} 08007238 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8007238: b480 push {r7} 800723a: b085 sub sp, #20 800723c: af00 add r7, sp, #0 800723e: 60f8 str r0, [r7, #12] 8007240: 60b9 str r1, [r7, #8] 8007242: 4613 mov r3, r2 8007244: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 8007246: 68fb ldr r3, [r7, #12] 8007248: 68ba ldr r2, [r7, #8] 800724a: 629a str r2, [r3, #40] ; 0x28 huart->RxXferSize = Size; 800724c: 68fb ldr r3, [r7, #12] 800724e: 88fa ldrh r2, [r7, #6] 8007250: 859a strh r2, [r3, #44] ; 0x2c huart->RxXferCount = Size; 8007252: 68fb ldr r3, [r7, #12] 8007254: 88fa ldrh r2, [r7, #6] 8007256: 85da strh r2, [r3, #46] ; 0x2e huart->ErrorCode = HAL_UART_ERROR_NONE; 8007258: 68fb ldr r3, [r7, #12] 800725a: 2200 movs r2, #0 800725c: 641a str r2, [r3, #64] ; 0x40 huart->RxState = HAL_UART_STATE_BUSY_RX; 800725e: 68fb ldr r3, [r7, #12] 8007260: 2222 movs r2, #34 ; 0x22 8007262: f883 203e strb.w r2, [r3, #62] ; 0x3e /* Process Unlocked */ __HAL_UNLOCK(huart); 8007266: 68fb ldr r3, [r7, #12] 8007268: 2200 movs r2, #0 800726a: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); 800726e: 68fb ldr r3, [r7, #12] 8007270: 681b ldr r3, [r3, #0] 8007272: 68da ldr r2, [r3, #12] 8007274: 68fb ldr r3, [r7, #12] 8007276: 681b ldr r3, [r3, #0] 8007278: f442 7280 orr.w r2, r2, #256 ; 0x100 800727c: 60da str r2, [r3, #12] /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); 800727e: 68fb ldr r3, [r7, #12] 8007280: 681b ldr r3, [r3, #0] 8007282: 695a ldr r2, [r3, #20] 8007284: 68fb ldr r3, [r7, #12] 8007286: 681b ldr r3, [r3, #0] 8007288: f042 0201 orr.w r2, r2, #1 800728c: 615a str r2, [r3, #20] /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); 800728e: 68fb ldr r3, [r7, #12] 8007290: 681b ldr r3, [r3, #0] 8007292: 68da ldr r2, [r3, #12] 8007294: 68fb ldr r3, [r7, #12] 8007296: 681b ldr r3, [r3, #0] 8007298: f042 0220 orr.w r2, r2, #32 800729c: 60da str r2, [r3, #12] return HAL_OK; 800729e: 2300 movs r3, #0 } 80072a0: 4618 mov r0, r3 80072a2: 3714 adds r7, #20 80072a4: 46bd mov sp, r7 80072a6: bc80 pop {r7} 80072a8: 4770 bx lr 080072aa : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 80072aa: b480 push {r7} 80072ac: b083 sub sp, #12 80072ae: af00 add r7, sp, #0 80072b0: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 80072b2: 687b ldr r3, [r7, #4] 80072b4: 681b ldr r3, [r3, #0] 80072b6: 68da ldr r2, [r3, #12] 80072b8: 687b ldr r3, [r7, #4] 80072ba: 681b ldr r3, [r3, #0] 80072bc: f422 7290 bic.w r2, r2, #288 ; 0x120 80072c0: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80072c2: 687b ldr r3, [r7, #4] 80072c4: 681b ldr r3, [r3, #0] 80072c6: 695a ldr r2, [r3, #20] 80072c8: 687b ldr r3, [r7, #4] 80072ca: 681b ldr r3, [r3, #0] 80072cc: f022 0201 bic.w r2, r2, #1 80072d0: 615a str r2, [r3, #20] /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80072d2: 687b ldr r3, [r7, #4] 80072d4: 6b1b ldr r3, [r3, #48] ; 0x30 80072d6: 2b01 cmp r3, #1 80072d8: d107 bne.n 80072ea { CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80072da: 687b ldr r3, [r7, #4] 80072dc: 681b ldr r3, [r3, #0] 80072de: 68da ldr r2, [r3, #12] 80072e0: 687b ldr r3, [r7, #4] 80072e2: 681b ldr r3, [r3, #0] 80072e4: f022 0210 bic.w r2, r2, #16 80072e8: 60da str r2, [r3, #12] } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80072ea: 687b ldr r3, [r7, #4] 80072ec: 2220 movs r2, #32 80072ee: f883 203e strb.w r2, [r3, #62] ; 0x3e huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80072f2: 687b ldr r3, [r7, #4] 80072f4: 2200 movs r2, #0 80072f6: 631a str r2, [r3, #48] ; 0x30 } 80072f8: bf00 nop 80072fa: 370c adds r7, #12 80072fc: 46bd mov sp, r7 80072fe: bc80 pop {r7} 8007300: 4770 bx lr 08007302 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8007302: b580 push {r7, lr} 8007304: b084 sub sp, #16 8007306: af00 add r7, sp, #0 8007308: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800730a: 687b ldr r3, [r7, #4] 800730c: 6a5b ldr r3, [r3, #36] ; 0x24 800730e: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 8007310: 68fb ldr r3, [r7, #12] 8007312: 2200 movs r2, #0 8007314: 85da strh r2, [r3, #46] ; 0x2e huart->TxXferCount = 0x00U; 8007316: 68fb ldr r3, [r7, #12] 8007318: 2200 movs r2, #0 800731a: 84da strh r2, [r3, #38] ; 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800731c: 68f8 ldr r0, [r7, #12] 800731e: f7ff ff2d bl 800717c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8007322: bf00 nop 8007324: 3710 adds r7, #16 8007326: 46bd mov sp, r7 8007328: bd80 pop {r7, pc} 0800732a : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 800732a: b480 push {r7} 800732c: b085 sub sp, #20 800732e: af00 add r7, sp, #0 8007330: 6078 str r0, [r7, #4] uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8007332: 687b ldr r3, [r7, #4] 8007334: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8007338: b2db uxtb r3, r3 800733a: 2b21 cmp r3, #33 ; 0x21 800733c: d13e bne.n 80073bc { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800733e: 687b ldr r3, [r7, #4] 8007340: 689b ldr r3, [r3, #8] 8007342: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8007346: d114 bne.n 8007372 8007348: 687b ldr r3, [r7, #4] 800734a: 691b ldr r3, [r3, #16] 800734c: 2b00 cmp r3, #0 800734e: d110 bne.n 8007372 { tmp = (uint16_t *) huart->pTxBuffPtr; 8007350: 687b ldr r3, [r7, #4] 8007352: 6a1b ldr r3, [r3, #32] 8007354: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8007356: 68fb ldr r3, [r7, #12] 8007358: 881b ldrh r3, [r3, #0] 800735a: 461a mov r2, r3 800735c: 687b ldr r3, [r7, #4] 800735e: 681b ldr r3, [r3, #0] 8007360: f3c2 0208 ubfx r2, r2, #0, #9 8007364: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 8007366: 687b ldr r3, [r7, #4] 8007368: 6a1b ldr r3, [r3, #32] 800736a: 1c9a adds r2, r3, #2 800736c: 687b ldr r3, [r7, #4] 800736e: 621a str r2, [r3, #32] 8007370: e008 b.n 8007384 } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 8007372: 687b ldr r3, [r7, #4] 8007374: 6a1b ldr r3, [r3, #32] 8007376: 1c59 adds r1, r3, #1 8007378: 687a ldr r2, [r7, #4] 800737a: 6211 str r1, [r2, #32] 800737c: 781a ldrb r2, [r3, #0] 800737e: 687b ldr r3, [r7, #4] 8007380: 681b ldr r3, [r3, #0] 8007382: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 8007384: 687b ldr r3, [r7, #4] 8007386: 8cdb ldrh r3, [r3, #38] ; 0x26 8007388: b29b uxth r3, r3 800738a: 3b01 subs r3, #1 800738c: b29b uxth r3, r3 800738e: 687a ldr r2, [r7, #4] 8007390: 4619 mov r1, r3 8007392: 84d1 strh r1, [r2, #38] ; 0x26 8007394: 2b00 cmp r3, #0 8007396: d10f bne.n 80073b8 { /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8007398: 687b ldr r3, [r7, #4] 800739a: 681b ldr r3, [r3, #0] 800739c: 68da ldr r2, [r3, #12] 800739e: 687b ldr r3, [r7, #4] 80073a0: 681b ldr r3, [r3, #0] 80073a2: f022 0280 bic.w r2, r2, #128 ; 0x80 80073a6: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 80073a8: 687b ldr r3, [r7, #4] 80073aa: 681b ldr r3, [r3, #0] 80073ac: 68da ldr r2, [r3, #12] 80073ae: 687b ldr r3, [r7, #4] 80073b0: 681b ldr r3, [r3, #0] 80073b2: f042 0240 orr.w r2, r2, #64 ; 0x40 80073b6: 60da str r2, [r3, #12] } return HAL_OK; 80073b8: 2300 movs r3, #0 80073ba: e000 b.n 80073be } else { return HAL_BUSY; 80073bc: 2302 movs r3, #2 } } 80073be: 4618 mov r0, r3 80073c0: 3714 adds r7, #20 80073c2: 46bd mov sp, r7 80073c4: bc80 pop {r7} 80073c6: 4770 bx lr 080073c8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 80073c8: b580 push {r7, lr} 80073ca: b082 sub sp, #8 80073cc: af00 add r7, sp, #0 80073ce: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 80073d0: 687b ldr r3, [r7, #4] 80073d2: 681b ldr r3, [r3, #0] 80073d4: 68da ldr r2, [r3, #12] 80073d6: 687b ldr r3, [r7, #4] 80073d8: 681b ldr r3, [r3, #0] 80073da: f022 0240 bic.w r2, r2, #64 ; 0x40 80073de: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80073e0: 687b ldr r3, [r7, #4] 80073e2: 2220 movs r2, #32 80073e4: f883 203d strb.w r2, [r3, #61] ; 0x3d #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 80073e8: 6878 ldr r0, [r7, #4] 80073ea: f7ff feb5 bl 8007158 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 80073ee: 2300 movs r3, #0 } 80073f0: 4618 mov r0, r3 80073f2: 3708 adds r7, #8 80073f4: 46bd mov sp, r7 80073f6: bd80 pop {r7, pc} 080073f8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 80073f8: b580 push {r7, lr} 80073fa: b086 sub sp, #24 80073fc: af00 add r7, sp, #0 80073fe: 6078 str r0, [r7, #4] uint8_t *pdata8bits; uint16_t *pdata16bits; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8007400: 687b ldr r3, [r7, #4] 8007402: f893 303e ldrb.w r3, [r3, #62] ; 0x3e 8007406: b2db uxtb r3, r3 8007408: 2b22 cmp r3, #34 ; 0x22 800740a: f040 8099 bne.w 8007540 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800740e: 687b ldr r3, [r7, #4] 8007410: 689b ldr r3, [r3, #8] 8007412: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8007416: d117 bne.n 8007448 8007418: 687b ldr r3, [r7, #4] 800741a: 691b ldr r3, [r3, #16] 800741c: 2b00 cmp r3, #0 800741e: d113 bne.n 8007448 { pdata8bits = NULL; 8007420: 2300 movs r3, #0 8007422: 617b str r3, [r7, #20] pdata16bits = (uint16_t *) huart->pRxBuffPtr; 8007424: 687b ldr r3, [r7, #4] 8007426: 6a9b ldr r3, [r3, #40] ; 0x28 8007428: 613b str r3, [r7, #16] *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 800742a: 687b ldr r3, [r7, #4] 800742c: 681b ldr r3, [r3, #0] 800742e: 685b ldr r3, [r3, #4] 8007430: b29b uxth r3, r3 8007432: f3c3 0308 ubfx r3, r3, #0, #9 8007436: b29a uxth r2, r3 8007438: 693b ldr r3, [r7, #16] 800743a: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 800743c: 687b ldr r3, [r7, #4] 800743e: 6a9b ldr r3, [r3, #40] ; 0x28 8007440: 1c9a adds r2, r3, #2 8007442: 687b ldr r3, [r7, #4] 8007444: 629a str r2, [r3, #40] ; 0x28 8007446: e026 b.n 8007496 } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8007448: 687b ldr r3, [r7, #4] 800744a: 6a9b ldr r3, [r3, #40] ; 0x28 800744c: 617b str r3, [r7, #20] pdata16bits = NULL; 800744e: 2300 movs r3, #0 8007450: 613b str r3, [r7, #16] if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 8007452: 687b ldr r3, [r7, #4] 8007454: 689b ldr r3, [r3, #8] 8007456: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 800745a: d007 beq.n 800746c 800745c: 687b ldr r3, [r7, #4] 800745e: 689b ldr r3, [r3, #8] 8007460: 2b00 cmp r3, #0 8007462: d10a bne.n 800747a 8007464: 687b ldr r3, [r7, #4] 8007466: 691b ldr r3, [r3, #16] 8007468: 2b00 cmp r3, #0 800746a: d106 bne.n 800747a { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 800746c: 687b ldr r3, [r7, #4] 800746e: 681b ldr r3, [r3, #0] 8007470: 685b ldr r3, [r3, #4] 8007472: b2da uxtb r2, r3 8007474: 697b ldr r3, [r7, #20] 8007476: 701a strb r2, [r3, #0] 8007478: e008 b.n 800748c } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 800747a: 687b ldr r3, [r7, #4] 800747c: 681b ldr r3, [r3, #0] 800747e: 685b ldr r3, [r3, #4] 8007480: b2db uxtb r3, r3 8007482: f003 037f and.w r3, r3, #127 ; 0x7f 8007486: b2da uxtb r2, r3 8007488: 697b ldr r3, [r7, #20] 800748a: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 800748c: 687b ldr r3, [r7, #4] 800748e: 6a9b ldr r3, [r3, #40] ; 0x28 8007490: 1c5a adds r2, r3, #1 8007492: 687b ldr r3, [r7, #4] 8007494: 629a str r2, [r3, #40] ; 0x28 } if (--huart->RxXferCount == 0U) 8007496: 687b ldr r3, [r7, #4] 8007498: 8ddb ldrh r3, [r3, #46] ; 0x2e 800749a: b29b uxth r3, r3 800749c: 3b01 subs r3, #1 800749e: b29b uxth r3, r3 80074a0: 687a ldr r2, [r7, #4] 80074a2: 4619 mov r1, r3 80074a4: 85d1 strh r1, [r2, #46] ; 0x2e 80074a6: 2b00 cmp r3, #0 80074a8: d148 bne.n 800753c { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 80074aa: 687b ldr r3, [r7, #4] 80074ac: 681b ldr r3, [r3, #0] 80074ae: 68da ldr r2, [r3, #12] 80074b0: 687b ldr r3, [r7, #4] 80074b2: 681b ldr r3, [r3, #0] 80074b4: f022 0220 bic.w r2, r2, #32 80074b8: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 80074ba: 687b ldr r3, [r7, #4] 80074bc: 681b ldr r3, [r3, #0] 80074be: 68da ldr r2, [r3, #12] 80074c0: 687b ldr r3, [r7, #4] 80074c2: 681b ldr r3, [r3, #0] 80074c4: f422 7280 bic.w r2, r2, #256 ; 0x100 80074c8: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 80074ca: 687b ldr r3, [r7, #4] 80074cc: 681b ldr r3, [r3, #0] 80074ce: 695a ldr r2, [r3, #20] 80074d0: 687b ldr r3, [r7, #4] 80074d2: 681b ldr r3, [r3, #0] 80074d4: f022 0201 bic.w r2, r2, #1 80074d8: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80074da: 687b ldr r3, [r7, #4] 80074dc: 2220 movs r2, #32 80074de: f883 203e strb.w r2, [r3, #62] ; 0x3e /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80074e2: 687b ldr r3, [r7, #4] 80074e4: 6b1b ldr r3, [r3, #48] ; 0x30 80074e6: 2b01 cmp r3, #1 80074e8: d123 bne.n 8007532 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80074ea: 687b ldr r3, [r7, #4] 80074ec: 2200 movs r2, #0 80074ee: 631a str r2, [r3, #48] ; 0x30 /* Disable IDLE interrupt */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80074f0: 687b ldr r3, [r7, #4] 80074f2: 681b ldr r3, [r3, #0] 80074f4: 68da ldr r2, [r3, #12] 80074f6: 687b ldr r3, [r7, #4] 80074f8: 681b ldr r3, [r3, #0] 80074fa: f022 0210 bic.w r2, r2, #16 80074fe: 60da str r2, [r3, #12] /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 8007500: 687b ldr r3, [r7, #4] 8007502: 681b ldr r3, [r3, #0] 8007504: 681b ldr r3, [r3, #0] 8007506: f003 0310 and.w r3, r3, #16 800750a: 2b10 cmp r3, #16 800750c: d10a bne.n 8007524 { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 800750e: 2300 movs r3, #0 8007510: 60fb str r3, [r7, #12] 8007512: 687b ldr r3, [r7, #4] 8007514: 681b ldr r3, [r3, #0] 8007516: 681b ldr r3, [r3, #0] 8007518: 60fb str r3, [r7, #12] 800751a: 687b ldr r3, [r7, #4] 800751c: 681b ldr r3, [r3, #0] 800751e: 685b ldr r3, [r3, #4] 8007520: 60fb str r3, [r7, #12] 8007522: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8007524: 687b ldr r3, [r7, #4] 8007526: 8d9b ldrh r3, [r3, #44] ; 0x2c 8007528: 4619 mov r1, r3 800752a: 6878 ldr r0, [r7, #4] 800752c: f7ff fe2f bl 800718e 8007530: e002 b.n 8007538 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8007532: 6878 ldr r0, [r7, #4] 8007534: f7ff fe19 bl 800716a #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8007538: 2300 movs r3, #0 800753a: e002 b.n 8007542 } return HAL_OK; 800753c: 2300 movs r3, #0 800753e: e000 b.n 8007542 } else { return HAL_BUSY; 8007540: 2302 movs r3, #2 } } 8007542: 4618 mov r0, r3 8007544: 3718 adds r7, #24 8007546: 46bd mov sp, r7 8007548: bd80 pop {r7, pc} ... 0800754c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 800754c: b580 push {r7, lr} 800754e: b084 sub sp, #16 8007550: af00 add r7, sp, #0 8007552: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8007554: 687b ldr r3, [r7, #4] 8007556: 681b ldr r3, [r3, #0] 8007558: 691b ldr r3, [r3, #16] 800755a: f423 5140 bic.w r1, r3, #12288 ; 0x3000 800755e: 687b ldr r3, [r7, #4] 8007560: 68da ldr r2, [r3, #12] 8007562: 687b ldr r3, [r7, #4] 8007564: 681b ldr r3, [r3, #0] 8007566: 430a orrs r2, r1 8007568: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 800756a: 687b ldr r3, [r7, #4] 800756c: 689a ldr r2, [r3, #8] 800756e: 687b ldr r3, [r7, #4] 8007570: 691b ldr r3, [r3, #16] 8007572: 431a orrs r2, r3 8007574: 687b ldr r3, [r7, #4] 8007576: 695b ldr r3, [r3, #20] 8007578: 4313 orrs r3, r2 800757a: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 800757c: 687b ldr r3, [r7, #4] 800757e: 681b ldr r3, [r3, #0] 8007580: 68db ldr r3, [r3, #12] 8007582: f423 53b0 bic.w r3, r3, #5632 ; 0x1600 8007586: f023 030c bic.w r3, r3, #12 800758a: 687a ldr r2, [r7, #4] 800758c: 6812 ldr r2, [r2, #0] 800758e: 68b9 ldr r1, [r7, #8] 8007590: 430b orrs r3, r1 8007592: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8007594: 687b ldr r3, [r7, #4] 8007596: 681b ldr r3, [r3, #0] 8007598: 695b ldr r3, [r3, #20] 800759a: f423 7140 bic.w r1, r3, #768 ; 0x300 800759e: 687b ldr r3, [r7, #4] 80075a0: 699a ldr r2, [r3, #24] 80075a2: 687b ldr r3, [r7, #4] 80075a4: 681b ldr r3, [r3, #0] 80075a6: 430a orrs r2, r1 80075a8: 615a str r2, [r3, #20] if(huart->Instance == USART1) 80075aa: 687b ldr r3, [r7, #4] 80075ac: 681b ldr r3, [r3, #0] 80075ae: 4a2c ldr r2, [pc, #176] ; (8007660 ) 80075b0: 4293 cmp r3, r2 80075b2: d103 bne.n 80075bc { pclk = HAL_RCC_GetPCLK2Freq(); 80075b4: f7ff f832 bl 800661c 80075b8: 60f8 str r0, [r7, #12] 80075ba: e002 b.n 80075c2 } else { pclk = HAL_RCC_GetPCLK1Freq(); 80075bc: f7ff f81a bl 80065f4 80075c0: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 80075c2: 68fa ldr r2, [r7, #12] 80075c4: 4613 mov r3, r2 80075c6: 009b lsls r3, r3, #2 80075c8: 4413 add r3, r2 80075ca: 009a lsls r2, r3, #2 80075cc: 441a add r2, r3 80075ce: 687b ldr r3, [r7, #4] 80075d0: 685b ldr r3, [r3, #4] 80075d2: 009b lsls r3, r3, #2 80075d4: fbb2 f3f3 udiv r3, r2, r3 80075d8: 4a22 ldr r2, [pc, #136] ; (8007664 ) 80075da: fba2 2303 umull r2, r3, r2, r3 80075de: 095b lsrs r3, r3, #5 80075e0: 0119 lsls r1, r3, #4 80075e2: 68fa ldr r2, [r7, #12] 80075e4: 4613 mov r3, r2 80075e6: 009b lsls r3, r3, #2 80075e8: 4413 add r3, r2 80075ea: 009a lsls r2, r3, #2 80075ec: 441a add r2, r3 80075ee: 687b ldr r3, [r7, #4] 80075f0: 685b ldr r3, [r3, #4] 80075f2: 009b lsls r3, r3, #2 80075f4: fbb2 f2f3 udiv r2, r2, r3 80075f8: 4b1a ldr r3, [pc, #104] ; (8007664 ) 80075fa: fba3 0302 umull r0, r3, r3, r2 80075fe: 095b lsrs r3, r3, #5 8007600: 2064 movs r0, #100 ; 0x64 8007602: fb00 f303 mul.w r3, r0, r3 8007606: 1ad3 subs r3, r2, r3 8007608: 011b lsls r3, r3, #4 800760a: 3332 adds r3, #50 ; 0x32 800760c: 4a15 ldr r2, [pc, #84] ; (8007664 ) 800760e: fba2 2303 umull r2, r3, r2, r3 8007612: 095b lsrs r3, r3, #5 8007614: f003 03f0 and.w r3, r3, #240 ; 0xf0 8007618: 4419 add r1, r3 800761a: 68fa ldr r2, [r7, #12] 800761c: 4613 mov r3, r2 800761e: 009b lsls r3, r3, #2 8007620: 4413 add r3, r2 8007622: 009a lsls r2, r3, #2 8007624: 441a add r2, r3 8007626: 687b ldr r3, [r7, #4] 8007628: 685b ldr r3, [r3, #4] 800762a: 009b lsls r3, r3, #2 800762c: fbb2 f2f3 udiv r2, r2, r3 8007630: 4b0c ldr r3, [pc, #48] ; (8007664 ) 8007632: fba3 0302 umull r0, r3, r3, r2 8007636: 095b lsrs r3, r3, #5 8007638: 2064 movs r0, #100 ; 0x64 800763a: fb00 f303 mul.w r3, r0, r3 800763e: 1ad3 subs r3, r2, r3 8007640: 011b lsls r3, r3, #4 8007642: 3332 adds r3, #50 ; 0x32 8007644: 4a07 ldr r2, [pc, #28] ; (8007664 ) 8007646: fba2 2303 umull r2, r3, r2, r3 800764a: 095b lsrs r3, r3, #5 800764c: f003 020f and.w r2, r3, #15 8007650: 687b ldr r3, [r7, #4] 8007652: 681b ldr r3, [r3, #0] 8007654: 440a add r2, r1 8007656: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 8007658: bf00 nop 800765a: 3710 adds r7, #16 800765c: 46bd mov sp, r7 800765e: bd80 pop {r7, pc} 8007660: 40013800 .word 0x40013800 8007664: 51eb851f .word 0x51eb851f 08007668 <__errno>: 8007668: 4b01 ldr r3, [pc, #4] ; (8007670 <__errno+0x8>) 800766a: 6818 ldr r0, [r3, #0] 800766c: 4770 bx lr 800766e: bf00 nop 8007670: 2000000c .word 0x2000000c 08007674 : 8007674: b538 push {r3, r4, r5, lr} 8007676: 4b0b ldr r3, [pc, #44] ; (80076a4 ) 8007678: 4604 mov r4, r0 800767a: 681d ldr r5, [r3, #0] 800767c: 6beb ldr r3, [r5, #60] ; 0x3c 800767e: b953 cbnz r3, 8007696 8007680: 2024 movs r0, #36 ; 0x24 8007682: f000 f8e7 bl 8007854 8007686: 4602 mov r2, r0 8007688: 63e8 str r0, [r5, #60] ; 0x3c 800768a: b920 cbnz r0, 8007696 800768c: 2139 movs r1, #57 ; 0x39 800768e: 4b06 ldr r3, [pc, #24] ; (80076a8 ) 8007690: 4806 ldr r0, [pc, #24] ; (80076ac ) 8007692: f000 fb4b bl 8007d2c <__assert_func> 8007696: 4620 mov r0, r4 8007698: 6be9 ldr r1, [r5, #60] ; 0x3c 800769a: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 800769e: f000 b807 b.w 80076b0 80076a2: bf00 nop 80076a4: 2000000c .word 0x2000000c 80076a8: 08008e1c .word 0x08008e1c 80076ac: 08008e33 .word 0x08008e33 080076b0 : 80076b0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80076b4: e9d0 6700 ldrd r6, r7, [r0] 80076b8: 460c mov r4, r1 80076ba: 2300 movs r3, #0 80076bc: 4630 mov r0, r6 80076be: 4639 mov r1, r7 80076c0: 4a4e ldr r2, [pc, #312] ; (80077fc ) 80076c2: f7f9 fa3f bl 8000b44 <__aeabi_ldivmod> 80076c6: 4639 mov r1, r7 80076c8: 4605 mov r5, r0 80076ca: 2300 movs r3, #0 80076cc: 4630 mov r0, r6 80076ce: 4a4b ldr r2, [pc, #300] ; (80077fc ) 80076d0: f7f9 fa38 bl 8000b44 <__aeabi_ldivmod> 80076d4: f44f 6061 mov.w r0, #3600 ; 0xe10 80076d8: 2a00 cmp r2, #0 80076da: bfbc itt lt 80076dc: f502 32a8 addlt.w r2, r2, #86016 ; 0x15000 80076e0: f502 72c0 addlt.w r2, r2, #384 ; 0x180 80076e4: fbb2 f1f0 udiv r1, r2, r0 80076e8: fb00 2211 mls r2, r0, r1, r2 80076ec: f04f 003c mov.w r0, #60 ; 0x3c 80076f0: 60a1 str r1, [r4, #8] 80076f2: fbb2 f1f0 udiv r1, r2, r0 80076f6: fb00 2211 mls r2, r0, r1, r2 80076fa: 6061 str r1, [r4, #4] 80076fc: f04f 0107 mov.w r1, #7 8007700: f505 232f add.w r3, r5, #716800 ; 0xaf000 8007704: bfac ite ge 8007706: f603 236c addwge r3, r3, #2668 ; 0xa6c 800770a: f603 236b addwlt r3, r3, #2667 ; 0xa6b 800770e: 6022 str r2, [r4, #0] 8007710: 1cda adds r2, r3, #3 8007712: fb92 f1f1 sdiv r1, r2, r1 8007716: ebc1 01c1 rsb r1, r1, r1, lsl #3 800771a: 1a52 subs r2, r2, r1 800771c: bf48 it mi 800771e: 3207 addmi r2, #7 8007720: 2b00 cmp r3, #0 8007722: 4d37 ldr r5, [pc, #220] ; (8007800 ) 8007724: 61a2 str r2, [r4, #24] 8007726: bfbd ittte lt 8007728: f5a3 320e sublt.w r2, r3, #145408 ; 0x23800 800772c: f5a2 722c sublt.w r2, r2, #688 ; 0x2b0 8007730: fb92 f5f5 sdivlt r5, r2, r5 8007734: fb93 f5f5 sdivge r5, r3, r5 8007738: 4832 ldr r0, [pc, #200] ; (8007804 ) 800773a: f648 62ac movw r2, #36524 ; 0x8eac 800773e: fb00 3005 mla r0, r0, r5, r3 8007742: f240 53b4 movw r3, #1460 ; 0x5b4 8007746: fbb0 f2f2 udiv r2, r0, r2 800774a: fbb0 f1f3 udiv r1, r0, r3 800774e: 4402 add r2, r0 8007750: 1a52 subs r2, r2, r1 8007752: 492d ldr r1, [pc, #180] ; (8007808 ) 8007754: f240 1c6d movw ip, #365 ; 0x16d 8007758: fbb0 f1f1 udiv r1, r0, r1 800775c: 1a52 subs r2, r2, r1 800775e: fbb2 f1fc udiv r1, r2, ip 8007762: 2764 movs r7, #100 ; 0x64 8007764: fbb2 f3f3 udiv r3, r2, r3 8007768: fbb1 f6f7 udiv r6, r1, r7 800776c: 2299 movs r2, #153 ; 0x99 800776e: 1af3 subs r3, r6, r3 8007770: 4403 add r3, r0 8007772: fb0c 3311 mls r3, ip, r1, r3 8007776: eb03 0e83 add.w lr, r3, r3, lsl #2 800777a: f10e 0e02 add.w lr, lr, #2 800777e: fbbe f0f2 udiv r0, lr, r2 8007782: f04f 0805 mov.w r8, #5 8007786: 4342 muls r2, r0 8007788: 3202 adds r2, #2 800778a: fbb2 f2f8 udiv r2, r2, r8 800778e: f103 0c01 add.w ip, r3, #1 8007792: ebac 0c02 sub.w ip, ip, r2 8007796: f240 52f9 movw r2, #1529 ; 0x5f9 800779a: 4596 cmp lr, r2 800779c: bf94 ite ls 800779e: 2202 movls r2, #2 80077a0: f06f 0209 mvnhi.w r2, #9 80077a4: 4410 add r0, r2 80077a6: f44f 72c8 mov.w r2, #400 ; 0x190 80077aa: fb02 1505 mla r5, r2, r5, r1 80077ae: 2801 cmp r0, #1 80077b0: bf98 it ls 80077b2: 3501 addls r5, #1 80077b4: f5b3 7f99 cmp.w r3, #306 ; 0x132 80077b8: d30d bcc.n 80077d6 80077ba: f5a3 7399 sub.w r3, r3, #306 ; 0x132 80077be: 61e3 str r3, [r4, #28] 80077c0: 2300 movs r3, #0 80077c2: f2a5 756c subw r5, r5, #1900 ; 0x76c 80077c6: e9c4 0504 strd r0, r5, [r4, #16] 80077ca: f8c4 c00c str.w ip, [r4, #12] 80077ce: 4620 mov r0, r4 80077d0: 6223 str r3, [r4, #32] 80077d2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80077d6: 078a lsls r2, r1, #30 80077d8: d102 bne.n 80077e0 80077da: fb07 1616 mls r6, r7, r6, r1 80077de: b95e cbnz r6, 80077f8 80077e0: f44f 72c8 mov.w r2, #400 ; 0x190 80077e4: fbb1 f6f2 udiv r6, r1, r2 80077e8: fb02 1216 mls r2, r2, r6, r1 80077ec: fab2 f282 clz r2, r2 80077f0: 0952 lsrs r2, r2, #5 80077f2: 333b adds r3, #59 ; 0x3b 80077f4: 4413 add r3, r2 80077f6: e7e2 b.n 80077be 80077f8: 2201 movs r2, #1 80077fa: e7fa b.n 80077f2 80077fc: 00015180 .word 0x00015180 8007800: 00023ab1 .word 0x00023ab1 8007804: fffdc54f .word 0xfffdc54f 8007808: 00023ab0 .word 0x00023ab0 0800780c <__libc_init_array>: 800780c: b570 push {r4, r5, r6, lr} 800780e: 2600 movs r6, #0 8007810: 4d0c ldr r5, [pc, #48] ; (8007844 <__libc_init_array+0x38>) 8007812: 4c0d ldr r4, [pc, #52] ; (8007848 <__libc_init_array+0x3c>) 8007814: 1b64 subs r4, r4, r5 8007816: 10a4 asrs r4, r4, #2 8007818: 42a6 cmp r6, r4 800781a: d109 bne.n 8007830 <__libc_init_array+0x24> 800781c: f001 f8d2 bl 80089c4 <_init> 8007820: 2600 movs r6, #0 8007822: 4d0a ldr r5, [pc, #40] ; (800784c <__libc_init_array+0x40>) 8007824: 4c0a ldr r4, [pc, #40] ; (8007850 <__libc_init_array+0x44>) 8007826: 1b64 subs r4, r4, r5 8007828: 10a4 asrs r4, r4, #2 800782a: 42a6 cmp r6, r4 800782c: d105 bne.n 800783a <__libc_init_array+0x2e> 800782e: bd70 pop {r4, r5, r6, pc} 8007830: f855 3b04 ldr.w r3, [r5], #4 8007834: 4798 blx r3 8007836: 3601 adds r6, #1 8007838: e7ee b.n 8007818 <__libc_init_array+0xc> 800783a: f855 3b04 ldr.w r3, [r5], #4 800783e: 4798 blx r3 8007840: 3601 adds r6, #1 8007842: e7f2 b.n 800782a <__libc_init_array+0x1e> 8007844: 08008f6c .word 0x08008f6c 8007848: 08008f6c .word 0x08008f6c 800784c: 08008f6c .word 0x08008f6c 8007850: 08008f70 .word 0x08008f70 08007854 : 8007854: 4b02 ldr r3, [pc, #8] ; (8007860 ) 8007856: 4601 mov r1, r0 8007858: 6818 ldr r0, [r3, #0] 800785a: f000 b881 b.w 8007960 <_malloc_r> 800785e: bf00 nop 8007860: 2000000c .word 0x2000000c 08007864 : 8007864: 440a add r2, r1 8007866: 4291 cmp r1, r2 8007868: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff 800786c: d100 bne.n 8007870 800786e: 4770 bx lr 8007870: b510 push {r4, lr} 8007872: f811 4b01 ldrb.w r4, [r1], #1 8007876: 4291 cmp r1, r2 8007878: f803 4f01 strb.w r4, [r3, #1]! 800787c: d1f9 bne.n 8007872 800787e: bd10 pop {r4, pc} 08007880 : 8007880: 4603 mov r3, r0 8007882: 4402 add r2, r0 8007884: 4293 cmp r3, r2 8007886: d100 bne.n 800788a 8007888: 4770 bx lr 800788a: f803 1b01 strb.w r1, [r3], #1 800788e: e7f9 b.n 8007884 08007890 <_free_r>: 8007890: b538 push {r3, r4, r5, lr} 8007892: 4605 mov r5, r0 8007894: 2900 cmp r1, #0 8007896: d040 beq.n 800791a <_free_r+0x8a> 8007898: f851 3c04 ldr.w r3, [r1, #-4] 800789c: 1f0c subs r4, r1, #4 800789e: 2b00 cmp r3, #0 80078a0: bfb8 it lt 80078a2: 18e4 addlt r4, r4, r3 80078a4: f000 fc8e bl 80081c4 <__malloc_lock> 80078a8: 4a1c ldr r2, [pc, #112] ; (800791c <_free_r+0x8c>) 80078aa: 6813 ldr r3, [r2, #0] 80078ac: b933 cbnz r3, 80078bc <_free_r+0x2c> 80078ae: 6063 str r3, [r4, #4] 80078b0: 6014 str r4, [r2, #0] 80078b2: 4628 mov r0, r5 80078b4: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 80078b8: f000 bc8a b.w 80081d0 <__malloc_unlock> 80078bc: 42a3 cmp r3, r4 80078be: d908 bls.n 80078d2 <_free_r+0x42> 80078c0: 6820 ldr r0, [r4, #0] 80078c2: 1821 adds r1, r4, r0 80078c4: 428b cmp r3, r1 80078c6: bf01 itttt eq 80078c8: 6819 ldreq r1, [r3, #0] 80078ca: 685b ldreq r3, [r3, #4] 80078cc: 1809 addeq r1, r1, r0 80078ce: 6021 streq r1, [r4, #0] 80078d0: e7ed b.n 80078ae <_free_r+0x1e> 80078d2: 461a mov r2, r3 80078d4: 685b ldr r3, [r3, #4] 80078d6: b10b cbz r3, 80078dc <_free_r+0x4c> 80078d8: 42a3 cmp r3, r4 80078da: d9fa bls.n 80078d2 <_free_r+0x42> 80078dc: 6811 ldr r1, [r2, #0] 80078de: 1850 adds r0, r2, r1 80078e0: 42a0 cmp r0, r4 80078e2: d10b bne.n 80078fc <_free_r+0x6c> 80078e4: 6820 ldr r0, [r4, #0] 80078e6: 4401 add r1, r0 80078e8: 1850 adds r0, r2, r1 80078ea: 4283 cmp r3, r0 80078ec: 6011 str r1, [r2, #0] 80078ee: d1e0 bne.n 80078b2 <_free_r+0x22> 80078f0: 6818 ldr r0, [r3, #0] 80078f2: 685b ldr r3, [r3, #4] 80078f4: 4401 add r1, r0 80078f6: 6011 str r1, [r2, #0] 80078f8: 6053 str r3, [r2, #4] 80078fa: e7da b.n 80078b2 <_free_r+0x22> 80078fc: d902 bls.n 8007904 <_free_r+0x74> 80078fe: 230c movs r3, #12 8007900: 602b str r3, [r5, #0] 8007902: e7d6 b.n 80078b2 <_free_r+0x22> 8007904: 6820 ldr r0, [r4, #0] 8007906: 1821 adds r1, r4, r0 8007908: 428b cmp r3, r1 800790a: bf01 itttt eq 800790c: 6819 ldreq r1, [r3, #0] 800790e: 685b ldreq r3, [r3, #4] 8007910: 1809 addeq r1, r1, r0 8007912: 6021 streq r1, [r4, #0] 8007914: 6063 str r3, [r4, #4] 8007916: 6054 str r4, [r2, #4] 8007918: e7cb b.n 80078b2 <_free_r+0x22> 800791a: bd38 pop {r3, r4, r5, pc} 800791c: 20003178 .word 0x20003178 08007920 : 8007920: b570 push {r4, r5, r6, lr} 8007922: 4e0e ldr r6, [pc, #56] ; (800795c ) 8007924: 460c mov r4, r1 8007926: 6831 ldr r1, [r6, #0] 8007928: 4605 mov r5, r0 800792a: b911 cbnz r1, 8007932 800792c: f000 f91a bl 8007b64 <_sbrk_r> 8007930: 6030 str r0, [r6, #0] 8007932: 4621 mov r1, r4 8007934: 4628 mov r0, r5 8007936: f000 f915 bl 8007b64 <_sbrk_r> 800793a: 1c43 adds r3, r0, #1 800793c: d00a beq.n 8007954 800793e: 1cc4 adds r4, r0, #3 8007940: f024 0403 bic.w r4, r4, #3 8007944: 42a0 cmp r0, r4 8007946: d007 beq.n 8007958 8007948: 1a21 subs r1, r4, r0 800794a: 4628 mov r0, r5 800794c: f000 f90a bl 8007b64 <_sbrk_r> 8007950: 3001 adds r0, #1 8007952: d101 bne.n 8007958 8007954: f04f 34ff mov.w r4, #4294967295 ; 0xffffffff 8007958: 4620 mov r0, r4 800795a: bd70 pop {r4, r5, r6, pc} 800795c: 2000317c .word 0x2000317c 08007960 <_malloc_r>: 8007960: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8007964: 1ccd adds r5, r1, #3 8007966: f025 0503 bic.w r5, r5, #3 800796a: 3508 adds r5, #8 800796c: 2d0c cmp r5, #12 800796e: bf38 it cc 8007970: 250c movcc r5, #12 8007972: 2d00 cmp r5, #0 8007974: 4607 mov r7, r0 8007976: db01 blt.n 800797c <_malloc_r+0x1c> 8007978: 42a9 cmp r1, r5 800797a: d905 bls.n 8007988 <_malloc_r+0x28> 800797c: 230c movs r3, #12 800797e: 2600 movs r6, #0 8007980: 603b str r3, [r7, #0] 8007982: 4630 mov r0, r6 8007984: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8007988: 4e2e ldr r6, [pc, #184] ; (8007a44 <_malloc_r+0xe4>) 800798a: f000 fc1b bl 80081c4 <__malloc_lock> 800798e: 6833 ldr r3, [r6, #0] 8007990: 461c mov r4, r3 8007992: bb34 cbnz r4, 80079e2 <_malloc_r+0x82> 8007994: 4629 mov r1, r5 8007996: 4638 mov r0, r7 8007998: f7ff ffc2 bl 8007920 800799c: 1c43 adds r3, r0, #1 800799e: 4604 mov r4, r0 80079a0: d14d bne.n 8007a3e <_malloc_r+0xde> 80079a2: 6834 ldr r4, [r6, #0] 80079a4: 4626 mov r6, r4 80079a6: 2e00 cmp r6, #0 80079a8: d140 bne.n 8007a2c <_malloc_r+0xcc> 80079aa: 6823 ldr r3, [r4, #0] 80079ac: 4631 mov r1, r6 80079ae: 4638 mov r0, r7 80079b0: eb04 0803 add.w r8, r4, r3 80079b4: f000 f8d6 bl 8007b64 <_sbrk_r> 80079b8: 4580 cmp r8, r0 80079ba: d13a bne.n 8007a32 <_malloc_r+0xd2> 80079bc: 6821 ldr r1, [r4, #0] 80079be: 3503 adds r5, #3 80079c0: 1a6d subs r5, r5, r1 80079c2: f025 0503 bic.w r5, r5, #3 80079c6: 3508 adds r5, #8 80079c8: 2d0c cmp r5, #12 80079ca: bf38 it cc 80079cc: 250c movcc r5, #12 80079ce: 4638 mov r0, r7 80079d0: 4629 mov r1, r5 80079d2: f7ff ffa5 bl 8007920 80079d6: 3001 adds r0, #1 80079d8: d02b beq.n 8007a32 <_malloc_r+0xd2> 80079da: 6823 ldr r3, [r4, #0] 80079dc: 442b add r3, r5 80079de: 6023 str r3, [r4, #0] 80079e0: e00e b.n 8007a00 <_malloc_r+0xa0> 80079e2: 6822 ldr r2, [r4, #0] 80079e4: 1b52 subs r2, r2, r5 80079e6: d41e bmi.n 8007a26 <_malloc_r+0xc6> 80079e8: 2a0b cmp r2, #11 80079ea: d916 bls.n 8007a1a <_malloc_r+0xba> 80079ec: 1961 adds r1, r4, r5 80079ee: 42a3 cmp r3, r4 80079f0: 6025 str r5, [r4, #0] 80079f2: bf18 it ne 80079f4: 6059 strne r1, [r3, #4] 80079f6: 6863 ldr r3, [r4, #4] 80079f8: bf08 it eq 80079fa: 6031 streq r1, [r6, #0] 80079fc: 5162 str r2, [r4, r5] 80079fe: 604b str r3, [r1, #4] 8007a00: 4638 mov r0, r7 8007a02: f104 060b add.w r6, r4, #11 8007a06: f000 fbe3 bl 80081d0 <__malloc_unlock> 8007a0a: f026 0607 bic.w r6, r6, #7 8007a0e: 1d23 adds r3, r4, #4 8007a10: 1af2 subs r2, r6, r3 8007a12: d0b6 beq.n 8007982 <_malloc_r+0x22> 8007a14: 1b9b subs r3, r3, r6 8007a16: 50a3 str r3, [r4, r2] 8007a18: e7b3 b.n 8007982 <_malloc_r+0x22> 8007a1a: 6862 ldr r2, [r4, #4] 8007a1c: 42a3 cmp r3, r4 8007a1e: bf0c ite eq 8007a20: 6032 streq r2, [r6, #0] 8007a22: 605a strne r2, [r3, #4] 8007a24: e7ec b.n 8007a00 <_malloc_r+0xa0> 8007a26: 4623 mov r3, r4 8007a28: 6864 ldr r4, [r4, #4] 8007a2a: e7b2 b.n 8007992 <_malloc_r+0x32> 8007a2c: 4634 mov r4, r6 8007a2e: 6876 ldr r6, [r6, #4] 8007a30: e7b9 b.n 80079a6 <_malloc_r+0x46> 8007a32: 230c movs r3, #12 8007a34: 4638 mov r0, r7 8007a36: 603b str r3, [r7, #0] 8007a38: f000 fbca bl 80081d0 <__malloc_unlock> 8007a3c: e7a1 b.n 8007982 <_malloc_r+0x22> 8007a3e: 6025 str r5, [r4, #0] 8007a40: e7de b.n 8007a00 <_malloc_r+0xa0> 8007a42: bf00 nop 8007a44: 20003178 .word 0x20003178 08007a48 : 8007a48: b40f push {r0, r1, r2, r3} 8007a4a: 4b0a ldr r3, [pc, #40] ; (8007a74 ) 8007a4c: b513 push {r0, r1, r4, lr} 8007a4e: 681c ldr r4, [r3, #0] 8007a50: b124 cbz r4, 8007a5c 8007a52: 69a3 ldr r3, [r4, #24] 8007a54: b913 cbnz r3, 8007a5c 8007a56: 4620 mov r0, r4 8007a58: f000 fa9c bl 8007f94 <__sinit> 8007a5c: ab05 add r3, sp, #20 8007a5e: 4620 mov r0, r4 8007a60: 9a04 ldr r2, [sp, #16] 8007a62: 68a1 ldr r1, [r4, #8] 8007a64: 9301 str r3, [sp, #4] 8007a66: f000 fbe1 bl 800822c <_vfiprintf_r> 8007a6a: b002 add sp, #8 8007a6c: e8bd 4010 ldmia.w sp!, {r4, lr} 8007a70: b004 add sp, #16 8007a72: 4770 bx lr 8007a74: 2000000c .word 0x2000000c 08007a78 <_puts_r>: 8007a78: b570 push {r4, r5, r6, lr} 8007a7a: 460e mov r6, r1 8007a7c: 4605 mov r5, r0 8007a7e: b118 cbz r0, 8007a88 <_puts_r+0x10> 8007a80: 6983 ldr r3, [r0, #24] 8007a82: b90b cbnz r3, 8007a88 <_puts_r+0x10> 8007a84: f000 fa86 bl 8007f94 <__sinit> 8007a88: 69ab ldr r3, [r5, #24] 8007a8a: 68ac ldr r4, [r5, #8] 8007a8c: b913 cbnz r3, 8007a94 <_puts_r+0x1c> 8007a8e: 4628 mov r0, r5 8007a90: f000 fa80 bl 8007f94 <__sinit> 8007a94: 4b2c ldr r3, [pc, #176] ; (8007b48 <_puts_r+0xd0>) 8007a96: 429c cmp r4, r3 8007a98: d120 bne.n 8007adc <_puts_r+0x64> 8007a9a: 686c ldr r4, [r5, #4] 8007a9c: 6e63 ldr r3, [r4, #100] ; 0x64 8007a9e: 07db lsls r3, r3, #31 8007aa0: d405 bmi.n 8007aae <_puts_r+0x36> 8007aa2: 89a3 ldrh r3, [r4, #12] 8007aa4: 0598 lsls r0, r3, #22 8007aa6: d402 bmi.n 8007aae <_puts_r+0x36> 8007aa8: 6da0 ldr r0, [r4, #88] ; 0x58 8007aaa: f000 fb23 bl 80080f4 <__retarget_lock_acquire_recursive> 8007aae: 89a3 ldrh r3, [r4, #12] 8007ab0: 0719 lsls r1, r3, #28 8007ab2: d51d bpl.n 8007af0 <_puts_r+0x78> 8007ab4: 6923 ldr r3, [r4, #16] 8007ab6: b1db cbz r3, 8007af0 <_puts_r+0x78> 8007ab8: 3e01 subs r6, #1 8007aba: 68a3 ldr r3, [r4, #8] 8007abc: f816 1f01 ldrb.w r1, [r6, #1]! 8007ac0: 3b01 subs r3, #1 8007ac2: 60a3 str r3, [r4, #8] 8007ac4: bb39 cbnz r1, 8007b16 <_puts_r+0x9e> 8007ac6: 2b00 cmp r3, #0 8007ac8: da38 bge.n 8007b3c <_puts_r+0xc4> 8007aca: 4622 mov r2, r4 8007acc: 210a movs r1, #10 8007ace: 4628 mov r0, r5 8007ad0: f000 f86c bl 8007bac <__swbuf_r> 8007ad4: 3001 adds r0, #1 8007ad6: d011 beq.n 8007afc <_puts_r+0x84> 8007ad8: 250a movs r5, #10 8007ada: e011 b.n 8007b00 <_puts_r+0x88> 8007adc: 4b1b ldr r3, [pc, #108] ; (8007b4c <_puts_r+0xd4>) 8007ade: 429c cmp r4, r3 8007ae0: d101 bne.n 8007ae6 <_puts_r+0x6e> 8007ae2: 68ac ldr r4, [r5, #8] 8007ae4: e7da b.n 8007a9c <_puts_r+0x24> 8007ae6: 4b1a ldr r3, [pc, #104] ; (8007b50 <_puts_r+0xd8>) 8007ae8: 429c cmp r4, r3 8007aea: bf08 it eq 8007aec: 68ec ldreq r4, [r5, #12] 8007aee: e7d5 b.n 8007a9c <_puts_r+0x24> 8007af0: 4621 mov r1, r4 8007af2: 4628 mov r0, r5 8007af4: f000 f8ac bl 8007c50 <__swsetup_r> 8007af8: 2800 cmp r0, #0 8007afa: d0dd beq.n 8007ab8 <_puts_r+0x40> 8007afc: f04f 35ff mov.w r5, #4294967295 ; 0xffffffff 8007b00: 6e63 ldr r3, [r4, #100] ; 0x64 8007b02: 07da lsls r2, r3, #31 8007b04: d405 bmi.n 8007b12 <_puts_r+0x9a> 8007b06: 89a3 ldrh r3, [r4, #12] 8007b08: 059b lsls r3, r3, #22 8007b0a: d402 bmi.n 8007b12 <_puts_r+0x9a> 8007b0c: 6da0 ldr r0, [r4, #88] ; 0x58 8007b0e: f000 faf2 bl 80080f6 <__retarget_lock_release_recursive> 8007b12: 4628 mov r0, r5 8007b14: bd70 pop {r4, r5, r6, pc} 8007b16: 2b00 cmp r3, #0 8007b18: da04 bge.n 8007b24 <_puts_r+0xac> 8007b1a: 69a2 ldr r2, [r4, #24] 8007b1c: 429a cmp r2, r3 8007b1e: dc06 bgt.n 8007b2e <_puts_r+0xb6> 8007b20: 290a cmp r1, #10 8007b22: d004 beq.n 8007b2e <_puts_r+0xb6> 8007b24: 6823 ldr r3, [r4, #0] 8007b26: 1c5a adds r2, r3, #1 8007b28: 6022 str r2, [r4, #0] 8007b2a: 7019 strb r1, [r3, #0] 8007b2c: e7c5 b.n 8007aba <_puts_r+0x42> 8007b2e: 4622 mov r2, r4 8007b30: 4628 mov r0, r5 8007b32: f000 f83b bl 8007bac <__swbuf_r> 8007b36: 3001 adds r0, #1 8007b38: d1bf bne.n 8007aba <_puts_r+0x42> 8007b3a: e7df b.n 8007afc <_puts_r+0x84> 8007b3c: 250a movs r5, #10 8007b3e: 6823 ldr r3, [r4, #0] 8007b40: 1c5a adds r2, r3, #1 8007b42: 6022 str r2, [r4, #0] 8007b44: 701d strb r5, [r3, #0] 8007b46: e7db b.n 8007b00 <_puts_r+0x88> 8007b48: 08008ef0 .word 0x08008ef0 8007b4c: 08008f10 .word 0x08008f10 8007b50: 08008ed0 .word 0x08008ed0 08007b54 : 8007b54: 4b02 ldr r3, [pc, #8] ; (8007b60 ) 8007b56: 4601 mov r1, r0 8007b58: 6818 ldr r0, [r3, #0] 8007b5a: f7ff bf8d b.w 8007a78 <_puts_r> 8007b5e: bf00 nop 8007b60: 2000000c .word 0x2000000c 08007b64 <_sbrk_r>: 8007b64: b538 push {r3, r4, r5, lr} 8007b66: 2300 movs r3, #0 8007b68: 4d05 ldr r5, [pc, #20] ; (8007b80 <_sbrk_r+0x1c>) 8007b6a: 4604 mov r4, r0 8007b6c: 4608 mov r0, r1 8007b6e: 602b str r3, [r5, #0] 8007b70: f7fb ff30 bl 80039d4 <_sbrk> 8007b74: 1c43 adds r3, r0, #1 8007b76: d102 bne.n 8007b7e <_sbrk_r+0x1a> 8007b78: 682b ldr r3, [r5, #0] 8007b7a: b103 cbz r3, 8007b7e <_sbrk_r+0x1a> 8007b7c: 6023 str r3, [r4, #0] 8007b7e: bd38 pop {r3, r4, r5, pc} 8007b80: 20003184 .word 0x20003184 08007b84 : 8007b84: 4603 mov r3, r0 8007b86: b510 push {r4, lr} 8007b88: b172 cbz r2, 8007ba8 8007b8a: 3901 subs r1, #1 8007b8c: 1884 adds r4, r0, r2 8007b8e: f813 0b01 ldrb.w r0, [r3], #1 8007b92: f811 2f01 ldrb.w r2, [r1, #1]! 8007b96: 4290 cmp r0, r2 8007b98: d101 bne.n 8007b9e 8007b9a: 42a3 cmp r3, r4 8007b9c: d101 bne.n 8007ba2 8007b9e: 1a80 subs r0, r0, r2 8007ba0: bd10 pop {r4, pc} 8007ba2: 2800 cmp r0, #0 8007ba4: d1f3 bne.n 8007b8e 8007ba6: e7fa b.n 8007b9e 8007ba8: 4610 mov r0, r2 8007baa: e7f9 b.n 8007ba0 08007bac <__swbuf_r>: 8007bac: b5f8 push {r3, r4, r5, r6, r7, lr} 8007bae: 460e mov r6, r1 8007bb0: 4614 mov r4, r2 8007bb2: 4605 mov r5, r0 8007bb4: b118 cbz r0, 8007bbe <__swbuf_r+0x12> 8007bb6: 6983 ldr r3, [r0, #24] 8007bb8: b90b cbnz r3, 8007bbe <__swbuf_r+0x12> 8007bba: f000 f9eb bl 8007f94 <__sinit> 8007bbe: 4b21 ldr r3, [pc, #132] ; (8007c44 <__swbuf_r+0x98>) 8007bc0: 429c cmp r4, r3 8007bc2: d12b bne.n 8007c1c <__swbuf_r+0x70> 8007bc4: 686c ldr r4, [r5, #4] 8007bc6: 69a3 ldr r3, [r4, #24] 8007bc8: 60a3 str r3, [r4, #8] 8007bca: 89a3 ldrh r3, [r4, #12] 8007bcc: 071a lsls r2, r3, #28 8007bce: d52f bpl.n 8007c30 <__swbuf_r+0x84> 8007bd0: 6923 ldr r3, [r4, #16] 8007bd2: b36b cbz r3, 8007c30 <__swbuf_r+0x84> 8007bd4: 6923 ldr r3, [r4, #16] 8007bd6: 6820 ldr r0, [r4, #0] 8007bd8: b2f6 uxtb r6, r6 8007bda: 1ac0 subs r0, r0, r3 8007bdc: 6963 ldr r3, [r4, #20] 8007bde: 4637 mov r7, r6 8007be0: 4283 cmp r3, r0 8007be2: dc04 bgt.n 8007bee <__swbuf_r+0x42> 8007be4: 4621 mov r1, r4 8007be6: 4628 mov r0, r5 8007be8: f000 f940 bl 8007e6c <_fflush_r> 8007bec: bb30 cbnz r0, 8007c3c <__swbuf_r+0x90> 8007bee: 68a3 ldr r3, [r4, #8] 8007bf0: 3001 adds r0, #1 8007bf2: 3b01 subs r3, #1 8007bf4: 60a3 str r3, [r4, #8] 8007bf6: 6823 ldr r3, [r4, #0] 8007bf8: 1c5a adds r2, r3, #1 8007bfa: 6022 str r2, [r4, #0] 8007bfc: 701e strb r6, [r3, #0] 8007bfe: 6963 ldr r3, [r4, #20] 8007c00: 4283 cmp r3, r0 8007c02: d004 beq.n 8007c0e <__swbuf_r+0x62> 8007c04: 89a3 ldrh r3, [r4, #12] 8007c06: 07db lsls r3, r3, #31 8007c08: d506 bpl.n 8007c18 <__swbuf_r+0x6c> 8007c0a: 2e0a cmp r6, #10 8007c0c: d104 bne.n 8007c18 <__swbuf_r+0x6c> 8007c0e: 4621 mov r1, r4 8007c10: 4628 mov r0, r5 8007c12: f000 f92b bl 8007e6c <_fflush_r> 8007c16: b988 cbnz r0, 8007c3c <__swbuf_r+0x90> 8007c18: 4638 mov r0, r7 8007c1a: bdf8 pop {r3, r4, r5, r6, r7, pc} 8007c1c: 4b0a ldr r3, [pc, #40] ; (8007c48 <__swbuf_r+0x9c>) 8007c1e: 429c cmp r4, r3 8007c20: d101 bne.n 8007c26 <__swbuf_r+0x7a> 8007c22: 68ac ldr r4, [r5, #8] 8007c24: e7cf b.n 8007bc6 <__swbuf_r+0x1a> 8007c26: 4b09 ldr r3, [pc, #36] ; (8007c4c <__swbuf_r+0xa0>) 8007c28: 429c cmp r4, r3 8007c2a: bf08 it eq 8007c2c: 68ec ldreq r4, [r5, #12] 8007c2e: e7ca b.n 8007bc6 <__swbuf_r+0x1a> 8007c30: 4621 mov r1, r4 8007c32: 4628 mov r0, r5 8007c34: f000 f80c bl 8007c50 <__swsetup_r> 8007c38: 2800 cmp r0, #0 8007c3a: d0cb beq.n 8007bd4 <__swbuf_r+0x28> 8007c3c: f04f 37ff mov.w r7, #4294967295 ; 0xffffffff 8007c40: e7ea b.n 8007c18 <__swbuf_r+0x6c> 8007c42: bf00 nop 8007c44: 08008ef0 .word 0x08008ef0 8007c48: 08008f10 .word 0x08008f10 8007c4c: 08008ed0 .word 0x08008ed0 08007c50 <__swsetup_r>: 8007c50: 4b32 ldr r3, [pc, #200] ; (8007d1c <__swsetup_r+0xcc>) 8007c52: b570 push {r4, r5, r6, lr} 8007c54: 681d ldr r5, [r3, #0] 8007c56: 4606 mov r6, r0 8007c58: 460c mov r4, r1 8007c5a: b125 cbz r5, 8007c66 <__swsetup_r+0x16> 8007c5c: 69ab ldr r3, [r5, #24] 8007c5e: b913 cbnz r3, 8007c66 <__swsetup_r+0x16> 8007c60: 4628 mov r0, r5 8007c62: f000 f997 bl 8007f94 <__sinit> 8007c66: 4b2e ldr r3, [pc, #184] ; (8007d20 <__swsetup_r+0xd0>) 8007c68: 429c cmp r4, r3 8007c6a: d10f bne.n 8007c8c <__swsetup_r+0x3c> 8007c6c: 686c ldr r4, [r5, #4] 8007c6e: 89a3 ldrh r3, [r4, #12] 8007c70: f9b4 200c ldrsh.w r2, [r4, #12] 8007c74: 0719 lsls r1, r3, #28 8007c76: d42c bmi.n 8007cd2 <__swsetup_r+0x82> 8007c78: 06dd lsls r5, r3, #27 8007c7a: d411 bmi.n 8007ca0 <__swsetup_r+0x50> 8007c7c: 2309 movs r3, #9 8007c7e: 6033 str r3, [r6, #0] 8007c80: f042 0340 orr.w r3, r2, #64 ; 0x40 8007c84: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8007c88: 81a3 strh r3, [r4, #12] 8007c8a: e03e b.n 8007d0a <__swsetup_r+0xba> 8007c8c: 4b25 ldr r3, [pc, #148] ; (8007d24 <__swsetup_r+0xd4>) 8007c8e: 429c cmp r4, r3 8007c90: d101 bne.n 8007c96 <__swsetup_r+0x46> 8007c92: 68ac ldr r4, [r5, #8] 8007c94: e7eb b.n 8007c6e <__swsetup_r+0x1e> 8007c96: 4b24 ldr r3, [pc, #144] ; (8007d28 <__swsetup_r+0xd8>) 8007c98: 429c cmp r4, r3 8007c9a: bf08 it eq 8007c9c: 68ec ldreq r4, [r5, #12] 8007c9e: e7e6 b.n 8007c6e <__swsetup_r+0x1e> 8007ca0: 0758 lsls r0, r3, #29 8007ca2: d512 bpl.n 8007cca <__swsetup_r+0x7a> 8007ca4: 6b61 ldr r1, [r4, #52] ; 0x34 8007ca6: b141 cbz r1, 8007cba <__swsetup_r+0x6a> 8007ca8: f104 0344 add.w r3, r4, #68 ; 0x44 8007cac: 4299 cmp r1, r3 8007cae: d002 beq.n 8007cb6 <__swsetup_r+0x66> 8007cb0: 4630 mov r0, r6 8007cb2: f7ff fded bl 8007890 <_free_r> 8007cb6: 2300 movs r3, #0 8007cb8: 6363 str r3, [r4, #52] ; 0x34 8007cba: 89a3 ldrh r3, [r4, #12] 8007cbc: f023 0324 bic.w r3, r3, #36 ; 0x24 8007cc0: 81a3 strh r3, [r4, #12] 8007cc2: 2300 movs r3, #0 8007cc4: 6063 str r3, [r4, #4] 8007cc6: 6923 ldr r3, [r4, #16] 8007cc8: 6023 str r3, [r4, #0] 8007cca: 89a3 ldrh r3, [r4, #12] 8007ccc: f043 0308 orr.w r3, r3, #8 8007cd0: 81a3 strh r3, [r4, #12] 8007cd2: 6923 ldr r3, [r4, #16] 8007cd4: b94b cbnz r3, 8007cea <__swsetup_r+0x9a> 8007cd6: 89a3 ldrh r3, [r4, #12] 8007cd8: f403 7320 and.w r3, r3, #640 ; 0x280 8007cdc: f5b3 7f00 cmp.w r3, #512 ; 0x200 8007ce0: d003 beq.n 8007cea <__swsetup_r+0x9a> 8007ce2: 4621 mov r1, r4 8007ce4: 4630 mov r0, r6 8007ce6: f000 fa2d bl 8008144 <__smakebuf_r> 8007cea: 89a0 ldrh r0, [r4, #12] 8007cec: f9b4 200c ldrsh.w r2, [r4, #12] 8007cf0: f010 0301 ands.w r3, r0, #1 8007cf4: d00a beq.n 8007d0c <__swsetup_r+0xbc> 8007cf6: 2300 movs r3, #0 8007cf8: 60a3 str r3, [r4, #8] 8007cfa: 6963 ldr r3, [r4, #20] 8007cfc: 425b negs r3, r3 8007cfe: 61a3 str r3, [r4, #24] 8007d00: 6923 ldr r3, [r4, #16] 8007d02: b943 cbnz r3, 8007d16 <__swsetup_r+0xc6> 8007d04: f010 0080 ands.w r0, r0, #128 ; 0x80 8007d08: d1ba bne.n 8007c80 <__swsetup_r+0x30> 8007d0a: bd70 pop {r4, r5, r6, pc} 8007d0c: 0781 lsls r1, r0, #30 8007d0e: bf58 it pl 8007d10: 6963 ldrpl r3, [r4, #20] 8007d12: 60a3 str r3, [r4, #8] 8007d14: e7f4 b.n 8007d00 <__swsetup_r+0xb0> 8007d16: 2000 movs r0, #0 8007d18: e7f7 b.n 8007d0a <__swsetup_r+0xba> 8007d1a: bf00 nop 8007d1c: 2000000c .word 0x2000000c 8007d20: 08008ef0 .word 0x08008ef0 8007d24: 08008f10 .word 0x08008f10 8007d28: 08008ed0 .word 0x08008ed0 08007d2c <__assert_func>: 8007d2c: b51f push {r0, r1, r2, r3, r4, lr} 8007d2e: 4614 mov r4, r2 8007d30: 461a mov r2, r3 8007d32: 4b09 ldr r3, [pc, #36] ; (8007d58 <__assert_func+0x2c>) 8007d34: 4605 mov r5, r0 8007d36: 681b ldr r3, [r3, #0] 8007d38: 68d8 ldr r0, [r3, #12] 8007d3a: b14c cbz r4, 8007d50 <__assert_func+0x24> 8007d3c: 4b07 ldr r3, [pc, #28] ; (8007d5c <__assert_func+0x30>) 8007d3e: e9cd 3401 strd r3, r4, [sp, #4] 8007d42: 9100 str r1, [sp, #0] 8007d44: 462b mov r3, r5 8007d46: 4906 ldr r1, [pc, #24] ; (8007d60 <__assert_func+0x34>) 8007d48: f000 f9a2 bl 8008090 8007d4c: f000 fd8a bl 8008864 8007d50: 4b04 ldr r3, [pc, #16] ; (8007d64 <__assert_func+0x38>) 8007d52: 461c mov r4, r3 8007d54: e7f3 b.n 8007d3e <__assert_func+0x12> 8007d56: bf00 nop 8007d58: 2000000c .word 0x2000000c 8007d5c: 08008e94 .word 0x08008e94 8007d60: 08008ea1 .word 0x08008ea1 8007d64: 08008ecf .word 0x08008ecf 08007d68 <__sflush_r>: 8007d68: 898a ldrh r2, [r1, #12] 8007d6a: b5f8 push {r3, r4, r5, r6, r7, lr} 8007d6c: 4605 mov r5, r0 8007d6e: 0710 lsls r0, r2, #28 8007d70: 460c mov r4, r1 8007d72: d457 bmi.n 8007e24 <__sflush_r+0xbc> 8007d74: 684b ldr r3, [r1, #4] 8007d76: 2b00 cmp r3, #0 8007d78: dc04 bgt.n 8007d84 <__sflush_r+0x1c> 8007d7a: 6c0b ldr r3, [r1, #64] ; 0x40 8007d7c: 2b00 cmp r3, #0 8007d7e: dc01 bgt.n 8007d84 <__sflush_r+0x1c> 8007d80: 2000 movs r0, #0 8007d82: bdf8 pop {r3, r4, r5, r6, r7, pc} 8007d84: 6ae6 ldr r6, [r4, #44] ; 0x2c 8007d86: 2e00 cmp r6, #0 8007d88: d0fa beq.n 8007d80 <__sflush_r+0x18> 8007d8a: 2300 movs r3, #0 8007d8c: f412 5280 ands.w r2, r2, #4096 ; 0x1000 8007d90: 682f ldr r7, [r5, #0] 8007d92: 602b str r3, [r5, #0] 8007d94: d032 beq.n 8007dfc <__sflush_r+0x94> 8007d96: 6d60 ldr r0, [r4, #84] ; 0x54 8007d98: 89a3 ldrh r3, [r4, #12] 8007d9a: 075a lsls r2, r3, #29 8007d9c: d505 bpl.n 8007daa <__sflush_r+0x42> 8007d9e: 6863 ldr r3, [r4, #4] 8007da0: 1ac0 subs r0, r0, r3 8007da2: 6b63 ldr r3, [r4, #52] ; 0x34 8007da4: b10b cbz r3, 8007daa <__sflush_r+0x42> 8007da6: 6c23 ldr r3, [r4, #64] ; 0x40 8007da8: 1ac0 subs r0, r0, r3 8007daa: 2300 movs r3, #0 8007dac: 4602 mov r2, r0 8007dae: 6ae6 ldr r6, [r4, #44] ; 0x2c 8007db0: 4628 mov r0, r5 8007db2: 6a21 ldr r1, [r4, #32] 8007db4: 47b0 blx r6 8007db6: 1c43 adds r3, r0, #1 8007db8: 89a3 ldrh r3, [r4, #12] 8007dba: d106 bne.n 8007dca <__sflush_r+0x62> 8007dbc: 6829 ldr r1, [r5, #0] 8007dbe: 291d cmp r1, #29 8007dc0: d82c bhi.n 8007e1c <__sflush_r+0xb4> 8007dc2: 4a29 ldr r2, [pc, #164] ; (8007e68 <__sflush_r+0x100>) 8007dc4: 40ca lsrs r2, r1 8007dc6: 07d6 lsls r6, r2, #31 8007dc8: d528 bpl.n 8007e1c <__sflush_r+0xb4> 8007dca: 2200 movs r2, #0 8007dcc: 6062 str r2, [r4, #4] 8007dce: 6922 ldr r2, [r4, #16] 8007dd0: 04d9 lsls r1, r3, #19 8007dd2: 6022 str r2, [r4, #0] 8007dd4: d504 bpl.n 8007de0 <__sflush_r+0x78> 8007dd6: 1c42 adds r2, r0, #1 8007dd8: d101 bne.n 8007dde <__sflush_r+0x76> 8007dda: 682b ldr r3, [r5, #0] 8007ddc: b903 cbnz r3, 8007de0 <__sflush_r+0x78> 8007dde: 6560 str r0, [r4, #84] ; 0x54 8007de0: 6b61 ldr r1, [r4, #52] ; 0x34 8007de2: 602f str r7, [r5, #0] 8007de4: 2900 cmp r1, #0 8007de6: d0cb beq.n 8007d80 <__sflush_r+0x18> 8007de8: f104 0344 add.w r3, r4, #68 ; 0x44 8007dec: 4299 cmp r1, r3 8007dee: d002 beq.n 8007df6 <__sflush_r+0x8e> 8007df0: 4628 mov r0, r5 8007df2: f7ff fd4d bl 8007890 <_free_r> 8007df6: 2000 movs r0, #0 8007df8: 6360 str r0, [r4, #52] ; 0x34 8007dfa: e7c2 b.n 8007d82 <__sflush_r+0x1a> 8007dfc: 6a21 ldr r1, [r4, #32] 8007dfe: 2301 movs r3, #1 8007e00: 4628 mov r0, r5 8007e02: 47b0 blx r6 8007e04: 1c41 adds r1, r0, #1 8007e06: d1c7 bne.n 8007d98 <__sflush_r+0x30> 8007e08: 682b ldr r3, [r5, #0] 8007e0a: 2b00 cmp r3, #0 8007e0c: d0c4 beq.n 8007d98 <__sflush_r+0x30> 8007e0e: 2b1d cmp r3, #29 8007e10: d001 beq.n 8007e16 <__sflush_r+0xae> 8007e12: 2b16 cmp r3, #22 8007e14: d101 bne.n 8007e1a <__sflush_r+0xb2> 8007e16: 602f str r7, [r5, #0] 8007e18: e7b2 b.n 8007d80 <__sflush_r+0x18> 8007e1a: 89a3 ldrh r3, [r4, #12] 8007e1c: f043 0340 orr.w r3, r3, #64 ; 0x40 8007e20: 81a3 strh r3, [r4, #12] 8007e22: e7ae b.n 8007d82 <__sflush_r+0x1a> 8007e24: 690f ldr r7, [r1, #16] 8007e26: 2f00 cmp r7, #0 8007e28: d0aa beq.n 8007d80 <__sflush_r+0x18> 8007e2a: 0793 lsls r3, r2, #30 8007e2c: bf18 it ne 8007e2e: 2300 movne r3, #0 8007e30: 680e ldr r6, [r1, #0] 8007e32: bf08 it eq 8007e34: 694b ldreq r3, [r1, #20] 8007e36: 1bf6 subs r6, r6, r7 8007e38: 600f str r7, [r1, #0] 8007e3a: 608b str r3, [r1, #8] 8007e3c: 2e00 cmp r6, #0 8007e3e: dd9f ble.n 8007d80 <__sflush_r+0x18> 8007e40: 4633 mov r3, r6 8007e42: 463a mov r2, r7 8007e44: 4628 mov r0, r5 8007e46: 6a21 ldr r1, [r4, #32] 8007e48: f8d4 c028 ldr.w ip, [r4, #40] ; 0x28 8007e4c: 47e0 blx ip 8007e4e: 2800 cmp r0, #0 8007e50: dc06 bgt.n 8007e60 <__sflush_r+0xf8> 8007e52: 89a3 ldrh r3, [r4, #12] 8007e54: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8007e58: f043 0340 orr.w r3, r3, #64 ; 0x40 8007e5c: 81a3 strh r3, [r4, #12] 8007e5e: e790 b.n 8007d82 <__sflush_r+0x1a> 8007e60: 4407 add r7, r0 8007e62: 1a36 subs r6, r6, r0 8007e64: e7ea b.n 8007e3c <__sflush_r+0xd4> 8007e66: bf00 nop 8007e68: 20400001 .word 0x20400001 08007e6c <_fflush_r>: 8007e6c: b538 push {r3, r4, r5, lr} 8007e6e: 690b ldr r3, [r1, #16] 8007e70: 4605 mov r5, r0 8007e72: 460c mov r4, r1 8007e74: b913 cbnz r3, 8007e7c <_fflush_r+0x10> 8007e76: 2500 movs r5, #0 8007e78: 4628 mov r0, r5 8007e7a: bd38 pop {r3, r4, r5, pc} 8007e7c: b118 cbz r0, 8007e86 <_fflush_r+0x1a> 8007e7e: 6983 ldr r3, [r0, #24] 8007e80: b90b cbnz r3, 8007e86 <_fflush_r+0x1a> 8007e82: f000 f887 bl 8007f94 <__sinit> 8007e86: 4b14 ldr r3, [pc, #80] ; (8007ed8 <_fflush_r+0x6c>) 8007e88: 429c cmp r4, r3 8007e8a: d11b bne.n 8007ec4 <_fflush_r+0x58> 8007e8c: 686c ldr r4, [r5, #4] 8007e8e: f9b4 300c ldrsh.w r3, [r4, #12] 8007e92: 2b00 cmp r3, #0 8007e94: d0ef beq.n 8007e76 <_fflush_r+0xa> 8007e96: 6e62 ldr r2, [r4, #100] ; 0x64 8007e98: 07d0 lsls r0, r2, #31 8007e9a: d404 bmi.n 8007ea6 <_fflush_r+0x3a> 8007e9c: 0599 lsls r1, r3, #22 8007e9e: d402 bmi.n 8007ea6 <_fflush_r+0x3a> 8007ea0: 6da0 ldr r0, [r4, #88] ; 0x58 8007ea2: f000 f927 bl 80080f4 <__retarget_lock_acquire_recursive> 8007ea6: 4628 mov r0, r5 8007ea8: 4621 mov r1, r4 8007eaa: f7ff ff5d bl 8007d68 <__sflush_r> 8007eae: 6e63 ldr r3, [r4, #100] ; 0x64 8007eb0: 4605 mov r5, r0 8007eb2: 07da lsls r2, r3, #31 8007eb4: d4e0 bmi.n 8007e78 <_fflush_r+0xc> 8007eb6: 89a3 ldrh r3, [r4, #12] 8007eb8: 059b lsls r3, r3, #22 8007eba: d4dd bmi.n 8007e78 <_fflush_r+0xc> 8007ebc: 6da0 ldr r0, [r4, #88] ; 0x58 8007ebe: f000 f91a bl 80080f6 <__retarget_lock_release_recursive> 8007ec2: e7d9 b.n 8007e78 <_fflush_r+0xc> 8007ec4: 4b05 ldr r3, [pc, #20] ; (8007edc <_fflush_r+0x70>) 8007ec6: 429c cmp r4, r3 8007ec8: d101 bne.n 8007ece <_fflush_r+0x62> 8007eca: 68ac ldr r4, [r5, #8] 8007ecc: e7df b.n 8007e8e <_fflush_r+0x22> 8007ece: 4b04 ldr r3, [pc, #16] ; (8007ee0 <_fflush_r+0x74>) 8007ed0: 429c cmp r4, r3 8007ed2: bf08 it eq 8007ed4: 68ec ldreq r4, [r5, #12] 8007ed6: e7da b.n 8007e8e <_fflush_r+0x22> 8007ed8: 08008ef0 .word 0x08008ef0 8007edc: 08008f10 .word 0x08008f10 8007ee0: 08008ed0 .word 0x08008ed0 08007ee4 : 8007ee4: 2300 movs r3, #0 8007ee6: b510 push {r4, lr} 8007ee8: 4604 mov r4, r0 8007eea: e9c0 3300 strd r3, r3, [r0] 8007eee: e9c0 3304 strd r3, r3, [r0, #16] 8007ef2: 6083 str r3, [r0, #8] 8007ef4: 8181 strh r1, [r0, #12] 8007ef6: 6643 str r3, [r0, #100] ; 0x64 8007ef8: 81c2 strh r2, [r0, #14] 8007efa: 6183 str r3, [r0, #24] 8007efc: 4619 mov r1, r3 8007efe: 2208 movs r2, #8 8007f00: 305c adds r0, #92 ; 0x5c 8007f02: f7ff fcbd bl 8007880 8007f06: 4b05 ldr r3, [pc, #20] ; (8007f1c ) 8007f08: 6224 str r4, [r4, #32] 8007f0a: 6263 str r3, [r4, #36] ; 0x24 8007f0c: 4b04 ldr r3, [pc, #16] ; (8007f20 ) 8007f0e: 62a3 str r3, [r4, #40] ; 0x28 8007f10: 4b04 ldr r3, [pc, #16] ; (8007f24 ) 8007f12: 62e3 str r3, [r4, #44] ; 0x2c 8007f14: 4b04 ldr r3, [pc, #16] ; (8007f28 ) 8007f16: 6323 str r3, [r4, #48] ; 0x30 8007f18: bd10 pop {r4, pc} 8007f1a: bf00 nop 8007f1c: 080087b9 .word 0x080087b9 8007f20: 080087db .word 0x080087db 8007f24: 08008813 .word 0x08008813 8007f28: 08008837 .word 0x08008837 08007f2c <_cleanup_r>: 8007f2c: 4901 ldr r1, [pc, #4] ; (8007f34 <_cleanup_r+0x8>) 8007f2e: f000 b8c1 b.w 80080b4 <_fwalk_reent> 8007f32: bf00 nop 8007f34: 08007e6d .word 0x08007e6d 08007f38 <__sfmoreglue>: 8007f38: 2268 movs r2, #104 ; 0x68 8007f3a: b570 push {r4, r5, r6, lr} 8007f3c: 1e4d subs r5, r1, #1 8007f3e: 4355 muls r5, r2 8007f40: 460e mov r6, r1 8007f42: f105 0174 add.w r1, r5, #116 ; 0x74 8007f46: f7ff fd0b bl 8007960 <_malloc_r> 8007f4a: 4604 mov r4, r0 8007f4c: b140 cbz r0, 8007f60 <__sfmoreglue+0x28> 8007f4e: 2100 movs r1, #0 8007f50: e9c0 1600 strd r1, r6, [r0] 8007f54: 300c adds r0, #12 8007f56: 60a0 str r0, [r4, #8] 8007f58: f105 0268 add.w r2, r5, #104 ; 0x68 8007f5c: f7ff fc90 bl 8007880 8007f60: 4620 mov r0, r4 8007f62: bd70 pop {r4, r5, r6, pc} 08007f64 <__sfp_lock_acquire>: 8007f64: 4801 ldr r0, [pc, #4] ; (8007f6c <__sfp_lock_acquire+0x8>) 8007f66: f000 b8c5 b.w 80080f4 <__retarget_lock_acquire_recursive> 8007f6a: bf00 nop 8007f6c: 20003181 .word 0x20003181 08007f70 <__sfp_lock_release>: 8007f70: 4801 ldr r0, [pc, #4] ; (8007f78 <__sfp_lock_release+0x8>) 8007f72: f000 b8c0 b.w 80080f6 <__retarget_lock_release_recursive> 8007f76: bf00 nop 8007f78: 20003181 .word 0x20003181 08007f7c <__sinit_lock_acquire>: 8007f7c: 4801 ldr r0, [pc, #4] ; (8007f84 <__sinit_lock_acquire+0x8>) 8007f7e: f000 b8b9 b.w 80080f4 <__retarget_lock_acquire_recursive> 8007f82: bf00 nop 8007f84: 20003182 .word 0x20003182 08007f88 <__sinit_lock_release>: 8007f88: 4801 ldr r0, [pc, #4] ; (8007f90 <__sinit_lock_release+0x8>) 8007f8a: f000 b8b4 b.w 80080f6 <__retarget_lock_release_recursive> 8007f8e: bf00 nop 8007f90: 20003182 .word 0x20003182 08007f94 <__sinit>: 8007f94: b510 push {r4, lr} 8007f96: 4604 mov r4, r0 8007f98: f7ff fff0 bl 8007f7c <__sinit_lock_acquire> 8007f9c: 69a3 ldr r3, [r4, #24] 8007f9e: b11b cbz r3, 8007fa8 <__sinit+0x14> 8007fa0: e8bd 4010 ldmia.w sp!, {r4, lr} 8007fa4: f7ff bff0 b.w 8007f88 <__sinit_lock_release> 8007fa8: e9c4 3312 strd r3, r3, [r4, #72] ; 0x48 8007fac: 6523 str r3, [r4, #80] ; 0x50 8007fae: 4b13 ldr r3, [pc, #76] ; (8007ffc <__sinit+0x68>) 8007fb0: 4a13 ldr r2, [pc, #76] ; (8008000 <__sinit+0x6c>) 8007fb2: 681b ldr r3, [r3, #0] 8007fb4: 62a2 str r2, [r4, #40] ; 0x28 8007fb6: 42a3 cmp r3, r4 8007fb8: bf08 it eq 8007fba: 2301 moveq r3, #1 8007fbc: 4620 mov r0, r4 8007fbe: bf08 it eq 8007fc0: 61a3 streq r3, [r4, #24] 8007fc2: f000 f81f bl 8008004 <__sfp> 8007fc6: 6060 str r0, [r4, #4] 8007fc8: 4620 mov r0, r4 8007fca: f000 f81b bl 8008004 <__sfp> 8007fce: 60a0 str r0, [r4, #8] 8007fd0: 4620 mov r0, r4 8007fd2: f000 f817 bl 8008004 <__sfp> 8007fd6: 2200 movs r2, #0 8007fd8: 2104 movs r1, #4 8007fda: 60e0 str r0, [r4, #12] 8007fdc: 6860 ldr r0, [r4, #4] 8007fde: f7ff ff81 bl 8007ee4 8007fe2: 2201 movs r2, #1 8007fe4: 2109 movs r1, #9 8007fe6: 68a0 ldr r0, [r4, #8] 8007fe8: f7ff ff7c bl 8007ee4 8007fec: 2202 movs r2, #2 8007fee: 2112 movs r1, #18 8007ff0: 68e0 ldr r0, [r4, #12] 8007ff2: f7ff ff77 bl 8007ee4 8007ff6: 2301 movs r3, #1 8007ff8: 61a3 str r3, [r4, #24] 8007ffa: e7d1 b.n 8007fa0 <__sinit+0xc> 8007ffc: 08008e90 .word 0x08008e90 8008000: 08007f2d .word 0x08007f2d 08008004 <__sfp>: 8008004: b5f8 push {r3, r4, r5, r6, r7, lr} 8008006: 4607 mov r7, r0 8008008: f7ff ffac bl 8007f64 <__sfp_lock_acquire> 800800c: 4b1e ldr r3, [pc, #120] ; (8008088 <__sfp+0x84>) 800800e: 681e ldr r6, [r3, #0] 8008010: 69b3 ldr r3, [r6, #24] 8008012: b913 cbnz r3, 800801a <__sfp+0x16> 8008014: 4630 mov r0, r6 8008016: f7ff ffbd bl 8007f94 <__sinit> 800801a: 3648 adds r6, #72 ; 0x48 800801c: e9d6 3401 ldrd r3, r4, [r6, #4] 8008020: 3b01 subs r3, #1 8008022: d503 bpl.n 800802c <__sfp+0x28> 8008024: 6833 ldr r3, [r6, #0] 8008026: b30b cbz r3, 800806c <__sfp+0x68> 8008028: 6836 ldr r6, [r6, #0] 800802a: e7f7 b.n 800801c <__sfp+0x18> 800802c: f9b4 500c ldrsh.w r5, [r4, #12] 8008030: b9d5 cbnz r5, 8008068 <__sfp+0x64> 8008032: 4b16 ldr r3, [pc, #88] ; (800808c <__sfp+0x88>) 8008034: f104 0058 add.w r0, r4, #88 ; 0x58 8008038: 60e3 str r3, [r4, #12] 800803a: 6665 str r5, [r4, #100] ; 0x64 800803c: f000 f859 bl 80080f2 <__retarget_lock_init_recursive> 8008040: f7ff ff96 bl 8007f70 <__sfp_lock_release> 8008044: 2208 movs r2, #8 8008046: 4629 mov r1, r5 8008048: e9c4 5501 strd r5, r5, [r4, #4] 800804c: e9c4 5504 strd r5, r5, [r4, #16] 8008050: 6025 str r5, [r4, #0] 8008052: 61a5 str r5, [r4, #24] 8008054: f104 005c add.w r0, r4, #92 ; 0x5c 8008058: f7ff fc12 bl 8007880 800805c: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 8008060: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 8008064: 4620 mov r0, r4 8008066: bdf8 pop {r3, r4, r5, r6, r7, pc} 8008068: 3468 adds r4, #104 ; 0x68 800806a: e7d9 b.n 8008020 <__sfp+0x1c> 800806c: 2104 movs r1, #4 800806e: 4638 mov r0, r7 8008070: f7ff ff62 bl 8007f38 <__sfmoreglue> 8008074: 4604 mov r4, r0 8008076: 6030 str r0, [r6, #0] 8008078: 2800 cmp r0, #0 800807a: d1d5 bne.n 8008028 <__sfp+0x24> 800807c: f7ff ff78 bl 8007f70 <__sfp_lock_release> 8008080: 230c movs r3, #12 8008082: 603b str r3, [r7, #0] 8008084: e7ee b.n 8008064 <__sfp+0x60> 8008086: bf00 nop 8008088: 08008e90 .word 0x08008e90 800808c: ffff0001 .word 0xffff0001 08008090 : 8008090: b40e push {r1, r2, r3} 8008092: b503 push {r0, r1, lr} 8008094: 4601 mov r1, r0 8008096: ab03 add r3, sp, #12 8008098: 4805 ldr r0, [pc, #20] ; (80080b0 ) 800809a: f853 2b04 ldr.w r2, [r3], #4 800809e: 6800 ldr r0, [r0, #0] 80080a0: 9301 str r3, [sp, #4] 80080a2: f000 f8c3 bl 800822c <_vfiprintf_r> 80080a6: b002 add sp, #8 80080a8: f85d eb04 ldr.w lr, [sp], #4 80080ac: b003 add sp, #12 80080ae: 4770 bx lr 80080b0: 2000000c .word 0x2000000c 080080b4 <_fwalk_reent>: 80080b4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 80080b8: 4606 mov r6, r0 80080ba: 4688 mov r8, r1 80080bc: 2700 movs r7, #0 80080be: f100 0448 add.w r4, r0, #72 ; 0x48 80080c2: e9d4 9501 ldrd r9, r5, [r4, #4] 80080c6: f1b9 0901 subs.w r9, r9, #1 80080ca: d505 bpl.n 80080d8 <_fwalk_reent+0x24> 80080cc: 6824 ldr r4, [r4, #0] 80080ce: 2c00 cmp r4, #0 80080d0: d1f7 bne.n 80080c2 <_fwalk_reent+0xe> 80080d2: 4638 mov r0, r7 80080d4: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 80080d8: 89ab ldrh r3, [r5, #12] 80080da: 2b01 cmp r3, #1 80080dc: d907 bls.n 80080ee <_fwalk_reent+0x3a> 80080de: f9b5 300e ldrsh.w r3, [r5, #14] 80080e2: 3301 adds r3, #1 80080e4: d003 beq.n 80080ee <_fwalk_reent+0x3a> 80080e6: 4629 mov r1, r5 80080e8: 4630 mov r0, r6 80080ea: 47c0 blx r8 80080ec: 4307 orrs r7, r0 80080ee: 3568 adds r5, #104 ; 0x68 80080f0: e7e9 b.n 80080c6 <_fwalk_reent+0x12> 080080f2 <__retarget_lock_init_recursive>: 80080f2: 4770 bx lr 080080f4 <__retarget_lock_acquire_recursive>: 80080f4: 4770 bx lr 080080f6 <__retarget_lock_release_recursive>: 80080f6: 4770 bx lr 080080f8 <__swhatbuf_r>: 80080f8: b570 push {r4, r5, r6, lr} 80080fa: 460e mov r6, r1 80080fc: f9b1 100e ldrsh.w r1, [r1, #14] 8008100: 4614 mov r4, r2 8008102: 2900 cmp r1, #0 8008104: 461d mov r5, r3 8008106: b096 sub sp, #88 ; 0x58 8008108: da08 bge.n 800811c <__swhatbuf_r+0x24> 800810a: 2200 movs r2, #0 800810c: f9b6 300c ldrsh.w r3, [r6, #12] 8008110: 602a str r2, [r5, #0] 8008112: 061a lsls r2, r3, #24 8008114: d410 bmi.n 8008138 <__swhatbuf_r+0x40> 8008116: f44f 6380 mov.w r3, #1024 ; 0x400 800811a: e00e b.n 800813a <__swhatbuf_r+0x42> 800811c: 466a mov r2, sp 800811e: f000 fbb9 bl 8008894 <_fstat_r> 8008122: 2800 cmp r0, #0 8008124: dbf1 blt.n 800810a <__swhatbuf_r+0x12> 8008126: 9a01 ldr r2, [sp, #4] 8008128: f402 4270 and.w r2, r2, #61440 ; 0xf000 800812c: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 8008130: 425a negs r2, r3 8008132: 415a adcs r2, r3 8008134: 602a str r2, [r5, #0] 8008136: e7ee b.n 8008116 <__swhatbuf_r+0x1e> 8008138: 2340 movs r3, #64 ; 0x40 800813a: 2000 movs r0, #0 800813c: 6023 str r3, [r4, #0] 800813e: b016 add sp, #88 ; 0x58 8008140: bd70 pop {r4, r5, r6, pc} ... 08008144 <__smakebuf_r>: 8008144: 898b ldrh r3, [r1, #12] 8008146: b573 push {r0, r1, r4, r5, r6, lr} 8008148: 079d lsls r5, r3, #30 800814a: 4606 mov r6, r0 800814c: 460c mov r4, r1 800814e: d507 bpl.n 8008160 <__smakebuf_r+0x1c> 8008150: f104 0347 add.w r3, r4, #71 ; 0x47 8008154: 6023 str r3, [r4, #0] 8008156: 6123 str r3, [r4, #16] 8008158: 2301 movs r3, #1 800815a: 6163 str r3, [r4, #20] 800815c: b002 add sp, #8 800815e: bd70 pop {r4, r5, r6, pc} 8008160: 466a mov r2, sp 8008162: ab01 add r3, sp, #4 8008164: f7ff ffc8 bl 80080f8 <__swhatbuf_r> 8008168: 9900 ldr r1, [sp, #0] 800816a: 4605 mov r5, r0 800816c: 4630 mov r0, r6 800816e: f7ff fbf7 bl 8007960 <_malloc_r> 8008172: b948 cbnz r0, 8008188 <__smakebuf_r+0x44> 8008174: f9b4 300c ldrsh.w r3, [r4, #12] 8008178: 059a lsls r2, r3, #22 800817a: d4ef bmi.n 800815c <__smakebuf_r+0x18> 800817c: f023 0303 bic.w r3, r3, #3 8008180: f043 0302 orr.w r3, r3, #2 8008184: 81a3 strh r3, [r4, #12] 8008186: e7e3 b.n 8008150 <__smakebuf_r+0xc> 8008188: 4b0d ldr r3, [pc, #52] ; (80081c0 <__smakebuf_r+0x7c>) 800818a: 62b3 str r3, [r6, #40] ; 0x28 800818c: 89a3 ldrh r3, [r4, #12] 800818e: 6020 str r0, [r4, #0] 8008190: f043 0380 orr.w r3, r3, #128 ; 0x80 8008194: 81a3 strh r3, [r4, #12] 8008196: 9b00 ldr r3, [sp, #0] 8008198: 6120 str r0, [r4, #16] 800819a: 6163 str r3, [r4, #20] 800819c: 9b01 ldr r3, [sp, #4] 800819e: b15b cbz r3, 80081b8 <__smakebuf_r+0x74> 80081a0: 4630 mov r0, r6 80081a2: f9b4 100e ldrsh.w r1, [r4, #14] 80081a6: f000 fb87 bl 80088b8 <_isatty_r> 80081aa: b128 cbz r0, 80081b8 <__smakebuf_r+0x74> 80081ac: 89a3 ldrh r3, [r4, #12] 80081ae: f023 0303 bic.w r3, r3, #3 80081b2: f043 0301 orr.w r3, r3, #1 80081b6: 81a3 strh r3, [r4, #12] 80081b8: 89a0 ldrh r0, [r4, #12] 80081ba: 4305 orrs r5, r0 80081bc: 81a5 strh r5, [r4, #12] 80081be: e7cd b.n 800815c <__smakebuf_r+0x18> 80081c0: 08007f2d .word 0x08007f2d 080081c4 <__malloc_lock>: 80081c4: 4801 ldr r0, [pc, #4] ; (80081cc <__malloc_lock+0x8>) 80081c6: f7ff bf95 b.w 80080f4 <__retarget_lock_acquire_recursive> 80081ca: bf00 nop 80081cc: 20003180 .word 0x20003180 080081d0 <__malloc_unlock>: 80081d0: 4801 ldr r0, [pc, #4] ; (80081d8 <__malloc_unlock+0x8>) 80081d2: f7ff bf90 b.w 80080f6 <__retarget_lock_release_recursive> 80081d6: bf00 nop 80081d8: 20003180 .word 0x20003180 080081dc <__sfputc_r>: 80081dc: 6893 ldr r3, [r2, #8] 80081de: b410 push {r4} 80081e0: 3b01 subs r3, #1 80081e2: 2b00 cmp r3, #0 80081e4: 6093 str r3, [r2, #8] 80081e6: da07 bge.n 80081f8 <__sfputc_r+0x1c> 80081e8: 6994 ldr r4, [r2, #24] 80081ea: 42a3 cmp r3, r4 80081ec: db01 blt.n 80081f2 <__sfputc_r+0x16> 80081ee: 290a cmp r1, #10 80081f0: d102 bne.n 80081f8 <__sfputc_r+0x1c> 80081f2: bc10 pop {r4} 80081f4: f7ff bcda b.w 8007bac <__swbuf_r> 80081f8: 6813 ldr r3, [r2, #0] 80081fa: 1c58 adds r0, r3, #1 80081fc: 6010 str r0, [r2, #0] 80081fe: 7019 strb r1, [r3, #0] 8008200: 4608 mov r0, r1 8008202: bc10 pop {r4} 8008204: 4770 bx lr 08008206 <__sfputs_r>: 8008206: b5f8 push {r3, r4, r5, r6, r7, lr} 8008208: 4606 mov r6, r0 800820a: 460f mov r7, r1 800820c: 4614 mov r4, r2 800820e: 18d5 adds r5, r2, r3 8008210: 42ac cmp r4, r5 8008212: d101 bne.n 8008218 <__sfputs_r+0x12> 8008214: 2000 movs r0, #0 8008216: e007 b.n 8008228 <__sfputs_r+0x22> 8008218: 463a mov r2, r7 800821a: 4630 mov r0, r6 800821c: f814 1b01 ldrb.w r1, [r4], #1 8008220: f7ff ffdc bl 80081dc <__sfputc_r> 8008224: 1c43 adds r3, r0, #1 8008226: d1f3 bne.n 8008210 <__sfputs_r+0xa> 8008228: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 0800822c <_vfiprintf_r>: 800822c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8008230: 460d mov r5, r1 8008232: 4614 mov r4, r2 8008234: 4698 mov r8, r3 8008236: 4606 mov r6, r0 8008238: b09d sub sp, #116 ; 0x74 800823a: b118 cbz r0, 8008244 <_vfiprintf_r+0x18> 800823c: 6983 ldr r3, [r0, #24] 800823e: b90b cbnz r3, 8008244 <_vfiprintf_r+0x18> 8008240: f7ff fea8 bl 8007f94 <__sinit> 8008244: 4b89 ldr r3, [pc, #548] ; (800846c <_vfiprintf_r+0x240>) 8008246: 429d cmp r5, r3 8008248: d11b bne.n 8008282 <_vfiprintf_r+0x56> 800824a: 6875 ldr r5, [r6, #4] 800824c: 6e6b ldr r3, [r5, #100] ; 0x64 800824e: 07d9 lsls r1, r3, #31 8008250: d405 bmi.n 800825e <_vfiprintf_r+0x32> 8008252: 89ab ldrh r3, [r5, #12] 8008254: 059a lsls r2, r3, #22 8008256: d402 bmi.n 800825e <_vfiprintf_r+0x32> 8008258: 6da8 ldr r0, [r5, #88] ; 0x58 800825a: f7ff ff4b bl 80080f4 <__retarget_lock_acquire_recursive> 800825e: 89ab ldrh r3, [r5, #12] 8008260: 071b lsls r3, r3, #28 8008262: d501 bpl.n 8008268 <_vfiprintf_r+0x3c> 8008264: 692b ldr r3, [r5, #16] 8008266: b9eb cbnz r3, 80082a4 <_vfiprintf_r+0x78> 8008268: 4629 mov r1, r5 800826a: 4630 mov r0, r6 800826c: f7ff fcf0 bl 8007c50 <__swsetup_r> 8008270: b1c0 cbz r0, 80082a4 <_vfiprintf_r+0x78> 8008272: 6e6b ldr r3, [r5, #100] ; 0x64 8008274: 07dc lsls r4, r3, #31 8008276: d50e bpl.n 8008296 <_vfiprintf_r+0x6a> 8008278: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800827c: b01d add sp, #116 ; 0x74 800827e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8008282: 4b7b ldr r3, [pc, #492] ; (8008470 <_vfiprintf_r+0x244>) 8008284: 429d cmp r5, r3 8008286: d101 bne.n 800828c <_vfiprintf_r+0x60> 8008288: 68b5 ldr r5, [r6, #8] 800828a: e7df b.n 800824c <_vfiprintf_r+0x20> 800828c: 4b79 ldr r3, [pc, #484] ; (8008474 <_vfiprintf_r+0x248>) 800828e: 429d cmp r5, r3 8008290: bf08 it eq 8008292: 68f5 ldreq r5, [r6, #12] 8008294: e7da b.n 800824c <_vfiprintf_r+0x20> 8008296: 89ab ldrh r3, [r5, #12] 8008298: 0598 lsls r0, r3, #22 800829a: d4ed bmi.n 8008278 <_vfiprintf_r+0x4c> 800829c: 6da8 ldr r0, [r5, #88] ; 0x58 800829e: f7ff ff2a bl 80080f6 <__retarget_lock_release_recursive> 80082a2: e7e9 b.n 8008278 <_vfiprintf_r+0x4c> 80082a4: 2300 movs r3, #0 80082a6: 9309 str r3, [sp, #36] ; 0x24 80082a8: 2320 movs r3, #32 80082aa: f88d 3029 strb.w r3, [sp, #41] ; 0x29 80082ae: 2330 movs r3, #48 ; 0x30 80082b0: f04f 0901 mov.w r9, #1 80082b4: f8cd 800c str.w r8, [sp, #12] 80082b8: f8df 81bc ldr.w r8, [pc, #444] ; 8008478 <_vfiprintf_r+0x24c> 80082bc: f88d 302a strb.w r3, [sp, #42] ; 0x2a 80082c0: 4623 mov r3, r4 80082c2: 469a mov sl, r3 80082c4: f813 2b01 ldrb.w r2, [r3], #1 80082c8: b10a cbz r2, 80082ce <_vfiprintf_r+0xa2> 80082ca: 2a25 cmp r2, #37 ; 0x25 80082cc: d1f9 bne.n 80082c2 <_vfiprintf_r+0x96> 80082ce: ebba 0b04 subs.w fp, sl, r4 80082d2: d00b beq.n 80082ec <_vfiprintf_r+0xc0> 80082d4: 465b mov r3, fp 80082d6: 4622 mov r2, r4 80082d8: 4629 mov r1, r5 80082da: 4630 mov r0, r6 80082dc: f7ff ff93 bl 8008206 <__sfputs_r> 80082e0: 3001 adds r0, #1 80082e2: f000 80aa beq.w 800843a <_vfiprintf_r+0x20e> 80082e6: 9a09 ldr r2, [sp, #36] ; 0x24 80082e8: 445a add r2, fp 80082ea: 9209 str r2, [sp, #36] ; 0x24 80082ec: f89a 3000 ldrb.w r3, [sl] 80082f0: 2b00 cmp r3, #0 80082f2: f000 80a2 beq.w 800843a <_vfiprintf_r+0x20e> 80082f6: 2300 movs r3, #0 80082f8: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 80082fc: e9cd 2305 strd r2, r3, [sp, #20] 8008300: f10a 0a01 add.w sl, sl, #1 8008304: 9304 str r3, [sp, #16] 8008306: 9307 str r3, [sp, #28] 8008308: f88d 3053 strb.w r3, [sp, #83] ; 0x53 800830c: 931a str r3, [sp, #104] ; 0x68 800830e: 4654 mov r4, sl 8008310: 2205 movs r2, #5 8008312: f814 1b01 ldrb.w r1, [r4], #1 8008316: 4858 ldr r0, [pc, #352] ; (8008478 <_vfiprintf_r+0x24c>) 8008318: f000 faf0 bl 80088fc 800831c: 9a04 ldr r2, [sp, #16] 800831e: b9d8 cbnz r0, 8008358 <_vfiprintf_r+0x12c> 8008320: 06d1 lsls r1, r2, #27 8008322: bf44 itt mi 8008324: 2320 movmi r3, #32 8008326: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 800832a: 0713 lsls r3, r2, #28 800832c: bf44 itt mi 800832e: 232b movmi r3, #43 ; 0x2b 8008330: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 8008334: f89a 3000 ldrb.w r3, [sl] 8008338: 2b2a cmp r3, #42 ; 0x2a 800833a: d015 beq.n 8008368 <_vfiprintf_r+0x13c> 800833c: 4654 mov r4, sl 800833e: 2000 movs r0, #0 8008340: f04f 0c0a mov.w ip, #10 8008344: 9a07 ldr r2, [sp, #28] 8008346: 4621 mov r1, r4 8008348: f811 3b01 ldrb.w r3, [r1], #1 800834c: 3b30 subs r3, #48 ; 0x30 800834e: 2b09 cmp r3, #9 8008350: d94e bls.n 80083f0 <_vfiprintf_r+0x1c4> 8008352: b1b0 cbz r0, 8008382 <_vfiprintf_r+0x156> 8008354: 9207 str r2, [sp, #28] 8008356: e014 b.n 8008382 <_vfiprintf_r+0x156> 8008358: eba0 0308 sub.w r3, r0, r8 800835c: fa09 f303 lsl.w r3, r9, r3 8008360: 4313 orrs r3, r2 8008362: 46a2 mov sl, r4 8008364: 9304 str r3, [sp, #16] 8008366: e7d2 b.n 800830e <_vfiprintf_r+0xe2> 8008368: 9b03 ldr r3, [sp, #12] 800836a: 1d19 adds r1, r3, #4 800836c: 681b ldr r3, [r3, #0] 800836e: 9103 str r1, [sp, #12] 8008370: 2b00 cmp r3, #0 8008372: bfbb ittet lt 8008374: 425b neglt r3, r3 8008376: f042 0202 orrlt.w r2, r2, #2 800837a: 9307 strge r3, [sp, #28] 800837c: 9307 strlt r3, [sp, #28] 800837e: bfb8 it lt 8008380: 9204 strlt r2, [sp, #16] 8008382: 7823 ldrb r3, [r4, #0] 8008384: 2b2e cmp r3, #46 ; 0x2e 8008386: d10c bne.n 80083a2 <_vfiprintf_r+0x176> 8008388: 7863 ldrb r3, [r4, #1] 800838a: 2b2a cmp r3, #42 ; 0x2a 800838c: d135 bne.n 80083fa <_vfiprintf_r+0x1ce> 800838e: 9b03 ldr r3, [sp, #12] 8008390: 3402 adds r4, #2 8008392: 1d1a adds r2, r3, #4 8008394: 681b ldr r3, [r3, #0] 8008396: 9203 str r2, [sp, #12] 8008398: 2b00 cmp r3, #0 800839a: bfb8 it lt 800839c: f04f 33ff movlt.w r3, #4294967295 ; 0xffffffff 80083a0: 9305 str r3, [sp, #20] 80083a2: f8df a0d8 ldr.w sl, [pc, #216] ; 800847c <_vfiprintf_r+0x250> 80083a6: 2203 movs r2, #3 80083a8: 4650 mov r0, sl 80083aa: 7821 ldrb r1, [r4, #0] 80083ac: f000 faa6 bl 80088fc 80083b0: b140 cbz r0, 80083c4 <_vfiprintf_r+0x198> 80083b2: 2340 movs r3, #64 ; 0x40 80083b4: eba0 000a sub.w r0, r0, sl 80083b8: fa03 f000 lsl.w r0, r3, r0 80083bc: 9b04 ldr r3, [sp, #16] 80083be: 3401 adds r4, #1 80083c0: 4303 orrs r3, r0 80083c2: 9304 str r3, [sp, #16] 80083c4: f814 1b01 ldrb.w r1, [r4], #1 80083c8: 2206 movs r2, #6 80083ca: 482d ldr r0, [pc, #180] ; (8008480 <_vfiprintf_r+0x254>) 80083cc: f88d 1028 strb.w r1, [sp, #40] ; 0x28 80083d0: f000 fa94 bl 80088fc 80083d4: 2800 cmp r0, #0 80083d6: d03f beq.n 8008458 <_vfiprintf_r+0x22c> 80083d8: 4b2a ldr r3, [pc, #168] ; (8008484 <_vfiprintf_r+0x258>) 80083da: bb1b cbnz r3, 8008424 <_vfiprintf_r+0x1f8> 80083dc: 9b03 ldr r3, [sp, #12] 80083de: 3307 adds r3, #7 80083e0: f023 0307 bic.w r3, r3, #7 80083e4: 3308 adds r3, #8 80083e6: 9303 str r3, [sp, #12] 80083e8: 9b09 ldr r3, [sp, #36] ; 0x24 80083ea: 443b add r3, r7 80083ec: 9309 str r3, [sp, #36] ; 0x24 80083ee: e767 b.n 80082c0 <_vfiprintf_r+0x94> 80083f0: 460c mov r4, r1 80083f2: 2001 movs r0, #1 80083f4: fb0c 3202 mla r2, ip, r2, r3 80083f8: e7a5 b.n 8008346 <_vfiprintf_r+0x11a> 80083fa: 2300 movs r3, #0 80083fc: f04f 0c0a mov.w ip, #10 8008400: 4619 mov r1, r3 8008402: 3401 adds r4, #1 8008404: 9305 str r3, [sp, #20] 8008406: 4620 mov r0, r4 8008408: f810 2b01 ldrb.w r2, [r0], #1 800840c: 3a30 subs r2, #48 ; 0x30 800840e: 2a09 cmp r2, #9 8008410: d903 bls.n 800841a <_vfiprintf_r+0x1ee> 8008412: 2b00 cmp r3, #0 8008414: d0c5 beq.n 80083a2 <_vfiprintf_r+0x176> 8008416: 9105 str r1, [sp, #20] 8008418: e7c3 b.n 80083a2 <_vfiprintf_r+0x176> 800841a: 4604 mov r4, r0 800841c: 2301 movs r3, #1 800841e: fb0c 2101 mla r1, ip, r1, r2 8008422: e7f0 b.n 8008406 <_vfiprintf_r+0x1da> 8008424: ab03 add r3, sp, #12 8008426: 9300 str r3, [sp, #0] 8008428: 462a mov r2, r5 800842a: 4630 mov r0, r6 800842c: 4b16 ldr r3, [pc, #88] ; (8008488 <_vfiprintf_r+0x25c>) 800842e: a904 add r1, sp, #16 8008430: f3af 8000 nop.w 8008434: 4607 mov r7, r0 8008436: 1c78 adds r0, r7, #1 8008438: d1d6 bne.n 80083e8 <_vfiprintf_r+0x1bc> 800843a: 6e6b ldr r3, [r5, #100] ; 0x64 800843c: 07d9 lsls r1, r3, #31 800843e: d405 bmi.n 800844c <_vfiprintf_r+0x220> 8008440: 89ab ldrh r3, [r5, #12] 8008442: 059a lsls r2, r3, #22 8008444: d402 bmi.n 800844c <_vfiprintf_r+0x220> 8008446: 6da8 ldr r0, [r5, #88] ; 0x58 8008448: f7ff fe55 bl 80080f6 <__retarget_lock_release_recursive> 800844c: 89ab ldrh r3, [r5, #12] 800844e: 065b lsls r3, r3, #25 8008450: f53f af12 bmi.w 8008278 <_vfiprintf_r+0x4c> 8008454: 9809 ldr r0, [sp, #36] ; 0x24 8008456: e711 b.n 800827c <_vfiprintf_r+0x50> 8008458: ab03 add r3, sp, #12 800845a: 9300 str r3, [sp, #0] 800845c: 462a mov r2, r5 800845e: 4630 mov r0, r6 8008460: 4b09 ldr r3, [pc, #36] ; (8008488 <_vfiprintf_r+0x25c>) 8008462: a904 add r1, sp, #16 8008464: f000 f882 bl 800856c <_printf_i> 8008468: e7e4 b.n 8008434 <_vfiprintf_r+0x208> 800846a: bf00 nop 800846c: 08008ef0 .word 0x08008ef0 8008470: 08008f10 .word 0x08008f10 8008474: 08008ed0 .word 0x08008ed0 8008478: 08008f30 .word 0x08008f30 800847c: 08008f36 .word 0x08008f36 8008480: 08008f3a .word 0x08008f3a 8008484: 00000000 .word 0x00000000 8008488: 08008207 .word 0x08008207 0800848c <_printf_common>: 800848c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8008490: 4616 mov r6, r2 8008492: 4699 mov r9, r3 8008494: 688a ldr r2, [r1, #8] 8008496: 690b ldr r3, [r1, #16] 8008498: 4607 mov r7, r0 800849a: 4293 cmp r3, r2 800849c: bfb8 it lt 800849e: 4613 movlt r3, r2 80084a0: 6033 str r3, [r6, #0] 80084a2: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 80084a6: 460c mov r4, r1 80084a8: f8dd 8020 ldr.w r8, [sp, #32] 80084ac: b10a cbz r2, 80084b2 <_printf_common+0x26> 80084ae: 3301 adds r3, #1 80084b0: 6033 str r3, [r6, #0] 80084b2: 6823 ldr r3, [r4, #0] 80084b4: 0699 lsls r1, r3, #26 80084b6: bf42 ittt mi 80084b8: 6833 ldrmi r3, [r6, #0] 80084ba: 3302 addmi r3, #2 80084bc: 6033 strmi r3, [r6, #0] 80084be: 6825 ldr r5, [r4, #0] 80084c0: f015 0506 ands.w r5, r5, #6 80084c4: d106 bne.n 80084d4 <_printf_common+0x48> 80084c6: f104 0a19 add.w sl, r4, #25 80084ca: 68e3 ldr r3, [r4, #12] 80084cc: 6832 ldr r2, [r6, #0] 80084ce: 1a9b subs r3, r3, r2 80084d0: 42ab cmp r3, r5 80084d2: dc28 bgt.n 8008526 <_printf_common+0x9a> 80084d4: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 80084d8: 1e13 subs r3, r2, #0 80084da: 6822 ldr r2, [r4, #0] 80084dc: bf18 it ne 80084de: 2301 movne r3, #1 80084e0: 0692 lsls r2, r2, #26 80084e2: d42d bmi.n 8008540 <_printf_common+0xb4> 80084e4: 4649 mov r1, r9 80084e6: 4638 mov r0, r7 80084e8: f104 0243 add.w r2, r4, #67 ; 0x43 80084ec: 47c0 blx r8 80084ee: 3001 adds r0, #1 80084f0: d020 beq.n 8008534 <_printf_common+0xa8> 80084f2: 6823 ldr r3, [r4, #0] 80084f4: 68e5 ldr r5, [r4, #12] 80084f6: f003 0306 and.w r3, r3, #6 80084fa: 2b04 cmp r3, #4 80084fc: bf18 it ne 80084fe: 2500 movne r5, #0 8008500: 6832 ldr r2, [r6, #0] 8008502: f04f 0600 mov.w r6, #0 8008506: 68a3 ldr r3, [r4, #8] 8008508: bf08 it eq 800850a: 1aad subeq r5, r5, r2 800850c: 6922 ldr r2, [r4, #16] 800850e: bf08 it eq 8008510: ea25 75e5 biceq.w r5, r5, r5, asr #31 8008514: 4293 cmp r3, r2 8008516: bfc4 itt gt 8008518: 1a9b subgt r3, r3, r2 800851a: 18ed addgt r5, r5, r3 800851c: 341a adds r4, #26 800851e: 42b5 cmp r5, r6 8008520: d11a bne.n 8008558 <_printf_common+0xcc> 8008522: 2000 movs r0, #0 8008524: e008 b.n 8008538 <_printf_common+0xac> 8008526: 2301 movs r3, #1 8008528: 4652 mov r2, sl 800852a: 4649 mov r1, r9 800852c: 4638 mov r0, r7 800852e: 47c0 blx r8 8008530: 3001 adds r0, #1 8008532: d103 bne.n 800853c <_printf_common+0xb0> 8008534: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8008538: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800853c: 3501 adds r5, #1 800853e: e7c4 b.n 80084ca <_printf_common+0x3e> 8008540: 2030 movs r0, #48 ; 0x30 8008542: 18e1 adds r1, r4, r3 8008544: f881 0043 strb.w r0, [r1, #67] ; 0x43 8008548: 1c5a adds r2, r3, #1 800854a: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 800854e: 4422 add r2, r4 8008550: 3302 adds r3, #2 8008552: f882 1043 strb.w r1, [r2, #67] ; 0x43 8008556: e7c5 b.n 80084e4 <_printf_common+0x58> 8008558: 2301 movs r3, #1 800855a: 4622 mov r2, r4 800855c: 4649 mov r1, r9 800855e: 4638 mov r0, r7 8008560: 47c0 blx r8 8008562: 3001 adds r0, #1 8008564: d0e6 beq.n 8008534 <_printf_common+0xa8> 8008566: 3601 adds r6, #1 8008568: e7d9 b.n 800851e <_printf_common+0x92> ... 0800856c <_printf_i>: 800856c: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 8008570: 7e0f ldrb r7, [r1, #24] 8008572: 4691 mov r9, r2 8008574: 2f78 cmp r7, #120 ; 0x78 8008576: 4680 mov r8, r0 8008578: 460c mov r4, r1 800857a: 469a mov sl, r3 800857c: 9d0c ldr r5, [sp, #48] ; 0x30 800857e: f101 0243 add.w r2, r1, #67 ; 0x43 8008582: d807 bhi.n 8008594 <_printf_i+0x28> 8008584: 2f62 cmp r7, #98 ; 0x62 8008586: d80a bhi.n 800859e <_printf_i+0x32> 8008588: 2f00 cmp r7, #0 800858a: f000 80d9 beq.w 8008740 <_printf_i+0x1d4> 800858e: 2f58 cmp r7, #88 ; 0x58 8008590: f000 80a4 beq.w 80086dc <_printf_i+0x170> 8008594: f104 0542 add.w r5, r4, #66 ; 0x42 8008598: f884 7042 strb.w r7, [r4, #66] ; 0x42 800859c: e03a b.n 8008614 <_printf_i+0xa8> 800859e: f1a7 0363 sub.w r3, r7, #99 ; 0x63 80085a2: 2b15 cmp r3, #21 80085a4: d8f6 bhi.n 8008594 <_printf_i+0x28> 80085a6: a101 add r1, pc, #4 ; (adr r1, 80085ac <_printf_i+0x40>) 80085a8: f851 f023 ldr.w pc, [r1, r3, lsl #2] 80085ac: 08008605 .word 0x08008605 80085b0: 08008619 .word 0x08008619 80085b4: 08008595 .word 0x08008595 80085b8: 08008595 .word 0x08008595 80085bc: 08008595 .word 0x08008595 80085c0: 08008595 .word 0x08008595 80085c4: 08008619 .word 0x08008619 80085c8: 08008595 .word 0x08008595 80085cc: 08008595 .word 0x08008595 80085d0: 08008595 .word 0x08008595 80085d4: 08008595 .word 0x08008595 80085d8: 08008727 .word 0x08008727 80085dc: 08008649 .word 0x08008649 80085e0: 08008709 .word 0x08008709 80085e4: 08008595 .word 0x08008595 80085e8: 08008595 .word 0x08008595 80085ec: 08008749 .word 0x08008749 80085f0: 08008595 .word 0x08008595 80085f4: 08008649 .word 0x08008649 80085f8: 08008595 .word 0x08008595 80085fc: 08008595 .word 0x08008595 8008600: 08008711 .word 0x08008711 8008604: 682b ldr r3, [r5, #0] 8008606: 1d1a adds r2, r3, #4 8008608: 681b ldr r3, [r3, #0] 800860a: 602a str r2, [r5, #0] 800860c: f104 0542 add.w r5, r4, #66 ; 0x42 8008610: f884 3042 strb.w r3, [r4, #66] ; 0x42 8008614: 2301 movs r3, #1 8008616: e0a4 b.n 8008762 <_printf_i+0x1f6> 8008618: 6820 ldr r0, [r4, #0] 800861a: 6829 ldr r1, [r5, #0] 800861c: 0606 lsls r6, r0, #24 800861e: f101 0304 add.w r3, r1, #4 8008622: d50a bpl.n 800863a <_printf_i+0xce> 8008624: 680e ldr r6, [r1, #0] 8008626: 602b str r3, [r5, #0] 8008628: 2e00 cmp r6, #0 800862a: da03 bge.n 8008634 <_printf_i+0xc8> 800862c: 232d movs r3, #45 ; 0x2d 800862e: 4276 negs r6, r6 8008630: f884 3043 strb.w r3, [r4, #67] ; 0x43 8008634: 230a movs r3, #10 8008636: 485e ldr r0, [pc, #376] ; (80087b0 <_printf_i+0x244>) 8008638: e019 b.n 800866e <_printf_i+0x102> 800863a: 680e ldr r6, [r1, #0] 800863c: f010 0f40 tst.w r0, #64 ; 0x40 8008640: 602b str r3, [r5, #0] 8008642: bf18 it ne 8008644: b236 sxthne r6, r6 8008646: e7ef b.n 8008628 <_printf_i+0xbc> 8008648: 682b ldr r3, [r5, #0] 800864a: 6820 ldr r0, [r4, #0] 800864c: 1d19 adds r1, r3, #4 800864e: 6029 str r1, [r5, #0] 8008650: 0601 lsls r1, r0, #24 8008652: d501 bpl.n 8008658 <_printf_i+0xec> 8008654: 681e ldr r6, [r3, #0] 8008656: e002 b.n 800865e <_printf_i+0xf2> 8008658: 0646 lsls r6, r0, #25 800865a: d5fb bpl.n 8008654 <_printf_i+0xe8> 800865c: 881e ldrh r6, [r3, #0] 800865e: 2f6f cmp r7, #111 ; 0x6f 8008660: bf0c ite eq 8008662: 2308 moveq r3, #8 8008664: 230a movne r3, #10 8008666: 4852 ldr r0, [pc, #328] ; (80087b0 <_printf_i+0x244>) 8008668: 2100 movs r1, #0 800866a: f884 1043 strb.w r1, [r4, #67] ; 0x43 800866e: 6865 ldr r5, [r4, #4] 8008670: 2d00 cmp r5, #0 8008672: bfa8 it ge 8008674: 6821 ldrge r1, [r4, #0] 8008676: 60a5 str r5, [r4, #8] 8008678: bfa4 itt ge 800867a: f021 0104 bicge.w r1, r1, #4 800867e: 6021 strge r1, [r4, #0] 8008680: b90e cbnz r6, 8008686 <_printf_i+0x11a> 8008682: 2d00 cmp r5, #0 8008684: d04d beq.n 8008722 <_printf_i+0x1b6> 8008686: 4615 mov r5, r2 8008688: fbb6 f1f3 udiv r1, r6, r3 800868c: fb03 6711 mls r7, r3, r1, r6 8008690: 5dc7 ldrb r7, [r0, r7] 8008692: f805 7d01 strb.w r7, [r5, #-1]! 8008696: 4637 mov r7, r6 8008698: 42bb cmp r3, r7 800869a: 460e mov r6, r1 800869c: d9f4 bls.n 8008688 <_printf_i+0x11c> 800869e: 2b08 cmp r3, #8 80086a0: d10b bne.n 80086ba <_printf_i+0x14e> 80086a2: 6823 ldr r3, [r4, #0] 80086a4: 07de lsls r6, r3, #31 80086a6: d508 bpl.n 80086ba <_printf_i+0x14e> 80086a8: 6923 ldr r3, [r4, #16] 80086aa: 6861 ldr r1, [r4, #4] 80086ac: 4299 cmp r1, r3 80086ae: bfde ittt le 80086b0: 2330 movle r3, #48 ; 0x30 80086b2: f805 3c01 strble.w r3, [r5, #-1] 80086b6: f105 35ff addle.w r5, r5, #4294967295 ; 0xffffffff 80086ba: 1b52 subs r2, r2, r5 80086bc: 6122 str r2, [r4, #16] 80086be: 464b mov r3, r9 80086c0: 4621 mov r1, r4 80086c2: 4640 mov r0, r8 80086c4: f8cd a000 str.w sl, [sp] 80086c8: aa03 add r2, sp, #12 80086ca: f7ff fedf bl 800848c <_printf_common> 80086ce: 3001 adds r0, #1 80086d0: d14c bne.n 800876c <_printf_i+0x200> 80086d2: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 80086d6: b004 add sp, #16 80086d8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80086dc: 4834 ldr r0, [pc, #208] ; (80087b0 <_printf_i+0x244>) 80086de: f881 7045 strb.w r7, [r1, #69] ; 0x45 80086e2: 6829 ldr r1, [r5, #0] 80086e4: 6823 ldr r3, [r4, #0] 80086e6: f851 6b04 ldr.w r6, [r1], #4 80086ea: 6029 str r1, [r5, #0] 80086ec: 061d lsls r5, r3, #24 80086ee: d514 bpl.n 800871a <_printf_i+0x1ae> 80086f0: 07df lsls r7, r3, #31 80086f2: bf44 itt mi 80086f4: f043 0320 orrmi.w r3, r3, #32 80086f8: 6023 strmi r3, [r4, #0] 80086fa: b91e cbnz r6, 8008704 <_printf_i+0x198> 80086fc: 6823 ldr r3, [r4, #0] 80086fe: f023 0320 bic.w r3, r3, #32 8008702: 6023 str r3, [r4, #0] 8008704: 2310 movs r3, #16 8008706: e7af b.n 8008668 <_printf_i+0xfc> 8008708: 6823 ldr r3, [r4, #0] 800870a: f043 0320 orr.w r3, r3, #32 800870e: 6023 str r3, [r4, #0] 8008710: 2378 movs r3, #120 ; 0x78 8008712: 4828 ldr r0, [pc, #160] ; (80087b4 <_printf_i+0x248>) 8008714: f884 3045 strb.w r3, [r4, #69] ; 0x45 8008718: e7e3 b.n 80086e2 <_printf_i+0x176> 800871a: 0659 lsls r1, r3, #25 800871c: bf48 it mi 800871e: b2b6 uxthmi r6, r6 8008720: e7e6 b.n 80086f0 <_printf_i+0x184> 8008722: 4615 mov r5, r2 8008724: e7bb b.n 800869e <_printf_i+0x132> 8008726: 682b ldr r3, [r5, #0] 8008728: 6826 ldr r6, [r4, #0] 800872a: 1d18 adds r0, r3, #4 800872c: 6961 ldr r1, [r4, #20] 800872e: 6028 str r0, [r5, #0] 8008730: 0635 lsls r5, r6, #24 8008732: 681b ldr r3, [r3, #0] 8008734: d501 bpl.n 800873a <_printf_i+0x1ce> 8008736: 6019 str r1, [r3, #0] 8008738: e002 b.n 8008740 <_printf_i+0x1d4> 800873a: 0670 lsls r0, r6, #25 800873c: d5fb bpl.n 8008736 <_printf_i+0x1ca> 800873e: 8019 strh r1, [r3, #0] 8008740: 2300 movs r3, #0 8008742: 4615 mov r5, r2 8008744: 6123 str r3, [r4, #16] 8008746: e7ba b.n 80086be <_printf_i+0x152> 8008748: 682b ldr r3, [r5, #0] 800874a: 2100 movs r1, #0 800874c: 1d1a adds r2, r3, #4 800874e: 602a str r2, [r5, #0] 8008750: 681d ldr r5, [r3, #0] 8008752: 6862 ldr r2, [r4, #4] 8008754: 4628 mov r0, r5 8008756: f000 f8d1 bl 80088fc 800875a: b108 cbz r0, 8008760 <_printf_i+0x1f4> 800875c: 1b40 subs r0, r0, r5 800875e: 6060 str r0, [r4, #4] 8008760: 6863 ldr r3, [r4, #4] 8008762: 6123 str r3, [r4, #16] 8008764: 2300 movs r3, #0 8008766: f884 3043 strb.w r3, [r4, #67] ; 0x43 800876a: e7a8 b.n 80086be <_printf_i+0x152> 800876c: 462a mov r2, r5 800876e: 4649 mov r1, r9 8008770: 4640 mov r0, r8 8008772: 6923 ldr r3, [r4, #16] 8008774: 47d0 blx sl 8008776: 3001 adds r0, #1 8008778: d0ab beq.n 80086d2 <_printf_i+0x166> 800877a: 6823 ldr r3, [r4, #0] 800877c: 079b lsls r3, r3, #30 800877e: d413 bmi.n 80087a8 <_printf_i+0x23c> 8008780: 68e0 ldr r0, [r4, #12] 8008782: 9b03 ldr r3, [sp, #12] 8008784: 4298 cmp r0, r3 8008786: bfb8 it lt 8008788: 4618 movlt r0, r3 800878a: e7a4 b.n 80086d6 <_printf_i+0x16a> 800878c: 2301 movs r3, #1 800878e: 4632 mov r2, r6 8008790: 4649 mov r1, r9 8008792: 4640 mov r0, r8 8008794: 47d0 blx sl 8008796: 3001 adds r0, #1 8008798: d09b beq.n 80086d2 <_printf_i+0x166> 800879a: 3501 adds r5, #1 800879c: 68e3 ldr r3, [r4, #12] 800879e: 9903 ldr r1, [sp, #12] 80087a0: 1a5b subs r3, r3, r1 80087a2: 42ab cmp r3, r5 80087a4: dcf2 bgt.n 800878c <_printf_i+0x220> 80087a6: e7eb b.n 8008780 <_printf_i+0x214> 80087a8: 2500 movs r5, #0 80087aa: f104 0619 add.w r6, r4, #25 80087ae: e7f5 b.n 800879c <_printf_i+0x230> 80087b0: 08008f41 .word 0x08008f41 80087b4: 08008f52 .word 0x08008f52 080087b8 <__sread>: 80087b8: b510 push {r4, lr} 80087ba: 460c mov r4, r1 80087bc: f9b1 100e ldrsh.w r1, [r1, #14] 80087c0: f000 f8aa bl 8008918 <_read_r> 80087c4: 2800 cmp r0, #0 80087c6: bfab itete ge 80087c8: 6d63 ldrge r3, [r4, #84] ; 0x54 80087ca: 89a3 ldrhlt r3, [r4, #12] 80087cc: 181b addge r3, r3, r0 80087ce: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 80087d2: bfac ite ge 80087d4: 6563 strge r3, [r4, #84] ; 0x54 80087d6: 81a3 strhlt r3, [r4, #12] 80087d8: bd10 pop {r4, pc} 080087da <__swrite>: 80087da: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80087de: 461f mov r7, r3 80087e0: 898b ldrh r3, [r1, #12] 80087e2: 4605 mov r5, r0 80087e4: 05db lsls r3, r3, #23 80087e6: 460c mov r4, r1 80087e8: 4616 mov r6, r2 80087ea: d505 bpl.n 80087f8 <__swrite+0x1e> 80087ec: 2302 movs r3, #2 80087ee: 2200 movs r2, #0 80087f0: f9b1 100e ldrsh.w r1, [r1, #14] 80087f4: f000 f870 bl 80088d8 <_lseek_r> 80087f8: 89a3 ldrh r3, [r4, #12] 80087fa: 4632 mov r2, r6 80087fc: f423 5380 bic.w r3, r3, #4096 ; 0x1000 8008800: 81a3 strh r3, [r4, #12] 8008802: 4628 mov r0, r5 8008804: 463b mov r3, r7 8008806: f9b4 100e ldrsh.w r1, [r4, #14] 800880a: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 800880e: f000 b817 b.w 8008840 <_write_r> 08008812 <__sseek>: 8008812: b510 push {r4, lr} 8008814: 460c mov r4, r1 8008816: f9b1 100e ldrsh.w r1, [r1, #14] 800881a: f000 f85d bl 80088d8 <_lseek_r> 800881e: 1c43 adds r3, r0, #1 8008820: 89a3 ldrh r3, [r4, #12] 8008822: bf15 itete ne 8008824: 6560 strne r0, [r4, #84] ; 0x54 8008826: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 800882a: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 800882e: 81a3 strheq r3, [r4, #12] 8008830: bf18 it ne 8008832: 81a3 strhne r3, [r4, #12] 8008834: bd10 pop {r4, pc} 08008836 <__sclose>: 8008836: f9b1 100e ldrsh.w r1, [r1, #14] 800883a: f000 b81b b.w 8008874 <_close_r> ... 08008840 <_write_r>: 8008840: b538 push {r3, r4, r5, lr} 8008842: 4604 mov r4, r0 8008844: 4608 mov r0, r1 8008846: 4611 mov r1, r2 8008848: 2200 movs r2, #0 800884a: 4d05 ldr r5, [pc, #20] ; (8008860 <_write_r+0x20>) 800884c: 602a str r2, [r5, #0] 800884e: 461a mov r2, r3 8008850: f7f9 f98a bl 8001b68 <_write> 8008854: 1c43 adds r3, r0, #1 8008856: d102 bne.n 800885e <_write_r+0x1e> 8008858: 682b ldr r3, [r5, #0] 800885a: b103 cbz r3, 800885e <_write_r+0x1e> 800885c: 6023 str r3, [r4, #0] 800885e: bd38 pop {r3, r4, r5, pc} 8008860: 20003184 .word 0x20003184 08008864 : 8008864: 2006 movs r0, #6 8008866: b508 push {r3, lr} 8008868: f000 f890 bl 800898c 800886c: 2001 movs r0, #1 800886e: f7fb f85a bl 8003926 <_exit> ... 08008874 <_close_r>: 8008874: b538 push {r3, r4, r5, lr} 8008876: 2300 movs r3, #0 8008878: 4d05 ldr r5, [pc, #20] ; (8008890 <_close_r+0x1c>) 800887a: 4604 mov r4, r0 800887c: 4608 mov r0, r1 800887e: 602b str r3, [r5, #0] 8008880: f7fb f878 bl 8003974 <_close> 8008884: 1c43 adds r3, r0, #1 8008886: d102 bne.n 800888e <_close_r+0x1a> 8008888: 682b ldr r3, [r5, #0] 800888a: b103 cbz r3, 800888e <_close_r+0x1a> 800888c: 6023 str r3, [r4, #0] 800888e: bd38 pop {r3, r4, r5, pc} 8008890: 20003184 .word 0x20003184 08008894 <_fstat_r>: 8008894: b538 push {r3, r4, r5, lr} 8008896: 2300 movs r3, #0 8008898: 4d06 ldr r5, [pc, #24] ; (80088b4 <_fstat_r+0x20>) 800889a: 4604 mov r4, r0 800889c: 4608 mov r0, r1 800889e: 4611 mov r1, r2 80088a0: 602b str r3, [r5, #0] 80088a2: f7fb f872 bl 800398a <_fstat> 80088a6: 1c43 adds r3, r0, #1 80088a8: d102 bne.n 80088b0 <_fstat_r+0x1c> 80088aa: 682b ldr r3, [r5, #0] 80088ac: b103 cbz r3, 80088b0 <_fstat_r+0x1c> 80088ae: 6023 str r3, [r4, #0] 80088b0: bd38 pop {r3, r4, r5, pc} 80088b2: bf00 nop 80088b4: 20003184 .word 0x20003184 080088b8 <_isatty_r>: 80088b8: b538 push {r3, r4, r5, lr} 80088ba: 2300 movs r3, #0 80088bc: 4d05 ldr r5, [pc, #20] ; (80088d4 <_isatty_r+0x1c>) 80088be: 4604 mov r4, r0 80088c0: 4608 mov r0, r1 80088c2: 602b str r3, [r5, #0] 80088c4: f7fb f870 bl 80039a8 <_isatty> 80088c8: 1c43 adds r3, r0, #1 80088ca: d102 bne.n 80088d2 <_isatty_r+0x1a> 80088cc: 682b ldr r3, [r5, #0] 80088ce: b103 cbz r3, 80088d2 <_isatty_r+0x1a> 80088d0: 6023 str r3, [r4, #0] 80088d2: bd38 pop {r3, r4, r5, pc} 80088d4: 20003184 .word 0x20003184 080088d8 <_lseek_r>: 80088d8: b538 push {r3, r4, r5, lr} 80088da: 4604 mov r4, r0 80088dc: 4608 mov r0, r1 80088de: 4611 mov r1, r2 80088e0: 2200 movs r2, #0 80088e2: 4d05 ldr r5, [pc, #20] ; (80088f8 <_lseek_r+0x20>) 80088e4: 602a str r2, [r5, #0] 80088e6: 461a mov r2, r3 80088e8: f7fb f868 bl 80039bc <_lseek> 80088ec: 1c43 adds r3, r0, #1 80088ee: d102 bne.n 80088f6 <_lseek_r+0x1e> 80088f0: 682b ldr r3, [r5, #0] 80088f2: b103 cbz r3, 80088f6 <_lseek_r+0x1e> 80088f4: 6023 str r3, [r4, #0] 80088f6: bd38 pop {r3, r4, r5, pc} 80088f8: 20003184 .word 0x20003184 080088fc : 80088fc: 4603 mov r3, r0 80088fe: b510 push {r4, lr} 8008900: b2c9 uxtb r1, r1 8008902: 4402 add r2, r0 8008904: 4293 cmp r3, r2 8008906: 4618 mov r0, r3 8008908: d101 bne.n 800890e 800890a: 2000 movs r0, #0 800890c: e003 b.n 8008916 800890e: 7804 ldrb r4, [r0, #0] 8008910: 3301 adds r3, #1 8008912: 428c cmp r4, r1 8008914: d1f6 bne.n 8008904 8008916: bd10 pop {r4, pc} 08008918 <_read_r>: 8008918: b538 push {r3, r4, r5, lr} 800891a: 4604 mov r4, r0 800891c: 4608 mov r0, r1 800891e: 4611 mov r1, r2 8008920: 2200 movs r2, #0 8008922: 4d05 ldr r5, [pc, #20] ; (8008938 <_read_r+0x20>) 8008924: 602a str r2, [r5, #0] 8008926: 461a mov r2, r3 8008928: f7fb f807 bl 800393a <_read> 800892c: 1c43 adds r3, r0, #1 800892e: d102 bne.n 8008936 <_read_r+0x1e> 8008930: 682b ldr r3, [r5, #0] 8008932: b103 cbz r3, 8008936 <_read_r+0x1e> 8008934: 6023 str r3, [r4, #0] 8008936: bd38 pop {r3, r4, r5, pc} 8008938: 20003184 .word 0x20003184 0800893c <_raise_r>: 800893c: 291f cmp r1, #31 800893e: b538 push {r3, r4, r5, lr} 8008940: 4604 mov r4, r0 8008942: 460d mov r5, r1 8008944: d904 bls.n 8008950 <_raise_r+0x14> 8008946: 2316 movs r3, #22 8008948: 6003 str r3, [r0, #0] 800894a: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800894e: bd38 pop {r3, r4, r5, pc} 8008950: 6c42 ldr r2, [r0, #68] ; 0x44 8008952: b112 cbz r2, 800895a <_raise_r+0x1e> 8008954: f852 3021 ldr.w r3, [r2, r1, lsl #2] 8008958: b94b cbnz r3, 800896e <_raise_r+0x32> 800895a: 4620 mov r0, r4 800895c: f000 f830 bl 80089c0 <_getpid_r> 8008960: 462a mov r2, r5 8008962: 4601 mov r1, r0 8008964: 4620 mov r0, r4 8008966: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 800896a: f000 b817 b.w 800899c <_kill_r> 800896e: 2b01 cmp r3, #1 8008970: d00a beq.n 8008988 <_raise_r+0x4c> 8008972: 1c59 adds r1, r3, #1 8008974: d103 bne.n 800897e <_raise_r+0x42> 8008976: 2316 movs r3, #22 8008978: 6003 str r3, [r0, #0] 800897a: 2001 movs r0, #1 800897c: e7e7 b.n 800894e <_raise_r+0x12> 800897e: 2400 movs r4, #0 8008980: 4628 mov r0, r5 8008982: f842 4025 str.w r4, [r2, r5, lsl #2] 8008986: 4798 blx r3 8008988: 2000 movs r0, #0 800898a: e7e0 b.n 800894e <_raise_r+0x12> 0800898c : 800898c: 4b02 ldr r3, [pc, #8] ; (8008998 ) 800898e: 4601 mov r1, r0 8008990: 6818 ldr r0, [r3, #0] 8008992: f7ff bfd3 b.w 800893c <_raise_r> 8008996: bf00 nop 8008998: 2000000c .word 0x2000000c 0800899c <_kill_r>: 800899c: b538 push {r3, r4, r5, lr} 800899e: 2300 movs r3, #0 80089a0: 4d06 ldr r5, [pc, #24] ; (80089bc <_kill_r+0x20>) 80089a2: 4604 mov r4, r0 80089a4: 4608 mov r0, r1 80089a6: 4611 mov r1, r2 80089a8: 602b str r3, [r5, #0] 80089aa: f7fa ffac bl 8003906 <_kill> 80089ae: 1c43 adds r3, r0, #1 80089b0: d102 bne.n 80089b8 <_kill_r+0x1c> 80089b2: 682b ldr r3, [r5, #0] 80089b4: b103 cbz r3, 80089b8 <_kill_r+0x1c> 80089b6: 6023 str r3, [r4, #0] 80089b8: bd38 pop {r3, r4, r5, pc} 80089ba: bf00 nop 80089bc: 20003184 .word 0x20003184 080089c0 <_getpid_r>: 80089c0: f7fa bf9a b.w 80038f8 <_getpid> 080089c4 <_init>: 80089c4: b5f8 push {r3, r4, r5, r6, r7, lr} 80089c6: bf00 nop 80089c8: bcf8 pop {r3, r4, r5, r6, r7} 80089ca: bc08 pop {r3} 80089cc: 469e mov lr, r3 80089ce: 4770 bx lr 080089d0 <_fini>: 80089d0: b5f8 push {r3, r4, r5, r6, r7, lr} 80089d2: bf00 nop 80089d4: bcf8 pop {r3, r4, r5, r6, r7} 80089d6: bc08 pop {r3} 80089d8: 469e mov lr, r3 80089da: 4770 bx lr